CSE493/593
MOS & Wire Capacitances
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.
and M. J. Irwin & Vijay Narayanan, PSU]
Review: Delay Definitions
Vin
Vout
Vin
input
waveform
Propagation delay
50%
tp = (tpHL + tpLH)/2
t
tpLH
tpHL
Vout
90%
output
waveform
signal slopes
50%
10%
tf
tr
t
CMOS Inverter: Dynamic
 Transient, or dynamic, response determines the
maximum speed at which a device can be operated.
VDD
First focus
Vout = 0
CL
Rn
Vin = V DD
tpHL = f(Rn, CL)
Next focus
Sources of Capacitance
Vout
Vin
CL
M2
Vin
Vout2
CGD12
M1
CG4
CDB2
M4
Vout
CDB1
Vout2
Cw
CG3
M3
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance
MOS Intrinsic Capacitances
 Structure capacitances
 Channel capacitances
 Depletion regions of the reverse-
biased pn-junctions of the drain and
source
MOS Structure Capacitances
lateral diffusion
Top view
Source
n+
Poly Gate
xd
xd
Drain
W n+
Ldrawn
n+
Leff
tox
n+
Overlap capacitance (linear)
CGSO = CGDO = Cox xd W = Co W
MOS Channel Capacitances
 The gate-to-channel capacitance depends upon
the operating region and the terminal voltages
CGS = CGCS + CGSO
S
VGS
CGD = CGCD + CGDO
G
+
D
-
n+
n channel
n+
CGB = CGCB
p substrate
B
depletion
region
Review: Summary of MOS Operating Regions
 Cutoff (really subthreshold) VGS ≤ VT
 Exponential in VGS with linear VDS dependence
ID = IS e (qVGS/nkT) (1 - e -(qVDS/kT) ) (1 - λ VDS) where n ≥ 1
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT = VGS - VT
ID = k’ W/L [(VGS – VT)VDS – VDS2/2] (1+λVDS) κ(VDS)
 Saturated (Constant Current) VDS ≥ VDSAT = VGS - VT
IDSat = k’ W/L [(VGS – VT)VDSAT – VDSAT2/2] (1+λVDS) κ(VDSAT)
NMOS
VT0(V)
0.43
γ(V0.5)
0.4
VDSAT(V)
0.63
k’(A/V2)
115 x 10-6
λ(V-1)
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
Average Distribution of Channel Capacitance
Operation
Region
CGCB
CGCS
CGCD
CGC
CG
Cutoff
CoxWL
0
0
CoxWL
CoxWL +
2CoW
Resistive
0
CoxWL/2
CoxWL/2
CoxWL
CoxWL +
2CoW
Saturation
0
(2/3)CoxWL
0

(2/3)CoxWL (2/3)CoxWL +
2CoW
Channel capacitance components are nonlinear and
vary with operating voltage
 Most important regions are cutoff and saturation
since that is where the device spends most of its time
MOS Diffusion Capacitances
 The junction (or diffusion) capacitance is from the
reverse-biased source-body and drain-body pn-junctions.
S
VGS
G
+
D
-
n+
n channel
n+
p substrate
CSB = CSdiff
depletion
region
CDB = CDdiff
B
MOS Capacitance Model
CGS = CGCS + CGSO
G
CGD = CGCD + CGDO
CGS
CGD
S
D
CSB
CSB = CSdiff
CGB
B
CGB = CGCB
CDB
CDB = CDdiff
Transistor Capacitance Values for 0.25µ
Example: For an NMOS with L = 0.24 µm, W = 0.36 µm,
LD = LS = 0.625 µm
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
CGC = Cox WL = 0.52 fF
so Cgate_cap = CoxWL + 2CoW = 0.74 fF
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF
so Cdiffusion_cap = 0.90 fF
NMOS
PMOS
Cox
Co
Cj
(fF/µm2)
(fF/µm)
(fF/µm2)
6
6
0.31
0.27
2
1.9
mj
φb
Cjsw
(V)
(fF/µm)
0.5 0.9
0.48 0.9
0.28
0.22
mjsw
φbsw
(V)
0.44
0.32
0.9
0.9
Review: Sources of Capacitance
Vout
Vin
CL
CG4
M2
Vin
Vout2
CGD12pdrain
M4
CDB2
ndrain
M1
CDB1
Vout
Vout2
Cw
CG3
M3
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance
Layout of Two Chained Inverters
VDD
PMOS
1.125/0.25
1.2µm
=2λ
Out
In
Metal1
Polysilicon
0.125
0.5
NMOS
0.375/0.25
W/L
AD (µm2)
NMOS 0.375/0.25
0.3
PMOS 1.125/0.25
0.7
GND
PD (µm)
1.875
2.375
AS (µm2) PS (µm)
0.3
1.875
0.7
2.375
Components of CL (0.25 µm)
C Term
CGD1
Expression
2 Con Wn
Value (fF) Value (fF)
H→L
L→H
0.23
0.23
CGD2
2 Cop Wp
0.61
0.61
CDB1
KeqbpnADnCj + KeqswnPDnCjsw
0.66
0.90
CDB2
KeqbppADpCj + KeqswpPDpCjsw
1.5
1.15
CG3
(2 Con)Wn + CoxWnLn
0.76
0.76
CG4
(2 Cop)Wp + CoxWpLp
2.28
2.28
Cw
from extraction
0.12
0.12
CL
∑
6.1
6.0
Wiring Capacitance
 The wiring capacitance depends upon the length and
width of the connecting wires and is a function of the
fan-out from the driving gate and the number of fan-out
gates.
 Wiring capacitance is growing in importance with the
scaling of technology.
Parallel Plate Wiring Capacitance
current flow
L
electrical field lines
W
H
tdi
dielectric (SiO2)
substrate
permittivity
constant
(SiO2= 3.9)
Cpp = (εdi/tdi) WL
Permittivity Values of Some Dielectrics
Material
Free space
Teflon AF
Aromatic thermosets (SiLK)
Polyimides (organic)
Fluorosilicate glass (FSG)
Silicon dioxide
Glass epoxy (PCBs)
Silicon nitride
Alumina (package)
Silicon
εdi
1
2.1
2.6 – 2.8
3.1 – 3.4
3.2 – 4.0
3.9 – 4.5
5
7.5
9.5
11.7
Sources of Interwire Capacitance
Cwire = Cpp + Cfringe + Cinterwire
= (εdi/tdi)WL
+ (2πεdi)/log(tdi/H)
+ (εdi/tdi)HL
fringe
interwire
pp
Impact of Interwire Capacitance
(from [Bakoglu89])
Insights
 For W/H < 1.5, the fringe component dominates the
parallel-plate component. Fringing capacitance can
increase the overall capacitance by a factor of 10 or more.
 When W < 1.75H interwire capacitance starts to dominate
 Interwire capacitance is more pronounced for wires in the
higher interconnect layers (further from the substrate)
 Rules of thumb




Never run wires in diffusion
Use poly only for short runs
Shorter wires – lower R and C
Thinner wires – lower C but higher R
 Wire delay nearly proportional to L2
Wiring Capacitances
Poly
Al1
Al2
Al3
Al4
Al5
Field
88
54
30
40
13
25
8.9
18
6.5
14
5.2
12
Interwire Cap
Active
41
47
15
27
9.4
19
6.8
15
5.4
12
Poly
57
54
17
29
10
20
7
15
5.4
12
Al1
Al2
Al3
Al4
pp in aF/µm2
fringe in aF/µm
36
45
15
27
8.9
18
6.6
14
41
49
15
27
9.1
19
35
45
14
27
38
52
Poly
Al1
Al2
Al3
Al4
Al5
40
95
85
85
85
115
per unit wire length in aF/µm for minimally-spaced wires
Dealing with Capacitance
 Low capacitance (low-k) dielectrics (insulators) such
as polymide or even air instead of SiO2
 family of materials that are low-k dielectrics
 must also be suitable thermally and mechanically and
 compatible with (copper) interconnect
 Copper interconnect allows wires to be thinner without
increasing their resistance, thereby decreasing
interwire capacitance
 SOI (silicon on insulator) to reduce junction
capacitance
Resistance
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
Sources of Resistance
Top view
Poly Gate
Drain n+
Source n+
W
L
 MOS structure resistance - Ron
 Source and drain resistance
 Contact (via) resistance
 Wiring resistance
MOS Structure Resistance
 The simplest model assumes the transistor is a switch
with an infinite “off” resistance and a finite “on” resistance
Ron
VGS ≥ VT
S
Ron
D
 However Ron is nonlinear, so use instead the average
value of the resistances, Req, at the end-points of the
transition (VDD and VDD/2)
Req = ½ (Ron(t1) + Ron(t2))
Req = ¾ VDD/IDSAT (1 – 5/6 λ VDD)
Equivalent MOS Structure Resistance
 The on resistance is
inversely proportional to
W/L. Doubling W halves
Req
 For VDD>>VT+VDSAT/2,
Req is independent of VDD
(see plot). Only a minor
improvement in Req occurs
when VDD is increased
(due to channel length
modulation)
 Once the supply voltage
approaches VT, Req
increases dramatically
7
x105
(for VGS = VDD,
VDS = VDD→VDD/2)
6
5
4
3
2
1
0
0.5
VDD(V)
NMOS(kΩ)
PMOS (kΩ)
1
1
35
115
1.5
2
1.5
19
55
2
15
38
VDD (V)
2.5
2.5
13
31
Req (for W/L = 1), for larger devices divide Req by W/L
Source and Drain Resistance
G
D
S
RS
RD
RS,D = (LS,D/W)R
where LS,D is the length of the source or drain diffusion
R is the sheet resistance of the source or drain
diffusion (20 to 100 Ω/)
 More pronounced with scaling since junctions are
shallower
 With silicidation R is reduced to the range 1 to 4 Ω/
Contact Resistance
 Transitions between routing layers (contacts through
via’s) add extra resistance to a wire
 keep signals wires on a single layer whenever possible
 avoid excess contacts
 reduce contact resistance by making vias larger (beware of
current crowding that puts a practical limit on the size of vias)
or by using multiple minimum-size vias to make the contact
 Typical contact resistances, RC, (minimum-size)
 5 to 20 Ω for metal or poly to n+, p+ diffusion and metal to poly
 1 to 5 Ω for metal to metal contacts
 More pronounced with scaling since contact openings
are smaller
Wire Resistance
L
H
ρL
R=
A
Sheet Resistance R
R1
=
=
ρ L
HW
R2
=
W
Material
Silver (Ag)
Copper (Cu)
Gold (Au)
Aluminum (Al)
Tungsten (W)
ρ(Ω-m)
1.6 x 10-8
1.7 x 10-8
2.2 x 10-8
2.7 x 10-8
5.5 x 10-8
Material
n, p well diffusion
n+, p+ diffusion
n+, p+ diffusion
with silicide
polysilicon
polysilicon with
silicide
Aluminum
Sheet Res. (Ω/)
1000 to 1500
50 to 150
3 to 5
150 to 200
4 to 5
0.05 to 0.1
Skin Effect
 At high frequency, currents tend to flow primarily on the
surface of a conductor with the current density falling off
exponentially with depth into the wire
W
H
δ= √(ρ/(πfµ))
where f is frequency
µ = 4π x 10-7 H/m
δ= 2.6 µm
for Al at 1 GHz
so the overall cross section is ~ 2(W+H)δ
 The onset of skin effect is at fs - where the skin depth is
equal to half the largest dimension of the wire.
fs = 4 ρ / (π µ (max(W,H))2)
 An issue for high frequency, wide (tall) wires (i.e., clocks!)
Skin Effect for Different W’s
for H = .70 um
% Increase in Resistance
1000
100
10
1
0.1
W = 1 um
W = 10 um
W = 20 um
1E8
1E9
1E10
Frequency (Hz)
 A 30% increase in resistance is observe for 20 µm Al wires
at 1 GHz (versus only a 1% increase for 1 µm wires)
The Wire
transmitters
schematic
receivers
physical
Wire Models
 Interconnect parasitics (capacitance, resistance, and
inductance)
l
reduce reliability
l
affect performance and power consumption
All-inclusive (C,R,l) model
Capacitance-only
Parasitic Simplifications
 Inductive effects can be ignored
l
l
if the resistance of the wire is substantial enough (as is the case
for long Al wires with small cross section)
if the rise and fall times of the applied signals are slow enough
 When the wire is short, or the cross-section is large, or
the interconnect material has low resistivity, a
capacitance only model can be used
 When the separation between neighboring wires is large,
or when the wires run together for only a short distance,
interwire capacitance can be ignored and all the parasitic
capacitance can be modeled as capacitance to ground
Simulated Wire Delays
Vin
L/10
L/4
L
Vout
L/2
L
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
time (nsec)
3.5
4
4.5
5
Wire Delay Models
 Ideal wire
l
l
same voltage is present at every segment of the wire at every point in
time - at equi-potential
only holds for very short wires, i.e., interconnects between very nearest
neighbor gates
 Lumped C model
l
when only a single parasitic component (C, R, or L) is dominant the
different fractions are lumped into a single circuit element
Driver
- When the resistive component is small and the switching frequency is low to
medium, can consider only C; the wire itself does not introduce any delay;
the only impact on performance comes from wire capacitance
Vout
RDriver
cwire
capacitance per unit length
l
good for short wires; pessimistic and inaccurate for long wires
Vout
Clumped
Wire Delay Models, con’t
 Lumped RC model
total wire resistance is lumped into a single R and total capacitance into
a single C
good for short wires; pessimistic and inaccurate for long wires
l
l
 Distributed RC model
circuit parasitics are distributed along the length, L, of the wire
l
- c and r are the capacitance and resistance per unit length
Vin
r∆L
r∆L
r∆L
r∆L
r∆L
c∆L
c∆L
c∆L
c∆L
c∆L
l
VN
Delay is determined using the Elmore delay equation
N
τDi = ∑ ckrik
k=1
Vin
(r,c,L)
VN
Elmore Delay Models Uses
 Modeling the delay of a wire
 Modeling the delay of a series of pass
transistors
 Modeling the delay of a pull-up and pull-down
networks
Distributed RC Model for Simple Wires
 A length L RC wire can be modeled by N segments of
length L/N
l
The resistance and capacitance of each segment are given by
r L/N and c L/N
τDN = (L/N)2(cr+2cr+…+Ncr) = (crL2) (N(N+1))/(2N2) = CR((N+1)/(2N))
where R (= rL) and C (= cL) are the total lumped resistance and
capacitance of the wire
 For large N
τDN = RC/2 = rcL2/2

Delay of a wire is a quadratic function of its length, L

The delay is 1/2 of that predicted (by the lumped model)
Step Response Points
Voltage Range
Lumped RC
Distributed RC
0 → 50% (tp)
0.69 RC
0.38 RC
0 → 63% (τ)
RC
0.5 RC
10% → 90% (tr)
2.2 RC
0.9 RC
0 → 90%
2.3 RC
1.0 RC

Time to reach the 50%
point is t = ln(2)τ = 0.69τ
Time to reach the 90%
point is t = ln(9)τ = 2.2τ
Example: Consider a Al1 wire 10 cm long and 1 µm wide
l
l
Using a lumped C only model with a source resistance (RDriver) of 10 kΩ and
a total lumped capacitance (Clumped) of 11 pF
t50% = 0.69 x 10 kΩ x 11pF = 76 ns
t90% = 2.2 x 10 kΩ x 11pF = 242 ns
Using a distributed RC model with c = 110 aF/µm and r = 0.075 Ω/µm
t50% = 0.38 x (0.075 Ω/µm) x (110 aF/µm) x (105 µm)2 = 31.4 ns
t90% = 0.9 x (0.075 Ω/µm) x (110 aF/µm) x (105 µm)2 = 74.25 ns
Poly: t50% = 0.38 x (150 Ω/µm) x (88+2×54 aF/µm) x (105 µm)2 = 112 µs
Al5: t50% = 0.38 x (0.0375 Ω/µm) x (5.2+2×12 aF/µm) x (105 µm)2 = 4.2 ns
Putting It All Together
RDriver
rw,cw,L
Vout
Vin
 Total propagation delay consider driver and wire
τD = RDriverCw + (RwCw)/2 = RDriverCw + 0.5rwcwL2
and tp = 0.69 RDriverCw + 0.38 RwCw
where Rw = rwL and Cw = cwL
 The delay introduced by wire resistance becomes
dominant when (RwCw)/2 ≥ RDriver CW (when
L ≥ 2RDriver/Rw)
l
For an RDriver = 1 kΩ driving an 1 µm wide Al1 wire, Lcrit is 2.67 cm
Design Rules of Thumb
 rc delays should be considered when tpRC > tpgate of the
driving gate
Lcrit > √ (tpgate/0.38rc)
l
actual Lcrit depends upon the size of the driving gate and the interconnect
material
 rc delays should be considered when the rise (fall) time at
the line input is smaller than RC, the rise (fall) time of the
line
trise < RC
l
when not met, the change in the signal is slower than the propagation
delay of the wire so a lumped C model suffices
Nature of Interconnect
Pentium Pro (R)
Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
No of nets
(Log Scale)
Local Interconnect
Global Interconnect
10
100
1,000
Length (u)
10,000
100,000
Source: Intel
Overcoming Interconnect Resistance
 Selective technology scaling
scale W while holding H constant
l
 Use better interconnect materials
lower resistivity materials like copper
l
- As processes shrink, wires get shorter (reducing C) but they get
closer together (increasing C) and narrower (increasing R). So RC
wire delay increases and capacitive coupling gets worse.
- Copper has about 40% lower resistivity than aluminum, so copper
wires can be thinner (reducing C) without increasing R
use silicides (WSi2, TiSi2, PtSi2 and TaSi)
l
silicide
- Conductivity is 8-10 times better than
poly alone
polysilicon
SiO2
n+
 Use more interconnect layers
l
p
n+
reduces the average wire length L (but beware of extra contacts)
Wire Spacing Comparisons
Intel P858
Al, 0.18µm
Intel P856.5
Al, 0.25µm
Ω - 0.05
M4
Ω - 0.33
M3
Ω - 0.33
M2
Scale: 2,160 nm
Ω - 0.07
M6
Ω - 0.08
M5
M5
Ω - 0.12
Ω - 1.11
IBM CMOS-8S
CU, 0.18µm
M1
Ω - 0.17
M4
Ω - 0.49
M3
Ω - 0.49
M2
Ω - 1.00
M1
Ω - 0.10
M7
Ω - 0.10
M6
Ω - 0.50
M5
Ω - 0.50
M4
Ω - 0.50
M3
Ω - 0.70
M2
Ω - 0.97
M1
From MPR, 2000
Comparison of Wire Delays
1
Normalized Wire Delay
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Al/SiO2
Cu/SiO2
Cu/FSG
Cu/SiLK
From MPR, 2000
Inductance
 When the rise and fall times of the signal become
comparable to the time of flight of the signal waveform
across the line, then the inductance of the wire starts to
dominate the delay behavior
Vin
l
r
g
l
r
c
g
l
r
c
g
l
r
c
g
c
Vout
 Must consider wire transmission line effects
l
Signal propagates over the wire as a wave (rather than diffusing
as in rc only models)
- Signal propagates by alternately transferring energy from capacitive
to inductive modes
More Design Rules of Thumb
 Transmission line effects should be considered when the
rise or fall time of the input signal (tr, tf) is smaller than
the time-of-flight of the transmission line (tflight)
tr (tf) < 2.5 tflight = 2.5 L/v
l
For on-chip wires with a maximum length of 1 cm, we only worry
about transmission line effects when tr < 150 ps
 Transmission line effects should only be considered
when the total resistance of the wire is limited
R < 5 Z0 = 5 (V/I)