COMPUTER ARCHITECT
Assignment
1 a) With the aid of circuit diagrams , describe each of the following semiconductor memory
cell:
i)
ii)
SRAM;
DRAM.
b) Draw a timing waveforms for each of the following:
i) SRAM memory read cycle;
ii) DRAM memory write cycle.
c) Differentiate between partial- and full- memory decoding , stating the merit of each.
d) A 256K x8 memory is constructed from 32Kx 4 RAM IC devices.
i) Determine the number of RAM chips required;
ii) Determine the size of the decoder required;
iii)
Draw a Schematic-block diagram for the memory implementation.
2 a) Describe each of the following I/O techniques:
i)
ii)
iii)
Programmed;
Interrupt;
Block or DMA.
b) State the main characteristics of each of the following computers, stating the Merits and
Demerits of each:
i) CISC;
ii) RISC.
3. a) With the aid of a block- schematic diagram show how the 8086 CPU can be interfaced to
Four 32KX 8 SRAM memories whose address ranges from C0000H. Use decoders , buffers
and gates to accomplish your design
b) Design a block Schematic diagram for an I/O port interface, using a Decoder, for the
following 8-bit I/O ports: 10H, 12H, 14H, 16H, and 18H, 1AH, 1CH and 1EH.
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4) Two computer systems are defined as follows:
System 1: An 8086, Two banks of 16KX8 ROM, Two banks of 16KX8 RAM, Octal Keypad, 8LED Display. The ROM address stars from F0000h while RAM Start address is 00000H. The I/O’s
occupy the uppermost address of the computer.
System 2: An 8086, one 8087, Two banks of 32KX8 ROM, Two banks of 26KX8 RAM,
Hexadecimal Keypad, Four(4) LCD Display. The ROM address stars from F0000h while RAM Start
address is 80000H. The I/O’s occupy the uppermost address of the computer.
a) Draw the memory Map of each system,
b) Draw detailed Block Schematic-block diagram of each system. Include Decoders, Clock generators,
Buffers , Transceivers etc. Also indicate the status of crucial signals required to configure the system
appropriately.
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