Discovery™ AMS:
Mixed-Signal Simulation
User Guide
Version C-2009.06, June 2009
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Printed in the U.S.A.
Discovery™ AMS:
ii
Mixed-Signal Simulation User Guide, C-2009.06
Discovery™ AMS:
Mixed-Signal Simulation User Guide
C-2009.06
Contents
Part I:
1.
Part II:
2.
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xii
Introduction to Mixed-Signal Simulations
Getting Started with Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . . .
3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Three Mixed-Signal Simulation Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
Verilog-SPICE Flow (Flow #1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
VHDL/Verilog-SPICE (Flow #2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Verilog-AMS-SPICE (Flow #3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Preparing for a Mixed-Signal Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Donut Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mixed-Signal Simulation Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Compiling and Running a Mixed-Signal Design. . . . . . . . . . . . . . . . . . . . . . . .
10
Mixed-Signal Simulation
Using Mixed Signal Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Mixed Signal Feature Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
Verilog-top/SPICE-top Flows and Donut Configurations . . . . . . . . . . . . .
14
Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPICE View Selection for Multi-view Cells Under Verilog . . . . . . . .
Verilog View Selection for Cells Under a SPICE Parent. . . . . . . . . .
14
15
15
Automatic Verilog Dummy Module Generation . . . . . . . . . . . . . . . . . . . .
15
Verilog-A Model Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
iii
Contents
3.
iv
Parameter Passing Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
XMR (Cross Module Referencing) Across Analog-Digital Boundary . . . .
Logic XMR Access to Analog Nodes . . . . . . . . . . . . . . . . . . . . . . . .
Real XMR Access to Analog Nodes . . . . . . . . . . . . . . . . . . . . . . . .
$snps_force_volt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
$snps_release_volt() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
$snps_get_volt(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
19
19
20
Interface A/D and D/A Signal Conversions . . . . . . . . . . . . . . . . . . . . . . .
When A/D and D/A Converters are Not Inserted for a mixed net . .
21
23
Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog. . . . . . .
Converting Signal Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Converting Signal Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating a Resistance Map File . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
28
30
Post-layout Simulation Through Back-annotation . . . . . . . . . . . . . . . . . . . . . .
32
Using the SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
Known Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Mixed-Signal Simulation in the Verilog-SPICE Flow. . . . . . . . . . . . . . . . . .
35
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
Mixed-signal Setup Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
Netlist-related Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
Identical Module/Subcircuit Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
Case-sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Method #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
37
37
Netlist Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Port-related Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Port-mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
Duplicate Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
Creating a Mixed-signal Simulation Control File . . . . . . . . . . . . . . . . . . . . . . .
45
Mixed-signal Control Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
The choose Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
The a2d command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
The d2a command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Contents
The bus_format Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.
52
The insert_cell Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
The spice_top Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
The use_spice Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
The use_verilog Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
The optimize_shadowfile Command . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
The param_pass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
The print_thru_net Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
The remove_d2a Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
The map_by_node Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
The rmap_file Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
The shadow_file_dir Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
The spice_port_order_as_vlog Command. . . . . . . . . . . . . . . . . . . . . . . .
65
The mview_vlog_noportswap Command . . . . . . . . . . . . . . . . . . . . . . . . .
65
Summary of Mixed-signal Simulation Commands . . . . . . . . . . . . . . . . . .
66
Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Running a Mixed-Signal Simulation in the Verilog-SPICE Flow . . . . . . . .
69
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
Setting Up the Simulation Environment for the Verilog-SPICE Flow . . . . . . . .
70
Version Compatibility Between Analog and Digital Engines . . . . . . . . . .
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Required UNIX Paths and Variable Settings . . . . . . . . . . . . . . . . . .
70
70
71
Required Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
Compiling the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
Running the Simulation in the Verilog-SPICE Flow . . . . . . . . . . . . . . . . . . . . .
74
Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE
75
5.
The ucli% ace Analog Interactive Commands . . . . . . . . . . . . . . . . . . . .
76
DC Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Recompiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Mixed-signal Simulation Output and Display in Verilog-SPICE. . . . . . . . .
79
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
Capturing Analog and Digital Signals in the Output File(s) . . . . . . . . . . . . . . .
79
Printing Analog Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
v
Contents
Dumping Digital Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
Generating a Unified Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merged VPD output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Merged UOD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
82
83
Part III: VHDL/Verilog-SPICE Mixed-Signal Simulation
6.
7.
8.
vi
Using the VHDL/Verilog-SPICE Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
VHDL/Verilog-SPICE Flow Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Donut Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
View Selection for Cells Under a VHDL Parent . . . . . . . . . . . . . . . .
View Selection for Cells Under a Verilog Parent. . . . . . . . . . . . . . . .
View Selection for Cells Under a SPICE Parent . . . . . . . . . . . . . . .
88
89
89
89
Real Port Support for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Interface A/D and D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Generating a Merged Output file for Analog and Digital Signals . . . . . . .
90
Known Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
Mixed-signal Simulation in the VHDL/Verilog-SPICE Flow . . . . . . . . . . . .
93
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
Input Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
VHDL and Verilog Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transistor-level Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
96
Using a VHDL Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
Using a Verilog Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE . . .
99
The use_vhdl Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
The use_verilog and use_spice Commands . . . . . . . . . . . . . . . . . . . . . .
101
Running a Mixed-Signal Simulation in VHDL/Verilog-SPICE. . . . . . . . . . .
103
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
Installation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
Contents
Setting up the NS-VCS-MX Simulation Environment. . . . . . . . . . . . . . . . . . . .
104
License. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
104
Required Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
Compiling the Netlists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
The Analysis Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The vlogan Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The vhdlan Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
106
109
The Elaboration Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Running the Simulation in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . . . . . . . . .
112
Simulation Time Resolution in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . .
113
Interactive Simulation with UCLI using NS-VCS-MX . . . . . . . . . . . . . . . .
113
Back-annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
114
Creating Verilog Wrappers in VHDL/Verilog-SPICE . . . . . . . . . . . . . . . . . .
115
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
The VHDL/Verilog-SPICE Autowrapper Utility . . . . . . . . . . . . . . . . . . . . . . . . .
115
Using the Autowrapper Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
10. Mixed Simulation Output and Display in VHDL/Verilog-SPICE . . . . . . . . .
125
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Generating an Analog Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Generating a Digital Output File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
126
Generating a Merged VPD Output File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
127
9.
Part IV: NanoSim-VCS-AMS Mixed-Signal Simulation
11. Using the NanoSim-VCS-AMS Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
Analog and Digital Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
Understanding Analog and Digital Blocks in Verilog-AMS . . . . . . . . . . . . . . . .
132
The Concept of Nets and Disciplines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
133
vii
Contents
12. Mixed-Signal Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
simv.msv Directory and Mixed-signal Report Files . . . . . . . . . . . . . . . . . . . . .
137
through_net.rpt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
hierarchy.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
mview.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
interface_element.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
138
names_map.rpt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
13. Using Multiple Views, Donut Partitioning and Connect Modules with NS-VCSAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
Selecting Multiple Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
141
Understanding Hierarchical Layering of SPICE and Verilog-AMS in a Design
142
Unsupported Features and Limitations in NS-VCS-AMS. . . . . . . . . . . . . . . . .
143
Converting Signals with Interface A/D and D/A Connect Modules . . . . . . . . .
144
Identifying the Correct Connect Module. . . . . . . . . . . . . . . . . . . . . . . . . .
144
Understanding Connect Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
145
Preparing a Mixed-Signal Simulation with NS-VCS-AMS . . . . . . . . . . . . .
149
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
149
Steps for Preparing a Mixed-Signal Simulation in NS-VCS-AMS . . . . . . . . . .
149
Files Containing Connect Rule and Connect Module Definitions . . . . . . . . . .
151
15. Running a Mixed-Signal Simulation with NS-VCS-AMS. . . . . . . . . . . . . . .
153
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
153
Steps for Running a Mixed-signal Simulation in NS-VCS-AMS . . . . . . . . . . . .
153
Compile Options Specific to NS-VCS-AMS . . . . . . . . . . . . . . . . . . . . . . .
-ams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-ams_discipline logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-ams_drreport. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-ams_iereport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
154
154
154
154
155
Required Input Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
Verilog Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
Mixed-signal Simulation Setup File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
156
14.
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Contents
Part V:
A.
Files Containing Connect Rule and Connect Module Definitions. . . . . . .
156
Compiling and Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
Appendices
Mixed-Signal Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
161
Unified Output Display (UOD) File Samples . . . . . . . . . . . . . . . . . . . . . . . .
163
UOD File Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
163
NanoSim-supported Command-line Options . . . . . . . . . . . . . . . . . . . . . . .
167
NanoSim Command-line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
Reserved Keywords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169
Reserved Keywords for NS-VCS and NS-VCS-MX . . . . . . . . . . . . . . . . . . . . .
169
Reserved Keywords for NS-VCS-AMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
172
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
179
B.
C.
D.
ix
Contents
x
About This Manual
The Discovery AMS Mixed-Signal Simulation User Guide describes how to set
up and use mixed-signal simulations in Discovery-AMS using one of the
following setups:
■
NanoSim-, HSIM-, or XA-VCS
■
NanoSim-, HSIM- or XA-VCS-MX
■
NanoSim-VCS-AMS
Audience
This user guide is meant for designers who use the Discovery-AMS
Mixed-Signal Verification (MSV).
Knowledge of UNIX, the analog tool used in mixed-signal (NanoSim, HSIM or
XA), VCS/VCS-MX, and a waveform viewer is assumed.
Related Publications
For additional information about these interfaces, see
■
The NanoSim/HSIM/XA Release Notes, available on SolvNet (see
Accessing SolvNet on page xiii)
■
Documentation on the Web, which provides HTML and PDF documents and
is available through SolvNet at http://solvnet.synopsys.com
Please refer to the documentation for the following related Synopsys products:
■
NanoSim, HSIM, or XA
■
VCS
■
VCS-MX
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About This Manual
Conventions
Conventions
The following conventions are used in Synopsys documentation.
Convention
Description
Courier
Indicates command syntax.
Italic
Indicates a user-defined value, such as object_name.
Bold
Indicates user input—text you type verbatim—in syntax and
examples.
[]
Denotes optional parameters, such as:
write_file [-f filename]
...
Indicates that parameters can be repeated as many times
as necessary:
pin1 pin2 ... pinN
|
Indicates a choice among alternatives, such as
low | medium | high
\
Indicates a continuation of a command line.
/
Indicates levels of directory structure.
Edit > Copy
Indicates a path to a menu command, such as opening the
Edit menu and choosing Copy.
Control-c
Indicates a keyboard combination, such as holding down
the Control key and pressing c.
Customer Support
Customer support is available through SolvNet online customer support and
through contacting the Synopsys Technical Support Center.
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About This Manual
Customer Support
Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and
answers to frequently asked questions about Synopsys tools. SolvNet also
provides access to a wide range of Synopsys online services, which include
downloading software, viewing Documentation on the Web, and entering a call
to the Support Center.
To access SolvNet:
1. Go to the SolvNet Web page at http://solvnet.synopsys.com.
2. If prompted, enter your user name and password. (If you do not have a
Synopsys user name and password, follow the instructions to register with
SolvNet.)
If you need help using SolvNet, click SolvNet Help in the Support Resources
section.
Contacting the Synopsys Technical Support Center
If you have problems, questions, or suggestions, you can contact the Synopsys
Technical Support Center in the following ways:
■
Open a call to your local support center from the Web by going to
http://solvnet.synopsys.com (Synopsys user name and password required),
then clicking “Enter a Call to the Support Center.”
■
Send an e-mail message to your local support center.
■
•
E-mail support_center@synopsys.com from within North America.
•
Find other local support center e-mail addresses at
http://www.synopsys.com/support/support_ctr.
Telephone your local support center.
•
Call (800) 245-8005 from within the continental United States.
•
Call (650) 584-4200 from Canada.
•
Find other local support center telephone numbers at
http://www.synopsys.com/support/support_ctr.
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About This Manual
Customer Support
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Part: 1 Introduction to Mixed-Signal
Simulations
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1
Getting Started with Mixed-Signal Simulation
This chapter provides a quick introduction to the mixed-signal features available
in Discovery-AMS.
Overview
Discovery-AMS provides a mixed-signal simulation, which enables simulating a
design that is partly modeled in analog and partly in digital.
Mixed-signal simulation is possible through three different solutions depending
on which of the analog simulators available in Discovery-AMS you use.
The three solutions are:
■
NanoSim-VCS/VCS-MX
■
HSIM-VCS/VCS-MX
■
XA-VCS/VCS-MX
Each of the above solutions supports some or all of the following flows:
■
Verilog-SPICE
■
VHDL/Verilog-SPICE
■
Verilog-AMS-SPICE
Table 1 on page 4 maps the solutions to the flows.
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Chapter 1: Getting Started with Mixed-Signal Simulation
Three Mixed-Signal Simulation Flows
Table 1
Solutions
Flows
Verilog-SPICE
VHDL/Verilog-SPICE
Verilog-AMS-SPICE
NanoSim-VCS/VCS-MX
X
X
X
HSIM-VCS/VCS-MX
X
X
XA-VCS/VCS-MX
X
X
Note:
Throughout this manual, any reference to "Verilog" implies "System-Verilog"
as well. This means that wherever Verilog is supported in the mixed-signal
flows, System-Verilog is supported as well.
This chapter contains the following topics:
■
■
■
Three Mixed-Signal Simulation Flows
•
Verilog-SPICE Flow (Flow #1)
•
VHDL/Verilog-SPICE (Flow #2)
•
Verilog-AMS-SPICE (Flow #3)
Preparing for a Mixed-Signal Simulation
•
Donut Configuration
•
Mixed-Signal Simulation Setup File
Compiling and Running a Mixed-Signal Design
This overview briefly describes these features and the components required to
perform a mixed-signal simulation. These topics are described in more detail in
the subsequent sections of this chapter.
Three Mixed-Signal Simulation Flows
There are three mixed-signal simulation flows available, and depending on the
description languages used to model the netlists (e.g., SPICE, VHDL, Verilog),
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Three Mixed-Signal Simulation Flows
one of the three flows must be used. The complete list of features and
limitations of each flow is described in detail in subsequent chapters:
1. Verilog-SPICE Flow (Flow #1)
2. VHDL/Verilog-SPICE (Flow #2)
3. Verilog-AMS-SPICE (Flow #3)
Verilog-SPICE Flow (Flow #1)
The Verilog-SPICE flow (Flow #1) is required when the analog parts of the
design are modeled in one of the SPICE formats supported by the analog
engine or behavioral analog (Verilog-A, ADFMI), and the digital parts are
modeled in Verilog. This flow is supported in three mixed-signal solutions
(depending on the analog engine used for the mixed-signal simulation): NSVCS, HSIM-VCS, and XA-VCS.
VHDL/Verilog-SPICE (Flow #2)
The VHDL/Verilog-SPICE flow (Flow #2) is required when a part, or all of the
digital portion of the design, is modeled in VHDL. In this flow, VCS-MX, which
supports VHDL as well as Verilog, must be used as the digital engine. This flow
is almost identical to Flow #1 (some restrictions apply) with the additional
capability of supporting VHDL blocks in the digital netlist. This flow is supported
in three mixed-signal solutions (depending on the analog engine used for the
mixed-signal simulation): NS-VCS, HSIM-VCS, and XA-VCS.
Verilog-AMS-SPICE (Flow #3)
The Verilog-AMS-SPICE flow (Flow #3) is required when a part, or all of the
design, is modeled in the Verilog-AMS language. Parts of the design can also
be modeled in SPICE and/or conventional digital Verilog. The only solution
currently supporting this flow is NS-VCS-AMS. HSIM and XA cannot be used
as the analog engine in this flow
Note:
VHDL is not currently supported in this flow.
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Chapter 1: Getting Started with Mixed-Signal Simulation
Preparing for a Mixed-Signal Simulation
Preparing for a Mixed-Signal Simulation
To run a mixed-signal simulation in any one the three flows, a mixed-signal
control file must be created. This file contains mixed-signal commands that
control the configuration of the mixed-signal simulation.
This section describes the donut configuration concept in a mixed-signal
simulation, and the mixed-signal control file:
■
Donut Configuration
■
Mixed-Signal Simulation Setup File
Donut Configuration
One of the factors that impacts the setup of a mixed-signal simulation is the
netlist formats used in different layers of the design hierarchy. For example, if
the top level of a design is in SPICE format, the design is called SPICE-top. A
design could also be Verilog-top, VHDL-top or Verilog-AMS-top.
Also, a design in which Verilog is on top of SPICE in the hierarchy is called a
Verilog-SPICE donut configuration. There are many possible donut
configurations for each of the three flows. There are also restrictions on certain
types of donut configurations that are described in detail in following sections.
Figure 1 shows a simple design and its hierarchy. The top_blk (top block)
instantiates two child blocks blk-1 and blk-2. Child block blk-2, in turn,
has child block blk-2-1.
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Preparing for a Mixed-Signal Simulation
Figure 1
Sample design with hierarchy
Cells blk-1 and blk-2-1 are referred to as leaf cells, because they are
located at the bottom of a hierarchy branch.
In a mixed-signal simulation, there are many possibilities for a donut
configuration. Figure 2 shows a Verilog-SPICE-Verilog donut configuration.
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Chapter 1: Getting Started with Mixed-Signal Simulation
Preparing for a Mixed-Signal Simulation
Figure 2
Verilog-top configuration
In Figure 3, another example of a possible donut configuration is shown where
a SPICE-top design has a SPICE-Verilog donut configuration.
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Preparing for a Mixed-Signal Simulation
Figure 3
SPICE-top configuration
Any one block in the hierarchy can have definitions in more than one format.
For example, blk-2 in Figure 3 can have both SPICE and Verilog definitions—
such a cell is called a multi-view cell.
The tool automatically selects a view for each multi-view cell. By default, the
view that matches the parent block is selected (if available).
For example, if blk-2 (in Figure 3) is a multi-view cell with both SPICE and
Verilog views, by default the analog engine selects the SPICE view because it
is the view for its parent block top_blk.
The default behavior can be changed by using a command that explicitly
instructs the tool to select a particular view for a given cell. The view selection
commands are described in detail in Chapter 3, Mixed-Signal Simulation in the
Verilog-SPICE Flow.
Mixed-Signal Simulation Setup File
To run a mixed-signal simulation, a mixed-signal simulation setup file must first
be created. This file is passed to VCS during compile time, and contains the
call to the analog engine (NanoSim, HSIM, or XA) and optional mixed-signal
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Chapter 1: Getting Started with Mixed-Signal Simulation
Compiling and Running a Mixed-Signal Design
commands. Example 1 shows a sample mixed-signal control file for the
NanoSim-VCS flow.
Example 1
Mixed-signal simulation setup file
use_spice -cell blk-1;
use_spice –cell blk-2;
choose nanosim -n blk-1.spi blk-2.spi
bus_format _%d;
-C ns.cfg ;
Compiling and Running a Mixed-Signal Design
Before running a mixed-signal simulation, the netlist must be compiled. This is
the stage where all digital and analog netlists are parsed, and the design
hierarchy is built with analog and digital components. After the compilation, an
executable binary file is generated that must be run to start the mixed-signal
simulation. Example 2 shows a sample compilation command.
Example 2
Compilation command
vcs -ad=control.init
comp.log
top_blk.v
blk-2-1.v
-l comp.log
-o simv -l
In Example 2, VCS is called and the Verilog files top_blk.v and blk-2-1.v
are passed to it. Also passed to VCS is the mixed-signal simulation setup file
control.init. This command generates an executable called simv and a
log file called comp.log.
To start the simulation, the executable file must be run.
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Using Mixed Signal Features
2
This chapter provides a detailed description of the features supported in all flows
of Discovery-AMS mixed-signal simulation.
Overview
Discovery-AMS allows mixed-signal simulation of a design in which some parts
of the design are modeled in SPICE and other parts in HDL (Verilog, VHDL, or
Verilog-AMS depending on the mixed-signal flow).
Note:
It is recommended that before starting a mixed-signal simulation, both
SPICE subcircuits and Verilog modules be verified individually to make sure
they are error-free.
A basic familiarity with both VCS and the analog simulator involved in mixedsignal is assumed, for review of this chapter. Refer to the respective manuals
for each product for more information.
This chapter describes the following topics:
■
Mixed Signal Feature Highlights
■
Known Limitations
Mixed Signal Feature Highlights
The following features are described in detail in this section:
■
Verilog-top/SPICE-top Flows and Donut Configurations
■
Multiple Views
■
Automatic Verilog Dummy Module Generation
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Chapter 2: Using Mixed Signal Features
Mixed Signal Feature Highlights
■
Verilog-A Model Instantiation
•
Parameter Passing Rule
■
XMR (Cross Module Referencing) Across Analog-Digital Boundary
■
Interface A/D and D/A Signal Conversions
•
■
■
When A/D and D/A Converters are Not Inserted for a mixed net
Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog
•
Converting Signal Values
•
Converting Signal Strength
•
Creating a Resistance Map File
Post-layout Simulation Through Back-annotation
•
Using the SDF File
Verilog-top/SPICE-top Flows and Donut Configurations
Discovery-AMS supports both Verilog-top/VHDL-top and SPICE-top
configurations.
In a SPICE-top configuration, the spice_top command must be used in the
mixed-signal simulation setup file, which by default is assumed to be called
vcsAD.init. For Verilog-top or VHDL-top configuration, no specific command is
required. For a description of the spice_top command, as well as other
mixed-signal commands used in Discovery-AMS, see Chapter 3, “Mixed-Signal
Simulation in the Verilog-SPICE Flow.”
Discovery-AMS allows any type of donut configuration (for example, Verilog/
VHDL-SPICE-Verilog/VHDL, SPICE-Verilog/VHDL-SPICE, etc.) with the
following:
■
In mixed-signal flow with NanoSim, ADFMI models can only be at the leaf
level and cannot contain a child block with a SPICE or Verilog view.
Multiple Views
Each block in the design can have definitions in more than one view (for
example, it can have both SPICE and Verilog definitions).
By default, Verilog-SPICE selects the view of the multi-view cell that is identical
to the parent block view. A particular view of a multi-view cell can also be
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Mixed Signal Feature Highlights
selected explicitly by using "use_spice" or "use_verilog" mixed-signal
commands.
SPICE View Selection for Multi-view Cells Under Verilog
By default, if a multi-view child cell is instantiated under Verilog, the Verilog
view of the child is used. But the mixed-signal command "use_spice" can be
used to direct the tool to instantiate the child cell in SPICE view instead.
If a multi-view cell is instantiated under SPICE, by default the SPICE view of
the child is used. Using the "use_spice" command on the child cell will have
no impact because the child view is already SPICE.
Please refer to The use_spice Command on page 55 for more details.
Verilog View Selection for Cells Under a SPICE Parent
By default, if a multi-view child cell is instantiated under SPICE, the SPICE view
of the child is used. But the mixed-signal command "use_verilog" can be
used to direct the tool to instantiate the child cell in Verilog view instead.
If a multi-view cell is instantiated under Verilog, by default the Verilog view of
the child is used. Using the "use_verilog" command on the child cell will
have no impact because the child view is already Verilog.
Please refer to The use_verilog Command on page 56 for more details.
Note:
In mixed-signal simulation using NanoSim, the views for ADFMI and
Verilog-A cannot be switched in the mixed-signal simulation setup file. To
switch views for ADFMI, the NanoSim command-line option -fm adfmi
file(s) must be used. To switch views to Verilog-A, see the section
Verilog-A Model Instantiation.
Automatic Verilog Dummy Module Generation
Discovery-AMS requires an internal Verilog view for every cell in the design—
even SPICE cells.
The tool automatically generates dummy Verilog modules for all subcircuits
available in the SPICE netlist that do not have a corresponding Verilog
module. A Verilog dummy module, also called a dummy wrapper or shadow
file, is defined as a spicemodule instead of module, and contains the port
name, port direction, net name, and instance module definitions (if available).
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Chapter 2: Using Mixed Signal Features
Mixed Signal Feature Highlights
These dummy Verilog modules are generated during the compile time, and are
kept in the simv.daidir directory (for more information about the compile
and simv.daidir directory, please refer to Chapter 4, Running a MixedSignal Simulation in the Verilog-SPICE Flow.
Verilog-A Model Instantiation
In Discovery-AMS, Verilog-A can be used as the analog view of a cell. Such a
Verilog-A cell can be instantiated under SPICE or Verilog.
There are two ways to read in Verilog-A blocks in Discovery-AMS depending
on the mixed-signal flow used.
■
■
For the Verilog-SPICE and Verilog/VHDL-SPICE flows, Verilog-A blocks are
read in by:
•
Using the .hdl command in the SPICE netlist to readin Verilog-A
file(s).
•
Using the appropriate command in the analog simulator to select the
Verilog-A view, in case there are both SPICE and Verilog-A definitions
for the same block. For NanoSim, the command is
use_model_veriloga. For HSIM, the command is .param
HSIMUSEVA=<module name>.
For the Verilog-AMS-SPICE flow, all Verilog files, including Verilog-A, are
passed to VCS at compile time. In this flow it is still possible, although not
preferable, to read in Verilog-A files through SPICE .hdl as well.
Parameter Passing Rule
Parameters can be passed between HDL blocks (Verilog or VHDL) and SPICE.
■
In Verilog-SPICE and Verilog/VHDL-SPICE flows, parameter passing
between HDL and SPICE is not enabled by default. To enable parameter
passing, the mixed-signal command "param_pass enable;" must be
used (see the mixed-signal command section of this manual).
■
Parameter passing between SPICE and Verilog-A is always enabled in all
solutions if Verilog-A is read in via the SPICE .hdl command, as shown in
Example 3.
Example 3
Parameter Passing
.hdl "inv_verilog_a.va"
x1 in out inv_verilog_a vhigh=3.3 vlow=0 td=10
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Mixed Signal Feature Highlights
■
In NS-VCS and NS-VCS-MX, parameter passing between HVA
(Hierarchical Verilog-A) blocks is disabled by default. To enable parameter
passing, the following environment variable must be set:
setenv HVA_ON 1
■
In HSIM-VCS and HSIM-VCS-MX parameter passing between HVA blocks
is not an issue because these solutions do not support HVA.
■
In XA-VCS and XA-VCS-MX parameter passing between HVA blocks is
supported by default.
■
In the Verilog-AMS-SPICE flow parameter passing between Verilog and
SPICE and parameter passing between HVA blocks are enabled by default.
XMR (Cross Module Referencing) Across Analog-Digital
Boundary
Discovery-AMS provides two XMR options to access internal analog nodes in
Verilog:
■
Logic XMR Access to Analog Nodes
■
Real XMR Access to Analog Nodes
Logic XMR Access to Analog Nodes
In this method, the Verilog code can simply treat an internal analog node as a
logic value for read or write operations. The same XMR principles used to
access a digital net must be used to access an analog net. This means that the
full hierarchical path to the analog node must be given whenever an XMR read
or write is made.
Discovery-AMS inserts a2d or d2a converters automatically depending on
whether Verilog is reading from or writing to the internal analog node. The
inserted converters will be subject to the same rules that govern the
conventional interface nets, including resistance map lookup. These a2d and
d2a converters will appear in the "simv.msv/interface_element.rpt"
file along with all other interface elements. And just like any other interface
element, the "a2d" and "d2a" mixed-signal commands can be used to
change the default settings for the a2d or d2a converters inserted for logic
XMR.
Example 4 shows an example of a logic XMR read on an analog node with the
hierarchical path "top.i1.i2.x1.clk" into a Verilog wire.
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Example 4
Assigning the Logic Value Corresponding to the Voltage of an
Analog Node to a Verilog Wire.
assign verilog_wire = top.i1.i2.x1.clk;
Example 5 shows a logic XMR read on an analog node with the hierarchical
path "top.i1.i2.x1.strb" into a Verilog register
Example 5
Assigning the Logic Value Corresponding to the Voltage of an
Analog Node to a Verilog Register.
initial begin
...
verilog_reg = top.i1.i2.x1.strb;
...
end
Example 6 shows how a logic XMR write can be done on an analog node. The
d2a converters inserted by Discovery-AMS will translate the logic values to
voltage values and apply them to the analog node.
Example 6
Assigning Logic Values of a Verilog Register to an iNternal
Analog Node as Voltages.
reg rst_reg;
assign top.i1.i2.x1.rst = rst_reg;
initial begin
...
rst_reg = 1'b0;
#5 rst_reg = 1'b1;
...
end
Real XMR Access to Analog Nodes
In this method, internal analog nodes are accessible to Verilog as real values.
The access is made through calls to Verilog system tasks or system functions
as described in.
The following Verilog system tasks and system functions provide real XMR
access to Analog nodes from Verilog:
Table 2
Accessing Analog Nodes with System Tasks or System Functions
System Tasks
System Function
18
■
■
$snps_force_volt(analog_node, voltage)
$snps_release_volt(analog_node)
■
$snps_get_volt(analog_node)
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Limitation:
For the 2009 release, XA-VCS does not support real XMR. Also, real XMR
is not supported in the VHDL/Verilog-SPICE and Verilog-AMS-SPICE flows.
$snps_force_volt()
This system task allows Verilog to force a voltage to any analog node, even
one connected to an ideal voltage source. In such a case this system task must
override the ideal voltage source.
Syntax
$snps_force_volt(analog_node_name, verilog_real_value |
verilog_real_variable);
Argument
Description
analog_node_name
The full hierarchical node name for the internal
SPICE node. This can also be a mixed net (an A/D
interface net).
verilog_real_value,
verilog_real_variable
An explicit real value or a Verilog real variable. The
value will be applied to the analog node as an ideal
voltage source.
Example:
$snps_force_volt (top.i1.spcell.n1, 3.3);
$snps_force_volt (top.i1.spcell.n1, real_var);
The voltage of the analog node will stay at the given real value until the next
$snps_force_volt or $snps_release_volt system task calls.
$snps_release_volt()
This system task removes the voltage source applied by a previous
$snps_force_volt task, and from that point on, allows the analog node to
assume voltages determined by the analog circuit. If the node has not been
forced with $snps_force_volt or is already released, this system task will
have no effect.
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Syntax
$snps_release_volt (analog_node);
Argument
Description
analog_node_name
The full hierarchical node name for the internal
SPICE node. This can also be a mixed net (an A/D
interface net).
Example
$snps_release_volt (top.i1.spcell.n1);
$snps_get_volt()
This is a Verilog function that allows sampling of voltage values for internal
analog nodes. A function must be used in an expression or assignment.
System tasks are stand-alone Verilog statements that must appear individually
in a line of Verilog code.
This function can be used to assign a value to a Verilog real variable or it could
be used as a real value in an expression.
Syntax:
$snps_get_volt (analog_node_name)
Argument
Description
analog_node_name
The full hierarchical node name for the internal
SPICE node. This can also be a mixed net (an A/D
interface net).
Example
real_var = $snps_get_volt(top.i1.spcell.n2);
if($snps_get_volt(top.i1.i2.sp1_node > 2.5)
…
else
…
end
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Limitation:
These system tasks and functions operate on an on-demand basis and are
not event-driven. This means that they sample/apply analog voltages only
at times when they are called in the Verilog code.
Interface A/D and D/A Signal Conversions
Mixed nets are the signals that enable the connection between analog and
digital blocks in a mixed-signal simulation. These signals are the interface
signals located at the analog-digital boundary.
Depending on whether the direction of the signal transfer is from digital-toanalog or from analog-to-digital, Discovery-AMS must perform D/A or A/D
conversions.
■
In the Verilog-AMS-SPICE flow, the A/D and D/A conversions are done via
"Connect Modules" (see Converting Signals with Interface A/D and D/A
Connect Modules on page 144).
■
In the Verilog-SPICE and Verilog/VHDL-SPICE flows, A/D and D/A
converters are inserted automatically by the tool to carry out A/D and D/A
conversions.
These conversions take place automatically based on the following principles:
■
Mixed nets can be uni-directional, in which case they are either a2d or d2a.
■
Mixed nets can be bi-directional, or inout, which implies that at different
simulation times they can be either of an a2d or d2a nature.
■
The direction of the mixed nets is determined from Verilog port directions:
■
•
In a Verilog child under a SPICE parent configuration, the port direction
of the Verilog child determines the direction of the mixed nets.
•
In a SPICE child under a Verilog parent configuration, if the SPICE child
has a Verilog view as well, the port directions in that Verilog view
determine the direction of the mixed nets.
•
If the SPICE child does not also have a Verilog view, the direction of all
mixed nets will be inout.
The default high and low voltage values in a d2a conversion are the local
analog VDD and 0V, respectively.You can use the mixed-signal "d2a"
command to override these default values (see Mixed-signal Control
Commands).
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■
The default high and low voltage threshold for A/D conversion is 50% of the
local analog VDD. You can use the mixed-signal"a2d" command to
override these default values (see Mixed-signal Control Commands).
■
In the d2a conversion, the digital driver is modeled as an ideal source in
series with a resistor on the analog side. The value of the resistor depends
on the Verilog drive strength, and is determined by the resistance map file
(see the section Creating a Resistance Map File).
■
The behavior of a2d conversion depends on the direction of the mixed-net
interface:
•
If the interface is a uni-directional a2d mixed-net, the analog driver is
modeled as a digital driver with the Verilog default drive strength of 6 or
Strong.
•
If the interface is a bidirectional mixed-net, the a2d events will be
modeled as a digital driver whose drive strength is determined by the
effective output resistance of the analog driver. The analog engine
calculates that output resistance and uses it as an index "resistance
map file" to get a corresponding drive strength for Verilog. Smaller
output resistances lead to stronger Verilog drive strengths and larger
output resistances lead to weaker Verilog drive strength (see the
section Creating a Resistance Map File).
You can use the a2d command’s hiz_on and hiz_off options to change
these default behaviors for a2d and bidirectional mixed-nets.
Note:
Calculating a2d drive strength and estimating the output resistance for
the a2d conversion is time consuming, which could noticeably slow
down the simulation if there are too many ports requiring it. Therefore,
Synopsys recommends that the use of "inout" mixed-nets be limited to
those interface nets that are functionally bidirectional. For those
interface nets that have become bidirectional only because they were
ports of a single-view SPICE cell (with no Verilog view to determine port
directions), it is recommended that you use the "a2d" command with
the "hiz_off" option to turn off a2d drive strength calculation.
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■
Only resistive elements—equivalent channel resistance for MOS transistors
and/or ideal resistors—that can be traced to the local power supply or to
ground from a mixed net are used in the calculation of net output resistance,
when such calculation is done.
■
The Verilog drive strength calculation in the a2d conversion for a mixed net
ignores the effects of BJTs, diodes, or coupling capacitors connected to the
ports inside the subcircuits.
A WARNING message is generated by NS-VCS when BJTs or coupling
capacitors are connected to mixed nets:
WARNING:NanoSim:0x2070fe17: the element ‘top.I1.cl’ is
not supported in mixed net driving strength calculation
When A/D and D/A Converters are Not Inserted for a mixed net
There are two cases in which A/D or D/A converters are not inserted on the
path of a mixed net:
Case #1 When two SPICE ports are connected to each other via a Verilog
wire in the parent Verilog cell
Case #2 When two Verilog ports are connected to each other via a SPICE net
in the parent SPICE cell
In these two cases, the analog engine detects that the origin and destination of
the mixed nets are from the same domain (SPICE or Verilog); as a result, No A/
D or D/A converters are inserted on their paths.
Figure 4 on page 24 graphically demonstrates Case #1. Two SPICE blocks,
blk-1 and blk-2, are instantiated under a Verilog parent, and a port of blk1 is connected to a port of blk-2 via a Verilog wire.
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Figure 4
SPICE is the source and destination
Because both the source and destination of that wire are analog, that wire is
treated as an analog net and no A/D or D/A converters are inserted on this path
from blk-1 to blk-2.
As a result, this mixed net is optimized as an analog net, despite its definition
as a Verilog wire, and by default is captured only in the analog output file. (You
can have a digital image of the signal dumped in the digital output file, which is
explained in the following text).
Figure 5 on page 25 graphically demonstrates Case #2. Two Verilog cells,
blk-1 and blk-2, are instantiated under a SPICE parent, and a port from
blk-1 is connected to a port from blk-2 via a SPICE net.
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Figure 5
Verilog is the source and destination
Because the tool detects that both the source and destination of the signal is
digital, it does not insert A/D or D/A converters on the path from blk-1 to blk2, and treats the SPICE net connecting the two digital ports as a digital net.
As a result, this mixed net is optimized as a digital wire, despite its definition as
a SPICE net. By default, this mixed net is captured only in the digital output
file. (You can have an analog image of the signal dumped in the analog output
file, which is explained in the following text).
Such mixed nets—which cross the analog and digital boundary, yet do not
incur the insertion of A/D or D/A components—are referred to interchangeably
as through-nets or thru-nets.
The through-net in Case #1 that connects two analog blocks is referred to as
an a2a through-net. The through-net in Case #2 that connects two digital
blocks is referred to as a d2d through-net.
An a2a through-net is optimized as an analog node and, by default, is dumped
only in the analog output file. You can use the print_thru_net mixed-signal
control command to generate a digital image of the signal created and dumped
in the digital output file. In doing so, a redundant A/D converter is added to the
optimized analog net to generate the digital image.
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Note:
No converter is inserted on the path from blk-1 to blk-2. The new a2d
converter will be added from the analog net between blk-1 to blk-2 and the
digital domain.
The same principle applies to d2d through-nets. By default, a d2d through-net
is optimized as a digital node and is dumped only in the digital output file. You
can use the print_thru_net mixed-signal control command to generate an
analog image of the signal created and dumped in the analog output file. In
doing so, a redundant D/A converter is added to the optimized digital net to
generate the analog image.
Caution!
These redundant A/D and D/A converters can create excess overhead for
the mixed-signal simulation and degrade performance; therefore, these
converters should be used with caution.
Also, when a dummy A/D or D/A converter is connected to an optimized net,
that mixed net is no longer reported as a "through-net".
Signal Conversion from Verilog-to-SPICE and SPICE-to-Verilog
Note that the term SPICE refers to all transistor-level netlist formats supported
by the analog engine. See the following conversion sections:
Converting Signal Values
In the A/D or D/A conversion, Discovery-AMS must translate both the signal
value and the signal strength from one domain to the other.
The signal strength translation (in each direction) is implemented with the help
of the resistance map file, which is described in the section Creating a
Resistance Map File.
The rules governing D/A signal conversion are summarized in Table 3.
Table 3
Signal value conversion rules for digital-to-analog conversion
Verilog value
Transistor-level value
0
■
■
26
0V (gnd)
Can be modified with the d2a mixed-signal
control command.
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Table 3
Signal value conversion rules for digital-to-analog conversion
Verilog value
Transistor-level value
1
■
■
Local supply voltage value
Can be modified by the d2a mixed-signal
control command.
Z
■
The analog node will not be driven by Verilog.
The voltage of the node will depend entirely
on the analog circuitry.
X
■
0V
Can be modified by the d2a mixed-signal
command.
■
Signal value conversion from the transistor level to Verilog is followed by the
digital event generation rule. By default, 50% of the local voltage supply is
used as a threshold for digital event generation. To change the threshold
values for digital event generation, the mixed-signal control command a2d
must be used.
The A/D signal value conversion rules are displayed in Table 4.
Table 4
Signal value conversion rules for analog-to-digital conversion
Transistor-level value
Verilog value
■
Less than (<) or equal to (=) the low
threshold voltage (default = 50% of local
voltage supply)
Can be modified by the a2d command
0
Greater than (>) or equal to (=) the high
threshold voltage (default = 50% of local
voltage supply)
Can be modified by the a2d command
1
In case of bidir interface nets or if the drive
strength calculation is enabled for a2d
interface nets and the analog node is HiZ.
Z
■
■
■
■
No value is converted from transistor-level to X in Verilog.
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Example 7 sets 0.35V as the low-thresh and 0.65V as the high-thresh for a2d
conversion at interface net "top.dout". If the voltage on the top.dout
interface node decreases to 0.35, a digital event is generated and the logic
value changes to 0. If the voltage on the top.dout interface node increases
to 0.65, a digital event is generated and the logic value changes from 0 to 1.
Example 7
Setting low-thresh and high-thresh
a2d loth=0.35
hith=0.65 node=top.dout;
Converting Signal Strength
There are eight different drive strengths defined in the Verilog language—0 is
the weakest and 7 is the strongest. The following list shows the eight Verilog
drive strengths and the way logic 0 and 1 are represented for each level in
Verilog:
■
Level 7: supply0, supply1
■
Level 6: strong0, strong1 (default)
■
Level 5: pull0, pull1
■
Level 4: large, large
■
Level 3: weak0, weak1
■
Level 2: medium, medium
■
Level 1: small, small
■
Level 0: highz0, highz1
These drive strengths enable multiple drivers—with differing strengths—to
drive the same net that can be modeled in Verilog. In case of a conflict between
multiple drivers driving a net, the driver with the value from the strongest driver
prevails and determines the net value. Unless explicitly stated in the Verilog
code, the default drive strength for all Verilog nets is 6 (Strong0, Strong1).
For the A/D conversion, if the mixed net has inout direction, the tool calculates
the effective analog output resistance of the mixed net to estimate an
equivalent drive strength on the digital side.
By default all SPICE ports are assumed to be inout, unless the SPICE cell has
a Verilog view where the direction of ports are explicitly declared. If the
direction of a SPICE port connected to a mixed net is output, no drive strength
mapping from Analog to Digital will take place during A/D conversion and the
mixed net will always assume Level 7 strength (the strongest) in Verilog.
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But if the mixed net connects to a SPICE port of type inout (either because
there is no Verilog view for the SPICE cell or the direction of the port in the
Verilog view is defined as inout) then the tool calculates the effective output
resistance for the analog output and maps it to a corresponding drive strength
in Verilog. This can be a time-consuming task during simulation and it is
recommended to avoid bi-directional mixed nets as much as possible.
For the D/A conversion, the Verilog drive strength is translated to an average
resistor in series with a model analog voltage supply. This drive strength
mapping in D/A conversion occurs for both unidirectional and bi-directional
mixed nets. The following sections describe the rules governing these
conversions:
Verilog-to-Transistor Level Conversion Verilog strength is converted to an
average resistance value. This value is calculated from a corresponding
resistance range listed in a resistance map file. For example, strength “5” is
converted to 3500.15 (ohm). See Figure 6 for a visual representation.
Figure 6
Verilog-to-transistor-level strength conversion
Transistor Level-to-Verilog Conversion Transistor-level resistance value is
converted to the corresponding Verilog strength by a resistance map file. For
example, resistance value 200 (ohm) for logic “1” and resistance value 450
(ohm) for logic “0” is converted to strength “6”. See Figure 7 for a visual
representation.
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Figure 7
Transistor level-to-Verilog strength conversion
Creating a Resistance Map File
The rmapAD.init default resistance map file is available in the directory
/<analog_simulator_installed_directory>/platform/ns/interface/
vcsace
The default resistance map file is used, unless you specify your own resistance
map file using the rmap_file command in the mixed-signal simulation setup
file (vcsAD.init, by default).
You can create a custom resistance map file using unidirectional mapping or
bi-directional mapping. The unidirectional resistance map file is useful when
you want different resistance mapping for either direction: from Verilog-totransistor level, or from transistor level-to-Verilog.
Unidirectional Mapping See the following syntax and description for
strength (Verilog) to resistance (transistor-level) unidirectional mapping.
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The unidirectional -from syntax is
resistance_map -from analog resistance_value_range -to
verilog strength;
The unidirectional -to syntax is
resistance_map -to analog resistance_value_range -from
verilog strength;
See Example 8 for a unidirectional file sample.
Example 8
Unidirectional mapping
resistance_map -from analog 90000.2-1e32 -to verilog 0;
resistance_map -from analog 70000.2-90000.1 -to verilog 1;
resistance_map -from analog 50000.2-70000.1 -to verilog 2;
resistance_map -from analog 5000.2-50000.1 -to verilog 3;
resistance_map -from analog 4000.2-5000.1 -to verilog 4;
resistance_map -from analog 3000.2-4000.1 -to verilog 5;
resistance_map -from analog 1.2-3000.1 -to verilog 6;
resistance_map -from analog 0-1.1 -to verilog 7;
resistance_map -to analog 2002.2-1e32 -from verilog 0;
resistance_map -to analog 1500.2-2002.1 -from verilog 1;
resistance_map -to analog 1000.2-1500.1 -from verilog 2;
resistance_map -to analog 500.2-1000.1 -from verilog 3;
resistance_map -to analog 400.2-500.1 -from verilog 4;
resistance_map -to analog 300.2-400.1 -from verilog 5;
resistance_map -to analog 1.2-300.1 -from verilog 6;
resistance_map -to analog 0-1.1 -from verilog 7;
Note:
Both direction definitions are required for unidirectional mapping.
Bi-directional Mapping See the following syntax and description for strength
(Verilog) to resistance (transistor-level) bidirectional mapping.
The bi-directional syntax is
resistance_map
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Post-layout Simulation Through Back-annotation
See Example 9 for a bidirectional file sample.
Example 9
bidirectional file sample
resistance_map 90000.2-1e32 0;
resistance_map 70000.2-90000.1 1;
resistance_map 50000.2-70000.1 2;
resistance_map 7000.2-50000.1 3;
resistance_map 6000.2-7000.1 4;
resistance_map 1000.2-6000.1 5;
resistance_map 1.2-1000.1 6;
resistance_map 0-1.1 7;
Post-layout Simulation Through Back-annotation
Discovery-AMS supports back-annotation of analog nodes, including those at
the analog/digital boundary, with DSPF/SPEF files. The Verilog modules
instantiated inside the back-annotated analog blocks do not get backannotated by DSPF/SPEF files—you must use the SDF files to back-annotate
those Verilog modules separately.
Discovery-AMS also supports back-annotation of digital blocks with SDF files;
mixed nets are not back-annotated (current limitation). The instantiated SPICE
subcircuit is not affected by the SDF files— you must use the HSPF/HSPEF
files to back-annotate those SPICE subcircuits.
To simulate donut-configured netlists with back-annotation, DSPF/SPEF or
HSPF/HSPEF files must be used for the SPICE representations—depending
on whether the SPICE block is the top level or at lower levels. Use the SDF
files to back-annotate the Verilog modules.
Using the SDF File
Use the $sdf_annotate system task (function) to specify SDF files in a
Verilog module. This usage model is identical to VCS. In Example 10, the
$sdf_annotate system task (function) is called inside the initial block in the
my_back_annotation module. The ./dut.sdf SDF file is in the current
directory. In example 7, the path ./dut.sdf points to the location of the SDF
file and module top identifies the Verilog block on which the SDF backannotation must be applied.
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Example 10
$sdf_annotate system task to specify SDF files
module my_back_annotation();
initial $sdf_annotate("./dut.sdf",top);
endmodule
In Example 8, the $sdf_annotate system task (function) is specified inside
the initial block in the top module. In this case, you do not need to specify
top in the task—the back-annotation applies on all instances of the module
top.
Example 11
$sdf_annotate system task and initial statement
module top ( );
........
initial $sdf_annotate (“./dut.sdf”);
........
endmodule
Known Limitations
The following are current limitations:
■
NanoSim set_sim_hierid command is ignored in the NanoSim-VCS/
VCS-MX flow. (At all times, use the default "." (period) hierarchical
delimiter.)
The following features are not supported in the NanoSim-VCS/VCS-MX flow:
■
HAR
■
BDC
■
.ALTER
■
Bisection
■
Selective BA (back-annotation)
■
SDF annotation on the mixed-net
A mixed net can be back-annotated with an SDF file, but due to hierarchical
net name optimization, the delay introduced by the SDF file might not be
transferred to the analog side in the D2A direction, which could lead to
incorrect results. But in the A2D direction, the delay introduced by the SDF
file for the mixed net is accounted for. Because of this inconsistency and
potentially incorrect results, the use of SDF back-annotation on mixed nets
is strongly discouraged.
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Known Problems
Known Problems
The following problems currently exist:
34
■
SDF back-annotation to the library cells does not function properly. Use the
library cells as design modules, if possible.
■
When a programming language interface (PLI) is used along with the g++
complier on the Linux platform, an error messages for multiple symbol
definition... might be generated. To resolve the error, set the UNIX
environmental variable as follows: setenv NO_STDPP 1
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3
Mixed-Signal Simulation in the Verilog-SPICE Flow
This chapter describes the required steps for preparing Verilog and SPICE
netlists for mixed-signal simulations, and how to generate a mixed-signal control
file.
Overview
Before using any one of the mixed-signal flows, there are several tasks that
should be completed. Verilog netlist files and/or SPICE netlist files may need
some modification for a successful netlist compilation. Check these guidelines
before simulating a design.
When running a mixed-signal simulation, note that the required mixed-signal
simulation control file contains commands that are described in the Creating a
Mixed-signal Simulation Control File section of this chapter.
This chapter contains the following topics:
■
Mixed-signal Setup Checklist
■
Netlist-related Issues
■
■
•
Identical Module/Subcircuit Name
•
Case-sensitivity
•
Power Supplies
•
Netlist Statements
•
Simulation Time
Port-related Issues
•
Port-mapping
•
Duplicate Ports
Creating a Mixed-signal Simulation Control File
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Mixed-signal Setup Checklist
■
Mixed-signal Control Commands
■
The optimize_shadowfile Command
■
Summary of Mixed-signal Simulation Commands
■
Known Limitations
Mixed-signal Setup Checklist
Table 5 is a checklist for the setup of the mixed-signal simulation. Each task
that pertains specifically to Verilog, SPICE, or both, is checked and is detailed
throughout this chapter.
Table 5
Mixed-signal setup checklist
Topic
Task
Verilog
SPICE
Netlist-related Issues
Identical Module/Subcircuit Name
x
x
Case-sensitivity
x
x
Power Supplies
x
x
Netlist Statements
Port-related Issues
x
Simulation Time
x
x
Port-mapping
x
x
Duplicate Ports
x
x
Netlist-related Issues
Each topic listed in Table 5 is described in the following:
Identical Module/Subcircuit Name
For a multi-view cell, the Verilog module name and the SPICE subcircuit names
must be identical, as well as the number of ports and their names between the
two views.
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Case-sensitivity
For a multi-view cell, the Verilog module name’s case and the SPICE subcircuit
name’s case must be identical. The cases for port names must be identical
between SPICE and Verilog views. Also, be aware that every name in HSPICE
netlists is treated as lowercase (by default). Because Verilog is case-sensitive,
and VCS processes everything as-is (by default), you must be aware of any
possible case discrepancies between the two views that may arise.
Power Supplies
Power supplies must be passed to SPICE subcircuits to function properly. If the
SPICE subcircuit is instantiated under Verilog, the supply nets can be passed
to it by one of the following two methods:
Method #1
If neither the subcircuit definitions, nor their instantiations under Verilog,
contain the supply pins (that is, VDD and VSS), then the supply pins must be
propagated to the SPICE subcircuits via.global statements in SPICE.
Method #2
If both the subcircuit definitions and their instantiations under Verilog contain
the supply pins (that is,VDD and VSS) then there are two options for passing
supplies to SPICE:
■
Verilog can drive the powernets (e.g. drive VDD to 1'b1 and VSS to 1'b0).
The powernets will be fed to SPICE through d2a elements at the boundary.
All d2a interface elements include a series resistance map resistor which
are undesirable for powernets. To remove the resistance map use the "d2a"
command with "powernet" option for both VDD and VSS.
Example:
d2a powernet
d2a powernet
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hiv=1.2 lov=0
hiv=1.2 lov=0
node=top.vdd;
node=top.vss;
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assuming that the power supply is 1.2V. The hierarchical paths to the
powernets must be taken from the "simv.msv/interface_element.rpt" report
file.
■
A new two-port SPICE subcircuit must be created that has defined analog
supplies. By instantiating this new subcircuit under Verilog, the two ports are
connected to the supply pins for other SPICE cells under Verilog. In this
way, the SPICE cell receives its supply.
Figure 8 shows an example of the SPICE definitions for Method #1, in which
VDD and VSS pins do not appear in the subcircuit port list, and a .global
statement is used instead to provide supply net connectivity:
Figure 8
SPICE supply pins passed to a subcircuit via a .global statement
Figure 9 shows the Verilog instantiation of the subcircuit defined in Figure 8.
Because the power supply nets are defined and passed to SPICE subcircuits
as globals nets, they do not need to appear in the SPICE instantiation under
Verilog:
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Figure 9
Instantiation of the subcircuit defined in Figure 8
Examples for Method #2 are displayed in Figure 10 and Figure 11. Supply nets
are defined as subcircuit ports and are passed to SPICE cells at their
instantiations under Verilog.
Figure 10 shows the subcircuit definitions. A two-port SPICE subcircuit is
defined that contains analog supply sources:
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Figure 10
SPICE definitions for the design cell and a user-defined subcircuit
Figure 11 shows the instantiation of these cells under Verilog. Note that the
two-port subcircuit containing the analog supplies must be instantiated under
Verilog, to establish supply connections to SPICE cells.
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Figure 11
Instantiation of SPICE cell containing analog supplies under Verilog
to establish supply connectivity
Netlist Statements
Any statements, keywords, or elements that are not supported by by the analog
simulator in a stand-alone analog simulation are also not supported in mixedsignal either. For example, a y element in an Eldo format netlist is not
supported in NanoSim and is therefore not supported in NS-VCS.
All other options and/or statements that are required for correct analog
simulation setup, such as .options scale=1e-6, must be included in the
netlist for mixed-signal as well. See Example 12 for a SPICE netlist file
sample.
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Example 12
SPICE netlist file sample
.lib ‘models’ TT
.inc ‘cells.spi’
.options scale=1e-6
.temp 27
.global vdd gnd
.subckt test a b c d
x1 a b n1 vdd cell1
x2 c n1 d ref cell2
vref ref gnd 2.0
.ends
vvdd vdd 0 dc 3.3
vgnd gnd 0 dc 0
.end
Simulation Time
In mixed-signal simulation, the simulation time can be determined by either the
analog domain (usually by the .tran statement) or in the digital domain
(usually a $finish system task in the Verilog code).
In the case when different stop times are specified in analog and digital
domains, the smaller of the two times determines the simulation stop time.
Note:
For NanoSim, HSIM, or XA to be able to report the completed percentage
of simulation time, there must be a .tran statement in the SPICE code.
The analog engine bases its percentage calculation on the run time given
by the .tran statement.
Port-related Issues
The section contains information about:
■
Port-mapping
■
Duplicate Ports
Port-mapping
For a SPICE parent instantiating a Verilog child, by default, ports are mapped
by position. However, name-based port mapping can be achieved by creating a
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SPICE view for the Verilog cell (if one is not already there). The tool then
automatically maps ports by name for the child Verilog cell, comparing the port
order between the SPICE and Verilog views, and rearranging the Verilog port
order to match the SPICE view.
In the case of a Verilog parent instantiating a SPICE child, either name-based
or position-based port-mapping can be used. When using port-mapping by
name, the Verilog module port name begins with a period character ( . ), and
must be identical to the SPICE port name. The cases for port names at the
instantiation must be identical to the case of ports in the subcircuit definition.
Figure 12 demonstrates the Verilog syntax for name-based port mapping.
Figure 13 is an example of port mapping by name.
Figure 12
Verilog syntax example
nor i2 (.a(in1));
instance port name
module port name
module name
Figure 13
instance name
Port mapping by name
// Verilog instantiation
...
//name mapping
nor2 i2(.a(in1),
.b(in2), .zn(out2));
*SPICE subckt
.subckt nor2 zn a b
...
.ends
Port-mapping at the Verilog instantiation can also be implemented by the port
position. Port count and positions must be identical between the Verilog
instantiation and the SPICE subcircuit definition. In Figure 14, the port zn of
the SPICE subcircuit nor1 is connected to the wire out1 at the instantiation
of that subcircuit in Verilog. The port count must also be identical.
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Figure 14
Port mapping by position
// Verilog instantiation
...
//position mapping
nor1 i1 (out1, in1, in2);
*SPICE subckt
.subckt nor1 zn a b
...
.ends
Port-mapping between Verilog and SPICE can also be achieved for bus ports.
By default, Discovery-AMS requires that the bus members be contiguous in the
subcircuit definition (that is, no other port defined between any two members of
the same bus port), and the ports must be sequentially numbered—ascending
or descending. Failing to meet these two requirements leads to compilation
failure. Additionally, the ascending or descending order of the bus members in
SPICE must be identical to the order expected by the Verilog parent block;
otherwise, the port connections will be incorrect.
However, if the bus port definition in the SPICE subcircuit does not meet these
requirements, the problem can be resolved by defining a Verilog view for the
subcircuit and using the following mixed-signal command to set the port order
in the SPICE subcircuits to that of their Verilog view:
spice_port_order_as_vlog;
Figure 15 shows an example of a SPICE subcircuit with bus ports and its
instantiation in a Verilog parent block. In the SPICE subcircuit, the port names
a[3], a[2], a[1] and a[0] are contiguous, and the sequencing of the bus
members meets the expectation of the parent Verilog (both are descending).
As a result, compilation should be without problems related to the bus order in
SPICE. In addition, the port connections for this bus are correct since both the
bus port a in SPICE and the wire ai in Verilog are in a descending order.
By default, the tool assumes that the SPICE port names that connect to a
mixed-net and contain closed bracket characters [ ] are members of a bus. If
the bus notation in the SPICE subcircuit is a string different from [ ], use the
mixed-signal bus_format command to override the default SPICE bus
notation.
For example, if the bus members of the SPICE subcircuit in Figure 15 were
a<3>, a<2>, a<1> and a<0>, add the following command to the mixedsignal simulation setup file:
bus_format <%d>;
For more information, see The bus_format Command section.
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Figure 15
Port mapping for the Verilog vector port and SPICE scalar port
// Verilog instantiation
...
addr i3(.a(ai[3:0]),
.b(bi[3:0]), .cin(ci),
.s(su[3:0]), .cout(co));
...
*SPICE subckt
.subckt addr a[3] a[2]
+a[1] a[0] b[3] b[2] b[1]
+b[0] cin s[3] s[2] s[1]
+s[0] cout
.ends
Duplicate Ports
Duplicate port names in the SPICE subcircuit cannot be used, except for power
supply nodes.
Creating a Mixed-signal Simulation Control File
By default, VCS looks for vcsAD.init file as the mixed-signal simulation
setup file if no file name is specified with the VCS switch "-ad". You can specify
a different file name with the -ad=<control_file_name> compile-time
option. The mixed-signal simulation control file contains all the commands to
configure mixed-signal simulation.
The mixed-signal simulation setup file must contain the choose command.
See the following syntax, examples, and descriptions for the mixed-signal
control commands:
■
The choose Command
■
The a2d command
■
The d2a command
■
The bus_format Command
■
The insert_cell Command
■
The spice_top Command
■
The use_spice Command
■
The use_verilog Command
■
The optimize_shadowfile Command
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■
The print_thru_net Command
■
The remove_d2a Command
■
The map_by_node Command
■
The rmap_file Command
■
The shadow_file_dir Command
■
The spice_port_order_as_vlog Command
■
The mview_vlog_noportswap Command
■
The rmap_file Command
To use these commands, the following rules apply:
■
All commands must be completed with a semi-colon (;)
■
To create a comment line, insert the double forward-slash character (//)
■
Commands can span more than one line with no line continuation character
needed. The Enter character at the end of each line will serve as the line
continuation character.
For example, the following command spread across two lines is considered
one command line:
choose nanosim -nspice test.spi
output_files/nanosim ;
-C config –nvec test.vec -o
Mixed-signal Control Commands
The following section describes the syntax and application of mixed-signal
control commands.
Note:
As of the 2009.06 release, the additional VCS switches ("-ad_hsim" and
"-ad_xa") which were previously required for HSIM and XA mixed-signal
simulations, are no longer needed.
The choose Command
Use the choose command to point to the analog simulator (NanoSim, HSIM,
or XA) and pass command line options to it.
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See the following syntax , examples, and description for the choose
command:
choose nanosim nanosim_command_line_options;
choose hsim hsim_command_line_options;
choose xa xa_command_line_options;
Example 13 specifies that a SPICE netlist named net.spi and an analog
configuration file named cfg for the NanoSim simulation must be read. Note
that the first line is a comment, which is preceded by a double-slash character
(//).
Example 13
The choose command in NanoSim-VCS/VCS-MX simulation
//This is a comment
choose nanosim -n net.spi -C
cfg;
Example 10 specifies that HSIM is the analog engine in the mixed-signal
simulation and a SPICE netlist named net.spi must be passed to it.
Example 14
The choose command in HSIM-VCS/VCS-MX simulation
//This is a comment
choose hsim -i net.spi;
Example 11 specifies that a SPICE netlist named net.spi must be read by XA
and it also uses the -c command line option to pass XA analog configuration
commands stored in the xa.cmd file.
Example 15
The choose command in XA-VCS/XA-VCS-MX simulation
//This is a comment
choose xa -n net.spi -c xa.cmd;
Mixed-signal simulation does not support all NanoSim command-line options.
See Appendix C, “NanoSim-supported Command-line Options,” for the
supported options.
The a2d command
Use this command to control all aspects of the A2D interfaces in the NS/HSIM/
XA-VCS and NS/HSIM/XA-VCS-MX solutions. If this command is not specified,
then by default all a2d events will be triggered at 50% of the local VDD.
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Syntax
a2d [ loth=lo_thrsh[V | %] ] [ hith=hi_thrsh[V | %] ]
hiz_off | hiz_on ] <cell=cell_name port=port_name |
node=hier_name>
Options
Description
lo_thrsh,
hi_thrsh
These two options determine the low and high
threshold values
[
The values are numeric and specify absolute
voltage values if used alone or followed by v or V.
hiz_off
Turns off the a2d drive strength calculation. All a2d
events are passed to digital with the Verilog default
drive strength of 6 (strong).
With this option enabled, no HiZ event will be
passed to digital, because the HiZ state is
determined as part of the a2d drive strength
calculation.
This feature is enabled by default for unidirectional
a2d interfaces.
hiz_on
Turns on the a2d drive strength calculation. For
each a2d event, the analog engine calculates the
analog output resistance and uses that value as an
index to the "resistance map" file to get the
corrsponding Verilog drive strength to pass to
Verilog.
With this option enabled, HiZ states are passed to
digital if the analog engine identifies them.
This feature is enabled by default for bidirectional
interface nets.
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Options
Description
cell=cell_name,
port=port_name,
node=hier_name
The command can be applied as cell-based, in
which case the cell name and port name must be
given.
Alternatively, the command can be, instance based,
in which case the hierarchical path to the instance
port must be given.
Cell and port names can contain the asterisk (*)
wildcard character. For example,
node=top.i1.ad*, cell = *foo, port=*
Each of the specifications in the following example sets the low threshold to
0.7V:
Example
loth=0.7
loth=0.7v
loth=0.7V
If, however, the numerical values are followed by % character, the values
represent ratios of the local supply. For example, the following specifications
set the low threshold value to 20% of the local supply:
Example
loth=20%
Each of the specifications in the following example sets the low threshold to
0.7V:
Example
The following example sets the a2d low and high thresholds for node
"top.i1.ctl" to 0.2V and 1.7V respectively.
a2d loth=0.2
hith=1.7 node=top.i1.ctl;
Note:
If multiple a2d commands in the mixed-signal control file target the same
node, the last command overrides all the others.
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The d2a command
Use this command to control all aspects of the D2A interfaces in the NS/HSIM/
XA-VCS and NS/HSIM/XA-VCS-MX solutions.
Syntax
d2a [powernet][rf_time=slope_time] | [rise_time=rise_time]
[fall_time=fall_time][delay=delay_time][x2v=0|1|2|3|4]
[hiv=high_voltage lov=low_voltage] <cell=cell_name
port=port_name | node=hier_name>
Options
Description
powernet
This command identifies a d2a node as an ideal
voltage source on the analog side without the
resistance map resistor. This option must be used
when Verilog drives analog powernets in order to
remove the series resistance map resistors and to
allow efficient partitioning of the analog circuit.
rf_time=slope_time
Specifies the analog rise and fall times. The default
time unit is in seconds, so specify the sub-unit with
the value rf_time=1.5n, for example. With this
option, both rise and fall times are set to the same
value .
rise_time=rise_time
Specifies the analog rise time. This option must be
used in combination with the fall_time option.
The default time unit is in seconds, so specify the
sub-unit with the value fall_time=1n
rise_time=2n, for example.
NOTE: When fall_time and rise_time are
used, the resistor maps are not used to perform
digital-to-analog translation.
fall_time=fall_time
Specifies the analog fall time. This option must be
used in combination with the rise_time option.
The default time unit is in seconds, so specify the
sub-unit with the value fall_time=1n
rise_time=2n, for example.
NOTE: When fall_time and rise_time are
used, the resistor maps are not used to perform
digital-to-analog translation.
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Options
Description
delay=delay_time
Specifies the delay before the analog transition
starts. The default time unit is in seconds, so specify
the sub-unit with the value delay=1.5n, for
example.
x2v=
Specified with a value of 0, 1, 2, 3 or 4. Sets the
rule on how a logic X must be translated to a voltage
level on the analog side:
Use this option to manage the translation of the X to
a voltage level.
■
■
■
■
■
0: always set to the logic zero voltage (default)
1: always set to the logic one voltage
2: if node is in PWL, SMS, or analog mode, set
to (the logic one voltage + the logic zero voltage)/
2; otherwise, set to low_voltage.
3: set to previous voltage
4: if logic = 0, set to the logic one voltage else;
if logic = 1 set to the logic zero voltage else get
previous voltage.
hiv=high_voltage
Specifies the logic one voltage level value. By
default, the analog engine determines this value.
This option must be used in combination with the
lov= option.
lov=low_voltage
Specifies the logic zero voltage level value. By
default, the analog engine determines this value.
This option must be used in combination with the
hiv= option.
cell=cell_name,
port=port_name,
node=hier_name
The command can be applied as cell-based, in
which case the cell name and port name must be
given.
Alternatively, the command can be instance based,
in which case the hierarchical path to the instance
port must be given.
Cell and Port names can contain the asterisk (*)
wildcard character. For example,
node=top.i1.ad*, cell = *foo, port=*
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Example
d2a hiv=1.8 lov=0.1 node=top.i1.ctl;
d2a powernet hiv=1.2 lov=0 node=top.vdd;
d2a powernet hiv=1.2 lov=0 node=top.vss;;
Note:
If multiple d2a commands in the mixed-signal control file target the same
node, the last command overrides all the others.
The bus_format Command
Use the bus_format command to specify the bus format used in the SPICE
netlist.
The bus index is indicated by the number shown at the %d position in the
SPICE netlist. The bus index must be sequential from MSB to LSB or from LSB
to MSB: for example, a<3> a<2> a<1> a<0>. If the bus index is not
sequential, NanoSim/HSIM/XA prints an error message and exits.
See the following syntax, example, and description for the bus_format
command:
bus_format open_char %d close_char;
Example 16 shows how to specify NS-VCS that angle brackets (< >) are used
as the bus notation in the SPICE netlist:
Example 16
Angle bracket character as a bus format
bus_format <%d>;
*SPICE subckt
.subckt addr4 a<3> a<2> a<1> a<0>
+b<3> b<2> b<1> b<0> cin
+s<3> s<2> s<1> s<0> cout
.ends
Example 17 Specifies that the underscore ( _) character in the SPICE netlist is
used as open_char, and no character is used as close_char.
Example 17
Underscore character as a bus format
bus_format _%d;
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*SPICE subckt
.subckt addr4 a_3 a_2 a_1 a_0
+b_3 b_2 b_1 b_0 cin
+s_3 s_2 s_1 s_0 cout
.ends
Note:
Discovery-AMS only supports the following bus format characters for
SPICE:
{ } < > [ ] _
The insert_cell Command
This command allows the insertion of a 2-port SPICE netlist on the analog side
of an interface net.
Syntax
insert_cell [model= ADFMI_model_name [param=parameter_list]
] [subckt= subcircuit_name apin=port_name dpin=port_name
] <cell=cell_name port=port_name | node=hier_name>
subckt= subcircuit_name apin=port_name dpin=port_name
Options
Description
subckt=
subcircuit_name
apin=port_name
dpin=port_name
Identifies a two-port subcircuit to be inserted on the
analog side of the interface and determines which
port will face the analog side and which the digital
side.
The "apin=" and "dpin=" options are only needed if
the the two ports of the inserted cell are not called
the default names "apin" and "dpin".
model=
Only for NS-VCS, NS-VCS-MX and NS-VCS-AMS
ADFMI_model_name
solutions: identifies the name of the ADFMI model
[param=parameter_list] to be inserted at the interface.
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Options
Description
cell=cell_name,
port=port_name,
node=hier_name
The command can be applied as cell-based, in
which case the cell name and port name must be
given.
Alternatively, the command can be instance based,
in which case the hierarchical path to the instance
port must be given.
Cell and port names can contain the asterisk (*)
wildcard character. For example,
node=top.i1.ad*, cell = *foo, port=*
Example
To insert the 2 port SPICE subcircuit:
.subckt multiplier in out
...
.ends
At the interface net "top.rst", the following command must be used:
insert_cell
subckt=multiplier apin=in
dpin=out node=top.rst;
Example
To insert the 2 port SPICE subcircuit:
.subckt term apin dpin
...
.ends
At the interface net "test.i1.d_in", the following command must be used:
insert_cell subckt=term
node=top.i1.d_in;
The spice_top Command
Use the spice_top command to indicate that the top-level of the design is
described in SPICE. This command is required for simulating a SPICE-top
design.
See the following syntax, example, and description for the spice_top
command:
spice_top [name=unique_name];
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The unique_name option assigns a name (of your choice) to the top-level
dummy module instance—see Example 18. Specifying a unique_name
option is useful when you want the name of the top-level block in design be
something other than the default SPICE-top name "snps_sptop".
Example 18
unique_name option
spice_top name=my_top;
The use_spice Command
Use the use_spice command to explicitly instruct the tool to use the SPICE
view of a multi-view cell for a child cell under a Verilog parent. By default
Discovery-AMS chooses the view for the child cell that is the same as the
parent cell view. So if the parent of a multi-view cell has a Verilog view, by
default the same view will be picked for the child cell. Use this command to
override the default view selection and explicitly select the SPICE view for a
given cell or instance of a cell. The * (asterisk) wildcard is accepted for SPICE
subcircuit names. In the case of NS-VCS/VCS-MX, a configuration file can also
be specified with the -C option.
See the following syntax, example, and description for the use_spice
command:
use_spice -cell subcircuit_names [-C cfg_file_name];
use_spice instance_names [-C cfg_file_name];
Note:
The first syntax shows the cell-based view selection, in which all instances
of the given cell use the SPICE view. The second syntax shows the
instance-based view selection, in which only the given instance name uses
the SPICE view.
Important:
Both the instance_names and the subcircuit_names options cannot
be used in a single command line.
Example 19 shows how the SPICE view is used for all instances of the cell
memory. This command can be used when both the memory Verilog module
and the memory SPICE subcircuit are available.
Example 19
Instantiating the SPICE subcircuit instead of the Verilog module
use_spice -cell memory;
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Note that the instance name (under the SPICE view) begins with the letter X.
To ensure that you are using the correct hierarchical path to the instance, use
the hierarchical names listed in the "interface_element.rpt" file under the
"simv.msv" directory as a guide. The "interface_element.rpt" file is explained in
Chapter 12, Mixed-Signal Report Files.
The use_verilog Command
Use the use_verilog command to explicitly instruct the tool to use the
Verilog view of a multi-view cell for a child cell under a SPICE parent. By
default Discovery-AMS chooses the view for the child cell that is the same as
the parent cell view. So if the parent of a multi-view cell has a SPICE view, by
default the same view will be picked for the child cell. Use this command to
override the default behavior and explicitly select the Verilog view for the given
cell or instance of a cell. The * (asterisk) wildcard can be accepted for module
names.
See the following syntax, example, and description for the use_verilog
command:
use_verilog [use_vcs] -module module_name;
use_verilog [use_vcs] instance_name;
Note:
The first syntax shows the cell-based view selection, in which all instances
of the given cell use the Verilog view. The second syntax shows the
instance-based view selection, in which only the given instance name uses
the Verilog view.
The use_vcs command can be used as an alias for the use_verilog
command.
Important:
Both the instance-based and cell-based options cannot be used in a single
command line.
Example 20 shows how to use the Verilog view for all instances of the cell
memory. This command can be used when both the memory Verilog module
and the memory SPICE subcircuit are available.
Example 20
Instantiating the Verilog module instead of the SPICE subcircuit
use_verilog -module memory;
(use_vcs -module memory;)
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Be aware that in most cases, when the use_verilog command is specified in
SPICE, the instance will begin with the X character.
The optimize_shadowfile Command
Use the optimize_shadowfile command to optimize the shadow Verilog
hierarchy generated for SPICE blocks. To save compile time, this command
instructs the analog engine that it should not generate unnecessary Verilog
dummy modules for blocks with the SPICE view. If references to nets in the
transistor-level netlist (from the Verilog netlist) are made when this command is
used, compilation errors related to the cross-module references (XMR) may
occur. Be cautious when using this option with XMR.
See the following syntax, example, and description for the
optimize_shadowfile command:
optimize_shadowfile;
In Example 21, NanoSim/HSIM/XA is instructed not to generate some of the
Verilog dummy modules so the Verilog hierarchy under the SPICE view can be
optimized.
Example 21
Optimizing Verilog hierarchy under the SPICE view
optimize_shadowfile;
Note:
Using this command prevents VCS from probing inside the SPICE
hierarchy; this can prevent optimization of D2D through-nets, potentially
increasing the number of interface nodes.
The param_pass Command
This command enables parameter passing between Verilog/VHDL and SPICE.
Table 6 shows the default behavior for parameter passing in different flows.
Use the param_pass command’s disable and enable options to change
the default behavior.
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param_pass [enable | disable]
Table 6
Flow
Default
Description
Verilog-AMS-SPICE
enable
Parameter passing between Verilog and SPICE
is enabled by default.
Verilog-SPICE
disable
Parameter passing between HDL and SPICE is
disabled by default.
Verilog/VHDL-SPICE
disable
Parameter passing between HDL and SPICE is
disabled by default.
The print_thru_net Command
Use the print_thru_net command to force NanoSim/HSIM/XA to
instantiate a dummy A/D or D/A converter at the given mixed-net to make an
image of through-nets visible in the other domain. By default, a2a through-nets
are only dumped in the analog output file, and d2d through-nets are only
dumped in the digital output file.
See the following syntax, example, and description for the
print_thru_net command:
print_thru_net a2a|d2d|all;
Argument
Description
a2a
Prints the digital image of all a2a through-nets in the
digital output file
d2d
Prints the analog image of all d2a through-nets in
the analog output file
all
Combines both the a2a and d2d arguments
Important:
When the print_thru_net command is added, extra A/D or D/A
converters are inserted, which could potentially result in a slower simulation.
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The remove_d2a Command
Use the remove_d2a command to remove a D2A (digital-to- analog) mixednet from the digital-analog boundary, and apply a constant DC voltage on the
analog side source with a value defined by the dc= argument. The node=
argument takes a mixed-net. The node= argument cannot take the asterisk
wild card character ( * ), such as node=* . However, a partial node search
using the asterisk character is legal; for example, node = top.din*
matches all signals with names starting with the top.din string.
See the following syntax, example, and description for the remove_d2a
command:
remove_2da [dc=dc_voltage_source_value] node=node_name;
Example 22 shows that top.VVDH is no longer a mixed-net node. The
constant dc voltage source value is 1.8V. , and is applied to that net in the
transistor-level netlist.
Example 22
Removing the node from the interface
remove_d2a dc=1.8 node=top.VVDH;
Example 23 shows that all net names starting with top.V are no longer
considered mixed-nets. In addition, the constant dc voltage source with a
value of 2.5V is applied to those nets in the transistor-level netlist.
Example 23
Using the wild card to specify nodes
remove_d2a dc=2.5 node=top.V* ;
Note:
When multiple remove_d2a commands are used for the same mixed-net(s)
in the mixed-signal simulation setup file, the last command takes
precedence.
The map_by_node Command
Use the map_by_node command if a specific resistance value is required for
d2a conversion at an interface node, instead of the value calculated from the
resistance map file. This command is only effective in the digital-to-analog
direction.
See the following syntax, example, and description for the map_by_node
command:
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map_by_node
r=resistance_value
node=node_name(s);
In Example 24, the 5 ohm resistance value is applied to the interface resistor
connected to the top.n1 node.
Example 24
Using 5 ohm as the interface resistor value
map_by_node r=5 node=top.n1;
When multiple map_by_node commands are used for the same mixed-nets in
the mixed-signal simulation setup file, the last command takes precedence.
The rmap_file Command
Use the rmap_file command to specify the resistance map file or the path
to where the resistance map file is located. If the command is not specified,
the default rmapAD.init resistance map file from the NanoSim/HSIM/XA
installation will be used.
See the following syntax, example, and description for the rmap_file
command:
rmap_file resistance_map_file_name [options];
The node, instance and subcircuit options are mutually exclusive, and
cannot be used with each other in the same command. However, these
options can be used in separate rmap_file commands.
When more than one rmap_file command is used, the last command
overrides the settings of the previous one(s).
See Table 7 for the four rmap_file command option categories.
Table 7
rmap_file command option categories
Category
Command option
file
Custom resistance map file name.
node
node=nodename(s)
instance
inst=instance_names(s)
inst=instance_name
port=port_name(s)
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Table 7
rmap_file command option categories
Category
Command option
subcircuit
subckt=subckt_name(s)
subckt=subckt_name
port=port_name(s)
In Example 25, resis_comp.map is the resistance map file in the current
directory.
Example 25
Using user-defined resistance map available in the current
directory
rmap_file resis_comp.map;
In Example 26, resis.map is the resistance map file in the /home/john/
work directory.
Example 26
Using user-defined resistance map with the directory path
rmap_file /home/john/work/resis.map;
In Example 27, r2.map is the resistance map file that is applied to the
top.i1.wen and top.i2.ren nodes. The default resistance map file is
applied to the remaining mixed-nets.
Example 27
Applying user-defined resistance map to the specified node
rmap_file r2.map node=top.i1.wen top.i2.ren;
In Example 28, r3.map is the resistance map file that is applied to all mixednets connected to the top.i1.abc and top.i2.xyz instances. The default
resistance map file is applied to the remaining mixed-nets.
Example 28
Applying user-defined resistance map to the specified instances
rmap_file r3.map inst=top.i1.abc top.i2.xyz;
In Example 29, r3.map is the resistance map file that is applied to the mixednet connected to port Z located at the top.i1 instance. The default
resistance map file is applied to the remaining mixed-nets.
Example 29
Applying user-defined resistance map to the specified port in the
specified instance
rmap_file r3.map inst=top.i1.abc port=Z;
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In Example 30, r4.map is the resistance map file that is applied to all mixednets connected to the pad subcircuit. The default resistance map file is applied
to the remaining mixed-nets.
Example 30
Applying user-defined resistance map to the specified subcircuit
rmap_file r4.map subckt=pad;
In Example 31, r4.map is the resistance map file that is applied to the mixednet connected to the IN port located at the pad subcircuit. The default
resistance map file is applied to the remaining mixed-nets.
Example 31
Applying user-defined resistance map at the specified port in the
specified subcircuit
rmap_file r4.map subckt=pad port=IN;
In Example 32, r5.map is the resistance map file that is applied to the
top.i1.clk, top.i2.addr[0], top.i2.addr[1] and top.i2.addr[2]
mixed-nets. The default resistance map file is applied to the remaining mixednets.
Example 32
Applying user-defined resistance map at the nodes specified in
the file
rmap_file r5.map nodefile=n1.txt;
Example 33 shows the content of the n1.txt file.
Example 33
n1.txt node file
top.i1.clk
top.i2.addr[0]
top.i2.addr[1]
top.i2.addr[2]
In Example 34, r6.map is the resistance map file that is applied to the mixednets connected to the top.i1, top.i2, top.i3.abc and top.i4.xyz
instances. The default resistance map file is applied to the remaining mixednets.
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Example 34
Applying user-defined resistance map to the instances specified
in the file
rmap_file
r6.map instfile=inst1.txt;
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Example 35 shows the content of the inst1.txt file.
Example 35
inst1.txt instance file
top.i1
top.i2
top.i3.abc
top.i4.xyz
In Example 36, r7.map is the resistance map file that is applied to the mixednets connected to the pad, abc and xyz subcircuits. The default resistance
map file is applied to the remaining mixed-nets.
Example 36
Applying user-defined resistance map to the subcircuits specified
in the file
rmap_file
r7.map subcktfile=s1.txt;
Example 37 shows the content of the s1.txt subcircuit file.
Example 37
s1.txt subcircuit file
pad
abc
xyz
In Example 38, r8.map is the resistance map file that is applied to all mixednets matched by the *addr* string. The default resistance map file is applied
to the remaining mixed-nets.
Example 38
Applying user-defined resistance map at the nodes matched by
the wild card
rmap_file
r8.map node=*addr*;
In Example 39, the r1.map resistance map file is ignored because the
second rmap_file command also encompasses the signal identified by the
first command. When two or more rmap_file commands encompass the
same signals, the last command always prevails—file rmap r2.map is applied
to node top.i1.addr.n1. The default resistance map file is applied to the
remaining mixed-nets that are not covered by these commands.
Example 39
Command priority
rmap_file
rmap_file
r1.map node=top.i1.addr.n1;
r2.map node=top.*addr*;
Example 40 is illegal. The options are mutually exclusive. The node and inst
options cannot be used together in the same command. An additional
rmap_file command must be used, such that one command contains the
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inst= option and the other command contains the node= option, as shown in
Example 41.
Example 40
Illegal command usage
rmap_file
r1.map node=top.i1.addr inst=top.i1.abc;
In Example 41, r2.map is the resistance map file that is applied to the mixednets connected to the top.i1.abc instance. The r1.map file is applied to the
top.i1.addr.n1 node. The default resistance map file is applied to the
remaining mixed-nets.
Example 41
Correct command usage
rmap_file
rmap_file
r1.map node=top.i1.addr.n1;
r2.map inst=top.i1.abc;
If multiple rmap_file commands target the same mixed-nets, and each one
of the commands uses one of the node, instance or subcircuit options,
use the options with the rmap_file command in the following order: (1)
subcircuit-based, (2) instance-based, and (3) node-based.
The wild card (*) character can be used in the port, node, instance, or
subcircuit name.
The period (.) character is the required hierarchical separator. The string
length must not exceed 4,096 characters.
Note:
When multiple rmap_file commands are used for the same mixed-net(s)
in the mixed-signal simulation setup file, the last command takes
precedence.
The shadow_file_dir Command
Use the shadow_file_dir command to specify the directory in which
debugged Verilog dummy module files reside.
In Verilog-SPICE and VHDL/Verilog-SPICE flows, Discovery-AMS
automatically generates Verilog dummy module files for subcircuit definitions
that are available in the SPICE netlist files.
VCS reads the files after they are generated, resolving all required modules in
the Verilog hierarchy. If there are any problems in the Verilog dummy modules,
which is usually caused by differences in the number of ports or their names
between Verilog and SPICE views, VCS fails in the compilation phase.
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All generated Verilog dummy modules are located in the simv.daidir
directory, or the unique_name.daidir directory, where unique_name is the
output name specified with the VCS "-o" option.
See the following syntax, example, and description for the shadow_file_dir
command:
shadow_file_dir directory_path;
Example 42 shows how to have Verilog dummy modules created in the
/home/john/work/wrapper_dir directory.
Example 42
Setting the Location for Verilog dummy modules
shadow_file_dir /home/john/work/wrapper_dir;
The spice_port_order_as_vlog Command
Use the spice_port_order_as_vlog command to force Discovery-AMS to
use the Verilog port order at the instantiation of the SPICE view. This
command applies to multi-view SPICE blocks instantiated under Verilog. By
default, if the SPICE view and the Verilog view of the multi-view cell have a
differing port order, the tool errors-out at compile time.
The mview_vlog_noportswap Command
Use the mview_vlog_noportswap command to force Discovery-AMS to use
the SPICE port order. This command applies to multi-view Verilog blocks
instantiated under SPICE. By default, if the SPICE view and the Verilog view of
the multi-view cell have a differing port order, Discovery-AMS uses the Verilog
port order to make port connections.
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Summary of Mixed-signal Simulation Commands
A summary of the mixed-signal simulation setup file commands is shown in
Table 8.
Table 8
Mixed-signal simulation commands
Command
Use
Definition
choose analog_engine_name
command-line options;
required
Specifies NanoSim, HSIM, or
XA as the analog engine and
its command-line options.
bus_format open_char %d
close_char;
optional
Specifies bus format used in
the SPICE netlist.
set interface_opt [option]
node=node_name(s);
optional
Models the digital-to-analog
interface.
mview_vlog_noportswap;
optional
Applies to multi-view Verilog
blocks instantiated under
SPICE. This command forces
the use of the original SPICE
port order instead of the
default Verilog port order.
optimize_shadowfile;
optional
Optimizes Verilog dummy
modules and hierarchy under
the SPICE view.
no_thru_net_opt [a2a | d2d |
all];
optional
Instructs NanoSim/HSIM/XA
to instantiate dummy A/D or D/
A inverters to generate the
digital image of an a2a
through-net and/or the analog
image of a d2d through-net.
remove_d2a
[dc=dc_voltage_source_value]
node=node_name;
optional
Specifies a d2a mixed-net to
be removed from the Verilog
and transistor-level boundary.
rmap_by_node r=
resistance_value
node=node_name(s);
optional
Applies the resistance value to
the interface resistor
connected to the node at the
digital-to-analog interface.
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Table 8
Mixed-signal simulation commands (Continued)
Command
Use
Definition
rmap_file
resistance_map_file_name
optional
Specifies the resistance map
file to be used.
spice_port_order_as_vlog;
optional
Applies to multi-view SPICE
blocks instantiated under
Verilog. It forces DiscoveryAMS to apply the port order in
the Verilog view of the cell to
the SPICE instantiation.
shadow_file_dir directory_path;
optional
Specifies the directory where
mixed-signal intermediate
files will be stored.
spice_top [name=unique_name];
optional
Specifies that the top level of the
design is SPICE
use_spice -cell
subcircuit_names -C
cfg_file_name;
optional
Specifies cells or instances to
be modeled and simulated in
analog. The "-C" option can
only be used in NS-VCS and
NS-VCS-MX.
optional
Specifies cells or instances to
be modeled and simulated in
digital.
OR
rmap_file
resistance_map_file_path_name
[option];
OR
use_spice instance_names -C
cfg_file_name;
use_verilog -module
module_name;
OR
use_verilog instance_name;
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Known Limitations
The following are known limitations:
■
Bi-directional pass switches and registered nets (tran, rtran, tranif1,
rtranif1, tranif0, and rtranif0) that are connected to mixed-nets
are not supported—the results could be incorrect.
■
Jumper ports that are connected to the mixed-nets are not supported—the
results are incorrect.
See Example 43 for a sample jumper port.
Example 43
Jumper port sample
module jumper (a, a);
inout a;
...
endmodule
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4
Running a Mixed-Signal Simulation in the Verilog-SPICE
Flow
This chapter provides information for the mixed-signal simulation with NS-VCS/
HSIM-VCS, and XA-VCS, including interactive and post-layout parasitic backannotation.
Overview
Information about compiling and simulating the design is described in Chapter
2, “Using Mixed Signal Features.”
This chapter contains the following topics:
■
Setting Up the Simulation Environment for the Verilog-SPICE Flow
•
Version Compatibility Between Analog and Digital Engines
•
Licenses
•
Required UNIX Paths and Variable Settings
•
Using the 64-bit Binaries
■
Required Input Files
■
Compiling the Design
■
Running the Simulation in the Verilog-SPICE Flow
•
Invoking the Interactive Mode with the UCLI Debugging Feature with
Verilog-SPICE
■
DC Initialization
■
Recompiling the Design
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Setting Up the Simulation Environment for the Verilog-SPICE Flow
Setting Up the Simulation Environment for the Verilog-SPICE Flow
To set up the simulation environment, be aware of the following:
Version Compatibility Between Analog and Digital Engines
To successfully run a simulation in the Verilog-SPICE flow, ensure that the
versions of the analog engine (NanoSim/HSIM/XA) and VCS are compatible;
otherwise, the compilation fails. Also ensure that the Operating System utilities
(such as cc, gcc and ld) used during the VCS compilation meet the mixedsignal simulation version requirements.
All the version compatibility requirements for NanoSim/HSIM/XA and VCS, as
well as the correct versions for compile utilities, are provided in the
compatibility table available in the Release Notes on SolvNet.
Licenses
To run a mixed-signal simulation, the following license keys are required:
■
Regular license keys for NanoSim, HSIM, or XA (depending on which
analog engine is being used)
■
Regular license keys for VCS
■
Mixed-Signal keys for NanoSim, HSIM, or XA (depending on which one of
them are used)
Either LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE can be used to
specify the license file location.
setenv LM_LICENSE_FILE Location_of_License_File
or
setenv SNPSLMD_LICENSE_FILE Location_of_License_File
By default, if any one of the required licenses for the analog or digital engines
are missing, the simulation will not compile or execute.
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To enable queuing for license keys, so that the compilation/simulation waits for
the required license key to become available, do the following:
■
For NanoSim:
setenv EPIC_WAIT_LICENSE
■
For HSIM:
setenv EPIC_WAIT_LICENSE
setenv HSIM_WAIT_LICENSE
■
For XA:
setenv EPIC_WAIT_LICENSE
setenv XA_WAIT_LICENSE
■
For VCS:
Use the +vcs+lic+wait switch at compile time.
vcs +vcs+lic+wait ...
Required UNIX Paths and Variable Settings
To set the paths for NanoSim/HSIM/XA and VCS, do the following:
■
For NanoSim:
source NanoSim_installation_directory/CSHRC_ns
■
For HSIM:
set path = (HSIM_installation_directory/hsimplus/bin $path)
■
For XA:
source XA_installation_directory/CSHRC_xa
■
For VCS:
setenv VCS_HOME VCS_installation_directory
set path = ($VCS_HOME/bin $path)
See Example 44:
Example 44
Required UNIX paths and settings
setenv VCS_HOME /usr/synopsys/VCS/vcsmx_2009.06
set path = ($VCS_HOME/bin $path)
source /usr/synopsys/Nanosim/2009.06/CSHRC_ns
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Required Input Files
Using the 64-bit Binaries Currently, mixed-signal supports Solaris, Suse,
and Linux (AMD) 64-bit platforms. The binaries must be either 32-bit or 64-bit
for both the analog and the digital engines. It is not permitted to have a 32-bit
binary for one engine and a 64-bit binary for the other; such a combination
would result in incompatibility between the binaries and a compilation error.
To enable 64-bit binaries for mixed-signal, the VCS switch "-full64" must
be used:
vcs -ad -full64 ...
This tells VCS to use 64-bit binaries and also instructs the analog engine
(NanoSim, HSIM, or XA) to use 64-bit binaries as well (assuming that the 64-bit
binaries for the analog engine are installed and the environment variables for
the analog engine are set as described above).
Required Input Files
Before using the Verilog-SPICE flow, the following files must be in place:
■
Verilog netlist files
■
Verilog-A module files, if used
■
SPICE netlist files (including device model libraries)
■
Mixed-signal simulation control file
■
Command file
One of the following, depending on which analog engine is being used:
•
NanoSim config file
•
HSIM hsim.ini command file
•
XA command file
Compiling the Design
To compile the design, invoke the vcs command:
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Compiling the Design
vcs verilog_design_file(s) -ad [=mixed-signal_control_file]
[vcs options]
Example 45 shows that vcs compiles the design.v file with the -ad VCS
compile time option. It reads the default vcsAD.init file as the mixed-signal
control file. The simv simulation executable is created (if no errors occur
during the compilation).
Example 45
vcs compiles the design.v file with the -ad option
vcs design.v -ad
Example 46 shows that vcs compiles the design files listed in the
my_list.txt file with the -ad VCS compile time option. It reads the
my_setup.init file as the mixed-signal simulation control file. A simulation
executable, my_simv, is created, instead of the default simv executable.
Example 46
vcs compiles the my_list.txt file with the -ad option and
my_setup.init file
vcs -f my_list.txt -ad=my_setup.init -o my_simv
Example 47 is identical to Example 45, except for the-full64 option. This
option generates 64-bit simv executable instead of the default 32-bit.
Example 47
-full64 option
vcs design.v -ad -full64
After simv is generated, the simulation can be run using the following syntax:
simv [vcs run-time options]
Example 48 shows how to instruct VCS to generate a run time log file called
simv.log.
Example 48
Simulation is executed with the simv .log file
simv -l simv.log
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Running the Simulation in the Verilog-SPICE Flow
Running the Simulation in the Verilog-SPICE Flow
To synchronize the digital and analog events, ideally, both the analog and
digital engines should have the same time resolution value, where time
resolution is the smallest timestep the simulator is allowed to take.
■
By default, in the case of NanoSim and HSIM, the analog engine assumes
the smaller of the analog and digital time resolution. For example, if VCS
time resolution is 10ps and NanoSim/HSIM time resolution is 1ps, NanoSim/
HSIM will run with 1ps time resolution and VCS with 10ps time resolution.
■
XA does not have a predetermined time resolution. In XA the time resolution
is constantly optimized and adjusted for accuracy and performance during
simulaton.
As a general rule the analog time resolution cannot be greater than the digital
time resolution, because a loss of synchronization that could happen at run
time causing a run time error.
■
In NS-VCS, if the digital time resolution value is smaller than the analog time
resolution value, then NanoSim automatically overrides its own time
resolution with the smaller digital value so as not to violate the above rule.
■
In HSIM-VCS, such a violation will result in a compliation error and a
warning that the analog time resolution value cannot be smaller than the
digital time resolution value.
■
In XA_VCS, such a violation cannot occur, because of the adjustable time
resolution mechanism in XA.
Table 9 shows a few examples for NanoSim/HSIM and VCS time resolution
settings and the final values that are eventually used for analog and digital time
resolutions. XA is not mentioned in this table because it does not have the
notion of a predetermined time resolution.
Table 9
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Timestep synchronization behavior overview
NanoSim/HSIM
VCS
Time Resolutions
10 ps
10 ps
The analog and digital engines both use 10 ps time
resolution.
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Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE
Table 9
Timestep synchronization behavior overview
NanoSim/HSIM
VCS
Time Resolutions
10 ps
1 ps
■
■
1 ps
10 ps
In the case of NS-VCS, the VCS timestep overrides
the NS timestep so that both use 1 ps as a timestep
value.
In the case of HSIM-VCS a compilation error
occurs warning that the analog timestep cannot be
smaller than the digital timestep.
NS/HSIM and VCS use their own time resolution
values independently
■
■
NS/HSIM uses 1 ps
VCS uses 10 ps
Limitation:
All timestep values for NanoSim, HSIM, and VCS must be set to a value that
is a power of 10; for example 1ns, 10ps, 100ps.
Invoking the Interactive Mode with the UCLI Debugging Feature with
Verilog-SPICE
To enable the interactive mode during a mixed-signal simulation, it is
recommended to use the VCS UCLI (Unified Command Line Interface)
debugging feature.
Note:
The previous method of entering Ctrl-C during a mixed-signal simulation, or
using the simv -s option, invokes the now-obsolete CLI debugging feature
in VCS and is not recommended.
To invoke the UCLI interactive mode, first use the -debug or-debug_all
VCS compile option:
vcs -debug_all ...
Next, invoke the simv binary file by passing the -ucli option to it:
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Invoking the Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE
% simv -ucli
This switch stops the mixed-signal simulation at simulation time 0, and
generates the UCLI prompt:
ucli%
All UCLI commands can be used at this prompt, such as
ucli % run 10
which will run the simulation for 10 (VCS) units of time.
The VCS time unit is usually defined by the `timescale directive in the
Verilog code.
The following command prints all the digital sources that drive the given
node_name with the file and line numbers locating the contributing Verilog
code
ucli% drivers -full hier_node_name
The ucli% ace Analog Interactive Commands
You can use analog interactive commands at the UCLI prompt if they are
preceded by the ace command as shown in the following examples.
Example 49
NS-VCS: Using NanoSim pnc interactive command at the UCLI
prompt
ucli% ace pnc hier_node_name
Example 50 prints the node current for the given node in HSIM-VCS.
Example 50
Get node current for a given node in HSIM-VCS
ucli% ace ni hier_node_name
Example 51 shows how the XA interactive command "iprint_time" can be used
at the UCLI interactive prompt.
Example 51
The use of XA interactive command "iprint_time" in the UCLI
interactive prompt
ucli% ace iprint_time
For a complete list of the UCLI commands, please refer to the VCS Unified
Command Line Interface User Guide.
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DC Initialization
Note:
The analog simulation time cannot be advanced using the UCLI command.
The analog simulation time can only be advanced by advancing the digital
simulation time in UCLI. (See the VCS User Guide for more information.)
DC Initialization
Due to replacing existing SPICE subcircuits with Verilog modules, the analog
DC initialization in mixed-signal simulation may not be identical to the standalone analog simulation. For DC initialization condition-sensitive circuits, it
may be necessary to apply specific DC initialization condition values at certain
nodes to get expected simulation behaviors.
Recompiling the Design
In the current standalone version of VCS, the -Mupdate option is on by
default. As mixed-signal requires both the compile-time phase and run-time
phase to work seamlessly, do not compile incrementally.
When you modify any design files (Verilog, Verilog-A, or SPICE) or the mixedsignal control file:
■
Remove all of the intermediate files/directories generated by the previous
mixed-signal simulation by removing the simv.daidir and csrc
directories.
■
Restart the compilation.
Also, if you use the analog configuration commands to change the case
sensitivity in SPICE netlists, then you musr recompile the design before those
changes can take effect.
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5
Mixed-signal Simulation Output and Display in VerilogSPICE
This chapter describes how to generate separate digital and analog waveforms
or a unified output file in Verilog-SPICE and how to view them.
Overview
In Verilog-SPICE, simulation results can be
■
Generated separately for analog and digital signals.
■
Viewed with Signal Explorer, CosmosScope, or nWave.
Alternatively, the output can be
■
Generated as a single output file in VPD (VCD Plus Dump) or UOD (Unified
Output Display) format.
This chapter contains the following topics:
■
■
Capturing Analog and Digital Signals in the Output File(s)
•
Printing Analog Signals
•
Dumping Digital Signals
Generating a Unified Output
Capturing Analog and Digital Signals in the Output File(s)
To capture digital and analog signals in the output file(s), use two sets of
commands: one set for analog signals and another set for digital signals.
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Capturing Analog and Digital Signals in the Output File(s)
Printing Analog Signals
Any method of printing analog signals that is used in stand-alone analog
simulations for NanoSim, HSIM, or XA can also be used in the Verilog-SPICE
flow, such as:
■
The NanoSim print_node_v and print_node_i config commands
■
The NanoSim print_veriloga_var config command to capture VerilogA variables in the output
■
The $display, $strobe and $write functions within the Verilog-A code
to dump Verilog-A variables or voltage and current values on the screen
■
SPICE-specific print commands, such as the HSPICE .print and
.probe commands
■
The XA "probe_waveform_va -var *" config command to capture
Verilog-A variables in the output
■
The HSIM ".param hsimvaprintvar=1" parameter to capture VerilogA variables in the output
The format of the analog output file can be any one of the formats supported by
the analog engine, including .vpd, .fsdb and ASCII .out.
The following configuration commands must be used to set the output format
for analog signals:
■
For NanoSim
Use the set_print_format for=vpd | fsdb ... command inside
the NanoSim config file. See the NanoSim User Guide for more details.
■
For HSIM
Use the SPICE parameter .param HSIMOUTPUT=vpd to have HSIM
generate a VPD output. By default HSIM generates an fsdb file. See the
HSIMplus Reference Manual for more details.
■
For XA
Use the set_waveform –format fsdb|wdf|wdb|out|vpd command
inside the XA command file. See the XA User Guide for more details
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Capturing Analog and Digital Signals in the Output File(s)
Dumping Digital Signals
To dump digital signals in the output, use the common VCS methods,
including:
■
The $dumpvars() and $dumpfile() system tasks in the Verilog code to
generate VCD output.
■
The VCS +vcs+dumpvars+output_file_name compile time option to
capture and dump digital signals in the given output_file_name in VCD
format.
■
The $vcdpluson() system task in Verilog code to create VPD output. Use
this system task along with either the -PP or the -debug_pp VCS compile
option, which enable VPD dumping.
To capture a specific analog or digital signal within the hierarchy, the
hierarchical path to that signal must be specified. To obtain the hierarchical
path to all cells within the design, use the information in the hierarchy.rpt file
generated at compile time. This file is located under simv.msv directory. If the
VCS option "-o vcs_output" is used to specify a VCS output name other
than the default "simv", the file will be located under the
"vcs_output.msv" directory. See hierarchy.rpt on page 138 for more detail.
Example 52 shows an entry in the hierarchy.rpt file:
Example 52
hierarchy.rpt file entry
top(top).dut(addr4).x1<addr>.x3<inv20>
This shows, for example, that the hierarchical path to instance dut is
top.dut
and the hierarchical path to instance x3 is
top.dut.x1.x3
■
To print a net called net1 under dut, which is a digital instance, use (in the
Verilog code)
$dumpvars(0, top.dut.net1);
or
$vcdpluson(0, top.dut.net1);
■
To capture all signals under dut and two hierarchical levels below it, use
$dumpvars(3, top.dut);
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Capturing Analog and Digital Signals in the Output File(s)
or
$vcdpluson(3, top.dut);
■
To print a net called net2 under x3, which is an analog instance, use the
following commands:
•
For NanoSim
Use the print_node_v top.dut.x1.x3.net2 configuration
command.
•
For HSIM, XA, and NanoSim
Use the .print v(top.dut.x1.x3.net2)or the .probe
v(top.dut.x1.x3.net2)the SPICE command
■
To print everything under x3, use the following commands:
•
For NanoSim
Use the print_node_v
command.
•
top.dut.x1.x3.* configuration
For HSIM, XA, and NanoSim
Use the .print v(top.dut.x1.x3.*) or the .probe
v(top.dut.x1.x3) SPICE command.
For more details on the commands controlling the generation of output files and
dumping signals, please refer to the documentation for the specific simulator
(VCS, XA, HSIM, or NanoSim) .
Generating a Unified Output
There are two ways to generate a Unified Output file that will contain both
analog and digital waveforms:
■
Merged VPD output
■
Merged UOD Output
Merged VPD output
VPD is a binary waveform format that allows compact and efficient storage of
output data.
To generate a merged VPD file the following steps must be taken:
1. VCS must generate a VPD output
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Capturing Analog and Digital Signals in the Output File(s)
2. NanoSim/HSIM/XA must be instructed to generate an analog output in the
VPD format and then merge it with the digital VPD file. Use the following
commands to merge a VPD file containing both analog and digital signals:
•
For NanoSim
Use the set_print_format for=vpd
command:
•
For HSIM
Use the param HSIMOUTPUT=vpd
•
file=merge config
file=merge SPICE command:
For XA
Use the set_waveform –format vpd
command.
–file=merge config
The merged VPD file takes the name determined by VCS, which can be either
of the following:
■
The VCS default name
■
The file name specified by the $vcdplusfile() system task in Verilog
For more information on VPD file generation in VCS, see the VCS/VCSi User
Guide.
Merged UOD Output
UOD is a text waveform format that is generated through post processing of
digital and analog outputs. Because of its large size and many limitations
(mentioned below), Synopsys recommends that you use merged VPD instead
of UOD whenever possible. Only NanoSim and HSIM (not XA) can generate a
UOD file.
To generate a merged UOD file the following steps must be taken:
1. VCS must generate a VCD output (as described earlier).
2. NanoSim/HSIM must create output of .out format.
Use the following configuration commands to create a merge UOD file:
•
For NanoSim
Use either the set_print_uod out=uod or the set_print_uod
out=all configuration command:
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The choice of command depends on whether you intend to purge the
original VCD and OUT files after the merge (the first command) or to
keep them (the second command). See the NanoSim Command
Reference for more detail.
•
For HSIM
Use either the .param HSIMOUTPUT=uod1&out or the .param
HSIMOUTPUT=uod2&out SPICE command:
The choice depends on whether you intend to purge the original VCD
and OUT files after the merge (the first command) or to keep them (the
second command).
Limitations
84
■
Because UOD files are created through post processing of digital and
analog outputs at the end of the simulation, they cannot be generated in
interactive mode.
■
Viewing waveforms during simulation (marching waveforms) is not possible
using UOD files, because the file is not generated until after the completion
of the simulation.
■
UOD files are in ASCII format, which have a much larger size than a
compact binary format such as VPD. Synopsys recommends that you use
a merged VPD file, instead of a UOD file, to avoid generating a huge output
file and filling disk space.
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Simulation
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Using the VHDL/Verilog-SPICE Flow
6
This chapter provides the basic information needed to start simulating in the
VHDL/Verilog-SPICE flow—including installation and setup.
Overview
The Verilog/VHDL-SPICE flow provides a mixed-signal, mixed-HDL language
verification solution. Verilog/VHDL-SPICE enables simulating a design
described in SPICE (or other transistor-level description language that the
analog engine supports), Verilog-HDL (“Verilog”), and VHDL.
You must be familiar with the SPICE, Verilog, and VHDL languages, as well as
NanoSim, HSIM, or XA (depending on which analog engine is being used) as
well as VCS_MX. See the respective manuals for more information.
This chapter contains the following sections:
■
VHDL/Verilog-SPICE Flow Highlights
■
Known Limitations
VHDL/Verilog-SPICE Flow Highlights
In VHDL/Verilog-SPICE simulation, different parts of the design can be
simulated in SPICE, Verilog, or VHDL models.
VHDL/Verilog-SPICE supports both Verilog-top and VHDL-top flows. SPICEtop is also supported.
The following features are described in detail in this section:
■
Donut Configurations
■
Multiple Views
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VHDL/Verilog-SPICE Flow Highlights
•
View Selection for Cells Under a VHDL Parent
•
View Selection for Cells Under a Verilog Parent
•
View Selection for Cells Under a SPICE Parent
■
Real Port Support for VHDL
■
Interface A/D and D/A Conversion
■
Generating a Merged Output file for Analog and Digital Signals
Donut Configurations
NS-VCS-MX/HSIM-VCS-MX/XA-VCS-MX support VHDL-top, Verilog-top, and
SPICE-top design configurations.
There is no restriction on donut configurations. VHDL, Verilog or SPICE blocks
can each instantiate blocks of the other two formats without restriction. The
only requirement is for SPICE instantiations under VHDL; those SPICE cells
must also have a Verilog view available in order for the instantiation under
VHDL to take place.
Multiple Views
The blocks in the design can contain more than one view (for example, SPICE
and VHDL).
By default, VHDL/Verilog-SPICE selects the view for the multi-view cell that is
identical to the parent block view. If that view is not available, VHDL/VerilogSPICE selects the next-available view.
A particular view of a multi-view cell can also be selected explicitly. The method
of explicit view selection for a child cell depends on the view of the parent cell.
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VHDL/Verilog-SPICE Flow Highlights
View Selection for Cells Under a VHDL Parent
For a VHDL parent, a Verilog or VHDL view for a child cell can be selected by
pointing to the design library that contains that view. This can be done in a
number of ways.
■
By placing the VHDL use lib_name.cell_name constructs inside the
VHDL code that explicitly points to a particular cell in a particular library
■
By VHDL configurations that determine which "architecture" from what
"library" must be used for which instance or instances
■
During the elaboration of the design where a library name can be specified
from where the cells must be selected. The elaboration stage of design
compilation is described later in more detail.
For more details on VHDL and Verilog view selections, see the VCS-MX User
Guide.
To select the SPICE view for a child cell,
1. VHDL code must use one of the three methods described above to select
the Verilog wrapper, since SPICE cells instantiated under VHDL require a
Verilog view of the SPICE cell.
2. The use_spice mixed-signal command must be used to indicate that the
SPICE view of the cell will replace the Verilog wrapper.
View Selection for Cells Under a Verilog Parent
For a Verilog parent, a Verilog or VHDL view for a child cell can be selected
during design elaboration by specifying the design library name that contains
the desired view of the child. The elaboration stage of design compilation is
described later in more detail. For more details on VHDL and Verilog view
selections, please refer to the VCS-MX User Guide.
To select the SPICE view for a child cell, use the use_spice mixed-signal
command.
View Selection for Cells Under a SPICE Parent
For a SPICE parent, a Verilog view for a child cell can be selected by the
use_verilog mixed-signal command.
To select the VHDL view, use the use_vhdl mixed-signal command.
For details about the syntax of the use_spice and use_verilog mixedsignal commands, see Mixed-signal Control Commands. For details about the
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Known Limitations
syntax of the use_vhdl mixed-signal command, see Creating a Mixed-signal
Simulation Control File for VHDL/Verilog-SPICE.
Real Port Support for VHDL
VHDL/Verilog-SPICE supports the exchange of real values between VHDL and
SPICE blocks.
Refer to the Using a Verilog Wrapper section in Chapter 7, Mixed-signal
Simulation in the VHDL/Verilog-SPICE Flow, for details.
Interface A/D and D/A Conversion
In VHDL/Verilog-SPICE, the A/D and D/A conversions between SPICE and
Verilog follow the same rules as in the Verilog-SPICE flow. However, through
net optimization and drive strength conversion only take place for interface nets
between SPICE and Verilog, not for those between SPICE and VHDL.
Each time a signal crosses the SPICE-VHDL boundary, an A/D or D/A
component is instantiated.
The "a2d" and "d2a" commands that control A/D and D/A conversions (and
their thresholds) are the same as in the Verilog-SPICE flow.
Refer to the Interface A/D and D/A Signal Conversions in Chapter 2, Using
Mixed Signal Features, for more details.
Generating a Merged Output file for Analog and Digital Signals
VHDL/Verilog-SPICE can create merged VPD files and (in cases of NS-VCSMX and HSIM-VCS-MX) UOD files. Please refer to Chapter 10, Mixed
Simulation Output and Display in VHDL/Verilog-SPICE for further details.
Known Limitations
Some limitations exist in VHDL/Verilog-SPICE, due to the existing limitations in
the VCS-MX flow. See the VCS-MX User Guide for more details.
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Known Limitations
The known VHDL/Verilog-SPICE limitations are:
■
Verilog wrappers are required for instantiations of SPICE under VHDL
(Please refer to "Using a Verilog Wrapper" section below for further details).
However, donuts of Verilog and SPICE blocks, or SPICE instantiating
VHDL, do not require a Verilog wrapper.
■
To generate a unified output display (UOD) file for all VHDL, Verilog and
SPICE signals, the digital output must be in VPD format (VCD is not
supported). And the UOD format is not supported in XA-VCS-MX. You must
generate a VPD file for both Verilog and VHDL signals for the UOD to work
properly. A merged VPD file is also supported and is the recommended way
of generating a merged output file. Please refer to Chapter 10, Mixed
Simulation Output and Display in VHDL/Verilog-SPICE for further details.
■
The NanoSim set_sim_hierid configuration command is ignored.
■
Instance-based view selection under SPICE and Verilog is not supported.
This means that only the cell-based options of the use_verilog,
use_vhdl, and use_spice commands can be used. Instance-based view
selection under VHDL is possible if done through VHDL library selection
mechanism (that is, a VHDL configuration file or VHDL "use lib.entity"
directives in the code).
■
Thru-net optimization is not supported for interface nets between SPICE
and VHDL.
Note:
As an alternative, real type connections in VHDL can be used to
generate unidirectional connections of SPICE ports via VHDL.
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7
Mixed-signal Simulation in the VHDL/Verilog-SPICE Flow
This chapter provides the instructions on how to prepare the files (input data) to
run a mixed-signal simulation with NS-VCS-MX/HSIM-VCS-MX or XA-VCS-MX.
Overview
Some of the issues that require attention for VHDL/Verilog-SPICE mixed-signal
simulation are identical to those for the Verilog-SPICE.
Those issues are:
■
Netlist-related
■
Port-related
For a description of the steps to take to ensure that these issues are
addressed, refer to the Netlist-related Issues and Port-related Issues sections
in Chapter 3, Mixed-Signal Simulation in the Verilog-SPICE Flow.
Figure 16 shows the recommended steps to take to prepare files for NanoSim/
HSIM/XA-VCS-MX mixed-signal simulation.
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Input Netlist Files
Figure 16
Flow for preparing a mixed-signal simulation
This chapter contains the following sections:
■
Input Netlist Files
•
VHDL and Verilog Descriptions
■
Using a VHDL Setup File
■
Using a Verilog Wrapper
■
Creating a Mixed-signal Simulation Control File for VHDL/Verilog-SPICE
•
The use_vhdl Command
•
The use_verilog and use_spice Commands
Input Netlist Files
Ensure that all the netlist files that model each block in the design are present.
The required files for analog models and blocks in the design are:
94
■
Transistor-level descriptions (or SPICE netlists)
■
Device model libraries (can be included inside the SPICE netlist)
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Input Netlist Files
Note:
The NanoSim/HSIM/XA configuration commands for analog parts of the
design are not required, but often used.
The required files for the digital components of the design are
■
VHDL and/or Verilog descriptions of the digital blocks
■
Dummy Verilog wrappers for SPICE blocks instantiated under VHDL
■
VHDL setup file
■
Mixed-signal simulation control file
Details for each of these files follows.
VHDL and Verilog Descriptions
Here are the issues to consider regarding the VHDL and Verilog netlists:
■
A VHDL block can contain a real data type port, as long as that port is meant
for data exchange between two VHDL blocks, or a VHDL and SPICE block.
■
In the case of VHDL instantiating SPICE, where a Verilog wrapper is
required for SPICE, the Verilog port that corresponds with the VHDL real
port must be defined as wreal.
■
The VHDL real ports and the Verilog wrapper wreal ports cannot have the
direction inout. These ports must have an input or output direction.
■
Cross-module reference (XMR) across digital/analog boundary is only
supported between Verilog and SPICE as explained in the Verilog-SPICE
section of this document. Cross referencing an analog node from inside
VHDL is not supported.
■
A mixed-net cannot connect to Verilog ports that are connected to bidirectional pass switches (tran, rtran, tranif0, rtranif0,
tranif1, and rtranif1)
■
A mixed-net cannot connect to Verilog jumper ports (see Example 53)
Example 53
Jumper port sample
module jumper (a, a);
inout a;
. . .
endmodule
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Using a VHDL Setup File
Transistor-level Descriptions
For the SPICE netlists, keep the following points in mind:
■
HSPICE and VHDL netlist formats are case-insensitive, but Verilog is casesensitive.
So the best practice is to create all subcircuit, port, and signal names
consistently, in either lower-case or upper-case, across all SPICE, Verilog
and VHDL files.
■
Unused ports must be removed from the subcircuits that are going to be
instantiated under VHDL, and a Verilog wrapper is generated for them.
NanoSim removes those ports by default. The corresponding ports in the
Verilog wrapper modules must also be removed. You will see a WARNING
and ERROR message when NanoSim removes the port:
WARNING: mixed node “net10” not found.
ERROR: Unable to find nanosim id for net ‘net10’
interface signal mismatch
Using a VHDL Setup File
VCS-MX uses a VHDL setup file named synopsys_sim.setup to set up and
configure the environment for VHDL and mixed-HDL designs. Multiple copies
of this setup file can be located in the VCS-MX installation directory, in your
home directory, or in your run directory. VCS-MX searches these locations—in
that order—and the last file found overrides any previously found file.
This setup file maps VHDL logical library names to physical directories, set
search paths, set the VHDL simulation time base and time resolution, and
assign values to some simulation control variables.
One of the most frequent uses of the VHDL setup file is to map logical VHDL
libraries to physical host directories.
In VHDL, design blocks can be analyzed and stored in one or more logical
libraries. This capability offers great flexibility in maintaining multiple versions of
a VHDL block by analyzing each version into a different library.
The VHDL setup file allows defining multiple logical library names and mapping
them to their actual physical location.
By default, all VHDL blocks are analyzed and stored in the WORK logical library.
The default physical directory for this library is ./WORK
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For more information on the VCS-MX setup file, please refer to the VCS-MX
User Guide.
Example 54 shows a sample synopsys_sim.setup file. Here, rtl_lib
and gate_lib (two logical libraries) and their physical locations are defined.
Also, the WORK default logical library is mapped to the rtl_lib library.
Example 54
VHDL setup file
WORK > rtl_lib
rtl_lib: ./rtl_library
gate_lib: ./gate_library
TIMEBASE=ns
TIME_RESOLUTION=10ps
Using a Verilog Wrapper
If in the design there is a SPICE block instantiated under VHDL, a dummy
Verilog wrapper for the SPICE block must be generated.
This dummy module must have the same name, number of ports and port
names as the SPICE cell. The body of the dummy module can be empty, as
VHDL/Verilog-SPICE does not read the body of that module if it is used as a
dummy wrapper for SPICE.
A dummy Verilog wrapper is not required for any type of Verilog or SPICE
donuts, nor for SPICE instantiating VHDL.
If a Verilog description already exists for the SPICE block, use the existing
Verilog module as the Verilog wrapper. If not, the wrapper can be created
either manually or by using the autowrapper utility—see section Using the
Autowrapper Utility in Chapter 9, “Creating Verilog Wrappers in VHDL/VerilogSPICE,” for the autowrapper usage.
If real ports are used in the VHDL description, ensure that a wreal declaration
is made for the same ports in the Verilog wrapper module (also include the
-realport switch when calling vlogan, which is discussed later in this
document). When using a wreal declaration, only input and output ports
are allowed—inout ports are not supported.
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Using a Verilog Wrapper
See Example 55 for a wreal declaration file sample.
Example 55
wreal declaration file
//Verilog wrapper for using real ports
module test (a, b);
input a;
wreal a;
output b;
wreal b;
/* in addition to module name, port name, and directions,
wreal declaration is also required */
end module
Note:
Using real ports can result in a simulation performance penalty; specifically,
real values passed from the analog engine to VHDL. Be aware that this,
when combined with smaller time resolution values, can cause slower
simulation runs.
Example 56 shows a SPICE subcircuit, its instance in the VHDL description,
and the required corresponding Verilog wrapper.
Example 56
SPICE subcircuit
*
.subckt chargepump_com
+ com_inv<3> com_inv<2> com_inv<1> com_inv<0>
+ com_rsh<3> com_rsh<2> com_rsh<1> com_rsh <0>
+ clk
* we skip the subckt description
.ends
Example 57 shows the instantiation of the SPICE block described in example
53 in the VHDL description. The sig_inv, sig_rsh and sig_clk signals are
defined in the VHDL block and connect to the chargepump ports.
Example 57
I3
98
Instance of Example 56 (SPICE subcircuit)
:
chargepump_com
port map (
com_inv=> sig_inv(3 downto 0),
com_rsh=> sig_rsh(3 downto 0),
clk
=> sig_clk
);
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Example 58 is a Verilog wrapper that must be generated to allow the
instantiation of the SPICE cell under VHDL.
Example 58
Verilog wrapper
'timescale 1ns/10ps
module chargepump_com(com_inv, com_rsh, clk);
input [3:0] com_inv, com_rsh;
input clk;
// The body of the Verilog wrapper can
// be empty. And if it is not, its content
// will be completely ignored.
endmodule
Creating a Mixed-signal Simulation Control File for VHDL/VerilogSPICE
In VHDL/Verilog-SPICE, as in Verilog-SPICE, a mixed-signal control file must
be created. This file, called by -ad=setup_file_name at compile time,
contains mixed-signal control commands which, among other things, controls
the view selection of multi-view cells and A/D and D/A conversions.
All the mixed-signal simulation commands supported by Verilog-SPICE (as
described in Creating a Mixed-signal Simulation Control File in Chapter 3,
Mixed-Signal Simulation in the Verilog-SPICE Flow) are also supported in the
VHDL/Verilog-SPICE flow—with the following exceptions:
■
The use_vhdl Command (view-selection command), is added in VHDL/
Verilog-SPICE. This command is used to select the VHDL view of a multiview cell instantiated under SPICE.
■
The use_verilog Command must be used to select the Verilog view of a
multi-view cell instantiated under SPICE.
■
The use_spice Command must be used to select the SPICE view of a multiview cell instantiated under Verilog. This command alone is not sufficient to
select a SPICE view for a cell instantiated under VHDL. The conventional
VHDL methods such as configuration files or explicit "use lib.cell_name"
must be used to select the Verilog wrapper for the SPICE block in addition
to using the "use_spice" command.
■
All view selection commands can only be cell-based. The instance-based
view selection is not currently supported for the use_vhdl, use_verilog
or use_spice mixed-signal commands. Instance-based view selection is
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only possible for cells instantiated under VHDL, when VHDL native methods
are used (that is, through use lib_name.cell_name in VHDL code or by
using VHDL configurations).
Example 59 is a sample mixed-signal control file for the NS-VCS-MX file.
Example 59
use_spice -cell chargepump;
use_verilog –module counter;
use_vhdl –cell d_flop;
use_vhdl –cell rtl_lib.mux_1;
choose nanosim -n spice_cells.spi -C cfg;
bus_format <%d>;
The mixed-signal control file for HSIM and XA will look the same except that
the choose nanosim line must be replaced with choose hsim or choose
xa.
The use_vhdl Command
The use_vhdl command selects the VHDL view of a multi-view cell
instantiated in a SPICE block.
See the following syntax (three formats to choose from), arguments, and
description:
use_vhdl –cell entity
use_vhdl –cell [Library.]entity[(arch)]
use_vhdl –cell [Library.]configuration
See Table 10 for the use_vhdl argument descriptions.
Table 10
100
use_vhdl arguments
Argument
Description
entity
Identifies the name of the VHDL entity being
referenced (Required argument)
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Table 10
use_vhdl arguments
Argument
Description
Library
Explicitly specifies a specific VHDL library where
you have previously analyzed the VHDL
entity.
By default, use_vhdl searches the default
WORK logical library for the entity name.
(Optional argument)
arch
Explicitly selects the architecture of the
choice, if you have analyzed multiple
architectures for the VHDL entity into a
library. (Optional argument)
configuration
Points to the configuration, if you have
analyzed a VHDL configuration to define the
entity-architecture association for a given
VHDL entity. (Optional argument)
The use_verilog and use_spice Commands
The syntax for the use_spice and use_verilog commands remain the
same as in Verilog-SPICE, with the exception that instance based view
selection is not supported for these commands. Refer to the use_verilog
and use_spice command descriptions in the Verilog-SPICE section of this
manual.
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Running a Mixed-Signal Simulation in VHDL/Verilog-SPICE
8
This chapter provides information for running an NS-VCS-MX, HSIM-VCS-MX,
or XA-VCS-MX mixed-signal simulation.
Overview
To run a VHDL/Verilog-SPICE mixed-signal simulation, you must first be
familiar with stand-alone VCS-MX and NanoSim/HSIM/XA simulations.
This chapter contains the following sections:
■
Installation Requirements
■
Setting up the NS-VCS-MX Simulation Environment
■
Required Input Files
■
Compiling the Netlists
■
■
•
The Analysis Stage
•
The Elaboration Stage
Running the Simulation in VHDL/Verilog-SPICE
•
Simulation Time Resolution in VHDL/Verilog-SPICE
•
Interactive Simulation with UCLI using NS-VCS-MX
Back-annotation
Installation Requirements
In order to use VHDL/Verilog-SPICE, both the analog engine (NanoSim, HSIM
or XA) and VCS-MX must be installed.
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Setting up the NS-VCS-MX Simulation Environment
Check the respective release notes for the compatibility table showing the
compatible versions of NanoSim/HSIM/XA and VCS-MX. The compatibility
table also specifies the utilities (such as "cc", "gcc" and "ld") and the versions
that are required for each release.
Generally, only one version of NanoSim/HSIM/XA and one version of VCS-MX
are certified for each VHDL/Verilog-SPICE release. (Non-recommended
versions are not guaranteed to be compatible with each other. Refer to the
Installation Requirements section of each manual for installation specifications.
Setting up the NS-VCS-MX Simulation Environment
Running a mixed-signal simulation requires setting up paths and environment
variables for both NanoSim/HSIM/XA and VCS-MX.
Here is how to set the paths:
■
For NanoSim
source NanoSim_installation_directory/CSHRC_ns
■
For HSIM:
set path = (HSIM_installation_directory/hsimplus/bin $path)
■
For XA:
source XA_installation_directory/CSHRC_xa
■
For VCS-MX
setenv VCS_HOME VCS-MX_installation_directory
set path = ($VCS_HOME/bin $path)
License
Both LM_LICENSE_FILE and SNPSLMD_LICENSE_FILE can be used to
specify the license file location.
setenv LM_LICENSE_FILE Location_of_License_File
or
setenv SNPSLMD_LICENSE_FILE Location_of_License_File
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Required Input Files
See the following example to set up the environment to run NS-VCS-MX on the
linux platform:
setenv VCS_HOME /usr/synopsys/VCS-MX
set path = ($VCS_HOME/bin $path)
source /usr/synopsys/Nanosim/CSHRC_linux
setenv LM_LICENSE_FILE 26585@synopsys:$LM_LICENSE_FILE
Required Input Files
Here are the required files for a VHDL/Verilog-SPICE simulation:
■
All netlist files
•
■
VCS-MX setup and run-time files
•
■
VHDL, Verilog, SPICE, Verilog-A, etc.
synopsys_sim.setup (optional), run-time command file (optional)
Mixed-signal simulation control file
Compiling the Netlists
In the VHDL/Verilog-SPICE flow, simulation is performed in three steps. The
compilation comprises the first two steps.
1. Design Analysis
2. Design Elaboration
3. Design Simulation
During Design Analysis, the syntax of Verilog and VHDL files are verified and
intermediary files are generated that are used during Design Elaboration. Any
syntax errors in Verilog or VHDL netlists are flagged during this step.
During Design Elaboration, the design hierarchy is built based on the
information obtained during the Design Analysis step. At this stage, incorrect
port connectivity or missing definitions for instantiated blocks in Verilog, VHDL
or SPICE are identified and flagged.
Figure 17 demonstrates the two stages and the commands required for each
stage.
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Compiling the Netlists
Figure 17
Netlist compilation stages
The Analysis Stage
The first step in the design compilation is the analysis of the Verilog and VHDL
netlists. To analyze Verilog and VHDL files, the vlogan and vhdlan utilities
are used, respectively. It is recommended that the analysis of the Verilog files
be completed before the VHDL files.
The vlogan Utility
To analyze Verilog files, the vlogan command must be used. The syntax of the
command follows:
vlogan [options] verilog_file(s)
106
Argument
Description
-f
verilog_list_file_name
Specifies a file that contains a list of paths to
Verilog source files and compile-time options
-help
Displays a succinct description of the most
commonly used options
-l log_file
Specifies a log file where VCS-MX records
compilation messages
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Argument
Description
-q
Suppresses compiler messages
-realport
Use this option if among the Verilog files passed
to vloganand there is one or more Verilog
wrappers for SPICE that contains a wreal port.
Such wreal ports must be defined in the
wrapper when a SPICE port connects to a VHDL
signal of type real.
-timescale=time_unit/
time_precision
Enables you to specify the timescale for the
source files that do not contain the ‘timescale
compiler directive, and precedes the source files
that do contain the ‘timescale compiler
directive.
-v library_file
Specifies a Verilog library file to search for
module definitions.
-y library_directory
+libext+ext
Specifies a Verilog library directory to search for
module definitions.
-work logical_library
Specifies the logical library where the
intermediate files are written into. The physical
location of logical libraries are defined inside the
synopsys_sim.setup file. If not given, by
default the intermediate files are stored in the
logical WORK directory.
+incdir+directory
Specifies the search directories to search for files
specified with the ‘include compiler directive.
You can specify more than one directory,
separating each path name with the plus (+)
character.
+v2k
Enables the use of new Verilog constructs in the
1364-2001 standard.
For a complete list of the command-line options for vlogan, refer to the VCS®
MX/VCS MXi User Guide.
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Compiling the Netlists
Example 60 shows the calling of vlogan, where the two Verilog netlist files
cell1.v and cell2.v are
passed for analysis.
Example 60
% vlogan
cell1.v
cell2.v
Because the –work option is not given, the intermediary files generated during
analysis are stored in the logical WORK directory—the physical location of which
is determined in the synopsys_sim.setup file.
Example 61 shows that instead of passing the names of individual Verilog files,
option -f passes the file_list file to vlogan, which includes the names of
the Verilog files to be analyzed. The intermediary files are also generated
during the analysis of the Verilog files and are written into the vlog_lib logical
library. The physical location of this logical library must be defined in the
synopsys_sim.setup file.
Example 61
% vlogan –f file_list -work vlog_lib
Example 62 shows how to analyze a Verilog wrapper file that contains one or
more wreal ports. The -realport option must be used.
Example 62
% vlogan –realport wrapper1.v
Here, vlogan is called to analyze the verilog file wrapper1.v. Also the
option -realport is used so that the ports defined as wreal in the
wrapper1.v file can be handled by vlogan; otherwise, analysis fails and an
error message is generated.
If there are no wreal ports defined in the Verilog files passed to vlogan, using
the -realport option has no impact on the analysis.
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Compiling the Netlists
The vhdlan Utility
To analyze VHDL files, the vhdlan command must be used. The syntax of the
command follows:
vhdlan [options] vhdl_file(s)
Argument
Description
-f optionsfile
Specifies an optionsfile that expands vhdlan
command-line options.
-help
Displays a succinct description of the most
commonly used options.
-version
Prints the version number of vhdlan and exits
without running analysis.
-work logical_library
Specifies the logical library where the intermediate
files are written into. The physical location of logical
libraries are defined inside the
synopsys_sim.setup file. If not given, by default
the intermediate files are stored in the logical WORK
directory.
-output outfile
Redirects standard output from VCS-MX analysis
(that usually goes to the screen) to the file you
specify as outfile.
For a complete list of the command-line options for vhdlan, refer to the VCS®
MX/VCS MXi User Guide.
Example 63 shows the calling of vhdlan, where the test1.vhd and
test2.vhd files are passed for analysis:
Example 63
% vhdlan test1.vhd test2.vhd
Because the -work option is not used, the intermediary files generated during
analysis are stored in the WORK logical library, the physical location of which is
determined in the synopsys_sim.setup file.
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Compiling the Netlists
Example 64 shows the file testbench.vhd is analyzed and the intermediary
files are stored in the vhd_lib logical library. The physical location of
vhd_lib must be defined inside the synopsys_sim.setup file.
Example 64
% vhdlan –work vhd_lib testbench.vhd
The Elaboration Stage
Once all the VHDL and Verilog blocks in the design (including the Verilog
wrappers) are analyzed, the next step is to elaborate those blocks, as well as
the SPICE cells, as the final stage of the compilation.
To elaborate the design, the vcs command is used with the following syntax:
vcs -ad[=initFile]
ElabOptions
110
topConfig | topModule| topEntity
Argument
Description
-ad [=initFile]
Enables the mixed-signal feature. If -ad is used
alone, the mixed-signal control file name is
assumed to be vcsAD.init. If the file name is
different, it must be given with the =initFile
option.
topConfig |
topModule| topEntity
Defines the top-level cell in the design. The toplevel cell can be defined in one of three ways:
topConfig
Defined by the VHDL configuration name that is
defined for the top-level cell, if the design is
VHDL-top.
topModule
Defined by the name of the top-level module, if
the design is Verilog-top.
topEntity
Defined by the name of the top-level entity, if the
design is VHDL-top.
ElabOptions
Some of the useful VCS options that can be used
during elaboration are listed as follows. For a
complete list of all VCS options, refer to the
VCS® MX/VCS MXi User Guide.
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Compiling the Netlists
Argument
Description
-debub
Enables DVE and UCLI debugging. This option
does not enable line-stepping.
-debub_all
Enables DVE and UCLI debugging, including
line-stepping.
-debug_pp
Enables both VPD generation and UCLI
debugging.
One of these two options (-debug_pp or -PP)
are needed in combination with a $vcspluson
system task embedded in the Verilog code to
generate a unified VPD output file for both
Verilog and VHDL signals.
Enables VPD generation.
-PP
One of these two options (-debug_pp or -PP)
are needed in combination with a $vcspluson
system task embedded in the Verilog code to
generate a unified VPD output file for both
Verilog and VHDL signals.
-o executable_name
Enables you to give the executable a different
name.
By default, simv is the name of the executable
generated by VCS.
-R
Runs the simulation immediately when the
compilation is successfully completed.
-ucli
Enables UCLI debugging and forces the
simulation to start in UCLI mode at run time.
Example 65 shows a sample compilation script for XA-VCS-MX containing
analysis and elaboration commands for a design with VHDL, Verilog and
SPICE components. The design is assumed to be VHDL-top, and the tb.vhd
and blk_1.vhd files contain all of the VHDL definitions, the blk_2.v and
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blk_3.v files contain all of the Verilog definitions, and the all_spice.spi
file contains the SPICE definitions.
Example 65
vlogan blk_2.v
blk_3.v
vhdlan tb.vhd blk1.vhd
vcs -ad=setup.init testbench -ad_xa
testbench is the name of the top-level entity.
Because the -work option is not present, the default logical WORK library is
used to analyze the digital blocks into. The mixed-signal control file "setup.init"
file can look like Example 66:
Example 66
choose xa –n all_spice.spi –c xa.cmd;
use_spice –cell counter ddr_flop;
bus_format <%d>;
Because counter and ddr_flop are multi-view cells, the "use_spice"
command has been used to explicitly specify that the SPICE view of those cells
must be used.
Running the Simulation in VHDL/Verilog-SPICE
To run the mixed-signal simulation, the executable generated during the
compilation must be run. By default, simv is the executable, unless the default
name is overridden by the VCS -o option. The syntax for running simv
follows:
% simv
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[runtime options]
Argument
Description
-include [VCS-MX
command file_name]
Specifies a file that contains VCS-MX
commands to be run during run-time.
-l [log_file_name]
Generates a run-time log file.
-ucli
Starts the simulation in the UCLI interactive
mode. The UCLI feature must have been
enabled at compile time by passing the -ucli
option to VCS.
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Argument
Description
-version
Prints the version of the VCS-MX used in
compilation.
In Example 67, simv generates a simv.log run-time log file.
Example 67
% simv –l simv.log
In Example 68, the -ucli option starts the simulation in the UCLI interactive
mode (assuming that the -debug or -debug_all option was also used during
VCS compilation).
Example 68
%simv -ucli
In Example 69, a command file is passed to simv at run time.
Example 69
% simv –include command.txt
The command.txt file can appear as follows:
run 1000
echo “Simulation run for 1000 time-units”
quit
Simulation Time Resolution in VHDL/Verilog-SPICE
The time resolution rules and requirements for in VHDL/Verilog-SPICE
simulation are identical to those for Verilog-SPICE simulation. Refer to the
section Running the Simulation in the Verilog-SPICE Flow in Chapter 4,
Running a Mixed-Signal Simulation in the Verilog-SPICE Flow.
Interactive Simulation with UCLI using NS-VCS-MX
The simulation with UCLI rules and requirements for NS-VCS-MX are identical
to those for an NS-VCS simulation. Refer to the section Invoking the
Interactive Mode with the UCLI Debugging Feature with Verilog-SPICE in
Chapter 4, Running a Mixed-Signal Simulation in the Verilog-SPICE Flow.
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Back-annotation
Back-annotation
The same rules governing back-annotation in Verilog-SPICE apply in VHDL/
Verilog-SPICE as well.
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9
Creating Verilog Wrappers in VHDL/Verilog-SPICE
This chapter describes how to use the autowrapper utility, which can generate
Verilog wrappers for SPICE subcircuits instantiated under VHDL.
Overview
The autowrapper generates an empty Verilog module for a given SPICE
subcircuit.
This chapter contains the following sections:
■
The VHDL/Verilog-SPICE Autowrapper Utility
•
Using the Autowrapper Utility
The VHDL/Verilog-SPICE Autowrapper Utility
As described in the previous chapters, a SPICE subcircuit cannot be directly
instantiated in a VHDL or a Verilog block. A Verilog wrapper corresponding to
the subcircuit must be initially created. The wrapper can be manually created or
automatically created using the autowrapper utility.
After the wrapper has been created, you have to change the port direction in
the wrapper.v file. Port direction does not pertain to a SPICE subcircuit, as all
ports are considered inout. The autowrapper utility specifies all ports with
inout direction. You must change the port direction in the wrapper.v file to
assign the actual direction to each port (such as input, output, or inout).
Although designating the directions of all ports as inout works, it could hinder
(slow) the run time because inout mixed-nets can lead to many successive
back-and-forth D/A and A/D conversions.
The autowrapper utility creates wrapper.v and wrapper.log files (by default).
The wrapper.v file contains all Verilog wrapper modules corresponding to all
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subcircuits that are defined in the SPICE file. For instance, if there are four
subcircuits specified in the SPICE file, this utility creates four Verilog wrapper
modules in the wrapper.v file.
See the following syntax, example, and description:
autowrapper -n[fmt] netlist_file(s)_name
[-bus_fm bus_format][-cell subckt_name(s)]
[-xcell subckt_name(s)] [-file netlist_file_name]
[-o output_file_name][-case s|S|l|L|u|U]
See the following example:
autowrapper -nspice test.spi
For instance, a SPICE file contains the following subcircuit, as shown in
Example 70.
Example 70
SPICE subcircuit file sample
*spice sub circuit definition example
.subckt inv a zn
m1 zn a vdd vdd p 1 0.35
m2 zn a gnd gnd n 2 0.35
.ends
The autowrapper utility creates a Verilog wrapper, as shown in Example 71.
Example 71
Verilog wrapper module file sample
//generated verilog wrapper example
module inv (a, zn);
inout a;
inout zn;
endmodule
All ports are defined as inout in module inv. You must change port
directions; for example, a as input and zn as output.
For a description of the autowrapper utility options, see Table 11.
Table 11
116
autowrapper Utility Description
Utility option
Description
-n[fmt]
netlist_file(s)_name
Specifies the file name (in any NanoSimsupported format) to be read-in. (Required
option)
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Table 11
autowrapper Utility Description (Continued)
Utility option
Description
-bus_fm bus_format
Enables the recognition of bus signals (with a
specified bus format) for the input netlist file.
The default bus format is [%d], but it can be
set to any valid node name symbols. See
Table 12 .
-cell subckt_name(s)
Specifies the subcircuits, in the netlist file, that
must be converted into Verilog wrapper
modules. (All other subcircuits are ignored.)
The module name uses the same casesensitivity as the subckt_name.
If the defined subcircuit is not detected in the
file, the following WARNING message is
displayed:
There is no subckt .... in
nanosim_netlist_name.
-xcell
subckt_name(s)
Specifies the subcircuits that must NOT be
converted into Verilog wrapper modules. (All
other subcircuits are converted into Verilog
wrapper modules.) This option excludes
specified subcircuits, and is case-insensitive.
If the defined subcircuit is not detected in the
file, the following WARNING message is
displayed:
There is no subckt .... in
nanosim_netlist_name.
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Table 11
autowrapper Utility Description (Continued)
Utility option
Description
-file
netlist_file_name
Defines a list of subcircuits that must be
converted into Verilog wrapper modules.
These subcircuits are defined in the
netlist_file. The netlist_file must
have one subcircuit name per line. You can
define the excluded subcircuit(s) commenting
out the subcircuit names with a semicolon (;),
as in the following example:
File:name.txt
;inv
;xor
;f_add
adder
-o output_file_name
Defines the name of the output file name where
the Verilog wrappers are written, and sets the
.log file prefix.
If the same file exists in the output directory, it
is overwritten without a WARNING message.
-case s|S|l|L|u|U
-case s or -case S maintains
case-sensitivity for the port names
-case l or -case L generates lowercase
port names (default)
-case u or -case U generates uppercase
port names
Table 12
118
-bus_fm bus_format options
bus signal
bus format
A[0]
[%d]
B_1
_%d
C<2>
<%d>
D_3_
_%d_
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Table 12
-bus_fm bus_format options
bus signal
bus format
E{4}
{%d}
F5
%d
G6_
%d_
For example, the _%d bus format directs the autowrapper utility to recognize
bus signals defined as A_1, A_2 ..., A_n.
Using the Autowrapper Utility
See the following guidelines about using the Autowrapper utility:
■
If an inout port is connected to the register type net, VCS generates an
error message and stops compilation. In Verilog, a register type net should
be connected to an input port—not an inout port. The autowrapper
utility only generates inout ports, since direction does not exist in SPICE
netlists. Therefore, before compiling, edit the wrapper.v file and specify the
correct port direction.
■
The autowrapper utility generates one Verilog wrapper module per
subcircuit; therefore, it can generate unnecessary Verilog wrappers. Some
of these modules might be using the same module name as other Verilog
modules in the original Verilog code. If this occurs, VCS generates an error
message and stops compilation. Therefore, before compiling, check the
module names in the Verilog wrapper file. If the name is used elsewhere in
the Verilog description, and the generated Verilog wrapper is not needed,
remove the module from the Verilog wrapper file. Example 72 displays the
SPICE definition for subcircuits adder4 and inv, and how a Verilog
wrapper can be generated.
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Example 72
Wrapper module for adder4 and inv
.subckt adder4 a[3] a[2] a[1] a[0] b[3] b[2] b[1] b[0]
+ clk cin cout
xinv1 clk clkn inv
…
.ends
.subckt inv a zn
m1 zn a vdd vdd p 1 0.35
m2 zn a gnd gnd n 2 0.35
.ends
You run the following:
autowrapper -nspi netlist -o net.v
The content of file net.v is shown in Example 73:
Example 73
net.v file sample
module adder4 (a, b, clk, cin, cout);
inout [3:0] a;
inout [3:0] b;
inout clk;
inout cin;
inout cout;
endmodule
module inv (a, zn);
inout a;
inout zn;
endmodule
The inv module is unnecessary here and can create confusion if another
inv module exists in the original Verilog code. You must remove the inv
module description from the net.v file.
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■
Verilog is case-sensitive. SPICE is not case-sensitive. The autowrapper
utility maintains case-sensitivity for module names; but, you must use the
-case option if you want to maintain case-sensitivity for port names.
■
No timescale information in the wrapper file is generated by the
autowrapper utility. Therefore, the wrapper file must be placed at the end
of the Verilog file’s compilation input:
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vcs -ad a.v c.v d.v wrapper.v
■
If the signal in the SPICE netlist is bus- or array-type, it must be expanded.
The autowrapper utility automatically generates bus- or array-type
signals in the Verilog wrapper file (original SPICE subcircuit), as shown in
Example 74. Refer to Table 11 for details.
Example 74
Bus- or array-type signals in a Verilog wrapper (original SPICE
subcircuit)
.subckt mem DATA[3], DATA[2], DATA[1], DATA[0],
+
WL[0], WL[1], WL[2], WL[3],
+
WL[4], WL[5], WL[6], WL[7],
+
R_WB, RAM_ENB
.ends
The autowrapper utility automatically forms bus- or array-type signals in
the Verilog wrapper file, as shown in Example 75. Refer to Table 11 for
details.
Example 75
Bus- or array-type signals in a Verilog wrapper (generated Verilog
wrapper module)
module mem (data, wl, r_wb, ram_enb);
inout [3:0] data;
inout [0:7] wl;
inout r_wb;
inout ram_enb;
endmodule
■
If special characters and Verilog-specific keywords are used for the signal or
subcircuit name, the name is assigned a backslash ( \ ) leading character.
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In addition, a space is inserted at the end of the name in the Verilog wrapper
file, as shown in Example 76.
Example 76
Backslash leading character and space in Verilog wrapper
module \inverter.test ( \if , \1 , \2 );
inout \if ;
inout \1 ;
inout \2 ;
endmodule
module vsources (\0 , \B#1 , B, \CE# , CLK, DECOUT, \Q^ , XDPD,
\b#2 );
inout
\0 ;
inout
\B#1 ;
inout [5:5] B;
inout
\CE# ;
inout
CLK;
inout [7:7] DECOUT;
inout
\Q^ ;
inout [7:7] XDPD;
inout
\b#2 ;
endmodule
■
If subcircuit ports in a bus are randomly ordered in the transistor netlist, the
autowrapper utility cannot function properly.
See Example 77 for a sample (unsupported) file.
Example 77
Subcircuit ports in bus format
.subckt p7ibptacddecwr clk wlw0[0] wlw0[10] wlw0[11] wlw0[12]
+wlw0[13] wlw0[14] wlw0[15] wlw0[1]
wlw0[2]
+wlw0[3] wlw0[4] wlw0[5] wlw0[6]
wlw0[7]
+wlw0[8] wlw0[9] wlw1[0] wlw1[10]
wlw1[11]
+wlw1[12] wlw1[13] wlw1[14] wlw1[15]
wlw1[1]
+wlw1[2] wlw1[3] wlw1[4] wlw1[5]
wlw1[6]
+wlw1[7] wlw1[8] wlw1[9] writeadd[0] writeadd[1]
+writeadd[2]
writeadd[3]
writeen[0] writeen[1]
.ends
■
Nested subcircuits in the SPICE netlist are supported. A module is
generated for the nested subcircuit; the module name is made of the nested
subcircuit name preceded by the parent subcircuit name, itself preceded by
a backslash character (\).
A nested subcircuit sample is shown in Example 78.
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Example 78
Nested subcircuit (original SPICE subcircuit)
.subckt s in out
.subckt inv13 in out
.ends inv13
.ends s
An automatically generated Verilog wrapper module sample is shown in
Example 79.
Example 79
Nested subcircuit (Verilog wrapper module)
module s (in, out)
inout out;
inout in;
endmodule
module \s.inv13 (in, out);
inout out;
inout in;
endmodule
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Mixed Simulation Output and Display in VHDL/VerilogSPICE
This chapter describes the ways analog and digital waveforms can be generated
and saved in NS-VCS-MX, HSIM-VCS-MX and XA-VCS-MX simulations.
Overview
The output of VHDL/Verilog-SPICE mixed-signal simulation can either be
saved into two separate files—one file for VCS-MX results (.vpd format) and
another for analog results (for example,.vpd or .fsdb format)—or the
simulation can generate a unified single output (in .vpd format or .uod in the
case of NS-VCS-MX or HSIM-VCS-MX format) that contains both digital and
analog waveforms.
This chapter contains the following sections:
■
Generating an Analog Output File
■
Generating a Digital Output File
■
Generating a Merged VPD Output File
Generating an Analog Output File
The same methods described in the Verilog-SPICE chapter earlier in this
document are applicable in VHDL/Verilog-SPICE as well (see Printing Analog
Signals on page 80).
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Generating a Digital Output File
Generating a Digital Output File
To capture both VHDL and Verilog signals in the design, the format of the
digital output file must be VPD (also called VCD+). Storing digital signals in
VPD also provides the option of merging the digital and analog signals into a
unified output file.
The method for generating the VPD file for digital signals depends on whether
the design is VHDL-top (top-level cell is in VHDL) or Verilog-top (top-level cell is
in Verilog).
The steps to generate VPD output for VHDL-top designs follows:
1. Use the -PP or -debug_pp compile time options with VCS to enable VPD
generation by VCS-MX, as follows:
vcs -ad top_entity_name -PP
or
vcs -ad top_entity_name –debug_pp
2. Use the simv run time options "-ucli -i ucli_command_file_name"
to pass UCLI commands to dump a VPD file to VCS_MX. The command file
must contain a dump command to create a VPD file. It can also contain an
optional command to specify the name of the output VPD file. The example
below shows how the UCLI command file is read at run time:
simv -ucli -i ucli_command_file
where the content of the command file looks like:
dump -file output.vpd
dump -add / -depth 99
run 50000
quit
in which the -deep option specifies that all signals—at and below the
hierarchical path /foo—are dumped in the VPD file. If foo is the name of
the top entity, every digital signal in the design is saved in the VPD file.
The -o option specifies the VPD file name, and in this example, the file
name is foo.vpd.
For a complete list of all options for the dump command, refer to the VCSMX User Guide.
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The steps to generate VPD output for Verilog-top designs follows:
1. Use the -PP or -debug_pp compile time options with VCS to enable VPD
generation by VCS-MX, as follows:
vcs -ad top_entity_name -PP
or
vcs -ad top_entity_name –debug_pp
2. Use the $vcdpluson system task in the Verilog code to create a VPD
output file. The file name is vcdplus.vpd.
The syntax for the $vcdpluson system task is:
$vcdpluson [(level_number,module_instance|net or reg)];
Example 80 captures all signals in block top.foo, and two levels below it:
Example 80
$vcdpluson (2,top.foo);
If $vcdpluson is called without parameters,
$vcdpluson;
all digital signals are dumped in the output VPD file.
For more descriptions of the $vcdpluson system task, refer to the VCSMX User Guide.
Generating a Merged VPD Output File
In VHDL/Verilog-SPICE, a merged output file in VPD format can be created.
To generate a merged VPD file, the following conditions must be met:
■
The analog signals must be saved in .vpd format and NanoSim/HSIM/XA
must be instructed to merge the analog VPD output with the one generated
by VCS through the following configuration commands:
•
For NanoSim
config command:
set_print_format for=vpd
•
file=merge
For HSIM
SPICE command:
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.param HSIMOUTPUT=vpd
•
file=merge
For XA
config command:
set_waveform –format vpd
■
–file=merge
The digital signals must be saved in .vpd format
The name of the merged VPD file will be the one determined by VCS.
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Using the NanoSim-VCS-AMS Feature
This chapter provides an overview of the NS-VCS-AMS flow.
Overview
The NS-VCS-AMS feature enables the NS-VCS mixed-signal engine to support
the Verilog-AMS language, as described in the Verilog-AMS LRM 2.2 (with
some exceptions and limitations described in this section).
The NS-VCS-AMS flow supports many of the same features as those in NSVCS, described in Chapter 2, Using Mixed Signal Features. This chapter
describes both the features that are specific to the NS-VCS-AMS flow, and
those features that differ from the NS-VCS flow.
Some of the concepts in the Verilog-AMS language that must be considered
when using the NS-VCS-AMS flow are:
■
Analog and digital blocks in Verilog-AMS
■
Connect rules and connect modules
■
Continuous and discrete domains
■
Nets and disciplines
This chapter contains the following topics:
■
Analog and Digital Domains
■
Understanding Analog and Digital Blocks in Verilog-AMS
■
The Concept of Nets and Disciplines
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Analog and Digital Domains
Analog and Digital Domains
Depending on the computational methods used to calculate the values of a
signals or variable, the signal or variable can belong to the analog domain (also
known as continuous domain) or digital domain (also known as discrete
domain).
Voltage and current values are calculated in the analog domain, while the
contents of registers and states of gate primitives are calculated in the digital
domain. Integer and real variables can belong to either the analog or digital
domain, depending on how their values are assigned.
If a value is assigned in an analog block, the domain is considered analog. If a
value is assigned in a digital block, the domain is considered digital. The
assignment to real and integer variables can occur only in one domain.
Values calculated in the digital domain change values in a discrete and noncontinuous manner. As a result, the derivative—with respect to the time of a
digital value—is always zero (0). Values calculated in the analog domain,
however, vary continuously and their derivative—with respect to the time—
varies (as the value varies).
Understanding Analog and Digital Blocks in Verilog-AMS
Verilog-AMS supports the definition of analog and digital blocks within the
same module, and for the digital block to access nets in the analog block (and
vice-versa).
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Example 81 shows Verilog-AMS code with both digital and analog blocks
(highlighted).
Example 81
Verilog-AMS code with both digital and analog blocks
`include "constants.vams"
`include "disciplines.vams"
module foo ( in, out);
input
in;
output out;
logic
in;
electrical out;
reg
clk; (Digital block)
initial begin
clk = 0;
forever #5 clk = ~clk;
end
analog begin (Analog block)
if (in == clk)
V(out) <+ 1.8;
else
V(out) <+ 0.0;
end
endmodule
A Verilog-AMS module can contain many digital blocks, but it can only contain
one analog block as defined in the Verilog-AMS LRM (Language Reference
Manual).
An analog block is identified by the keyword analog. All other blocks inside a
module definition are considered digital blocks (e.g., initial and always blocks).
Since Verilog-AMS is a superset of the Verilog-A and digital Verilog-HDL
languages, a module that only contains digital blocks (conventional digital
Verilog HDL) or a module that only contains an analog block (conventional
Verilog-A) is also viewed and treated as Verilog-AMS code by the simulator.
The Concept of Nets and Disciplines
In Verilog-AMS, the term net refers to nodes inside a module that provide
connections between two or more submodules. Every port of an instantiated
module provides a connection between two nets.
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A net can belong to a digital or analog domain. The way to declare the domain
for a net is by associating it with a predefined discipline in Verilog-AMS. Two of
the most common disciplines in Verilog-AMS are electrical—for analog nets,
and logic—for digital nets.
The discipline declaration for each net can be made explicitly in the code, or the
simulator can resolve it, based on the discipline resolution algorithm. However,
the discipline of all nets in a Verilog-AMS code must be determined before the
simulation can start.
In Example 81, port in is defined as a net of discipline logic, while port out is
declared as a net of discipline electrical.
Example 82 shows an example of a module in which internal nets n1, n2 and
n3 are defined to make connections between submodules.
Example 82
Port connectivity for instances via nets for which no explicit
disciplines are defined
`include "constants.vams"
`include "disciplines.vams"
module test;
// no disciplines declared for nets "n1", "n2" and "n3"
blka
blkb
blkc
i1
i2
i3
(.a( n1), .b(n2), .z(n3) );
(.out(n1) );
(.a(n3), .out(n2) );
endmodule
Note:
No explicit disciplines are declared for these nets, and the simulator can use
the discipline resolution method to assign the proper discipline.
In the digital Verilog-HDL language, no explicit discipline declaration is made
for wire, reg or port, so the compilation of the Verilog-HDL files can fail
when they are used in the NS-VCS-AMS flow.
To resolve this problem, a default discipline can be declared for all nets without
an explicit discipline declaration. This can be achieved by either placing the
`default_discipline directive inside the Verilog code, or by using the
-ams_discipline VCS compile switch.
Example 83 shows where the `default_discipline directive in Verilog
code is used to define the discipline logic as the default discipline. In this
example, ports a and b of module foo have no explicit discipline declaration.
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However, because of the `default_discipline logic statement, the logic
discipline is assigned.
Example 83
Defining a default discipline using the `default_discipline directive
`include "constants.vams"
`include "disciplines.vams"
`default_discipline logic
module foo ( a , b);
input a;
output b;
…
endmodule
Example 84 shows the -ams_discipline VCS switch defines a default
discipline.
Example 84
vcs
-ams_discipline switch declares a default discipline
testbench.v
-R -ad -ams_discipline logic
Unlike nets, disciplines are not explicitly declared for variables.. The domain of
a variable is determined by the context in which the assignment is made. If the
variable is assigned a value in an analog context (i.e., in an analog block), the
variable is considered analog. If, however, the assignment is made in a digital
context (i.e., in a digital block), the variable is considered digital. A variable can
only be assigned a value in one domain, but it can be accessed for reading
from any domain.
Example 85 shows a digital domain variable. The real variable v is assigned a
value in the digital domain (inside the initial block), and as a result is
considered a digital variable.
Example 85
Digital variable assigned a value in a digital domain (inside "initial"
block)
`include "constants.vams"
`include "disciplines.vams"
module foo;
real v;
initial begin
v=1.5;
end
…
endmodule
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Example 86 shows a variable definition in Verilog-AMS code. The variable is
assigned a value in the analog domain, and is treated as an analog variable.
Example 86
Analog variable assigned a value in an analog domain (inside
"analog" block).
`include "constants.vams"
`include "disciplines.vams"
module foo;
real v;
analog begin
…
v = 1.5;
…
end
…
endmodule
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Mixed-Signal Report Files
This chapter provides a detailed description of the intermediate files generated
in these mixed-signal simulation flows: Verilog-SPICE, VHDL/Verilog-SPICE,
and Verilog-AMS-SPICE.
simv.msv Directory and Mixed-signal Report Files
In all flows of the Discovery-AMS mixed-signal simulation, a directory with the
.msv extension is created to store mixed-signal report files. By default, the
name for the directory will be simv.msv unless the VCS -o option is used to
change the name of the executable generated by VCS. In that case, the name
of the directory will be vcs_output.msv.
The following sections describe the report files that are stored in the .msv
directory and explains their contents.
■
through_net.rpt
■
hierarchy.rpt
■
mview.rpt
■
interface_element.rpt
■
names_map.rpt
through_net.rpt
This file is only generated in Verilog-SPICE and VHDL/Verilog-SPICE flows. It
contains the list of all thrunets in the design and gets generated only if there is
at least one a2a or d2d net in the design. If both a2a and d2d thrunets exist in
the design, the a2a nets will be listed first, followed by d2d nets, as shown in
the example below:
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snps_sptop.lock a2a
snps_sptop.reset a2a
snps_sptop.f6g_b d2d
snps_sptop.xpll.lfin d2d
…
hierarchy.rpt
This file lists the hierarchical paths to all cells in the design along with their cell
names with exact same content and format as in “itree.map”. An example of
the file content is shown below:
top(top).dut<addr4>.x4<addr>.x9<nor2>
top(top).dut<addr4>.x1<addr>.x2<xor2>.x2<inv>
top(top).dut<addr4>.x1<addr>.x2<xor2>.x3<inv>
top(top).dut<addr4>.x1<addr>.x2<xor2>.x4<xfer>
mview.rpt
The name and content of this file remains unchanged. It lists all cells in the
design that have more than one view (for example, SPICE, Verilog, Verilog-A).
Here is an example of the file content:
; Lists of modules: Verilog Spice Verilog-A Adfmi
pll pll
*
*
*
inv inv
*
In this example, multi-view cell “pll” has Verilog and SPICE views, while cell
“inv” has SPICE and Verilog-A views.
interface_element.rpt
This file is only generated in Verilog-SPICE and VHDL/Verilog-SPICE flows. It
contains all information related to interface nets in the design in the following
format:
138
■
A header explaining the meanings of acronyms used in the file (a2d, e2r
etc.)
■
Total number of all resistors added to the netlist because of interface
elements
■
A list of resistance map files used
■
A list of all interface nodes
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The following comment lines appear at the top of the report file. They explain
the meaning of the acronyms used in describing the type of interface nets:
# a2d:
Analog to Digital interface node
# d2a:
Digital to Analog interface node
# inout: bidirectional interface node
# e2r:
Real interface node with an Analog to Digital direction
# r2e:
Real interface node with a Digital to Analog direction
The header is followed a list of resistance map files used in the design. If no
explicit resistance map file is used, only the default resistance map will be
listed:
rmap_file 1 = tool_install_dir/resistance.map
otherwise all resistance map files that apply to interface nets will be listed as
shown below:
rmap_file 1 = ./global_res.map
rmap_file 2 = ./cust_res_a.map
rmap_file 3 = ./cust_res_b.map
rmap_file 4 = ./cust_res_lv.map
rmap_file 5 = ./cust_res_hv.map
The next section in the report file is the list of interface nodes, which looks like
the following:
…
a2d
loth=0.2v
hith=1.7v node= snps_sptop.xpll.lock;
d2a
hiv=3.3
lov=0.0 node= snps_sptop.xpll.xpfd.xlock.lock;
inout hiv=3.3
lov=0.0 loth=0.3v hith=2.7v node= top.i1.clk;
e2r
node=top.i2.ctl;
r2e
node=top.i3.data;
…
The “loth” and “hith” values for “a2d” and “inout” nodes are reported as
absolute values and not as ratios (percentages). It is important to note that for
“a2d” and “d2a” nodes, the reports are generated with correct syntax for “a2d”
and “d2a” commands. Consequently, to change the default settings, these lines
can be copied and pasted into mixed-signal control file (vcsAD.init) and the
only changes needed will be the ones to the high and low levels/thresholds.
The equivalent report in the Verilog-AMS-SPICE flow is the Connect Module
report which can be generated with the VCS option -ad_iereport.
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names_map.rpt
This file is only generated in the Verilog-SPICE and VHDL/Verilog-SPICE
flows. Each line in this file corresponds to an interface element and contains
two entries in the following format:
interface_low_conn : interface_hi_conn
where low_conn and hi_conn refer to the two ends of a mixed-net.
■
low_conn refers to the net name in the child cell that connects to the
interface.
■
hi_conn refers to the net name in the parent cell that connects to the
interface.
If Verilog/VHDL instantiates SPICE, the hi_conn node will be in Verilog/VHDL
net and the low_conn will be a SPICE one.
If SPICE instantiates Verilog/VHDL, the hi_conn will be a SPICE net and
low_conn will be a Verilog/VHDL one.
In the following example, signal top.ctl is the hi_conn for the given
interface net and top.i1.x4.ctl_sig is the low_conn net.
top.i1.x4.ctl_sig:top.ctl:
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Using Multiple Views, Donut Partitioning and Connect
Modules with NS-VCS-AMS
13
This chapter describes using multiple views, donut partitioning, and connect
modules in NS-VCS-AMS.
Overview
The following topics are described in this section:
■
Selecting Multiple Views
■
Understanding Hierarchical Layering of SPICE and Verilog-AMS in a
Design
■
Unsupported Features and Limitations in NS-VCS-AMS
■
Converting Signals with Interface A/D and D/A Connect Modules
•
Identifying the Correct Connect Module
•
Understanding Connect Rules
Selecting Multiple Views
In the NS-VCS-AMS flow, multi-view cells can exist, meaning that the cells
have both a SPICE subcircuit and a Verilog module definition. The appropriate
view can be selected by using The use_spice Command or The use_verilog
Command (mixed-signal control commands). Both of these commands—just
as in NS-VCS—support instance-based, as well as cell-based, view selection.
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Understanding Hierarchical Layering of SPICE and Verilog-AMS in a Design
Note:
In the NS-VCS-AMS flow, there is no distinction between Verilog-A, digital
Verilog-HDL or Verilog-AMS code. Verilog-A and digital Verilog-HDL are
both viewed as subsets of Verilog-AMS. Legacy digital Verilog-HDL code or
legacy Verilog-A code are both considered Verilog-AMS code in the NSVCS-AMS flow.
In the NS-VCS-AMS flow, a cell can only have one module definition.
Regardless of the type of Verilog language used, the definition is viewed as
Verilog-AMS and can be selected by using the use_verilog command.
Example 87 shows a mixed-signal control file where both instance-based and
cell-based view selection commands are used.
Example 87
A mixed-signal simulation setup file with both cell-based and
instance-based usage for "use_spice" and "use_verilog"
commands
choose nanosim -n spice_files.spi -c cfg;
use_verilog
use_spice
top.i1.i2;
top.i1.i3;
use_verilog -module
use_spice
-cell
mux;
inverter;
Note:
In the NS-VCS-AMS flow, all Verilog files are passed to VCS at compile time.
In the NS-VCS flow, Verilog-A files are passed to NanoSim, using the `hdl
command. Although this feature is also supported in the NS-VCS-AMS flow,
it is recommended that all Verilog files, including legacy Verilog-A, be
passed to VCS at compile time as described in Chapter 4, Running a MixedSignal Simulation in the Verilog-SPICE Flow.
Understanding Hierarchical Layering of SPICE and Verilog-AMS in a
Design
NS-VCS-AMS supports both SPICE-top and Verilog-top flows. It also supports
any donut configuration with arbitrary layering of SPICE and Verilog-AMS in the
design hierarchy.
By default, NS-VCS-AMS assumes that the design is Verilog-top, unless the
spice_top command is placed in the mixed-signal control file. The support of
the SPICE-top and Verilog-top flows in NS-VCS-AMS is consistent with their
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Unsupported Features and Limitations in NS-VCS-AMS
support in NS-VCS. For further information, please refer to the section Three
Mixed-Signal Simulation Flows in Chapter 1, Getting Started with Mixed-Signal
Simulation.
Unsupported Features and Limitations in NS-VCS-AMS
The following Verilog-AMS 2.2 features are not currently supported in the NSVCS-AMS flow:
■
Cross-Module Referencing (XMR) across the analog/digital boundary
Note:
XMR within the Verilog code is supported. However, an XMR in which
the source or the target of the XMR is located in the analog domain is
not supported.
■
abstol parameter in ddt() (LRM chapter 4.4.4)
■
aliasparam (LRM chapter 3.2)
■
ddx() (LRM chapter 4.4.7 )
■
detail discipline resolution (LRM chapter 8.4.4.2)
■
driver access functions, $driver_xxx (LRM chapter 8.10)
■
hierarchical net discipline coercion (LRM chapter 8.4.4.3)
■
hierarchical system parameters (LRM chapter 7.2.6)
■
last_crossing (LRM chapter 4.4.11)
■
localparam (LRM chapter 3.2)
■
parameterized-width analog buses
■
parameter arrays (LRM chapter 3.2.4)
■
paramsets (LRM chapter 7.3 )
■
$param_given() (LRM chapter 10.11)
■
$port_connected() (LRM chapter 10.11)
■
predefined macros (LRM chapter 11.7)
■
$rdist_xxx functions (LRM chapter 10.3)
■
$simparam() (LRM chapter 10.1)
■
VPI routines (LRM chapter 13)
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Converting Signals with Interface A/D and D/A Connect Modules
Converting Signals with Interface A/D and D/A Connect Modules
In Verilog-AMS, the conversion of signals between the analog and digital
domains is done by interface blocks called connect modules. Connect modules
are inserted automatically by the simulator at the interface between analog and
digital nets, but they can also be inserted manually.
A connect module is a predefined Verilog-AMS module with two ports—one
analog and one digital. Example 88 shows a sample connect module with the
arbitrary name of snps_cm_a2d that takes an input of type electrical and
produces an output of type logic.
Example 88
An a2d connect module with an arbitrary name of "snps_cm_a2d"
connectmodule snps_cm_a2d (ain, dout);
output dout;
input ain;
logic dout;
electrical ain;
… // The body of the connect-module
… // will be defined here
endmodule
Identifying the Correct Connect Module
The process of identifying and applying the appropriate connect module for
each interface requires the following steps:
1. The simulator ensures that every net in a module has a defined discipline. If
a net does not have an explicit discipline definition, the discipline resolution
algorithm is called to resolve and assign a discipline based on the discipline
of other nets connected to it.
2. Once the disciplines for all nets are determined, the simulator identifies
connections between nets of digital and analog disciplines
3. connect modules with matching disciplines are then inserted between the
analog and digital nets. Direction of the ports are also accounted for.
Note:
These steps occur at compilation time. If any steps are unsuccessful, the
compile exits with an error message.
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Converting Signals with Interface A/D and D/A Connect Modules
Verilog-AMS enables associating a particular connect module, based on the
disciplines and port directions of the two nets connected, by defining a connect
rule that is passed to the simulator.
Connect modules of this type are commonly called a2d connect modules.
Connect modules that take a digital input and deliver an analog output are
usually called d2a connect modules. The connect modules with bidirectional
analog and digital ports are called bidi connect modules.
Understanding Connect Rules
Example 89 shows a connect rule where two connect module associations are
made. The first rule defines the connect module to be used in case an a2d
interface must be inserted between two nets. The second rule defines the
connect module to be used as a d2a interface between two nets.
Example 89
Connect rule definition "snps_crules"
connectrules snps_crules;
connect snps_cm_a2d input electrical, output logic ;
connect snps_cm_d2a input logic, output electrical ;
endconnectrules
A connect rule may contain many more associations; for example, to define
interfaces between other types of digital and analog disciplines, or to define bidi
connect modules.
Note:
Connect rules and connect modules are only deployed by the simulator if
there is a connection between a digital and an analog net. If no direct
connection exists throughout the netlist, connect rules and connect modules
are not used.
In NS-VCS-AMS, all conversions of signals between digital and analog are
done by-way-of connect modules, as opposed to the resistance mapping
used in NS-VCS.
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Example 90 displays an example in which no connect module is required.
Example 90
Direct net access between analog and digital blocks within the
same module
module foo ( dig_in, dig_out, an_in, an_out);
input
dig_in,
an_in;
output dig_out, an_out;
reg
dig_out;
logic
electrical
dig_in, dig_out;
an_in, an_out;
…
always @ (above(V(an_in), +1)
dig_out = 1b'1;
// analog signal accessed in digital domain
…
analog begin
if (dig_in == 1b'1) // digital signal accessed in analog domain
V(an_out) <+ 1.8;
end
…
endmodule
Figure 18 shows an example of a circuit, a simple inverter chain, where
connect modules are used because of a direct connection of analog and digital
nets.
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Figure 18
Verilog-D
logic
Cells of an inverter chain modeled in SPICE, Verilog-D, Verilog-A
and Verilog-AMS
SPICE
logic
electrical
Verilog-AMS
electrical
logic
electrical
Verilog-A
electrical
electrical
The circuit in this example contains four inverters:
■
The first inverter is modeled in Verilog-D
The inverter is defined by a module that contains only digital block(s)
■
The second inverter is modeled in SPICE
All ports of a SPICE cell assume electrical discipline in NS-VCS-AMS
■
The third inverter is modeled in Verilog-AMS with logic input and
electrical output
The inverter is defined by a module that contains both an analog block and
digital block(s)
■
The fourth inverter is modeled in Verilog-A
The inverter is defined by a module that contains only an analog block
Note:
In the NS-VCS-AMS flow, all "Verilog" modules, regardless of whether they
contain an analog or digital block, or both, are considered Verilog-AMS
code. The examples of Verilog-A and Verilog-D referenced in Figure 18 are
only used for clarification.
Figure 19 shows where the simulator inserts connect modules. There are two
inserted connect modules: d2a and a2d.
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Figure 19
Inserted connect modules when two nets of different disciplines
come into contact
Verilog-D
SPICE
d2a
logic
148
logic
Verilog-AMS
Verilog-A
a2d
electrical
electrical
logic
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14
Preparing a Mixed-Signal Simulation with NS-VCS-AMS
This chapter describes the special requirements for compiling netlists for an NSVCS-AMS simulation.
Overview
Before compiling netlists for an NS-VCS-AMS simulation, special requirements
must be met; for example, identical subcircuit and module names for multi-view
cells, port name matching between SPICE and Verilog views, etc.
The following topics are described in this section:
■
Steps for Preparing a Mixed-Signal Simulation in NS-VCS-AMS
■
Files Containing Connect Rule and Connect Module Definitions
Steps for Preparing a Mixed-Signal Simulation in NS-VCS-AMS
In addition to the tasks required for using the NS-VCS flow, which are
mentioned in Table 5 in Chapter 3, Mixed-Signal Simulation in the VerilogSPICE Flow, the following steps must be taken to prepare a mixed-signal
simulation in NS-VCS-AMS:
1. Define proper connect modules and connect rules, if needed.
2. Use/modify the default connect rule and connect module files available in
the NanoSim installation.
3. Include the following two lines at the top of the first Verilog file passed to the
simulator:
•
`include "constants.vams"
•
`include "disciplines.vams"
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Steps for Preparing a Mixed-Signal Simulation in NS-VCS-AMS
Note:
Connect rules and connect modules are not used if direct connection(s)
between analog and digital nets do not exist. This occurs if the interactions
between analog and digital nets are implemented by-way-of the analog/
digital cross-boundary sampling within a Verilog-AMS module—not through
port connections—as shown in Figure 19 in Chapter 13, Using Multiple
Views, Donut Partitioning and Connect Modules with NS-VCS-AMS.
However, if there are direct connections between analog and digital nets (e.g.,
nets of electrical and logic disciplines), the definitions for connect rules and
connect modules must be passed to the simulator at compile time.
NanoSim installation comes with default connect rules and connect modules.
They are located at:
NanoSim_install_dir/platform_type/ns/interfaces/vcsace
where platform_type is the name of the platform (e.g., linux, amd64,
sparcOS5 etc.). For example, the default connect rules and connect modules
for a Linux platform are located at:
NanoSim_install_dir/linux/ns/interfaces/vcsace
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Files Containing Connect Rule and Connect Module Definitions
Files Containing Connect Rule and Connect Module Definitions
The files that contain default definitions for connect rules and connect modules
are:
■
snps_cm_a2d_1.vams and snps_cm_d2a_1.vams (connect module)
These files contain the default a2d and d2a connect module definitions. The
connect modules contain many parameters that define their behavior, such
as parameters to define the analog supply voltage, high and low thresholds
for a2d or d2a conversions, delay times, etc.
These parameters have default values that can be overwritten when the
modules are referenced in the connect rule files.
■
snps_crules_1_xx.vams (connect rule)
Specific xx strings signify specific connect rule definitions for specific
analog supply voltages. For example, the default connect rule file for a 1.8V
supply is:
snps_crules_1_18.vams
If the design has specific characteristics (e.g., an analog supply voltage of
1.6V) that do not match any of the default connect rule files, define a connect
rule file by copying one of the default files to a new file and change the
parameters for the connect module referenced inside of it.
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15
Running a Mixed-Signal Simulation with NS-VCS-AMS
This chapter describes the steps required for running an NS-VCS-AMS mixedsignal simulation.
Overview
The following topics are described in this section:
■
Steps for Running a Mixed-signal Simulation in NS-VCS-AMS
•
Compile Options Specific to NS-VCS-AMS
■
Required Input Files
■
Verilog Netlist Files
■
Mixed-signal Simulation Setup File
•
■
Files Containing Connect Rule and Connect Module Definitions
Compiling and Running the Design
Steps for Running a Mixed-signal Simulation in NS-VCS-AMS
The steps required for running an NS-VCS-AMS mixed-signal simulation are,
mostly, identical to the steps outlined in Chapter 4, Running a Mixed-Signal
Simulation in the Verilog-SPICE Flow. The only differences between the two
flows are:
■
Compile options specific to NS-VCS-AMS
■
Required input files
■
Compiling and running the design
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Steps for Running a Mixed-signal Simulation in NS-VCS-AMS
Compile Options Specific to NS-VCS-AMS
The following compile options are specific to the NS-VCS-AMS flow:
■
-ams (mandatory)
■
-ams_discipline logic (optional, but highly recommended)
■
-ams_drreport (optional)
■
-ams_iereport(optional)
-ams
-ams
To enable the NS-VCS-AMS feature, include the -ams switch in the compile
script as shown in Example 91.
Example 91
vcs -ad -ams
…
-ams_discipline logic
The -ams_discipline logic option tells the simulator that all nets without
an explicit discipline definition must assume discipline type logic. This
compile option is used when importing legacy Verilog-D code in which no
disciplines are defined for module ports.
By using this option, discipline logic is assigned to all such ports avoiding a
compile-time error.
While logic is the common digital discipline, if other digital disciplines
are defined in the Verilog-AMS code, they can be used instead of logic. See
Example 92.
Example 92
-ams_drreport
The -ams_drreport compile option prints—both on the screen and in the
compile log file—the discipline resolution report. This report lists all the
interface nodes, their level of hierarchy, and how their disciplines were assigned
(by-way-of discipline resolution or by explicit declaration).
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Required Input Files
Example 93 shows how these compile options (specific to the NS-VCS-AMS
flow) can be used.
Example 93
vcs -f verilog_file_list -ad -ams
ams_iereport -ams_drreport …
-ams_discipline logic
-
-ams_iereport
The -ams_iereport compile option prints—both on the screen and the
compile log file—a list of all the instances of connects modules in the design
with the following information:
■
instance name under which the connect module was inserted
■
instance name of the connect module
■
module name of the connect module
■
discipline resolution mode used (i.e., merged or split)
■
net and port that connect to each end of the connect module
Required Input Files
Most of the input files required for the NS-VCS-AMS flow are identical to those
in the NS-VCS flow, with some differences in the following categories:
■
Verilog netlist files
■
Mixed-signal simulation setup file
■
Files containing connect rule and connect module definitions
Verilog Netlist Files
In NS-VCS-AMS, all Verilog files, whether Verilog-D, Verilog-A or full VerilogAMS, are passed to the simulator at compile time.
Example 94 is an example of how all Verilog files are passed to the simulator at
compile time.
Example 94
Verilog files passed to the simulator at compile time
vcs -ams -ad
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block1.va
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Mixed-signal Simulation Setup File
In this example, testbench.v contains Verilog-D code, block1.va contains
Verilog-A code, and block2.vams contains a full Verilog-AMS code.
Note:
It is possible to pass Verilog-A files to the simulator using the SPICE .hdl
command, but it is highly recommended to pass the files at compile time.
Mixed-signal Simulation Setup File
NS-VCS-AMS requires a mixed-signal control file, just like NS-VCS. The format
and content of this file is identical between the two flows, and the file (just like in
the NS-VCS flow), is called at compile time using the -ad switch.
The only difference is when there are no SPICE file(s) used in the NS-VCSAMS flow. This occurs when all analog blocks are described in Verilog-AMS or
Verilog-A code. In such a case, the call to NanoSim in the mixed-signal control
file can be as simple as the following:
choose
nanosim -C nanosim.cfg;
Files Containing Connect Rule and Connect Module Definitions
In NS-VCS-AMS, definitions for connect rules and connect modules are passed
to the simulator at compile time. As described in Chapter 3, Mixed-Signal
Simulation in the Verilog-SPICE Flow, the NanoSim installation directory
contains default connect rule and connect module files, as well as sample files
with default values.
These default files can be used, or new files can be created by creating a copy
of the default files and modifying them to suit the specific design characteristics
(e.g., changing the vsup supply voltage parameter for the connect module).
Example 95 shows how connect rule and connect module definitions can be
passed to the simulator.
Example 95
"Connect rule" and "connect module" files passed to the simulator
at compile time
vcs -ad -ams snps_cm_a2d_1.vams snps_cm_d2a_1.vams
snps_crules_1_18.vams …
In this example, it is assumed that the files are in the local directory. If not, a full
path to the location of these files is required (just as in any other Verilog file).
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Compiling and Running the Design
Compiling and Running the Design
Similar to the NS-VCS flow, the design is compiled and run using the generated
binary executable.
Example 96 shows a sample compile script.
Example 96
A sample NS-VCS-AMS compile script
vcs -ad -ams -f verilog_file_list
snps_cm_a2d_1.vams
snps_cm_d2a_1.vams
snps_crules_1_18.vams
-ams_discipline logic
-l comp.log
To run the NS-VCS-AMS simulation, add the -R switch to the compile script so
the simulation starts automatically after compiling or,
% simv
[run-time options]
to run the mixed-signal simulation.
Note:
simv is the default name for the binary executable generated after
compilation that can be overwritten using the -o exec_file_name
compile time switch.
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Chapter 15: Running a Mixed-Signal Simulation with NS-VCS-AMS
Compiling and Running the Design
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A
Mixed-Signal Commands
A
This appendix lists the old and new Mixed-signal commands.
Overview
In 2009.06 a new set of mixed-signal commands is introduced which will
replace, and in some cases add to, the old command set.
Table 13 maps the new commands to the old ones. The table also identifies the
old, obsolete commands and new commands that do not have a counterpart in
the old command set.
Both sets of commands will be supported in the 2009.06 release, but the old
commands will be phased out in later releases.
Table 13
Old and New Mixed-Signal Commands
Old Mixed-Signal Commands
New Mixed-Signal Commands
(to be phased out after 2009.06)
(starting from 2009.06)
choose
choose
set bus_format
bus_format
N/A
a2d (replaces NanoSim config
command "set_node_thresh"
and the use of HSIM
".hsimvcs_intfparam"
command for a2d interface elements)
set interface_opt
d2a (also replaces the use of HSIM
".hsimvcs_intfparam"
command for d2a interface nets)
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Appendix A: Mixed-Signal Commands
Overview
Table 13
162
Old and New Mixed-Signal Commands
Old Mixed-Signal Commands
New Mixed-Signal Commands
(to be phased out after 2009.06)
(starting from 2009.06)
N/A
insert_cell (new in 2009.06)
set irmap (obsolete, replaced by
XMR system tasks in 2009.06)
N/A
set mview_vlog_noportswap
mview_vlog_noport_swap
set opt_shadowfile
optimize_shadowfile
set print_thru_net
no_thru_net_opt
N/A
param_pass (new in 2009.06)
set remove_interface
remove_d2a
set res_by_node
rmap_by_node
set spice_port_order_as_vlog
spice_port_order_as_vlog
set wrapper_dir
shadow_file_dir
spice_top
spice_top
use_spice
use_spice
use_verilog
use_verilog
use_vhdl
use_vhdl
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B
Unified Output Display (UOD) File Samples
B
This appendix contains sample Unified Output Display (UOD) files and their
respective contents.
UOD File Samples
The sample part of the example shown in Example 97 is generated from a
NanoSim .out file.
Example 97
Original NanoSim .out file
.index v(test_adder.c[2]) 129 v
.index test_adder.c[2] 130 l
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Appendix B: Unified Output Display (UOD) File Samples
UOD File Samples
For a sample of a .vcd file, see Example 98.
Example 98
Partial content of a .vcd file
$scope module test_adder $end
$var wire 4 $ s [3:0] $end
$var wire 3 % c [2:0] $end
$var reg 1 & cin $end
$scope module x2 $end
$var wire 4 $ S [3:0] $end
$var wire 3 % C [2:0] $end
$var wire 1 & CIN $end
$scope module XI15 $end
$var wire 1 ( a $end
$var wire 1 0 b $end
$var wire 1 G c $end
$var wire 1 H s $end
$var wire 1 # co $end
$upscope $end
$scope module XI14 $end
$var wire 1 * a $end
$var wire 1 2 b $end
$var wire 1 I c $end
$var wire 1 J s $end
$var wire 1 K co $end
$upscope $end
$upscope $end
$upscope $end
For a partial file sample that was converted from .vcd to _uod.out format,
see Example 99.
Example 99
.vcd to .out format partial file
;
; Begin VCD Definitions Part ***
;
.index test_adder.c[2] 14 l
.index test_adder.x2.C[2] 14 l
.index test_adder.x2.XI15.c 50 l
.index test_adder.x2.XI14.co 54 l
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Appendix B: Unified Output Display (UOD) File Samples
UOD File Samples
All mixed-signals are generated from NanoSim/HSIM signals. NanoSim/HSIM
data in mixed-signals is preserved and maintained, while VCS data in mixedsignals is eliminated.
In a _uod.out file, only the analog versions of the mixed-signals are present,
which are copied over from the original NanoSim/HSIM-generated .out file.
The digital version of the mixed-nets are not copied over to the _uod.out file
from the VCS-generated .vcd file.
For a sample of a _uod.out file, see Example 100.
Example 100 _uod.out file
.index v(test_adder.c[2]) 129 v
.index v(test_adder.x2.XI15.c) 129 v
.index v(test_adder.x2.XI14.co) 129 v
.index test_adder.c[2] 130 l
.index test_adder.x2.XI15.c 130 l
.index test_adder.x2.XI14.co 130 l
; Begin VCD Definitions Part ***
.index v(test_adder.x2.C[2]) 129 v
.index test_adder.x2.C[2] 130 l
For a sample nWave waveform display, see Figure 20.
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Appendix B: Unified Output Display (UOD) File Samples
UOD File Samples
Figure 20
166
nWave waveform display
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C
C
NanoSim-supported Command-line Options
This appendix contains a subset of NanoSim command-line options that are
supported in NS-VCS, NS-VCS-MX and NS-VCS-AMS solutions.
NanoSim Command-line Options
For a summary of NanoSim-supported command-line options, see Table 14.
Table 14
NanoSim-Supported Command-Line Options
NanoSim command-line
option syntax
Description
[--version]
This option prints NanoSim’s banner, which
contains version information.
[-A]
This option starts the double-precision version of
NanoSim. You often need to use this option to
simulate analog circuits.
[-C configuration_ file(s)]
This option does the same as the -c option, except
that all the commands in the configuration files
specified with this option are logged in the .log file.
[-c configuration_ file(s)]
This option specifies the names of the configuration
files for a NanoSim run.
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Appendix C: NanoSim-supported Command-line Options
NanoSim Command-line Options
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D
D
Reserved Keywords
This appendix describes the reserved keywords. When using NS-VCS, NSVCS-MX, or NS-VCS-AMS, these terms are treated as keywords in the Verilog
modules. If any of the following keywords are used as net names, port names,
instance names or module names in the Verilog (D) modules, you must rename
these keywords to avoid compilation errors.
Overview
This appendix contains the following items:
■
Reserved Keywords for NS-VCS and NS-VCS-MX
■
Reserved Keywords for NS-VCS-AMS
Reserved Keywords for NS-VCS and NS-VCS-MX
See Table 15 for an alphabetical listing of the reserved keywords for NS-VCS
and NS-VCS-MX:
Table 15
Reserved keywords for NS-VCS and NS-VCS-MX
abs
absdelay
abstol
access
acos
acosh
ac_stim
always
analog
analysis
and
asin
asinh
assign
atan
atan2
atanh
begin
branch
buf
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Appendix D: Reserved Keywords
Reserved Keywords for NS-VCS and NS-VCS-MX
Table 15
170
Reserved keywords for NS-VCS and NS-VCS-MX (Continued)
bufif0
bufif1
capacitor
case
casex
casez
ceil
cmos
connect
connectrules
continuous
cos
cosh
cross
ddt
ddt_nature
deassign
default
defparam
disable
discipline
discrete
domain
driver_update
edge
else
end
enddiscipline
endcase
endconnectrules
endmodule
endfunction
endnature
endprimitive
endspecify
endtable
endtask
event
exclude
exp
final_step
flicker_noise
floor
flow
for
force
forever
fork
from
function
generate
genvar
ground
highz0
highz1
hypot
inductor
idt
idtmod
idt_nature
iexp
ipulse
ipwl
isine
if
ifnone
inf
initial
intial_step
inout
input
integer
join
laplace_nd
laplace_np
laplace_zd
laplace_zp
large
last_crossing
limexp
ln
log
macromodule
max
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Appendix D: Reserved Keywords
Reserved Keywords for NS-VCS and NS-VCS-MX
Table 15
Reserved keywords for NS-VCS and NS-VCS-MX (Continued)
medium
merged
min
module
nand
nature
negedge
net_resolution
nmos
noise_table
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
potential
pow
primitive
pull0
pull1
pullup
pulldown
rcmos
real
realtime
reg
release
repeat
resolveto
resistor
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
sin
sinh
slew
small
specify
specparam
split
sqrt
strong0
strong1
supply0
supply1
table
tan
tanh
task
time
timer
tline
tran
tranif0
tranif1
transition
tri
tri0
tri1
triand
trior
trireg
units
vcvs
vccs
vectored
vexp
vpulse
vpwl
vsine
wait
wand
weak0
weak1
while
white_noise
wire
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Appendix D: Reserved Keywords
Reserved Keywords for NS-VCS-AMS
Table 15
Reserved keywords for NS-VCS and NS-VCS-MX (Continued)
wor
wreal
xnor
xor
zi_nd
zi_np
zi_zd
zi_zp
Reserved Keywords for NS-VCS-AMS
See Table 16 for an alphabetical listing of the reserved keywords for NS-VCSAMS:
Table 16
172
Reserved keywords for NS-VCS-AMS
above
abs
absdelay
acos
acosh
ac_stim
aliasparam
always
analog
analysis
and
asin
asinh
assign
atan
atan2
atanh
begin
branch
buf
bufif0
bufif1
case
casex
casez
ceil
cmos
connectrules
cos
cosh
cross
ddt
ddx
deassign
default
defparam
disable
discipline
driver_update
edge
else
end
enddiscipline
endcase
endconnectrules
endmodule
endfunction
endnature
endparamset
endprimitive
endspecify
endtable
endtask
event
exclude
exp
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Appendix D: Reserved Keywords
Reserved Keywords for NS-VCS-AMS
Table 16
Reserved keywords for NS-VCS-AMS (Continued)
final_step
flicker_noise
floor
flow
for
force
forever
fork
from
function
generate
genvar
ground
highz0
highz1
hypot
idt
idtmod
if
ifnone
inf
initial
intial_step
inout
input
integer
join
laplace_nd
laplace_np
laplace_zd
laplace_zp
large
last_crossing
limexp
ln
localparam
log
macromodule
max
medium
min
module
nand
nature
negedge
net_resolution
nmos
noise_table
nor
not
notif0
notif1
or
output
parameter
paramset
pmos
posedge
potential
pow
primitive
pull0
pull1
pullup
pulldown
rcmos
real
realtime
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtranif1
scalared
sin
sinh
slew
small
specify
specparam
sqrt
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Appendix D: Reserved Keywords
Reserved Keywords for NS-VCS-AMS
Table 16
174
Reserved keywords for NS-VCS-AMS (Continued)
string
strong0
strong1
supply0
supply1
table
tan
tanh
task
time
timer
tran
tranif0
tranif1
transition
tri
tri0
tri1
triand
trior
trireg
vectored
wait
wand
weak0
weak1
while
white_noise
wire
wor
wreal
xnor
xor
zi_nd
zi_np
zi_zd
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Glossary
GL
A2A through-net
A net that is used only for port connections between two SPICE subcircuits in a
Verilog view.
A2D
An analog-to-digital converter.
ADFMI view
In a given design, at a particular hierarchy, if an ADFMI module is available and
is used to simulate a particular block, it is considered an ADFMI view for that
block.
BA (back-annotation)
Back-annotation (BA) is a process of stitching the parasitic RCs back to the
design netlist through connectivity information (net name, instance name, pin
name) inside the parasitic file.
bidirectional switch
A device that conducts in both directions. In such cases, signals on either side
of the device can be the driver signal. A bidirectional switch is typically used to
enable isolation between buses or signals.
D2A
A digital-to-analog converter.
D2D through-net
A net that is only used for port connections between two Verilog modules in a
SPICE view.
donut configuration
In NS-VCS, a description of the design using different views across different
hierarchies. For example: Verilog-SPICE-Verilog or SPICE-Verilog-SPICE is
considered a donut configuration.
In NS-VCS-MX, a donut configuration only applies to the VCS-MX description.
You can instantiate a Verilog design in a VHDL design in a Verilog design
(Verilog-VHDL-Verilog). This is commonly referred to as a mixed-HDL donut.
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Glossary
DSPF
A detailed standard parasitic format (DSPF) output netlist format is generated
by an extraction tool, and describes interconnect information. Actual net
parasitic resistance and capacitance component information is contained in this
format.
GUI
A graphical user interface (GUI) for NanoSim.
HAR
Hierarchical array reduction (HAR) in NanoSim that speeds-up the simulation
for memory designs (DRAM and SRAM).
instantiation
The process of creating an instance from a module definition or simulator
primitive, and defining the connectivity and parameters of that instance.
mixed-net
A net that connects the discrete domain (digital) to the continuous domain
(analog). All nodes that exist at the boundary between VCS and NanoSim are
considered mixed-nets.
mixed-signal
A circuit containing analog- and digital-style components.
multiple view
In a given design, at a particular hierarchy, if more than one representation is
available for simulation (from the choices of Verilog, SPICE, ADFMI, and
Verilog-A), it is considered a multiple view.
NanoSim
The Synopsys fast-SPICE transistor-level simulator.
PLI
A programming language interface (PLI) of Verilog HDL is a mechanism for
interfacing Verilog programs with programs written in the C language. PLI also
provides a mechanism for accessing internal databases of the simulator from
the C program.
real data type
The Verilog or VHDL data type defined in IEEE Std 1264-1996 and Std 13642001.
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Glossary
resistance map file
An ASCII file that equates MOSFET "on" resistance to Verilog drive strength;
the resistance map file contains the signal conversion data between a SPICE
analog value to a Verilog digital value, and a Verilog digital value to a SPICE
analog value.
SDF
A standard delay format (SDF) file stores the timing data generated by EDA
tools for use in any stage of a design process. The data in the SDF file is
represented in a tool-independent way and includes the following information:
delay, timing check, timing constraint, incremental and absolute delay.
simv
A Verilog simulator command.
single view
In a given design, at a particular hierarchy, if there is only one view available for
simulation (from the choices of Verilog, SPICE, ADFMI, and Verilog-A), it is
considered a single view. A single view is automatically selected for simulation
as it is the only view available.
SPEF
A standard parasitic extraction format (SPEF) file is an IEEE standard format.
This file provides a standard median to pass parasitic information between EDA
tools during any stage in the design process. This format contains actual net
parasitic resistance and capacitance components.
SPICE netlist
In the present context, the term SPICE netlist is used in place of transistorlevel netlist.
SPICE-top
The top level of the design hierarchy is described in a transistor-level netlist
format.
SPICE view
In a given design, at a particular hierarchy, if a SPICE module is available and is
used to simulate a particular block, it is considered a SPICE view for that block.
VCS
A Synopsys Verilog hardware description language (HDL) simulator.
VCS-MX
A Synopsys simulator for Verilog, VHDL, and mixed-HDL design descriptions.
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Glossary
Verilog dummy module
A module that is the Verilog place holder for a transistor block. A dummy
module is an empty module containing only the module declaration and port
declarations.
Verilog-top
The top level of the design hierarchy is described in Verilog RTL or gate-level
netlist format.
Verilog view
In a given design, at a particular hierarchy, if a Verilog module is available and
is used to simulate a particular block, it is considered a Verilog view for that
block.
Verilog wrapper
A Verilog netlist comprising an empty module. Only the module name and port
description are in the wrapper.
VHDL
VHSIC HDL
vhdlan
A VHDL analyzer command.
vlogan
A Verilog analyzer command.
VPD
An output format for VCS-MX. VPD uses the VCD+ (value change dump)
format.
wreal data type
A real net data type used in a Verilog wrapper module to interface a real data
type VHDL port and a SPICE port in NS-VCS-MX.
XMR
A feature that is extensively used in Verilog testbenches, and is referred to as a
cross-module reference or Verilog hierarchical referencing. This feature
enables simple probing into, or monitoring of, buried signals without requiring
the signals to be routed to the top of the design for observation. No declaration
of global signals in a package is required for this feature, nor is any modification
of the original monitored code.
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Index
A
I
a2d command 47
array-type signal, Verilog wrapper 121
array-type signals, Verilog wrapper 121
autowrapper utility 115
input files
configuration 167
K
keywords, reserved 169, 172
B
back-annotation 32
back-annotation simulation 32
bi-directional mapping 31
bus_format command 52
bus-type signal, Verilog wrapper 121
bus-type signals, Verilog wrapper 121
C
choose command 46
commands
a2d 47
bus_format 52
choose 46
d2a 50
rmap_by_node 59
set spice_port_order_as_vlog 65
spice_top 54
use_spice 55
use_verilog 56
configuration files, specifying 167
creating a resistance map file 30
cross module referencing (XMR) 17
D
d2a command 50
DC initialization 77
double-precision mode 167
dummy Verilog modules 15
M
mapping
bidirectional 31
unidirectional 30
mixed-signal control file commands, summary 66
mixed-signal simulation 35, 36
mixed-signal simulation setup
bus_format 52
no_thru_net_opt 58
optimize_shadowfile 57
remove_d2a 59
rmap_by_node 59
rmap_file 60
shadow_file_dir 65
spice_top 54
use_spice 55
use_verilog 56
mixed-signal simulation setup file 45
N
nanosim command, choosing 47
NanoSim command-line options 167
netlist
SPICE 35
Verilog 35
no_thru_net_opt command 58
nWave waveform display 165
O
optimize_shadowfile command 57
179
Index
P
P
partitioning commands
bus_format 52
set rmap 100
port-mapping 43
R
remove_d2a command 59
reserved keywords 169, 172
resistance map file 30
resistance map file, creating 30
rmap_by_node command 59
rmap_file command 60
simv executable 73
sno_thru_net_opt command 58
SPICE netlist
array-type signal 121
bus-type signal 121
spice_top 54
spice_top command 14, 54
U
unidirectional mapping 30
UOD file samples 163
use_spice command 55
use_verilog command 56
S
V
SDF files 32
set mview_vlog_nosportswap command 65
set spice_port_order_as_vlog command 65
setting up environment 104
setup file, creating 45
shadow_file_dir 64
shadow_file_dir command 64, 65
simulator, selecting 47
vcs +ad command
-Mupdate option 73
Verilog wrapper file, bus/array-type signals 121
VHDL design library 96
180
X
XMR (cross module referencing) 17