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Document Change History
Rev.
0
Effective
Date
2012-12-11
1
2012-12-28
Author
Change Description
JingJing Initiate.
Wang
JingJing Wang
Revised document title from “SMIC (SH) Design Service Standard
IO Application Note (Ver4p0) O.I.” to “SMIC (SH) Design Service
Standard I/O Library Application Notes (Ver4p1) O.I.”
Added PANA2CAP in table 7.4.3.1
Added section 7.4.5 – “Digital Cells within Analog Domain” for
PVSS4CAP application
Revised “Appendix A” to SMIC in section 7.10.2
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Library Application Notes (Ver4p1) O.I.
1. Title: SMIC (SH) Design Service Standard IO Application Note (Ver4p1) O.I.
2. Purpose: For Customer Reference
3. Scope: SMIC Customers
4. Nomenclature: NA
5. Reference: NA
6. Responsibility: DS Maintain
7. Subject Content:
7.1 SMIC Standard I/O Library Application Notes
Notice
©2012 Copyright.
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Library Application Notes (Ver4p1) O.I.
TABLE OF CONTENTS
7.1 SMIC Standard I/O Library Application Notes ............................................................................................2
7.2 Introduction ......................................................................................................................................................5
7.2.1 The Outline of the Document ......................................................................................................................................5
7.2.2 Input Sequence of Libraries for Synthesis ...................................................................................................................5
7.3 I/O and Bonding Pad........................................................................................................................................5
7.3.1 I/O Layout and Power/Ground rails.............................................................................................................................5
7.3.2 Bonding pad and Its Placement....................................................................................................................................6
7.3.2.1 Non-DUP I/O Bonding Pad ......................................................................................................................................6
7.3.2.2 DUP I/O Bonding Pad.............................................................................................................................................10
7.4 Digital and Analog Power Supply Cells........................................................................................................13
7.4.1 Digital Power Supply Cells........................................................................................................................................14
7.4.1.1 Digital domain for library without PVDD2PUDC cell...........................................................................................15
7.4.1.2 Digital domain for library with PVDD2PUDC cell ................................................................................................16
7.4.2 Analog Power Supply Cells .......................................................................................................................................17
7.4.2.1 Families of Analog Power Supply Cells .................................................................................................................17
7.4.2.2 Analog Power/Ground Supply Cells Configuration................................................................................................19
7.4.3 Analog I/O cells .........................................................................................................................................................22
7.4.4 Analog Cells within Digital Domain..........................................................................................................................23
7.4.5 Digital Cells within Analog Domain..........................................................................................................................23
7.5 Power-Up and Power-Down Sequence .........................................................................................................24
7.5.1 The sequence for library without PVDD2PUDC cell ................................................................................................24
7.5.2 Sequences for library with PVDD2PUDC cell ..........................................................................................................25
7.6
I/O Power/Ground Bus Connection Cells .............................................................................................25
7.6.1 I/O Power/Ground Cell ..............................................................................................................................................25
7.6.2 Filler Cell and Corner Cell.........................................................................................................................................25
7.6.3 Transition Cell ...........................................................................................................................................................26
7.7
Open Drain Application Note.................................................................................................................26
7.8
Oscillator I/O Application Note..............................................................................................................27
7.8.1 Oscillating Circuits ....................................................................................................................................................27
7.8.2 Continuity test method...............................................................................................................................................28
7.8.3 Noise immunity for Oscillator I/O .............................................................................................................................28
7.9
Electromigration for Power I/O Pads....................................................................................................29
7.10 Simultaneously Switching Outputs (SSO)..................................................................................................30
7.10.1 Ground Bounce Effect .............................................................................................................................................30
7.10.2 I/O Power/Ground Cell Number Calculation...........................................................................................................32
7.10.3 Tips to Reduce SSN .................................................................................................................................................33
7.10.4 SSO Simulation Model and Driving Factor .............................................................................................................34
7.11
Electrostatic Discharge Considerations.................................................................................................35
7.11.1 Power Supply Cell Placement..................................................................................................................................35
7.11.2 Dummy Power/Ground Cells...................................................................................................................................36
7.11.3 Power Cut Cells .......................................................................................................................................................37
7.11.4 Tie high/Tie low .......................................................................................................................................................40
7.11.5 ESD protection devices in core area ........................................................................................................................40
7.11.6 I/O cell to digital/analog interfaces ..........................................................................................................................41
7.11.7 I/O Cell with IP macros............................................................................................................................................43
The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in
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Library Application Notes (Ver4p1) O.I.
7.11.8 Layout of devices connected directly to IO pad.......................................................................................................45
7.11.9 Secondary ESD devices ...........................................................................................................................................45
7.11.10 ESD and Floorplan Consulting Service .................................................................................................................45
7.12 SMIC Standard IO LVS Verification..........................................................................................................45
7.13 I/O Library Tape-out Layer Integration ....................................................................................................46
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7.2 Introduction
SMIC Standard I/O Library offers a great deal of I/O flexibility. This document describes the
application of SMIC Standard I/O Library. It provides a general guideline to the application of
SMIC Standard I/O Library.
7.2.1 The Outline of the Document
The outline of the following chapters is presented in this section:
Chapter 3 describes SMIC standard I/O layout configuration and structure, bonding pad structure,
such as in-line and stagger bonding pad. Bonding pad placement is also addressed in detail.
Chapter 4 introduces the main power supply cells. The basic concept and structure of SMIC
Standard I/O Library’s analog and digital power supply cells are explained. Various types of analog
I/O cells for low and high frequency applications are also presented.
Chapter 5 highlights power up/down sequence to avoid the latch-up issue since I/O library uses
different voltage supplies for pre-driver and post driver.
Chapter 6 illustrates non-signal I/O cells, such as I/O power/ground cells, filler and corner cells.
Chapter 7 explains open drain application of I/O library without tolerance.
Chapter 8 addresses oscillators of I/O cells.
Chapter 9 checks the maximum allowable currents for power I/O pad in consideration to
electromigration effects.
Chapter 10 presents general information and guideline to the reduction of simultaneous switching
outputs (SSO) or ground bounce effect.
Chapter 11 discusses the ESD protection methodology with emphasis on the functionality of power
cut cells, dummy power/ground cells, tie-high and tie-low cells and core protection cells used in chip
core area, analog-digital interface and IP macros (i.e. Phase Lock Loop (PLL) )
Chapter 12 presents LVS verification.
Chapter 13 recommends the preferred tape-out steps.
7.2.2 Input Sequence of Libraries for Synthesis
When different synthesizers or static timing analysis tools (such as Design Compiler, RTL Compiler
and PrimeTime) are used, user may notice different timing delays in the same library. To avoid this
kind of issue, SMIC recommends user to input Standard Cell synthesis library first and Standard
I/O synthesis library afterwards.
7.3 I/O and Bonding Pad
This chapter covers I/O layout structure including power/ground rails, the bonding pad, either
in-line or stagger style and the placement of these pads.
7.3.1 I/O Layout and Power/Ground rails
SMIC Standard I/O structure is composed of pre-driver and post-driver section shown in the figure below.
Each section has its own function. Pre-driver provides logic operation for I/O circuit, while post-driver
provides large driving capability and ESD protection. Customer can add metal dummy if there are no
dummy block layers in I/O cells.
The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in
whole or in part without prior written permission of SMIC.
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Library Application Notes (Ver4p1) O.I.
Non-DUP I/O Cell
DUP I/O Cell
VDD
Pre-driver
Pre-driver
VSS
VDD25
VSSD
VDD25
Post-driver
Post-driver
VSSD
VDD25
PAD
VSSD
Pad
Figure 7.3.1.1 Layout structure of Non-DUP I/O cell and DUP I/O cell
7.3.2 Bonding pad and Its Placement
Different SMIC I/O libraries provide different types of bonding pad cells. Refer to specific SMIC
I/O data book for the full list of the bonding pads.
SMIC offers different pitches for IO cells. The pitch is defined as cell width of the I/O plus the
space between two adjacent I/O cells.
When bonding pads are included with SMIC I/O cells, the library will not provide any additional
bonding pad cells. But when bonding pads are not included with SMIC I/O cells, additional
bonding pad cells are supplied and users must attach these pads to the cells for themselves.
Basically, there are two types of I/O cells with the different placement of pads: Non-DUP I/O and
DUP I/O. They will be explained in the following sections.
7.3.2.1 Non-DUP I/O Bonding Pad
There are two bonding styles in Non-DUP I/O library: stagger style and in inline style.
1) For stagger style, both PADI40 and PADO40 pad cells are used.
2) For inline pad style, different bonding pad can be used according to the required PAD pitch.
Table 7.3.2.1 Non-DUP I/O bonding pad
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Bonding Pad
Stagger style
Inline style
PAD pitch
(Minimum)
PADI40&
PADO40
√
40um
PADI45 PADI50 PADI55
PADI60 PADI65
√
45um
√
60um
√
50um
√
55um
√
65um
Caution:
Pad cells have the same width of Place and Route (P&R) boundary (gds layer# 127) as the IO cells. When
pad cell is attached to I/O cell, leave no space between their Place and Route boundaries. So the pad
appears to be an extension of IO cell.
The following two sketches (Figure 7.3.2.1 and Figure 7.3.2.3) show how to stitch I/O cells and bonding
pads together along their P&R boundaries. The layout corresponding to each sketch is also shown in
Figure 7.3.2.2 and Figure 7. 3.2.4.
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Library Application Notes (Ver4p1) O.I.
I/O cell
Filler
cell
I/O cell
PAD pitch
(80um)
No space left
between I/O cell
boundary and
bonding pad’s
boundary
I/O cells boundary
(in Blue)
PADO40
PADO40
Bonding pad
boundary
(in Orange)
Figure 7.3.2.1 Inline pad placement with Non-DUP I/O cell (sketch)
Figure 7.3.2.2 Inline pad placement with Non-DUP I/O cell (layout)
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Library Application Notes (Ver4p1) O.I.
I/O cell I/O cell I/O cell I/O cell
PAD pitch
(40um)
No space left
between I/O cell
boundary and
bonding pad’s
boundary
I/O cells boundary
(in Blue)
Bonding pad
boundary
(in Orange)
PADO40 PADI40
PADO40 PADI40
Figure 7.3.2.3 Staggered pad placement with Non-DUP I/O cell (sketch)
Figure 7.3.2.4 Staggered pad placement with Non-DUP I/O cell (layout)
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7.3.2.2 DUP I/O Bonding Pad
This section shows two examples of DUP I/O library; one in stagger pad style and the other in inline
pad style.
1) For stagger pad style, the user can use the combination of PADI30 and PADO30 pad cell.
2) For inline pad style, different bonding pad can be used according to the required PAD pitch.
Table 7.3.2.2 DUP I/O bonding pad
Bonding Pad
PADI30& PADO30
Stagger style
Inline style
PAD pitch (Minimum)
√
30um
PADO50
PADO55
√
50um
√
55um
Caution:
The user should attach bonding pad to the I/O cell according to the following rules:
The origin of bonding pad’s boundary (gds layer# 127) should coincide with that of I/O cell’s (gds
layer# 127) without any rotation or flip.
The following two sketches (Figure 7.3.2.5 and Figure 7.3.2.7) show how to place I/O cells and
bonding pads together. The real layout in Figure 7.3.2.6 and Figure 7.3.2.8 are appended after the
sketches respectively.
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Library Application Notes (Ver4p1) O.I.
I/O
cell
Fille
r cell
I/O
cell
PAD pitch (60um)
The origins of their
boundaries should
coincide to each other.
I/O cells boundary
(in Blue)
PADO30
PADO30
Bonding pad
boundary
(in Orange)
Figure 7.3.2.5 Inline pad placement with DUP I/O cell (sketch)
Figure 7.3.2.6 Inline pad placement with DUP I/O cell (layout)
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I/O cell I/O cell I/O cell I/O cell
I/O cells
boundary
(in Blue)
PAD pitch (30um)
The origins of their
boundaries should
coincide to each
other.
PADI30
PADI30
PADO3
0
PADO3
0
Bonding pad
boundary
(in Orange)
Figure 7.3.2.7 Staggered pad placement with DUP I/O cell (sketch)
Figure 7.3.2.8 Staggered pad placement with DUP I/O cell (layout 1)
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Figure 7.3.2.9 Staggered pad placement with DUP I/O cell (layout 2)
7.4 Digital and Analog Power Supply Cells
This chapter covers the basic concept and structure of SMIC Standard I/O analog and digital
power supply cells and Analog I/O cells and can be used as a general application guide and data
book. Note different SMIC I/O libraries contain different components.
Considering the circuit performance and ESD protection, it is necessary to ensure that the core
is supplied with at least two pairs of power/ground cells on each side of the chip in digital or
analog power domain. This requirement holds true regardless of whether or not the core is already
supplied with a voltage regulator.
The SMIC analog IO library is specially designed for SMIC mixed mode macros.
SMIC does not recommend customers to use this library to interface with non-SMIC
analog macros. Misuse of the analog library may cause damages to customer’s chip.
Digital IO and analog IO cells should not be used in mix in the same domain.
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7.4.1 Digital Power Supply Cells
This section explains various types of Digital Power Supply Cells in SMIC Standard I/O library:
PVDD1, PVDD1CE, PVDD2, PVDD2CE, PVDD2PUDC, PVSS1, PVSS2, and PVSS3.
PVDD1 and PVSS1 are power and ground cell respectively for pre-driver and core.
PVDD2 and PVSS2 are power and ground cell respectively for post-driver.
PVSS3 is the combination of PVSS1 and PVSS2. In this case, power supply cell PVSS3 is used to
connect different VSS ground lines (VSS and VSSD).
PVDD1CE is a digital power cell for core ESD protection without bonding pad and doesn’t require
a bonding pad. The same for PVDD2CE cell used for I/O ESD protection.
PVDD2PUDC cell supplies digital power to post-driver, which also generates FP and FPB signals to
it.
Usually IO power supply gets powered up before the core power supply. Since the logic level
(achieved by core power supply) to drive the post driver (powered by IO power supply) is not ready,
the PMOS and NMOS of the post driver may be conductive at the same time and generate big
currents. To avoid short circuit current, SMIC Standard IO library utilizes FP/FPB signal to turn off
I/O cell’s post driver circuit when post driver gates are not conditioned. “PUDC” (power up detecting
circuit) is employed in this scheme included in different power cell for different SMIC I/O library,
and it can activate the FP/FPB signal. FP stands for ‘From Power Pad’ and FPB is the complement of
FP signal. FP/FPB pins are global signals. Under normal condition, FP is activated by dedicated
power cell turned to ‘HIGH’ voltage level, while FPB is activated by the same cell turned to ‘Low’
voltage level (0V). FP and FPB rails will be automatically connected while the digital I/O cells are
merged together.
For the library without PVDD2PUDC cell, PVDD2 cell contains PUDC that generates FP and FPB
signals in general. In rare cases, cell other than PVDD2 would have PUDC. For the library with
PVDD2PUDC cell, PVDD2PUDC cell contains PUDC. User should refer to specific SMIC I/O data
book for more details.
If SMIC standard I/O library contains PVDD2PUDC cell, it is strongly recommended to place only
one PVDD2PUDC with multiple PVDD2 cells in each domain rather than multiple PVDD2PUDC
cells. By doing so, FP/FPB signal can only be generated by a single PVDD2PUDC cell so as to avoid
FP/FPB signal contention. If PVDD2PUDC cell is present in standard I/O library, only
PVDD2PUDC cell can generate FP/FPB signals, PVDD2 cell can’t.
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7.4.1.1 Digital domain for library without PVDD2PUDC cell
Figure 7.4.1.1.1 Digital power/ground cells connected to power/ground rails
Recommended digital domain IO cell configurations are listed:
1. PVDD1 + PVSS1 + PVDD2 + PVSS2 + [Digital I/O cells] + [Analog cell within digital domain]
+ ……
2. PVDD1 + PVDD2 + PVSS3 + [Digital I/O cells] + [Analog cell within digital domain] + ……
Note: cell in [] is optional.
PANA1ANP
PBCU8
PVSS2
PVDD2
PVSS1
PVDD1
Figure 7.4.1.1.2 A placement example of digital power/ground and IO cell in a digital domain without
PUDC cell
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7.4.1.2 Digital domain for library with PVDD2PUDC cell
Figure 7.4.1.2.1 Digital power/ground cells connected to power/ground rails
Recommended digital domain IO cell configurations are listed:
3. PVDD1 + PVSS1 + PVDD2PUDC + PVDD2 + PVSS2 + [Digital I/O cells] + [Analog cell within
digital domain] + ……
4. PVDD1 + PVDD2PUDC + PVDD2 + PVSS3 + [Digital I/O cells] + [Analog cell within digital domain]
+ ……
Note: cell in [] is optional.
One PVDD2PUDC and multiple
PVDD2 in each domain
PBCU8
PVDD2PUDC
PVSS2
PVDD2
PVDD2
PVDD2
PVSS1
PVDD1
Figure 7.4.1.2.2 A placement example of digital power/ground and digital I/O cell in a digital domain
with PVDD2PUDC
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7.4.2 Analog Power Supply Cells
This chapter introduces analog power supply cells that should be placed in analog domain. There
are three types of power supply cell combinations being shown in Figure 7.4.2.1. The purpose of
developing three families of components is to provide noise free power specifically for analog
application. Some library has PVPP power cell, which is used for testing only.
7.4.2.1 Families of Analog Power Supply Cells
PVDD3AP is used to supply power to core, pre-driver and post drivers, and is equivalent to
PVDD1AP + PVDD5AP. Furthermore, PVDD5AP can be replaced by PVDD4AP+PVDD2AP.
PVDD1AP1 is distinguished from PVDD1AP by using a different power/ground rail for ESD
devices. The detailed description and power connection of these cells are listed in Table 7.4.2.1.
PVSSxAPx are similar to PVDDxAPx, except they supply ground. They must be paired with power
cells in the same family.
Family 1
Family 2
PVDD1AP
PVDD1CAP
PVDD3AP
PVDD3CAP
Family 3
PVDD1AP1
PVDD1CAP1
PVDD4AP
PVDD5AP
Analog
Power
Supply
Cells
PVDD2AP
PVSS1AP
PVSS1CAP
PVSS3AP
PVSS3CAP
PVSS1AP1
PVSS1CAP1
PVSS4AP
PVSS5AP
PVSS2AP
Figure 7.4.2.1.
Families of Analog Power/Ground Supply Cells
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Table 7.4.2.1 Analog Power Supply Cells, Connections and Descriptions
Cell Name
Ports to core/ Pre-driver
Description
Ports to
Power/
bonding pad
Post-driver
Power
PVDD1AP
SVDD1AP/
SAVDD/
Power supply for core logic
>Core voltage
SVDD1AP
SAVDD
only, protecting IO device.
PVDD1CAP
SVDD1CAP/ SAVDD/
Power supply for core logic
<=Core Voltage SVDD1CAP SAVDD
only, protecting core device.
PVDD1AP1
SVDD1AP1/ SAVDD /
Resemble PVDD1AP but use
>Core Voltage
SVDD1AP1
SAVDD33 different post-driver power
PVDD1CAP1
SVDD1CAP1/ SAVDD/
Resemble PVDD1AP but use
<=Core Voltage SVDD1CAP1 SAVDD33 different post-driver power
PVDD4AP
(Null)/
SAVDD/
Power supply for pre-driver
SAVDD
SAVDD33 only, also protects IO device.
PVDD5AP
(Null)/
SAVDD/
Power supply for both preSAVDD
SAVDD
and post-driver
PVDD2AP
(Null)/
SAVDD/
Power supply for post-driver
SAVDD33
SAVDD33 only, protects IO device.
PVDD3AP
SAVDD/
SAVDD/
Power supply for core，
，
>Core Voltage
SAVDD
SAVDD
pre-driver and post-driver
PVDD3CAP
SAVDD/
SAVDD/
Power supply for core，
，
<=Core Voltage SAVDD
SAVDD
pre-driver and post-driver
PVDD1ANP
SVDD1ANP/ VDD/
Power supply for core logic
>Core voltage
SVDD1ANP VDD33
only used in digital power
domain
PVDD1CANP
SVDD1CANP/ VDD/
Power supply for core logic
<=Core voltage SVDD1CANP VDD33
only used in digital power
domain
Note: “>Core Voltage“ means that the voltage of port connected to pad is higher than core voltage.
“<=Core Voltage“ means that the voltage of port connected to pad is equal to or lower than core voltage. Typical Core
Voltages: 1.8Vfor 0.18µm process, 1.5V for 0.15µm process, 1.2V for 0.13µm Generic process and 1.1V for 40nm Low
Leakage process. For example, for 0.18µm I/O(core voltage is 1.8V), if the voltage of port connected to pad is higher
than 1.8V, PVDD1AP should be used; if the voltage of port connected to pad is equal to or lower than 1.8V, PVDD1CAP
should be used instead. Any misuse could damage to user’s circuit and make the chip malfunctioning. In other words, the
user should pay close attention to the voltage of port connected to pad and choose the right cell.
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7.4.2.2 Analog Power/Ground Supply Cells Configuration
The recommended analog domain IO cell configurations are listed below; refer to next section for analog
I/O cells.
1. PVDD3AP + PVSS3AP + [PANA1AP] + …..
2. PVDD3CAP + PVSS3CAP + [PANA1CAP] + ……
3. PVDD3AP + PVSS3AP + [PVDD1AP] + [PVSS1AP] + [PANA1AP] + ……
4. PVDD3AP + PVSS3AP + [PVDD1CAP] + [PVSS1CAP] + [PANA1AP] + ……
5. PVDD3CAP + PVSS3CAP + [PVDD1CAP] + [PVSS1CAP] + [PANA1CAP] + ……
6. PVDD5AP + PVSS5AP + [PVDD1AP] + [PVSS1AP] + [PANA1AP] + ……
7. PVDD5AP + PVSS5AP + [PVDD1CAP] + [PVSS1CAP] + [PANA1AP] + ……
8. PVDD4AP + PVSS4AP + PVDD2AP + PVSS2AP + [PVDD1AP1] + [PVSS1AP1] + [PANA1AP1] +
[PANA2AP1] + ……
9. PVDD4AP + PVSS4AP + PVDD2AP + PVSS2AP + [PVDD1CAP1] + [PVSS1CAP1] + [PANA1AP1]
+ [PANA2AP1] + ……
An example of analog power/ground and I/O cell placement is shown in Figure 7.4.2.2. And several
examples below illustrate how to use these three families in Figure 7.4.2.3, 7.4.2.4, 7.4.2.5 and
7.4.2.6.
Figure 7.4.2.2 An example of analog power/ground and analog I/O cell placement
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Family 1:
PVDD3AP and PVSS3AP cells supply power and ground to core, pre-driver and post-drivers with the same
voltage. Note the voltage level of PVDD1AP should not be higher than that of PVDD3AP.
Figure 7.4.2.3. PVDD3AP and PVSS3AP with other I/O cells
PVDD3CAP and PVSS3CAP cells supply power and ground to core, pre-driver and post-drivers with the
same voltage. The voltage level of PVDD1CAP should not be higher than that of PVDD3CAP.
Figure 7.4.2.4. PVDD3CAP and PVSS3CAP with other I/O cells
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Family 2:
The voltage level of PVDD1AP should not be higher than that of PVDD5AP.
Figure 7.4.2.5. PVDD5AP and PVSS5AP with other I/O cells
Family 3:
The voltage level of PVDD1AP1 and PVDD1CAP1 should not be higher than that of PVDD2AP.
Figure 7.4.2.6 PVDD4AP, PVSS4AP, PVDD2AP and PVSS2AP with other I/O cells
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7.4.3 Analog I/O cells
SMIC Standard I/O Library contains analog I/O cells shown in the table below. PANA1AP and
PANA2AP have the same structure as PANA1AP1 and PANA2AP1 except that the power of
pre-driver and post-driver are the same for the former, different for the latter. The table below has
more details about these differences.
Table 7.4.3.1 Analog I/O pad category
Cell Name
Port#1 Pre-driver supply;
Post-driver supply#2
PANA1AP
Low
PAD SAVDD/SAVSS;
SAVDD/SAVSS
Low
PAD SAVDD/SAVSS;
SAVDD/SAVSS
Low
PAD SAVDD/SAVSS;
SAVDD33/SAVSSD
High
PAD SAVDD/SAVSS;
SAVDD/SAVSS
High
PAD SAVDD/SAVSS;
SAVDD/SAVSS
High
PAD SAVDD/SAVSS;
SAVDD33/SAVSSD
High
PAD SAVDD/SAVSS;
SAVDD/SAVSS
PANA1CAP
PANA1AP1
PANA2AP
PANA2CAP
PANA2AP1
PANA4AP
PANA3AP
PAD SAVDD/SAVSS;
SAVDD/SAVSS
PANA1ANP PAD VDD/VSS;
VDD33/VSSD
PANA1CANP PAD VDD/VSS;
VDD33/VSSD
Frequency
Range#3
Domain
Protected devices#4
Analog I/O devices
Analog Core devices
Analog I/O devices
Analog I/O devices
Analog Core devices
Analog I/O devices
Analog I/O devices; (With
High
higher sustainable
current than
PANA2AP)
Analog I/O devices;
(Tolerance
application#5)
Low
Digital I/O devices
Low
Digital Core devices
Note: #1: All analog I/O cell’s ports are connected to core and bonding pad.
#2: Pre-driver Power/Ground is listed before post-driver Power/Ground in the table.
#3: Low frequency range is up to 100MHz, high frequency range is 100MHz and above.
#4: Only PANA1CAP, PANA2CAP and PANA1CANP can protect core devices.
#5: 5V tolerance for 3.3 I/O Application; 3.3V tolerance for 2.5V I/O Application
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Caution:
1) PANA1AP and PANA1ANP are for analog signal higher than core logic, while PANA1CAP and
PANA1CANP are for analog signal equal to or lower than core logic. PANAxAPx and
PANA1ANP cells are designed to protect I/O device only, and PANAxCAPx and PANA1CANP
cells are designed to protect core device only.
2) There is no resistor in analog I/O cells. So for ESD consideration, the user should add resistor to
his circuit if necessary. Refer to I/O cell section with digital/analog interfaces for details.
3) PANA3AP IO cell: 5V tolerance means the maximum allowable signal voltage is 5V, NOT power
supply voltage (such as USB VBus); 3.3V tolerance means the maximum allowable signal
voltage is 3.3V, NOT power supply voltage.
7.4.4 Analog Cells within Digital Domain
There are analog power supply cells and I/O cells which can be used within digital power domain, please
refer to the section above for details.
PVDD1ANP and PVDD1CANP are analog power cells within digital power domain.
PVSS1ANP and PVSS1CANP are analog ground cells within digital power domain.
PANA1ANP and PANA1CANP are analog IO cells for low frequency application within digital domain.
PANA2ANP are analog IO cells for high frequency application within digital domain.
7.4.5 Digital Cells within Analog Domain
In some library there is one digital power supply cell PVSS4CAP which can be used within analog power
domain.
PVSS4CAP is one digital VSS ground pad within analog power domain for core supply. Use this cell in
analog domain and bond it to improve cross-domain ESD performance.
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7.5 Power-Up and Power-Down Sequence
7.5.1 The sequence for library without PVDD2PUDC cell
SMIC Standard I/O Library uses different voltage supply for pre-driver and post driver. For full chip
Electro Static Discharge (ESD) protection design, multiple voltage ESD clamping circuits have to be
adopted. The presence of PMOS in core power supply cell will cause a parasitic diode between core
power rail (VDD) and I/O power rail (VDD25) as shown in Figure 7.5.
Higher Voltage
VDD25
Parasitic
Diode
Lower Voltage
VDD
Figure 7.5 Parasitic Diode creates a forward current path from core to I/O power rail
If lower voltage power rail is turned on earlier than the higher voltage power rail, a serious latch-up issue
may occur. The path created by parasitic diode may activate latch-up in chip. To prevent this parasitic
diode from latching-up, this chapter introduces standard power-up and power-down sequence that must be
observed.
Power-Up Sequence:
Method: Turn on Higher Voltage Rail first
We can avoid activating the parasitic diode shown in previous page by turning on higher voltage power
rail before lower voltage power rail. However, if the delay time between the turn-on of higher voltage rail
and lower power rail is really long, some reliability issues may arise: Firstly, unpowered lower voltage
rail will drive post-driver circuit into an unknown state. A short circuit current may be created in
post-driver which degrades the circuit performance. Secondly, there might be bus contention of IO cell
when only higher voltage power rail is turned on.
Power-Down Sequence:
The degradation factors such as latch-up and reliability issues are not so important in power-down
sequence. The main concern for power-down sequence is the minimum degree of power consumption
with regard to the transient current. This can be approached by applying power-down sequence in
reversed order of power-up sequence. Please refer to the example below for more details.
The Example:
If power-up sequence is turning on higher voltage power rail first, then turning off lower voltage power
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rail first in a power-down sequence.
7.5.2 Sequences for library with PVDD2PUDC cell
Because there is no PMOS in core power supply cell of the Standard I/O Library with PVDD2PUDC cell,
we can have the power-up and power-down sequence in any order.
Power-Up Sequence:
Method 1: Turn on higher voltage power rail first then lower voltage power rail.
Method 2: Turn on lower voltage power rail first then higher voltage power rail.
Power-Down Sequence:
Method 1: Turn off higher voltage power rail first then lower voltage power rail.
Method 2: Turn off lower voltage power rail first then higher voltage power rail.
7.6 I/O Power/Ground Bus Connection Cells
In SMIC Standard I/O library, there are several I/O power/ground bus connection cells. Fillers and corner
cells have neither pad to off chip circuit nor port to internal core circuit. They have no function either.
They are used for power/ground bus rail connections only.
7.6.1 I/O Power/Ground Cell
The functionality of the I/O power/ground cells will be discussed in Chapter 11. Please refer to Chapter
11.2 for more details.
7.6.2 Filler Cell and Corner Cell
Filler cell is a power and ground rail used to connect various types of I/O cells. There are two kinds of
filler cells in SMIC Standard I/O library design kit: digital filler cell (PFILLx) and analog filler cell
(PFILLxA). The digital filler cell has VDD, VSS, VSSD, VDD25, FP and FPB power and ground rails
and analog filler cell has SAVDD, SAVSS power and ground rails. The corner cell (PCORNER) is used
for power/ground bus connection around the chip corners.
The following rules should be observed to choose filler cells for cascading I/O cells.
In the case of:
a) Fill two digital I/O cells or power cut cells by digital filler cell PFILLx.
b) Fill two analog I/O cells or power cut cell with analog IO cell by analog filler cell PFILLxA.
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c) Consider wider filler cell first when choosing filler cells. For example, choosing PFILL10/PFILL10A
and PFILL2/PFILL2A is better than six PFILL2/PFILL2A filler cells to fill up the space between I/O
cells.
7.6.3 Transition Cell
SMIC translation I/O library is used to translate from one SMIC I/O library to another SMIC I/O library.
Please look up translation I/O library for more details.
7.7 Open Drain Application Note
SMIC Standard I/O library supports open drain application by non tolerant I/O library. When
OEN control pin is connected to I input pin, the cell can be used for open drain application, in
which case the external pull-up device must be present. In Figure 7.7 Rup is external pull-up
resister, CLoad is loading capacitance.
External power supply
SMIC I/O Cell
Rup
CLoad
Figure7.7 Open Drain application
Truth Table for Open Drain Application
Input
OEN
0
1
I
0
1
Output
PAD
0
1
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7.8 Oscillator I/O Application Note
In this Chapter, oscillator I/O cell usage and application are presented. The circuit for fundamental mode
oscillation is also included in this chapter for reference.
For 55nm,65nm,90nm,130nm,180nm and etc. processes, there are six oscillator I/O cells in SMIC
Standard I/O library: PXWE1/2/3 and PX1/2/3. The oscillator I/O cells are designed to oscillate with
crystal samples in the frequency range of 2MHz to 10MHz (PXWE1/PX1), 10MHz to 20MHz
(PXWE2/PX2) and 20MHz to 30MHz (PXWE3/PX3) in fundamental mode. PXWE1/2/3 are
distinguished from PX1/2/3 by the presence of an enable signal. PXWE1/2/3 are oscillator cells with an
active high enable signal and feedback resistor while PX1/2/3 are oscillator cells with feedback resistor
only.
For 40nm process, there are four oscillator I/O cells in SMIC Standard I/O library: PXWE3/PXWE3LIN
and PX3/PX3LIN. The oscillator I/O cells are designed to oscillate with crystal samples in the
frequency range of 2MHz to 30MHz in fundamental mode. PXWE3/PXWE3LIN is distinguished from
PX3/PX3LIN by the presence of an enable signal. PXWE3LIN is an oscillator cell with an active high
enable signal and feedback resistor while PX3LIN is an oscillator cell with feedback resistor only. Both
PXWE3LIN and PX3LIN are bonded in inline style. Conforming to crystal specifications is very critical
to select an oscillator I/O cell correctly.
To turn on the oscillator, the oscillating circuit must provide the negative resistance (-Re) at least five
times the equivalent series resistance (ESR) of the crystal sample. The larger -Re value, the faster
oscillating circuit will be turned on. Higher gm providing larger -Re is able to start oscillation when
crystal has larger ESR if the load capacitance (CL) is the same. However, this consumes more power.
There are two key parameters governing the turn on of oscillator: CL and the maximum ESR at the target
frequency. By reducing the CL, thus increasing -Re, shorter turn on time can be achieved. However, if CL
is too small, the deviation from the target frequency becomes significant because of the relative large
capacitance variation. There is a trade-off between short turn on time and small frequency deviation when
picking CL value in a design. The crystal sample with smaller ESR can also reduce turn on time, however
the price is dear. Table 7.8 is typical values of CL and ESR at certain oscillating frequency.
Table 7.8 Typical values of CL and ESR under certain oscillating frequency
Target Freq (Hz)
2M-3M 3M-6M 6M-10M
10M-20M 20M-30M
CL (pf)
25
20
16
12
8
Maximum ESR (ohm)
1K
400
100
80
40
7.8.1 Oscillating Circuits
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Figure 7.8 Oscillating circuit for fundamental mode
Figure 7.8 is the main part of the oscillator schematic. Resistance of feedback resistor (Rf), damping resistor
(Rd), loading C1 and C2 are used to adjust the turn on time, the stability and the accuracy of the oscillator.
Rf is used to bias the inverter in the high gain region. It can’t be set too low or the loop may not oscillate.
For mega Hertz range applications, Rf of 1Mohm is normal. Rd is used to increase stability, lower power
consumption, suppress the gain in high frequency region and also reduce -Re of the oscillator. Thus, a
proper Rd should never be too large to stop the loop oscillation. C1 and C2 are determined by the crystal or
resonator CL specification. In the steady state of oscillation, CL is defined as (C1*C2)/(C1+C2). Actually,
the I/O ports, bond pad, and package pin all contribute to the parasitic capacitance of C1 and C2. Thus, CL
can be rewritten as (C1’*C2’)/(C1’+C2’), where C1’=(C1+Cin,stray) and C2’=(C2+Cout,stray). In this case, the
required C1 and C2 can be reduced.
Note: This oscillating circuit is designed for parallel resonation but not series resonation. Because C1, C2,
Rd and Rf are varied with the crystal specifications and the selected oscillator I/O cell, there is no single
set of magic numbers that satisfy all the applications.
Sometimes user is free to use the oscillation output from external oscillator to feed XIN pin of the cell, in
which case there is no need to connect crystal, C1, C2, Rf and Rd. For 65nm/55nm/40nm process in
SMIC Standard I/O library, the crystal oscillator I/O cells have embedded internal resistor, so the user
need not add feedback resistor Rf as above description. For other processes, refer to specific SMIC I/O
library data book whether crystal oscillator I/O cells have internal resistor or not.
7.8.2 Continuity test method
In order to avoid the problem of the floating gate, the following test setup is necessary: when testing the
XIN, connect XOUT pin to ground; when testing the XOUT, ground XIN pin.
7.8.3 Noise immunity for Oscillator I/O
In order to reduce the noise disturbance, please sandwich Oscillator I/O cell between Power and/or
Ground cell.
Please note that, Oscillator output signal is fed into one of the input signal named Reference Clock Signal
(RCK) of the PLL (XIN). This RCK signal should be kept as quiet as possible. Ideally, RCK should be
routed without any other active signals on adjacent layers above or beneath, or within 5 microns of its
neighborhood in the same metal layer.
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Otherwise, RCK should be shielded by PLL’s VSS line. If RCK is for other application in the chip, it
should be buffered close to its source and fed to the non-PLL blocks from this buffer. Keep in mind that
the source of RCK should be as close to the PLL as possible.
7.9 Electromigration for Power I/O Pads
Electromigration (EM) can cause considerable material movements in metals. Because of the
directional movement of atoms caused by the collision of electrons under strong electric field, a slow
displacement of the metal line is observed over the time. This eventually, will result in a
discontinuity in the current-carrying lines. Therefore, EM limits the density of current that flows in
the metals.
SMIC Standard I/O library provides maximum allowable current (mA) information in Appendix of
I/O Library Data Book. This maximum allowable current could be used as a guide to avoid EM in
the conducting metals.
In general, EM failure can be greatly reduced by dropping more vias and widening metal lines at the
connection ports of power/ground cells.
If package’s pin count is limited or EM failure is a concern, it is recommended to assume double
bonding scheme as shown in Figure 7.9.1. By bonding two of the same power/ground pads into a
single package pin, both issues can be addressed simultaneously.
Figure 7.9.1 Two same power/ground pads bonded to a single package pin
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7.10 Simultaneously Switching Outputs (SSO)
Most silicon devices have limitations on the number of simultaneously switching outputs (SSO) that are
permitted between adjacent power pin pairs and/or ground pin pairs, because increasing the number of I/O
pins may introduce more switching noise. Two common noise-related problems encountered by digital
designers are ground bounce and VCCsag. Ground bounce and VCCsag exist in almost every board. SMIC
Standard I/O library is well aware of these phenomena. The I/O cells in SMIC Standard I/O library have
different drive strengths to adapt to different situation.
The purpose of this chapter is to help users to figure out the suitable number of power ground pads in their
design. It also serves as a general guideline to reduce SSO or ground bounce effect.
Please use SSO Application note to derive driving factor value for different processes:
7.10.1 Ground Bounce Effect
Figure 7.10.1 shows a typical connection between a board, a device, and a load for a certain package type. It
illustrates how the device ground bounces when the I/O pins switch from HIGH to LOW. If the I/O pin
switches to HIGH, the load capacitor is charged. When the pin switches from HIGH to LOW, the capacitor
discharges and a current (di/dt) flows from the load capacitor through the inductor L1 to the board ground
(Refer to Figure 7.10.1). This sudden rush of current (di/dt) through parasitic inductor (L2) causes a voltage
bounce between the device ground and the board ground where the degree of bounce can be determined by
the equation V = L2(di/dt).
Although the noise caused by single output switch is usually below input LOW voltage (VIL), it is
possible that the aggregated noise of multiple SSO I/O cells hikes above the logic threshold of subsequent
receiving device. The maximum number of SSO I/O cells that generate noise up to VIL is characterized
by DI, and then DF – the reciprocal of DI, can be determined accordingly. These DI and DF will be
explained in more details in next section.
Also, VCCsag occurs in the same manner as ground bounce, when the outputs switch from LOW to HIGH.
However due to small switch currents in the device, this noise is so small that it can be ignored.
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VCC
L3
I/O
Pin
L1
SSO
I/O
cells
C
Die
Ground
L2
Current (di/dt)
Package
Board
Ground
Figure 7.10.1 Illustration of Ground Bounce
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7.10.2 I/O Power/Ground Cell Number Calculation
In SSO case:
The minimum required number of ground cells in an I/O domain = SDF
The minimum required number of power cells in an I/O domain= (SDF/1.1)
For Non-SSO case, the required number of power/ground cells in an I/O power domain is less than the
SSO case:
The minimum required number of ground cells in an I/O domain = (SDF/1.5)
The minimum required number of power cells for an I/O domain = (SDF/1.6)
SDF stands for “Sum of Drive Factors” where it accumulates the DF values of all the I/O cells within a
power domain of the chip. SDF determines the minimum number of power/ground cells that must be
placed in an I/O power domain to suppress SSO noise.
DF stands for “Driver Factor”, a variable indicating how much the specific output buffer contributes to
the SSN (Simultaneously Switching Noise, caused by Ground Bounce Effects) on a power/ground rail.
The DF value of an output buffer is proportional to di/dt, the derivative of the current on the output buffer
with respect to time. Practically, DF can be obtained as:
DF = 1/DI
Where DI is the maximum number of specific I/O cells switching from high to low simultaneously
without making the voltage on the quiet output “0” higher than “VIL”.
The corresponding DF table is provided by SMIC. The SSO Simulation Model and all parameters for SSO
simulation are listed as well. From DF table, users can easily calculate the required power/ground cell
number in an I/O domain in either SSO or non-SSO case. Several examples are given here to show more
details in calculation:
(1) Check the DF value of each type of I/O cells
The noise occurred at the stable output node is called Quite Output Switching (QOS).
QOS of “VIL” is one of the failure criteria in SSO simulation. If four identical I/O cells with
one ground cell (L2) cause noise of “VIL”, the DI would be 4 and 1/4=0.25 for DF. Users can
check out the DF values, along with their package wiring inductances (L3, L2 and L1).
(2) Calculate the SDF value of whole chip
Once DF of various types of IO is obtained, SDF value will be the summation of those
DFs.
For example, a design that has eight 2mA and 10 12mA non-slew-rate-controlled buffers and 20
24mA slew-rate-controlled buffers with wiring inductance of 5.2nH. The SDF value can be
determined according to the DF table, from which DF values for 2mA, 12mA, and 24mA cells
are 0.014, 0.109, and 0.249 respectively if wiring inductance is 5.2nH. SDF then becomes
(8 × 0.014) + (10 × 0.109) + (20 × 0.249) = 6.182
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(3) The number of required power/ground cells would be:
In SSO case:
Ground cell number = 6.182→7
Power cell number = 6.182/1.1= 5.62→6
So, 7 ground cells and 6 power cells in an I/O domain are required.
In Non-SSO case:
Ground cell number = 6.182/1.5 = 4.121→5
Power cell number = 6.182/1.6 = 3.864→4
Thus, 5 ground cells and 4 power cells are required in an I/O domain.
7.10.3 Tips to Reduce SSN
1. Choose the right output buffer. (Never use stronger buffer than necessary).
2. Always use slew-rate controlled output cell.
3. Insert power and ground cells in an I/O domain as many as possible. It is recommended to separate
output buffers in the middle by power ground cells.
4. Place the noise sensitive I/O cells (such as Oscillator I/O cells, analog I/O cells) away from SSO IOs.
5. Consider double bonding for the duplicated power/ground cells to reduce parasitic inductance of the
pin.
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7.10.4 SSO Simulation Model and Driving Factor
RVCC
CVdd
Quiet
I/O cell
Lpin
LVdd
SSO I/O
cells
Rpin
Vo
Vi
Lpin
Cload
Rpin
Vout
Vin
Cload
Cpin
Cload
A
LVSS
CVSS
RVSS
Figure 7.10.4 SSO Simulation Model
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R, L, C values:
Rvss, Rvdd = Rpin = 0.3 ohms
CVSS, Cvdd = Cpin =4pF
Cload (for 2mA, 4mA IO) = 5pF / 10pF / 25pF
Cload (for 8mA IO) = 10pF / 25pF / 50pF
Cload (for 12mA IO) = 25pF / 50pF / 75pF
Cload (for 16mA, 24mA IO) = 50pF / 75pF / 100pF
LVSS, Lvdd = Lpin = 5.2nH / 7.8nH / 10.5nH
7.11 Electrostatic Discharge Considerations
Electrostatic discharge (ESD) events can lead to field failures if circuits are poorly protected. Therefore, a
systematic approach of ESD protection in design must be followed. It is absolutely necessary to place
proper ESD protection circuits inside each power/ground cell for ESD considerations.
SMIC Standard I/O library has full chip ESD solution to cover all possible ESD attacks. Silicon of a
library must pass JEDEC ESD standard of Human Body Model (HBM) and Machine Model (MM). The
stress modes of test include positive-to-ground (PS), negative-to-ground (NS), positive-to-VDD (PD) and
negative-to-VDD (ND) for both HBM and MM. In PS-mode, a positive discharge pulse is applied to VSS
pin and its related grounds, but the VDD pin and other pins are floated. In NS-mode, a negative discharge
pulse is applied to VSS pin and its related grounds, but the VDD pin and other pins are floated. In PD and
ND modes, a positive/negative discharge pulse is applied to VDD pin and its related powers, but the VSS
pin and other pins are floated.
In this chapter ESD protection methodology in I/O ring, core area and digital/analog interfaces are
explained in detail. Users should follow “SMIC IO Application Check List” in their ASIC chip floorplan.
SMIC also offer IO ESD and floorplan consultation service in this phase.
7.11.1 Power Supply Cell Placement
The VSSD bus resistance from each IO cell to the nearest bonded Power and GND cells should be less
than 1ohm (Estimation: a pair of core power/GND and a pair of I/O power/GND should be added every
500um in an I/O ring).
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7.11.2 Dummy Power/Ground Cells
Although proper ESD protection circuit resides in each power/ground cell, it is still recommended to fill
up the space of IO cells by dummy power/ground cells (e.g. PVDD2, PVSSx, PVDD1CE, PVDD2CE,
PVDDxAP and PVSSxAP) instead of filler cells along an I/O pad ring wherever space is allowed as
shown in Figure 7.11.2. Because these dummy power/ground cells can provide a short ESD discharge
path to improve the ESD performance while filler cells couldn’t.
Users should pay attention to I/O cell PVDD1CE/PVDD2CE:
1). PVDD1CE is a digital VDD power cell for core ESD protection used in digital power domain.
PVDD2CE is a digital VDD power cell for I/O ESD protection used in digital power domain. It is not
necessary to bond PVDD1CE and PVDD2CE cells.
2). For 90nm process and above, it’s preferred to place at least one PVDD1CE cell in each digital power
domain and on each side of a chip.
3).For good core ESD protection, it is strongly recommended to connect PVDD1CE’s pin to chip digital
core area by a wide metal.
Dummy
Power or
Ground
Cell
Figure 7.11.2 Place dummy power or ground cell instead of filler cell for better ESD protection
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7.11.3 Power Cut Cells
In the mixed-mode application circuit, noise that is generated by switches of digital circuit is undesirable,
therefore connecting digital power/ground directly to the power/ground ports of analog circuits is
forbidden. Power cut cells (e.g. P1DIODEx/P2DIODEx/PDIODEx) are designed to separate analog
domain from digital domain to reduce noise disturbance while still maintaining good ESD performance.
As diode number increases from 0 in PDIODE8S, 1 in P1DIODE/P1DIODE8 cell, 2 in P2DIODE /
P2DIODE8 to 3 in PDIODE / PDIODE8 cell, noise is more and more strictly isolated.
Table 7.11.3.1 Power Cut Cells Category
Cell Name
Description of Power Cut Cells
P1DIODE
P1DIODE is similar to PDIODE, but P1DIODE only contains two
single diodes of opposite polarity connected in parallel.
P1DIODE8
P1DIODE8 is similar to PDIODE8, but P1DIODE8 only contains
two single diodes of opposite polarity connected in parallel.
P2DIODE
Power-cut cell for same voltage level between digital and analog
domain, contains four diodes of opposite polarity connected in parallel
between digital and analog post ground
P2DIODE8
Power-cut cell for high voltage drop for different voltage level between
digital and analog domain, contains four diodes of opposite polarity
connected in parallel between digital and analog post ground
PDIODE
Power-Cut Cell for same voltage level between digital and analog
domain, contains six diodes of opposite polarity connected in parallel
between digital and analog post ground
PDIODE8
Power-Cut Cell for High Voltage Drop for difference voltage level
between digital and analog domain, contains six diodes of opposite
polarity connected in parallel between digital and analog post ground
PDIODE8S
Power-Cut Cell for High Voltage Drop for difference voltage level
between digital and analog domain, but shorts ground
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Figure 7.11.3.1 Power Cut Cells Illustrate
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Disconnect power ground rails of analog from digital domain solves the problem of digital noise
disturbance. However, doing so will deteriorate the ESD performance. To compromise the issue, power
cut cells are introduced. Power cut cell connects analog power ground rails to digital through appropriate
number of diodes, providing good isolation of digital power noise while still keeping good ESD discharge
path, thus maintaining good ESD performance. These capabilities are enabled by the diode characteristic,
as diode can be turned on only if the voltage drop across it exceeds its threshold voltage. This effectively
blocks digital noise and also acts as an effective cross-coupling clamp between analog and digital I/O cell
by providing a discharge path through it. This ensures all excessive currents are shunted to bonding pads
through ESD devices and none into the core region should a high ESD voltage is stressed to the I/O cell.
This shall significantly improve the ESD performance.
Figure 7.11.3.2 Layout of power cut cell among two I/O cell.
Figure 7.11.3.2 shows the layout of P1DIODEx/P2DIODEx/PDIODEx between two I/O cells. It should
be noted that the guard bands within the P1DIODEx/P2DIODEx/PDIODEx are disconnected from the left
and right side of the cell. Thus, user should close these gaps of guard rails manually by two metal pieces.
However, only ONE side of the guard rail should be shortened (Refer to Figure 7.11.3.2). The other side
must be left disconnected to separate powers across the power cut cell. Several rules in descending
priority help decide which side should be connected.
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For the Power guard rail:
1. If there is a voltage difference between two sides, always connect bands on the side of higher VDD
voltage.
2. Always make connection on the side with more I/O cells.
3. Since Analog side is less noisy, always make connection on it.
For the Ground guard rail:
1. If there is a voltage difference between two sides, always make the connection on the side of lower
ground voltage.
2. Same as power rail rule above.
3. Same as power rail rule above.
Caution:
1) For ESD consideration there should not be more than 12 total diodes along the post-driver
ground bus loop. Too many diodes could degrade ESD performance and damage the whole
chip.
2) Before LVS check, user should make sure all power cut cells (i.e.
P1DIODEx/P2DIODEx/PDIODEx) have been instantiated in the netlist, with external port
names matching to power ground names on cut cell’s two sides.
3) PDIODE8S cell can be placed between digital power rails or between analog power rails. If it is
placed between digital and analog power rails, LVS error will be reported.
4) Since ground rail of PDIODE8S cell will be automatically connected, only power rail gaps should
be manually closed
7.11.4 Tie high/Tie low
For ESD safety, user must choose tie-high/tie-low cell to condition IO cell pin instead of directly tying the
pin to power/ground. By doing so, input or control pin is kept from floating. Moreover, thin gate load
device is protected by tie-high/tie-low cell from breakdown when an ESD event happens.
7.11.5 ESD protection devices in core area
SMIC provides local ESD protection for core and e-fuse in 65nm and 40nm technology nodes. User
should refer to related SMIC databook (e.g. “SMIC_S65NLL_CP_DataBook”) for more details.
To improve ESD performance of 40nm process, VDD2CE should be placed on power and ground buses
driven by power and ground cells of PVDD1AP/PVSS1AP, PVDD3AP/PVSS3AP, and
PVDD1ANP/PVSS1ANP.
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7.11.6 I/O cell to digital/analog interfaces
This section introduces some ESD protection methods for analog and digital interface.
Users are urged to insert embedded ESD resistors in front of their secondary ESD devices.
Figure 7.11.6.1 Input ESD resistor should be added before secondary ESD device
For long metal line through the interface, ESD protection devices should be added locally to avoid device
damage.
Figure 7.11.6.2 Use ESD protection devices for long interfacing metal line
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ESD protection devices must be present at digital-digital interface, or digital-analog interface.
Solution 1 is to short the power and ground respectively at the interface (Digital1-Digital2 or
Digital1-Analog).
Solution 2 Connect the interface (Digital1-Digital2 or Digital1-Analog) by back-to-back diodes. In
addition ESD protection devices must be added locally to the receiver to avoid device damage.
Figure 7.11.6.3 Add ESD protection devices to interface
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7.11.7 I/O Cell with IP macros
When SMIC I/O cells are used for IP macros, such as ADC (analog-to-digital converter), DAC
(digital-to-analog converter), High Speed IP, LVDS (Low Voltage Differential Signaling), PLL
(Phase Lock Loop) and so on, SMIC strongly recommend users to connect digital power and
ground pins of IP macros to chip digital core power and ground (usually VDD and VSS).
This section provides several place and route tips of Phase Lock Loop (PLL) (SMIC PLL IP Only) driven
by SMIC Standard I/O cell. In an example shown in Figure 7.11.7.1, PDIODE8 power cut cells are
inserted between power pads of PLL and other digital pads to isolate digital power noise. Double bonding
is used at the power pad (AVDD, AVSS) in order to reduce the wire inductance. If possible, it is also
suggested to minimize the bonding wire length of the power/ground pads. The following rules serve as
general guidelines: (Refer to Figure 7.11.7.1 and Figure 7.11.7.2):
1. Place PLL macro at the corner of a chip with its power and ground pins close to the analog power I/O
pads. The routing paths should be kept as short as possible but far away from any other large driver
or frequently switching digital I/O pads. Should user place PLL on the edge instead of the corner of
die, then do allow 100µm distance from other diffusions or wells.
2. Do not place any noisy internal circuits or fast switching output drivers close to PLL macro.
Generally speaking, higher frequency and higher voltage level aggressors generate more noise than
lower frequency low level counterparts.
3. Never place any core-logic power rail over PLL unit. Create dead zone between PLL internal circuit
and all other internal circuits. Physical spacing is a good way of reducing noise coupled through the
chip substrate. A minimum space of 30um between PLL and digital core power rings and a minimum
space of 100um between PLL and any other diffusions or wells of digital core are recommended.
4. Do not lay any core logic power lines or signal lines over that of PLLs.
5. Short PLL’s digital power/ground pins (such as DVDD, DVSS) to chip digital core’s (usually VDD
and VSS). And the metal width in connection should be wider than 10um.
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Figure 7.11.7.1 Suggested Place and Route of PLL
If PLL has dual power supplies (e.g. core power and IO power), PVDD3AP/PVSS3AP are required to
drive PLL’s high power circutry. If PLL has only one power supply, (for example, core power),
PVDD3CAP and PVSS3CAP cells are used to drive PLL’s internal circuitry solely.
User should refer to Chapter 4 “Digital and Analog Power Supply Cells” for more details about the
power/ground rail connection and various power separation schemes.
Figure 7.11.7.2. Suggested Place and Route of PLL
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7.11.8 Layout of devices connected directly to IO pad
In analog IP, if any two terminals of a transistor are connected directly to IO pad, the layout of the
transistor must follow ESD MOS device layout rules strictly. Otherwise, this scenario is forbidden.
7.11.9 Secondary ESD devices
Secondary ESD devices must be inserted between MOS gate and IO pad as direct connection of the two is
forbidden. An embedded ESD resistor must be inserted before any secondary ESD devices such as ESD
N/PMOS and diodes.
7.11.10 ESD and Floorplan Consulting Service
There is another document SMIC_IO_Application_Check_List available for SMIC IO library user. The
document includes a check list table to ensure proper design at floor plan phase to achieve better ESD
performance at chip level. Users must follow every check item listed in the table before tape-out.
SMIC offers PERC (Programmable Electronic Rule Check) design kits to automatically test all check
items listed in SMIC_IO_Application_Check_List. Moreover, customers can use the Mentor Calibre
PERC and PERC design kits to check GDS database by themselves.
Users are encouraged to make requests for floor plan consulting services at their design, P&R, and
tape-out stage. The detailed information and procedure can be found in the file of ‘Floor Plan review
criteria and procedure’.
7.12 SMIC Standard IO LVS Verification
There shouldn’t be any LVS errors reported by Hercules if only one I/O cell is checked at a time.
However, when multiple I/O cells are checked together, Hercules will report ‘short’ errors. These errors
can be effectively removed by promoting both ‘FP’ and ‘FPB’ to global signals in netlist, just like VDD,
VSS and etc. signals. For more details about FP /FPB, please refer to “Digital Power Supply Cells”
section.
For Hercules LVS:
below:
Add FP and FPB as global signals in options part of the runset file as shown
options {
layout_power = {VDD, VDD25……}
layout_ground = {VSS, VSSD……}
layout_global = {VDD, VSS, VDD25, VSSD……}
schematic_power = {VDD, VDD25……}
schematic_ground = {VSSD, VSS……}
schematic_global = {VDD, VSS, VSSD, VDD25, FP, FPB}
}
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7.13 I/O Library Tape-out Layer Integration
Integration of I/O library tape-out layers such as GDSII layer and mask layer is a very important step in
producing I/O mask for tape-out. SMIC believes that correctly preparing the I/O mask for the
customer/user’s tape-out is timing critical. To achieve quick tape-out cycle time and ‘successful first
tape-out’, I/O library tape-out layer integration with SMIC process technology is required.
To correctly tape-out with SMIC Standard I/O library, each user is urged to check carefully before
taping-out.
ESD Mask：
ESD implant layer is essential to 0.25um process and below in SMIC I/O standard library. SMIC
ESD implant mask code is 110 and GDSII number is 41 (Refer to Mask Layer Name Mapping Table).
Please note that for 65nm process and above, this layer requires logical operation of related layers,
however for 40nm process and below, this layer is drawing layer.
8. Attachment: NA
The information contained herein is the exclusive property of SMIC, and shall not be distributed, reproduced, or disclosed in
whole or in part without prior written permission of SMIC.
According to: SMIC Document Control Procedure; Attachment No.: QR-QUSM-02-2001-002; Rev.:1
2008-06-27