Journal of Mechanics, 2020, 37, 134–148
DOI: 10.1093/jom/ufaa022
Regular Article
Parasitic extraction and power loss estimation of power
devices
H.-C. Cheng
, Y.-H. Shen2 and W.-H. Chen2
1
Department of Aerospace and Systems Engineering, Feng Chia University, Taichung, Taiwan, Republic of China
Department of Power Mechanical Engineering, National Tsing Hua University, Hsinchu, Taiwan, Republic of China
∗ Corresponding author: hccheng@fcu.edu.tw
A B ST R A C T
This study aims to characterize the switching transients and power losses of silicon (Si) power metal–oxide–semiconductor field-effect transistor (MOSFET) in an SOT-227 package (hereinafter named “power MOSFET package”) and Si power MOSFET-based three-phase MOSFET
inverter during load cycles through numerical modeling and experimental validation. The three-phase inverter comprises six power MOSFET
packages as switches for brushless direct current motor drive. First of all, three-dimensional electromagnetic analyses are performed to extract
the parasitic parameters of these two power devices. Subsequently, the device model and the previously derived package model of the power
MOSFET are combined together in circuit simulation of a double pulse test (DPT). The calculated waveform profiles and switching times are
compared with those obtained from the DPT experiment. Likewise, an effective compact circuit simulation model of the three-phase six-switch
inverter, considering the parasitic effects, is developed for the switching loss estimation in the first switching interval of the six-step switching
sequence. At last, parametric study is performed to explore, respectively, the influences of some crucial factors on the parasitic inductances and
switching transients of the power MOSFET package and the switching losses of the three-phase inverter.
KEY WOR DS: three-phase power MOSFET inverter, parasitic parameter extraction, power losses, double pulse test
1. IN TRODUCTION
Nowadays, there is a rapid advancement in power semiconductor devices, such as bipolar junction transistors, metal–
oxide–semiconductor field-effect transistors (MOSFETs) and
insulated-gate bipolar transistors (IGBTs), and even widebandgap power electronics such as gallium nitride, silicon carbide (SiC), etc. This has made them usable for a wide range
of engineering applications ranging from renewable power generation, electric drives, high-voltage direct current transmission
to power supplies. As compared to IGBTs, MOSFETs have a
smaller switching loss and a higher switching speed largely because of no storage delay induced by minority carriers, and thus
are more advantageous for use in high switching frequency applications such as transformers, rectifiers, inverters [1] and direct current–direct current (DC–DC) converters [2]. Inverters,
also named direct current–alternate current (DC–AC) converters, have been broadly applied in many industrial applications,
including induction motor drives, traction, standby power supplies and uninterruptible AC supplies. The input DC voltage of
the inverters supplied from the transformation of the AC power
could be from either an independent power source such as battery, fuel cell or solar cell, or the rectified output of a power
supply. Typically, inverters can be classified into two categories:
current source inverter and voltage source inverter. Of these two
categories of inverters, the most widely used is the voltage source
inverter, which is applied to supply a three-phase induction
motor with variable frequency and variable voltage for variable
speed control.
Three-phase bridge inverters that control three-phase asynchronous induction motors are extensively used in high-power
applications, such as AC motor drives and general AC supplies.
In three-phase bridge inverters, the device junction temperature oscillates significantly owing to the considerable change in
the fundamental frequency and phase currents during the load
cycles. In general, power electronics has a junction temperature limit because the power handling ability of power devices
is mainly restricted to the maximum junction temperature rating [3]. Thus, an accurate estimate of the junction temperature becomes extremely critical for a safe and complete operation of power devices. To date, the market growing demands
for high power capacity, high switching frequency operation and
miniaturization are pushing the boundaries of power semiconductor devices/modules toward high power density [4]. High
power density operation of power electronics unavoidably induces great loss of power, including conduction loss resulting
from the on-state resistance and switching loss resulting from simultaneous current and voltage waveforms during the switching state and the influences of input/output capacitance and inductance. Note that high power losses are the main heat sources
of power electronics. The generation of massive heat together
with an extreme operating condition leads to high temperature,
which would, in turn, accelerate the loss of power. The process
would eventually cause thermal instability [5] and eventually
Received: 22 September 2020; Accepted: 23 November 2020
© The Author(s) 2020. Published by Oxford University Press on behalf of Society of Theoretical and Applied Mechanics of the Republic of China, Taiwan. This is an Open Access
article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse, distribution,
and reproduction in any medium, provided the original work is properly cited.
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2
1,∗
Parasitic extraction and power loss estimation of power devices
Chen et al. [19] performed parametric analysis on the effects
of the drain, source and gate inductances on the voltage spike
and switching loss of a power MOSFET in a TO-247 package.
It was found that the voltage spike would be substantially related to the drain and gate inductances, whereas the source inductance would influence the switching losses. It is clear from
the above literature that parasitic effects are essential for an accurate prediction of the switching transients and switching losses;
thus, there is a critical need of comprehensive characterization
of the parasitic parameters. As an illustration, Chen et al. [20]
extracted the parasitic elements of integrated power electronics modules using Maxwell Q3D Extractor. Together with the
device model and the derived parasitic inductances and capacitances, the impedance curves are calculated using Saber. Yuan
et al. [21] explored the parasitic parameters of an IGBT-based
voltage source inverter using Ansoft Q3D Extractor. The characterized parasitic parameters are implemented in an equivalent
circuit model built in PSPICE with the appropriate switch device models for circuit simulation, and their results are compared
with the experimental results. Temperature also has a certain impact on the switching losses of power devices, depending on the
type of power semiconductors. The effects of temperature on
the switching transients and power losses of power devices have
been extensively addressed in the literature. For instance, Sang
[22] found that both the conduction loss of Si power MOSFET and the turn-on loss due to reverse-recovery loss of boost
diode have a positive temperature coefficient. Wang [23] discovered that the turn-on and turn-off losses of Si power MOSFET
rise slightly with temperature, unlike Si IGBT whose switching
losses vary importantly with junction temperature. Ravi [24]
performed power loss analysis of an SiC MOSFET-based power
electronic converter, and evaluated the dependences of switching losses on load current and heat sink temperature. It was found
that switching losses are positively dependent on load current
but negatively proportional to heat sink temperature. Qi et al.
[26] investigated the influence of temperature on the switching
losses of two SiC power MOSFETs and one Si IGBT. They found
that the Si IGBT’s switching losses have a strong positive temperature correlation, but the SiC power MOSFETs have a weak
negative temperature dependence. This result is consistent with
that of Wang [23] for Si MOSFET, but to a much greater extent,
and that of Ravi [24] for SiC MOSFET.
Based on the above literature review, most of the previous
works focus on investigating the temperature dependence of
switching losses of SiC power MOSFETs and Si IGBT-based
power devices. Relatively, there are limited studies on the switching features and switching losses of an SOT-227 packaged power
MOSFET-based three-phase inverter. In this study, we deal with
a numerical and an experimental investigation of the switching
transients and power losses of power devices, namely Si power
MOSFET in an SOT-227 package (hereinafter named “power
MOSFET package”) and Si power MOSFET-based three-phase
MOSFET inverter for brushless DC motor drive during load
cycles. This inverter consists of three phase legs or six power
MOSFET packages as switches. To take account of the parasitic effects due to packaging on the switching transients and
so switching losses of the power devices, the study starts from
three-dimensional (3D) electromagnetic (EM) simulations of
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chip breakdown if the heat dissipation capability is not sufficient. Besides, high temperature might also bring about other
thermal/mechanical issues, such as warpage (see e.g. [6,7]) and
even thermal fatigue reliability [8]. Accordingly, high power density applications face many tough challenges. To enhance the
thermal performance of power devices, additional passive/active
cooling systems could be straightforward and effective, but the
trade-off is increased cost and system size. Additionally, power
loss minimization and thermal management can be a viable alternative to lessen the device junction temperature. Minimization of power losses, including conduction and switching, can
be made through the application of power semiconductors with
low on-state resistances and capacitances. Alternatively, conduction loss can also be minimized through an increased die size;
however, this would increase switching losses due to an increase
in the input capacitance. On the other hand, switching loss is
strongly governed by the turn-on/turn-off delay time, drain current, drain–source voltage, switching frequency and even temperature. The minimization of switching losses continues to
be a key challenge for power device design. Prior to effective
characterization of the junction temperature of power devices
and even minimization of power losses, it is essential to have
a more insightful understanding of their switching characteristics and power losses during the load cycle. In general, the device datasheet provides the switching loss data at certain load
conditions (supply voltage, gate resistance, drain current and
gate–source voltage). However, in an actual inverter, switching
loss may be considerably affected by parasitic parameters, supply
voltage and gate resistance in the current loop. Because it is not
likely that the current design has the same specifications as those
in the datasheet, directly implementing the switching characteristics given in the spec sheet, such as switching time or switching
losses, into the power loss model will bring about significant prediction errors [9].
In recent years, there has been an extensive study on switching loss estimation using experimental, analytical and numerical
models [10–26]. For example, Spaziani [11] introduced a simple
analytical model for switching loss calculation based on piecewise linear turn-on and turn-off waveforms. Clearly, the source
inductance and the nonlinearity of the device capacitances are
not included in the switching loss calculation; as a result, the
predicted results considerably disagree with the experimental
results, especially for high-frequency applications. To improve
the prediction accuracy, Tabisz et al. [13] and Xiong et al. [14]
developed a mathematical model that considers the effects of
gate–drain and gate–source parasitic capacitances to calculate
the switching losses of power MOSFET devices. Presently, due
to the lessening of the parasitic capacitance in the new generation
of MOSFETs, the extent of the influence of parasitic inductance
on switching waveforms is gradually increasing. Illustratively, Bai
et al. [15] introduced an effective model for MOSFET switching
loss estimation by accounting for the effects of drain and source
parasitic inductances. Ren et al. [16] proposed a more accurate
analytical MOSFET switching loss model that takes into account
the nonlinear characteristics of the capacitor of the device and
the parasitic inductance in the circuit. In particular, the current
and voltage ringing effects observed in the switching transients,
which are usually ignored in the previous studies, are included.
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• Journal of Mechanics, 2020, Vol. 37
Figure 1 The power MOSFET-based three-phase inverter system: (a) three-phase bridge inverter and (b) power MOSFET package.
the power devices using ANSYS® Q3D Extractor. Next, the
characterized parasitic inductances from the 3D EM simulation and the nonlinear drain–source voltage-dependent parasitic
capacitances and output characteristics provided in the device
datasheet are combined in circuit simulation of a double pulse
test (DPT) in ANSYS Simplorer to derive the switching features and switching losses. The validity of the proposed electrical
circuit simulation is demonstrated by comparing the calculated
waveform profiles and switching times with those of the DPT
experiment. Furthermore, a compact circuit simulation model
of the three-phase six-switch inverter is developed, which integrates the power MOSFET device model that consists of the output characteristics and the power MOSFET’s parasitic capacitances, and the inverter’s package model. The electrical circuit
simulation of the three-phase inverter during the first switching state of the six-step switching sequence is undertaken, by
which the corresponding switching losses are obtained. Finally,
the dependences of the parasitic inductances and switching transients of the power MOSFET package on the device geometry,
duty cycle and operating temperature, and those of the switching losses of the three-phase inverter on the switching frequency,
resistive load, parasitic inductance and gate resistance are addressed through parametric study. The analysis gives a better insight into the switching features and switching losses of power
devices.
2. POWER MOSFET PACKAGE A ND
THR EE -PH A SE BR ID GE INVERTER
The three-phase inverter, as plotted in Fig. 1a, under investigation contains three legs (one leg for one phase), and each leg
comprises two power MOSFET switching devices (one upper
side switch and one lower side switch) in a three-phase (U, V,
W) bridge topology (Fig. 1b). These two switches in the same
leg operate in a complementary fashion as they could not be
simultaneously turned on to prevent from shorting the input
voltage. In total, there are six power MOSFET switching devices
(i.e. 100 V/350 A power MOSFET), namely three upper side
switches (Q1, Q3, Q5) and three lower side switches (Q2, Q4,
Q6), mounted onto an aluminum (Al) heat spreader for heat dissipation to form the three-phase bridge circuit with six switching arms that can drive and block the current, as displayed in
Fig. 2a. For 120° commutation of a BLDC motor, the commutation sequence with pulse-width modulation (PWM) is controlled using a three-phase bridge inverter. At any switching state,
only two of the six switches, i.e. one of the upper side switches
and one of the lower side switches, are switched on to supply
currents to two of the three-phase windings. The three-phase
six-arm design constitutes a six-step switching operation in each
periodic cycle, schematically plotted in Fig. 2b. The conduction order of the entire switching operation is Q1Q4–Q1Q6–
Q3Q6–Q3Q2–Q5Q2–Q5Q4, and the corresponding current
state is UV, UW, VW, VU, WU and WV. In this investigation,
the switching signal of these upper side switches is PWM “on”
whereas that of the lower side switches is continuous “on” [27].
The power MOSFET packages, as shown in Fig. 1b, are embedded with three parallel-connected Si power MOSFET chips
to increase the current rating [23]. Furthermore, the typical
PWM technique via a waveform generator is applied for controlling the power MOSFETs. A microcontroller is applied to provide gate pulses to the switches. Current or voltage is supplied to
the power MOSFET devices, and is further regulated by rapidly
turning on and off the switch via PWM. If the turn-on time period is longer than the turn-off time period in a PWM cycle, more
electrical power is provided to the devices. A duty cycle is defined as the ratio of the turn-on time pulse width to the switching cycle time. The load conditions of the inverter are 50 V power
supply voltage VDD , a square-wave PWM switching frequency of
10 kHz with a duty cycle of 50% (see Fig. 2b) and 55 Hz output
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Figure 2 (a) The three-phase bridge circuit and (b) PWM signal sequence.
Parasitic extraction and power loss estimation of power devices
• 137
Figure 4 (a) Equivalent circuit model of power MOSFET and (b) the three parasitic capacitances as a function of drain–source voltage (Vds ).
frequency. The output characteristics of the power MOSFET are
shown in Fig. 3. The maximum drain voltage and current of the
power MOSFET are 100 V and 350 A, respectively. It is straightforward to see from Fig. 3a that the on-state resistance Rds(on)
shows great temperature (T) dependence with a positive slope
coefficient. In addition, the equivalent circuit model of power
MOSFET is schematically presented in Fig. 4a.
The power MOSFET package has four terminals, i.e. one gate,
one drain and two sources, for electrical connections. In addition, it primarily consists of Si power MOSFET chips, Al
bond wires, Al pads, Cu terminal leads, an Al2 O3 -based direct
bonded copper (DBC) substrate, a Cu base plate, a polyphenylene sulfide (PPS) housing, a quick-drying rubber-based adhesive (cement) used to fill the space between the housing and the
DBC/Cu terminal leads for insulation, and three layers of Sn–
3.0Ag–0.5Cu (SAC305) solder that are applied to bind the Si
power MOSFET chips and the Cu terminal leads, the Cu terminal leads and the DBC substrate, and the DBC substrate and the
Cu base plate. The thicknesses of the chips, pads, terminal leads,
DBC substrate, base plate and those three solder layers are 0.33,
0.01, 0.8, 0.45, 2.0, 0.05, 0.1 and 0.1 (mm). In total, there are
12 Al bond wires bonded onto the Al pads of these three power
MOSFET chips.
3. POWER LOSS PR EDICTION
During operation, the power dissipation in a MOSFET includes
conduction, switching and current leakage losses, and conduction and reverse-recovery losses of a body diode. Due to the
fact that leakage current loss in a power semiconductor device
is generally far less than conduction loss [23], it is neglected
in this study. However, for high-frequency switching, the effect
may not be negligible. The conduction and switching losses of a
MOSFET, i.e. WC and WS , respectively, during switching transition can be estimated in the following.
3.1 Conduction loss of MOSFET
As a MOSFET is switched on with a drain–source current Ids ,
conduction loss arises in a way of Joule’s heating primarily as a
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Figure 3 Output characteristics of the power MOSFET: (a) on resistance; (b) diode characteristic; (c) output characteristic; and (d) transfer
characteristic.
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• Journal of Mechanics, 2020, Vol. 37
result of the drain–source on-state resistance Rds(on) . The conduction loss can be simply characterized from the static I–V characteristics of semiconductor devices. During one switching period tsw , the conduction loss can be roughly described by the
conduction dissipation:
tsw
1
2
Rds(on) (T )Ids
(t )dt.
(1)
WC =
tsw 0
Clearly, the temperature dependence of conduction loss is considered due to the high temperature-dependent on-state resistance, as shown in Fig. 3a. For a duty cycle, the conduction loss
presented in Eq. (1) needs to be corrected by multiplying the
duty cycle value.
3.2 Switching losses of MOSFET
Power MOSFETs during the switching transient would induce
switching losses as a result of the turn-on (Pon ) and turn-off
(Poff ) energy dissipations. The former is primarily due to the current growth of the power semiconductor devices from the trivial leakage current up to the drain–source current Ids , and meanwhile, the voltage drops from the off-state voltage to the on-state
voltage. The latter is owing to the current drop from the on-state
current to the leakage current, and in the meantime, the voltage
gains from the on-state voltage to the off-state voltage. In addition, switching energy losses are positively linearly dependent
on switching frequency and, consequently, tend to become excessive for high switching applications. Switching losses show
strong dependence on both circuit parameters, including device
parasitics (capacitance, inductance and resistance), gate drive
current, reverse-recovery current and device parameters. During switching operations, typical turn-on and turn-off transients
are shown in Fig. 5, where the nonlinear curves are simply approximated by a piecewise-linear function [11]. These switching
transients mainly depend on the parasitic drain inductance Ld ,
source inductance Ls and gate inductance Lg , and also the parasitic gate–drain Cgd capacitance, gate–source capacitance Cgs
and drain–source capacitance Cds . These parasitic capacitances
constitute the input capacitance Ciss , output capacitance Coss
and reverse transfer capacitance Crss :
Ciss = Cgs + Cgd ,
(2)
Coss = Cgd + Cds ,
(3)
Crss = Cgd .
(4)
Basically, they are closely related to the drain–source voltage
(Vds ). Ciss , Coss and Crss for the applied power MOSFET are displayed in Fig. 4b, where the output capacitance Coss presents the
greatest dependence on Vds , principally due to Cds .
The total switching energy loss PS is the sum of the turn-on
and turn-off energy dissipations:
tswon
tswoff
PS = Pon + Poff =
Ids (t )Vds (t )dt +
Ids (t )Vds (t )dt,
0
0
(5)
on
off
and tsw
are the turn-on and turn-off switching periods,
where tsw
respectively. The total switching loss is the sum of the turn-on
and turn-off energy dissipations:
WS = fS PS ,
(6)
where fs is the switching frequency.
The following gives a brief introduction of the turn-on and
turn-off characteristics. Start from the turn-on transients. As the
switch is turned on at t = 0, Cgs starts to charge, and the gate–
source voltage Vgs gradually increases. As Vgs at t = t1 attains a
threshold voltage VTH , Ids commences to flow into the drain. At
t > t1 , Cgs continues to charge, Vgs increases and also Ids continually rises. At t = t2 , Ids gets to the on-state current value IDS
and Vgs attains the gate plateau voltage Vgp . At t > t2 , Ids and Vgs
remain at IDS and Vgp , respectively, while Vds undergoes a sharp
drop from the supply voltage VDD . Clearly, there is a large current spike (overshoot) Ipeak mainly due to the reverse-recovery
stress of the body diode from the high-side power MOSFET (in
a DPT circuit), which would likely cause an increased switching
loss. At the phase, Ids stays at IDS , and hence, Vgs remains at the
gate plateau voltage Vgp . At t = t3 , Vds falls down to the low conduction voltage VON , which is equivalent to IDS Rds(on) . On the
other hand, in the beginning phase of the turn-off transients, Vgs
commences to fall from the gate drive voltage VGS , and the device capacitances Cgs and Cgd begin to discharge via Rg and Ls .
At this phase, Ids and Vds would still stay constant, namely IDS
and VON , respectively, until Vgs goes down to Vgp at t = t4 . At
t > t4 , Vds starts to increase. Typically, Ids would remain at IDS ,
and Vgs at Vgp . Once Vds attains the supply voltage VDD at t = t5 ,
Ids and Vgs gradually decrease from IDS and Vgp , respectively,
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Figure 5 Switching transients of power MOSFET: (a) turn-on waveform and (b) turn-off waveform.
Parasitic extraction and power loss estimation of power devices
until Ids becomes zero and Vgs reaches VTH at t = t6 . At this phase
(t5 < t < t6 ), Ids commences to fall, and as a result of the parasitic inductance, the power MOSFET would experience a high
voltage spike. In general, the time increments t2 − t1 and t6 −
t5 are alternatively called the rise time tir and fall time tif of the
on-state current Ids , respectively, and the time increments t3 −
t2 and t5 − t4 are termed the fall time tvf and rise time tvr of the
drain–source voltage Vds , respectively. In principle, the turn-on
on
is equal to t3 − t1 , and the turn-off switching
switching period tsw
off
time tsw is equal to t6 − t4 .
WCDiode (t ) = IS (t )VSD (t ) = IS (t )VSD0 + IS2 (t )RD (t ), (7)
where IS (t) is the current through the diode, VSD0 is the diode
on-state zero-current voltage and RD (t) is the diode on-state resistance. These parameters can be derived from the diagrams in
the device datasheet. The total diode conduction losses across
on
can be written as
the turn-on switch period tsw
tsw
1
WCDiode =
WCDiode (t )dt
tsw 0
tsw
1
IS (t )VSD0 + IS2 (t )RD (t ) dt. (8)
=
tsw 0
On the other hand, the reverse-recovery loss is due to the release
of the charge of the capacitance Cds of the complementary power
MOSFET between the drain and source during the second turnon of the power MOSFET. The loss of a single turn-on can be
calculated as
1
(9)
Err = QrrVrr ,
4
where Qrr is the reverse-recovery charge and Vrr is the voltage
across the diode during reverse recovery. For the worst-case calculation, Vrr can be roughly equivalent to the supply voltage VDD .
It is worth noting that the switching losses are calculated through
the product of the voltage and current waveforms across the
turn-on and turn-off periods. Since the reverse-recovery effect
has been included in the output current waveform during the
MOSFET turn-on period, it would not be particularly addressed
in this study.
4. ELECTR IC A L E X PER I M EN T
DPT is a favorable standard test method for characterization of
the switching characteristics and dynamic behaviors of power
devices, including turn-on, turn-off and reverse-recovery parameters, by which the switching losses can be assessed. Thus, dynamic characteristics of the applied power MOSFETs in an SOT227 package are assessed in a double pulse tester. The DPT ex-
periment setup, as illustrated in Fig. 6a, includes an arbitrary
function generator to produce pulses with variable pulse widths,
an oscilloscope together with a high-common-mode rejection
probe because of the susceptibility of the gate drive VGS to
common-mode noise, a differential voltage probe and a current
probe to measure Vgs , Vds and Ids , and a DC power supply to
supply the load voltage. In specific, the DPT circuit possesses
a phase-leg structure with a power MOSFET package pair. Except the device under test (DUT) (i.e. the lower side switching device), the DPT circuit also comprises a freewheeling diode
(FWD) (i.e. the upper side switching device) for characterizing
the effect of reverse recovery on the switching losses of the DUT
(i.e. the power MOSFET package switching device). Figure 6b
displays ideal DPT waveforms of VGS , load (inductor current)
(IL ), drain current (ID ) and drain–source voltage (VDS ). In addition, a schematic of the DPT circuit is shown in Fig. 7a, where
Lg is the inductance of the gate terminal lead, Ld1 and Ld2 are
the inductances of the drain terminal lead, Ls1 and Ls2 are the
sum of the inductances of the Al bond wires and source terminal
leads, and L1 /L3 and L2 are the stray inductances due to the connecting wires between the power MOSFET package and the DC
power supply and between the DUT and the FWD, respectively.
Switching characteristics are evaluated under an inductive load
condition at room temperature. As shown in Fig. 6b, two pulses
with a delay time between them are input to the gate of the DUT
through a gate driver. The inductive load is charged to a desired
test current value IL through a first long gate pulse (i.e. from t1 to
t2 ). This pulse is used to elevate the current to the desired value.
According to the relationship between the induced voltage and
the rate of change in the current,
dI
,
(10)
dt
where V is the voltage, L is the inductance, I is the current and t
is the time. The pulse width of the long gate pulse is attuned for
achieving a desired test current value with a given inductive load
and supply voltage VDD . For instance, assume that the desired
test current value is 100 A, the inductive load is 3.4 μH and the
supply voltage is 50 V. The calculated pulse width of the first long
gate pulse is 6.8 μs. As the DUT is turned off, current is generated in the FWD. The turn-off period should be short enough to
keep the load current a constant value. The second pulse, which
is usually shorter than the first pulse in order to keep the load current from a sharp increase, is used in the analysis of the switching transients of the DUT. Noticeably, the DUT is turned on
and off at nearly the same current value. At this phase, a current
spike is likely observed essentially due to the reverse recovery of
the FWD from the high-side MOSFET. The DPT switching loss
measurement is combined with the output characteristics of the
DUT, given in the device datasheet.
V =L
5. ELECTROM AGNETIC A ND ELECTR IC A L
CIRCUIT MODELING
5.1 Theory
Macroscopic electromagnetism phenomena can be well described by Maxwell’s equations, comprising a number of coupled partial differential equations. According to Maxwell’s
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3.3 Power losses of body diode
The body diode may cause great conduction loss and reverserecovery loss. Perhaps, it may be the main source of the total
power loss due to its poor performance. The conduction loss
is induced when the MOSFET is turned off and the current
flows through the complementary power MOSFET (more indicatively, the body diode in the power MOSFET) in the same
leg [12], and the instantaneous value of the diode conduction
losses can be expressed as
• 139
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• Journal of Mechanics, 2020, Vol. 37
equations, when a conductor is subjected to a direct current
[28], the differential form is represented by the following formulas:
∇ · D = ρv ,
(11)
∇ · B = 0,
(12)
∇ ×E =−
∂B
,
∂t
where D is the electric flux vector, B is the magnetic intensity
vector, E is the electric field vector, ρ v is the volume charge density, H is the magnetic intensity vector and Jf is the current density vector. The Ampère equation (Eq. 14) is also called the
Maxwell–Ampère equation.
As the current produces a steady-state electric field on the
surface of the conductor, we can take the divergence of the
vector ∇ × H in Eq. (14):
(15)
∂D
∂ (∇ · D)
∂ρv
=−
=−
.
∂t
∂t
∂t
(16)
Thus,
∇ × H = Jf +
∂D
,
∂t
(14)
∇ · Jf = −∇ ·
Figure 6 (a) DPT experimental setup and prototype and (b) ideal DPT waveforms.
Figure 7 DPT circuit and inverter circuit with parasitic elements: (a) power MOSFET package and (b) three-phase inverter.
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∂D
= 0.
∂t
∇ · (∇ × H) = ∇ · Jf + ∇ ·
(13)
Parasitic extraction and power loss estimation of power devices
• 141
The equation is the continuity equation derived from the principle of conservation of charge. Under the condition of stable current, the charge density does not change with time, ∂ρv /∂t = 0,
and Eq. (16) can be rewritten as
∇ · Jf = 0.
(17)
According to the Ohm’s law, Jf = σ E and E = −∇V, Eq. (17)
can thus be expressed as
∇ · [σ (−∇V )] = 0.
Materials
εr
μr
σ a (S/m)
tan δ
Si (die)
Cu (lead/DBC)
Al (wire/pad)
SAC305 (solder)
Alumina (DBC)
11.9
1.0
1.0
1.0
9.8
1.0
1.0
1.0
1.0
1.0
0.0e + 00
5.8e + 07
3.8e + 07
7.0e + 06
0.0e + 00
0.0
0.0
0.0
0.0
0.0
(18)
When the conductivity σ of the conductor material is constant
and evenly distributed, Eq. (18) can be reduced to
∇ 2V = 0,
Table 1 Electrical properties of the materials in the power devices.
(19)
which is the steady-state electric field governing equation.
5.2 3D EM analysis for parasitic parameter extraction
3D quasi-static EM analysis using the ANSYS® Q3D extraction
tool is performed to extract the parasitic parameters of the single
power MOSFET package and the three-phase inverter with various assigned conducting nets, and also explore their effects on
the power losses. The 3D parasitic extraction tool applies methods of moments and finite element methods to solve the EM
problems. The parasitic extraction simulation between two terminals is performed by first defining a current conductive path
through assigning a source and a sink terminal, where the former serves as a current injector and the latter gathers the current.
Moreover, an adaptive meshing scheme is applied in the ANSYS
Q3D for adaptively adjusting/refining the mesh. To extract the
parasitics at different frequencies, a discretized frequency sweep
is performed. For the power MOSFET package, the Al bond
wires and Cu terminal leads (namely, one gate, one drain and two
sources) would be the root cause of the parasitic effects. Accordingly, the aim of the parasitic analysis is to determine the parasitic
inductances of the drain, gate and source leads, i.e. Ld , Lg and Ls .
The geometry of the power MOSFET package is imported into
ANSYS Q3D, including MOSFET chips, Al bond wires, Al pads,
Cu terminal leads, a DBC substrate, a Cu base plate and solder
layers. In other words, the PPS housing and the filling material
(i.e. the quick-drying rubber-based adhesive) are not included.
The geometry model for parasitic inductance extraction of the
power MOSFET package is shown in Fig. 8a. The EM simulation model consists of 68 742 finite elements. In addition, three
conducting nets associated with the drain, source and gate of the
power MOSFET package are assigned for the parasitic analysis,
and then, the inputs/outputs of each net are defined. The working frequency is set to be 20 kHz. It is noted that the conducting net associated with the source includes the source terminal
leads and Al wires, as plotted in Fig. 8a; hence, the calculated Ls
includes two parts: one is the parasitic inductance of the source
terminal leads and the other is that of these Al wires.
Figure 8b displays the geometry model of the three-phase inverter and the defined conducting nets that describe the current
paths and their identification number. In total, 12 critical conducting nets in the inverter, as illustrated in the figure, are assigned in accordance with the switching sequence of the inverter.
Ld and Ls of the power MOSFET in an SOT-227 package are defined as Nets 8 and 9, respectively, as shown in Fig. 8b. In fact,
they are determined from the preceding parasitic parameter extraction of the single power MOSFET package. Take an example
of the first switching state in the six-step switching sequence, involving Q1 and Q4. The major current conductive paths during
the first switching state include the DC bus+ to the drain of Q1
(Net 1), the drain terminal of Q1 (Net 8), the source terminal of
Q1 (including Al wires) (Net 9), the source of Q1 to the motor
load (Net 10), the motor load to the drain of Q4 (Net 11), the
drain terminal of Q4 (Net 8), the source terminal of Q4 (including Al wires) (Net 9), the Cu bridge (Net 5) and the Cu bridge
to the DC bus− (Net 7). Likewise, the housing and other insulation materials are not considered in the modeling. The working
frequency is set to be 10 kHz. The electrical properties of the
main component materials, namely bulk conductivity (σ a ), dielectric loss tangent (tan δ), relative permeability (μr ) and relative permittivity (εr ), are shown in Table 1, which are given by
the material library inside the reference manual of the ANSYS
Q3D Extractor.
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Figure 8 3D EM models for (a) the power MOSFET package and (b) inverter and the assigned nets and their identification number.
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• Journal of Mechanics, 2020, Vol. 37
5.3 Electrical circuit analysis
6. R ESULTS A ND DISCUSSION
6.1 Parasitic extractions and power loss estimation of power
MOSFET package
6.1.1 Parasitic parameter extraction
EM simulation is first performed on the single power MOSFET
package for parasitic extraction. The simulated parasitic inductances associated with the drain and source terminals for both
Switching time (ns)
Experiment
Simulation
tvf
tir
tvr
tif
201.0
154.0
161.6
212.0
226.0
160.0
156.0
210.0
the FWD (Ld1 , Ls1 ) and DUT (Ld2 , Ls2 ) are plotted in Fig. 7a,
where they are 5.47 and 7.53 nH, respectively. As noted earlier, Ls comprises the parasitic inductances of the source terminal leads and Al wires, and their values are 5.92 and 1.61 nH,
respectively. In addition, the gate inductance of the DUT (Lg )
is 8.60 nH, also shown in Fig. 7a. The stray inductances of the
connection Cu wires used in the DPT experiment (i.e. L1 , L2 ,
and L3 in Fig. 7a) are also taken into consideration. The connection Cu wires for L1 and L3 are 10 mm long with a diameter of 1 mm and that for L2 is 30 mm long with a diameter of 2
mm. The calculated stray inductances of these three connection
Cu wires from the EM modeling are ∼4.76, ∼16.24 and ∼4.76
nH, as also shown in Fig. 7a. Besides, by using the multiple-point
averaging approximation scheme, the average capacitance values of Ciss , Coss and Crss across the drain–source voltage range
[0, 50 V] are 22 498.97, 28 209.04 and 8614.84 pF. According
to Eqs (2)–(4), the average capacitance values of Cgs , Cds and
Cgd can be found, which are 13 884.13, 19 594.20 and 8614.84
pF. These capacitance values are also listed in Fig. 7a.
With these parasitic parameters, circuit simulation is performed on the power MOSFET package using ANSYS Simplorer. The modeled and measured switching waveforms of the
power MOSFET in a DPT circuit with VDD = 50 V and ID = 100
A are presented in Fig. 9. The corresponding switching times,
i.e. the fall time tvf and the rise time tvr of the drain–source
voltage, and the fall time tif and the rise time tir of the on-state
current, are listed in Table 2. Clearly, a fair consistency in the
modeled and experimental waveform profiles is observed even
though some discrepancies can be found in the current and voltage overshoots and oscillations. The fair discrepancies could be
mainly attributed to a concern about the accuracy of the power
MOSFET parasitic capacitance values provided in the device
datasheet. Moreover, the calculated switching times show a very
good agreement with the experimental values. According to the
current and voltage waveforms, the total turn-on switching time
Figure 9 (a) Modeled and (b) measured switching waveforms of the power MOSFET in an SOT-227 package.
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Dynamic characteristics of the power MOSFET in an SOT-227
package are characterized in the inductive DPT circuit shown in
Fig. 7a, where the inductive load L (i.e. 3.4 μH), the extracted
parasitic inductances (i.e. Ld , Lg , Ls ) from the EM analysis,
the stray inductances of the connection Cu wires (L1 , L2 , L3 )
and the parasitic capacitances from the device datasheet are
also listed. Subsequently, they are exported into the ANSYS
Simplorer circuit analysis model to simulate the inductive DPT
circuit. The other required parameters, namely temperaturedependent output characteristics of the power MOSFET and
body diode, transfer characteristics and on-state conduction
resistance, are given in the device datasheet, as illustrated in
Fig. 3. The absolute maximum ratings of the power MOSFET
are also provided in the device datasheet. Moreover, the nonlinear dependences of these parasitic capacitances shown in Fig. 4b
on the drain–source voltage Vds are also accounted for in the
calculation. To precisely address such nonlinearity in the circuit
calculation is not straightforward. The effect of the nonlinearity
is often approximated using the two-point method approach
[12]. For simplicity and better computational efficiency, it is
instead approximated using a multiple-point averaging approximation in this work, where the parasitic capacitance curves in
the range of the low conduction voltage (VON ) to the supply
voltage (VDD ) are divided into five even regions using six evenly
spaced points, and the capacitances at these Vds points are
averaged. The average value is taken as the parasitic capacitance.
The DPT simulation is done under 50 V DC bus voltage, 100
A load current and room temperature. Figure 7b displays the
equivalent circuit of the three-phase inverter that takes account
of the parasitic effects and the three-phase motor loads, i.e. a
series connection of inductor and resistor (RU , LU ; RV , LV ; RW ,
LW ). For these three phases, the equivalent motor load consists
of 0.125 resistor, in series with a 20 μH inductor.
Table 2 Modeled and measured rise and fall times of voltage and current.
Parasitic extraction and power loss estimation of power devices
• 143
(tvf + tir ) and turn-off switching time (tif + tvr ) and so the
switching losses of the single power MOSFET package can be
obtained.
6.1.2 Effect of temperature on switching transient
Besides the conduction loss, the switching losses of power MOSFETs could also be temperature dependent because it is a function of the temperature-sensitive gate resistance and threshold
voltage [23]. It will be confirmed later that a smaller gate resistance would result in higher turn-on and turn-off speeds and thus
a lower switching loss. As a consequence, the temperature dependence of the switching waveforms and so the switching losses
of the power MOSFET package are assessed through the inductive DPT circuit simulation using ANSYS Simplorer at two different ambient temperatures, i.e. 25 and 125°C. The modeled
waveforms of turn-on transient at these two ambient temperatures are shown in Fig. 10. It is clearly seen that the drain current waveform Id would not vary with temperature; however,
temperature has a great influence on the drain–source voltage
waveform Vds . This suggests that the turn-on switching loss increases with temperature, mainly due to a much more significant
oscillation in the drain–source voltage waveform. A similar result can also be found in the turn-off switching loss. That is to
say, temperature has a positive temperature correlation. The result is consistent with Wang’s prediction [23] for Si MOFET,
and also with Qi et al.’s result [26] for Si IGBT, but the degree
of this effect is not as important as that of Si IGBT. Moreover,
the result has a distinct trend from those of SiC MOSFET (see
e.g. [24–26]).
6.1.3 Estimation of power losses
The calculated conduction and switching losses of the power
MOSFET and the conduction loss of the body diode in a single
load step with a duration of 1 s at a PWM duty cycle of 50% and
switching frequency of 10 kHz are shown in Fig. 11a. The circuit
simulation is performed at the room temperature (i.e. 25°C). It
can be seen from the figure that the switching loss of the power
MOSFET is ∼1.81 times the conduction loss, implying that it
could not be negligible in the power loss estimation. Besides,
the turn-off switching loss considerably outperforms the turnon one. It is important to note that the conduction loss of the
body diode in the FWD is much greater than the total power
loss (sum of the conduction and switching losses) of the power
MOSFET transistors in the DUT. Thus, in order to reduce the
total power loss, the first priority is to lower the conduction loss
of the body diode. This can be achieved by use of either a nearzero dead time, though not very practical, or an external Schottky
diode that is connected in parallel with the power MOSFET to
shunt the body diode, though it has increased inefficiency and
cost. In general, the forward voltage drop of a Schottky diode is
smaller than that of a typical PN junction diode, thereby leading
to a less conduction loss.
6.1.4 Dependence of power losses on duty cycle
The effect of duty cycle on the power losses of the power MOSFET and the conduction loss of the body diode in a single load
step with a duration of 1 s at 10 kHz PWM frequency and various
PWM duty cycles is explored. The duty cycles considered are
10%, 30%, 50%, 70% and 90%. The parametric analysis results
Figure 11 (a) Calculated power losses of power MOSFET package in a single load step with a duration of 1 s and (b) effect of duty cycle on
power losses.
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Figure 10 Modeled turn-on transient waveforms at (a) 25°C and (b) 125°C.
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• Journal of Mechanics, 2020, Vol. 37
are shown in Fig. 11b. The figure shows that the conduction loss
and so the total power loss of the power MOSFET package (i.e.
DUT in the DPT circuit) would increase significantly with duty
cycle, mainly due to an increase in the “ON time” of the signal but
a decrease in the “OFF time”. On the other hand, it is surprising
to see that an increasing duty cycle greatly reduces the conduction loss of the body diode. This is mainly due to a smaller time
interval where the diode is conducting with the increase of duty
cycle. Indicatively, the duration of the interval is a function of the
duty cycle and the dead time of the gate signal. A similar result
can be found in Kumar [29] for an Si IGBT inverter. Since the
diode’s conduction loss is the major power loss source, the total
power loss would correspondingly decrease with an increase in
the duty cycle accordingly.
6.1.5 A novel source terminal design for reduced parasitic inductance
In order to reduce the parasitic inductance associated with the
source, a new source terminal design is proposed, as presented
in Fig. 12a, where the two source leads are bonded together.
As compared to the original design (Fig. 12a), where these
two source leads are separated, the new design demonstrates
a larger conduction cross-sectional area and a smaller conduction length. The parasitic simulation reveals that the source parasitic inductance of the novel design reduces from 5.92 down to
2.59 nH, and as much as ∼44% reduction in parasitic inductance
is achieved.
6.1.6 Parametric study of parasitic inductance
The effects of the Al wire diameter, loop geometry (loop height),
pitch and amount on their parasitic inductances are examined.
The Al loop height and pitch are defined in Fig. 12b. In the parametric study, the Al wire diameter, loop height, pitch and amount
range from 0.1 to 0.5 mm, 0.5 to 2.5 mm, 1 to 2 mm and 3 to 5, respectively. It is noted that an increase in the Al wire diameter and
loop height increases the wire area and length. The parametric
results are presented in Fig. 13. It demonstrates that the Al wire
loop height and amount tend to have a greater impact on their
Figure 13 Effects of (a) Al wire diameter, (b) loop height, (c) pitch and (d) amount on the parasitic inductances of power MOSFET package.
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Figure 12 (a) Two different source terminal designs (left: original design; right: novel design) and (b) definition of Al wire loop height and
pitch.
Parasitic extraction and power loss estimation of power devices
• 145
Table 3 Parasitic inductances (nH) of the assigned conducting nets and the effect of switching frequency (kHz).
Frequency
L1
L2
L3
L4
L5
L6
L7
L10
L11
L12
0
10
20
27.07
23.34
22.10
16.56
14.74
14.37
29.52
25.52
25.06
30.99
31.31
29.49
7.00
6.93
5.31
4.10
3.67
3.64
68.15
54.89
53.81
19.79
19.79
19.79
19.52
19.52
19.52
19.78
19.78
19.78
6.2 Parasitic extraction and switching loss prediction of
three-phase inverter
6.2.1 Parasitic parameter extraction
In the three-phase inverter, the parasitic inductances of the
assigned conducting nets are extracted using ANSYS Q3D, as
can be seen in Figs 7b and 8b. The effects of switching frequency
on the parasitic inductances are also examined. A total of three
different switching frequencies, namely 0 (DC), 10 and 20
kHz, are considered. Note again that Ld and Ls of the power
MOSFET in an SOT-227 package, identified as Nets 8 and 9,
respectively, are extracted from the preceding inductive DPT circuit simulation, and they are 5.47 and 7.53 nH, respectively. The
calculated parasitic inductances of the remaining 10 conducting
nets (L1 –L7 , L10 –L12 ) as a function of switching frequency are
shown in Table 3. Among these 10 assigned conducting nets,
Net 7 (L7 ), i.e. from the Cu bridge to the DC bus−, holds the
largest parasitic inductance value because of possessing the
longest conducting channel and relatively smaller conducting
cross-sectional area, while Nets 5 (L5 ) and 6 (L6 ), i.e. the Cu
bridges, yield the smallest parasitic inductance. Moreover, all
these parasitic inductances, except L4 and L10 –L12 , tend to
slightly decrease with an increasing switching frequency from
0 to 20 kHz. This result is very consistent with the literature
findings (see e.g. [30]). The exception for the former (L4 ) is
probably due to the computational accuracy of the EM finite
element analysis, and that for the latter (L10 –L12 ) is because
of the insignificant switching frequency variation range. The
parasitic inductances at 10 kHz switching frequency are applied
in the subsequent circuit simulation of the three-phase inverter.
6.2.2 Parametric analysis of switching loss
The following investigates the effects of several key factors on
the switching losses of the three-phase inverter during one PWM
cycle at the first switching step of the six-step switching control.
The considered factors are parasitic inductance, gate resistance,
resistive load and switching frequency. Figure 14 shows the
inverter circuit at the first switching step of the six-step switching
control and its current loops. In total, three switches are involved
in this switching step: Q1, Q2 and Q4, where the Q2 switch is
used as an FWD in the commutation step. As mentioned earlier,
Q1 is a PWM power MOSFET, whereas Q4 is a commutation
power MOSFET. As can be seen in Fig. 14, this switching operation consists of two current loops: one is when the Q1 switch is
turned on during a PWM switching cycle, i.e. PWM “on”, and
the other is when the Q1 switch is turned off, i.e. PWM “off”.
The first current loop involves the following conductive paths:
Net 1, Net 8, Net 9, Net 10, Net 11, Net 8, Net 9, Net 5 and Net
7, and the other Net 11, Net 8, Net 9, Net 4, Net 9 Net 8 and
Net 10. The mutual inductances of these two current loops are
also calculated using the proposed EM simulation. The mutual
inductances of these two current loops are found to be 16.42
and 1.02 nH. Since the switching loss is only generated at the
Q1 switch, the first current loop, i.e. when the Q1 switch is
on, is simply considered in the simulation. The total inductance of the series chain in the first current loop is found by
simply summing all the individual inductances of these seriesconnected inductors. According to Table 3, it is around 150.47
nH, which is much larger than the corresponding mutual inductance. Subsequently, circuit simulation of the three-phased inverter is carried out. The equivalent circuit of the three-phase inverter is shown in Fig. 7b. A simple and effective compact circuit
Figure 14 The inverter circuit at the first switching step of the six-step switching control together with the corresponding current loops: (a) Q1
in PWM on mode and (b) Q1 in PWM off mode.
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parasitic inductances. Moreover, a decreasing Al wire diameter,
pitch and amount and an increasing Al wire loop height would
lead to a greater parasitic inductance. It will be confirmed in the
following section that a lower parasitic inductance would minimize the switching loss.
146
• Journal of Mechanics, 2020, Vol. 37
simulation model for the three-phase inverter is developed using ANSYS Simplorer, where the power MOSFET packages are
approximated as resistors. The above-characterized parasitic elements and other components, such as load resistor and load inductor, are also used in the circuit simulation. It is noted that
the effect of mutual inductance among these resistors is not considered because the mutual inductance is much smaller than the
self-inductance. In addition, the switching frequency, gate resistance, gate voltage, gate inductance, inductive load and resistive
load are set to 10 kHz, 1.6 , 10 V, 8.6 nH, 20 μH and 0.125 ,
respectively.
A huge spike of voltage between the drain and source during
the turn-off transient may be generated due to circuit inductance
and stray inductance. Accordingly, the effects of the total inductance of the series-connected inductors in the first current loop
on the turn-on, turn-off and total switching energy losses are first
examined and the results are shown in Fig. 15a. The nominal inductance value (the original design) is 150.47 nH, i.e. the total inductance of the series chain. In the parametric analysis, the total
parasitic inductance varies from 75.27 to 225.74 nH, i.e. ±50%
of the nominal value, which implies that the inductance of each
net in the current loop would also change ±50% of the original
value. The figure shows that the turn-off energy loss markedly
outperforms the turn-on energy loss. In addition, the turn-off
and total switching energy losses rise with the growth of parasitic
inductance, whereas an increasing parasitic inductance tends to
slightly lower the turn-on loss. The former is probably due to the
fact that a smaller parasitic inductance brings about a lower voltage spike in the turn-off transient, thereby leasing to a less switching loss. In addition, the parasitic inductance has a more important impact on the turn-off energy loss than turn-off one.
Switching time can be controlled by means of gate resistance.
The gate resistance is typically within the range of 1–3 ; as a
result, in the parametric analysis, the variation of the gate resistance is in the range of 0.8–2.4 . Note that the nominal gate
resistance value is 1.6 . Figure 15b exhibits the dependence
of the switching energy losses of the inverter on the gate resistance. It is found that the increase in gate resistance raises all
these switching energy losses, namely the turn-on, turn-off and
total. This result can be attributed to the fact that a smaller gate
resistance results in a shorter switching time and faster switching speed, thereby diminishing these switching losses. Similar to
the parasitic inductance, the gate resistance also plays a much
more significant role in the turn-off energy loss than the turnon. It should be noted that even though the switching time becomes shorter with a smaller gate resistance, the voltage spike in
the turn-off transient may reversely increase in magnitude. Special attention needs to be also taken when the drain–source voltage exceeds the voltage rating or breakdown voltage of the power
device since it may cause a false switching event, which would
make the power device extremely vulnerable to permanent
damage.
The influence of the resistive load on the switching energy
losses is examined. The resistive load varies ±50% from its nominal value, i.e. 0.125 . The variations of the switching energy
losses with these resistive loads are presented in Fig. 15c. The
figure reveals that all these switching losses decrease with the
resistive load. This can be explained by the fact that a smaller resistive load would result in a larger drain current, thereby causing a greater switching loss. It is also found that a greater resistive
load would not only bring about a less current fluctuation amplitude during the switching operation but also take more time to
reach the specified load current, i.e. 100 A in this investigation.
According to the slope of these curves, the resistive load shows
a much greater impact on the switching loss, as compared to the
parasitic inductance and gate resistance. Likewise, the resistive
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Figure 15 Effects of (a) parasitic inductance, (b) gate resistance, (c) resistive load and (d) switching frequency on the switching losses.
Parasitic extraction and power loss estimation of power devices
load demonstrates a greater influence on the turn-off energy loss
than the turn-on one.
The switching losses of the inverter as a function of the PWM
frequency are assessed and the results are displayed in Fig. 15d.
For avoiding noise, most commercial inverters would not be operated at switching frequencies <5 kHz. As a consequence, in
this investigation, three different switching frequencies are considered, namely 5, 10 and 15 kHz. From the figure, it is not surprising to see that these switching losses elevate with switching
frequency. Besides, in terms of noise and switching loss, a switching frequency of 5 kHz could be a preferred option.
This study utilizes both experimental and numerical methods to
explore the switching transients and power losses of a Si power
MOSFET-based three-phase MOSFET inverter for brushless
DC motor drive during the load cycles. EM simulations are performed using the 3D EM simulator to explore the parasitic inductances of the power MOSFET package and three-phase inverter. A compact circuit simulation model that combines the
device model and package model is constructed for the power
MOSFET package and three-phase inverter. The switching transients of the power MOSFET package are experimentally tested
and numerically evaluated with the DPT circuit. Despite having certain discrepancies in the overshoots and oscillations of
current and voltage, the experimental results in terms of waveform profiles and switching times are found to be appropriately
consistent with the simulated ones. They could be probably attributed to insufficient accuracy of the parasitic capacitances provided in the device datasheet. Finally, a design guideline for reduced parasitic inductances and decreased switching losses is
sought through parametric study. Some essential remarks are
briefed below:
1. The results show that temperature has a little impact on
the drain current waveform but an important effect on the
drain–source voltage waveform. In other words, the turnon and turn-off switching losses and so the total switching
loss all have a positive temperature coefficient, mostly because of the increased voltage ringing. The result agrees
well with the literature findings for Si power MOSFET
devices while being opposite to those for SiC MOSFET.
Besides, the extent of temperature effect for Si power
MOSFET devices is not as significant as that for Si IGBT
devices.
2. The DPT simulation demonstrates that the switching loss
of the power MOSFET package greatly outperforms its
conduction loss, indicating that the effect of switching loss
could not be neglected in the power loss analysis. Moreover, the turn-off switching loss turns out to be much
greater than the turn-on one.
3. The major power loss source in the power MOSFET package is the conduction loss of the body diode, which can be
greatly reduced by use of an external Schottky diode, followed by the switching loss and conduction loss of power
MOSFETs.
4. It is interesting to see that the total power loss decreases
with the increase of duty cycle, mainly because the conduction loss of the body diode decreases with duty cycle,
eventually leading to a reduced total power loss. This can
be explained by the fact that the increase of duty cycle upgrades the signal’s “ON time” but lowers the signal’s “OFF
time”.
5. It is interesting to find that the proposed novel source terminal design can extensively help to reduce the parasitic
inductance, thereby allowing for a lower switching loss.
Furthermore, as compared to wire pitch and diameter, the
loop height and number of wires have a relatively large effect on their parasitic inductance. Besides, the parametric
analysis reveals that a lower parasitic inductance in the Al
wires can be achieved by use of a larger wire diameter, wire
pitch and number of wires, and a smaller loop height.
6. Parasitic parameter extraction of the three-phase inverter
demonstrates that among the assigned nets, the conductive path from the Cu bridge to the DC bus− (Net 7)
yields the largest value of parasitic inductance because
of having the longest conducting channel and relatively
smaller conducting cross-sectional area. On the other
hand, the Cu bridges, i.e. Nets 5 and 6, possess the lowest parasitic inductance. In addition, the parasitic inductances have a minor negative influence on the switching
frequency as it varies from 0 to 20 kHz.
7. Parametric study of the switching energy losses of the
three-phase inverter demonstrates that the turn-off and
total switching losses during the first switching step of
the six-step switching sequence tend to reduce with a decreased parasitic inductance, gate resistance and switching frequency, and an increased resistive load.
ACKNOWLED GE M EN T
This work was partially supported by the Ministry of Science and
Technology, Taiwan, Republic of China, under grants MOST
106-2221-E-035-052-MY3 and MOST 109-2221-E-035-004MY3.
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