PHYSICAL DESIGN
(GATE LEVEL NETLIST TO GDSII)
WHAT IS SYNTHESIS? & GOALS OF SYNTHESIS
Synthesis: It is the process of converting RTL code to Gate Level Netlist
Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific
gate level netlist (includes nets, sequential and combinational cells and their connectivity).
Goal of synthesis:
1. To get a gate level netlist
2. Inserting clock gates
3. Logic Optimization
4. Inserting DFT (Design for Testability)
5. Logic Equivalence Check B/W RTL to Netlist should be maintained
SYNTHESIS INPUTS
INPUTS FOR SYNTHESIS
1. RTL(.V)
2. LIBRARAY LIFES(.LIB)
3. SYNOPSYS DESIGN CONSTRAINTS (.SDC)
4. UNIFIED POWER FORMAT (UPF)
5. SCAN CONFIGURATION FILE
6. TECHNOLOGY FILE(.TF )
INPUT FILES REQUIRED
Tech related:
1.
.tf- technology related information.
2.
.lib-timing info of standard cell & macros
Design related:
1.
.v- RTL code.
2.
SDC- Timing constraints.
3.
UPF- power intent of the design.
4.
Scan config- Scan related info like scan chain length, scan IO, which flops are to be considered in the scan
chains.
For Physical aware:
1.
RC co-efficient file (tluplus).
2.
LEF/FRAM- abstract view of the cell.
3.
Floorplan DEF- locations of IO ports and macros.
SYNTHESIS FLOW STEPS
1)Analyze
Checks syntax on RTL and generates immediate files.
SYNTHESIS FLOW
2)Elaborate
1.
Brings all lower level blocks into synthesis tool.
2.
All the codes and arithmetic operators are converted into GTECH and DW (Design Ware)
components. These are technology independent libraries.
I.
GTECH- contains basic logic gates &flops.
II.
Design Ware- contains complex cells like FIFO, counters.muxs
Elaborate performs following tasks;
Analyses design hierarchy. Removes empty switches and dead branches. Executes initial commands.
Detects asynchronous reset. Converts decision trees to mux. Converts synchronous to D Latch/DFF.
FSM pass
1.
Detects FSM logic and extracts the no of input, output bits and state bits.
2.
Converts FSM logic to basic logic.
SYNTHESIS FLOW
Memory pass
Merging DFF to memory write(memwr) and memory read (memrd)
Consolidating memwr/memrd cells
Generate memory (mem) cells
Mapping mem cells to basic logic
3)Import constraints and UPF
1. Once the design is extracted in the form of technology independent cells, timing constraints are
imported from the SDC file.
2. If the design consists of multiple power domains, then using the UPF power domains, isolation
cells, level shifters, power switches, retention flops are placed.
4.CLOCK GATING
 Due to high switching activity of clock ,a lot of dynamic power is consumed. One of the techniques to lower
the dynamic power is clock gating. In load enabled flops, the output of the flops switches only when the
enable is on. But clock switches continuously, increasing the dynamic power consumption.
 By converting load enable circuits to clock gating circuit, dynamic power can be reduced. Normal clock
gating circuit consists of an AND gate in the clock path with one input as enable. But when enable becomes
one in between positive level of the clock a glitch is obtained
SYNTHESIS FLOW
1.To remove the glitches due to AND gate, integrated clock gate is used. It has a negative level
sensitive latch and an AND gate.
2.Clock gating makes design more complex. Timing and CG timing closure becomes complex. Clock gating
adds more gates to the design. Hence min bit width (minimum register bit width to be clock gated) should be
wisely chosen, because the overall dynamic power consumption may increase.
SYNTHESIS
5)Compile
 Performs Boolean optimization.
 Maps all the cells to technology libraries.
 Performs logic and design optimization.
SYNTHESIS FLOW
Optimization
Logic optimization
Design optimization
1. Detect identical cells
1.Reduce TNS and WNS
2. Optimize mux(dead branches in mux)
2.Power Optimization
3. consolidate mux and reduce inputs(many to single )
3. Area Optimization
4. Remove DFF with constant value
4.Meet the timing DRV’s
5. Reduce word size of the cells
5. incremental clock gating
6.
Remove unused cells and wires
7.
Constant folding
SYNTHESIS
7)DFT (Design for Testing) insertion
1. DFT circuits are used for testing each and every node in the design.
2. More the numbers of nodes that can be tested with some targeted pattern, more is the coverage.
3. To get more coverage the design needs to be more controllable and observable.
4. For the design to be more controllable we need more control points (mux through which alternate
path is provided to propagate pattern).
5. For the design to be more observable we need more observe point (A scan-able flop that
observes the value at that node).
6. Scan mode is used to test stuck at faults and anufactured devices for delay.
SYNTHESIS
7)DFT (Design for Testing) insertion
Scan mode is done using scan chains
1. Scan chains are part of scan based designs to propagate the test data.
2. By having scan chains, the design can be more controlable and observable.
3. Each scan chain inputs the pattern through scan input and outputs the pattern through scan
output.
4. Scan chain consists of scan flops where the output of scanflops is directly connected to scan inputs
of the flops
SYNTHESIS
7)DFT (Design for Testing) insertion
Stages of scan mode
1. Inputs the pattern through scan input port.
2. Scan shift- Scan enable is set to 1. Then inputs the pattern through the scan input, shifts the pattern
through the scan flops and load all the flops with test pattern.
3. Scan capture- Scan enable is set to 0. In one clock cycle the loaded value in the flops propagates
through combinational circuit and reaches the D pin of the next flop.
4. Scan enable is set to 1 and outputs the pattern through scan output port.
SYNTHESIS
1.
The scan chain length and number of scan chains has to be properly chosen, as having more scan
chain length increases the pattern propagation time and having more scan chains increases the
number of scan IO ports.
2.
Scan chain
Compile incremental
1.
Technology mapping of DFT circuit
2.
Optimization of the design
SYNTHESIS OUTPUTS
Outputs of synthesis
1. synthesized netlist
2. Modified constraints (.sdc)
3. Modified UPF
4. Timing reports
5. Scan DEF: Information of scan flops and their connectivity in scan chain
SYNTHESIS CHECKS
1.Check if the RTL and Netlist are logically equivalent (LEC)
2.Check if SDC and UPF are generated after synthesis and also check their completeness.
3.Checks Timing - Command: check_timing
4. Checks Design - Command: check_design
SYNTHESIS CHECKS
• SDC Checks: ICC command: check_timing
1. If any unconstrained paths exist in the design then PNR tool will not optimize that path, so these checks are used to report unconstrained
paths
2.
Checks whether the clock is reaching to all the clock pin of the flip-flop.
3.
Check if multiple clock are driving same registers
4.
Check unconstrained endpoints
5.
Port missing input/output delay.
6.
Port missing slew/load constraints.
You can correct unconstrained paths by adding new constraints using commands such as
create_clock, set_input_delay, and set_output_delay. check_timing
[-overlap_tolerance minimum_distance]
[-override_defaults check_list]
[-include check_list]
[-exclude check_list]
[-multiple_clock]
[-retain]
SYNTHESIS CHECKS
Design checks: ICC command: check_design
Check if current design is consistent or not
It checks the quality of netlist and identifies:
1.
Floating pins
2.
Multidriven nets
3.
Undriven input ports
4.
Unloaded outputs
5.
Unconstrained pins
6.
Pin mismatch counts between an instance and its reference
7.
Tristate buses with non-tristate drivers
8.
Wire loops across hierarchies
TOOLS FOR PNR
SYNOPYSIS TOOL:1. ICC2 (New),
DC compiler (logic synthesis)
2.DC Topo (physical synthesis)
3.Fusion compiler (combo of both)
CADENCE TOOL: 1.RC Compiler (logic synthesis),Genus innoves (Physical synthesis)
OVERVIEW OF PHYSICAL DESIGN FLOW
1.Physical Design is a part in ASIC design flow.
2.It is the process of converting Gate Level Netlist Into Transistor level GDSII layout. Which can
be physically manufacturable with best QOR (Quality of Results ) and without changing the
functionality.
Thus Physical Design flow is also called as Netlist to GDSII Flow.
3.Most Commonly Used Tools presently in the industry for physical design ,
ICC2 From Synopsys
&
Innovus From Cadence.
PNR/NETLIST TO GDSII/PHYSICAL DESIGN FLOW
DESIGN IMPORT
• The first step is Design Import all required Inputs
files for PD
• Like
1.Netlist(.v) ………..given by synthesis people
2.Synopsys Design Constraints (.sdc)……given by
synthesis people
3.Logical /Timing library's (.lib)…... given by vendors
4.Physical Library (.lef)……given by vendors
5.TLU+ files …..given by fabrication people
6.Technology File (.tf)…… given by fabrication people
DESIGN IMPORT
Netlist: Format is .V
1.
It contains Logical connectivity Of all Cell(Std cells, Macros).
2.
It contain List of nets.
3.
In the design for Knowing connectivity by using Fly lines.
SDC :Format is .SDC :
1. CLOCK DEFINITIONS: Create Clock Period.
2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
DESIGN IMPORT
-------------->Exceptions<------------------------9. Multi cycle path
10. False path
11. Half cycle path
12. Disable timing arcs
13. Case Analysis
Multi cycle path, False path are Exceptions /contraints
DESIGN IMPORT
• Physical libraries: format is .lef:
1. Physical information of std cells,macros,pads.
2. Pin information.
• Define unit tile placement.
• Minimum Width of Resolution.
• Hight of the placement Rows .
• Preferred routing Directions.
• Pitch of the routing tracks.
8. Antenna Rules.
9 Routing Blockages
In physical info height,area,width, are present. and also it contains two views
• 1)Cell View: In this all layout information is present,it is used at the time of tapeout
• 2)FRAM view: is abstract view, it is used at the Place & Route
DESIGN IMPORT
Logical libraries :format is .lib
1. Timing information of Standard cells,Soft macros,Hard macros.
2. functionality information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models, Non linear delay models,CCS models.
8. functionality is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out put voltage.
DESIGN IMPORT
And PVT contains
------->Cell leakage Power
-------->Internal Power
--------->Rise Transition
----------->fall transition
---------->>Setup rise
----------->setup fall
-------------->Hold rise
------------->Hold fall
----------------->cell rise
---------------->cell fal
-------------------->Pin Capacitance
And it contains A view(sub directory) i.e. LM(Logical Model view)view.
It contains logical libraries
DESIGN IMPORT
Technology file: format is .tf:
1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of layer and via
3. In Physical characteristics Min width,area,height are present.
4. In Electrical characteristics Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.
DESIGN IMPORT
TLU+ files: format is .TLUP:
1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names
SANITY CHECKS
Before going to floor plan we will do some sanity checks ,so after reading the inputs (Design Import
input files) sanity checks performs to make sure the correctness of the given inputs ,
So to avoid any mistakes and issues for further stage and verify the inputs by these checks
1.Check design –Netlist file command: check_design
2.Check timing -.sdc timing constraints command: check_timing
3.Check library –Connectivity b/w logical and physical librarys consist or not command: check_library
This command shows the name of the library, library type & its version, units of time, capacitance, leakage power, and
current.
It shows the number of cells missing, the number of metal or pins missing in the physical and logical library
4.Design Data –Import Design feeding the all required inputs
FLOOR PLANNING
 Before going to FP ,we have to estimate the die size, After Estimating the Die size for floorplan, first will placed the IO ports /Pins a as per the
information given by the full chip engineer. Then we have to analyze by using fly lines.
WHAT IS FLOOR PLAN ?
Primary aim of the FP, is place the macros into the core area towards the
boundary. with sufficient area available for standard cells and routing.
standard cell row:
The area allotted for the standard cells on the core is divided into
rows where standard cells are placed.
The height of the row is equal to the height of the standard cell and width
varies. The height varies according to multiple standard cell row height.
there may be double-height cells, triple-height cells, etc.
The standard cells will sit in the row with proper orientation
GOALS OF FLOORPLAN
FLOOR PLAN INPUTS
FLOOR PLAN STEPS
1. Decide core width and height for die size estimation.
2.IO pad sites are created for placement of IO pad placement.
3.Placement of macros.
4.The standard cell rows created for standard cell placement.
5. Power planning (pre routing)
6.Adding physical only cells
• apart from this aspect ratio of the core, utilization of core area, cell orientation, and core to IO
clearance are also taken care of during the floorplan stages.
FLOORPLAN CONTROL PARAMETER:
• core area depends upon :
• Aspect ratio: Aspect ratio will decide the size and shape of the chip. It is the ratio between
horizontal routing resources to vertical routing resources (or) ratio of height and width.
• Aspect ratio = width/height
• Core utilization:- Utilization will define the area occupied by the standard cells, macros, and other
cells. If core utilization is 0.8 (80%) that means 80% of the core area is used for placing the standard
cells, macros, and other cells, and the remaining 20% is used for routing purposes.
•
(macros area + std cell area +pads area)
Core utilization : ================================
•
total core area
• : Ex: check: Initialize_floorplan –side_ratio {2 2} –core_offset {10}
MACRO PLACEMENT GUIDELINES(MPG)
Macros may be memories, analog blocks. Proper placement of macros has a great impact on the quality and performance
of the ASIC design. Macro placement can be manual or automatic.
 placing the macros are near to boundary for easily communicate with other blocks of macros through IO pins
 place similar macros together
 avoid criss cross connections
 pin direction towards the core
 provide the enough space around the macro for IO routing
 fix the macro locations , so that tool wont alter during optimization
 apply the keep out margin around the macro because cells disturb the macro.
 macro orientation is 180 degrees .for
(No of pins to be routed * pitch of the routing layer *2 )
 Spacing between macros = ------------------------------------------------------------------------Available routing layers in the preferred direction
MACRO PLACEMENT GUIDELINES(MPG)
Avoid notch formation
 Notch are is not utilized effectively, so it will increase the placement density of the core and will
rise the congestion
CONGESTION: means available resources are lesser than the required resources.
Reasons for Congestion.
 High standard cell density in small area,
 Placement of standard cells near macros,
 High pin density at the edge of macros
 Bad floorplan
 During IO optimization tool does buffering, so lot of cells placed in the core area.
HOW TO CONTROL THE CONGESTION
High cell density can cause the congestion.by default the cell density can be up to 95%.
We can reduce the cell density in congested areas by using coordinate option
 check: Set_congestion_options –max_util 0.45 –coordinate {x1 y1 x2 y2}
Here we set the maximum cell density up to 45% and given the coordinates for the particular area.
BLOCKAGES
 Blockages can be used for avoiding congestion
Two types of blockages:
1. placement blockage: check: Create _placement_blockage -type …
2
.Routing blockage :check: Create_routing_blockage –type..
placement blockage again can be divided into 3 types
1.Hard ,2.soft And,partial blockage
1.Hard blockage : No std cells are allowed
2.Soft blockage : only inverters /buffers are allowed and std cells are not allowed
3.Partial blockage
only std cells are allowed
partial std cell blockage is used to avoid congestion
we can block the std cells as per the required percentage value.
MACRO PLACEMENT GUIDELINES
 Placement of macros are the based on the fly-lines ( its shows the connectivity b/w macro to macro and macro to pins)
so we can minimize / reduce the interconnect length between IO pins and other cells.
fly lines: macros are placed manually using fly lines. fly lines are a virtual connection between macros and
macros to IO pads. , fly lines are of two types
1.macros to IO pin:
2. macros to macros fly lines
 Avoids notches while placing macros, if anywhere notches is present then use hard blockages in that area
Between two macros at least one pair of power straps (power and Ground) should be present.
• Note: lots of iterations happen to get optimum floorplan. the designer takes care of the design parameter such
as power, area, timing and performance during floor planning.
HALO/KEEP KEEP-OUT MARGIN MPG:
 The region around the four sides of macros, so no standard cells will not sit near to Macro pins. This
technique avoids the congestion. Check:Create_keepout_margin –outer {10 10 10 10} my_lib_macro
 This is the region around the fixed macros so that no other macros and standard cell can be placed
near to macros boundary
 The width of the keep out margin on each side of the fixed cell can be the same or different
depending on how you define keep out margin.
 keeping the placement of cells out of such regions avoids congestion and produce better QOR
 Halo of two adjacent macros can be overlap.
 If the macros moved from one place to another place, the halo will also move.
TYPES OF FLOORPLAN TECHNIQUES
2 Types of Floor Plan Techniques
1. Abutted:- When the chip is divided into blocks in the
abutted design there is no gap between the blocks.
2.Non abutted:- In this design there is a gap between blocks.
The connection between the blocks is done through the
routing nets.
OUTPUTS OF FLOORPLAN
1. Die/Block area
2. I/O pad/placed
3. Macro placed
4. Power grid design
5. Power pre-routing
6. Standard cell placement areas.
POWER PLANING
Power planning means to provide power to the every macros, standard
cells, and all other cells are present in the design.
 Power planning is also called Pre-routing as the Power Network
Synthesis (PNS) is done before actual signal routing and clock
routing.
Power ring is designed around the core.
Power rings contains both VDD and VSS rings.
 power mesh is nothing but horizontal and vertical lines on the chip.
 Objective of power planning is to meet IR drop budget.
POWER PLANING
LEVELS OF POWER DISTRIBUTION
1. Power Rings: Carries VDD and VSs around the chip
2. Power Straps: Carries VDD and VSS from rings across the chip
3. Power Rails: Connect VDD and VSS to the standard cells.
4.Trunks :Connects Ring to Power Pad
INPUTS FOR POWER PLANNING
1. Netlist(.v)
2. SDC
3. physical and logical libraries (.lef & .lib)
4. TLU+
5. UPF
6. Power rings and power straps width..
7. Power budget.
8. Spacing between the VDD and VSS straps.
METAL LAYERS FOR POWER PLANNING
M1-Metal layer
M8-Metal layer
M2 -Metal layer
M9 -Metal layer….For power
M3 -Metal layer ….For Routing
M10 -Metal layer (AP)
M4 –Metal layer
M11 -Metal layer
M5 –Metal layer
M12 -Metal layer…..For power Planing
M6 –Metal layer
M7 -Metal layer…..For signal and clock Routing………Note: Only for Understandings Purpose
For Higher metal layers used for to avoid the EM and IR Drop.
Electromigration: Movement of molecular transfer of electrons in the metal from one area to another, that
caused by high density electric current flows in the metal. It can creates shorts b/w wires
IR Drop: Reduction in supply voltage ,that occurs power supply networks in IC,due to increasing current
density ,this causes the voltage available at Standard cells to be a lower than the what is desired .
IR=IR(V=IR VOLTAGE DROP)
There are two types of IR drop
• Static IR drop
• Dynamic IR drop
Static IR drop:
• This drop is independent of cell switching
Dynamic IR drop :
. This drop is calculated with the help of the switching of cells.
Methods to improve static IR drop
Methods to improve dynamic IR drop
1.
We can go for higher layers if available
1.Use de-cap cells
2.
Increase the width of the straps.
2. Increase the number of straps
3. Increase the number of wires.
4. Check if any via is missing then add more via.
ELECTROMIGRATION
Methods to solve EM:
1.Increase the width of wire
2.Buffer insertion
3.Downsize the driver
4.Switch the net to higher metal layers.
5.Adding more vias
6.Keep the wire length short
LOW POWER DESIGN
Power Dissipations :
Static (During stable condition)
1.
Leakage current /Sub-threshold current
2.
Gate oxide leakage current
Dynamic ( During Switching activity)
1.
Switching power dissipation
2.
Short Circuit (SC) Power Dissipation
Low power Design Cells
1. Level shifters
2. power switches
3. Isolation cell
4. Retention registers /cells These are Used in Power Management Techniques
POWER MANAGEMENT TECHNIQUES
1.Clock Gating Method: (Place the ICG (integrated clk gate cells )) it makes particular ckt. is active
2.Multi Vth Design: (LVT & HVT cells)
3.Multi voltage Design: (when 2 dffnt. Voltage domains contains in chip we will use Level Shifters)
4.Power Gating Method: It is similar to Clock gating
power switches : It makes to always turned on in specific time)
Isolation cells: It ll work isolate nets b/w gated domain and always on block ,means it will be
clamped either 0 or 1
Retentions cells:If gated domain off state ,system consist of flip-flops we will lose the data we need to
retain the data so we will be use this cells
OUTPUT OF POWER PLANNING /CHECKS
Outputs:
1. Design with power structure.
2. Floorplan with synthesized power mesh.
Checks:
1. check_pg_missing_vias
2. check_pg_drc
3. check_pg_connectivity
4. (Report_power)
5. (Analyze_powerplan…)
6. (Check_design –checks pre_placement_stage)
PHYSICAL ONLY CELLS
These are Typically invented for chip finishing
(Tie Cells (these are used for preventing damage of cells) not a pre-placed cells
Pre-placed cells
1.EndCap cells (Before placing the standard cells )
These are added to end of the cells rows and around the boundaries (core area,macro,blockages ,voltage area and corner cells)
2.Well tap cells ( To avoid the latch-up: low impedance path gets formed between VDD and GND terminal and there is direct current flow
from VDD to GND)
To reduce the resistance values tap the N well to VDD and P substrate VSS
3.Decap cells (To avoid the dynamic IR Drop)
It will provide instantaneous current to driveres to reduce IR drop
4.Filler Cells (after placement ,to cover the any gab )
We can fill empty space in the standard cells rows and it will provide continuity in the rows for VDD and VSS Nets
5.Spare cells ( after Routing any violations appear. It is reducing time & cost )
PLACEMENT
 placement is the process of finding the suitable physical location for each standard cell in the
design
standard cells are placed on placement tracks with automatically at placement stage
Steps:
1. Pre Placement
2. Initial Placement / Course Placement / Global Placement
3. Legalization
4. HFNS (High Fanout Net Synthesis)
5. Iteration for Congestion, Timing, DRV, and Power Optimization
6. Timing optimization iterations
7. Scan-Chain Reorder
PLACEMENT
Goals of Placement:
1. Timing,area,and power optimization
2 . Routable Design
3 . Min.cell density ,pin density (Reduce the congestion due to cells and pins)
4. Minimum timing DRC’s
Inputs To Placement Stage:
1. Netlist
2. Mapped and Floor planed Design
3. Logical and Physical Libraries
4. Design Constraints
PLACEMENT STAGES
1. Pre Placement:
 Before starting the actual placement of the standard
cells present in the synthesized netlist, we need to
place various physical only cells like end-cap cells,
well-tap cells, IO buffers, antenna diodes, and
spare cells
 Once the pre Placement stage has been
completed, We can start the placement of standard
cells
 but before that, we have to provide all the correct
placement and optimization settings that we want to
be applied while the tool does the placement and
optimization.
PLACEMENT STAGES
2.Global placement/Coarse placement:
 The std cells can be placed into the core region
 cells are overlapped , cells does not have legalized
locations
 it is rough placement
3 Legalization :
 The global placement stage, the instances are left with
overlap. In this step, the tool will move the instances in nearby
places to overcome the overlap. To match the proper power
pins like the VDD pin of a standard cell should be on the VDD
rail and VSS on VSS rail and for that if the flipping of instance
is required tool also do the flipping. This process is called
legalization.
PLACEMENT
4.( high fan out net synthesis :
Initially, there are some nets which have very high numbers of fanout.
We have a constraint of maximum fanout, so we need to distribute the sinks on nets
to different drivers.
The process of adding buffers and splitting the fanout is called high fanout net
synthesis (HFNS). So In this step, all high fanout nets get synthesize
 The buffering of high fan out nets to balance the load.
If you are not balance the load , transition time and delay is more
PLACEMENT STAGES
5.Iteration (the repetition of a process):for Congestion, Timing, DRV, and Power Optimization:
 In this step tool first, do an early global route and estimate the routing overflow/congestions in the design.
 The tool tries to initially minimize the congestion in this stage.
 Next, the tool starts the RC extraction to calculate the delay for setup analysis.
 The tool tries to minimize the setup WNS(Worst –Ve Slack) and TNS(Total –Ve Sack) in this step.
 Similarly, the tool also tries to minimize the DRV and Power in this stage.
6.Timing optimization iterations:
 This is a long step in which the tool tries to minimize the WNS and TNS of each path group in various iterations .
 There are several iterations required to get a minimum WNS and TNS depending upon the effort set and initial WNS number .
 In case the result is not good after this stage,
 we can further run incremental optimization for timing. Similarly, for congestion,
 we can run congestion repair followed by incremental optimization to get a better result. But these additional steps will increase the run
time
7.Scan chain reordering
This is nothing but scan-chain reordering.
 Scan-chain reordering helps to Reduce congestion and Total wire-length
Before
After
PLACEMENT
1.Placement Can be Done as
1.Timing Driven: Tool tries to place the standard cells along timing critical path close together to reduce net RC and meet setup timing.
check: create_placement -timing
2.Congestion Driven: when path for routability, Tool tries to spread the cells where the density of cells are more for the reduction of congestion.
Check: create_placement -congestion
3.Power Driven: In a library contains multiple-threshold- voltage cells,
 The LVT cells have higher leakage current but better performance.
 The HVT cells have lower leakage current but worst performance.
 Percentage low threshold voltage optimization tries to find a balance between power and performance goals restricted the
use of LVT cells.
 During low power placement, the tool tries to minimize the length of high switching nets to improve the power QOR.
 During Dynamic power-driven placement, the tool tries to improve both the timing and power of the critical nets and
the power QOR without affecting the timing QOR.
PLACEMENT BOUNDS
 It is a constraint , that controls the placement of groups of leaf cells and hierarchical cells.
 When our timing is critical during placement then we create bounds in that area where two
communicating cells are sitting far from another
 By using the bounds ,we can place the same group the cells into a bound.
 The wire length can be reduced
 It can be used for avoiding the congestion also.
Types of bounds
i)Hard bound (In this tool must place the cells in the move bound within a specified region.)
ii)Soft bound (In this tool tries to place the cells in the move bound within a specified region, however,
there is no guarantee that the cells are placed inside the bounds.)
iii)Exclusive bound:(In this tool tries to place the cells in the group bound within a floating region,
however, there is no guarantee that the cells are placed inside the bound)
OUTPUTS OF PLACEMENT & CHECKS
Outputs:
1.
Physical Layout Information
2.
Cell placement location
3.
Physical Layout Timing and Technology information of logical librarys
Checks:
1.
Check legalization command: Check_legality and report_congestion
2.
Check PG connections for all the cells.
3.
Check congestion, density screens & pin density maps all these should be under control
4.
Timing QOR, there should not be any high WNS violations.
5.
Minimum max Tran and max cap violations.
6.
Check whether all don’t touch cells & nets are preserved.
7.
Check the total utilization of design after placement
PLACEMENT STEPS PRACTICAL
• Create_placement – will perform coarse placement of std. cells in core area
• Legalise_placement – will place std. cells in their appropriate std. cell rows
• ‘Place_opt’ – This command will follow through a order of steps and places the std. cells in their
respective rows and attempts to legalise them as well as optimising the timing
• By default place_opt runs through 5 stages:
• 1. initial_place
• 2. initial_drc
• 3. initial_opto
• 4. final_place
• 5. final_opto
PRE -CTS OPTIMIZATION PLACEMENT OPTIMIZATION
Cell Sizing
Sized up/ down to meet optimizing for timing and area
Up sizing will give timing advantage and Down sizing will give area advantage
VT Swapping
To optimize for leakage power (HVT, RVT, LVT)
Cloning
Is to distribute the load , To reduce fan out
Buffering
Long nets are buffered or remove buffers to bring the timing advantage
Logical Restructuring
To optimize timing and area without changing the functionality of the design
Breaking complex cells into simpler cells or vice versa
Pin Swapping
PRE CTS OPTIMIZATION
Set Non-Default Rule (NDR): Clock nets are very sensitive and impacts timing if it changes a
little.
 NDRs make the Clock Routes less sensitive to Crosstalk or EM effects
 Double/ Triple Width for avoiding Electro migration
 Double/ Triple Spacing for avoiding Crosstalk
 NDRs will improve Insertion Delay
Set the target skew and target latency
(Ex: set_clock_tree_options –clocks [get_clocks {clk}] –target_latency 0.450 –target_skew 0.150
Check legality : (check_legality)
BEFORE GOING TO CTS CHECKS
 It should meet the following requirements:
 The clock source are identified with the create clock or create_generated_clock commands.
 The placement of standard cells and optimization is done. {NOTE: use check_legality –verbose
command to verify that the placement is legalized. If cells are not legalize the qor is not good and it
might have long run time during CTS stage}
 Power ground nets- pre-routed
 Congestion- acceptable
 Timing – acceptable
 Estimated max Tran/cap – no violations
 High fan-out nets such as scan enable, reset are synthesized with buffers.
CLOCK TREE SYNTHESIS (CTS)
 Clock is not propagated before CTS so after clock tree build in CTS stage we consider hold timings and
try to meet all hold violations..
 CTS is the process of connecting the clocks to all clock pin of sequential circuits by using
inverters/buffers in order to balance the skew and to minimize the insertion delay. All the clock pins
are driven by a single clock source. Clock balancing is important for meeting all the design constraints
 . Effect of CTS: Clock buffers are added congestion may increase non-clock cells may have been
moved to less ideal locations can introduce timing and tran/cap violations

before the clock tree is not build
CTS structure after clock tree build
CLOCK TREE SYNTHESIS (CTS)
CTS Quality Checks:
 Minimize Insertion Delay.
 Skew Balancing
 Duty Cycle
 Pulse Width
 Clock Tree power consumption
 Signal Integrity and Crosstalk
INPUTS REQUIRED FOR CTS:
1.Placement DB : (Netlist, DEF, LIB, LEF, SDC, UPF )
2. CTS Spec File:
 Target latency and skew if specify (SDC)
 Buffer or inverters for building / balance the clock tree
 The source of clock and all the sinks where the clock is going to feed (all sink pins).
 Clock tree DRC (max Tran, max cap, max fan-out, max no. of buffer levels)
 NDR (Nondefault routing) rules (because clock nets are more prone to cross-talk effect)
 Routing metal layers info. VIA's information used for clocks
CTS TARGET & CTS GOAL:
CTS target:
• To make Skew Zero. For this we this reason we will need to synthesize the clock tree
• To Balance Insertion Delay
CTS goal:
• Max Tran
• Max cap
• Max fan-out
• A buffer tree is built to balance the loads and minimize skew, there are levels of buffer in the clock tree
between the clock source and clock sinks.
• To fix the setup and after CTS you should meet all the Hold Violations
CLOCK TREE SYNTHESIS (CTS)
If clock is divided then separate skew analysis is necessary.
Skew: This phenomenon in synchronous circuits. .
The Difference in arrival of clock at two consecutive pins of a sequential element..
Global skew: the difference between max insertion delay and the min insertion delay
Local skew : Difference in arrival of clock at two consecutive pins of sequential element.
it can be positive and negative local skew also
Useful skew: If the clock is skewed intentionally to resolve setup violations
Positive skew: if the capture clock comes late than the launch clock.
Negative skew: if the capture clock comes early than the launch clock.
Zero skew: when the capture clock and launch clock arrives at the same time. (ideally, it is not possible)
CLOCK TREE SYNTHESIS (CTS)
Insertion delay: Time taken to reach clk source to leaf point is called
Latency: The delay difference from the clock generation point to the clock endpoints.
ON-CHIP CLOCK SOURCE
There are two types of latency:
Source latency: Source latency is also called insertion delay. The delay from the clock source to the
clock definition points. Source latency could represent either on-chip or off-chip latency.
Network latency: The delay from the clock definition points (create_clock) to the flip-flop clock pins
CLOCK TREE SYNTHESIS (CTS)
Advantages of the low Latency:
 Less buffer, hence less power consumption. As we know clock paths are the heaviest power dissipated path.
 Cell area reduction as less buffer in the clock path.
 Less runtime since less buffer need to be inserted in the design, which saves optimization as well
Duty Cycle : The on time and off time totally depends upon the rise transition and fall transition.
Due to transition differences, duty cycle changes and hence the calculation becomes bad. Practically, rise and fall
transition are not same.
Pulse Width: If we have variation in rise and fall transition from the input transition of rise and fall, then the
threshold (50%) will go worse. Hence the pulse width will decrease.
If pulse width decreases, then we might lose data which was about to be captured at some time.
CLOCK TREE SYNTHESIS (CTS)
Clock Uncertainty: the difference between the arrivals of clocks at registers in one clock
domain or between domains.
Timing Uncertainty of clock period is set by the command (set_clock_uncertainty ) at the synthesis stage to
reserve some part of the clock period for uncertain factors (like skew, jitter, OCV, CROSS TALK, MARGIN or any
other pessimism) which will occur in PNR stage
Clock uncertainty for setup effectively reduces the available clock period by the specified amount
• Pre CTS uncertainty = clock skew + jitter + margin
• CTS uncertainty = jitter + margin
CLOCK TREE SYNTHESIS (CTS)
• Clock Buffers:
 are designed with some special property like high drive strength and less delay.
 Clock buffers have equal rise and fall time.
 This prevents duty cycle of clock signal from changing when it passes through a chain of clock
buffers.
Normal buffers:
 are designed with W/L ratio such that sum of rise time and fall time is minimum.
 They too are designed for higher drive strength.
CLOCK TREE SYNTHESIS (CTS)
• Clock Tree Exceptions :
 Stop Pin: No buffer/inverter insertion beyond this point (Don't touch scenario)
 Ignore Pin : (Float Pins) No DRV, No Balance
 Exclude Pin : DRV Fixing but no balancing
 Through Pin : DRV Fixing as well as Balancing
 Don’t buffer nets :
 Don’t size cell :
CLOCK TREE SYNTHESIS (CTS)
What is Signal Integrity : The nets routed that even nets are at their track but impacted by the noise from
other nets. This unwanted element is called Signal Integrity
Crosstalk?: Crosstalk is the undesirable electrical interaction between two or more physically adjacent nets due to
capacitive cross-coupling.
Crosstalk noise: During the transition on aggressor net causes a noise bump or glitch on victim net. This noise
is known as crosstalk noise..
Reasons for Crosstalk:
.How To fix Crosstalk Issue
 Increasing number of metal layers,
1. Double spacing=>more spacing=>less capacitance=>less cross talk
 Routing congested Design
2. Multiple vias=>less resistance=>less RC delay
 Thin and long metal layer routed
3. Shielding=> constant cross coupling capacitance =>known value of crosstalk
 Faster waveform due to higher frequencies- 4. Buffer insertion=>boost the victim strength
 Low voltage design
CTS(CLOCK TREE SYNTHESIS
Types of Clock Trees:
1.
1.
H-Tree
2.
Balanced Fanout Clock Tree
3.
Binary Clock Tree
4.
Mesh tree
5.
Fish-bone tree 2. Balanced Fanout TREE
6.
X-tree
3. Binary Clock Tree
4. X-tree
Outputs: Database with properly build clock tree in the design
Checks:
1)report_timing -delay_type min
2)report_timing -delay_type max
3)report_clock -skew
Clock tree synthesis is performed using command clock_opt. Here clock tree is built keeping in
mind skew and hold time .
Clock_opt undergoes 3 stages by default i.e
1.
build_clock
2.
route_clock
3.
final_opto
ROUTING
Before going to routing we need to check
1.Target skew ,Target Latency should be met in CTS stage
2.We Should check Setup and Hold Violations met or not
3.DRV (Design Rule Violations)
4.No of Clock buffers and Inverters added should be in control
ROUTING
• Routing: creating physical connection to all logical connection present in the design with the help of
metal layers is known as routing
Objectives
 minimize the total wire length
 minimize the vias
 Routed paths must meet setup and hold timing margin
 minimizing the congestion hotspots.
 Complete the connections with out increasing the total area of the block.
 Reduction in cross talk noise.
 meeting the timing DRC’s and obtaining a good timing QOR
 minimize the critical path delay
ROUTING CONSTRAINTS
 setting the maximum length for the routing wires
 Blocking routing in specific regions
 set straighten guidelines for minimum width and minimum spacing.
 set preferred routing directions to specific metal layers during routing
 constraining the routing density
ROUTING FLOW
1.Global routing
 Does not consider DRC rules ,which gives an overall view of routing and congested nets.
 Assign layers to the nets
 Avoid congested areas and long detours.
 Avoid routing for Blockages
 Avoid routing for pre route nets. such as Rings/stripes/Rails
 Identify and assign the net segments over the specific routable window called Global route
cell(GRC).
ROUTING FLOW
2)Track Assignment
 Assign tracks both Horizontal and vertical direction
 It does not follow the physical DRC rules.
 It will do the timing aware Track assignment.
 It helps in via minimization.
3)Detail Routing
 It performs the complete DRC aware and timing driven routing.
 It is the final routing.
 Detail routing is done after analyze the cause for congestion in the design
TIMING ANALYSIS:
Timing analysis is necessary to calculate the design’s system performance, describes the chips
specification.
Types of timing analysis: Static timing analysis (STA) and Dynamic timing analysis
1.Dynamic timing analysis (DTA) (Gate level Simulation):
A series of vectors over a time are applied during a simulation run, simulation calculates the logic value
and delays over that time. So, in that manner we check the design’s functiality with time. on
TIMING ANALYSIS:
2.Static Timing Analysis:
Static timing analysis is a method of validating the timing performance of a design by checking all
possible paths for timing violations under worst-case conditions.
. So, it validates the design for desired frequency of operation, without checking the functionality
of the design
Dynamic timing
STA COMPARISON DTA
1.
Requires exhaust set of vectors
2.
Checks for both functional and timing problems
3.
Requires more resources (like run time, CPU memory, etc.)
4.
Can work with any type of Logic either synchronous or asynchronous
5.
Slower as compared to STA.
6.
Easy to learn and all corners cases are not covered
Static timing
1.
Doesn't requires any set of vectors.
2.
Checks for timing only.
3.
Requires fewer resources than DTA.
4.
Restricted to synchronous part of the design only.
5.
Faster as compared to DTA.
6.
Difficult to learn
STA( STATIC TIMING ANALYSIS)
What is STA ?:
Static timing analysis is one. of the techniques used to verify the timing of a digital design.
Why Static timing Analysis?
1. To analyze the timing relationships of a given circuit to verify that the circuit works at the specified
frequency (verification).
2. You can’t achieve the clock speed without it.
3. All paths are assumed critical.
4. Process variation across die can be modeled.
5. Constraints and reports are concise and easy to interpret.
6. It can detect other serious problems like glitches, slow paths and clock
INPUT AND OUTPUT FILES OF STA :
INPUTS:
Netlist (.v): The gate level netlist, having circuit description.
Constraints (.sdc): Synopsys Design Constraint file. It contains all the timing related information about the
design. Includes the Clock definition (Created clock, generated clock, Virtual clock), Uncertainty (Jitter, Skew,
Extra margin), IO Delays, False paths, Multi-cycle paths, Max trans, Max fanout, Max cap, Fanout load.
SDF (.sdf): Standard Delay Format File containing back-annotated delays.
OR
Standard Parasitic Exchange Format (.spef): These are the parasitic of the design extracted from physical design
tools.
Liberty File (.lib): The delay model of every cell in the library.
OUTPUTS
Reports: Different timing paths reports, which can be used for debugging.
STATIC TIMING ANALYSIS
STA involves three main steps:
1.
Break the design into sets of timing paths
2.
Calculate the delay of each path
3.
Path delays are checked to see if timing constraints have been met.
But first some Basic STA concepts: Timing Paths:
Each path has a start point and an endpoint
Start points:
Input ports (A, Q)
Clock pins of sequential devices (CLk)
Endpoints:
Output ports (D, Z)
Data input pins of sequential devices (D) by sing these points we can identify the Path
STATIC TIMING ANALYSIS
1. STA TOOL Break the design into sets of timing paths
2.Calculate the propagation Delay along with each path
3.Check for timing violations (depending on the constraints eg: clock) on different paths and also inputs
/outputs interface.
Timing paths:
1.Data path,
2.Clock Path,
3.Clock Gating path.
4.Asynchronous path.
5.Critical path
6.Short path
STATIC TIMING ANALYSIS
1.Data path: We have 4 data paths
1.In to Reg ( Start Point (i/p), End Point (D1 ff )
2.Reg to Reg (start point ( D1 ff of clk) , end point (D2 ff
3.Reg to Out (start point (d2 ff of clk) , end point (o/p 1)
4.In to Out
(start point ( input ) ,end point (output2)
By using these points we can analyze
It timing reports
STATIC TIMING ANALYSIS
2.Clock Path: It is generated from PLL (Phased Lock Loop) In b/w start and end points there may
be lot of buffers and inverters
3.Clock Gating Path:
This is used in may synchronous ckts
For Reducing the dynamic power dissipation
STATIC TIMING ANALYSIS
4. Asynchronous Path:
1. A path from an input port to an asynchronous set or clear pin of a sequential element
2. We know that the functionality of set/reset pin is independent from the clock.
3.
Its level triggered pins and can start functioning at any time of data. We can say that this path is not in
synchronous with the rest of the circuit and so such type of path is called Asynchronous path.
STATIC TIMING ANALYSIS
 In a STA ,the entire chip we are dividing into 4 paths because ,analyze better way and we can debug it easily
Suppose we have any violations internally in those paths(In to reg ,reg to reg ,reg to out and In to out) ,we can fix
and close the block. By using Setup and Hold Timing Violations:
Some basic Definitions:
: Is a signal that oscillates between high and low logic. Clock controls timing in
the design there can be multiple clocks in the design.
1. Clock
2. Setup Time: the amount of time the Synchronous input (D) data must be stable before the active edge of the
Clock.
3.
Hold Time :The amount of time the synchronous input (D) data must be stable after the active edge of clock.
4. Slack : The difference between arrival time and required time is called slack
STATIC TIMING ANALYSIS
Clock skews (timing skew):
Clock signal in synchronous circuits ,arrives at different components(generally latches or FFs) at different times.
STATIC TIMING ANALYSIS
1. Launch Path
Launch path is launch clock path which is responsible for launching the data at launch flip flop
2. Capture Path
Capture path is capture clock path which is responsible for capturing the data at capture flip flop
3. Arrival Time
Launch path and data path together constitute arrival time of data at the input of capture flip-flop
4. Required Time
Capture clock period and its path delay together constitute required time of data at the input of capture flop
STATIC TIMING ANALYSIS
1. Positive Slack indicates that the design is meeting the timing and still it can be improved.
2. Zero slack means that the design is critically working at the desired frequency.
3. Negative slack means , design has not achieved the specified timings at the specified frequency.
4. Slack has to be positive always and negative slack in
STATIC TIMING ANALYSIS
There are 3 basic paths where the Set-up/Hold violations may occur:
inputs-to-register path -- actually if there is any violation in this path then first you have to see the
"set_input_delay" setting. By changing the value you can fix this path. setup and hold can be fixed by
constraining input delay and clock period
register-to-outputs path -- same with this case.. yo can do concentrate on set_output_delay setting.
So basically these 2 can be managed by timing budgetting of a particular block. if you want to fix
these inside the block, you can also use buffer/delay inside the block, else add these delay and all
outside the block. And for the block the effective value of the delay changes and that can be fixed by
setting different value of set_input_delay/set_out_put delay.
register-to-register path .. all the general ways like delay insertion/swapping/resizing ..etc will be
the part for this path in case there is any violation.
STATIC TIMING ANALYSIS
• Setup Slack: Required time > Arrival time [RT-AT]
Setup Equation: [Tlaunch+Tck2q+Tpd]<[Tcap+Tclk-Tsetup]
• Reasons for violations :
Capture clock comes early than launch clock,
Because of high delay in the data path or When data and clock are routed in opposite direction then it is negative skew.
To Fix The Setup Violations:
1 Reduce the amount of delay in data path, this can be done by reducing the necessary buffers
2.VT swapping, means you swap HVT cell with SVT or LVT cells
[size_cell instancename(present cell) referencename(replacing cell]
3. Buffering:
Use of two inverters in place of buffer ,if a cell is driving an exceptionally long net. considering that the driver cell
already has good driving strength, buffering helps to split the net which in turn reduces the total capacitance. Hence the
data path delay will be reduced, and arrival time reduces. [ insert_buffer netname referencename (buffer)]
4. Readjusting the position of cells
STATIC TIMING ANALYSIS
5.Skewing:
Positive skew is good for setup and negative skew is good for hold
6. Gate Sizing: Upsizing cell
If a low driving strength cell is driving a higher load, it results in higher cell delay.
To fix this, one can upsize the cell which will reduce cell delay and helps to meet the setup time. 3. How upsize will help
for fixing the setup violations?
Upsizing means increasing the drive strength, if drive strength increases the width of the
gate increases, if width increases the resistance reduces, as resistance and delay are directly
proportional to each other if resistance reduces the delay also reduces in this way upsizing
will help in fixing setp violations.
7. Cloning:
Cloning refers to creating the same driver cell with the same functionality and giving it the same inputs as the original
cell.
If gate sizing and buffering are not possible, then cloning can be helpful as this will split the load between the original
cell and the newly cloned cell
STATIC TIMING ANALYSIS
Hold Slack check= Required time < Arrival time [AT-RT]
Hold Equation : :[Tlaunch+Tck2q+Tpd]>[Tcap+Thold]
Reasons for Hold Violations :
If capture clock comes late than launch clock then it is called +ve skew
If data comes early or due to positive skew.
When data and clock are routed in same direction then it is Positive skew.
It is possible to have a flip flop with 0 hold time or negative hold time.
For example, if the hold time is -3 ns then it complies that we should not have any change in the input
data before 3ns of the clock event trigger
Minimum Time Period (T minimum) or Maximum clock operating frequency (F maximum)
1.
To decide the speed of a chip design clock cycle frequency is the main parameter.
2.
We all want a high-speed chip or processor which means the clock frequency must be as high as possible.
3.
But we also know that clock frequency is inversely proportional to clock time period. So here we will have to constrain
on the minimum time period to be decided.
STATIC TIMING ANALYSIS
• To Fix Hold Time Violations:
1.
Vt swapping from LVT to HVT cell
2.
Pushing the launch clock
CLOCK PUSH –INSERT_BUFFER
3.
Pulling the capture clock
CLOCK PULL –REMOVE BUFFER
4.
Inserting Buffer at D pin
5.
Metal width decreases
6.
Net deteriorate
7.
Using spare cells after BTO (Base Tape Out)
8.
Inserting metal buff's after BTO
9.
Voltage can be reduced.
10. Downsizing the cell
11
Skewing:
• Either we can late skew i.e. increase the clock network delay of launch flop making data to launch late or we can early skew
i.e. reduce the clock network delay of capture flop so that data will be reaching faster at the endpoint.
STATIC TIMING ANALYSIS
• Hold time constraint
•
Thold_time <= Tclock_Q + delay
The hold time must be less than or equals to the sum of the clock to Q delay and other delays such as clock
jitter
• Setup time constraint
Tsetup_time + Tclock_Q + delay <= Tminimum
• Which says the overall sum of flop setup time and clock to Q delay and other delays such as jitter must be
less than or equals to the minimum clock time period.
• Note:
• If a situation comes to have a choice between setup violation fix and hold violation fix after the chip design
is completed and fabricated, then it is a better option to chose hold violation fix.
• The reason is to fix the setup time violation we need to modify Tminimum.
• As we saw above setup time constraint involves clock time period parameter which decides the overall
chip speed which cannot be modified after the chip come from the foundry.
STATIC TIMING ANALYSIS
Delays
Time taken by a signal to propagate through a Cell or Net
1. Gate Delay/Propagation Delay
Amount of delay from the input to the output of a logic gate. It is calculated based on 2 parameters.
Input Transition Time
Output Load Capacitance
2. Net Delay:
Amount of delay from the output of a gate to the input of the next gate in a timing path. It depends on
the following parameters.
Parasitic Capacitance.
Resistance of net
Insertion Delay : The delay between the clock root pin and clock sink pin of the flip flop
STATIC TIMING ANALYSIS
Jitter: Jitter is the variation of the clock period from edge to edge. It can vary +/- jitter value.
OR Variation in period from clock source (PLL)
Critical Path
• The path which creates longest delay
• Also called worst path/ late path/ max. path
Shortest Path
• One that takes the shortest time; this is also called the best path or early path or a min path
STATIC TIMING ANALYSIS
Timing Exceptions: Timing exceptions are nothing but constraints.
Single Cycle Path
 Timing path that is designed to take only one clock cycle for the data to propagate from the start point to the endpoint
 Start point and endpoint are flops clocked by the same clock
 By default tool will consider all timing paths as single cycle paths
Multi-Cycle Path
 Timing path that is designed to take more than one clock cycle for the data to propagate from the start point to the endpoint
 Start point and endpoint are flops clocked by the same clock This is usually a large combinational block between two registers.
Half Cycle Path
 Timing path that is designed to take half clock cycle (both of the clock edges) for the data to propagate from the start point to the endpoint
 Start point and endpoint are flops clocked by the same clock( hold edge of capture flop can be earlier than the hold edge of launch flop)
False Path
 Physically exist in the design but are Logically/ Functionally inactive/ incorrect path
 Means no data is transferred from Start Point to End Point
STATIC TIMING ANALYSIS
Recovery and Removal Time:
• These are timing checks for asynchronous signals similar to the setup and hold checks
• Recovery time: Recovery time is the minimum amount of time required between the release of an asynchronous signal from the active state
to the next active clock edge.
• Removal time: Removal time specifies the minimum amount of time between an active clock edge and the release of an
asynchronous control signal.
Design Rule violations (DRV’s
Maximum Transition Time (Max Tran)
1. Time required by a pin to change logic values ( 0 to1 or 1to 0) is called Transition time
2. the longest time required by a pin to change logic values is called Maximum Transition time.
3. Due to this , large dynamic power dissipation can happen.
4. To reduce the maximum transition time by adding buffers on the net
fixes:
1)replace hvt to lvt
2)replace net length by adding buffers
3)increase driver size
STATIC TIMING ANALYSIS
Design Rule violations (DRV’s
Maximum capacitance (Max Cap.)
1. It is the capacitive load on output pin can drive.
2. the output pin of cell can drive the inter connect capacitance of net and input
capacitance of cell.
3. If large capacitance load is there , it will take more time to charge or discharge.
4. to avoid this ,high drive strength cells are used , then it can drive the more load
capacitance.
fixes:
1)upsize driver cell
2)adding buffer in mid of long route
STATIC TIMING ANALYSIS
• Maximum fan out (Max Fanout)
1. output can drive other inputs without any degradation
2. If load increases ,current will be degraded
3. cloning and load splitting can be used to reduce the fanout
fixes:
1.
Reduce fanout by load splitting by buffering
2.
Cloning :Cloning is a good method to distribute the load and to improve the signal
strength.
STATIC TIMING ANALYSIS
• Min pulse width violation:
1. If we have variation in rise and fall transition from the input transition of
rise and fall, then the threshold (50%) will go worse. Hence the pulse width
will decrease.
2. If pulse width decreases, then we might lose data which was about to be
captured at some time.
STATIC TIMING ANALYSIS
Virtual clock:
1.Virtual clock as the name suggests doesn't exist physically in the design at all, its just used for the specifying
the input / output delay values ( if no clock is existing )
2. Virtual clock can be created same as Create_clock, except that the port/pin name must not be specified !
incase if u have a purely combination path and if u want to specify a
set_input_delay
or
set_output_delay
for that path, then the virtual clock is used
STATIC TIMING ANALYSIS
• Signal Integrity :Signal Integrity is the ability of an electrical signal to carry information reliably
And TO resist the effects of high-frequency electromagnetic interference from nearby signals.
Effects: CrossTalk, EM, Antennae Effects.
CrossTalk:
Crosstalk is the undesirable electrical interaction between two or more physical adjacent nets due to cross coupling capacitance
or
The switching activity in aggressor net overlaps (or) going to affect the victim net
. Crosstalk can lead to crosstalk-induced delay changes or static noise.
• There are two types of crosstalk:
1) crosstalk noise
2) crosstalk delay
Glitch- A glitch is a short-lived fault in a system.
An electrical pulse of short duration that is usually the result of a fault or design error, particularly in a digital circuit
STATIC TIMING ANALYSIS
Crosstalk noise: If one net is switching & another neighbouring net is at constant logic.
If they have mutual capacitance between them, other net may be affected & that net may have a
sudden raising or falling bump or spike.
such a spike on victim net is called crosstalk noise/glitch
STATIC TIMING ANALYSIS
Crosstalk Delay:
It occurs ,when both aggressor & victim nets switching together. which may violate setup time/hold time
violations
How timing will effect with crosstalk delay?
1.When both the nets are switching in the same direction due to crosstalk the delay reduced in the victim due to this we get
hold violations in data path and setup violations in clock path.
2. When both the nets are switching in the opposite direction due to crosstalk the delay increases in the victim due to this we
get setup violations in the data path and hold violations in clock path
STATIC TIMING ANALYSIS
• PVT: PVT is abbreviation for process, Voltage and Temperature. In order to make our chip to work in all possible conditions,
• Process:
• Process variation is the deviation in attributes of transistor during the fabrication.
Process variation is gradual . It can not be abrupt.
Process variation is different for different technologies but is more dominant in lower node technologies (<65nm).
Below are few important factors which can cause process variation;
1.
Wavelength of the UV light
2.
Manufacturing defects
The affects of process variation are listed below;
1.
Oxide thickness variation
2.
Dopant and mobility fluctuation
3.
Transistor width, length etc.
4.
RC Variation
STATIC TIMING ANALYSIS
These variations will cause the parameters like threshold voltage to change its value from expected.
Threshold voltage depends on oxide thickness, source-to-body voltage and implant impurities.
Consider the drain current equation for NMOS;
ID = (1/2)μnCox (W/L)(VGS – VTh)2
As we are talking about process variation, it deals with physical properties of MOSFET. So, current
flowing through the channel directly depends upon mobility (μn), oxide capacitance Cox (and
hence thickness of oxide i.e. tox) and ratio of width to length.
Any of these parameters change, it will result in changing the current. In other words, it will affect
the delay of the circuit. Delay decreases with increase in current.
STATIC TIMING ANALYSIS
Voltage:
There are multiple reasons for voltage variation. These are discussed below.
The important reason for supply voltage fluctuations is IR drop. IR drop is caused by the current flow over
the parasitic resistance of the power grid. IR drop reduces the supply voltage from the required value.
The second important reason for voltage variation is supply noise caused by parasitic inductance in
combination with resistance and capacitance. The current through parasitic inductance causes the voltage
bounce. Both these effects together can not only lead to voltage drops but also voltage overshoot.
Supply voltage that any chip works on is given externally. It can come from DC source or some voltage
regulator. Voltage regulator will not give same voltage over a period of time. It can go above or below the
expected voltage and hence it will cause current to change making the circuit slower or faster than
earlier.
STATIC TIMING ANALYSIS
Temperature:
The temperature variation is with respect to junction and not ambient temperature. The temperature at
the junction inside the chip can vary within a big range and that’s why temperature variation need to
be considered. Figure 3 shows the variation of delay with respect to temperature.
Delay of a cell increases with increase in temperature. But this is not true for all technology nodes.
For deep sub-micron technologies this behavior is contrary.
This phenomenon is called as temperature inversion.
The delay depends on the output capacitance and ID current (directly proportional to Cout and
inversely proportional to ID). When the temperature increases, delay also increases (due to the
variation in carrier concentration and mobility). But when temperature decreases, delay variation
shows different characteristics for submicron technologies. For technology nodes below 65nm, the
delay will increase with decrease in temperature and it will be maximum at -40°C. This phenomena is
known as “temperature inversion”.
STATIC TIMING ANALYSIS
Why Temperature inversion happens?
As temperature increases, mobility and threshold voltage start decreasing. The delay is inversely
proportional to the mobility and directly proportional to the threshold voltage.
So the resultant effect from both mobility and threshold voltage decides the value of delay.
Consider the current equation of a MOSFET for better understanding;
ID = (1/2)μnCox (W/L)(VGS – VTh)2
In the higher technology node, where the supply voltage is very high, the effect of VTh is very low as (VGS
– VTh) value is large. Hence mobility plays major role in deciding current. So at higher technology nodes,
when the temperature increases mobility decreases and as a result the delay will increase.
At the lower technology node (specifically, less than 65nm), the supply voltage is very low, so the (VGS –
VTh) difference is small and the square of this value is very small resulting reduced ID current, which
increases delay at lower temperature. Where at other end above 65nm delay decreases at lower
temperature.
STATIC TIMING ANALYSIS
RC Variation:
RC variation is also considered as corners for the setup and hold checks. RC variation can happen
because of fabrication process and the width of metal layer can vary from the desired one
Critical corners for Setup and Hold check
We always check our chip to work in worst scenarios. We should be very pessimistic about setup and hold checks. So consider worst case
scenarios.
Setup violation can be caused if data is coming very slow. So the condition when process is slow, voltage is minimum and temperature is maximum
is the worst case for setup check. Also because of temperature inversion at lower technology node, delay will increase as temperature decrease.
Hence lowest temperature results in more delay. It is not compulsory that the delay at lowest temperature is always less than delay at highest
temperature.
Hold violation is caused if data comes faster. So process should be faster, voltage should be maximum and temperature should be minimum.
Now if setup and hold are checked in worst corners, then the chip should work in every scenario. Still we check them in typical corners because
we need to analyze power consumption. Refer following table for the worst case scenarios for setup and hold.
STATIC TIMING ANALYSIS
OCV,AOC AND POCV
1.
During fabrication the chips on the same die may suffer from variations due to process, voltage or temperature
change, thus transistors can be faster or slower in different dies.
2.
To compensate the variation, static timing analysis(STA) introduces a concept called On Chip Variation(OCV).
3.
During design time, extra timing margins are added in timing analysis.
4.
OCV has been evolved to Advanced On Chip Variation(AOCV), or even Parametric On Chip Variation(POCV).
5.
On Chip Variation(OCV): This concept is related to fabrication process, these variation related to fabrication steps
first is Etching and second is oxide thickness.
There are two types of variation:
Global Variation: These variations are die to die or inter-chip variation. They depend on Pressure, voltage and
temperature.
Local Variation: These variation are intra-chip variations and local variation are taken by derates, timing derates are
multiplied by cell delays and wire delays to account OCV.
STATIC TIMING ANALYSIS
Etching:
Etching is one of the sources of variation, which is used the define the structure of a transistor. In practical
case the width and length of transistor is different from the expected W and L ratio. The small change for one
transistor will result in big impact on chain of billion of transistor
From the above figure we observe that ideal case is different from practical case.Let
us take W and L in Ideal case . lt is different from W and L in actual case.
Now we will see how this small change in W/L ratio affect the cell delay
As we know the formula of Drain current
STATIC TIMING ANALYSIS
As we know the formula of Drain current
Drain current (ld) = u Cox (W/L) [(Vgs-Vth)Vds-(1/2)VdsA2]
Where u is mobility of charge carriers,Cox is capacitance per unit area, W is width of channel,L is channel length,
Vgs is gate to source voltage, Vth is threshold voltage and Vds is drain to source voltage.
We can observe from drain current equation Id is directly proportional to (W/L),
when we think of a capacitor at the output of an inverter then capacitor charging depends on the
amount of current that is flowing it.
If drain current changes the amount of time taken by capacitor definitely.
If drain current (ld) is high then capacitor takes less amount of time to charge and
hence delay is minimum.
If drain current (ld) is low then capacitor takes huge amount of time to charge and
hence delay is maximum .
Hence we can say that delay decrease with increase in current and vice versa.
STATIC TIMING ANALYSIS
Oxide thickness:
Oxide thickness is another source of variation, In practical case the oxide thickness is not uniform along the
channel.
We know the drain current equation,
Drain current (ld) = uCox(W/L)I(Vgs-Vth)Vds-(1/2)Vds^2].
where Cox=Eox/tox , ld is inversely proportional to tox.
If the value of tox changes the value of drain current is also changes.
Now we will see how delay of cell is related to W/L and tox from formula point of view,
we know that delay of a cell depends on resistance(R) and capacitance(C)and from ohm's law
resistance varies as current changes.
Delay (tpd)=function(R,C)=f(ld)=f(tox,W,L)
STATIC TIMING ANALYSIS
As a result of OCV, some cells may be fast or slow than expected.
If these variations are not accounted, results maybe pessimistic and can lead to setup or hold
violations.
In order to model these, we introduce derates. Timing derates are multiplied with the net delay and
cell delay for the launch and capture clock paths.
STATIC TIMING ANALYSIS
How to calculate timing slack using OCV:
Setup Analysis: While calculating the setup analysis we need to take late derate along the launch path and early derate along the capture path.
Arrival Time:
Arrival time includes addition of cell and wire delays along the launch path.
Arrival Time(AT) = [wire1 delay late derate + clk to q *late derate + wire2 delay late derate inverter delay latederate+wire3 delay late
derate.]
Arrival Time(AT) =[ 0.1*1.1 +0.2*1.1+0.2*1.1+ 3*1.1 +0.4*1.1]
Arrival Time(AT) = 4.29 ns
Required Time:
Required Time(RT) = [Tclk-Tsetup+ [Twire delays'early derate+ Tcell delays'early derate]
RT [2-0.2+[0.3 0.9+2'0.9+0.4 0.9]
Required Time(RT) = 4.23 ns
Setup Slack RT-AT=4.23-4.29= -0.06 ns (-ve slack).Negative slack indicates setup violation
STATIC TIMING ANALYSIS
Hold Analysis: While calculating the hold analysis we need to take early derate along the launch path
and late derate along the capture path.
Arrival Time(AT) = wire1 delay early derate +clk to q early derate + wire2 delay early derate +
inverter delay early derate + wire3 delay *early derate.
Arrival Time(AT) = 0.1*0.9 +0.2*0.9 + 0.2*0.9 +3*0.9 0.4*0.9 3.51 ns
Required Time:
Required Time(RT) = T hold +Twire delays late derate+ T cell delays late derate
Required Time(RT) = 0.1+0.3*1.1+2*1.1 +0.4*1.1 3.07 ns
Hold Slack = AT-RT=3.51-3.07 0.44 ns(+ve slack) which shows hold condition is met
STATIC TIMING ANALYSIS
Without ocv
setup Analysis:
Arrival Time:
Arrival Time(AT) = wire1 + clk toq+ inv delay +wire3
Arrival Time(AT) = 0.1+0.2+0.2+3+0.4 3.9 ns
Required Time:
Required Time(RT) = Tclk-Tsetup + Twire delays + T cell delays
Required Time(RT) 2-0.2+0.3+2+0.4 = 4.5 ns
Setup Slack = RT-AT = 4.5-3.9 0.6 ns(+ve slack)
which shows setup condition is met.
Hold Analysis:
Arrival Time:
Arrival Time(AT) = wire1 + clk to q + inv delay + wire3
Arrival Time(AT) = 0.1+0.2+0.2+3+0.4 3.9 ns
Required Time:
Required Time(RT) = Thold + Twire delays + T cell delays
Required Time(RT) =0.1+0.3+2+0.4 2.8 nsHold Slack = AT-RT = 3.9-2.8 = 1.1 ns(+ve slack)
which shows hold condition is met.
From above two cases we conclude that we should always consider the derates and apply them to avoid timing violations
.
STATIC TIMING ANALYSIS
Advanced On chip Variation(AOCV):
In case of OCV constant derates are applied across the timing path. But in AOCV we multiply cell and wire delays with different
derate factors depending on the distance and depth.
AOCV is represented by a two dimensional table: the derate value of a cell is determined by logic depth and distance.
For smaller path depths OCV gives optimistic results when compared to AOCV. For larger path depths OCV tends to be more
pessimistic than AOCV(AOCV gives accurate values)
Parametric On Chip Variation(POCV):
Below 1Onm technologies AOCV cannot reduce pessimism hence to reduce the pessimism at lower technology nodes POCV
was introduced.
Here cell delay is calculated based on delay variation of cell, delay variation denoted by sigma and delay is denoted by u.
POCV models a cell delay using Gaussian distribution directly, instead of adding a derate value.
Cell delay is calculated from a parameter, which is extracted from either library, or POCV table.
Pocv-here the derates will be based up on the cell type and the special distance.
STATIC TIMING ANALYSIS
Different Modes
Function Mode
Scan Mode
Slowm40
Fastm40
Slow125
Fast125
Fastm40
Fast125
Corners
Slowm40…….(.lib+RC techfile Cmax
Slow125
Fastm40…….(.lib+RC techfile(Cmin|)
Fast125
STATIC TIMING ANALYSIS
Timing eco flow fixing order:
ORDER OF ECO FIXING STEPS
1. Before you attempt ECO fixing, ensure that the design is fully placed and routed, with generated
clock trees, and use physically aware ECO to ensure the best quality of results.
2. The Prime Time ECO commands and command option let the ECO fixing goals.
3. Setup or hold fixing does not degrade DRC (max_capacitance and max_transition) violations,
4. but DRC fixing can degrade setup or hold violations because DRC fixing has the highest priority.
5. Also, hold fixing preserves setup slack, but setup fixing is allowed to introduce some hold
violations, because setup is a harder problem to fix. Therefore,
6.
it is a good idea to fix DRC violations first, then setup violations, and finally hold violations
ECO FLOW
In the Primetime tool, an engineering change order (ECO) is an incremental change in a chip design to
reduce design rule constraint (DRC) violations, timing violations, or power.
The Primetime tool finds these design issues and corrects them by sizing cells, replacing cells, or inserting
buffers, and it writes out the changes in script format so that you can implement the changes in other tools.
The commands to perform ECO fixing are:
1.
fix_eco_drc
2.
fix_eco_timing
3.
fix_eco_power
After ECO fixing is complete, to implement the changes, use the write_changes command to write out the
changes, and run the script in the IC Compiler or IC Compiler II tool. After the changes are implemented,
you should perform parasitic extraction and run timing analysis again in the Primetime tool.
SETTING THE ECO OPTIONS
• Before you run any ECO fixing commands, follow these steps to set the ECO options:
1. Import the design into Primetime by reading the Verilog, SDC, and parasitic data files.
2. Set the timing_save_pin_arrival_and_slack variable to true.
3. Perform a full timing update (update_timing or report_timing).
4. Set the ECO variables that are relevant for your design or analysis conditions
ORDER OF ECO FIXING STEPS
Steps Commands Fixing
Step 3: Fix timing violations
Step1: Power recovery
fix_eco_timing Fixing mechanisms Buffer insertion, cell
fix_eco_powe Fixing mechanisms
Cell sizing, buffer removal sizing Setup fixing honors DRC and alters hold slack if
needed; hold fixing honors setup slack and DRC
Does not introduce new timing or DRC violations
Step 4: Final leakage recovery
Step 2: Fix DRC and noise violations
fix_eco_power Fixing mechanisms Threshold voltage
fix_eco_drc
Fixing mechanisms
Buffer insertion, cell sizing
swapping
Alters setup and hold slacks as needed
Does not introduce new timing or DRC violations; does not
change layout
STATIC TIMING ANALYSIS
• Bottleneck:
• NAME
report_si_bottleneck:
Identify the crosstalk bottlenecks in the design.
This is useful when the major sources of violations come from crosstalk effects.
SYNTAX
int report_si_bottleneck -cost_type type
Removing common clock buffer delay between launch path and capture path is CPPR. (common path pessimism
removal)
CPPR (CLOCK RE-CONVERGENCE PESSIMISM REMOVAL )
1. The delay difference along the common paths of the launching and capturing clock paths is called CRPR.
2. This common path delays are multiplied with different derates (early and late), resulting in different delays.
3.
These cells have max delay in launch path and min delay in capture path.
4. The same cell cannot have different delays at the same time.
5. This results in additional pessimism which has to be removed. Here comes the need for Clock Re-convergence Pessimism Removal
(CRPR) or Common Path Pessimism Removal (CPPR).
6. This pessimism value is the difference between the max and min delay at the common clock path.
7. To reduce pessimism, CRPR is added to required time in setup analysis and subtracted from required time in hold analysis.
8. CRPR = Max. value - min. value
9. In the CRPR process we are removing the derating to common buffer.
10. it is clear that with the CRPR method both setup and hold are benefited
11. some commands related to CRPR:
pt_shell>
set_operating_conditions -analysis_type on_chip_variation -min MIN -max MAX
set timing_remove_clock_reconvergence_pessimism TRUE
PT SHELL FLOW
1.
Starting from an RTL design.
2.
The Design Compiler tool generates a gate-level
design.
3.
From the gate-level netlist and physical library
information, the physical implementation tool (IC
Compiler or IC Compiler II) performs placement and
routing.
4.
The Star RC parasitic extraction tool extracts the
parasitic RC data from the chip layout database.
5.
The Prime Time tool reads the gate-level netlist and
parasitic data, and verifies the design timing using
information provided in the logic (.db) library.
6.
If the tool finds any violations, it can generate
engineering change orders (ECOs) that guide the
physical implementation tool to fix the violations and
optimize power.
PT SHELL
Compatibility With Galaxy Implementation Tools
The Prime Time static timing analysis tool is designed to work well with the Design Compiler synthesis tool and the IC
Compiler II place-and-route tool. These tools are compatible in the following ways:
1.
They use the same logic libraries and read the same design data files.
2.
They support the Synopsys Design Constraints (SDC) format for specifying design constraints, including the
timing and area constraints.
3.
They share many commands (such as create_clock, set_input_delay, and report_timing) that are identical or similar
in operation.
4.
They share the same delay calculation algorithms and produce similar delay results.
5.
They generate similar timing reports.
6.
Prime Time can provide engineering change order (ECO) guidance to IC Compiler II by generating change lists
that fix timing violations and optimize power.
Although the Design Compiler and IC Compiler II tools have their own built-in static timing analysis capabilities
The Prime Time tool has better speed, accuracy, capacity, and flexibility for static timing analysis.
PT_SHELL COMMANDS
Getting Help on the Command Line
To get help when running the Prime Time tool, use the following resources:
• Command help
❍ To list all Primetime commands, organized by command group, enter
pt_shell> help
❍ To show a brief description of a command, enter
pt_shell> help command_name
❍ To show all options and arguments for a command, enter
pt_shell> help -verbose command_name
• Man pages
To display the man page of a command, variable, or message, enter
pt_shell> man command_variable_or_message_nam
PT_SHELL COMMANDS
PT_SHELL COMMANDS
PT_SHELL COMMANDS
command fixes setup violations throughout the design:
pt_shell> fix_eco_timing -type setup
The following command fixes hold violations throughout the design using both cell sizing
and buffer insertion, and using exhaustive path-based analysis for reduced timing pessimism:
pt_shell> fix_eco_timing -type hold -pba_mode exhaustive \
-buffer_list {BUFX2 DLY1X2 DLY2X2
STATIC TIMING ANALYSIS
STA Checks:
1 Setup and Hold Violations
2.Recovery and Removal Timings
3.Mean Pulse width Violations
4.Design Rule Violations
PHYSICAL VERIFICATION
Physical Verification : It is a process whereby an integrated ckt layout design is verified via EDA
software tools to ensure correct electrical and logical functionality
EDA electronic design automation tool such a ic validator from synopsis an caliber tool by mentor
graphics
After routing your pnr tool should give you zero drc/lvs violations
The major checks are
1.DRC
2.LVS
3 ERC
PHYSICAL VERIFICATION
Design Rule Check (DRC)
Design Rule Check (DRC) is the process of checking physical layout data against fabrication-specific rules specified by the
foundry to ensure successful fabrication.
Process specific design rules must be followed when drawing layouts to avoid any manufacturing defects during the
fabrication of an IC.
Process design rules are the minimum allowable drawing dimensions which affects the X and Y dimensions of layout and not
the depth/vertical dimensions.
As Technology Shrinks Number of Design Rules are increasing Corsplexity of Routing Rules is increasing Increasing the
number of objects involved More Design Rules depending on Width, Halo, Parallel Length
PHYSICAL VERIFICATION
Design Rule examples:
Maximum Rules: Manufacturing of large continuous regions can lead to stress
cracks. So wide metal' must be slotted' (holes)
Angles: Usually only multiples of 45 degree are allowed
Grid: Al corner points must lie on a minimal grid, otherwise an "off griderror"
is produced
Minimum Spacing: The minimum spacing between objects on a single layer
Minimum Width: The min width rule specifies the minimum width of individual
shapes on a single layer
Minimum Enclosurel Overlap: Implies that the second layer is fully enclosed
by the first one Notch: The rule specifies the
minimum spacing rule: for objects on the same net, including defining the
minimum notch on a single-layer, merged object
Minimum Cut: the minimum number of cuts a via must have when it is on a
wide wire
PHYSICAL VERIFICATION
Order of fixes in signoff 1PO w.r.t To Intel:
1 Trclvs and Onlinelvs
2 Density Violation (Denallpheml)
3 Antenna Violations (Drc_IPHALL)
4 Drc_m1base
5.Drc_dv1up
6 Dfi_intergra (boundary violations)
7 Drc_sk (via stack violation) ..In 10nm tech more than 3vias can not be placed one above the other
PHYSICAL VERIFICATION
Layout Versus Schematic (LVS): DRC only verifies that the
given layout satisfies the design rules provided by the
fabrication unit. It does not ensure the functionality of
layout. Because of this, idea of LVS is originated.
• It is the method of verifying the layout of the design is
Functionally equivalent to the schematic of design.
Layout Versus Schematic (LVS) verifies the connectivity of a
Verilog Netlist and Layout Netlist (Extracted Netlist from
GDS) . Tool extracts circuit devices and interconnects from
the layout and saved as Layout Netlist (SPICE formats LVS
performs comparison between 2 Netlist, it does not
compare the functionalities of both the Netlist.
LVS FLOW
PHYSICAL VERIFICATION
• Inputs Requirements
1.
LVS Rule deck
2. Verilog Netlist
3. Physical layout database (GDS)
4. Spice Netlist (Extracted by the tool from GDS)
LVS rule deck : is a set of code written in Standard Verification Rule Format (SVRF) or TCL Verification Format (TVF).
It guides the tool to extract the devices and the connectivity of IC’s.
It contains the layer definition to identify the layers used in layout file and to match it with the local on of layer in
GDS. It also contains a device structure definitions
LVS checks:
Short Net Error, Open Net Error, Extract errors, Compare errors (Malformed Devices Pin Errors Device Mismatch
Net Mismatch)
PHYSICAL VERIFICATION
• Steps of LVS
• Extraction:
1.
The tool takes GDSII file containing all the layers and uses polygon based approach to determine the
components like transistors, diodes, capacitors and resistors and also connectivity information between
devices presented in the layout by their layers of construction.
2.
All the device layers, terminals of the devices, size of devices, nets, vias and the locations of pins are
defined and given an unique identification.
Reduction:
1.
All the defined information is extracted in the form of netlist.
Comparison:
1.
The extracted layout netlist is then compared to the netlist of the same stage using the LVS rule deck. In
this stage the number of instances, nets and ports are compared.
2.
All the mismatches such as shorts and opens, pin mismatch etc.. are reported.
3.
The tools also checks topology and size mismatch
PHYSICAL VERIFICATION
LVS Checks :
No of devices in schematic and its layout
Type of devices in schematic and its layout
No of nets in schematic and its layout
Errors occur
Shorts: Shorts are formed, if two or more wires which should not be connected together are connected
Opens: Opens are formed, if the wires or components which should be connected together are left floating or
partially connected.
Component mismatch: Component mismatch can happen, if components of different types are used (e.g., LVT cells
instead of HVT cells)
Missing components: Component missing can happen, if an expected component is left out from the layout
Parameter mismatch: All components has it's own properties, LVS tool is configured to compare these properties
with some tolerance. If this tolerance is not met, then it will give parameter mismatch.
PHYSICAL VERIFICATION
Electrical Rule Check (ERC):
Electrical Rule Check (ERC) is used to analyze or confirm the electrical connectivity of an IC design
ERC checks are run to identify the following errors in layout.
1. To locate devices connected directly between Power and Ground
2. To locate floating Devices, Substrates and Wells
3. To locate devices which are shorted
4. To locate devices with missing connections
Well Tap connection error: The Well Taps should bias the Wells
Well Tap Density Error: If there is no enough Taps for a given area then this error is flagged Taps need
to be placed regularly which blases the Well to prevent Latch-up
Tools: Mentor Graphics Calibre, Synopsys Hercules, Cadence Assura, Magma Quartz
PHYSICAL VERIFICATION
Onlinelvs: check_lvs
Trclvs: Internally generated from Diagram ,so we need to laod this IC
Validator with respect synopsis after loading IC Validator this report we
need to open ,while popup will happens like : shorts and opens ,device
mismatch.
Difference b/w onlinelvs and Trclvs is
In Trclvs hierarchical shorts are visible
In Onlinelvs hierarchical shorts are not visible
PHYSICAL VERIFICATION
Antenna effect Definition:
During the fabrication of MOS integrated circuits, especially at the time of plasma etching, there will be a chance of collecting
more charges at the gate and causes damage to the gate oxide layer since it is very thin. This condition is known as Antenna
effect.
Antenna Violation : The ratio of the gate area to the gate oxide area is known as Antenna ratio.
Solutions for Antenna Violation:
1 Metal Jumper insertion /metal jogging: Breaks the long wire which is connected gate and route to upper metal layer. So it
becomes short and less capable of collecting charge. If the antenna violation happens at a metal layer, always use higher metal
layers as metal jumper ,since all the lower layers are already fabricated at that moment .
2. Diode insertion: Connect reverse biased diodes near gate input where violation occurs on a net provides a discharge path to
the substrate which saves the gate of the transistor. it can protect the gate oxide
Adding diode increases the area and also the capacitance which leads to increase in delay,
3.IPN( Inter Process Node)
Add vias: near the gate(s), to connect the gate to the highest layer used. This adds more vias, but involves fewer changes to
the rest of the net.
1.INTERVIEW QUESTIONS
1. What is uncertainty values for hold time
2. What is skew values for setup and hold which one is violating
3. Where do you check set up & hold violations in multicycle paths?
4. Hold fixing for reg to out path?
5. How to reduce propagation delay ?
6. What are retention registers?
7. In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps.
Then what is the maximum operating frequency?
8. How R and C values are affecting time?
9. How do u calculate insertion delay.
10. what are effects OCV on insertion delay and skew
11. setup is checked in which clock cycle and hold is checked in which clock cycle
2.INTERVIEW QUESTIONS
why to reduce insertion delay what are its impact
1.
which is better for insertion delay more low drive strength buffers or less high drive strength buffers
2.
Why do we use buffer for fixing violations instead of AND and NAND gates?
3.
What setup analysis and how to fix setup violations ?if you tried all the setup methods, still violations
are there, what you do ?
4.
What is clock pulling and clock pushing?
5.
What is clock budgeting ? How much percentage will you provide to the design?
6.
What is insertion delay ? In your design, insertion delay is more, how do you fix it? Whether it will
effect on the timing
7.
How do you fix timing violations after routing?
8.
How do you fix DRC violations after routing?
9.
Explain multi voltage design?
10. How you worked on multi voltage design?