Usage of Early Clock Flow (ECF) in
Innovus
Product Version 18.1
July, 2018
Copyright Statement
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 2
Usage of Early Clock Flow (ECF) in Innovus
Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Terms .......................................................................................................................... 4
1.
Overview ............................................................................................................ 5
2.
ECF flow steps ................................................................................................... 6
2.1 Preparation......................................................................................................... 6
2.2 Steps inside ECF ............................................................................................... 7
2.3 Results and outputs ......................................................................................... 10
2.3.1 Information about useful skew advancing and delaying ................................ 11
2.3.2 GigaOpt and CCOpt progress and summary information .............................. 12
2.3.3 Pin insertion delays output ............................................................................ 12
3.
Pin insertion delays .......................................................................................... 13
Example..................................................................................................................... 14
Summary ................................................................................................................... 16
Support ...................................................................................................................... 16
Feedback ................................................................................................................... 16
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 3
Usage of Early Clock Flow (ECF) in Innovus
Purpose
In the default Innovus implementation flow, the clock tree cells are not yet inserted
during placement. Therefore, Innovus cannot consider routing congestion caused by the
addition of clock tree cells and the clock gating timing paths are inaccurate. This
application note describes the different steps done by the so-called ECF. Although it is
very design dependent, ECF can be used to get better placement and therefore better
congestion estimation, as well as clock gate enable timing estimation / optimization.
Audience
Since Innovus 18.1, ECF is no longer limited access. This document is intended for
Innovus users who are running into timing problems or routing congestion and want to
use ECF to achieve better timing and/or routability results.
Terms
CTD Clock Tree Debugger
CTS Clock Tree Synthesis
ECF Early Clock Flow
FF
Flip Flop
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 4
Usage of Early Clock Flow (ECF) in Innovus
1. Overview
ECF is inserting a preliminary clock tree during place_opt_design (note: place_design
is not sufficient – it will not launch ECF) using a fast clock tree clustering of CCOpt and
annotates the clock latencies for timing optimization. Figure 1 shows the basic steps
inside place_opt_design. Although it is very design dependent, building a clock tree
during place_opt_design normally results in a better placement and congestion
estimation. ECF includes clock gating timing path estimation as well. This can result in
better timing, because pre-CTS optimization has more timing impact than post-CTS and
ccopt_design has a better starting point. ECF uses CCOpt useful skew technologies,
doing late as well as early skewing.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 5
Usage of Early Clock Flow (ECF) in Innovus
2. ECF flow steps
This section describes the different steps inside ECF.
2.1 Preparation
Since Innovus 18.1, ECF is no longer a limited access feature. ECF is invoking fast
CCOpt CTS clustering during place_opt_design. Therefore, the CTS setup must be
done before invoking place_opt_design. At the end of this application note is a basic
script file example running ECF. You enable ECF with:
setDesignMode -earlyClockFlow true # default is false
As shown in Table 1, useful skew is turned on during place_opt_design by default. You
can turn off useful skew during place_opt_design by using one of the following
variables:
setOptMode -usefulSkewPreCTS false # default is true
setOptMode -usefulSkew false
# default is true, master switch for useful
skew
When ECF is turned on (default set to false) and useful skew is turned off (default set to
true), you will get early clock buffering and better congestion estimation caused by CTS
without useful skewing.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 6
Usage of Early Clock Flow (ECF) in Innovus
2.2 Steps inside ECF
See Figure 2 for steps inside place_opt_design using ECF. For detailed information,
refer to the Innovus .log files and the corresponding documentation (for example,
InnovusUG.pdf > Clock Tree Synthesis).
place_opt_design starts with extracting the clock tree specification. You create a clock
tree specification with create_ccopt_clock_tree_spec or by sourcing an appropriate
specification file. If there is no clock specification in the memory, Innovus will create it
on the fly and delete it at the end of place_opt_design. This can be seen in the log file at
the beginning of the place_opt_design_step:
…
Begin: Create ccopt clock spec
Creating clock tree spec for modes (timing configs): f_mode test_cmode
…
And at the end of place_opt_design:
…
CCOpt: Deleting clock spec ...
…
Whereas if the clock tree specification file already exists in the memory, you will see it
as well in the log file at the beginning of place_opt_design:
…
CCOpt: Pre-existing ccopt clock spec ...
…
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 7
Usage of Early Clock Flow (ECF) in Innovus
After extracting the clock tree specification, there is a global placement step followed by
an initial timing summary:
-----------------------------------------------------------Initial Summary
-----------------------------------------------------------Setup views included:
func_max_view test_max_view
+--------------------+---------+
|
Setup mode
|
all
|
+--------------------+---------+
|
WNS (ns):| -2.251 |
|
TNS (ns):|-223.050 |
|
Violating Paths:|
289
|
|
All Paths:| 4307
|
+--------------------+---------+
Then, the preliminary clock tree is built. At the end of the clustering, several useful
reports are written into the log file. Look for DAG (Directed Acyclic Graph) to find it in
the log file. This information includes number and type of buffers and inverters used for
the clock tree, clock tree wire lengths for top, trunk and leaf nets, clock net violations,
skew group summary together with its minimal, maximal insertion delay, skew, skew
targets, … Similar information is written into the log file during CTS (ccopt_design).
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 8
Usage of Early Clock Flow (ECF) in Innovus
Clock DAG stats at the end of CTS:
==============================
-------------------------------------------------------------Cell type
Count
Area
Capacitance
-------------------------------------------------------------Buffers
88
3768.218
1.351
Inverters
0
0.000
0.000
…
Clock DAG library cell distribution at end of CTS:
==================================================
-------------------------------------------Name
Type
Inst
Inst Area
Count
(um^2)
-------------------------------------------Clkbufx12
buffer
67
3361.792
Clkbufxx8
buffer
1
40.141
…
Skew group summary at end of CTS:
=================================
---------------------------------------------------------------------Half-corner
Skew Group
Min ID Max ID Skew Skew target …
---------------------------------------------------------------------Setup_max:setup.late clk_f/f_mode 0.864
1.588
0.724
0.432*
…
…
Slew violation summary across all clock trees - Top 10 violating pins:
======================================================================
Target and measured clock slews (in ns):
--------------------------------------------------------------------------------------------Half corner
Violation Slew
Slew
Dont
Ideal Target
Pin
amount
target achieved touch net?
source
net?
--------------------------------------------------------------------------------------------Setup_max:setup.late
0.000
0.300
0.300
N
N
auto extracted /test_des/FF3/CK
…
After building the initial clock tree, several iterations between incremental placement,
timing optimization, useful skewing (if useful skew is set to true; see table 1), congestion
repair, power optimization, … will follow. Inside optimization, there are several useful
skew passes. These passes start in the log file with the following:
CCOptDebug: Before useful skew*: reg2cgate* WNS -1.696ns TNS -4.003ns;
and ending with the following:
CCOptDebug: After useful skew*: reg2cgate* WNS -1.376ns TNS -3.683ns;
At the end of place_opt_design is a summary table about the progress of these different
useful skew passes (see an example in section 2.3.2, GigaOpt and CCOpt progress
and summary information). After place_opt_design, ccopt_design will follow as the next
major step inside the Innovus implementation flow.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 9
Usage of Early Clock Flow (ECF) in Innovus
2.3 Results and outputs
With ECF, a preliminary clock tree is created during place_opt_design using CCOpt
clustering. Therefore, information about the clock tree such as CTS cell usage, counts
and area, CTS slew violations … can be found in the log file. Similar information is
written into the log file during ccopt_design. As in a non-ECF flow, the progress of
timing closure is also written into the log file. Additional useful information using ECF is
in the log file at the end of place_opt_design. This includes statistical information about
useful skew advancing and delaying, the timing progress of place_opt_design and a
dump of the applied pin insertion delays. The additional information about useful skew
(sections 2.3.1 – 2.3.3) is only written into the log file if you have turned on useful skew
during place_opt_design (see Table 1).
Clock gate latencies are updated irrespective of whether you are using the ECF flow
with or without useful skew. Latency updated SDC are written into the
<design_database>/mmmc/views/<view>/latency.sdc file. These latencies are
translated into pin insertion delays (see the Pin insertion delays section) when read into
Innovus. Following is an example of such a SDC update:
set_clock_latency -clock_gate -0.47 [get_pins {test/clk_u/CK}] -clock [get_clocks {clk_r}]
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 10
Usage of Early Clock Flow (ECF) in Innovus
2.3.1 Information about useful skew advancing and delaying
The following information about useful skew advancing and delaying can be found in the
log file at the end of place_opt_design. The equivalent Innovus command to get useful
skew advancing and delaying statistics is report_ccopt_pin_insertion_delays.
Useful skew: advancing
======================
Found 31 advances (1.085% of 2679 clock tree sinks)
----------------------------From (ns)
To (ns)
Count
----------------------------0.000
0.090
12
0.090
0.180
11
…
1.620
1.710
0
1.710
1.800
1
----------------------------Total
Mean
Std.Dev
: 7.876ns
: 0.272ns
: 0.416ns
Smallest advance : 0.003ns at test_design/FF1/CK
Largest advance : 1.765ns at test_design/FF35/CK
Useful skew: delaying
=====================
Found 41 delays (1.235% of 2679 clock tree sinks)
----------------------------From (ns)
To (ns)
Count
-----------------------------0.170
-0.160
9
-0.160
-0.150
11
….
-0.030
-0.020
0
-0.020
-0.010
1
----------------------------Total
Mean
Std.Dev
: -4.157ns
: -0.126ns
: 0.049ns
Smallest delay : -0.013ns at
Largest delay : -0.163ns at
test_design/FF95CK
test_design/FF63CK
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 11
Usage of Early Clock Flow (ECF) in Innovus
2.3.2 GigaOpt and CCOpt progress and summary information
The following information about the timing progress is written into the log file after
place_opt_design when ECF is used together with useful skew:
2.3.3 Pin insertion delays output
Pin insertion delays as a result of ECF and useful skew are also written to the log file:
Begin: Dump ccopt insertion delays
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> 1.76493
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> 0.310455
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> -0.0327267
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> -0.0454266
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> -0.042
...
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> 0.0103148
set_ccopt_property insertion_delay -delay_corner max -late -rise -pin <pin-name> 0.08515
End: Dump ccopt insertion delays
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 12
Usage of Early Clock Flow (ECF) in Innovus
3. Pin insertion delays
Pin insertion delays are used to forward latencies to CTS (ccopt_design). Therefore, do
not use reset_cts_config or reset_ccopt_config before running ccopt_design. These
commands will delete pin insertion delays. Skew measurements of CTS includes the pin
insertion delay. Pin insertion delays are also displayed in the clock tree debugger
window after place_opt_design or ccopt_design. Figure 5 at the end of this application
note shows an example.
Be aware of the different prefixes of the SDC command versus the insertion_delay
command inside Innovus.
In SDC, a negative offset means the sink is advanced – for CTS it is a positive offset as
shown in Figure 3.
SDC:
In Innovus:
set_clock_latency -0.25 [get_pins {m0/ck}]
set_ccopt_property insertion_delay -pin m0/ck 0.25
A positive offset in SDC means the sink is delayed – for CTS it is a negative offset.
SDC:
In Innovus:
set_clock_latency 0.3 [get_pins {f2/CK}]
set_ccopt_property insertion_delay -pin f2/CK -0.3
Using ECF, there is a preliminary clock tree (using CCOpt clustering algorithm) after
running place_opt_design. These clock tree cells will get removed at the invocation of
ccopt_design. Inside ccopt_design, the clock tree will be recreated using CCOpt
clustering, balancing and skewing algorithms.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 13
Usage of Early Clock Flow (ECF) in Innovus
Example
In this section, the results of a small design with clock gating timing problems are
described. For this design, the following basic script file was used. There have been two
runs – one with ECF (and useful skew) and the other without ECF. Routability was not a
problem for both runs. Using this design, ECF helped to fix clock gating violations – but
this is of course very design dependent.
# very basic script file for running ECF
setMultiCpuUsage -localCpu 4
#
restoreDesign testDesign.enc
#
# early clock flow till 17.x is limited access
# setLimitedAccessFeature innovusEarlyClockFlow 1
setDesignMode -earlyClockFlow true
#
set clock_buffer_cells {clkbufx2 clkbufx4 clkbufx8 clkbufx12 clkbuf16}
set clock_inverter_cells {clkinvx2 clkinvx4 clkinvx8 clkinvx12 clkinvx16}
set icgCells {clkicg1 clkicg2 clkicg4 clkicg6 clkicg8 clkicg12 clkicg16}
#
create_ccopt_clock_tree_spec
set_ccopt_property buffer_cells $clock_buffer_cells
set_ccopt_property inverter_cells $clock_inverter_cells
set_ccopt_property clock_gating_cells $icgCells
# additional ccopt settings like
#
create_route_type ...
# should be made here
place_opt_design
#
ccopt_design
#
The timing after ccopt_design without ECF (setDesignMode -earlyClockFlow false)
shows timing violations:
-----------------------------------------------------------optDesign Final Summary
-----------------------------------------------------------Setup views included:
func_max_view
+--------------------+---------+---------+---------+---------+
|
Setup mode
|
all
| reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|
WNS (ns):| -0.710 | -0.369 | -0.710 | 4.940 |
|
TNS (ns):| -7.589 | -6.646 | -0.943 | 0.000 |
|
Violating Paths:|
51
|
47
|
4
|
0
|
|
All Paths:| 2781
| 2708
|
73
|
175
|
+--------------------+---------+---------+---------+---------+
Total CPU time:
0:14:27
Peak memory (main): 1791.05MB
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 14
Usage of Early Clock Flow (ECF) in Innovus
Using ECF results in significantly better timing. As already mentioned, this is very
design dependent!
-----------------------------------------------------------optDesign Final Summary
-----------------------------------------------------------Setup views included:
func_max_view
+--------------------+---------+---------+---------+---------+
|
Setup mode
|
all
| reg2reg |reg2cgate| default |
+--------------------+---------+---------+---------+---------+
|
WNS (ns):| 0.011 | 0.011 | 0.046 | 5.941 |
|
TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 |
|
Violating Paths:|
0
|
0
|
0
|
0
|
|
All Paths:| 2781
| 2708
|
73
|
175
|
+--------------------+---------+---------+---------+---------+
Total CPU time:
0:14:42
Peak memory (main): 1819.89MB
The runtime of flows is in the same range, because the time you spent for ECF during
place_opt_design will be saved during timing optimization (ccopt_design).
The clock tree debugger (CTD) after place_opt_design displays the preliminary
implemented clock tree (see Figure 4).
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 15
Usage of Early Clock Flow (ECF) in Innovus
Pin insertion delays are displayed as vertical dotted lines. The insertion delays are
visible after place_opt_design (see Figure 5) or ccopt_design.
Summary
This application note described how to use ECF inside Innovus. The document
explained the setup of ECF, its steps preformed inside place_opt_design, its results and
outputs, and how the results of ECF are forwarded to ccopt_design.
Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2018 Cadence Design Systems, Inc. All rights reserved worldwide.
Page 16