Project
RISC-V
Physical Design
Submitted by:
Gowtham Yechuri
(PD - 04)
Under the esteemed guidance of
Mr.MaheeshaNB
Technical Trainer
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TABLE OF CONTENTS
S.No
Title
Page No.
1
RISC-V
3
2
Design Compiler
7
3
ICC-II Compile Flow
14
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CHAPTER 1
RISC-V
Objectives:
 To understand how to come up with various file like .tcl,
.sdc, .vew, .def, .tech, .v, .vcs, and various reference libraries
required for the physical design process and how to source those
files.
 To understand how to do the process of synthesis, dft, floorplan,
powerplan, placement, clock tree synthesis, routing and signoff.
 To understand how to correlate all the above process and how to
handle the errors occuring during the physical design.
What is RISC-V?
RISC-V stands for reduced instruction set computer (RISC) five.
The number five refers to the number of generations of RISC
architecture that were developed at the University of California,
Berkeley since 1981.
RISC-V is an open-source instruction set architecture (ISA) used
for the development of custom processors targeting a variety of end
applications.
Unlike proprietary processor architectures, RISC-V is an open-source
instruction set architecture (ISA) used for the development of custom
processors targeting a variety of end applications. Originally developed
at the University of California, Berkeley, the RISC-V ISA is considered
the fifth generation of processors built on the concept of the reduced
instruction set computer (RISC). Due to its openness and its technical
merits, it has become very popular in recent years. The standard is now
managed by RISC-V International, which has more than 3,000
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members and which reported that more than 10 billion chips containing
RISC-V cores had shipped by the end of 2022. Many implementations
of RISC-V are available, both as open-source cores and as commercial
IP products.
How does RISC-V work?
As an open-standard architecture, RISC-V is defined by member
companies of RISC-V International, the global nonprofit organization
behind the ISA. The intent is that through collaboration, the member
companies can contribute new avenues of processor innovation while
promoting new degrees of design freedom.
The royalty-free RISC-V ISA features a small core set of instructions
upon which all the design’s software runs. Its optional extensions allow
designers to tailor the architecture for a variety of different end markets.
Essentially, the RISC-V architecture allows designers to customize and
build their processor in a way that’s tailored to their target end
applications, so they can optimize the power, performance, and area
(PPA) for those applications. The RISC-V ISA also provides the
flexibility to pick and choose from available features, rather thanhaving
to use the full feature set.
While the initial market adoption of RISC-V has been with embedded
applications and microcontrollers, the open-source architecture also
holds promise for high-performance computing and data centers.
The history of RISC-V
RISC-V began as a project at UC Berkeley to create an open-source
computer system based on RISC principles. It was initially designed
for academic use. The standard has evolved and is now managed by
RISC-V International.
The RISC-V International organization has moved its headquarters to
Switzerland to maintain neutrality for designers worldwide without any
government regulations.
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The ecosystem is emerging and growing to support the standard. As the
adoption rate accelerates, industry collaboration continues, further
evolving the architecture.
What are the benefits of RISC-V?
RISC-V has gained popularity because the architecture provides
simplified instructions to the processor to accomplish various tasks. It
also enables designers to create thousands of potential custom
processors, facilitating faster time to market. The commonality of the
processor IP also saves on software development time. Other benefits
of RISC-V include:
Its open-standard nature, which allows collaboration and
innovation across the industry
 Common ISA, which helps make software development easier
since all processors could potentially use the same architecture.
Designers can use the same base ISA, from simple embedded
devices to the largest supercomputers, tailoring their device to the
needs of the market. Compared to previous ISAs, RISC-V ISAs
have unique features and can be customized based on their
requirements.
 Availability of smaller, energy-efficient, and modular options
 Security features, which are available through open-source
reference designs, software composition analysis tools, and
security extensions. In addition, its open-source nature means that the
entire RISC-V architecture can be scrutinized closely in the
public domain, eliminating back doors and hidden channels.

What are key RISC-V applications?
The application options are endless for the RISC-V ISA:
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 Wearables,
Industrial, IoT, and Home Appliances. RISC-V
processors are ideal for meeting the power requirements of spaceconstrained and battery-operated designs.
 Smartphones. RISC-V cores can be customized to handle the
performance needed to power smartphones, or can be used as part
of a larger SoC to handle specific tasks for phone operation.
 Automotive, High-Performance Computing (HPC), and Data
Centers. RISC-V cores can handle complex computational tasks
with customized ISAs, while RISC-V extensions enable
development of simple, secure, and flexible cores for greater
energy efficiency.
 Aerospace and Government. RISC-V offers high reliability and
security for these use applications.
Who's using RISC-V?
The industry is seeing a large amount of interest in this processor IP.
RISC-V IP is expected to grow at a compounded annual growth rate of
35% projected through 2027. There are three main market segments
interested in the RISC-V architecture:
 IP providers who can offer their own designs
 SoC teams using commercial IP
 Designers building custom, RISC-V processor-based SoCs
RISC-V Design and Verification Challenges
RISC-V presents special challenges because its specification is
designed to provide a configurable and customizable solution for
general-purpose processors. There are many options and variations
defined in the ISA specification, and users are permitted to extend the
ISA even further by adding custom instructions. Therefore, any RISCV verification solution must be flexible enough to accommodate
customizations.
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CHAPTER 2
DESIGN COMPILER
Basically, Design Compiler optimizes a design to provide
miniaturized and fastest representation of logical function. It also
provides topographical technology, which allows us to predict
accurate post- layout, timing, area and power during RTL. synthesis.
We know that Design compiler is a Graphical tool which helps us in
finding a multicore-multimode designs and allows us to create and
modify floorplan I came across that it also reduces routing congestion
and it improves area similarities. Usually we came across logic
synthesis which is the process of converting Verilog to gate-level
netlist which is mapped to a specific logic library and we check
whether the synthesized design meets required functionality timing,
power, and area requirements.
Design Flow
Basically, design flow consists of three steps i.e.
 Synthesis
 Optimization
 Compile
Synthesis
As we know in this stage it generates a gate-level netlist from a RTL
and design is created. Synthesis is a process where different inputs are
required to carry out the design.
 Technology Files (tf)
 Reference libraries(ref.lib)(.DB'S)
 RTL(Verilog code)
 Design constraints(.sdc)
 Floorplan constraint
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 TLU-plus files(parasitic files)
 DFT inputs
Optimization
Followed by synthesis we have optimization in this step we implement
a combination of library cells and we have to check whether we
obtained required function, area and power
Compile
Compile is the Design Compiler process that executes the synthesis and
optimization steps. After you read in the design and perform other
necessary tasks, you run the "compile_ultra or compile" command to
generate a gate-level netlist for the design.
The following are the output which are generated after synthesis
 Area
 Power
 Timing
 Design details
 Netlist
 Design constraints file
 Parasitic extraction
 SDF file (Standard delay format)
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Command Flow:
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Power:
 Using Design compiler we can automatically minimizes power
consumption at the RTL and gate level, and enables concurrent
timing,area,power and test optimizations within the Design
Compiler
 The command used to get power report is report_power.
Timing:
 In Timing we can consider the following types of paths for timing
analysis: Clock path, a path from a clock input port or cell pin,
through one or more buffers or inverters, to the clock pin of a
sequential element; for data setup and hold checks. Clock-gating
path.
 The command used to get timing report is report_timing.
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Congestion:
 If the number of required routing resources are more than the
number of available routing tracks, then the area becomes
congested. High congestion causes detours and leads to worse
results. Congestion makes the design non-routable that means
routing will not be converged if there are congestion in the design.
 The command used to get congestion report is report_congestion.
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Report_qor:
 The command used to get quality of report summary
is report_qor.
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Schematic View Generated by Design Compiler:
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CHAPTER 3
ICC-II COMPILE FLOW
ICC II Compiler is a complete netlist-GDS implementation, which,
includes innovative for flat and hierarchical design planning, early
design exploration, Congestion aware placement and optimization,
clock tree synthesis, advanced node routing convergence,
manufacturing compliance and signoff closure.
We have some set of inputs which we have to provide for ICC II tool
such as
 Technology files(tf) & Netlist
 NDM library's
 TLU-plus files
 Design constraints file from DC
ICC II tool is basically a PNR (Power and Routing) tool which can
process some particular steps as follows.
 Floor Planning
 Placement
 Clock Tree Synthesis
 Routing
Step 1: First step in ICC II compiler is creating a library, we can create
a library by using the same library file and Technological files. To
create a library, Create_lib command is used where in which it is
supported with all the technology files and library name.
Step 2: In this step ICC II reads a library in the form of NDM's i.e.,
Reading RTL and the reading SDC which is generated from Design
compiler.
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Step 3: This step involves floor planning which in turn involves
determining the locations, shape, size of modules in a chip and we can
get a rough estimation of the chip area, delay and the wiring congestion
thereby providing a ground work for layout.
Step 4: In this step a default parasitic model is created with targeting
of TLU +files and its related map files & all the related scenarios
targeting to different PVTs should be created.
Step 5: Placement Creation
Step 6: Clock Tree Synthesis
Clock Tree Synthesis is a technique for distributing the clock equally
among all sequential parts. The purpose of Clock tree Synthesis is
provided the placement data as well as the clock tree limitations as
input
A signal with constant rise and fall with ideally equal width (50% rise
and 50% fall of the signal width) helps to control data propagation
through the clock elements like Flip-Flop, Latches etc. The clock
source mostly present in top-level design and from there propagation.
PLL Oscillator like constant sources are being used normally in designs
to get the clock.
Inputs of CTS:
 Placement DB
 CTS Spec File
Placement DB:
Placement DB contains Placement completed Netlist, DEF, LIB, LEF,
SDC, UPF and other information which contain all the files from the
placement database. This can be a zipped file. This DB is also known
as PLACE EXIT db. Which means we are not going to do any standard
cell placement and related things here onward.
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CTS Spec File:
CTS spec file contains the below information:
 Inverters or buffers to be defined which will be used to balance
the clock tree.
 CTS Exceptions (End points of clock tree).
 Skew group information.
 Contains target Skew, max target transition and other timing
constraints as per clock tree.
 Top layer and bottom layer route info. VIA's information which
will be used during clock route.
 Clock related info (Generated clocks (Eg. Clock divider, Clock
multiplier etc)).
 NDR Rule definition.
Step 7: Routing
Routing is the process of path selection in any network. A computer
network is made of many machines, called nodes, and paths or links
that connect those nodes. Communication between two nodes in an
interconnected network can take place through many different paths.
There are three types of Routing:
 Static Routing.
 Default Routing.
 Dynamic Routing.
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Command Flow:
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Final Routed Design:
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Timing:
 In Timing we can consider the following types of paths for timing
analysis: Clock path, a path from a clock input port or cell pin,
through one or more buffers or inverters, to the clock pin of a
sequential element; for data setup and hold checks. Clock-gating
path.
 The command used to get timing report is report_timing.
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Power:
The command used to get power report is report_power.
Congestion:
 If the number of required routing resources are more than the
number of available routing tracks, then the area becomes congested.
High congestion causes detours and leads to worse results. Congestion
makes the design non-routable that means routing will not be converged
if there are congestion in the design.
 The command used to get congestion report is report_congestion.
Report_qor:
 The command used to get quality of report summary
is report_qor.
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Check_LVS:
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Check_routes:
Report_utilization:
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