North South University
Department of Electrical & Computer Engineering
Course Code: EEE211L
Course Title: Digital Logic Design Lab
Faculty: Meem Tasfia Zaman
Project Report of “Design a Digital Logic Circuit
(Combinational and Sequential) to display“FE21L-03
” in a Seven Segment Display
Date of Submission: 06/11/2023
Section: 02
Group Number: 06
Submitted To: MD. AL – AMIN BHUIYAN
Submitted By
S.N.
Student Name
ID
16
Md. Asiful Islam
2112281643
27
Md. Abrar Masud
2221449043
28
Huraira Islam Mahin
2221680043
31
Towhidul Islam Sunto
2223032643
Abstract:
This project aimed to design a digital logic circuit, comprising both combinational and
sequential logic, to display the alphanumeric string "FE21L-03" on a 7-segment display using
only NAND gates. The report outlines the design methodology, circuit implementation, and
testing results.
Purpose: The purpose of the project is to learn how circuit building works. Since we can see
that there are a lot of gates and combination we can use to build a circuit, it becomes
difficult what we will take or choose. Which method is easier and when we pick to build. So,
the purpose we can say that is to learn how circuit building works and efficient way to build a
circuit which prints FE21L-03
Methodology:
In this project we used NAND gate. Since our purpose is to learn the building works and
efficient way to build circuit we chose to use NAND IC to build. Although it takes more than
10 NAND gates, but it is simple and easy to implement. Also we used JK- Flip Flop for the
countdown which is important in this implementation.
Results:
The one equations for the 7 segment display was wrong somewhere, but after that we able to
solve the wrong things and able to printout the letters(FE21L-03) in the 7 segment display. We
used 9v battery and NAND(7400) gate to cover the whole operation also we added JK Flip
Flops for A, B and C then finally we able to implement the circuit correctly.
Conclusion:
conclusion the project target we set to achieve the work successfully. We were successfully
implemented the circuit in a easiest and correct way. So we thought that or assume that our
circuit is completely and correctly working.
Background: In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an
output which is false only if all its inputs are true; thus, its output is complement to that of
an AND gate. A LOW (0) output results only if all the inputs to the gate are HIGH (1); if any
input is LOW (0), a HIGH (1) output results . 7400 IC (NAND Gates): 4 gates on this package,
each with 2 input pins, 1 output pin. The output pin is low only when all input pins are high
at the same time.
The seven elements of the display can be lit in different combinations to represent each of
the Arabic numerals. The individual segments are referred to by the letters "a" to "g", With
its the display can show numbers from 0 to 9. Additionally, they can also display upper case
letters A, C, E, F and lower case letters b and d.
A flip flop in digital electronics is a circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. There are basically 4
types of flip-flops in digital electronics:
1. SR Flip-Flop
2. JK Flip-Flop
3. D Flip-Flop
4. T Flip-Flop
Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics.
The JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.
JK Flip Flop Circuit
The input condition of J=K=1 gives an output inverting the output state. However, the
outputs are the same when one tests the circuit practically.In simple words, If J and K data
input are different (i.e. high and low), then the output Q takes the value of J at the next clock
edge. If J and K are both low, then no change occurs. If J and K are both high at the clock
edge, then the output will toggle from one state to the other. JK Flip-Flops can function as
Set or Reset Flip-flops.
JK FF Truth Table:
J
K
Q
Q’
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
Project Work Plan:
Combinational
0
1
2
3
4
5
6
7
ABC
a
b
c
d
e
f
g
000
001
010
011
100
101
110
111
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
1
0
0
1
0
1
K-MAP
For a ,
1
1
1
1
1
F=A’B’+AB+BC’
=((A’B’)’(AB)’(BC’))’
For b ,
1
1
1
1
F=B
For c,
1
1
1
F=BC+AB
=((BC)’+(AB)’)’
=((BC)’(AB)’)’
For d,
1
1
1
1
1
F
E
2
I
L
0
3
F=A’B’C+AC’+AB+BC’
=((A’B’C+AC’+AB+BC’)’)’
=((A’B’C)’(AC’)’(AB)’(BC’)’)’
For e,
1
1
1
1
1
F=C’+A’B’
=((C’+A’B’)’)’
=(C(A’B’)’)’
For f,
1
1
1
1
F=AC’+A’B’
=((AC’+A’B’)’)’
=((AC’)’(A’B’)’)’
For g ,
1
1
1
1
1
F=AC+A’B’+A’C’
=((AC+A’B’+A’C’)’)’
=((AC)’(A’B’)’(A’C’)’)’
Equation minimization
a = (A’B’)’(AB)’(BC’)’
b=B
c = (AB)’(BC)’
d = (A’B’C)(AB)(AC’)(BC’)
e= (A’B’)’
f = (A’B’)’(AC’)’
Sequential
Using JK flip flop;
Given combination,
g = (A’B’)’(AC) C’
000->111->110->101->100->011->010->001->000
Present
State
ABC
000
001
010
011
100
101
110
111
Next
State
A*B*C*
111
000
001
010
011
100
101
110
For JA ,
1
0
0
0
x
x
x
x
For KA,
x
x
x
x
1
0
0
0
For JB ,
1
0
x
x
1
0
x
x
For KB,
x
x
0
1
x
x
0
1
For JC ,
1
x
x
1
1
x
x
1
JA= B’C’
KB= B’C’
JB=c’
KB= C’
JA
1
0
0
0
x
x
x
x
KA
x
x
x
x
1
0
0
0
JB
1
0
x
x
1
0
x
x
KB
x
x
1
0
x
x
1
0
Jc
1
x
1
x
1
x
1
x
KC
x
1
x
1
x
1
x
1
JC= 1
For KC,
x
1
1
x
x
1
1
x
Kc= 1
Timer part
We're going to build a 555 timer circuit .To build this project we will need a 555 timer, a
100uF electrolytic capacitor, two 5.1 kilo ohm resistors, and a 220 ohm resistor. The first
thing we want to do is bridge both busses. This way power and ground will be available on
both sides of the breadboard. Then we'll add the 555 timer IC. Now we'll connect the reset
pin to the voltage input pin. This enables the 555 timer. ground this pin to reset the timer.
Next we're going to connect the trigger pin to the threshold pin. Then we connect the power
supply pin to the supply rail of the breadboard, and the ground pin to the ground rail of the
breadboard Now we need to connect a capacitor to the trigger pin of the 555 timer. We're
going to use a 100uF electrolytic capacitor. And then we need to ground the capacitor. Next,
we're going to connect a 5.1K Ohm resistor to the discharge pin, and connect the other lead
of the resistor to the supply rail of the breadboard. Then we need to connect the threshold
and discharge pins with another 5. 1K Ohm resistor. Lastly we need to add the timer with the
circuit . We'll add the 555's output pin to the clock part
Human Resource:
Md. Asiful Islam (2112281643)Helped with the NAND (main & minimized) circuit diagram
and built the whole circuit practically including combinational, sequential and timer part.
Md. Abrar Masud (2221449043) Tables , kmaps and equations of combinational and
sequential part. Simulating combinational and sequential circuit in Logisim .Background and
timer part .Report writing .
Huraira Islam Mahin (2221680043) Simulation, minimize equation, Collect data, Collect the
equipment’s, Helped to build sequential circuit and conclusion of the sequential part.
Towhidul IslamSunto(2223032643)- Simulating of combinational and sequential circuits also
design of sequential circuit and helped to build sequential circuits practically and Abstracts
Purpose, Methodology, Results, conclusion.
Proposed Budget:
Product Name
QTY
Price
1
7400 NAND GATE
10
250
2
MB102 BREADBOARD(LARGE)
2
318
3
Jumper Wires (M to M) 20 Pieces
2
113.8
3
82.77
3
83.01
1
155
2
66
1
26.59
IC 7404
4
Hex Iinverter (Not gate)
IC 7410
5
Triple 3-Input NAND Gate
Breadboard (Big)
6
Breadboard 840 Tie Points
IC 4027
7
Dual jk Flip-Flops
IC 7408
8
Quad 2-inpul AND Gates
Conclusion:
Provide brief overview of the 7-segment display technology, its applications, and NAND gates
as essential components of digital logic circuit. Explain the binary representations of
characters and digits in the alphanumeric string "FE21L-03" for the 7-segment display. The
truth table that maps the input values (binary representations) to the 7-segment display
outputs. Combinational logic circuit was designed using only NAND gates based on the truth
table. Include relevant equations and diagrams. Sequential Logic Design is also used