MIPS CPU
Instruction level parallelism
Based Verilog code
Write Back
• (Not all instructions require this stage)
Writes the results of the computation back
into a register.
Sub-Block : forwarding, PipelineStall
• forwarding-If a subsequent instruction needs a
value that a previous instruction is currently
calculating => Delivers the data at the moment
the actual value of the data is determined.
• PipelineStall-Pauses the instruction at a
certain stage until the necessary conditions are
met (e.g., waiting for data to be written back).
• Sub-Block which isn’t involved in 5 Stages :
flush_control-Using to remove any instructions
that were wrongly fetched based on the
incorrect prediction.
Forwarding:
Part of the hazard resolution in a pipelined CPU
Input: regwrite_s4, regwrite_s5 (which indicate whether a register write will occur in stages 4 and 5 of the pipeline)
Input: wrreg_s4, wrreg_s5 (5-bit input signals for each of the stages 4 and 5 )
rs_s3, rt_s3 (for the source operands)
outputs: forward_a, forward_b (will dictate the forwarding action for two data inputs to the ALU (data1 and data2))
Forward_a
Forward_b
s: stage
1. Use to determines the value of forward_a, which is used for the first ALU operand.
Initially, it sets forward_a to 0, meaning no forwarding is necessary.
(a) If condition one match which is
(If regwrite_s4 is true/1 and the register written in stage 4 (wrreg_s4) is the same as the source register needed
in stage 3 (rs_s3), then forward_a is set to 1),
indicating that the ALU should use the value from stage 4.
(b) If the above condition isn't met
(but regwrite_s5 is true and wrreg_s5 matches rs_s3)
then forward_a is set to 2, which means the value from stage 5 should be forwarded to the ALU.
2. Similarly for forward_b stage
forwarding - if the upcoming ALU operations in the pipeline can be fed with data from later stages (stage 4 or stage 5)
instead of the default data path. This is to avoid stalling the pipeline for data hazards where a subsequent instruction
needs data that a previous instruction is about to write to a register.
The outputs forward_a and forward_b are control signals that tell the pipeline how to route the data to the ALU for each
operand, ensuring correct operation without needless delays.
forwarding testbench / simulation
in : regwrite_s4, regwrite_s5,
wrreg_s4, wrreg_s5,
rs_s3, rt_s3
out : forward_a, forward_b
=> connect to alu-input1, input2
No Valid data in stage 4&5
Valid data in stage 4
Reg addr being written to in stage 4 & 5
Source reg addr being read in stage 3 pipeline
Forward or not if forward then which stage
Valid data in stage 5
PipelineStall :
to handle stall conditions in a pipeline (stalling the pipeline under certain conditions)
Input : memread_s3 (indicating whether a memory read operation is occurring in stage 3)
rt, rs (source registers in the instruction being processed)
rt_s3 (register target in stage 3 of the pipeline)
output: stall_s1_s2 indicates whether a stall should be inserted between stages 1 and 2 of the pipeline
Condition for performing stall or not
PipelineStall testbench / simulation
in : memread_s3, rt, rt_s3, rs
out : stall_s1_s2
=> connect to program_counter
Mem read operation occur
but neither rt nor rs matched
with stage 3 register
No stall due to unmatched condition
Stall due to mem read operation occur and
either rt or rs matched with rt_s3
Note: pipeline stall is connected to the program counter to prevent the PC from fetching new instructions during stall conditions, ensuring instructions are executed in the correct order and with the correct data. This connection maintains execution integrity and avoids data hazards by synchronizing the instruction flow with the
pipeline's readiness to process new data
flush_control
•
managing the pipeline during branch and jump operations
In pipelined CPU architectures, instructions are processed in stages through a pipeline. This efficient design can execute multiple instructions simultaneously, with each instruction at a
different processing stage. However, when the execution flow changes unexpectedly due to branches or jumps, instructions that have entered the pipeline but are no longer needed or
correct must be removed or "flushed" from the pipeline. This prevents them from completing, ensuring only the correct instructions execute.
•
Input :
pcsrc - indicates a branch condition that requires the PC to source its next value
from somewhere other than its typical sequence
jump_s4: This signal indicates a jump operation is occurring at stage 4 of the
pipeline, requiring a change in the instruction flow
•
Output : flush_s1, flush_s2, flush_s3: These are control signals to flush
If either pcsrc or jump_s4 is true (1'b1), indicating a branch or jump instruction requires altering the flow of execution
flush_control testbench / simulation
in : pcsrc, jump_s4
out : flush_s1, flush_s2, flush_s3
=> connect to regr(pipeline register)
No branch condition thus follow typical sequence
c
No branch condition thus follow typical sequence
Therefore, no flush required in all the stage
Configurable power
from usb or external sources
Ethernet
Hdmi
Micro sd
card slot
Bypass header if we need
to use own jtag programmer
On board Programming
Headphone
Microphone
Line in
USB on-the-go
6 buttons 2 reset buttons
4 LEDs
4 switches
1 RGB led