Unit 4
• 8086 Bus Configuration and Timings
• Physical memory Organization, General Bus operation cycle, I/O addressing
capability, Special processor activities, Minimum mode 8086 system and Timing
diagrams, Maximum Mode 8086 system and Timing diagrams.
• Basic Peripherals and their Interfacing with 8086 :Static RAM Interfacing with
8086 , Interfacing I/O ports, PIO 8255, Modes of operation – Mode-0 and BSR
Mode, Interfacing simple switches and simple LEDs using 8255.
Signal Description of 8086
• 8086, a 16 bit CPU is available in three clock rates, ie. 5, 8 and 10MHz,
packaged in a 40 pin plastic package
• 8086 operates in single processor or multiprocessor configurations to
achieve high performance
• Some of the pins serve a particular function in minimum mode (single
processor mode) and others function in maximum mode
(multiprocessor mode) configuration
• The 8086 signals are categorized into 3 groups
• The first are the signals having common functions in minimum as well
as maximum mode, the second are the signals which have special
functions for minimum mode and the third are the signals having
special functions for maximum mode
Pin configuration of 8086
Address/data bus
• AD15-AD0- These are time multiplexed memory, I/O address and data lines
• Address remains on the lines during T1 state, while the data is available on
the data bus during T2,T3, Tw and T4. Here T1, T2, T3, T4 and Tw are the
clock states of a machine cycle. Tw is a wait state.
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
39
8086
AD15
A19/S6,A18/S5,A17/S4,A16/S3
These are the time multiplexed address and status lines.
•During T1, these are the most significant address lines for memory
operations.
•During I/O operations, these lines are low.
• During memory or I/O operations, status information is available on
those lines for T2,T3,Tw and T4.
•S6 is always 0, S5 indicates the condition of the IF flag bit
• S4 & S3 show which segment is presently being used for memory
accesses.
•The address bits are separated from the status bits using the latches
controlled by the ALE
Address and Data lines
BHE/S7- Bus High Enable/Status
BHE*
A0
Characteristics
0
0
Whole word
0
1
Upper byte from / to odd address
1
0
Lower byte from / to even address
1
1
None
Signal Description
Signal Group of 8086
INTR-Interrupt Request:
• This is a triggered input.
• Used to request a hardware interrupt
•This can be internally masked by resetting the interrupt enable flag.
• This signal is active high and internally synchronized.
8086
NMI
17
INTR
18
NMI-Non – Maskable Interrupt
An edge triggered input which causes a type 2
interrupt.
A subroutine is vectored to via an interrupt vector
lookup table located in system memory.
NMI is not maskable internally by software.
A transition from a LOW to HIGH initiates the interrupt
at the end of the current instruction.
This input is internally synchronized.
Reset
• This causes the processor to immediately terminate its present
activity and start execution from FFFF0h, if it is active HIGH for at
least four clock cycles.
• It restarts execution when the RESET is low
• when RESET returns LOW. RESET is internally synchronized.
CPU component
Contents
Flags
Cleared
Instruction Pointer
0000H
CS
FFFFH
DS, SS and ES
0000H
Queue
Empty
Unit 4: 8086 Bus Configuration and Timings
• Physical memory Organization, General Bus operation cycle, I/O
addressing capability, Special processor activities, Minimum mode
8086 system and Timing diagrams, Maximum Mode 8086 system and
Timing diagrams.
• Basic Peripherals and their Interfacing with 8086 :Static RAM
Interfacing with 8086 , Interfacing I/O ports, PIO 8255, Modes of
operation – Mode-0 and BSR Mode, Interfacing simple switches and
simple LEDs using 8255.
Minimum Mode Interface
• When the Minimum mode operation is selected, the 8086 provides all
control signals needed to implement the memory and I/O interface.
• The minimum mode signal can be divided into the following basic
groups :
• address/data bus
• status
• control
• interrupt
• DMA.
• Address/Data Bus : these lines serve two functions. As an address
bus is 20 bits long and consists of signal lines A0 through A19. A19
represents the MSB and A0 LSB. A 20bit address gives the 8086 a
1Mbyte memory address space. More over it has an independent I/O
address space which is 64K bytes in length.
Minimum Mode Interface contd..
• The 16 data bus lines D0 through D15 are actually multiplexed with
address lines A0 through A15 respectively. By multiplexed we mean
that the bus work as an address bus during first machine cycle and as
a data bus during next machine cycles. D15 is the MSB and D0 LSB.
• When acting as a data bus, they carry read/write data for memory,
input/output data for I/O devices, and interrupt type codes from an
interrupt controller.
Minimum Mode Interface contd..
Source: NPTEL 8086 microprocessor
Minimum Mode Interface contd..
• Status signal : The four most significant address lines A19 through
A16 are also multiplexed with status signals S6 through S3. These
status bits are output on the bus at the same time that data are
transferred over the other bus lines.
• Bit S4 and S3 together from a 2 bit binary code that identifies which
of the 8086 internal segment registers are used to generate the
physical address that was output on the address bus during the
current bus cycle.
• Code S4 S3 = 00 identifies a register known as extra segment register
as the source of the segment address.
Minimum Mode Interface contd..
• Status line S5 reflects the status of another internal characteristic of
the 8086. It is the logic level of the Internal Enable flag. The last status
bit S6 is always at thelogic 0 level.
• Control Signals : The control signals are provided to support the 8086
memory and I/O interfaces.
• They control functions such as when the bus is to carry a valid
address in which direction data are to be transferred over the bus,
when valid write data are on the bus and when to put read data on
the system bus.
O/P
• This is an interrupt acknowledge signal.
• When microprocessor receives INTR
signal, it acknowledges the interrupt by
generating this signal.
• It is an active low signal.
DMA Interface Signals
DMA Interface Signals – HOLD (I/P ) & HLDA (O/P)
• When DMA controller needs to use
address/data bus, it sends a request
to the CPU through this pin.
• It is an active high signal.
• When microprocessor receives HOLD
signal, it issues HLDA signal to the
DMA controller.
DMA Interface Signals – HOLD & HLDA
• HLDA- It is a HOLD Acknowledge signal.
• It is issued after receiving the HOLD signal.
• It is an active high signal.
ALE(Output)
• This is an Address Latch Enable signal.
• It indicates that valid address is
available on bus AD0 – AD15.
• It is an active high signal and remains
high during T1 state.
• It is connected to enable pin of latch
8282.
• This is a Data Transmit/Receive signal.
• It decides the direction of data flow
through the transceiver.
• When it is high, data is transmitted
out.
• When it is low, data is received in
• This signal is issued by the microprocessor
to distinguish memory access from I/O
access.
• When it is high, memory is accessed.
• When it is low, I/O devices are accessed.
Pin Description for Maximum Mode
QS1 and QS0 (Output)
• These pins provide the status of instruction queue.
• These status signals indicate the operation being
done by the microprocessor.
• This information is required by the Bus Controller
8288.
• Bus controller 8288 generates all memory and I/O
control signals.
• The minimum mode signals, INTA, ALE, DEN, DT/ IT, M/ 10 ,
WR , HLDA, and HOLD (on pins 24 to 31) that are essential
for interfacing memory and I/O devices, are not available
in the system if the 8086 is operated in maximum mode.
• An 8288 bus controller is used to generate the
relevant signals for interfacing memory and I/O
devices in the maximum mode. ...
0
0
0
0
1
1
1
1
S0
S1
S2
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Indication
Interrupt Acknowledge
Read I/O port
Write I/O port
Halt
Code access
Read memory
Write memory
Passive
• This signal indicates that other processors
should not ask CPU to relinquish the
system bus.
• When it goes low, all interrupts are masked
and HOLD request is not granted.
• This pin is activated by using LOCK prefix
on any instruction
• When the CPU is executing a critical
instruction which requires the system bus,
the LOCK prefix instruction ensures that
other processors connected in the system
will not gain the control of the bus
8086 Minimum Mode
• In the minimum mode of 8086, MN/MX pin is connected to logic 1
(+5V )
• There is a single processor (8086) in this mode
• All the control signals are given out by the microprocessor chip itself.
• Other supporting components in the system are latches,
transeceivers, clock generator, memory and I/O devices.
• Requires less (or minimum) hardware (than maximum mode) & thus
less costly but can not be used in large multiprocessor systems
8086 Minimum Mode contd..
8086 Maximum Mode
8086 Maximum Mode contd..
8086 Memory Organization
8086 Memory Organization contd..
• While referring to word data, the BIU requires two memory cycles,
depending upon whether the starting byte is at an even or odd
address
• If it is located at an even address, only one read or write cycle is
required
• If the word is located at an odd address, the first read/write cycles is
required for accessing the lower byte while the second one is
required for accessing the upper byte.
• Two bus cycles are required, if a word is located at an odd address
• As 8086 is a 16-bit processor, it can access two bytes of data in one
memory or I/O read or write operation
• But the commercially available memory chips are only one byte size, i.e
they can store only one byte in a memory location
• Hence to store 16 bit data, two successive memory locations are used and
the lower byte is stored in the first memory location and the higher byte
in the next location
• In a 16 but read or write operation, both of these bytes will be read or
written in a single machine cycle
Physical Memory Organization
• Bits D0-D7 of a word will be transferred over D0-D7 (lower byte) of
16-bit data bus to/from 8-bit memory and bits D8-D15 of the 16-bit
data will be transferred over D8-D15 (higher byte) of the 16-bit data
bus of the processor
• Hence to transfer 16-bit data at a time using 8-bit memories, the
memory map of 8086 is divided into even and odd address memory
banks.
General Bus Operation
• 8086 has a time multiplexed address and data bus . The main reason is to reduce
the number of pins on the IC
• The bus can be demultiplexed using a few latches and transceivers, whenever
required
• Basically, all the processor bus cycles consist of at least four clock cycles T1,
T2,T3 and T4 .
• The address is transmitted by the processor during T1. It is present on the bus
only for one cycle. During T2, i.e. the next cycle, the bus is tristated for changing
the direction of bus for the following data read cycle. The data transfer takes
place during T3 and T4. In case, an addressed device is slow and shows ‘NOT
READY’ status the wait states Tw are inserted between T3 and T4. These clock
states during wait period are called idle states (Ti), wait states (Tw ) or inactive
states. The processor uses these cycles for internal housekeeping.
General Bus Operation cycle
I/O Addressing Capability
• The 8086/8088 processor can address up to 64K I/O byte registers or
32K word registers.
• The limitation is that the address of an I/O device must not be greater
than 16 bits in size, this means that a maximum number of 216, i.e.
64Kbyte I/O devices may be accessed by the CPU.
• The I/O address appears on the address lines A 0 to A 15 for one clock
cycle (T1).
• It may then be latched using the ALE signal.
• The upper address lines (A19-A16) are at logic 0 level during the I/O
operations.
I/O Addressing Capability contd..
• The 16-bit register DX is used as 16-bit I/O address pointer, with full
capability to address up to 64K devices.
• In this case, the I/O ports are addressed in the same manner as
memory locations in the based addressing mode using BX.
• In memory mapped I/O interfacing, the I/O device addresses are
treated as memory locations in page 0, i.e. segment address 0000H.
Even addressed bytes are transferred on D0—D7 and odd addressed
bytes are transferred on D8 to D15 lines. While designing any 8-bit
I/O system around 8086, care must be taken that all the byte registers
in the system should be even addressed.
• IN AL, DX DX=16 bit port address OUT 9ch, AX/AL
• IN AL, 9h (8 bit port address)
OUT DX, AL/AX
8086 IO addressing scheme.
Unit 4: 8086 Bus Configuration and Timings
• Physical memory Organization, General Bus operation cycle, I/O
addressing capability, Special processor activities, Minimum mode
8086 system and Timing diagrams, Maximum Mode 8086 system and
Timing diagrams.
• Basic Peripherals and their Interfacing with 8086 :Static RAM
Interfacing with 8086 , Interfacing I/O ports, PIO 8255, Modes of
operation – Mode-0 and BSR Mode, Interfacing simple switches and
simple LEDs using 8255.
Minimum Mode Signals
Minimum mode system and timings
Read cycle timing diagram for minimum mode
Write cycle timing diagram for minimum mode
Write cycle timing diagram for minimum mode contd..
Maximum Mode Signals
Maximum mode-Bus status codes
The minimum mode signals, INTA, ALE, DEN, DT/ IT, M/ 10 , WR
, HLDA, and HOLD (on pins 24 to 31) that are essential for
interfacing memory and I/O devices, are not available in the
system if the 8086 is operated in maximum mode
Memory read timing in Maximum mode
Memory read timing in Maximum mode contd..
• The maximum mode system timing diagrams are also divided into two
portions as read (input) and write (output) timing diagrams
• The address/data and address/status timings are similar to minimum
mode
• ALE is asserted in T1 just like minimum mode
• The only difference lies in the status signals used and the available
control and advanced command signals (AIOWC, AMWC..)
Memory write timing in Maximum mode
Static RAM interfacing
• The semiconductor memories are organized as two dimensional arrays of
memory locations.
• For example, 4K x 8 or 4K byte memory contains 4096 locations, where
each location contains 8-bit data and only one of the 4096 locations can
be selected at a time.
• Once a location is selected all the bits in it are accessible using ‘data
bus’.
• For addressing 4K bytes of memory, twelve address lines are required.
• In general, to address a memory location out of N memory locations , we
will require at least n bits of address, i.e. n address lines where n = Log2 N.
• Thus if the microprocessor has n address lines, then it is able to address
at the most N locations of memory, where 2n = N.
Static RAM interfacing contd..
• The general procedure of static memory interfacing with 8086 is
briefly described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus
width. The upper 8-bit bank is called ‘odd address memory bank’ and
the lower 8-bit bank is called ‘even address memory bank’,
2. Connect available memory address lines of memory chips with those
of the microprocessor and also connect the memory RD and WR inputs
to the corresponding processor control signals. Connect the 16-bit data
bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0 are
used for decoding the required chip select signals for the odd and even
memory banks. The CS of memory is derived from the O/P of the
decoding circuit
Example
Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with 8086.
Select suitable maps.
• Solution: We know that, after RESET, the IP and CS are initialized to
form address FFFF0H. Hence, this address must lie in the EPROM. The
address of RAM may be selected any where in the 1MB address space
of 8086, but we will select the RAM address such that the address
map of the system is continuous, as shown
FE000h-FFFFFh=ROM
FC000h-FDFFFh-RAM
Solution contd..
• Total 8K bytes of EPROM need 13 address lines A0—A12 (since 213 =
8K). Address lines A13—A19 are used for decoding to generate the chip
select. The BHE signal goes low when a transfer is at odd address or
higher byte of data is to be accessed. Let us assume that the latched
address, BHE and demultiplexed data lines are readily available for
interfacing.
BHE*
A0
Characteristics
0
0
Whole word
0
1
Upper byte from / to odd address
1
0
Lower byte from / to even address
1
1
None
Solution contd..
• The memory system in this example contains in total
four 4K x 8 memory chips.
• The two 4K x 8 chips of RAM and ROM are arranged in BHE A
*
parallel to obtain 16-bit data bus width. If A0 is 0, i.e.
the address is even and is in RAM, then the lower RAM 0 0
0
1
chip is selected indicating 8-bit transfer at an even
address. If A0 is 1, i.e. the address is odd and is in RAM, 1 0
the BHE goes low, the upper RAM chip is selected,
1
1
further indicating that the 8-bit transfer is at an odd
address.
• If the selected addresses are in ROM, the respective
ROM chips are selected. If at a time A0 and BHE both
are 0, both the RAM or ROM chips are selected, i.e. the
data transfer is of 16 bits.
0
Characteristics
Whole word
Upper byte from / to odd
address
Lower byte from / to even
address
None
Interfacing diagram
A13 A0 BHE* =1 1 0 – Odd address
A13 A0 BHE* =1 0 1 -- even address
Unit 4- L5-L6-9.6.2021
Recap
• MIN and MAX mode timing diagrams,
• Interfacing static RAM with an example
Unit 4: 8086 Bus Configuration and Timings
• Physical memory Organization, General Bus operation cycle, I/O
addressing capability, Special processor activities, Minimum mode
8086 system and Timing diagrams, Maximum Mode 8086 system and
Timing diagrams.
• Basic Peripherals and their Interfacing with 8086 :Static RAM
Interfacing with 8086 , Interfacing I/O ports, PIO 8255, Modes of
operation – Mode-0 and BSR Mode, Interfacing simple switches and
simple LEDs using 8255.
Example
Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with 8086.
Select suitable maps.
• Solution: We know that, after RESET, the IP and CS are initialized to
form address FFFF0H. Hence, this address must lie in the EPROM. The
address of RAM may be selected any where in the 1MB address space
of 8086, but we will select the RAM address such that the address
map of the system is continuous, as shown
FE000h-FFFFFh=ROM
FC000h-FDFFFh-RAM
Solution contd..
• The two 4K x 8 chips of RAM and ROM are arranged in
parallel to obtain 16-bit data bus width. If A0 is 0, i.e.
the address is even and is in RAM, then the lower RAM
BHE A
chip is selected indicating 8-bit transfer at an even
*
address. If A0 is 1, i.e. the address is odd and is in RAM, 0 0
the BHE goes low, the upper RAM chip is selected,
0
1
further indicating that the 8-bit transfer is at an odd
1
0
address.
1
1
• If the selected addresses are in ROM, the respective
ROM chips are selected. If at a time A0 and BHE both
are 0, both the RAM or ROM chips are selected, i.e. the
data transfer is of 16 bits.
0
Characteristics
Whole word
Upper byte from / to odd
address
Lower byte from / to even
address
None
Interfacing diagram
A13 A0 BHE* =1 1 0 – Odd address
A13 A0 BHE* =1 0 1 -- even address
ROM Interfacing, A13 is always 1, RAM Interfacing= A13 is
always 0
Solution contd..
• The two 4K x 8 chips of RAM and ROM are arranged in parallel to
obtain 16-bit data bus width. If A0 is 0, i.e. the address is even and is
in RAM, then the lower RAM chip is selected indicating 8-bit transfer
at an even address. If A0 is 1, i.e. the address is odd and is in RAM,
the BHE goes low, the upper RAM chip is selected, further indicating
that the 8-bit transfer is at an odd address. If the selected addresses
are in ROM, the respective ROM chips are selected. If at a time A0
and BHE both are 0, both the RAM or ROM chips are selected.
Selection of Chips is shown in the table
Example 2
•It is required to interface two chips of 16K x 8 ROM and two chips of 32K x 8
RAM with 8086. Select the EPROM address suitably. The RAM address must
start at 00000h
•Show the implementation of this memory system.
Solution : The last address in the map of 8086 is FFFFFh. After resetting, the
processor starts from FFFF0h..
Hence this address must lie in the address range of EPROM.
Address Mapping
• For 32 KB, number of address lines required -15 A0-A14
• For 64 KB, number of address lines required -16 A0-A15
• It is better not to use a decoder to implement the above map because
it is not continuous . I.e.. There is some unused address space
between the last RAM address (0FFFFh) and the first EPROM address
(F8000h)
Interfacing Diagram
For 32 KB, number of address lines
required -15 A0-A14, hence A15-A19 are
used for chip selection
For 64 KB, number of address lines
required -16 A0-A15
hence A16-A19 are used for chip
selection
BHE*
A0
Characteristics
0
0
Whole word
0
1
Upper byte from / to odd address
1
0
Lower byte from / to even address
1
1
None
Interfacing I/O ports
•I/O ports are the devices through which the microprocessor communicates with
other devices or external data sources/destinations.
•Input activity, as one may expect, is the activity that enables the microprocessor
to read data from external devices , for example keyboards, joysticks, mouse, etc.
•These devices are known as input devices as they feed data into a microprocessor
system.
•Output activity transfers data from the microprocessor to the external devices, for
example CRT display, 7-segment displays, printers, etc.
•The devices which accept the data from a microprocessor system are called
output devices.
•Thus for a microprocessor the input activity is similar to read operation, while the
output activity is similar to write operation. i.e an input device can only be read
and an output device can only be written.
Interfacing I/O ports contd..
• Hence IORD operation is for reading data from an input device and IOWR
operation is for writing data to an output device
• After executing an OUT operation, the data appears on the data bus and
simultaneously a device select signal is generated from the address and control
signals.
• Now, if the data is to be there, at the output of the device till the next change, it
must be latched. The latch acts as a good output port. The chip 74LS373, contains
eight bufferred latches and can be used as an 8-bit output port.
• While reading an input device one must take care that much current should not
be sourced or sunk from the data lines to avoid loading.
• To overcome this problem, one may use a tristate buffer as an input device. An
input port may not be a latch as it reads the status of a signal at a particular
instant. The chip 74LS245 contains eight buffers and may be used as an 8-bit
input port.
Tri-state Buffer
• The “Tri-state Buffer”-output can be “electronically” disconnected from its output circuitry when
required.
• A Tri-state Buffer can be thought of as an input controlled switch with an output that can be
electronically turned “ON” or “OFF” by means of an external “Control” or “Enable” ( EN ) signal
input. This control signal can be either a logic “0” or a logic “1” type signal resulting in the Tristate Buffer being in one state allowing its output to operate normally producing the required
output or in another state were its output is blocked or disconnected.
• Then a tri-state buffer requires two inputs. One being the data input and the other being the
enable or control input as shown.
• 74LS245 is a bidirectional buffer, but while using it as an input device, only one
direction is useful. This direction of data transfer in 74LS245 is selected using its DIR
pin
• If DIR is 1, then the direction is from A(I/Ps) to B(O/Ps), otherwise the data
direction is from B(I/Ps) to A(O/Ps).
Steps in Interfacing an l/O Device
• The following steps are performed to interface a general I/O device
with a CPU:
• (i) Connect the data bus of the microprocessor system with the data
bus of the I/O port.
• (ii) Derive a device address pulse by decoding the required address
of the device and use it as the chip select of the device.
• (iii) Use a suitable control signal, i.e. IORD and/or IOWR to carry out
device operations, i.e. connect IORD to RD input of the device if it is
an input device, otherwise connect IOWR to WR input of the device.
• In some cases the RD or WR control signals are combined with the
device address pulse to generate the device select pulse.
Methods of Interfacing l/O Devices
• There are two methods of interfacing general I/O devices.
1. I/O mapped
2. Memory-mapped
The principal distinction in the two approaches is that in I/O mapped
interfacings, the devices are viewed as distinct I/O devices and are
addressed accordingly.
While in memory-mapped scheme, the devices are viewed as memory
locations and are addressed likewise.
I/O mapped interfacing
• All the available address lines of a microprocessor may not be used for interfacing
the devices.
• The processor 8086 has 20 address lines. The I/O mapped scheme may use at
the most 16 address lines A0 -A15 or even 8 address lines for address
decoding.
• The unused higher order address lines are logic zero, while addressing the device.
An I/O mapped device requires the use of IN and OUT instructions for accessing
them.
• The I/O mapped method requires less hardware for decoding, as less number of
address lines are used. In case of 8086, a maximum of 64K input and 64K byte
output devices or 32K input and 32K word output devices can be interfaced. In
addition to address and data busses, to address an input device, we require the
IORD signal and to address an output device, we use IOWR signal for the
respective operations.
• The IOWR and IORD signals are used for I/O mapped interfacing
Memory-mapped interfacing
• All the available address lines are used for address decoding. Thus
each memory-mapped I/O device with 8086 has a 20-bit address, i.e.
8086 can have as many as 1M memory- mapped input and as many
byte output devices.
• Practically this is impossible, as memory-mapped I/O devices
consume the addresses in the memory map of the CPU.
• 1M byte devices will require the complete IMbyte of the memory
map and nothing will be left as program memory. Also the memory
locations and
• the memory-mapped devices cannot have common addresses. The
MRDC and MRTC signals are used for interfacing in memory-mapped
I/O scheme.
• All the applicable data transfer instructions (e.g. MOV, LEA) can be
used to communicate with memory-mapped I/O devices
Example
• Interface an input port 74LS245 to read the status of switches SW1 to SW8.
The switches, when shorted, input a ‘1’ else input a ‘0’ to the
microprocessor system. Store the status in register BL. The address of the
port is 0740H.
• The address, control and data lines are assumed to be readily available at
the microprocessor system.
The ALP is given below
MOV BL , 00H; Clear BL for status
MOV DX, 0740H
; 16-bit port address in DX
IN AL, DX ; Read port 0740H for switch positions
MOV BL, AL; Store status of switches from AL into BL
HLT
; Stop
8255 (Programmable Peripheral Interface or programmable
peripheral input-output port)
8255 features
•The 8255 is a 40-pin DIP chip.
•It has three separately accessible ports.
•The ports are each 8-bit, and are named A, B and C.
•The individual ports of the 8255 can be programmed as input or output and
can be changed dynamically.
•In addition, 8255 ports have handshaking capability, thereby allowing
interface with devices that also have handshaking signals, such as printers.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
8255 features contd…
The Intel's 8255 is designed for use with Intel's 8-bit, 16-bit and higher
capability microprocessors.
It has 24 input/output lines which may be individually programmed in two
groups of twelve lines each, or three groups of eight lines.
The two groups of I/O pins are named as Group A and Group B. Each of these
two groups contain a subgroup of eight I/O lines called as 8-bit port and
another subgroup of four I/O lines or a 4-bit port.
Thus Group A contains an 8-bit port A along with a 4-bit port, C upper.
The port A lines are identified by symbols PA0—PA7 while the port C lines are
identified as PC4—PC7. Similarly, Group B contains an 8-bit port B, containing
lines PB0 — PB7 and a 4-bit port C with lower bits PC0—PC3. The port C upper
and port C lower can be used in combination as an 8-bit port C. Both the port
Cs are assigned the same address. Thus one may have either three 8-bit I/O
ports or two 8-bit and two 4-bit I/O ports
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
8255 Internal Architecture
The 8-bit data bus buffer is controlled by the
read/write control logic. The read/write
control logic manages all of the internal and
external transfers of both data and control
words
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
The pin diagram of 8255 is shown in the figure below.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
8255 ports
• PA0-PA7 – The 8-bit port A can be programmed as all input or output, or
all bits as bidirectional input/output.
• PB0-PB7 The 8-bit port B can be programmed as all input or output , but it
cannot be used as a bidirectional port.
• PC0–PC7- The 8-bit port C can be used as all input or output. It can also be
split into two parts. , CU (upper bits PC4-PC7) and CL (lower bits PC3-PC0).
• Each can be used for input or output.
• Each bit of PC can be programmed individually
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
RD and WR :These two active low control signals are inputs to the 8255.
The RD and WR signals from the 8086 are connected to these inputs.
D0-D7 data pins: The data pins of the 8255 are connected to the data pins of
the processor allowing it to send back and forth between the processor and
the 8255 chip.
RESET: This is an active-high signal input into the 8255 and used to clear the
control register.
• A logic high on this line clears the control word of 8255.
• All ports are set as input ports by default after RESET.
• In many designs, this pin is connected to the RESET output of the system
bus grounded to make it inactive.
• Like all IC input pins, it should not be left unconnected.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
• A0, A1 and CS: When CS selects the entire chip, it is
A0 and A1 that select specific ports.
• These three pins are used to access ports A, B, C or
the control register as shown in the table
CS
0
0
0
0
1
A1
0
0
1
1
X
A0
0
1
0
1
x
Selection
Port A
Port B
Port C
Control Register
8255 not selected
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
Mode selection of the 8255
While A, B and C are used to input or output data, it is the control
register that must be programmed to select the operation mode of the
three ports.
The ports of the 8255 can be programmed in two modes.
 I/O mode
 BSR mode.
I/O mode-This mode is selected when the most significant bit (D7) in the
control register is 1.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
1. Mode 0-simple I/O mode
• In this mode, any of the ports A, B and C can be used as input
or output.
• In this mode, all bits are out or all bits are in.
• i.e Individual bit of a port cannot be programmed.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
2. Mode 1-In this mode, port A and port B can be used as input or
output ports with handshaking capabilities.
The handshaking signals are provided by the bits of port C.
Example: When CPU wants to send data to slow peripheral device
like printer, it will send handshaking signal to printer to tell whether
it is ready or not to transfer the data. When printer will be ready it
will send one acknowledgement to CPU then there will be transfer
of data through data bus.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
Mode 2-Port A can be used as a bidirectional I/O port with handshaking
capabilities provided by port C.
Port B can be used either in mode 0 or mode 1.
II. BSR (Bit set/reset ) mode- Only the individual bits of port C can be
programmed.
When the MSB of control register is 0, this mode is selected as shown
below.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
8255 Control Word Format (I/O Mode)
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
Example: Find the control word of the 8255 for the following
configurations
(a) All the ports of A, B and C are output ports (mode 0)
(b) PA=in, PB=out, PCL=out, PCH=out
Solution:
(a)10000000=80H (b)10010000=90H
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
Example: Refer the fig below and
1.Find the addresses for the ports A, B and C and the control register
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
(a)The address of the ports is such that only if A14 is 1, the chip will be
selected. Also the condition of A1 and A0 for the ports and control register
are as follows
A1
A0
Port A
0
0
Port B
0
1
Port C
1
0
Control register
1
1
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
The rest of the address lines can be 1 or 0.
For example,. If we take all these lines as 0, the addresses will be 4000h
for port A, 4001h for port B, 4002h for Port C and 4003h for the control
register.
A15 A14 A13 A12 A11…………………………………………A1.A0
0
1
0
0,
0 ……………………………………………0..0 4000h
0
1
0
0 ,
0…………………………………………… 0 1 4001h
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
2. Four switches are connected to the lower 4-bit line (PB0-PB3). Write a
program to transfer the status of these switches to LEDs connected to the
upper 4-bits of port A (PA4-PA7).
• Since the switch information has to be read into the A register, port B
has to be an input port.
• Port A is an output port because it is connected to LEDs which display
data fed into it. The control word is 10000010b, ie. 82h
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE
(a). Find the I/O port addresses assigned to ports A, B, C and the control register
(b). Find the control byte for PA=in, PB=out, PC= out.
Prepared by Dr Rajeshwari Hegde, Dept. of ETE, BMSCE