Scan Assignments: 2
1. Why do we need SCAN?
Scan chain testing is a method to detect various manufacturing faults in the silicon.
Although many types of manufacturing faults may exist in the silicon. Circuit is designed
using pre-described design rules. Test structure is added to the verified design.
Replacing the standard flops to a scan flip-flops and connect to form one or more shift
registers in test mode. This is done in order to make every point in the chip controllable
and observable as discussed below.
2. SCAN STYLES:
There are three types of scan styles that are commonly talked about in the industry.
They are,
1. Multiplexed Scan Style
2. Dual Clock Scan Style and
3. LSSD (Level Sensitive Scan Design) style
The most commonly used method is the first one (MUXScan style) and this is a simpler
method too. Most of the tools and ASIC vendors support this method of scan design.
The second method is also not a very difficult one. The difference here is that there will
be a separate clock for the scan mode. apart from the normal functional mode clock.
These two methods are more suitable for flipflop based designs.
The third method is more suitable for latch based designs and the ASIC vendor has to
support this scan design using special types of cells particularly designed for this
method. These scan cells occupy almost double the size of the normal flop cell and
hence there is a huge area impact on the chip. This method is not very widely used.
3. How do we do scan?








Select scan mode
Shift scan cell values
Select normal mode
Force primary input values
Measure primary output values.
Capture circuit response into scan cells.
Select scan mode
Shift out scan data,shift in next set of scan cells.
4. What is scan insertion?
The process of converting the sequential elements to the scan cells and stitching them
to a shift register to have full controllability and observability in the design is called scan
stitching/scan insertion/scan stitching.
5. Scan Rules:
 All internal clocks must be controlled by port level clk signal(primary
input)in scan test mode.
 Avoid implementation of combinational feedback.
 Asynchronous set/reset pins of the flip flops must be controlled by the
port level RESET In scan test mode.
 Gated clock must be enabled in scan test mode.
 Latches must be avoided as much as possible, if present make them
transparent in scan test mode.
 Don’t replace flops of the shift register structure by equivalent scan
flops.
 Clock should not be used as data in scan test mode.
 Bypass the memory/macros in the scan test mode
6. Stuck at fault detection for the given circuit