MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
Salient Features of 8051:
1) A Microcontroller is a complete computer system built on a single chip.
2) It contains all components like Processor (CPU), RAM, ROM, Serial port, Parallel port,
Interrupt logic, Timers etc.. on chip.
3) A Microcontroller saves cost, saves power consumption and makes the circuit compact.
4) Microcontrollers are ideally suited for appliances like remote controllers, refrigerators,
microwave ovens, modems etc.
5) 8051 is an 8-bit Microcontroller, it has an 8 bit ALU. This means all arithmetic and logic
operations are of 8 bits.
6) 8051 has an 8-bit data bus, so all external Data Transfers will be of 8-bits in one cycle.
7) It has internal ROM of 4KB used for storing programs.
8) It has internal RAM of 128 bytes used for storing data.
9) Since program memory (ROM) and data memory (RAM) are separate, 8051 follows
Harvard Model. In contrast, Processors based on Von Neumann Model store programs and data
in a common memory space.
10) There are 4, 8bit, bidirectional I/O ports for interfacing external devices like keyboards,
displays etc. These ports can also be used for their alternate functions like multiplexed
address data buses and control signals.
11) It has a serial port for long distance communication.
The serial port can perform synchronous and asynchronous transfers.
12) 8051 has two, 16bit Timers, which act as ‘up’ counters.
They are used to produce hardware delays and for counting external events.
13) There are 5 interrupts, operating at two priority levels.
14) 8051 has two power saving modes called “Idle mode” and “Power Down mode”.
15) In addition to internal memory, up to 64 KB of external RAM and External ROM can be
connected, as per user requirement. The figure 64 KB is due to the 16-bit address bus.
16) 8051 is a 40-pin IC and typically operates at 12 MHz frequency.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
PIN DIAGRAM OF 8051
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8051 has 40 pins.
The function of these pins is briefly explained as follows.
XTAL1
&
XTAL2
These are connected to the crystal oscillator.
The typical operating frequency is 12 MHz.
In Serial communication based applications, the operating frequency is
chosen to be 11.0592 MHz, in order to derive the standard universal baud
rates. This will be discussed in detail in the further chapters.
Reset
It is used to reset the 8051 microcontroller.
On reset PC becomes 0000H.
This address is called the reset vector address.
From here, 8051 executes the BIOS program also called the Booting
program or the monitor program. It is used to set-up the system and make
it ready, to be used by the end-user.
It is used to enable the latching of the address.
The address and data buses are multiplexed.
ALE
This is done to reduce the number of pins on the 8051 IC.
Address
Once out of the chip, address and data have to be separated that is called
Latch Enable
de-multiplexing.
This is done by a latch, with the help of ALE signal.
ALE is “1” when the bus carries address and “0” when the bus carries data.
This informs the latch, when the bus is carrying address so that the latch captures only address and
not the data.
EA
Enable External
Access
It decides whether the first 4 KB of program memory space (0000H… 0FFFH)
will be assigned to internal ROM or External ROM.
If EA = 0, the External ROM begins from 0000H.
In this case the Internal ROM is discarded.
8051 now uses only External ROM.
If EA = 1, the External ROM begins from 1000H.
In this case the Internal ROM is used. It occupies the space 0000H… 0FFFH.
In modern FLASH ROM versions, this pin also acts as VPP (12 Volt programming voltage) to write
into the FLASH ROM.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
8051 has a 16-bit address bus (A15 – A0).
This should allow 8051 to access 64 KB of external Memory as 216 = 64 KB.
PSEN
Interestingly though, 8051 can access 64 KB of External ROM and 64 KB
Program
of External RAM, making a total of 128 KB.
Status Enable
Both have the same address range 0000H to FFFFH.
This does not lead to any confusion because there are separate control signals
for External RAM and External ROM.
RD and WR are control signals for External RAM.
PSEN is the READ signal for External ROM.
It is called Program Status Enable as it allows reading from ROM also known as Program Memory.
Having separate control signals for External RAM and External ROM actually allows us to double
the size of the external memory to a total of 128 KB from the original 64 KB.
Vcc
&
GND
These are power supply pins.
8051 works at +5V / 0V power supply.
These are 8 pins of Port 0.
We can perform a byte operation (8-bit) on the whole port 0.
We can also access every bit of port 0 individually by performing bit
P0.0… P0.7
operations like set, clear, complement etc.
The bits are called P0.0… P0.7.
Additionally, Port 0 also has an alternate function.
It carries the multiplexed address data lines.
A0-A7 (the lower 8 bits of address) and D0-D7 (8 bits of data) are multiplexed into AD0-AD7.
In any operation address and data are not issued simultaneously.
First, address is given, then data is transferred.
Using a common bus for both, reduces the number of pins.
To identify if the bus is carrying address or data, we look at the ALE signal.
If ALE = 1, the bus carries address,
If ALE = 0, the bus carries data.
P1.0… P1.7
These are 8 pins of Port 1.
We can perform a byte operation (8-bit) on the whole port 1.
We can also access every bit of port 1 individually by performing bit
operations like set, clear, complement etc. on P1.0… P1.7.
Port 1 also has NO alternate function.
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P2.0… P2.7
These are 8 pins of Port 2.
We can perform a byte operation (8-bit) on the whole port 2.
We can also access every bit of port 2 individually by performing bit
operations like set, clear, complement etc. on P2.0… P2.7.
Additionally, Port 2 also has an alternate function.
It carries the higher order address lines A8-A15.
P3.0… P3.7
These are 8 pins of Port 3.
We can perform a byte operation (8-bit) on the whole port 3.
We can also access every bit of port 3 individually.
The bits are called P0.0… P0.7.
The various pins of Port 3 have a lot of alternate functions.
P3.0 (Rxd) and P3.1 (Txd):
They are used to receive and transmit serial data.
This forms the serial port of 8051.
P3.2 ( INT0 ) and P3.3 ( INT1 ): They are external hardware interrupts of 8051.
If they occur simultaneously, INTO is by default higher priority.
P3.4 (T0) and P3.5 (T1):
They are used timer clock inputs.
They provide external clock inputs to Timer 0 and Timer 1.
P3.6 ( WR ) and P3.7 ( RD ):
They are used as control signals for External RAM.
8051 can access 64 KB External RAM from 0000H to FFFFH..
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
8051 BLOCK DIAGRAM
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Alternate diagram …
ALTERNATE DIAGRAM FOR 8051 ARCHITECTURE / BLOCK DIAGRAM
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
8051 is a microcontroller. This means it has an internal processor, internal memory and an I/O
section. The architecture of 8051 is thus divided into three main sections:
• The CPU
• Internal Memory
• I/O components.
CPU
8051 has an 8 bit CPU.
This is where all 8-bot arithmetic and logic operations are performed.
It has the following components.
ALU – ARITHMETIC LOGIC UNIT
It performs 8-bit arithmetic and logic operations.
It can also perform some bit operations.
Example:
ADD A, R0
ANL A, R0
CPL P0.0
; Adds contents of A register and R0 register and stores the result in A register.
; Logically ANDs contents of A register and R0 register and stores the result in A register.
; Complements the value of P0.0 pin.
A – REGISTER (ACCUMULATOR)
It is an 8-bit register.
In most arithmetic and logic operations, A register hold the first operand and also gets the
result of the operation.
Moreover, it is the only register to be used for data transfers to and from external memory.
Example:
ADD A, R1
MOVX A, @DPTR
; Adds contents of A register and R1 register and stores the result in A register.
; A gets the data from External RAM location pointed by DPTR
B – REGISTER
It is an 8-bit register.
It is dedicated for Multiplication and Division.
It can also be used in other operations.
Example:
MUL AB
DIV AB
; Multiplies contents of A and B registers. Stores 16-bit result in B and A registers.
; Divides contents of A by those of B. Stores quotient in A and remainder in B.
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PC – PROGRAM COUNTER
It is an 16-bit register.
It holds address of the next instruction in program memory (ROM).
PC gets automatically incremented as soon as any instruction is fetched.
That’s what makes the program move ahead in a sequential manner.
In the case of a branch, a new address is loaded into PC.
DPTR – DATA POINTER
It is an 16-bit register.
It holds address data in data memory (RAM).
DPTR is divided into two registers DPH (higher byte) and DPL (lower byte).
It is typically used by the programmer to transfer data from External RAM.
It can also be used as a pointer to a look up table in ROM, using Indexed addressing mode.
Example:
MOVX A, @DPTR
; A gets the data from External RAM location pointed by DPTR
MOVC A, @A+DPTR ; A gets the data from ROM location pointed by A + DPTR
SP – STACK POINTER
It is an 8-bit register.
It contains address of the top of stack.
The Stack is present in the Internal RAM.
Internal RAM has 8-bit addresses from 00H… 7FH.
Hence SP is an 8-bit register.
It is affected during Push and Pop operations.
During a Push, SP gets incremented.
During a Pop, SP gets decremented.
PSW – PROGRAM STATUS WORD
It is an 8-bit register.
It is also called the “Flag register”, as it mainly contains the status flags.
These flags indicate status of the current result.
They are changed by the ALU after every arithmetic or logic operation.
The flags can also be changed by the programmer.
PSW is a bit addressable register.
Each bit can be individually set or reset by the programmer.
The bits can be referred to by their bit numbers (PSW.4) or by their name (RS1).
Example:
SETB PSW.3
CLR PSW.4
; Makes PSW.3 ç 1
; Makes PSW.4 ç 0
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
FLAG REGISTER (PSW) OF 8051
RS1 RS0
0
0
1
1
0
1
0
1
REGISTER BANK
RAM ADDRESS
SELECTED BY INSTRUCTIONS
Bank 0
Bank 1
Bank 2
Bank 3
00H … 07H
08H … 0FH
10H … 17H
18H … 1FH
CLR PSW.4, CLR PSW.3
CLR PSW.4, SETB PSW.3
SETB PSW.4, CLR PSW.3
SETB PSW.4, SETB PSW.3
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INTERNAL
MEMORY
8051 has two forms of internal memories.
It has 128 bytes of Internal RAM and 4 KB of Internal ROM.
INTERNAL RAM
8051 has 128 bytes of Internal RAM.
RAM is used to store data, hence is also called Data Memory.
The are 128 locations each containing one byte information.
The address range is 00H… 7FH.
It contains Register banks, a Bit addressable area and a General purpose area.
INTERNAL ROM
8051 has 4 KB of Internal ROM.
ROM is used to store programs, hence is also called Program Memory or Code Memory.
The are 4 K locations each containing one byte information.
The address range is 0000H… 0FFFH.
It mainly contains programs.
It may also contains some permanent data stored in the form of look up tables.
To access programs, the address is given by PC – Program Counter.
To access data, the address is given by DPTR – Data Pointer.
Like any other typical microcontroller, 8051 has several I/O components.
They include I/O ports, Timers, Serial port etc.
COMPONENTS
8051 has 4, 8-bit I/O ports: P0, P1, P2 and P3.
They support bit and byte operations.
They also have several alternate functions.
There are two 16-bit timers, which operate as down counters.
There is a serial port having pins Rxd and Txd to receive and transmit data serially.
There are two external interrupt pins.
Additionally there are address, data and control signals for transfers with External RAM and
External ROM.
I/O
Finally, 8051 has 21, 8-bit internal SFRs (Special Function Registers).
These are used to control operations of the various I/O components mentioned above.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
FLAG REGISTER (PSW) OF 8051
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PSW – PROGRAM STATUS WORD
It is an 8-bit register.
It is also called the “Flag register”, as it mainly contains the status flags.
These flags indicate status of the current result.
They are changed by the ALU after every arithmetic or logic operation.
The flags can also be changed by the programmer.
PSW is a bit addressable register.
Each bit can be individually set or reset by the programmer.
The bits can be referred to by their bit numbers (PSW.4) or by their name (RS1).
CY - CARRY FLAG
It indicates the carry out of the MSB, after any arithmetic operation.
If CY = 1 : There was a carry out of the MSB
If CY = 0 : There was no carry out of the MSB
AC – AUXILIARY CARRY FLAG
It indicates the carry from lower nibble (4-bits) to higher nibble.
If the 8bits are numbered Bit 7 --- Bit 0, this is the carry from Bit 3 to Bit 4.
If AC = 1 : There was an auxiliary carry
If AC = 0 : There was no auxiliary carry
Note: It is particularly useful in an operation called DA A (Decimal Adjust after Addition).
OVR - OVERFLOW FLAG
It indicates if there was an overflow during a signed operation.
An 8-bit signed number has the range -80H… 00H… +7FH.
Any result, out of this range causes an overflow.
If OVR = 1 : There was an overflow in the result
If OVR = 0 : There was no overflow in the result
Overflow is determined by doing an Ex-Or between the 2nd last carry (C6) and the last carry (C7)
Note: After an overflow, the Sign (MSB) of the result becomes wrong.
P - PARITY FLAG
It indicates the Parity of the result.
Parity is determined by the number of 1’s in the result.
If PF = 1 : The result has ODD parity
If PF = 0 : The result has EVEN parity
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
F0 – USER DEFINED FLAG
This flag is available to the programmer.
It can be used by us to store any user defined information.
For example: In an Air Conditioning unit, programmer can use this flag indicate whether the
compressor is ON or OFF (1 or 0).
This flag can be changed by simple instructions like SETB and CLR.
SETB PSW.5; This makes F0 bit ç 1
CLR PSW.5; This makes F0 bit ç 0
RS1, RS0 – REGISTER BANK SELECT
The initial 32 locations (bytes) of the Internal RAM are available to the programmer as registers.
Having so many registers makes programming easier and faster.
Naming R0… R31, would tremendously increase the number of opcodes.
Hence the registers are divided into 4 banks: Bank0… Bank3.
Each bank has 8 registers named R0… R7.
At a time, only of the four banks is the “active bank”.
RS1 and RS0 are used by the programmer to select the active bank.
RS1 RS0
REGISTER BANK
SELECTED BY INSTRUCTIONS
0
0
Bank 0
CLR PSW.4
CLR PSW.3
0
1
Bank 1
CLR PSW.4
SETB PSW.3
1
0
Bank 2
SETB PSW.4
CLR PSW.3
1
1
Bank 3
SETB PSW.4
SETB PSW.3
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NUMERICAL EXAMPLES FOR FLAG REGISTER
1
+
=
31 H
23 H
54 H
Flags Affected:
+
=
39 H
27 H
60 H
Flags Affected:
0
0
0
0
0
1
1
1
0
CY
0
0
0
0
1
0
1
AC
0
0
0
0
1
1
0
0
1
0
1
0
OVR
0
P
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
CY
0
AC
1
1
1
0
OVR
0
1
1
0
P
0
1
+
=
42 H
44 H
86 H
Flags Affected:
0
0
1
CY
0
1
1
0
0
0
0
0
0
0
AC
0
0
0
0
0
1
1
1
0
1
OVR
1
0
0
0
P
1
The result 86H is out of range for a “Signed” Number as it has become greater than +7FH.
Such an event is called a “Signed Overflow”.
In such a case the MSB of the result gives a wrong sign.
Though the result is +ve (+86H) the MSB is “1” indicating that the result is –ve.
Overflow is determined by doing an Ex-Or between the 2nd last Carry and the last Carry.
Here the 2nd last Carry (the one coming into the MSB) is “1”.
The final carry (The one going out of the MSB) is “0”.
As “1” Ex-Or “0” = “1”, the Overflow flag is “1”.
For similar examples, but on Negative numbers…
Please refer to Bharat Sir’s Classroom Notes.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
MEMORY ORGANIZATION
OF 8051
8051 operates with 4 different memories:
Internal ROM
External ROM
Internal RAM
External RAM
Being based on Harvard Model, 8051 stores programs and data in separate memory spaces.
Programs are stored in ROM, whereas data is stored in RAM.
Microcontrollers are used in appliances.
Washing machines, remote controllers, microwave ovens are some of the examples.
Here programs are generally permanent in nature and very rarely need to be modified.
Moreover, the programs must be retained even after the device is completely switched off.
Hence programs are stored in permanent (non-volatile) memory like ROM.
Data on the other hand is continuously changed at runtime.
For example current temperature, cooking time etc. in an oven.
Such data is not permanent in nature and will certainly be modified in every usage of the device.
Hence Data is stored in writeable memory like RAM.
However, sometimes there is permanent data, such as ASCII codes or 7-segment display codes.
Such data is stored in ROM, in the form of Look up tables and is accessed using a dedicated
addressing mode called Indexed Addressing mode. We will discover this in more depth in further
topics.
We are now going to take a closer look at all four memories.
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ROM ORGANIZATION / CODE MEMORY / PROGRAM MEMORY
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
We can implement ROM in three different ways in 8051.
ONLY INTERNAL ROM
8051 has 4 KB internal ROM.
In many cases this size is sufficient and there is no need for connecting External ROM.
Such systems use only Internal ROM of 8051.
All addresses from 0000H… 0FFFH will be accessed from Internal ROM.
Any address beyond that will be invalid.
In such systems EA will be “1” as Internal ROM is being used.
(PS: Read the whole answer to understand EA clearly)
INTERNAL AND EXTERNAL ROM
8051 has 4 KB internal ROM.
In many cases this size is may be insufficient and we may need to add some External ROM.
Such systems use a combination of Internal ROM and External ROM.
The “total” ROM that can be accessed is 64 KB.
Since we are using the Internal ROM of 4 KB, the maximum amount of External ROM that can be
connected is 60 KB.
All addresses from 0000H… 0FFFH will be accessed from Internal ROM.
Addresses 1000H… FFFH will be accessed from External ROM.
In such systems EA will be “1” as Internal ROM is being used.
(PS: Read the whole answer to understand EA clearly)
ONLY EXTERNAL ROM
This is the most interesting case.
Though 8051 has 4 KB of Internal ROM, the user may choose the discard it and connect only
External ROM.
This may happen due to several reasons.
The program stored in the Internal ROM may have become invalid or outdated, or the system may
need to be upgraded etc.
Such systems use only External ROM, and the Internal ROM is discarded.
Here we can connect up to 64 KB of External ROM.
All addresses from 0000H… FFFFH will be accessed from External ROM.
But do keep in mind, that the Internal ROM is still present in 8051.
We need to clearly indicate to 8051 that the Internal ROM must be ignored and every address from
0000H… FFFFH must be accessed externally. This is indicated by us to 8051 using EA .
By making EA = 0, we inform 8051 that the Internal ROM must be discarded and all ROM must be
accessed externally.
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Note: Use of EA pin of 8051.
The EA pin of 8051 decides whether the Internal ROM will be used or not.
If the Internal ROM has to be used we must make EA = 1.
Now 8051 will Access the internal ROM for all addresses from 0000H to 0FFFH and will only access
external ROM for addresses 1000H and beyond.
But if EA = 0, then the Internal ROM is completely discarded.
Now 8051 will access the External ROM for all addresses from 0000H to FFFFH, hence discarding the
internal ROM.
8051 checks EA pin during every ROM operation where the address is 0000H… 0FFFH.
If EA = 1, this location is accessed from internal ROM.
If EA = 0, this location is accessed from external ROM.
If the address is 1000H or more, 8051 does not check EA as this location can only be present in
External ROM.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
STRUCTURE OF INTERNAL RAM OF 8051
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8051 has a 128 Bytes of internal RAM.
These are 128 locations of 1 Byte each.
The address range is 00H… 7FH.
This RAM is used for storing data.
It is divided into three main parts: Register Banks, Bit addressable area and a general purpose
area.
REGISTER BANKS
1) The first 32 locations (Bytes) of the Internal RAM from 00H… 1FH, are used by the
programmer as general purpose registers.
2) Having so many general purpose registers makes programming easier and faster.
3) But as a downside, this also vastly increases the number of opcodes (refer my class lectures
for detailed understanding of this).
4) Hence the 32 registers are divided into 4 banks, each having 8 Registers R0… R7.
5) The first 8 locations 00H… 07H are registers R0… R7 of bank 0.
6) Similarly locations 08H… 0FH are registers R0… R7 of bank 1 and so on.
A register can be addressed using its name, or by its address.
Eg: Location 00H can be accessed as R0, if Bank 0 is the active bank.
MOV A, R0; “A” register gets data from register R0.
It can also be accessed as Location 00H, irrespective of which bank is the active bank.
MOV A, 00H; “A” register gets data from Location 00H.
7) The appropriate bank is selected by the RS1, RS0 bits of PSW.
Since PSW is available to the programmer, any Bank can be selected at run-time.
8) Bank 0 is selected by default, on reset.
BIT ADDRESSABLE AREA
1) The next 16-bytes of RAM, from 20H… 2FH, is available as Bit Addressable Area.
2) We can perform ordinary byte operations on these locations, as well as bit operations.
#Please refer Bharat Sir's Lecture Notes for detailed explanation on this ...
3) As each location has 8-bits, we have a total of è 16 × 8 = 128 Addressable Bits.
4) These bits can be addressed using their individual address 00H … 7FH.
SETB 00H; Will store a “1” on the LSB of location 20H
CLR 07H; Will store a “0” on the MSB of location 20H
5) Normal “BYTE” operations can also be performed at the addresses: 20H … 2FH.
MOV 20H, #00H; Will store a “0” on all 8-bits of location 20H.
6) Here is something very interesting to know and will also help you understand further topics.
The entire internal RAM is of 128 bytes so the address range is 00H… 7FH.
The bit addressable area has 128 bits so its bit addresses are also 00h… 7FH.
7) This means every address 00H… 7FH can have two meanings, it could be a byte address or a
bit address.
8) This does not lead to any confusion, because the instruction in which we use the address,
will clearly indicate whether it is a bit operation or a byte operations.
SETB, CLR etc. are bit ops whereas ADD, SUB etc. are byte operations.
9) SETB 00H;
This is a bit operation.
It will make Bit location 00H contain a value “1”.
10) MOV A, 00H; This is a byte operation.
“A” register will get 8-bit data from byte location 00H.
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GENERAL PURPOSE AREA
1) The general-purpose area ranges from location 30H … 7FH.
2) This is an 80-byte area which can be used for general data storage.
STACK OF 8051
4)
5)
6)
7)
Another important element of the Internal RAM is the Stack.
Stack is a set of memory locations operating in Last In First Out (LIFO) manner.
It is used to store return addresses during ISRs and also used by the programmer to store
data during programs.
In 8051, the Stack can only be present in the Internal RAM.
This is because, SP which is an 8-bit register, can only contain an 8-bit address and
External RAM has 16-bit address. (#Viva)
On reset SP gets the value 07H.
Thereafter SP is changed by every PUSH or POP operation in the following manner:
PUSH:
SP ç SP + 1
[SP] ç New data
8)
9)
POP:
Data ç [SP]
SP ç SP – 1
The reset value of SP is 07H because, on the first PUSH, SP gets incremented and then
data is pushed on to the stack. This means the very first data will be stored at location 08H.
This does not affect the default bank (0) and still gives the stack, the maximum space to
grow. (#Viva)
Before Push
operation
08
07
06
05
04
03
02
01
00
SP è
xx
Bank 0
SP è
After Push
operation
08
07
06
05
04
03
02
01
00
Data
xx
Bank 0
1)
2)
3)
10) The programmer can relocate the stack to any desired location by simply putting a new
value into SP register.
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SPECIAL FUNCTION REGISTERS (SFRS) OF 8051
8051 has 21, 8-bit Special Function registers.
NAME
*
Used for holding data and
status during Programming
A
B*
PSW*
SP
DPL
DPH
P0*
P1*
P2*
P3*
SCON*
SBUF
TCON*
TMOD
TL0
TL1
TH0
TH1
IE*
IP*
PCON
-
Used in instructions to
point to memory
locations.
-
Used by the respective
I/O Ports
-
Used by the Serial Port
-
Used for Timer Control
-
Used for Interrupt
Control
-
Used for Power Control
*
FUNCTION
BYTE ADDRESS
BIT ADDRESS
0E0H
0F0H
0D0H
81H
82H
83H
80H
90H
0A0H
0B0H
98H
99H
88H
89H
8AH
8BH
8CH
8DH
0A8H
0B8H
87H
0E7H…0E0H
0F7H…0F0H
0D7H…0D0H
NA
NA
NA
87H…80H
97H…90H
0A7H…0A0H
0B7H…0B0H
9FH…98H
NA
8FH…88H
NA
NA
NA
NA
NA
0AFH…0A8H
0BFH…0B8H
NA
Accumulator
Arithmetic
Program Status Word
Stack Pointer
Address External Memory
Address External Memory
I/O Port latch
I/O Port latch
I/O Port latch
I/O Port latch
Serial Port Control
Serial Port Data Buffer
Timer/Counter Control
Timer/Counter Mode Control
Timer 0 Low Byte
Timer 1 Low Byte
Timer 0 High Byte
Timer 1 High Byte
Interrupt Enable
Interrupt Priority
Power Control
-
Means the SFR is Bit Addressable
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SFRs are 8-bit registers.
Each SFR has its own special function.
2) They are placed inside the Microcontroller. #Please refer Bharat Sir's Lecture Notes for this ...
3) They are used by the programmer to perform special functions like controlling the timers, the
serial port, the I/O ports etc.
4) As SFRs are available to the programmer, we will use them in instructions.
This causes another problem.
SFRs are registers after all, and hence using them would tremendously increase the number of
opcodes. (Refer to Bharat Sir’s Lecture notes for more on this)
5) To reduce the number of opcodes, SFRs are allotted addresses.
These addresses must not clash with any other addresses of the existing memories.
6) Incidentally, the internal RAM is of 128 bytes and uses addresses only from 00H… 7FH.
This gives an entire range of addresses from 80H… FFH completely unused and can be freely
allotted to the SFRs.
7) Hence SFRs are allotted addresses from 80H… FFH.
It is not a co-incidence that these addresses are free. It is how 8051 design was planned. The
Internal RAM was restricted to 128 bytes instead of 256 bytes so that these addresses are free
for SFRs.
8) Moreover, some SFRs are bit addressable, like Port 0.
All 8-bits can be individually accessed from P0.0… P0.7, by instructions like SETB, CLR etc.
But again, this will again tremendously increase the number of opcodes.
9) To avoid this problem, even the bits of the SFRs are allotted addresses.
These are bit addresses, which are different from byte addresses.
These bit addresses must not clash with those of the bit addressable area of the Internal RAM.
Amazingly, even the bit addresses in the Internal RAM are 00H… 7FH (again 128 bits), keeping
bit addresses 80H… FFH free to be used by the SFR bits.
10) So bit addresses 80H… FFH are allotted to the bits of various SFRs.
(Watch Bharat Acharya Education, videos on YouTube for more on this)
11) Port 0 has a byte address of 80H and its bit addresses are from 80H… 87H.
A byte operation at address 80H will affect entire Port0.
E.g.:: MOV A, P0; this refers to Byte address 80H that’s whole Port 0.
12) A bit operation at 80H will affect only P0.0.
E.g.:: SETB P0.0; this refers to bit address 80H that’s Port0.0
1)
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ADDRESSING MODES OF 8051
Addressing Modes is the manner in which operands are given in the instruction.
8051 supports the following 5 addressing modes:
1) IMMEDIATE ADDRESSING MODE
In this addressing mode, the Data is given in the Instruction itself.
We put a "#" symbol, before the data, to identify it as a data value and not as an address.
Eg:
MOV A, #35H
; A ç 35H
MOV DPTR, #3000H ; DPTR ç 3000H
2) REGISTER ADDRESSING MODE
In this addressing mode, Data is given by a Register in the instruction.
The permitted registers are A, R7 … R0 of each memory bank.
Note: Data transfer between two RAM registers is not allowed.
Eg:
MOV A, R0
; A ç R0 … If R0 = 25H, then A gets the Value 25H.
MOV R5, A
; R5 ç A
MOV Rx, Ry
; NOT ALLOWED. That’s because this would allow 64 combinations of registers
; As registers invite opcodes, this would need 64 opcodes!
3) DIRECT ADDRESSING MODE
Here, the address of the operand is given in the instruction.
Only Internal RAM addresses (00H…7FH) and SFR addresses (from 80H to FFH) allowed.
Eg:
MOV A, 35H
; A ç Contents of RAM location 35H
MOV A, 80H
; A ç Contents of Port 0 (SFR at address 80H)
MOV 20H, 30H
; [20H] ç [30H]
; i.e. Location 20H gets the contents of Location 30H
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4) INDIRECT ADDRESSING MODE
Here, the address of the operand is given in a register.
Internal RAM and External RAM can be accessed using this mode.
The advantage of giving an address using a register is that we can increment the address in a
loop, by simply incrementing the register, and hence access a series of locations.
INTERNAL RAM: (8-BIT ADDRESS GIVEN BY R0 OR R1)
ONLY R1 or R0, called as Data Pointers, can be used to specify address (00H … 7FH).
An "@" sign is present before the register to indicate that the register is giving an address.
Eg:
MOV A, @R0
; A ç [R0]
; i.e. A ç Contents of Internal RAM Location whose address is given by R0.
; if R0 = 25H, then A gets the contents of Location 25H from Internal RAM
MOV @R1, A
; [R1] ç A i.e. Internal RAM Location pointed by R1 gets value of A.
EXTERNAL RAM: (16 BIT ADDRESS GIVEN BY DPTR)
For the External RAM, address is provided by R1 or R0, or by DPTR.
If DPTR is used to give an address, then the full 64KB range of External RAM from 0000H…
FFFFH is available. This is because DPTR is 16-bit and 216 = 65536.
An "X" is present in the instruction, to indicate External RAM.
Eg:
MOVX A, @DPTR
; A ç [DPTR]^
; A gets the contents of External RAM Location whose address is given by DPTR
; If DPTR = 2000H, then A gets contents of Location 2000H from External RAM
MOVX @DPTR, A
; [DPTR]^ ç A
; i.e. A is stored at the External RAM Location whose address is given by DPTR
EXTERNAL RAM: (8 BIT ADDRESS GIVEN BY R0 OR R1)
If R0 or R1 is used to give an address, then only the first 256 locations of External RAM is
available from 0000 H to 00FF H. This is because R0 or R1 are 8-bit and 28 = only 256.
Eg:
MOVX A, @R0
; A ç [R0]^
; i.e. A gets the contents of External RAM Location whose address is given by R0
; If R0 = 25H, then A gets contents of Location 0025H from the External RAM
MOVX @R1, A
; [R1]^ ç A
; i.e. A is stored at the External RAM Location whose address is given by R1
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5) INDEXED ADDRESSING MODE
This mode is used to access data from the Code memory (Internal ROM or External ROM).
In this addressing mode, address is indirectly specified as a “SUM” of (A and DPTR) or (A and
PC).
This is very useful because ROM contains permanent data which is stored in the form of Look Up
tables. To access a Look Up table, address is given as a SUM or two registers, where one acts as
the base and the other acts as the index within the table.
A "C" is present in such instructions, to indicate Code Memory.
Eg:
MOVC A, @A+DPTR ; A ç Contents of a ROM Location pointed by A+DPTR.
; If DPTR = 0400H and A = 05H,
; then A gets the contents of ROM Location whose address is 0405 H.
MOVC A, @A+PC
; A ç Contents of a ROM Location pointed by A+PC.
The same instruction may operate on Internal or External ROM, depending upon the address and
on the value of EA pin of 8051.
If the address is in the range of 0000… 0FFFH, then EA pin will decide if it operates on Internal
ROM or External ROM. IF
EA = 0, External ROM else Internal ROM.
If Address is 1000H and more, it will certainly be External ROM.
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ARITHMETIC
INSTRUCTIONS
Here you will see operations like:
• Addition
• Addition with Carry
• Subtraction with Borrow
• Increment
• Decrement
• Multiply
• Divide
• Decimal Adjustment after addition.
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1) ADD A, #n
| “Add”
Example:
ADD A, #25H; A ç A + 25H
Operation:
Adds A Register with Immediate data.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
Please do remember to check for carry after performing addition.
Carry flag is checked by instructions like JC and JNC.
2) ADD A, Rr
| “Add”
Example:
ADD A, R0; A ç A + R0
Operation:
Adds A Register with the value of a RAM register.
Stores the result in A Register.
No of cycles required: 1
3) ADD A, addr
| “Add”
Example:
ADD A, 25H; A ç A + [25H]
Operation:
Adds A Register with the contents of the address.
Stores the result in A Register.
No of cycles required: 1
4) ADD A, @Rp
| “Add”
Example:
ADD A, @R0; A ç A + [R0]
Operation:
Adds A Register with the contents of the location pointed by the register.
Result is stored in A Register.
If R0 = 20H and Location 20H contains value 35H, then 35H will be added to A register.
No of cycles required: 1
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5) ADDC A, #n
| “Add with carry”
Example:
ADDC A, #25H; A ç A + 25H + Carry Flag
Operation:
Adds A Register with Immediate data along with the Carry of the previous addition which is present in the Carry Flag.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
ADDC is used when we want to ADD two large numbers like 16 bit numbers.
First we add the lower bytes using ADD instruction.
Then we add the higher bytes using ADDC instruction.
If the Lower byte has produced a Carry, then CF will be 1.
This Carry will be added into the higher bytes.
Please refer to our classroom example of adding 12FFH + 0001H = 1300H.
6) ADDC A, Rr
| “Add with carry”
Example:
ADDC A, R0; A ç A + R0 + Carry Flag
Operation:
Adds A Register with the value of a RAM register along with the Carry of the previous addition.
Stores the result in A Register.
No of cycles required: 1
7) ADDC A, addr
| “Add with carry”
Example:
ADDC A, 25H; A ç A + [25H] + Carry Flag
Operation:
Adds A Register with the contents of the address along with the Carry of the previous addition.
Stores the result in A Register.
No of cycles required: 1
8) ADDC A, @Rp
| “Add with carry”
Example:
ADDC A, @R0; A ç A + [R0] + Carry Flag
Operation:
Adds A Register with the contents of the location pointed by the register along with the Carry of the previous addition.
Result is stored in A Register.
No of cycles required: 1
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9) SUBB A, #n
| “Subtract with borrow”
Example:
SUBB A, #25H; A ç A - 25H - Carry Flag
Operation:
Performs A Register – Immediate data – Carry Flag (Carry Flag holds the borrow of the previous subtraction).
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
SUBB is used when we want to Subtract two large numbers like 16 bit numbers.
First we Subtract the lower bytes.
If the Lower byte subtraction needs a borrow, then CF will be 1.
This Carry will be subtracted from the higher bytes.
It is important to realize that there is no ordinary SUB instruction.
Hence if we want to perform simple 8-bit subtraction, we still have to use SUBB instruction.
If we don’t want Carry flag to interfere with the operation,
We must first clear the carry flag using CLR C instruction before using SUBB.
10) SUBB A, Rr
| “Subtract with borrow”
Example:
SUBB A, R0; A ç A - R0 - Carry Flag
Operation:
Performs A Register – value of RAM register – Carry Flag (Carry Flag holds the borrow of the previous subtraction).
Stores the result in A Register.
No of cycles required: 1
11) SUBB A, addr
| “Subtract with borrow”
Example:
SUBB A, 25H; A ç A - [25H] - Carry Flag
Operation:
Performs A Register – contents of memory address – Carry Flag (Carry Flag holds the borrow of the previous subtraction).
Stores the result in A Register.
No of cycles required: 1
12) SUBB A, @Rp
| “Subtract with borrow”
Example:
SUBB A, @R0; A ç A - [R0] - Carry Flag
Operation:
Performs A Register – Contents of the memory location pointed by the register – Carry Flag.
Result is stored in A Register.
No of cycles required: 1
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13) INC A
| “Increment”
Example:
INC A; A ç A + 1
Operation:
Increments the value of A register. Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
During INC A, if A was FFH, it will roll over to 00H.
14) INC Rr
| “Increment”
Example:
INC R0; R0 ç R0 + 1
Operation:
Increments the value of a RAM register. Stores the result in the same RAM Register.
No of cycles required: 1
15) INC addr
| “Increment”
Example:
INC 25H; [25H] ç [25H] + 1
Operation:
Increments the contents of a memory address. Stores the result back in the same location.
No of cycles required: 1
16) INC @Rp
| “Increment”
Example:
INC @R0; [@R0] ç [@R0] + 1
Operation:
Increments the contents of a memory location pointed by R0. Will store the result back at the same location.
No of cycles required: 1
17) INC DPTR
| “Increment”
Example:
INC DPTR; DPTR ç DPTR + 1
Operation:
Increments the 16-bit value of DPTR register. Stores the result in DPTR Register.
No of cycles required: 2
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18) DEC A
| “Decrement”
Example:
DEC A; A ç A – 1
Operation:
Decrements the value of A register.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
During DEC A, if A was 00H, it will roll back to FFH.
That’s because 00H – 1 = – (01H) which is FFH in 2’s complement form.
Please refer to classroom explanation for more clarity on this.
Also, do remember, DEC DPTR does not exists.
If you need to decrement DPTR, you can do it by individually decrementing DPL and DPH.
First decrement DPL. If it rolls back from 00H to FFH, then also decrement DPH.
E.g.:: 1300H – 1 = 12FFH.
19) DEC Rr
| “Decrement”
Example:
DEC R0; R0 ç R0 – 1
Operation:
Decrements the value of a RAM register.
Stores the result in the same RAM Register.
No of cycles required: 1
20) DEC addr
| “Decrement”
Example:
DEC 25H; [25H] ç [25H] – 1
Operation:
Decrements the contents of a memory address.
Stores the result back in the same location.
No of cycles required: 1
21) DEC @Rp
| “Decrement”
Example:
DEC @R0; [@R0] ç [@R0] – 1
Operation:
Decrements the contents of a memory location pointed by R0.
Will store the result back at the same location.
No of cycles required: 1
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22) MUL AB
| “Multiply A and B”
Example:
MUL AB; B (Higher) . A (Lower) ç A x B
Operation:
Multiples the 8-bit values of A register and B register.
Stores the 16 bit result in B and A Registers.
B register gets the Higher Byte, A register gets the Lower Byte.
No of cycles required: 4
23) DIV AB
| “Divide A by B”
Example:
DIV AB; B (Remainder) . A (Quotient) ç A ÷ B
Operation:
Divides the 8-bit value of A register by the 8-bit value of B register.
Stores the result in B and A Registers.
B register gets the Remainder, A register gets the Quotient.
No of cycles required: 4
IMPORTANT TIP FROM BHARAT ACHARYA
During DIV AB, if B register is 00H, then the instruction will be aborted.
A and B registers will contain garbage values after the operation.
This is indicated to the programmer by the OVERFLOW FLAG.
If Overflow Flag becomes “1” after the operation, it simply means division by 0 was attempted.
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24) DA A
| “Decimal Adjust after Addition”
Example:
DA A;
Operation:
It is used when we want to add two decimal numbers (BCD numbers).
We first enter the decimal numbers, as if they are Hexadecimal.
We add them by normal ADD instruction.
The answer is then adjusted using DA A instruction.
DA A always works on A Register only.
It first checks the Lower nibble of A Register.
If Lower nibble is > 9 or Aux Carry is 1, then ADD 06H
It then checks the Higher nibble of A Register.
If Higher nibble is > 9 or Carry Flag is 1, then ADD 60H
The final answer will be stored in A and Carry flag.
Please refer numerous examples discussed in the class. For doubts call #BharatSir @9820408217
Assume we want to add 25d + 25d, the result must obviously be 50d.
We enter the numbers as if they are hexadecimal, and add them by normal ADD instruction.
MOV A, #25H
ADD A, #25H
; A ç 25
; A ç 4A
Now we perform the adjustment using DAA instruction.
; Aç 50
DA A
24H
26H
28H
50H
80H
99H
+ 25H
+ 26H
+ 28H
+ 50H
+ 80H
+ 99H
After ADD
= 49H
After ADD
= 4CH
After ADD
= 50H
After ADD
= A0H
After ADD
= 100H
After ADD
= 132H
After DA A
è 49
After DA A
è 52
After DA A
è 56
After DA A
è 100
After DA A
è 160
After DA A
è 198
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
Please get this clear, “DA A does not convert any number from Hexadecimal to Decimal”.
It simply makes the addition work like decimal addition.
DA A can only be used “After performing an Addition” operation.
VIVA question: Put 25H in A register and show the working of DA A.
Reply: Invalid question! We must first perform addition. Simply putting 25H in A and doing DA A is absurd.
VIVA question: 29H and 3CH and show the working of DA A.
Reply: Invalid question! DA A is used to Add decimal numbers. 3C is not decimal!
Also, do remember, DA A is an adjustment for Addition. So there is always a chance of a carry.
If the answer exceeds 99, the lower two digits will be in A and the highest digit will be Carry Flag.
If the answer is 160, A will contain 60 and Carry Flag will get 1.
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LOGIC
INSTRUCTIONS
Here you will see operations like:
• AND
• OR
• XOR
• Clear
• Complement
• Rotate
• Rotate with Carry
• Swap
• No Operation
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25) ANL A, #n
| “AND logically”
Example:
ANL A, #25H; A ç A AND 25H
Operation:
Logically ANDs the value of A register with the immediate data.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
AND is used to CLEAR any bit of a register.
If we want to clear any bit, we must AND that particular bit with “0” and the remaining bits with “1”.
This is because, if we AND anything (0 or 1) with 0, it becomes 0.
But if we AND anything (0 or 1) with 1, it remains the same.
Suppose we want to CLEAR the lower nibble of A register.
Assume: A register is 95H è 1001 0101
AND this register with the number F0H è 1111 0000
As a result A will become 90H è 1001 0000
Please refer examples form Bharat Academy lecture notes for more clarity on this.
26) ANL A, Rr
| “AND logically”
Example:
ANL A, R0; A ç A AND R0
Operation:
Logically ANDs the value of A register with the value of RAM register.
Stores the result in A Register.
No of cycles required: 1
27) ANL A, addr
| “AND logically”
Example:
ANL A, 25H; A ç A AND [25H]
Operation:
Logically ANDs the value of A register with contents of the address.
Stores the result in A Register.
No of cycles required: 1
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28) ANL A, @Rp
| “AND logically”
Example:
ANL A, @R0; A ç A AND [R0]
Operation:
Logically ANDs the value of A reg. with contents of the location pointed by the reg.
Stores the result in A Register.
No of cycles required: 1
29) ANL addr, A
| “AND logically”
Example:
ANL 25H, A; [25H] ç [25H] AND A
Operation:
Logically ANDs contents of the address with the value of A register.
Stores the result at the address.
No of cycles required: 1
30) ANL addr, #n
| “AND logically”
Example:
ANL 25H, #30H; [25H] ç [25H] AND 30H
Operation:
Logically ANDs contents of the address with the immediate data.
Stores the result at the address.
No of cycles required: 2
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31) ORL A, #n
| “OR logically”
Example:
ORL A, #25H; A ç A OR 25H
Operation:
Logically ORs the value of A register with the immediate data.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
OR is used to SET any bit of a register.
If we want to set any bit, we must OR that particular bit with “1” and the remaining bits with “0”.
This is because, if we OR anything (0 or 1) with 1, it becomes 1.
But if we OR anything (0 or 1) with 0, it remains the same.
Suppose we want to SET the lower nibble of A register.
Assume: A register is 95H è 1001 0101
OR this register with the number 0FH è 0000 1111
As a result A will become 9FH è 1001 1111
Please refer examples form Bharat Academy lecture notes for more clarity on this.
32) ORL A, Rr
| “OR logically”
Example:
ORL A, R0; A ç A OR R0
Operation:
Logically ORs the value of A register with the value of RAM register.
Stores the result in A Register.
No of cycles required: 1
33) ORL A, addr
| “OR logically”
Example:
ORL A, 25H; A ç A OR [25H]
Operation:
Logically ORs the value of A register with contents of the address.
Stores the result in A Register.
No of cycles required: 1
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34) ORL A, @Rp
| “OR logically”
Example:
ORL A, @R0; A ç A OR [R0]
Operation:
Logically ORs the value of A reg. with contents of the location pointed by the reg.
Stores the result in A Register.
No of cycles required: 1
35) ORL addr, A
| “OR logically”
Example:
ORL 25H, A; [25H] ç [25H] OR A
Operation:
Logically ORs contents of the address with the value of A register.
Stores the result at the address.
No of cycles required: 1
36) ORL addr, #n
| “OR logically”
Example:
ORL 25H, #30H; [25H] ç [25H] OR 30H
Operation:
Logically ORs contents of the address with the immediate data.
Stores the result at the address.
No of cycles required: 2
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37) XRL A, #n
| “Ex-OR logically”
Example:
XRL A, #25H; A ç A XOR 25H
Operation:
Logically XORs the value of A register with the immediate data.
Stores the result in A Register.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
XOR is used to COMPLEMENT any bit of a register.
If we want to complement any bit, we must XOR that bit with “1” and the remaining bits with “0”.
This is because, if we XOR anything (0 or 1) with 1, it gets complemented.
But if we XOR anything (0 or 1) with 0, it remains the same.
Suppose we want to COMPLEMENT the lower nibble of A register.
Assume: A register is 95H è 1001 0101
XOR this register with the number 0FH è 0000 1111
As a result A will become 9AH è 1001 1010
Please refer examples form Bharat Academy lecture notes for more clarity on this.
38) XRL A, Rr
| “Ex-OR logically”
Example:
XRL A, R0; A ç A XOR R0
Operation:
Logically XORs the value of A register with the value of RAM register.
Stores the result in A Register.
No of cycles required: 1
39) XRL A, addr
| “Ex-OR logically”
Example:
XRL A, 25H; A ç A XOR [25H]
Operation:
Logically XORs the value of A register with contents of the address.
Stores the result in A Register.
No of cycles required: 1
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40) XRL A, @Rp
| “Ex-OR logically”
Example:
XRL A, @R0; A ç A XOR [R0]
Operation:
Logically XORs the value of A reg. with contents of the location pointed by the reg.
Stores the result in A Register.
No of cycles required: 1
41) XRL addr, A
| “Ex-OR logically”
Example:
XRL 25H, A; [25H] ç [25H] XOR A
Operation:
Logically XORs contents of the address with the value of A register.
Stores the result at the address.
No of cycles required: 1
42) XRL addr, #n
| “Ex-OR logically”
Example:
XRL 25H, #30H; [25H] ç [25H] XOR 30H
Operation:
Logically XORs contents of the address with the immediate data.
Stores the result at the address.
No of cycles required: 2
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43) RL A
| “Rotate Left”
Example:
RL A; A ç A register rotated left by one position
Operation:
Rotates the bits of A register in the left direction by one position.
Each bit goes one position to the left.
MSB goes to the Carry flag as well as to the LSB.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
Rotates are used to determine the value of any bit, in A register.
To know the value of a bit, Rotate the register as many times, so that the bit comes into Carry Flag.
Now check the carry flag to know if your desired bit was 0 or 1.
44) RR A
| “Rotate Right”
Example:
RR A; A ç A register rotated right by one position
Operation:
Rotates the bits of A register in the right direction by one position.
Each bit goes one position to the right.
LSB goes to the Carry flag as well as to the MSB.
No of cycles required: 1
45) RLC A
| “Rotate Left, with Carry”
Example:
RLC A; A ç A register rotated left by one position along with the carry flag
Operation:
Rotates the bits of A register in the left direction by one position along with the carry flag.
Each bit goes one position to the left.
MSB goes to the Carry flag and Carry Flag goes to the LSB.
No of cycles required: 1
46) RRC A
| “Rotate Right, with Carry”
Example:
RRC A; A ç A register rotated right by one position along with the carry flag
Operation:
Rotates the bits of A register in the right direction by one position along with the carry flag.
Each bit goes one position to the right.
LSB goes to the Carry flag and Carry Flag goes to the MSB.
No of cycles required: 1
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47) CPL A
| “Complement A”
Example:
CPL A; A ç One’s complement of A.
Operation:
Complements the value of A register.
Works just like a Not gate.
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
CPL is used as a NOT operation.
If we do CPL after AND, it works like NAND.
CPL after OR, it works like NOR.
CPL after XOR, it works like XNOR.
48) CLR A
| “Clear A”
Example:
CLR A; A ç 00H.
Operation:
Clears the entire A register and makes it 00H.
No of cycles required: 1
49) SWAP A
| “SWÃP A”
Example:
SWAP A; A Lower Nibble çè A Higher Nibble
Operation:
Interchanges the Nibbles of A register.
If A register was 35H it will become 53H.
It is as good as rotating A register four times.
No of cycles required: 1
50) NOP
| “No operation”
Example:
NOP; No operation. PC simply becomes PC + 1.
Operation:
This instruction performs no operation.
It is typically used to produce a delay.
No of cycles required: 1
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BOOLEAN
INSTRUCTIONS
Here you will see bit wise operations like:
• Set
• Clear
• Complement
• Movement between a bit and Carry flag
• Logical AND
• Logical OR
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IMPORTANT TIP FROM BHARAT ACHARYA
These are bit wise operations.
“b” represents any bit from the bit addressable area of the internal RAM having bit addresses 00H… 7FH.
“b” can also be a bit of any bit addressable SFR like PSW.3 or P0.7 etc.
100) SETB C
| “SET the carry Flag”
Example:
SETB C; Carry Flag ç 1
Operation:
This instruction is used to SET the Carry Flag.
This makes Carry Flag ç 1
No of cycles required: 1
101) CLR C
| “CLEAR the carry Flag”
Example:
CLR C; Carry Flag ç 1
Operation:
This instruction is used to CLEAR the Carry Flag.
This makes Carry Flag ç 0
No of cycles required: 1
102) CPL C
| “COMPLEMENT the carry Flag”
Example:
CPL C; Carry Flag ç complement of Carry Flag
Operation:
This instruction is used to COMPLEMENT the Carry Flag.
This makes Carry Flag ç Complement of Carry Flag
No of cycles required: 1
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IMPORTANT TIP FROM BHARAT ACHARYA
These are bit wise operations.
“b” represents any bit from the bit addressable area of the internal RAM having bit addresses 00H… 7FH.
“b” can also be a bit of any bit addressable SFR like PSW.3 or P0.7 etc.
103) SETB b
| “SET a bit”
Example:
SETB P0.2; P0.2 ç 1
SETB 00H; bit location 00H of Internal RAM gets the value ç 1
Operation:
This instruction is used to SET the any bit “b”.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
No of cycles required: 1
104) CLR b
| “CLEAR a bit”
Example:
CLR P0.2; P0.2 ç 0
CLR 00H; bit location 00H of Internal RAM gets the value ç 0
Operation:
This instruction is used to CLEAR the any bit “b”.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
No of cycles required: 1
105) CPL b
| “COMPLEMENT a bit”
Example:
CPL P0.2; P0.2 gets complemented
CPL 00H; bit location 00H of Internal RAM gets the value gets complemented
Operation:
This instruction is used to COMPLEMENT the any bit “b”.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
No of cycles required: 1
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106) MOV C, b
| “Move a bit into the Carry Flag”
Example:
MOV C, P0.2; Carry Flag ç P0.2
MOV C, 25H; Carry Flag ç [25H] bit address
Operation:
This instruction is used to copy the value of some bit into the Carry Flag.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
No of cycles required: 1
IMPORTANT TIP FROM BHARAT ACHARYA
There is a clear difference between the following two instructions:
MOV A, 25H; This refers to Byte Location 25H.
We can make this conclusion because A is an 8-bit register.
MOV C, 25H; This refers to Bit Location 25H.
We can make this conclusion because C is the Carry Flag.
107) MOV b, C
| “Move a from Carry flag into a bit”
Example:
MOV P0.2, C; P0.2 ç Carry Flag
MOV 25H, C; [25H] bit address ç Carry Flag
Operation:
This instruction is used to copy the value of the Carry Flag into some bit.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
No of cycles required: 2
IMPORTANT TIP FROM BHARAT ACHARYA
There is a clear difference between the following two instructions:
MOV 25H, A; This refers to Byte Location 25H.
We can make this conclusion because A is an 8-bit register.
MOV 25H, C; This refers to Bit Location 25H.
We can make this conclusion because C is the Carry Flag.
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108) ANL C, b
| “AND Carry Flag with a bit”
Example:
ANL C, P0.2; Carry Flag ç Carry Flag AND P0.2
ANL C, 25H; Carry Flag ç Carry Flag AND [25H] bit address
Operation:
This instruction is used to AND the value of some bit with the Carry Flag.
It can be a bit from the bit addressable area of the Internal RAM having bit address 00H… 7FH
It can also be a bit from a bit addressable SFR like TCON.4
The result will be stored in the Carry Flag
It is interesting to note that, in bit wise operations, Carry Flag acts as the “Accumulator”.
No of cycles required: 2
109) ANL C, /b
| “AND Carry Flag with the COMPLEMENT of a bit”
Example:
ANL C, P0.2; Carry Flag ç Carry Flag AND (NOT) P0.2
ANL C, 25H; Carry Flag ç Carry Flag AND (NOT) [25H] bit address
Operation:
This instruction is used to AND the value of Carry Flag with the COMPLEMENT of a bit.
No of cycles required: 2
108) ORL C, b
| “OR Carry Flag with a bit”
Example:
ORL C, P0.2; Carry Flag ç Carry Flag OR P0.2
ORL C, 25H; Carry Flag ç Carry Flag OR [25H] bit address
Operation:
This instruction is used to OR the value of some bit with the Carry Flag.
No of cycles required: 2
109) ORL C, /b
| “OR Carry Flag with the COMPLEMENT of a bit”
Example:
ORL C, P0.2; Carry Flag ç Carry Flag OR (NOT) P0.2
ORL C, 25H; Carry Flag ç Carry Flag OR (NOT) [25H] bit address
Operation:
This instruction is used to OR the value of Carry Flag with the COMPLEMENT of a bit.
No of cycles required: 2
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DATA TRANSFER
INSTRUCTIONS
Here you will see operations like:
• MOV
• MOVX
• MOVC
• PUSH
• POP
• Exchange
• Exchange Digit
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51) MOV A, #n
| “Move”
Example:
MOV A, #25H; A ç 25H
Operation:
A Register gets the value of the Immediate data.
No of cycles required: 1
52) MOV A, Rr
| “Move”
Example:
MOV A, R0; A ç R0
Operation:
A Register gets the value of a RAM register.
The value remains in the RAM register and is also copied into A register.
No of cycles required: 1
53) MOV A, addr
| “Move”
Example:
MOV A, 25H; A ç [25H]
Operation:
A Register gets the contents of the address.
No of cycles required: 1
54) MOV A, @Rp
| “Move”
Example:
MOV A, @R0; A ç [R0]
Operation:
A Register gets the contents of the location pointed by the register.
If R0 = 20H and Location 20H contains value 35H, then 35H will be copied into to A register.
No of cycles required: 1
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55) MOV Rr, A
| “Move”
Example:
MOV R0, A; R0 ç A
Operation:
RAM Register gets the value of A Register.
No of cycles required: 1
56) MOV Rr, #n
| “Move”
Example:
MOV R0, #25H; R0 ç 25H
Operation:
RAM Register gets the value of the Immediate Data.
No of cycles required: 1
57) MOV Rr, addr
| “Move”
Example:
MOV R0, 25H; R0 ç [25H]
Operation:
RAM Register gets the contents of the address.
No of cycles required: 2
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58) MOV addr, A
| “Move”
Example:
MOV 25H, A; [25H] ç A
Operation:
The RAM location gets the value of A Register.
No of cycles required: 1
59) MOV addr, #n
| “Move”
Example:
MOV 25H, #25H; [25H] ç 25H
Operation:
The RAM location gets the value of the Immediate Data.
No of cycles required: 2
60) MOV addr, Rr
| “Move”
Example:
MOV 25H, R0; [25H] ç R0
Operation:
The RAM location gets the contents of the RAM register.
No of cycles required: 2
61) MOV addr1, addr2
| “Move”
Example:
MOV 30H, 25H; [30H] ç [25H]
Operation:
The RAM location 1 gets the contents of RAM location 2.
No of cycles required: 2
62) MOV addr, @Rp
| “Move”
Example:
MOV 25H, @R0; [25H] ç [R0]
Operation:
The RAM location gets the contents of the address pointed by the register.
No of cycles required: 2
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63) MOV @Rp, A
| “Move”
Example:
MOV @R0, A; [R0] ç A
Operation:
The RAM location pointed by the register gets the value of A Register.
No of cycles required: 1
64) MOV @Rp, #n
| “Move”
Example:
MOV @R0, #25H; [R0] ç 25H
Operation:
The RAM location pointed by the register gets the value of the Immediate Data.
No of cycles required: 1
65) MOV @Rp, addr
| “Move”
Example:
MOV @R0, 25H; [R0] ç [25H]
Operation:
The RAM location pointed by the register gets the contents of the address.
No of cycles required: 2
66) MOV DPTR, #nn
| “Move”
Example:
MOV DPTR, #2000H; DPTR ç 2000H
Operation:
DPTR register gets the 16 bit Immediate Data given in the instruction.
No of cycles required: 2
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67) MOVX A, @Rp
| “Move Ex”
Example:
MOVX A, @R0; A ç [R0]^
Operation:
A Register gets the data from the location pointed by R0 in the External RAM.
If R0 = 20H then A Register gets data from External RAM location 0020H.
No of cycles required: 2
68) MOVX A, @DPTR
| “Move Ex”
Example:
MOVX A, @DPTR; A ç [DPTR]^
Operation:
A Register gets the data from the location pointed by DPTR in the External RAM.
If DPTR = 4000H then A Register gets data from External RAM location 4000H.
No of cycles required: 2
69) MOVX @Rp, A
| “Move Ex”
Example:
MOVX @R0, A; [R0]^ ç A
Operation:
Location pointed by R0 in the External RAM gets the data from A Register.
If R0 = 20H then value of A Register gets stored into External RAM location 0020H.
No of cycles required: 2
70) MOVX @DPTR, A
| “Move Ex”
Example:
MOVX @DPTR, A; [DPTR]^ ç A
Operation:
Location pointed by R0 in the External RAM gets the data from A Register.
If DPTR = 4000H then value of A Register gets stored into External RAM location 4000H.
No of cycles required: 2
IMPORTANT TIP FROM BHARAT ACHARYA
When working with External RAM, remember the following rules:
1) We cannot use direct addressing mode.
We can ONLY use Indirect addressing using R0/ R1 or DPTR.
2) All data can only be transferred to or from “A” register.
MOVX operates only on A Register.
3) We can only perform data transfers with these memories.
We can NOT directly perform ADD or SUB etc.
Such operations are only allowed with Internal RAM.
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71) MOVC A, @A + DPTR
| “Move C”
Example:
MOVC A, @A + DPTR; A ç [A + DPTR]ROM
Operation:
A Register gets the data from the location pointed by A + DPTR in ROM.
If A = 05H and DPTR = 0400H, then A Register gets data from ROM location 0405H.
This operation can happen either on Internal ROM or External ROM.
If the address formed after adding A + DPTR is 1000H or more, the operation will happen on External ROM.
If the address is less than 1000H, then it depends upon EA pin.
If EA pin = 0, operation will happen on External ROM.
If EA pin = 1, operation will happen on Internal ROM.
No of cycles required: 2
IMPORTANT TIP FROM BHARAT ACHARYA
This operation can happen either on Internal ROM or External ROM.
If the address formed after adding A + DPTR is 1000H or more,
the operation will happen on External ROM.
If the address is less than 1000H,
then it depends upon EA pin.
If EA pin = 0,
operation will happen on External ROM.
If EA pin = 1,
operation will happen on Internal ROM.
This instruction is extremely useful in accessing Look Up Tables.
DPTR is initialized with the starting address of the table. E.g.:: 0400H.
The required index in the table is initialized in A register. E.g.:: 05H.
By doing MOVC A, @ A+DPTR, A register gets the value from element 5, of table staring at 0400H.
Please recollect the 7-Segment code translation example from the classroom lecture.
71) MOVC A, @A + PC
| “Move C”
Example:
MOVC A, @A + PC; A ç [A + PC]ROM
Operation:
A Register gets the data from the location pointed by A + PC in ROM.
If A = 25H and PC = 0400H, then A Register gets data from ROM location 0425H.
No of cycles required: 2
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MICROCONTROLLERS & APPLICATIONS
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73) PUSH addr
| “Push”
Example:
PUSH 25H; First SP ç SP + 1, Then [SP] ç [25H]
Operation:
This instruction is used to push new data into the top of stack.
First SP will become SP + 1
Then at the new location pointed by SP, data from the specified address will be pushed.
This newly pushed data will now become the top of stack.
SP è
Before Push
operation
After Push
operation
25
…
08
07
06
25
…
08
07
06
63
SP è
xx
xx
63
63
xx
xx
No of cycles required: 2
74) POP addr
| “Pop”
Example:
POP 25H; First [25H] ç [SP], Then SP ç SP - 1
Operation:
This instruction is used to pop data from the top of Stack and store it into the desired RAM location.
First data from the top of Stack will be popped and stored into the desired RAM location.
Then SP will become SP - 1
The data now pointed by SP becomes the new top of stack.
SP è
Before Pop
operation
After Pop
operation
25
…
08
07
06
25
…
08
07
06
xx
63
xx
Xx
SP è
63
xx
xx
No of cycles required: 2
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75) XCH A, Rr
| “Exchange”
Example:
XCH A, R0; A çè R0
Operation:
It will interchange the values of A Register and the specified RAM Register.
Suppose A Register contains 34H and R0 contains 67H, then after the operation,
A will get 67H and R0 will get 34H.
No of cycles required: 1
76) XCH A, addr
| “Exchange”
Example:
XCH A, 25H; A çè [25H]
Operation:
It will interchange the values of A Register and the contents of the specified RAM location.
Suppose A Register contains 34H and location 25H contains 67H, then after the operation,
A will get 67H and location 25H will get 34H.
No of cycles required: 1
77) XCH A, @Rp
| “Exchange”
Example:
XCH A, @R0; A çè [R0]
Operation:
It will interchange the values of A Register and the contents of the location pointed by the Register.
Suppose A Register contains 34H and location pointed by R0 contains 67H, then after the operation,
A will get 67H and location pointed by R0 will get 34H.
No of cycles required: 1
78) XCHD A, @Rp
| “Exchange Digit”
Example:
XCHD A, @R0; A Lower Nibble çè [R0] Lower Nibble
Operation:
It will interchange only the lower nibbles of A Register and the contents of the location pointed by the Register.
Since only one digit is exchanged it is called Exchange Digit.
Suppose A Register contains 34H and location pointed by R0 contains 67H, then after the operation,
A will get 37H and location pointed by R0 will get 64H.
No of cycles required: 1
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
BRANCH CONTROL
INSTRUCTIONS
Here you will see operations like:
• SJMP, AJMP & LJMP
• ACALL & LCALL
• RET & RETI
• CJNE
• DJNZ
• JC & JNC
• JZ & JNZ
• JB, JNB & JBC
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BRANCH OPERATIONS OF 8051 (SJMP, AJMP AND L JMP)
SHORT JUMP
Syntax: SJMP radd; // Short Jump using the relative address
Range: (-128 … +127) locations because “radd” is an 8-bit signed number
Size of instruction: 2 Bytes (Opcode of SJMP= 1Byte, radd = 1Byte)
New address calculation: PC ç PC (address of next instruction) + radd
Usage: SJMP (unconditional) and ALL Conditional jumps like JC, JNC, CJNE, DJNZ etc. ç Important for VIVA
Description: Here the branch address (radd) is calculated as a relative distance from the next instruction to the branch location.
In simple terms, instead of telling where we want to jump, we are telling how far we want to jump. This “radd” is then added to PC,
which normally contains address of the next instruction. For examples of SJMP, please refer #BharatSir Lecture Notes
ABSOLUTE JUMP
Syntax: AJMP sadd; // Absolute Jump using the short address
Range: max 2KB as long as the Jump is within the Same Page
Size of instruction: 2 Bytes (Opcode of AJMP= 1Byte, sadd = 1Byte)
New address calculation:
Usage: AJMP and ACALL.
Description: Here the entire program memory (64 KB), is divided into 32 pages, each page being of 2KB. We can jump to any
location of the same page, giving a max range of 2 KB. As the jump is in the same page, only the lower 11 bits of the address will
change. Out of them, lower 8 bits are given by “sadd” and the higher 3 bits are given by the opcode of AJMP. 3 bits have 8
combinations, hence AJMP has 8 opcodes. For examples of AJMP, please refer #BharatSir Lecture Notes
LONG JUMP
Syntax: L JMP ladd; // Long Jump using the long (full) address
Range: 64 KB because “ladd” is a 16-bit address so can be any value from 0000H… FFFFH.
Size of instruction: 3 Bytes (Opcode of LJMP= 1Byte, ladd = 2Bytes)
New address calculation: PC ç ladd
Usage: L JMP, LCALL.
Description: This is the simplest type of Jump. Here we simply give the address where we wish to jump using “ladd”. This
“ladd” is then simply put into PC. For examples of LJMP, please refer #BharatSir Lecture Notes
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Jump operation
1
In a Jump, we simply branch to
the new location and continue
from there on.
Call operation
In a Call, we branch to the new
location, which is basically a
subroutine, we execute the
subroutine, and at the end, we
return to the main program right at
the NEXT instruction after the Call
instruction.
There is no intention to return to
the previous location..
To invoke the subroutine we use Call
instruction.
To return to the main program we
use RET instruction.
3
There is no need for storing any
return address into the stack
During Call, the return address (PC),
is pushed into the stack.
During RET, the return address is
popped from the stack and put back
into PC.
4
Jumps can be of three types:
Short, Absolute or Long Jump.
Call can be of two types: Absolute or
Long Call.
5
Furthermore, Jumps can be
unconditional or conditional.
Calls are always unconditional in
8051.
2
RET
RETI
1
RET is used at the end of an
ordinary Subroutine
RETI is used at the end of an ISR
2
RET will simply return back to the
next instruction of the main
program.
RETI will not only return back to the
next instruction of the main
program, but will also re-enable the
interrupts, by making EA bit ç 1.
Operation:
POP PC; PCHç [SP]
PCLç [SP-1]
SPç SP-2
Operation:
POP PC; PCHç [SP]
PCLç [SP-1]
SPç SP-2
EA ç 1; Enables interrupts by
making EA bit “1” in the
IE-SFR.
3
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79) SJMP radd
| “Short jump to relative address”
Example:
SJMP label;
Operation:
Program takes a short jump to the location “label”.
Please refer to the earlier discussion for a detailed explanation on SJMP, AJMP and LJMP.
They are VERY IMPORTANT for Theory, Practicals and VIVA exams.
No of cycles required: 2
80) AJMP sadd
| “Absolute jump to short address”
Example:
AJMP label;
Operation:
Program takes an absolute jump to the location “label”.
Please refer to the earlier discussion for a detailed explanation on SJMP, AJMP and LJMP.
They are VERY IMPORTANT for Theory, Practicals and VIVA exams.
No of cycles required: 2
81) LJMP ladd
| “Long jump to long address”
Example:
LJMP label;
Operation:
Program takes a long jump to the location “label”.
Please refer to the earlier discussion for a detailed explanation on SJMP, AJMP and LJMP.
They are VERY IMPORTANT for Theory, Practicals and VIVA exams.
No of cycles required: 2
82) JMP @A+DPTR
| “Jump”
Example:
JMP @A+DPTR;
Operation:
Program takes a jump to the location whose address is calculated by A + DPTR.
If A = 25H and DPTR is 1000H then the program will jump to location 1025H by putting 1025H into PC.
No of cycles required: 2
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CONDITIONAL JUMPS
A conditional jump instruction can have two possible executions, depending upon the condition.
If condition is true, program will jump to the branch location, specified by the label.
If condition is false, program will simply proceed to the next instruction.
Please do remember, All conditional jumps are SHORT type of jumps.
87) DJNZ Rr, radd
| “Decrement and Jump if Not Zero”
Example:
DJNZ R7, Back; Decrement R7 and if not equal to “0”, go to “Back”
Operation:
This instruction is extremely useful.
It is used by the programmer to create loops.
We initialize the loop count in some register like R7.
At the end of the loop we write this instruction: “DJNZ R7, Back”
Back is the Label where we wish to begin the loop from.
This instruction will first decrement R7.
It will then check if R7 has become 0 or not.
If R7 is NOT ZERO, program will jump to the location Back.
This will go on happening till R7 finally becomes Zero.
That’s when the loop will break and program will simply proceed to the next instruction.
The count could have been in any register from R0… R7.
Get this clear, whatever is the count, we get the exact same number of iterations.
Neither one more, nor one less.
A count of 5 will produce exactly 5 iterations, neither 4 and nor 6.
Hope you remember various cases we discussed at BHARAT ACADEMY, for minimum and maximum number of iterations.
No of cycles required: 2
88) DJNZ addr, radd
| “Decrement and Jump if Not Zero”
Example:
DJNZ 25H, Back; Decrement the contents of location 25H, and if not equal to “0”, go to “Back”
Operation:
This instruction is again used to make loops just like the previous one.
Except that, now the count is in a memory address, instead of a register.
Say, we initialize the loop count in some RAM location like 25H.
At the end of the loop we write this instruction: “DJNZ 25H, Back”
This instruction will first decrement contents of location 25H.
It will then check if the value has become 0 or not.
Based on that, it will do the iterations the same way as explained in the above instruction.
No of cycles required: 2
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MICROPROCESSORS 8051 & ARM
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89) CJNE A, #n, radd
| “Compare and Jump if Not Equal”
Example:
CJNE A, #25H, Down; Compare A with number 25H. If not equal jump to location “Down”
Operation:
This instruction will compare A register with the number 25H.
If they are NOT EQUAL, program will jump to location “Down”, else will simply proceed to the next instruction.
No of cycles required: 2
90) CJNE A, addr, radd
| “Compare and Jump if Not Equal”
Example:
CJNE A, 25H, Down; Compare A with [25H]. If not equal jump to location “Down”
Operation:
This instruction will compare A register with the contents of location 25H.
If they are NOT EQUAL, program will jump to location “Down”, else will simply proceed to the next instruction.
No of cycles required: 2
91) CJNE Rr, #n, radd
| “Compare and Jump if Not Equal”
Example:
CJNE R0, #25H, Down; Compare R0 with number 25H. If not equal jump to location “Down”
Operation:
This instruction will compare R0 register with the number 25H.
If they are NOT EQUAL, program will jump to location “Down”, else will simply proceed to the next instruction.
No of cycles required: 2
92) CJNE @Rp, #n, radd
| “Compare and Jump if Not Equal”
Example:
CJNE @R0, #25H, Down; Compare [R0] with number 25H. If not equal jump to location “Down”
Operation:
This instruction will compare the contents of the location pointed by R0, with the number 25H.
If they are NOT EQUAL, program will jump to location “Down”, else will simply proceed to the next instruction.
No of cycles required: 2
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93) JC radd
| “Jump if Carry”
Example:
JC Down; If Carry flag is “1”, jump to location “Down”
Operation:
This instruction is used to check the Carry flag.
If Carry flag = “1”, program will jump to the location “Down”
Else, program will simply proceed to the next location.
JC and JNC are used very frequently in programs where carry is involved.
No of cycles required: 2
94) JNC radd
| “Jump if No Carry”
Example:
JNC Down; If Carry flag is “0”, jump to location “Down”
Operation:
This instruction is used to check the Carry flag.
If Carry flag = “0”, program will jump to the location “Down”
Else, program will simply proceed to the next location.
No of cycles required: 2
95) JZ radd
| “Jump if Zero”
Example:
JZ Down; If A register is “Zero”, jump to location “Down”
Operation:
This instruction is used to check the value of A Register.
If A Register = “0”, program will jump to the location “Down”
Else, program will simply proceed to the next location.
In other processors, JZ and JNZ operate on Zero flag.
Since 8051 does not have a Zero Flag, these instructions simply check the value of A Register.
No of cycles required: 2
96) JNZ radd
| “Jump if Not Zero”
Example:
JNZ Down; If A register is “Not Zero”, jump to location “Down”
Operation:
This instruction is used to check the value of A Register.
If A Register ≠ “0”, program will jump to the location “Down”
Else, program will simply proceed to the next location.
No of cycles required: 2
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MICROPROCESSORS 8051 & ARM
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Mumbai 2018
BOOLEAN CONDITIONAL INSTRUCTIONS
These instructions check the value if individual bits to decide whether to Jump or Not.
They are very useful in Embedded system Application programming of Timers, Serial Port etc.
Often this sub-group is asked as an independent 5 mark question in the exam.
97) JB bit, radd
| “Jump if Bit”
Example:
JB P0.0, Down; If P0.0 = “1”, jump to location “Down”
Operation:
This instruction is used to check the value of a bit.
Suppose the bit in question is P0.0
If P0.0 = “1”, then jump to location “Down”
Else, simply proceed top next location.
No of cycles required: 2
98) JNB bit, radd
| “Jump if Not Bit”
Example:
JNB P0.0, Down; If P0.0 = “0”, jump to location “Down”
Operation:
This instruction is used to check the value of a bit.
Suppose the bit in question is P0.0
If P0.0 = “0”, then jump to location “Down”
Else, simply proceed top next location.
No of cycles required: 2
99) JBC bit, radd
| “Jump if Bit and complement/ clear”
Example:
JBC P0.0, Down; If P0.0 = “1”, jump to location “Down” and make P0.0 ç “0”
Operation:
This instruction is used to check the value of a bit.
Suppose the bit in question is P0.0
If P0.0 = “1”, then jump to location “Down”, and while jumping, also make P0.0 ç 0
Else, simply proceed top next location.
No of cycles required: 2
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BRANCH OPERATIONS OF 8051 (SJMP, AJMP AND L JMP)
SHORT JUMP
Syntax: SJMP radd; // Short Jump using the relative address
Range: (-128 … +127) locations because “radd” is an 8-bit signed number
Size of instruction: 2 Bytes (Opcode of SJMP= 1Byte, radd = 1Byte)
New address calculation: PC ç PC (address of next instruction) + radd
Usage: SJMP (unconditional) and ALL Conditional jumps like JC, JNC, CJNE, DJNZ etc. ç Important for VIVA
Description: Here the branch address (radd) is calculated as a relative distance from the next instruction to the branch location.
In simple terms, instead of telling where we want to jump, we are telling how far we want to jump. This “radd” is then added to PC,
which normally contains address of the next instruction. For examples of SJMP, please refer #BharatSir Lecture Notes
ABSOLUTE JUMP
Syntax: AJMP sadd; // Absolute Jump using the short address
Range: max 2KB as long as the Jump is within the Same Page
Size of instruction: 2 Bytes (Opcode of AJMP= 1Byte, sadd = 1Byte)
New address calculation:
Usage: AJMP and ACALL.
Description: Here the entire program memory (64 KB), is divided into 32 pages, each page being of 2KB. We can jump to any
location of the same page, giving a max range of 2 KB. As the jump is in the same page, only the lower 11 bits of the address will
change. Out of them, lower 8 bits are given by “sadd” and the higher 3 bits are given by the opcode of AJMP. 3 bits have 8
combinations, hence AJMP has 8 opcodes. For examples of AJMP, please refer #BharatSir Lecture Notes
LONG JUMP
Syntax: L JMP ladd; // Long Jump using the long (full) address
Range: 64 KB because “ladd” is a 16-bit address so can be any value from 0000H… FFFFH.
Size of instruction: 3 Bytes (Opcode of LJMP= 1Byte, ladd = 2Bytes)
New address calculation: PC ç ladd
Usage: L JMP, LCALL.
Description: This is the simplest type of Jump. Here we simply give the address where we wish to jump using “ladd”. This
“ladd” is then simply put into PC. For examples of LJMP, please refer #BharatSir Lecture Notes
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MICROPROCESSORS 8051 & ARM
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Mumbai 2018
TIMER SECTION OF 8051
8051 has 2, 16-bit Up Counters T1 and T0.
If the counter counts internal clock pulses it is known as timer.
If it counts external clock pulses it is known as counter.
Each counter is divided into 2, 8-bit registers TH1 - TL1 and TH0 - TL0.
The timer action is controlled mainly by the TCON and the TMOD registers.
TCON - Timer Control (SFR) [Bit-Addressable As TCON.7 to TCON.0]
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TF1 and TF0: (Timer Overflow Flag)
Set (1) when Timer 1 or Timer 0 overflows respectively i.e. its bits roll over from all 1's to all 0's.
Cleared (0) when the processor executes ISR (address 001BH for Timer 1 and 000BH for Timer 0).
TR1 and TR0: (Timer Run Control Bit)
Set (1) - Starts counting on Timer 1 or Timer 0 respectively.
Cleared (0) - Halts Timer 1 or Timer 0 respectively.
IE1 and IE0: (External Interrupt Edge Flag)
Set (1) when external interrupt signal received at INT1 or INT0 respectively.
Cleared (0) when ISR executed (address 0013H for Timer 1 and 0003H for Timer 0).
IT1 and IT0: (External Interrupt Type Cobtrol Bit)
Set (1) - Interrupt at INT1 or INT0 must be -ve edge triggered.
Cleared (0) - Interrupt at INT1 or INT0 must be low-level triggered.
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TMOD - Timer Mode Control (SFR) [NOT Bit-Addressable]
Gate
C/T
M1
M0
Gate
C/T
Timer 1
M1
M0
Timer 0
C/T: (Counter/Timer)
Set (1) - Acts as Counter (Counts external frequency on T1 and T0 pin inputs).
Cleared (0) - Acts as Timer (Counts internal clock frequency, fosc/12).
Gate: (Gate Enable Control bit)
Set (1) - Timer controlled by hardware i.e. INTX signal.
Cleared (0) – Counting independent of INTX signal.
M1, M0: (Mode Selection bits)
Used to select the operational modes of the respective Timer.
M1 M0
0 0
0 1
1 0
1 1
Timer Mode
Mode 0
Mode 1
Mode 2
Mode 3
Timer Counter Interrupts
To use the timer, a certain count value is placed in the Count Register.
This value is the
Max Count - Desired Count + 1 .
On each count (rising edge of the input clock) the counter increments its value.
When the counter rolls over (i.e. form all 1's to all 0's) it is said to overflow.
Thus the Timer Overflow Flag, TFX (TF1 or TF0) is set.
If timer interrupt is enabled then the Timer Interrupt will occur on overflow.
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Timer Counter Logic
As shown above, based on C/T bit the timer functions as a Counter or as a Timer.
If it is a Timer, it will count the internal clock frequency of 8051 divided by 12d (f/12).
If it is a Counter, the input clock signal is applied at the TX (T1 or T0) input pins for Timer1 or
Timer0 respectively. #Please refer Bharat Sir's Lecture Notes for this ...
As shown the Timer is running only if the TRX bit (TR1 or TR0) is set.
Also if the Gate bit is set in the TMOD then the INTX ( INT1 or INT0 ) pin must be “high (1)”
for the timer to count.
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Timer Modes
a) Timer Mode 0 (13-bit Timer/Counter)
THX is used as an 8-bit counter.
TLX is used as a 5-bit pre-set. Hence 13-bits are used for counting.
On each count the TLX increments.
Each time TLX rolls-over, THX increments.
Thus the input frequency is divided by 32 (5-bits of TLX and 25 = 32).
The timer overflow flag TFX is set only when THX overflows i.e. rolls from FFH to 00H.
Max Count = 213 = 8K = 8192 (1FFFH). Hence Max Delay è 8192(12/f)
b) Timer Mode 1 (16-bit Timer/Counter)
All 16-bits of the Counter are used (8 bits of THX and 8 bits of TLX).
On each count the 16-bit Timer increments.
The timer overflow flag TFX is set when the Timer rolls-over from FFFFH to 0000H.
Max Count => 216 = 16K = 65536 (FFFFH). Hence Max Delay è 65536(12/f).
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MICROPROCESSORS 8051 & ARM
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c) Timer Mode 2 (Auto reload TL from TH)
TLX is used as an 8-bit counter.
THX holds the count value to be reloaded.
On each count TLX increments.
When TLX rolls-over (i.e. from FFH to 00H), the following events take place:
1. Timer overflow flag TFX is set, hence timer interrupt occurs.
2. The value of THX is copied into TLX. Hence TLX is auto-reloaded form THX, and the process
repeats.
Thus the timer interrupt occurs at regular intervals "Continuously".
This mode is used to generate a desired frequency using the Timer Flag.
Max Count è 28 = 256 (FFH). Hence Max Delay è 256(12/f).
d) Timer Mode 3 (Two 8-bit Timers Using Timer0)
Timer 0 is used as 2 separate 8-bit timers TH0 and TL0.
TL0 uses the control bits (TR0 and TF0) of Timer 0.
It can work as a Timer or a Counter.
TH0 uses the control bits (TR1 and TF1) of Timer 1.
It can work only as a Timer. #Please refer Bharat Sir's Lecture Notes for this ...
Timer 1 can be in Mode 0, Mode 1, or Mode 2, but will not generate an interrupt.
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MICROPROCESSORS 8051 & ARM
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8051 TIMER/COUNTER (HARDWARE DELAY) PROGRAMMING
Q10
WAP to generate a delay of 20 µsec using internal timer-0 of 8051.
After the delay send a “1” through Port3.1. Assume Suitable Crystal
Frequency
NOTE:
In 8051, if we select a Crystal of 12 MHz, then Timer freq will be
fosc/12 è 1MHz. Hence each count will require 1/1MHz è 1 µsec. Thus
for 20 µsec, the Desired Count will be 20d è 14H. For an Up-Counter
(Mode 1):
Count = Max Count – Desired Count + 1
Count = FFFF – 14 + 1
Count = FFECH #Please refer Bharat Sir's Lecture Notes for this ...
SOLN:
MOV TMOD, #01H
MOV TL0, #0ECH
MOV TH0, #0FFH
MOV TCON, #10H
JNB TCON.5, WAIT
SETB P3.1
MOV TCON, #00H
SJMP HERE
WAIT:
HERE:
Q11
; Program TMOD è (0000 0001)2 ... Timer0 Mode1
; Load lower byte of Count
; Load upper byte of Count
; Program TCON è (0001 0000)2 … start Timer0
; Wait for overflow
; Send a “1” through Port3.1
; Stop Timer0
; End of program
WAP to generate a Square wave of 1 KHz from the TxD pin of 8051,
using Timer1. Assume Clock Frequency of 12 MHz.
NOTE:
For a Square wave of 1 KHz, the delay required is .5 msec.
We know, each count will require 1/1MHz è 1 µsec.
Thus for 500 µsec, the Desired Count will be 500d è 01F4H. For an
Up-Counter (Mode 1):
Count = Max Count – Desired Count + 1
Count = FFFF – 01F4 + 1
Count = FE0CH
SOLN:
CLR P3.1
MOV TMOD, #10H
MOV TL1, #0CH
MOV TH1, #0FEH
MOV TCON, #40H
JNB TCON.7, WAIT
CPL P3.1
MOV TCON, #00H
SJMP REPEAT
REPEAT:
WAIT:
; Clear Txd Line initially
; Program TMOD è (0001 0000)2 ... Timer1 Mode1
; Load lower byte of Count
; Load upper byte of Count
; Program TCON è (0100 0000)2 … start Timer1
; Wait for overflow
; Toggle Txd pin after the delay
; Stop Timer1
; Repeat the process
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Q12
NOTE:
WAP to generate a Rectangular wave of 1 KHz, having a 25% Duty Cycle
from the TxD pin of 8051, using Timer1. Assume XTAL of 12 MHz.
For a Rectangular wave of 1 KHz, having 25% Duty Cycle:
TON = 250 µsec; TOFF = 750 µsec.
For TON: Desired Count = 250 d è 00FAH
CountON = Max Count – Desired Count + 1
CountON = FFFF – 00FA + 1
CountON = FF06H
For TOFF: Desired Count = 750 d è 02EEH
CountOFF = Max Count – Desired Count + 1
CountOFF = FFFF – 02EE + 1
CountOFF = FD12H
SOLN:
MOV TMOD, #10H
; Program TMOD è (0001 0000)2 ... Timer1 Mode1
REPEAT:
MOV TL1, #06H
MOV TH1, #0FFH
SETB P3.1
MOV TCON, #40H
JNB TCON.7, ON
CLR P3.1
MOV TCON, #00H
; Load lower byte of CountON
; Load upper byte of CountON
; Display “1” at Txd
; Program TCON è (0100 0000)2 … start Timer1
; Maintain “1” at Txd
; Clear Txd
; Stop Timer1
MOV TL1, #12H
MOV TH1, #0FDH
MOV TCON, #40H
JNB TCON.7, OFF
MOV TCON, #00H
; Load lower byte of CountOFF
; Load upper byte of CountOFF
; Program TCON è (0100 0000)2 … start Timer1
; Maintain “0” at Txd
; Stop Timer1
SJMP REPEAT
; Repeat the process
ON:
OFF:
Note: If System Freq = 12MHz, it is clear that 1 Count requires 1 msec.
In Mode 1, we have a 16bit Count.
Hence max pulses that can be desired is 216 = 65536.
Count = Max Count – Desired Count + 1
= 65535 – 65536 + 1
= 0.
Thus we will get max delay if we load the count as 0000H, as it will have to “roll-over”
back to 0000H to overflow.
Hence Max delay if XTAL is of 12 MHz … is 65536 µsec è 65.536 msec.
Similarly Max delay if XTAL is of 11.0592 MHz … is 71106 µsec è 71.106 msec.
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Q13
WAP to generate a delay of 1 SECOND using Timer1.
Assume Clock Frequency of 12 MHz. (Popular Question in College!)
NOTE:
Max delay if XTAL is of 12 MHz … is 65536 µsec è 65.536 msec.
Hence to get a delay of 1 second, we will have to perform the
counting repeatedly in a loop.
Lets keep the Desired Count 50000. (50 msec delay)
Now 50000d = C350H
Count = Max Count – Desired Count + 1
Count = FFFF – C350 + 1
Count = 3CB0H #Please refer Bharat Sir's Lecture Notes for this ...
We will have to perform this counting 1sec/50msec times è 20 times
SOLN:
MOV TMOD, #10H
MOV R0, #14H
MOV TL1, #0B0H
MOV TH1, #3CH
MOV TCON, #40H
JNB TCON.1, WAIT
MOV TCON, #00H
DJNZ R0, REPEAT
SJMP HERE:
REPEAT:
WAIT:
HERE:
; Program TMOD è (0001 0000)2 ... Timer1 Mode1
; Load count 20 in R0
; Load lower byte of CountON
; Load upper byte of CountON
; Program TCON è (0100 0000)2 … start Timer1
; Wait for an overflow
; Stop Timer1
; repeat the process 20 times
; End of program
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Q14
WAP to read the data from Port1, 10 times, each after a 1 sec delay.
Store the data from RAM locations 20H onwards. When the operation is
complete, ring an “Alarm” connected at Port3.1. Assume CLK = 12 MHz.
NOTE:
As seen from the previous program, for a delay of 1 second, we have
Count = 3CB0H. Counting has to be performed 20 times.
Also note that all ports of 8051 are o/p ports by default.
To program a port as i/p ports, all “1”s must be sent though it.
SOLN:
CLR P3.1
MOV TMOD, #10H
MOV 90H, #0FFH
; Clear Port3.1 line
; Program TMOD è (0001 0000)2 ... Timer1 Mode1
; Program Port1 as i/p by sending all “1”s through it
REPEAT:
MOV R0, #0AH
MOV R1, #20H
MOV @R1, 90H
INC R1
ACALL DELAY
DJNZ R0, REPEAT
SETB P3.1
SJMP HERE:
; Load Data Count of 10 in R0
; Load Storage address in R1
; Read data from Port
; Increment data storage address from next Iteration
; Call delay of 1 sec before going into next Iteration
; Repeat till all 10 bytes are read
; Ring “Alarm” at Port3.1
; End of program
MOV R2, #14H
MOV TL1, #0B0H
MOV TH1, #3CH
MOV TCON, #40H
JNB TCON.1, WAIT
MOV TCON, #00H
DJNZ R2, REPEAT
RET
; Load count 20 in R0
; Load lower byte of CountON
; Load upper byte of CountON
; Program TCON è (0100 0000)2 … start Timer1
; Wait for an overflow
; Stop Timer1
; Repeat the process 20 times
; End of delay routine
HERE:
DELAY:
REPEAT:
WAIT:
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
SERIAL PORT OF 8051
8051 has a high speed, full duplex, software programmable Serial Port.
Data is received serially through the RxD line, and transmitted through the TxD line.
SBUF register acts as a buffer for both reception and transmission.
The SCON SFR mainly controls serial Communication.
The SMOD bit in the PCON SFR controls the baud rate.
SCON - Serial Control (SFR) [Bit-Addressable As SCON.7 to SCON.0]
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
SM0 and SM1: (Serial Port Mode Bits 0 and 1)
SM0 SM1
0 0
0 1
1 0
1 1
SERIAL MODE
Mode 0
Mode 1
Mode 2
Mode 3
DESCRIPTION
Shift Register
8-bit UART
9-bit UART
9-bit UART
BAUD RATE
Fixed è fosc/12
Variable
Fixed è fosc/32 or fosc/64
Variable
SM2: (Serial Port Mode Bits 2)
Enables multiprocessor features in Mode 2 and Mode 3. i.e.
Mode 2 or Mode 3: If SM2 = 1 RI will be 1 when the 9th data bit received is "1".
Mode 1:
If SM2 = 1 RI will be 1 when the Stop bit received is "1". (valid)
Mode 0:
SM2 is kept 0 i.e. Not Used.
REN: (Receiver Enable)
REN = 1
Enables the Receiver.
REN = 0
Disables the Receiver.
TB8:
(Bit 8 i.e. 9th bit transmitted)
In Mode 2 and Mode 3 it holds the 9th Programable bit, to be transmitted.
In Mode 1 and Mode 0 it is not used.
RB8: (Bit 8 i.e. 9th bit recieved)
In Mode 2 and Mode 3 it is used to receive the 9th Programable bit.
In Mode 1 it recieves the Stop bit.
In Mode 0 it is not used.
RI:
(Receive Interrupt)
RI = 1 è One Complete character is received.
RI must be explicitly cleared by software before receiving the next byte.
TI:
(Transmit Interrupt)
TI = 1 è One Complete character is transmitted.
TI must be explicitly cleared by software before transmitting the next byte.
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The Baud Rate is controlled by the bit SMOD in PCON SFR.
SMOD: (Serial Baud rate Modify Bit in PCON SFR)
SMOD = 1 è Doubles the Baud rate of Timer 1 for Modes 1, 2 and 3.
SMOD = 0 è Uses Timer 1 Baud Rate.
SBUF Register
It is physically two registers, one for holding the received character and the other for holding the
character to be transmitted.
Both receive and transmit registers are addressed 99H.
Serial data Interrupt
When a complete character is received the RI bit is set in the SCON Register.
When a complete character is transmitted the TI bit is set in the SCON Register.
These two bits are OR'ed to produce the serial data interrupt.
RI/TI bit must be explicitly cleared by the program before transferring the next charecter.
Data Transmission
Data written in SBUF.
Data transmitted through TxD.
When a complete character is transmitted TI is set.
Serial Data interrupt occurs.
In its ISR the TI bit is reset.
New data written into SBUF and the process continues till all the data is transmitted.
Data Reception
REN in SCON must be set, this prevents receiving unwanted data (eg noise).
Data received through RxD into the SBUF.
When a complete character is received RI is set.
Serial Data interrupt occurs. #Please refer Bharat Sir's Lecture Notes for this ...
In its ISR the RI bit is reset and so the program accepts the received data.
New data is received in SBUF and the process continues till all the data is received.
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Mumbai 2018
Serial Data Transfer Modes
a) Mode 0 (Shift Register)
This is a 8-bit Half-Duplex mode.
The Start/Stop bits are not required.
Both transmission and reception happen through the RxD line.
TxD line provides the shift clock for data transfer.
The signal on the TxD line is a square wave high for S6, S1, and S2 and low for S3, S4, and S5.
During Tramsnission data is "shifted" out of SBUF during S6 P2. #Please refer Bharat Sir's Lecture Notes for this ...
During Reception RxD is sampled during S5 P2 and then "shifted".
This mode is mainly used for high speed data collection using discrete logic.
It is not intended for data communication between computers.
Baud rate: Fixed.
fBaud = f/12. (f = Oscillator Frequency).
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b) Mode 1 (8-bit “Standard” UART)
This is a 10-bit Full-Duplex mode.
RxD receives data, TxD transmits data.
For Transmission data is sent as 1 Start bit (0), 8 Data bits (LSB first), 1 Stop bit (1).
Transmit Interrupt flag TI is set only after all the above 10 bits are transmitted.
Each bit interval is inverse of Baud rate i.e. each bit has to be maintained for that interval.
Data is also received in the same order at the programmed Baud Rate.
During reception, Start bit is discarded, 8 Data bits received in SBUF, Stop bit saved in RB8.
The RI will be set only if SM2 = 0 (unconditional) or the RB8 = 1 (condition satisfied). This is
an anti-noise safeguard.
Once RI is set the program is interrupted to accept the data just received.
Baud Rate: Variable (can be controlled be changing the overflow rate using difeent counts)
fBaud = 2SMOD × (Timer 1 overflow frequency).
32
fBaud =
1 × (Timer 1 overflow frequency); {when SMOD = 0}.
32
fBaud =
1 × (Timer 1 overflow frequency); { when SMOD = 1}.
16
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MICROPROCESSORS 8051 & ARM
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Mumbai 2018
c) Mode 2 (9-bit UART) (Multiporcessor Mode)
This mode is similar to Mode 1 except that it has 11 bits per character.
Format : 1 Start bit (0), 8 Data bits, 9th Programmable Bit and 1 Stop bit (1).
During Transmission the 9th data bit is copied form bit TB8 of SCON.
During Reception the 8 data bits are received in SBUF, 9th bit in RB8 of SCON.
Both Start bit and Stop bits are discarded.
This 9th bit can be used to control Multiprocessor Communication.
Baud Rate: Fixed (cannot be controlled be Timer1)
fBaud = 2SMOD × (Oscillator Frequency).
64
fBaud =
1 × (Oscillator Frequency) {when SMOD = 0}.
64
fBaud =
1 × (Oscillator Frequency) {when SMOD = 1}.
32
d) Mode 3 (9-bit UART) (Multiporcessor Mode)
This mode is exactly the same as Mode 2 except that the Baud rate is Variable i.e. it is
determined using the Timer 1 overflow rate as in Mode 1.
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Multiprocessor Communication in Mode 2:
8051 (A)
{SM2 = 0}
8051 (B)
{SM2 = 1}
8051 (C)
{SM2 = 0}
8051 (D)
{SM2 = 1}
This mode is also used for multiprocessor communication.
Here the 9th bit is very useful.
If the 9th bit is 1 …
Then every processor will be interrupted and hence will recive the
data (SM2=0 or 1)
This can be use to “Broadcast” the data to all processors.
It the 9th bit is 0 …
Then ONLY those processors with SM2 = 0 will be interrupted,
hence receive the data.
This enables Selective Transmission i.e. processors can selectively talk to
one another.
In the above example,
If “A” send data with the 9th bit as 1 then all will receive, and it will be a “Broadcast”
If “A” send data with the 9th bit as 0 then only “C” will receive, and hence it will be
“Selective Transmission”.
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Mumbai 2018
8051 SERIAL PORT PROGRAMMING
Q15
NOTE:
WAP to transfer the number 35H Serially at a Baud rate of 9600 using
8051. Assume suitable XTAL frequency.
For Serial Transmission, XTAL of 11.0592 MHz is selected to provide
the Standard Baud Rates.
We Know for Serial Mode 1: BR = (2SMOD/32) x T1 Overflow rate.
If SMOD = 0, And the timer Overflows just after 1 count, then the
Baud Rate will be è (1/32) x (11.0592 x 106)/12 x 1
BR = 28800.
Similarly if timer Counts 3 pulses, then BR = 28800/3 = 9600.
Count = Max Count – Desired Count + 1
Count = FF – 3 + 1
Count = FDH
Timer1 (Higher Byte) should be loaded with the above count and
programmed to work in Mode 2 (Continuous mode).
#Please refer Bharat Sir's Lecture Notes for this ...
SOLN:
HERE:
MOV TMOD, #20H
MOV TH1, #0FDH
MOV SCON, #50H
SETB TCON.6
MOV SBUF, #35H
JNB SCON.1 SENDING
CLR SCON.1
SJMP HERE
Baud Rate
28800
14400
9600*
4800*
2400*
1200*
600
Desired Count
1
2
3
6
12
24
48
SENDING:
; Program TMOD è (0010 0000)2 ...Timer 1 Mode2
; Load appropriate count
; Program SCON è (0101 0000)2 ...Serial Mode1; REN enabled
; Start Timer1
; Load data to be transferred in SBUF; Now the Transfer Begins
; Wait for transfer to get completed till TI gets set
; Clear TI
;
Load TH1 as
FF
FE
FD
FA
F4
E8
D0
Standard
Baud
Rates
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Q16
SOLN:
HERE:
TRANSFER:
SENDING:
WAP to transfer “SUCCESS” Serially at 2400 Bauds, with 8 data bits,
1 Start bit (0) and 1 Stop bit (1) using 8051.
MOV TMOD, #20H
MOV TH1, #0F4H
MOV SCON, #50H
SETB TCON.6
; Program TMOD è (0010 0000)2 ...Timer 1 Mode2
; Load appropriate count for counting 12d pulses
; Program SCON è (0101 0000)2 ...Serial Mode1; REN enabled
; Start Timer1
MOV A, #”S”
ACALL TRANSFER
MOV A, #”U”
ACALL TRANSFER
MOV A, #”C”
ACALL TRANSFER
ACALL TRANSFER
MOV A, #”E”
ACALL TRANSFER
MOV A, #”S”
ACALL TRANSFER
ACALL TRANSFER
SJMP HERE
;
; Transfer S
;
; Transfer U
;
; Transfer C
; Transfer C again
;
; Transfer E
;
; Transfer S
; Transfer S again
; End of program
MOV SBUF, A
JNB SCON.1 SENDING
CLR SCON.1
RET
; Load data to be transferred into SBUF
; Wait for transfer to get completed till TI gets set
; Clear TI
;
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
Q17
WAP to read 10 bytes from Port1 and send each byte Serially at 2400
Bauds, with 8 data bits, 1 Start bit (0) and 1 Stop bit (1).
SOLN:
MOV R0, #0AH
MOV 90H, #0FFH
MOV TMOD, #20H
MOV TH1, #0F4H
MOV SCON, #50H
SETB TCON.6
; Load count of 10 as 10 bytes have to be transferred
; Program Port1 as an input port
; Program TMOD è (0010 0000)2 ...Timer 1 Mode2
; Load appropriate count for counting 12d pulses
; Program SCON è (0101 0000)2 ...Serial Mode1; REN enabled
; Start Timer1
REPEAT:
MOV A, 90H
ACALL TRANSFER
DJNZ R0, REPEAT
SJMP HERE
; Read from Port1 into A register
; Transfer Contents of A register serially
; Repeat till all 10 bytes are transferred
; End of program
MOV SBUF, A
JNB SCON.1 SENDING
CLR SCON.1
RET
; Load data to be transferred into SBUF
; Wait for transfer to get completed till TI gets set
; Clear TI
;
HERE:
TRANSFER:
SENDING:
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INTERRUPTS OF 8051
8051 supports 5 interrupts.
2 External Interrupts are on the following pins
INT1
INT0
2 Internal Timer interrupts are:
Timer 1 Overflow Interrupt
Timer 0 Overflow Interrupt
1 Serial Port Interrupt (Common for RI or TI)
All interrupts are vectored i.e. they cause the program to execute an ISR from a pre-determined
address in the Program Memory. #Please refer Bharat Sir's Lecture Notes for this ...
Interrupts are controlled mainly by IE and IP SFR's and also by some bits of TCON SFR.
IE - Interrupt Enable (SFR) [Bit-Addressable As IE.7 to IE.0]
EA
Enable All
1 = Enable All Interrupts
0 = Disable All Interrupts
---
ET2
Reserved
ES
ET1
EX1
Enable Timer
1 Interrupt
Enable Serial
Interrupt
ET0
EX0
Enable Timer
0 Interrupt
Enable Ext.
Interrupt 1
Enable Ext.
Interrupt 0
1 = Enable respective Interrupt
0 = Disable respective Interrupt
IP - Interrupt Priority (SFR) [Bit-Addressable As IP.7 to IP.0]
---
---
PT2
Reserved
PS
PT1
PX1
Priority of
Timer 1 Int.
Priority of
Serial Int.
PT0
PX0
Priority of
Timer 0 Int.
Priority of
Ext. Int.1
Priority of
Ext. Int.0
1 = Priority of respective Interrupt è HIGH
0 = Priority of respective Interrupt è LOW
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MICROPROCESSORS 8051 & ARM
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Mumbai 2018
Timer Overflow Interrupts (TF1 and TF0)
When any of the 2 Timers overflow, their respective bit TFX (TF1 or TF0) is set in TCON SFR.
If Timer Interrupts are enabled then the timer interrupt occurs.
The TFX bits are cleared when their respective ISR is executed.
Serial Port Interrupt (RI or TI)
While receiving serial data, when a complete byte is received the RI (receive interrupt) bit is set
in the SCON.
During transmission, when a complete byte is transmitted the TI (transmit interrupt) bit is set in
the SCON.
ANY of these events can cause the Serial Interrupt (provided Serial Interrupt is enabled).
The RI/TI bit is not cleared automatically on executing the ISR. The program should explicitly
clear this bit to allow further Serial Interrupts.
External Interrupts ( INT1 and INT0 )
Pins INT1 and INT0 are inputs for external interrupts.
These interrupts can be -ve edge or low-level triggered depending upon the IT0 and IT1 bit in
TCON SFR. (ITX = 1 è -ve edge triggered)
Whew any of these interrupts occur the respective bits TE1 or IE0 are set in the TCON SFR.
If External Interrupts are enabled then the ISR is executed from the respective address.
Interrupt Sequence
The following sequence is executed to service an interrupt:
Address of next instruction of the main program i.e. PC is Pushed into the Stack.
All interrupts are disabled, by making EA bit in IE SFR ç 0.
Program Control is shifted to the Vector Address (location) of the ISR.
The ISR begins.
Returning Sequence
RETI instruction denotes the end of the ISR.
It causes the processor to POP the contents of the Stack Top into the PC.
It also re-enables interrupts by making EA bit in IE SFR ç 1.
The main program resumes.
Interrupt Priorities
8051 has only two priority levels for the interrupts: Low and High.
Interrupt priorities are set using the IP SFR.
As the name suggests, a high priority interrupt can interrupt a low priority interrupt.
It two or more interrupts at the same level occur simultaneously then priorities are decided as
follows:
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INTERRUPT
PRIORITY
VECTOR ADDRESS
INT0
1
0003H
TF0
2
000BH
INT1
3
0013H
TF1
Serial (RI or TI)
4
5
001BH
0023H
DIAGRAM FOR INTERRUPTS… OPTIONAL
DRAW ONLY IF ASKED
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POWER SAVING FEATURE OF 8051
8051 provides the following two power saving modes:
1) Idle Mode.
2) Power Down Mode.
To enter one of these modes the corresponding bit is set in the PCON SFR
PCON- Power Control (SFR) [NOT Bit-Addressable]
SMOD
X
X
SMOD
Programs Baud Rate in
Mode 1, 2 and 3 of Serial Port.
X
GF1
GF0
General Purpose
Flag Bits
PD
IDL
1 => Enter Idle Mode
1 => Enter Power Down
Mode
Advantages of Power Saving Feature
1. It is cost effective as less power is consumed.
2. Power saving reduces the heat generated during the operations and hence more compact circuit
designs can be implemented.
3. Expensive fans and blowers are not required.
4. As components are subject to less heat, their reliability increases and longer life is assured.
Power Saving Logic
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MICROPROCESSORS 8051 & ARM
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Mumbai 2018
1) Idle Mode
8051 enters Idle Mode when the IDL bit of PCON SFR is set to 1.
As PCON is NOT Bit-Addressable, the instruction used is ORL 87H, #01H. {Address of PCON is 87H}
In Idle Mode ONLY the clock signal to the CPU is cut off. Hence the CPU goes to sleep.
As the CPU draws upto 80% of the Power supply, this saves sufficient amount of power.
ALE and PSEN signals are held high.
The Oscillator is still running so the On-Chip Components like the RAM, Timer, Serial Port,
Interrupts, PC, SP, PSW, A registers retain their value as long as Vcc is maintained high.
Termination from Idle Mode
There are two ways of terminating the Idle Mode.
a) Interrupt
When a valid interrupt occurs the IDL bit in the PCON register is reset to 0.
8051 comes out of the Idle Mode.
ISR for the Interrupt is executed. Control returns to the main program and execution of the
main program continues after the instruction that caused the Idle Mode.
As the internal components maintained their original values, the original state of the program is
restored.
b) Reset
If the manual reset signal is applied to the 8051, the Idle Mode is terminated.
The reset signal must be active only for 2 clock cycles as the oscillator is still running. As 8051 is
reset, all SFR's and internal registers are reset, PC is cleared, all ports contain 1's and the program
starts from location 0000H.
Hence, the original state of the program is not restored.
2) Power Down Mode
8051 enters Power Down Mode when the PD bit of PCON SFR is set to 1.
As PCON is NOT Bit-Addressable, the instruction used is ORL 87H, #02H. {Address of PCON is 87H}
Here the entire chip is put to sleep as the oscillator is turned off.
On-Chip RAM and SFR's maintain their values. #Please refer Bharat Sir's Lecture Notes for this ...
If 8051 is running from external clock source then it is blocked.
ALE and PSEN signals are held low.
Important Use: (Reduced Power Supply Mode)
In Power down Mode the Vcc can be reduced to minimize power consumption.
It is important that Vcc must be maintained high until 8051 enters the Power Down Mode,
and Vcc must be restored before Power Down Mode is terminated. This would ensure that
no damage is done to the internal circuit.
Termination from Power Down Mode
There is only one way of terminating the Power Down Mode.
Reset
The ONLY way of terminating the Power down Mode is the manual reset signal.
As the Oscillator is not running, the Reset signal must be active long enough for the oscillator to
restart and stabilize. As 8051 is reset, all SFR's and internal registers are reset, PC is cleared, all
ports contain 1's and the program starts from location 0.
Hence the original state of the program is not restored.
If Vcc was held high during Power Down Mode then the data of the Internal RAM is maintained.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
IO PORTS OF 8051
STRUCTURE OF PORT 0
Structure
1) The above figure represents one bit (one line) of Port 0.
2) Every port line has a one-bit latch, in the form of a D Flip Flop
It is used to hold the value on the port, when used as an output port.
The latch will capture a “0” or a “1” from the internal bus, on getting “write to latch” signal.
3) The port also has buffers that allow us to either read from the latch or read from the port line.
4) Port 0 has an alternate function.
It can act as the multiplexed Address Data Bus (AD7 – AD0).
Hence, there is a MUX that will decide if the port operates as A/D bus or simply as a Port.
Input operation
1) When a “1” is written to the latch, the port becomes an input port, by turning the FETs off.
2) Since the Port line goes into a “float” state (neither 0 nor 1), it is a “true bidirectional” port.
3) We can now read (input) the value of the port pin by enabling the “read pin” buffer.
A “READ” type of instruction like MOV A, P0; will read the value from the port pins.
4) Similarly, we can also read the value from the latch by enabling the “read latch” buffer.
A “READ-MODIFY” type of instruction like INC P0; will read the value from the latch.
Output operation
1) To send a “0”: Write a “0” on the latch.
This turns ON the FET and the port pin gets grounded, so the port pin contains logic “0”.
2) To send a “1”: Write a “1” on the latch.
This turns OFF the FET and the port line “floats”, containing neither logic 0 nor 1 (just like input).
By connecting VCC using an external pull up resister, we can output a “1” on the port line.
Alternate function
1)
2)
3)
4)
Port 0 can also be used as the multiplexed bus AD7 – AD0, and can carry address or data.
The “control” signal shown in the diagram directs the address line to the “gate” of the FET.
If A/D line is “1”, upper FET is ON, Lower is OFF so pin becomes Logic “1”.
If A/D line is “0”, upper FET is OFF, Lower is ON so pin becomes Logic “0”.
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STRUCTURE OF PORT 1
Structure
1) The above figure represents one bit (one line) of Port 1.
2) Every port line has a one-bit latch, in the form of a D Flip Flop
It is used to hold the value on the port, when used as an output port.
The latch will capture a “0” or a “1” from the internal bus, on getting “write to latch” signal.
3) The port also has buffers that allow us to either read from the latch or read from the port line.
4) Port 1 is a simple I/O port and has no alternate function, hence the output of the latch is
directly connected to the FET through an internal pull up.
Input operation
1)
2)
3)
4)
When a “1” is written to the latch, the port becomes an input port, by turning the FETs off.
The Port line will not go into a “float” state.
Instead, the internal pull up will maintain a logic 1 (Vcc) on the port line.
This means, in spite of being in input mode, the pin still carries “1” through the Vcc Pull up.
Hence it is called a “quasi bidirectional” port. {Quasi means almost but not fully}
5) We can now read (input) the value of the port pin by enabling the “read pin” buffer.
A “READ” type of instruction like MOV A, P1; will read the value from the port pins.
6) Similarly, we can also read the value from the latch by enabling the “read latch” buffer.
A “READ-MODIFY” type of instruction like INC P1; will read the value from the latch.
Output operation
1) To send a “0”: Write a “0” on the latch.
This turns ON the FET and the port pin gets grounded, so the port pin contains logic “0”.
2) To send a “1”: Write a “1” on the latch. This turns OFF the FET.
The internal Vcc Pull up provides a logic “1” on the port line.
Alternate function
1) Port 1 does not have any alternate function.
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
STRUCTURE OF PORT 2
Structure
1) The above figure represents one bit (one line) of Port 2.
2) Every port line has a one-bit latch, in the form of a D Flip Flop
It is used to hold the value on the port, when used as an output port.
The latch will capture a “0” or a “1” from the internal bus, on getting “write to latch” signal.
3) The port also has buffers that allow us to either read from the latch or read from the port line.
4) Port 2 has an alternate function.
It can act as the higher order Address Bus (A15 – A8).
Hence, there is a MUX that will decide if the port operates as Address bus or simply as a Port.
Input operation {Totally same as port 1}
1)
2)
3)
4)
When a “1” is written to the latch, the port becomes an input port, by turning the FETs off.
The Port line will not go into a “float” state.
Instead, the internal pull up will maintain a logic 1 (Vcc) on the port line.
This means, in spite of being in input mode, the pin still carries “1” through the Vcc Pull up.
Hence it is called a “quasi bidirectional” port. {Quasi means almost but not fully}
5) We can now read (input) the value of the port pin by enabling the “read pin” buffer.
A “READ” type of instruction like MOV A, P2; will read the value from the port pins.
6) Similarly, we can also read the value from the latch by enabling the “read latch” buffer.
A “READ-MODIFY” type of instruction like INC P2; will read the value from the latch.
Output operation {Totally same as port 1}
1) To send a “0”: Write a “0” on the latch.
This turns ON the FET and the port pin gets grounded, so the port pin contains logic “0”.
2) To send a “1”: Write a “1” on the latch. This turns OFF the FET.
The internal Vcc Pull up provides a logic “1” on the port line.
Alternate function
1) Port 2 can be used as the higher order address bus (A15 – A8).
2) The “control” signal shown in the diagram directs the address line to the “gate” of the FET.
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STRUCTURE OF PORT 3
Structure {Totally same as port 1 & 2}
Input operation {Totally same as port 1 & 2}
Output operation {Totally same as port 1 & 2}
Alternate function
1) Port 3 has a list of alternate functions
2) The “Alternate Output function” signal directs the alternate function to the “gate” of the FET.
ALTERNATE FUNCTIONS OF PORT 3 PINS
PIN
FUNCTION USE
P3.0
RxD
Used to receive Serial data bit by bit
P3.1
TxD
Used to transmit Serial data bit by bit
P3.2
INT0
Used to receive external hardware Interrupt 0
P3.3
INT1
Used to receive external hardware Interrupt 1
P3.4
T0
Gives clock input to Timer 0 to act as a Counter
P3.5
T1
Gives clock input to Timer 1 to act as a Counter
P3.6
WR
Used to Write data into external RAM
P3.7
RD
Used to Read data from external RAM
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Microcontroller & Embedded Prog. (MU-Sem 5-IT)
CLR
5-16
8051 Interfacing and Applications
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
MOV
P1, A
; Put Command value in P1 from A Register
CLR
P2.0
; Make Register Select = 0 for Command
CLR
P2.1
; Make Read/Write Select = 0 for Write
SETB
P2.2
; Make Latch Enable = 1
CLR
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
RET
Command :
ACALL Delay
; Call a delay of 10 milliseconds
RET
Data:
MOV
P1, A
; Put Data value (ASCII Code) in P1 from A Register
SETB
P2.0
; Make Register Select = 1 for Data
CLR
P2.1
; Make Read/Write Select = 0 for Write
SETB
P2.2
; Make Latch Enable = 1
CLR
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
ACALL Delay
; Call a delay of 10 milliseconds
RET
! 5.5 8051 | 4x4 Matrix Keyboard Interfacing
Draw interfacing of keyboard matrix with 8051 in detail with diagram. Write a
Q.
program to generate Hexadecimal values.
(Q. 5(B), Dec. 19, 10 Marks)
! Working of a Key
x
A keyboard is the most basic input device.
x
When a Key is connected to a port pin, the port pin must be configured as an input pin. We read the
value of the pin to establish of a key is pressed.
x
Most circuits use an active low logic for a key.
x
The Keys are connected to Vcc via a pull up resister. The default value on the keys is a 1. When a
Key is pressed, it gets connected to GND making its value 0.
! Concept of a matrix Keyboard
x
For a small keypad, like a car remote key, we need only 2-3 keys. We could simply connect them
on each line of a port.
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5-17
8051 Interfacing and Applications
But for a large keyboard like a TV Remote or the computer’s keyboard, the number of keys is
large. We cannot afford one port pin each for every key.
x
So we connect the keys in a matrix form. This gives us more keys using less lines. By identifying
the row and the column we can figure out which key is pressed.
! 4x4 Matrix Keyboard
x
We use four lines of a port, say P1.0… P1.3 as rows.
x
We use for lines of a different port, say P2.0… P2.3 as columns. Rows will be Output whereas
Columns will be Input.
x
The columns will have a default value of 1 due to the Vcc with a pull up resister. This gives us 16
intersecting points, on each we plant a key.
x
When the key is “Pressed”, the corresponding row and column will come into contact.
! Program Logic
x
First off, we need to know IF A KEY IS PRESSED?
x
For this we keep sending 0s on all rows and read the columns.
x
If columns are still all 1’s it means no key is pressed. Repeat this process. Else move to Row
Check. Once we are sure that a key is pressed, we check each row individually.
x
This is done by sending a 0 on every row and checking the columns till the 0 comes on the
columns. Once the row is identified we check the column by rotating the column data till a 0 is
found.
x
This finally identifies the key.
! Key De-bounce
x
Practically every key uses a spring mechanism and hence will bounce.
x
This means when a key is pressed there are microscopic vibrations which fluctuate the key value
between 0 and 1 till it finally settles to a stable 0. Reading the key during this bouncing period may
give you a wrong result. Avoid this bouncing period by calling a delay before performing row and
column checking. This allows the key to stabilize in the “pressed” state of logic 0. The delay is
typically 10-20 milliseconds. This is called key de-bouncing.
Hence write a program to identify the key pressed and display the key on a 7 segment display.
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! Interface
Fig. 5.5.1 : Matrix keyboard interface with 8051
! Algorithm
x
Initialise look up table for 7 segment codes at 0400H.
x
Initialise DPTR to point to look up table.
x
Initialise Port 2 as input port (for columns).
x
To know if A KEY IS PRESSED, send all 0 on P1 (rows) and read P2 (columns). If P2 = 0FH then
repeat else break for Row Check.
x
Call delay for de-bouncing and start Row Check
x
Send 0 on each row and keep R2 as the smallest key of the row.
x
Read the column. Break for column check if value not equal to 0FH. Else next row.
x
In column check, rotate right the column value.
x
If no carry then R2 is the key else increment R2 and repeat.
x
Once key is identified, get its 7 segment code from look up table, display the key and repeat the
whole program for the next key.
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8051 Interfacing and Applications
Program : ORG 0400H
Table DB C0H, F9H, A4H, B0H, 99H, 92H, 82H, F8H, 80H, 90H
MOV DPTR, #0400H
; Initialise DPTR as a pointer to starting of the
; look up table = 0400H
Check :
Pressed:
MOV P2, #0FFH
; Initialise P2 as an input port for the columns
MOV P1, #00H
; Send a 0 on all rows
MOV A, P2
; Read the columns
CJNE A, #0FH, Pressed
; If A != 0FH that means a key is pressed
SJMP Check
; Else repeat this process
ACALL Delay
MOV R0, #00H
; 10 millisecond Delay to let the bouncing settle down
; Smallest key of 1st row
MOV P1, #0EH
; Send 0 only on 1st row first row (0000 1110)
MOV A, P2
; Read the columns
CJNE A, #0FH, Colcheck ; If A != 0FH that means row is identified,
MOV R0, #04H
; move to column check
; Smallest key of 2nd row
MOV P1, #0DH
; Send 0 only on 2nd row first row (0000 1101)
MOV A, P2
; Read the columns
CJNE A, #0FH, Colcheck ; If A != 0FH that means row is identified,
MOV R0, #08H
; move to column check
; Smallest key of 3rd row
MOV P1, #0BH
; Send 0 only on 3rd row first row (0000 1011)
MOV A, P2
; Read the columns
CJNE A, #0FH, Colcheck ; If A != 0FH that means row is identified,
MOV R0, #0CH
; move to column check
; Smallest key of 4th row
MOV P1, #07H
; Send 0 only on 4th row first row (0000 0111)
MOV A, P2
; Read the columns
; No need to check, obviously 4th row is identified,
; move to column check
Colcheck :
RR A
; rotate right the column value in A register and
; check the carry flag
JNC Display
; If CF = 0, R2 is the Key Pressed, go and display it
INC R2
; Else increment R2
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SJMP Colcheck
5-20
8051 Interfacing and Applications
; Repeat. No need for a count. Loop will break in
; 4 iterations for sure.
Display :
MOV A, R2
; A ç Index from R2 (The Key that was Pressed)
MOVC A, @A+DPTR
; A ç 7 segment code from Look Up Table
MOV P3, A
; Call the “Data” function with the ASCII value in A register
ACALL Delay
; Optional. It is the “repeat delay” of a key board,
; typically 50 millisecond
SJMP Check
; Go back and check for the next key
! 5.6 8255 | Internal Block Diagram
Q.
Draw and explain the functional block diagram of 8255 Programmable Peripheral
(Q. 3(a), May 19, 10 Marks)
Interface.
(1C1)Fig. 5.6.1 : Architecture of 8255
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 4.1 8051 | 7 Segment LED Display
# 4.1.1 Basics of LED
x
An LED (Light Emitting Diode) is one of the most basic output devices.
x
You see them everywhere around you, starting from the TV ON/OFF light, Fancy decoration lights,
Traffic indicators etc. They are simply turned On or OFF by a basic 1/0 logic.
x
The LED has an Anode which needs a logic 1 and a cathode which needs a logic 0.
x
When you hold the LED in your hand, you will notice the Anode to be slightly longer than the Cathode.
There are two ways to connect an LED.
Fig. 4.1.1 : Basics of LED
Sourcing Method
x
We connect the Anode to a port pin and the Cathode to ground. Here we need to make the port pin logic
1 to turn ON the LED. The current is “Sourced” by µC and will “sink” into ground.
x
Hence it is called Sourcing method.
Sinking Method
x
We connect the Cathode to a port pin and the Anode to Vcc. Here we need to make the port pin logic 0
to turn ON the LED. The current is “Sourced” by Vcc and the µC will “Sink” it.
x
Hence it is called Sinking method.
# 4.1.2 Blinking LED program
´ Write a program to blink an LED connected to P1.0 Algorithm
Algorithm
x
Make P1.0 Í 1
x
Call a Delay subroutine
x
Make P1.0 Í 0
x
Call a Delay subroutine
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Program
Program : Loop this infinitely
Again :
SETB P1.0
; P1.0 Í 1
ACALL Delay
; Call a delay routine of typically half a second
CLR P1.0
; P1.0 Í 0
ACALL Delay
; Call a delay routine of typically half a second
SJMP Again
; Jump to label “Here” and end the program
Note : We have made ample Delay Routines in the previous chapter. You could use any of them for the
delay.
´ There are 8 LEDs connected to the port pins of P1. Write a program to blink them alternately.
Algorithm
x
Send 55H to P1. (55H = 0 1 0 1 0 1 0 1)
This makes 4 LEDs on and 4 OFF alternately
x
Call a Delay routine (roughly 500 milliseconds)
x
Send AAH to P1. (AAH = 1 0 1 0 1 0 1 0)
This makes the other 4 LEDs on and 4 OFF alternately
x
Call a Delay routine (roughly 500 milliseconds)
x
Loop this infinitely
Program
Again :
MOV P1, 55H
; P1.0 Í 0101 0101
ACALL Delay
; Call a delay routine of typically half a second
MOV P1, 0AAH
; P1.0 Í1111 1111
ACALL Delay
; Call a delay routine of typically half a second
SJMP Again
; Jump to label “Here” and end the program
# 4.1.3 7 Segment LED
x
A 7 segment LED is used at various places like floor indicators in a lift, temperature indicators, time
indicators, cab meters and so on. It is formed by 7 LEDs put together to display digits. In fact in places
where a point is needed, there is an 8th LED which acts as a decimal point.
x
A 7 segment LED can be connected in two ways: Common Cathode or Common Anode.
x
In Common Cathode, the cathode of all LEDs is commonly connected to ground and the Anode is
connected to the port pins. Here, sending a 1 on any LED will turn it ON.
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4-4
8051 Interfacing & Applications
In Common Anode, the anode of all LEDs is commonly connected to Vcc and the Cathode is
connected to the port pins. Here, sending a 0 on any LED will turn it ON.
Look Up Table
x
To display a number like 1, we don’t really send “1” to the LED. We send a code called a 7 segment
code. It will turn ON some and turn OFF some LEDs such that the required digit “1” comes up on the
display. The digits are named a, b, c, d, e, f, g and dp for the decimal point. To display 1, we need to
turn ON b and c and turn OFF the rest of them.
x
For common Anode, driven by Port 1 pins, the codes will be as follows:
Value
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
dp
g
f
e
d
c
b
a
7 segment code
0
1
1
0
0
0
0
0
0
C0 H
1
1
1
1
1
1
0
0
1
F9 H
2
1
0
1
0
0
1
0
0
A4 H
3
1
0
1
1
0
0
0
0
B0 H
4
1
0
0
1
1
0
0
1
99 H
5
1
0
0
1
0
0
1
0
92 H
6
1
0
0
0
0
0
1
0
82 H
7
1
1
1
1
1
0
0
0
F8 H
8
1
0
0
0
0
0
0
0
80 H
9
1
0
0
1
0
0
0
0
90 H
x
Do understand that some programmer may connect P1.0… P1.7 in the order dp – to – a instead of the
order a – to – dp. Then the nibbles will be interchanged.
x
Similarly, if common cathode method is used, then all values will be inverted as “1” will turn the LED
ON and “0” would then turn it OFF. Either way, the programmer creates the look up table as per her/his
circuit connections and stores them in the memory.
x
Let us say the table is stored at memory location 0400H. This is done using the following instructions:
ORG 0400H
Table
DB
C0H, F9H, A4H, B0H, 99H, 92H, 82H, F8H, 80H, 90H
This creates a look up table of 7 segment codes from ROM location 0400H
This creates a look up table of 7 segment codes from ROM location 0400H
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Address
7 segment code
Common Anode
7 segment code
Common Cathode
DPTR = 0400 Î
0400 H
C0 H
(Code of 0)
3F H
(Code of 0)
& A = 05
0401 H
F9 H
(Code of 1)
06 H
(Code of 1)
0402 H
A4 H
(Code of 2)
5B H
(Code of 2)
0403 H
B0 H
(Code of 3)
4F H
(Code of 3)
0404 H
99 H
(Code of 4)
66 H
(Code of 4)
0405 H
92 H
(Code of 5)
6D H
(Code of 5)
0406 H
82 H
(Code of 6)
7D H
(Code of 6)
0407 H
F8 H
(Code of 7)
07 H
(Code of 7)
0408 H
80 H
(Code of 8)
7F H
(Code of 8)
0409 H
90 H
(Code of 9)
67 H
(Code of 9)
@A+DPTR Î
x
4-5
Î A gets code of 5
Now, to get the code a number lets say 5, these are the steps to be performed:
MOV DPTR, #0400H
; Initialise DPTR as a pointer to starting of the look up table = 0400H
MOV A, #05H
; A has the number to be translated into its 7 segment code = 05H
MOVC A, @A+DPTR
; A gets the 7 segment code of 5 from the location 0400 + 5 = 0405H
z NOTES z
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# 4.1.4 Program to display a countdown from 9…0.
´ Interface a 7 segment LED to port 1 and write a program to display a countdown from 9 to 0.
There must be a delay of 1 second after each count displayed.
Algorithm
x
Create look up table at say 0400H
x
Initialise DPTR to look up table address
x
Initialise R7 as loop count of 10
x
Initialise R6 = 9 as the starting number to be displayed.
x
Move R6 into A
x
Translate A into its 7 segment code using the look up table
x
Put out A on port 1
x
Call a delay of 1 second
x
Decrement R6 (the number to be displayed)
x
Decrement R7, the loop count and loop back till R7 becomes 0.
Program
ORG 0400H
Table DB C0H, F9H, A4H, B0H, 99H, 92H, 82H, F8H, 80H, 90H
Back:
MOV DPTR, #0400H
; Initialise DPTR as a pointer to starting of the look up table = 0400H
MOV R7, #0AH
; Initialise R7 = 0AH, Loop count of 10
MOV R6, #09H
; Initialise R6 = 09H, Starting number to be displayed
MOV A, R6
; A Í Number to be displayed
MOVC A, @A+DPTR
; A gets 7 segment code of the number to be displayed
MOV P1, A
; P1 Í A, the number gets displayed on the 7 segment LED
ACALL Delay
; Call a delay of 1 second (Refer previous chapter
; for the delay routine)
Here:
DEC R6
; Decrement R6, the number to be displayed
DJNZ R7, Back
; Decrement loop count and jump to back 10 times
SJMP Here
; Program ends
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# 4.1.5 Program and Interface 4 digit Multiplexed 7 segment LED
´ Interface a 4 digit 7 segment multiplexed LED to 8051 and hence write a program to display
1605.
Interface
Fig. 4.1.1
x
A 4 digit 7 segment display is formed by multiplexing 4 digits on a single port say P1. 7 segment codes
for all 4 digits will be sent out on P1, one by one.
x
The lines of P2 will be used to select the digit to be activated.
x
Suppose we wish to display 1605 on the 4 digits. We will send the 7 segment codes in this manner…
Send code of “1” on P1 and Activate the 1st digit using P2.3
x
Send code of “6” on P1 and Activate the 2nd digit using P2.2 Send code of “0” on P1 and Activate the
3rd digit using P2.1 Send code of “5” on P1 and Activate the 4th digit using P2.0
x
Now, repeat the above cycle continuously, so fast that we beat “Persistence of Vision”.
x
The human eye needs roughly 80-100 milliseconds to register an event.
x
If we can loop back within that much time, the human eye will get the “Illusion” that all 4 digits are on
simultaneously though that’s not the real case. This is the same principle behind motion picture or
movies. The µC however is so fast that it can finish the loop in less than one millisecond.
x
We therefore take the liberty of adding a small delay (5-10 milliseconds) as each digit is displayed, to
allow the LEDs enough time to fire up. It still gives the µC enough time to finish the loop in the
stipulated time window.
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Algorithm
x
Create Look up table of 7 segment codes at say 0400H
x
Make DPTR point to the table
x
Send code of 1 on P1, Activate P2.3, Call delay of 10 milliseconds
x
Send code of 6 on P1, Activate P2.2, Call delay of 10 milliseconds
x
Send code of 0 on P1, Activate P2.1, Call delay of 10 milliseconds
x
Send code of 5 on P1, Activate P2.0, Call delay of 10 milliseconds
x
Repeat sending the above 4 codes
Program
ORG 0400H
Table DB C0H, F9H, A4H, B0H, 99H, 92H, 82H, F8H, 80H, 90H
First:
MOV
DPTR, #0400H ; Initialise DPTR as a pointer to starting of the look up table = 0400H
MOV
A, #01H
; A Í “1”
MOVC A, @A+DPTR
; A Í 7 segment code of “1”
MOV
P1, A
; Send code of “1” on P1
MOV
P2, #07H
; P2 = 0000 0111… this will select 1st digit on P2.3
ACALL Delay
; Call a delay of 10 millisecond
; (Refer previous chapter for delay routine)
Second: MOV
A, #06H
; A Í “6”
MOVC A, @A+DPTR
; A Í 7 segment code of “6”
MOV
P1, A
; Send code of “6” on P1
MOV
P2, #0BH
; P2 = 0000 1011… this will select 2nd digit on P2.2
ACALL Delay
; Call a delay of 10 millisecond (Refer previous chapter
; for delay routine)
Third:
MOV
A, #00H
; A Í “0”
MOVC A, @A+DPTR
; A Í 7 segment code of “0”
MOV
P1, A
; Send code of “0” on P1
MOV
P2, #0DH
; P2 = 0000 1101… this will select 3rd digit on P2.1
ACALL Delay
; Call a delay of 10 millisecond
; (Refer previous chapter for delay routine)
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Fourth: MOV
A, #05H
MOVC A, @A+DPTR
MOV
P1, A
4-9
8051 Interfacing & Applications
; A Í “5”
; A Í 7 segment code of “5”
; Send code of “5” on P1
MOV
P2, #0EH
ACALL Delay
; P2 = 0000 1110… this will select 4th digit on P2.0
; Call a delay of 10 millisecond (Refer previous chapter
; for delay routine)
SJMP First
; Repeat sending the above four codes
Select Digit
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
Value on Port 2
1st Digit
0
0
0
0
0
1
1
1
07 H
2nd Digit
0
0
0
0
1
0
1
1
0B H
3rd Digit
0
0
0
0
1
1
0
1
0D H
4th Digit
0
0
0
0
1
1
1
0
0E H
¯ Please Note :
9 Next time you see a multi-digit 7 segment LED E.g.:: railway station indicator, taxi meter etc. remove
9 your phone camera. The camera captures images at a much higher rate than human eye. Point the camera towards
the 7 segment LED. You will see the digits coming in a wavy sequence, especially when you shoot the video in slomo.
Common Cathode
For Common Cathode, driven by Port 1 pins, the codes will be as follows :
Value
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
dp
g
f
e
d
c
b
a
0
1
1
0
0
0
0
0
0
3F H
1
1
1
1
1
1
0
0
1
06 H
2
1
0
1
0
0
1
0
0
5B H
3
1
0
1
1
0
0
0
0
4F H
4
1
0
0
1
1
0
0
1
66 H
5
1
0
0
1
0
0
1
0
6D H
6
1
0
0
0
0
0
1
0
7D H
7
1
1
1
1
1
0
0
0
07 H
8
1
0
0
0
0
0
0
0
7F H
9
1
0
0
1
0
0
0
0
67 H
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8051 Interfacing and Applications
Syllabus
Interfacing ADC, DAC, Stepper motor, LCD, KBD matrix, 8255 PPI
! 5.1 8051 | 8-bit ADC with Temperature Sensor LM35
Q.
Draw the functional pin diagram of ADC 0808.
! 5.1.1 8-bit ADC 0809 | Pin Diagram
Vin(0) .... Vin(7)
:
8 analog input voltage
+ Vref ’ – Vref
:
Reference voltage range
8 bit data o/p
:
Digital data output after conversion
C, B, A
:
3 bits to select input channel out of 3 options
ALE
:
Latch channel number
SOC
:
Start of conversion
Fig. 5.1.1 : Pin diagram of ADC 0809
(Q. 1(c), May 19, 5 Marks)
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! 5.1.2 LM-35 | Temperature Sensor
x
Calibrated Directly in Celsius (Centigrade)
x
Linear + 10-mV/°C Scale Factor
x
0.5°C Ensured Accuracy (at 25°C)
x
Rated for Full −55°C to 150°C Range
x
Suitable for Remote Applications
x
Low-Cost Due to Wafer-Level Trimming
x
Operates From 4 V to 30 V
x
Less Than 60-µA Current Drain
Fig. 5.1.2 : LM-35 Temperature Sensor
! 5.1.3 ADC 0809 | Interfacing and Temperature Sensing program
! Interface
Explanation
1.
ADC 0809 is an 8 channel, 8 bit ADC. It converts analog voltage input into an 8 bit digital data output.
2.
To select one input out of 8 options, there are three select lines (C, B and A).
3.
We put a channel number on these lines (0…7) and latch it using ALE.
4.
Now we give SOC indicating start of conversion.
5.
The channel voltage is internally sampled and held into a capacitor.
6.
Conversion takes place internally using “Successive Approximations Algorithm”.
7.
Reference voltage for conversion is provided using +Vref and –Vref.
8.
The clock supply needed for conversion is given through CLK (typically ~ 1MHz).
9.
The end of conversion is indicated by the ADC using EOC signal.
10. Now we give the OE signal enabling 8-bit data output from the ADC to a port of 8051.
11. This data can be compared, stored or processed by the µC.
12. The process is repeated for subsequent channels, by changing the channel number.
13. ADCs have a vast use in the modern electronic world for Data Acquisition Systems.
They can be used for temperature sensing, voice recording, speed sensing etc.
! Algorithm:
x
Initialise P1 as input (For accepting data from ADC)
x
Initialise P0 as input for accepting EOC from ADC
x
Initialise R7 = 08H as loop count for 8 channels
x
Initialise R6 = 00H as channel number
x
Initialise R0 = 20H as pointer to RAM location
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x
Make ALE = 0, SOC = 0 and OE = 0 of ADC
x
Put channel number on port P2
x
Make ALE = 1, call a delay of 10 milliseconds and then make ALE = 0
x
Make SOC = 1 to start conversion
x
Wait for EOC to become 1
x
Make OE = 1 to get the data into P1
x
Store the data into RAM location pointed by R0
x
Increment R6 to go to next channel
x
Increment R0 to point to next location
x
Decrement count in R7 and loop for all channels
! Program
Back :
Wait:
Here:
MOV P1, #0FFH
; P1 ç input port (data input)
MOV P0, #0FFH
; P0 ç input port (EOC input)
MOV R7, #08H
; R7 ç 08H (Loop count, 8 channels)
MOV R6, #00H
; R6 ç 00H (Channel number)
MOV R0, #20H
; R0 ç 20H (Pointer to Internal RAM location 20H)
CLR P3.0
; Make ALE = 0
CLR P3.1
; Make SOC = 0
CLR P3.2
; Make OE = 0
MOV P2, R6
; P2 ç Channel Number
SETB P3.0
; Make ALE = 1
ACALL Delay
; Call 10 millisecond Delay to latch the channel number
CLR P3.0
; Make ALE = 0
SETB P3.1
; Make SOC = 1
JNB P0.0, Wait
; Wait for EOC to become 1
SETB P3.2
; Make OE = 1
MOV A, P1
; Read converted data into A register
MOV @R0, A
; Store converted data into Internal RAM location pointed by R0
INC R6
; Increment Channel number
INC R0
; Increment location pointer
DJNZ R7, Back
; Read converted data into A register
SJMP Here
; End the program
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! Interfacing of ADC with 8051
Fig. 5.1.3 : Interfacing of ADC with 8051
! 5.2 8051 | 8-bit DAC Interfacing
! 5.2.1 Interface DAC 0808 to 8051
x
DAC is an 8 bit Digital to Analog Converter.
x
It can convert an 8 bit digital data input into an analog voltage output.
x
Reference voltage for conversion is provided using +Vref and –Vref.
x
The output of the DAC is actually in current form.
x
This can be converted into voltage using an op-amp IC 741.
x
DACs are used in various applications such as PWM, Motor control Applications, DSP etc.
x
For waveform displays, we connect the output to a display device like a CRO.
x
By simple programming we can generate several types of wave forms like
x
Ramp, Saw-tooth, Triangular waveform etc.
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! Interfacing of ADC with 8051
Fig. 5.1.3 : Interfacing of ADC with 8051
! 5.2 8051 | 8-bit DAC Interfacing
! 5.2.1 Interface DAC 0808 to 8051
x
DAC is an 8 bit Digital to Analog Converter.
x
It can convert an 8 bit digital data input into an analog voltage output.
x
Reference voltage for conversion is provided using +Vref and –Vref.
x
The output of the DAC is actually in current form.
x
This can be converted into voltage using an op-amp IC 741.
x
DACs are used in various applications such as PWM, Motor control Applications, DSP etc.
x
For waveform displays, we connect the output to a display device like a CRO.
x
By simple programming we can generate several types of wave forms like
x
Ramp, Saw-tooth, Triangular waveform etc.
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8051 Interfacing and Applications
Fig. 5.2.1 : DAC 0808 interfacing with 8051
! 5.2.2 Program to Generate Staircase Waveform
! Interface
Refer Previous Section, draw the exact same diagram.
Fig. 5.2.2 : Staircase waveform
! Algorithm
x
Initialise A as 00H
x
Send A on P1
x
Call delay (100 milliseconds)
x
Increment A
x
Loop till A crosses FFH and rolls back to 00H.
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8051 Interfacing and Applications
! Program
Back :
Here :
MOV A, #00H
; A ç 00H
MOV P1, A
; P1 ç A register
ACALL Delay
; Call a delay of 100 milliseconds
INC A
; Increment A
JNZ Back
; Loop till A rolls back to 00H.
SJMP Here
; End the program
" Please Note
! This is truly a fun program to do in practical sessions. For taller steps, increment A by 2 (or even higher).
! For wider or narrower steps, increase or reduce the delay duration respectively.
! All these waveforms like staircase, ramp, saw-tooth, triangle etc. sound very boring when you only treat them as
just waveforms. But if you imagine controlling external devices using these waveforms, you will understand WHY
you are required to learn these programs.
! Imagine if this output was connected to a bulb. It will turn on with increasing levels of brightness on each step.
Smoothen the output and now you will get theatre dimming and glowing effect.
! Connect the output to the spout of a fountain and you will see the water jet rising higher and higher with increasing
intensity, and so on.
! 5.2.3 Program to generate Ramp waveform
x
Same as a staircase, just reduce the delay to 5-10 milliseconds
x
Program : Same as a staircase, just reduce the delay to 5-10 milliseconds
Fig. 5.2.3 : Ramp waveform
! 5.2.4 Program to generate Saw-tooth waveform
! Algorithm
x
Initialise A as 00H
x
Send A on P1
x
Call delay (10 milliseconds)
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x
Increment A
x
Loop infinitely, so that the output goes from
x
00H gradually to FFH then drops to 00H and repeats
8051 Interfacing and Applications
! Program
Back:
MOV A, #00H
; A ç 00H
MOV P1, A
; P1 ç A register
ACALL Delay
; Call a delay of 10 milliseconds
INC A
; Increment A
SJMP Back
; Loop back, infinitely
Fig. 5.2.4 : Saw tooth waveform
! 5.2.5 Program to Generate Triangular Waveform
Write an assembly language program to generate triangular wave using DAC
Q.
interfacing with 8051 micro controller.
(Q. 4(A), Dec. 18, 10 Marks)
Write a program to generate a triangular waveform using DAC and 8051. Draw the
Q.
interfacing circuit diagram.
(Q. 4(B), Dec. 19, 10 Marks)
! Algorithm
x
Initialise A as 00H
x
Send A on P1
x
Call delay (10 milliseconds)
x
Increment A gradually from 00H…FFH and stop
x
Repeat the process decrementing A from FEH…01H.
x
Repeat the whole process, infinitely.
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! Program
MOV A, #00H
Back1 : MOV P1, A
; A ç 00H
; P1 ç A register
ACALL Delay
; Call a delay of 10 milliseconds
INC A
; Increment A
JNZ Back1
; Loop till A rolls back to 00H.
MOV A, #0FEH
; A ç FEH
Back2 : MOV P1, A
; P1 ç A register
ACALL Delay
; Call a delay of 10 milliseconds
DEC A
; Decrement A
JNZ Back2
; Loop till A reduces to 00H (outputs 01H).
SJMP Back1
; Loop back, infinitely
Fig. 5.2.5 : Triangular waveform
! 5.3 8051 | Stepper Motor
Q.
Discuss working of stepper motor.
(Q. 1(B), Dec. 18, 5 Marks)
! Introduction to Stepper Motor
x
Stepper motors are high precision devices that can rotate
in tiny accurate steps, controlled by the program.
Applications where step wise rotation is required like
Robotic arm, Printer etc. prefer Stepper motors instead of
DC motors.
x
They are very easy to interface and program.
x
Besides, they can easily switch between clockwise and
anticlockwise motion.
x
Fig. 5.3.1
A Stepper motor is formed by four stator magnets and one rotor magnets.
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x
We need to control the four stator by giving a sequence of 0s and 1s. that decides the movement of the
rotor, and hence the stepper motor on the whole.
x
For this we simply need to connect four lines of a Port of 8051 say P1.
! Need for a driver – ULN2003
x
Stepper motors are controlled by our µC
8051.
x
8051 however sources/sinks current around 15mA at voltage 5V.
x
A Stepper motor however requires much higher current and voltages to drive real world appliances. For
this purpose we use drivers.
x
A typical Driver like ULN2003 can provide a max current around 500mA at voltage up to 50V. We
could also use a relay driver like L293D.
! Interface
Fig. 5.3.2
! Working
x
Pins P1.0… P1.3 of 8051 are used to control the motor via ULN2003.
x
By sending values on these pins we rotate the motor in clockwise and anti-clockwise direction. The
motor is connected at the output of ULN2003.
x
The logic table for controlling the motor movement is given below.
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! Wave Step mode
x
Here we activate only one stator. This uses less power but also produces low torque in the rotor’s
movement as only one end of the magnet is pulled.
x
This mode is rarely used due to its low torque.
! Full Step mode
x
This is the most commonly used mode. Here we activate only two stators at a time. This uses more
power but also produces double the torque in the rotor’s movement as both ends of the magnet are
pulled.
x
The Excitation sequence for the stators is as shown :
P1.3 (D)
P1.2 (C)
P1.1 (B)
P1.0 (A)
Value
0
0
1
1
3H
0
1
1
0
6H
1
1
0
0
CH
1
0
0
1
9
H
" Please Note
! Though we are interested in only 4 lines of P1, if we connect the other four lines to ground then we can obtain these
patterns by simply rotating the number.
P1.7
(X)
P1.6
(X)
P1.5
(X)
P1.4
(X)
P1.3
(D)
P1.3
(D)
P1.3
(D)
P1.3
(D)
Value
0
0
1
1
0
0
1
1
33 H
0
1
1
0
0
1
1
0
66 H
1
1
0
0
1
1
0
0
CC H
1
0
0
1
1
0
0
1
99 H
These are irrelevant
Rotate Left
Just observe these bits
! Half Step mode
x
This mode is used when we want better accuracy and more steps in the movement. Full step
produces 4 steps in the cycle but half step produces 8 steps.
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x
Here we activate two stators, then only one stator then two stators and so on.
x
This allows half steps as in the rotor not only stops at every stator’s position but also stops in inbetween the stators, being pulled (or repelled) by both stators equally.
x
The Excitation sequence for the stators is as shown:
P1.3 (D)
P1.2 (C)
P1.1 (B)
P1.0 (A)
Value
0
0
0
1
1H
0
0
1
1
3H
0
0
1
0
2H
0
1
1
0
6H
0
1
0
0
4H
1
1
0
0
CH
1
0
0
0
8H
1
0
0
1
9H
" Please note
! In some other literature you may find the four stator lines, ABCD connected in a different way and hence the
numbers may appear different but the logic remains the same. The idea is, in one excitation we must activate one
stator, in the next we must activate the current and the next stator and repeat the process.
! Also, unlike full step, these codes cannot be derived by simply rotating one of the numbers. Hence we must first
store these codes in memory in the form of a… yes you guessed it right! A look up table at 0400H.
Org 0400H
Table DB 01H, 03H, 02H, 06H, 04H, 0CH, 08H, 09H
! 5.3.1 Program to Rotate a Stepper Motor
# Write a program to rotate the Stepper motor continuously using half step 8 sequence.
Assume look up table at 0400H …
! Algorithm
x
Initialise DPTR = 0400H to point to look up table
x
Initialise R7 = 08H as step counter of 8
x
Initialise R6 = 00H as index in the table
x
Take index into A from R6
x
Get excitation code from look up table into A register
x
Put the code into P1 from A register
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x
Call a delay of 1 second
x
Increment R6 for next index
x
Decrement R7 and loop till 8 counts
x
Now Initialise everything again and loop continuously
8051 Interfacing and Applications
! Program
Again :
Back :
MOV DPTR, #0400H
; Pointer to look up table
MOV R7, #08H
; Count of 8
MOV R6, #00H
; Index of 0
MOV A, R0
; Take Index into A
MOVC A, @A+DPTR
; Get excitation code from look up table into A
MOV P1, A
; Put excitation code on P1
ACALL Delay
; Refer previous chapter for a 1 second delay program
INC R6
; Next index
DJNZ R7, Back
; Loop 8 times
SJMP Again
; Repeat the whole process to rotate the motor continuously
# Assume 1 step causes a rotation of 1.8 degrees. Rotate the stepper motor to 117 degrees.
! Use full step mode.
Calculation :
1 step = 1.8 degrees
x steps = 117 degrees.
x = (117/1.8) = 65d = 41H. This is our loop count.
! Algorithm:
x
Initialise R7 = 41H as loop count of 65d
x
Initialise A register as 33H (any one of the four excitation codes to be used in full step mode)
x
Put the code into P1 from A register
x
Call a delay of 10 milliseconds
x
Rotate A to form the next code
x
Decrement R7 and loop till 65 counts
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8051 GENERAL PROGRAMMING
Q1
WAP to add the contents of Internal RAM locations 40H and 41H. Store
Result at 42H and Carry at 43H
SOLN:
SKIP:
HERE:
MOV 43H, #00H
MOV A, 40H
ADD A, 41H
JNC SKIP
INC 43H
MOV 42H, A
SJMP HERE
Q2
WAP to multiply the numbers B2H and 2FH. Store Result in registers R0
(LSB) and R1 (MSB) of Bank 2.
SOLN:
HERE:
MOV A, #0B2H
MOV 0F0H, #2FH
MUL AB
SETB PSW.4
CLR PSW.3
MOV R0, A
MOV R1, 0F0H
SJMP HERE
Q3
WAP to add a series of 10 numbers. The series begins from location 20H
in Internal RAM. Store the result at locations 30 and 31H.
SOLN:
MOV R0, #20H
MOV R1, #0AH
CLR A
MOV 0F0H, #00H
ADD A, @R0
JNC SKIP
INC OFOH
INC R0
DJNZ R1, REPEAT
MOV 30H, A
MOV 31H, 0F0H
SJMP HERE
REPEAT:
SKIP:
HERE:
; Initialize Carry as “0”
; Read first number
; Add second number
; If no Carry, directly store the Sum
; Store Carry as “1”
; Store Sum
; End of program
; Read first number
; Read second number
; Multiply the operands
; Select Bank 2
; Store LSB of result
; Store MSB of result
; End of program
; Initialize Source address
; Initialize count of 10
; A register will accumulate the Sum
; B register will accumulate the Carry
; Add the current element
; If no carry, then directly proceed ahead
; If there is a carry, increment B Register
; Increment source address
; Decrement count. If Count is NOT ZERO then repeat.
; Store Sum
; Store Carry
; End of program
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MICROPROCESSORS 8051 & ARM
Author: Bharat Acharya
Sem V – EXTC
Mumbai 2018
Q4
WAP to add a series of 10 “BCD” numbers. The series begins from
location 20H. Store the result at locations 30 and 31H.
SOLN:
HERE:
MOV R0, #20H
MOV R1, #0AH
CLR A
MOV 0F0H, #00H
ADD A, @R0
DA A
JNC SKIP
INC OFOH
INC R0
DJNZ R1, REPEAT
MOV 30H, A
MOV 31H, 0F0H
SJMP HERE
Q5
WAP to add a series of 10 numbers. The series begins from location
2000H in External RAM. Store the result at locations 3000 and 3001H.
SOLN:
MOV DPTR, #2000H
MOV R1, #0AH
CLR A
MOV 0F0H, #00H
MOV R0, #00H
MOVX A, @DPTR
ADD A, R0
JNC SKIP
INC OFOH
INC DPTR
MOV R0, A
DJNZ R1, REPEAT
MOV DPTR, #3000H
MOVX @DPTR, A
INC DPTR
MOV A, OFOH
MOVX @DPTR, A
SJMP HERE
REPEAT:
SKIP:
REPEAT:
SKIP:
HERE:
; Initialize Source address
; Initialize count of 10
; A register will accumulate the Sum
; B register will accumulate the Carry
; Add the current element
; Decimal adjust as the operands were BCD numbers
; If no carry, then directly proceed ahead
; If there is a carry, increment B Register
; Increment source address
; Decrement count. If Count is NOT ZERO then repeat.
; Store Sum
; Store Carry
; End of program
; Initialize Source address
; Initialize count of 10
; “A” will accumulate the Sum, and ALSO get the data from Ext. RAM
; B register will accumulate the Carry
; R0 will be used to
; Get the data from Ext RAM
; Add the data to the previous sum
; If no carry, then directly proceed ahead
; If there is a carry, increment B Register
; Increment source address
; Store current Sum in R0 from next iteration
; Decrement count. If Count is NOT ZERO then repeat.
; DPTR gets address to store the Sum
; Store Sum
; DPTR gets address to store the Carry
; Transfer Carry from B to A register
; Store Carry
; End of program
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Q6
WAP to copy the value 25H to all locations from 2000H to 2100H in the
External RAM.
MOV A, #25H
; Number stored in A as MOVX works only on “A”
MOV R0, #00H
; R0 will contain the count
MOV DPTR, #2000H
; DPTR contains the Dest address
BACK: MOVX @DPTR, A
; Store at Ext RAM location pointed by DPTR
INC DPTR
; Inc Dest address
INC R0
; Inc Count
CJNE R0, #00H, BACK ; Check if RO has again become 0. If not: repeat
MOVX @DPTR, A
; Store at 2100H
HERE: SJMP HERE
; End of program
8
In the above program, you must remember that an 8-bit register like R0 will give 2 i.e. 256 counts,
Hence the extra step after the loop is required. #Please refer Bharat Sir's Lecture Notes for this ....
SOLN:
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Microcontrollers & Applications (MU-Sem. 6-E&TC)
4-10
8051 Interfacing & Applications
 4.2 8051 | 16x2 Generic LCD Display
Univ. Q.
Interface LCD to 8051 and write assembly language program to display message
“HELLO” on it.
Univ. Q.
(MU - Dec. 17, 10 Marks)
Explain LCD interfacing with 8051 and write assembly language program to display
message “HI” on it. Draw the connection diagram of 8051 with LCD.
(MU - May 19, 10 Marks)
Univ. Q.
Interface LCD to 8051 and write a program to display the message “LCD” on it.
Draw the connection diagram of 8051 with LCD.
(MU - Dec. 19, 10 Marks)
x
LCD displays are far more useful than 7 segment LEDs because they can be used to display text adequately.
Complex charecters like W, M, K, Q etc. can be easily displayed using a matrix of pixels .
x
In most cases 5x7 matrix is used to display one character, 5 columns and 7 rows.
An LCD Unit comes with an LCD display and its own controller. The entire unit is interfaced with 8051 as
shown :
Pin Description of the LCD unit
Pin Number
Function
1
Ground
2
Vcc
3
Brightness (Contrast) Adjust
4
Register Select | 0: Command | 1: Data
5
Read Write Select | 0: Write | 1: Read
6
Latch Enable | Falling Edge Latches Command/ Data
7-14
8-bit Command or Data Value
Typical LCD Command Codes
Command Value
Function
38 H
Initialise 16 character, 2 rows 5x7 matrix display layout
0F H
Display ON, Cursor ON, Cursor Blinking
01 H
Clear Display (Clears the On-Chip DRAM of the LCD Unit)
06 H
Cursor Increment Mode (Moves Cursor from Left to Right)
80 H
Cursor Home Command ()
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4-11
8051 Interfacing & Applications
Steps to send Command or Data to the LCD Unit
Steps for sending Command
Steps for sending Data
x
Put out the command on the port (P1)
x
Put out the data on the port (P1)
x
Make Register Select = 0 (Command)
x
Make Register Select = 1 (Data)
x
Make R/W = 0 (As we are writing)
x
Make R/W = 0 (As we are writing)
x
Make Latch Enable = 1
x
Make Latch Enable = 1
x
Make Latch Enable = 0 (Falling Edge)
x
Make Latch Enable = 0 (Falling Edge)
x
Call a delay of 10 milliseconds
x
Call a delay of 10 milliseconds
´ Interface a 16x2 line LCD Unit to 8051 and hence write a program to display “Happy Diwali”
Interface
Fig. 4.2.1
Algorithm
x
Create Look up table of ASCII codes of Happy Diwali at say 0400H
x
Make DPTR point to the table
x
Initialise LCD unit by sending command codes: 38H, 0FH, 01H, 06H, 80H
x
Initialise R7 with Loop count of 12 (Happy Diwali has 12 characters including the space)
x
Initialise R6 with index of 0
x
Using R6 as index, obtain ASCII code of every character from look up table into A
x
Send this code as Data to the LCD unit
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Microcontrollers & Applications (MU-Sem. 6-E&TC)
4-12
x
Increment Index R6
x
Decrement Loop count R7 and Loop till all characters re displayed
8051 Interfacing & Applications
Program : ORG 0400H
Table DB “Happy Diwali”
Initialise :
MOV
A, #38H
ACALL Command
; Call the “Command” function with the command
; value 38H in A register
MOV
A, #0FH
ACALL Command
; Call the “Command” function with the command
; value 0FH in A register
MOV
A, #01H
ACALL Command
; Call the “Command” function with the command
; value 01H in A register
MOV
A, #06H
ACALL Command
; Call the “Command” function with the command
; value 06H in A register
MOV
A, #80H
ACALL Command
; Call the “Command” function with the command
; value 80H in A register
MOV
DPTR, #0400H
; Initialise DPTR as a pointer to starting of the
; look up table = 0400H
Display:
MOV
R7, #0CH
; Initialise R7 with Loop Count of 12
MOV
R6, #00H
; Initialise R6 with Index of 0
MOV
A, R6
; A Í Index from R6
MOVC A, @A+DPTR
; A Í ASCII code from Look Up Table
ACALL Data
; Call the “Data” function with the ASCII value in A
; register
INC
R6
; Increment the Index
DJNZ
R7, Display
; Loop till all 12 characters are displayed
Here:
SJMP
Here
; End the program
Command :
MOV
P1, A
; Put Command value in P1 from A Register
CLR
P2.0
; Make Register Select = 0 for Command
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8051 Interfacing & Applications
CLR
P2.1
; Make Read/Write Select = 0 for Write
SETB
P2.2
; Make Latch Enable = 1
CLR
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
MOV
P1, A
; Put Command value in P1 from A Register
CLR
P2.0
; Make Register Select = 0 for Command
CLR
P2.1
; Make Read/Write Select = 0 for Write
SETB
P2.2
; Make Latch Enable = 1
CLR
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
RET
Command :
ACALL Delay
; Call a delay of 10 milliseconds
RET
Data:
MOV
P1, A
; Put Data value (ASCII Code) in P1 from A Register
SETB
P2.0
; Make Register Select = 1 for Data
CLR
P2.1
; Make Read/Write Select = 0 for Write
SETB
P2.2
; Make Latch Enable = 1
CLR
P2.2
; Make Latch Enable = 0 (This produces a Falling Edge)
ACALL Delay
; Call a delay of 10 milliseconds
RET
 4.3 8051 | Relay and DC Motor
Introduction to DC Motor
x
DC motors are widely used at places where constant speed is required. They are very easy to
interface and program.
x
Besides, they can easily switch between clockwise and anticlockwise motion. Their typical usage is
in fans, blowers, conveyor belts, pumps, lifts etc.
x
A DC motor simply requires two pins to control its movements.
x
By sending a 01 or a 10 on these pins we can move the motor clockwise or anticlockwise. Sending
a 11 or a 00 on the two pins will stop the motor.
Need for a relay – L293D
x
DC motors are controlled by our µC 8051.
x
8051 however sources/sinks current around 15mA at voltage 5V.
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8051 Microcontroller
Simulation Programs
for Lab Practicals
`
Link to download EdSim Simulator: https://www.edsim51.com
Q1: Write a program to add two 8bit numbers stored at internal Ram
locations 20H and 21H. Store Sum at 22H and Carry at 23H.
Program:
org 0
start:
MOV R2, #00H
MOV A, 20H
ADD A, 21H
JNC Skip
INC R2
Skip:
MOV 22H, A
MOV 23H, R2
; perform the addition
; only when there is a carry
; store sum from A to 22
; store carry from R2 to 23
here: SJMP here
end
Q2: Write a program to subtract two 8bit numbers stored at internal
Ram locations 20H and 21H. Store Result at 22H and Borrow at 23H.
Program:
org 0
start:
MOV R2, #00H
MOV A, 20H
ADD A, 21H
JNC Skip
INC R2
Skip:
MOV 22H, A
MOV 23H, R2
; perform the subtraction
; only when there is a borrow
; store result from A to 22
; store borrow from R2 to 23
here: SJMP here
end
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8051 Microcontroller
Simulation Programs
for Lab Practicals
Q3: Write a program to multiply two 8bit numbers stored at internal
Ram locations 20H and 21H. Store Result at 22H and 23H.
Program:
org 0
start:
MOV A, 20H
MOV B, 21H
MUL AB
MOV 22H, A
MOV 23H, B
; take first number in A
; take second number in B
; Multiply the numbers
; store lower byte of result (A) at 22H
; store higher byte of result (B) at 23H
here: SJMP here
end
Q4: Write a program for 8bit division. Dividend at internal Ram location
20H, Divisor at 21H. Store quotient at 22H and remainder23H.
Program:
org 0
start:
MOV A, 20H
MOV B, 21H
DIV AB
MOV 22H, A
MOV 23H, B
; take dividend in A
; take divisor in B
; divide the numbers
; store quotient (A) at 22H
; store remainder (B) at 23H
here: SJMP here
end
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
`
Block Transfer Program
Q1: Write a program to transfer a block of 10 bytes form loc 20H in Internal
RAM to loc 30H in Internal RAM
Program:
org 0
MOV R0, #20H
MOV R1, #30H
MOV R7, #0AH
; source pointer
; destination pointer
; count of 10d
BACK:
MOV A, @R0
MOV @R1, A
INC R0
INC R1
DJNZ R7, BACK
; take data from source
; store data at destination
; increment source address
; increment destination address
; decrement count and loop back
HERE:
END
SJMP HERE
START:
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
Inverted Block Transfer Program
Q2: Write a program to perform and inverted block transfer of 10 bytes form
loc 20H in Internal RAM to loc 30H in Internal RAM
Program:
org 0
MOV R0, #20H
MOV R1, #39H
MOV R7, #0AH
; source pointer at beginning
; destination pointer at end
; count of 10d
BACK:
MOV A, @R0
MOV @R1, A
INC R0
DEC R1
DJNZ R7, BACK
; take data from source
; store data at destination
; increment source address
; decrement destination address
; decrement count and loop back
HERE:
END
SJMP HERE
START:
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
Highest Number Program
Q3: Write a program to find the highest number in a series of 10 numbers
stored at Internal Ram loc 20H. Store result at 30H.
Program:
START:
BACK:
NEXT:
SKIP:
HERE:
END
org 0
MOV R0, #20H
MOV R7, #0AH
CLR A
; pointer to data
; count of 10d
; A = 0, the assumed highest number
MOV B, @R0
CJNE A, B, NEXT
JNC SKIP
MOV A, B
INC R0
DJNZ R7, BACK
; B = current number from the series
; Compare A and B… (A-B)
; if no carry, A is already higher, skip
; else copy B to A… new highest number
; point to next number
; decrement count and loop back
MOV 30H, A
SJMP HERE
; Store result (highest number) at 30H
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
Note: For finding the lowest number there are two minor changes in the
program…
Initialise A with FF instead of 0
Change JNC Skip to JC Skip
Program for finding the lowest number….
START:
BACK:
NEXT:
SKIP:
HERE:
END
org 0
MOV R0, #20H
MOV R7, #0AH
MOV A, #0FFH
; pointer to data
; count of 10d
; A = FF, the assumed lowest number
MOV B, @R0
CJNE A, B, NEXT
JC SKIP
MOV A, B
INC R0
DJNZ R7, BACK
; B = current number from the series
; Compare A and B… (A-B)
; if carry, A is already lower, skip
; else copy B to A… new highest number
; point to next number
; decrement count and loop back
MOV 30H, A
SJMP HERE
; Store result (highest number) at 30H
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
Sorting Program
Q4: Write a program to sort a series of 5 numbers stored at Internal Ram loc
20H.
Program:
org 0
START:
BACK2:
MOV R7, #04H
MOV R6, #04H
MOV R0, #20H
; outer loop count
; inner loop count
; pointer
BACK1:
MOV A, @R0
INC R0
MOV B, @R0
CJNE A, B, NEXT
; A = 1st No
; R0 points to 2nd No
; B = 2nd No
; Compare A and B… (1st No – 2nd No)
NEXT:
JC SKIP
MOV @R0, A
DEC R0
MOV @R0, B
INC R0
; if no carry, already correct order, skip
; store 1st No (A) to 2nd position (R0)
; R0 points to 1st position
; store 2nt No (B) to 1st position (R0)
; R0 points to 2nd position
SKIP:
DJNZ R6, BACK1
DJNZ R7, BACK2
; do inner loop R6 times
; do outer loop R7 times
HERE:
SJMP HERE
END
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8051 Microcontroller
Simulation Programs for
Lab Practicals Part 2
For Descending, simply change JC skip to JNC Skip
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8051
MCQ - 2021
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8051 Microcontroller
MCQ 2020-21
Section 1
Introduction and Architecture of 8051
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8051 Microcontroller
MCQ 2020-21
Q1)
8051 is an 8-bit processor because…
(a) It has an 8-bit data bus
(b) It has an 8-bit ALU
(c) It has an 8-bit address bus
(d) It has an 8-bit control bus
Answer…
(a) It has an 8-bit data bus
(b) It has an 8-bit ALU
(c) It has an 8-bit address bus
(d) It has an 8-bit control bus
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q2)
The only I/O Port without an alternate
function is…
(a) Port 0
(b) Port 1
(c) Port 2
(d) Port 3
Answer…
(a) Port 0
(b) Port 1
Important Type
of Question
(c) Port 2
(d) Port 3
Video Reference: 8051 | Pin Diagram
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8051 Microcontroller
MCQ 2020-21
Q3)
Internal RAM of 8051 is of size…
(a) 128 bits
(b) 128 Bytes
(c) 4 KB
(d) 64 KB
Answer…
(a) 128 bits
(b) 128 Bytes
(c) 4 KB
(d) 64 KB
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q4)
Internal ROM of 8051 is of size…
(a) 128 bits
(b) 128 Bytes
(c) 4 KB
(d) 64 KB
Answer…
(a) 128 bits
(b) 128 Bytes
(c) 4 KB
(d) 64 KB
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q5) Which statement is true…
(a) DPTR contains data
(b) DPTR contains instruction
(c) DPTR contains address of instruction
(d) DPTR contains address of data
Answer…
(a) DPTR contains data
(b) DPTR contains instruction
(c) DPTR contains address of instruction
(d) DPTR contains address of data
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q6) MSB of a number indicates …
(a) Sign of the number
(b) Parity of the number
(c) If the number is Even or Odd
(d) The power of the number
Answer…
(a) Sign of the number
(b) Parity of the number
(c) If the number is Even or Odd
(d) The power of the number
Video Reference: 8051 | Flag Register
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8051 Microcontroller
MCQ 2020-21
Q7) What is the range of an 8-bit signed number?
(a) 0…255
(b) -127…+128
(c) -128….+128
(d) -128…+127
Answer…
(a) 0…255
(b) -127…+128
(c) -128….+128
(d) -128…+127
Video Reference: 8051 | Flag Register
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8051 Microcontroller
MCQ 2020-21
Q8) How is -01H stored in “A” register?
(a) – 0000 0001
(b)
1000 0001
(c)
1111 1111
(d)
1111 1110
Answer…
(a) – 0000 0001
(b)
1000 0001
(c)
1111 1111
(d)
1111 1110
Important Type
of Question
Video Reference: 8051 | Flag Register
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8051 Microcontroller
MCQ 2020-21
Q9) The address range of Internal RAM is…
(a) 00H… FFH
(b) 00H… 7FH
(c) 80H… FFH
(d) 0000H… 0FFFH
Answer…
(a) 00H… FFH
Important Type
(b) 00H… 7FH
of Question
(c) 80H… FFH
(d) 0000H… 0FFFH
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q10) The address range of Internal ROM is…
(a) 00H… FFH
(b) 00H… 7FH
(c) 80H… FFH
(d) 0000H… 0FFFH
Answer…
Important Type
(a) 00H… FFH
of Question
(b) 00H… 7FH
(c) 80H… FFH
(d) 0000H… 0FFFH
Video Reference: 8051 | Architecture
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8051 Microcontroller
MCQ 2020-21
Q)
Should you learn by cheating / piracy?
(a) Yes, I am raised like this!
(b) Who cares about the teacher’s effort? I am
cheap!
(c) Education by cheating will still help me!
(d) NO. We should support good teachers who
work so hard yet charge very less!
Answer…
I leave this answer to YOU!
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8051 Microcontroller
MCQ 2020-21
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8051 Microcontroller
MCQ 2020-21
Section 2
Addressing Modes and Instruction Set
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15
8051 Microcontroller
MCQ 2020-21
Q11) Immediate addressing mode means
(a) Data is given in the instruction
(b) Address is given in the instruction
(c) Data is given in registers
(d) Address is given using a register
Answer…
(a) Data is given in the instruction
(b) Address is given in the instruction
(c) Data is given in registers
(d) Address is given using a register
Video Reference: 8051 | Addressing Modes
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8051 Microcontroller
MCQ 2020-21
Q12) ADD A, R0 is an example of
(a) Immediate Addressing mode
(b) Register Addressing mode
(c) Direct Addressing mode
(d) Indirect Addressing mode
Answer…
(a) Immediate Addressing mode
(b) Register Addressing mode
(c) Direct Addressing mode
(d) Indirect Addressing mode
Video Reference: 8051 | Addressing Modes
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8051 Microcontroller
MCQ 2020-21
Q13) In which addressing mode we give the
address of the operand?
(a) Immediate Addressing mode
(b) Register Addressing mode
(c) Direct Addressing mode
(d) Indirect Addressing mode
Answer…
(a) Immediate Addressing mode
(b) Register Addressing mode
(c) Direct Addressing mode
(d) Indirect Addressing mode
Video Reference: 8051 | Addressing Modes
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8051 Microcontroller
MCQ 2020-21
Q14) Indirect addressing mode is used when we
want to…
(a) Not disclose the address
(b) Access a series of locations
(c) Access the odd bank
(d) Indirectly end the program
Answer…
(a) Not disclose the address
(b) Access a series of locations
(c) Access the odd bank
(d) Indirectly end the program
Video Reference: 8051 | Addressing Modes
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8051 Microcontroller
MCQ 2020-21
Q15) Assume internal RAM location values…
[20] = 10H,
[21] = 20H,
[22] = 30H
[23] = 40H,
[24] = 50H,
[25] = 60H
What will happen after...
MOV A, 20H
MOV 21H, A
(a)
(b)
(c)
(d)
[21] = 20H, A = 20H
[21] = 21H, A = 20H
[21] = 10H, A = 10H
[21] = 20H, A = 10H
Important Type
Answer…
(a)
(b)
(c)
(d)
[21] = 20H, A = 20H
[21] = 21H, A = 20H
[21] = 10H, A = 10H
[21] = 20H, A = 10H
Video Reference: 8051 | Simulation Programs
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20
8051 Microcontroller
MCQ 2020-21
Q16) Assume internal RAM location values…
[20] = 10H,
[21] = 20H,
[22] = 30H
[23] = 40H,
[24] = 50H,
[25] = 60H
What will happen after...
MOV A, 20H
INC A
MOV 21H, A
INC A
MOV 22H, 20H
Important Type
(a)
(b)
(c)
(d)
[21] = 11H, [22] = 12H
[21] = 11H, [22] = 20H
[21] = 10H, [22] = 30H
[21] = 11H, [22] = 10H
Answer…
(a)
(b)
(c)
(d)
[21] = 11H, [22] = 12H
[21] = 11H, [22] = 20H
[21] = 10H, [22] = 30H
[21] = 11H, [22] = 10H
Video Reference: 8051 | Simulation Programs
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21
8051 Microcontroller
MCQ 2020-21
Q17) Assume internal RAM location values…
[20] = 10H,
[21] = 20H,
[22] = 30H
[23] = 40H,
[24] = 50H,
[25] = 60H
What will happen after...
MOV R0, 20H
MOV A, R0
MOV 21H, A
MOV A, @R0
MOV 22H, A
Important Type
(a)
(b)
(c)
(d)
[21] = 20H, [22] = 0AH
[21] = 10H, [22] = 20H
[21] = 20H, [22] = 10H
[21] = 20H, [22] = 20H
Answer…
(a)
(b)
(c)
(d)
[21] = 20H, [22] = 0AH
[21] = 10H, [22] = 20H
[21] = 20H, [22] = 10H
[21] = 20H, [22] = 20H
Video Reference: 8051 | Simulation Programs
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22
8051 Microcontroller
MCQ 2020-21
Q18) Assume internal RAM location values…
[20] = 10H,
[21] = 20H,
[22] = 30H
[23] = 40H,
[24] = 50H,
[25] = 60H
What will happen after...
MOV R0, #20H
MOV A, @R0
INC A
INC R0
MOV @R0, A
Important Type
(a)
(b)
(c)
(d)
[21] = 11H, R0 = 11H
[21] = 10H, R0 = 21H
[21] = 11H, R0 = 10H
[21] = 11H, R0 = 21H
Answer…
(a)
(b)
(c)
(d)
[21] = 11H, R0 = 11H
[21] = 10H, R0 = 21H
[21] = 11H, R0 = 10H
[21] = 11H, R0 = 21H
Video Reference: 8051 | Simulation Programs
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23
8051 Microcontroller
MCQ 2020-21
Q19) Assume internal RAM location values…
[20] = 10H,
[21] = 20H,
[22] = 30H
[23] = 40H,
[24] = 50H,
[25] = 60H
What will happen after...
MOV R0, 20H
INC R0
MOV 25H, R0
MOV R0, 24H
MOV 23H, 25H
Important Type
(a)
(b)
(c)
(d)
[23] = 60H, [25] = 11H
[23] = 11H, [25] = 20H
[23] = 50H, [25] = 11H
[23] = 11H, [25] = 11H
Answer…
(a)
(b)
(c)
(d)
[23] = 60H, [25] = 11H
[23] = 11H, [25] = 20H
[23] = 50H, [25] = 11H
[23] = 11H, [25] = 11H
Video Reference: 8051 | Simulation Programs
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24
8051 Microcontroller
MCQ 2020-21
Q20) Assume
[20] = 10H,
[21] = 20H,
[23] = 40H,
[24] = 50H,
What will happen after...
MOV 21H, 20H
MOV 20H, 22H
MOV 22H, 21H
(a)
(b)
(c)
(d)
Exchange [20] and [22]
Exchange [20] and [21]
Exchange [21] and [22]
None of the above
[22] = 30H
[25] = 60H
Important Type
Answer…
(a)
(b)
(c)
(d)
Exchange [20] and [22]
Exchange [20] and [21]
Exchange [21] and [22]
None of the above
Video Reference: 8051 | Simulation Programs
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25
8051 Microcontroller
MCQ 2020-21
Q21) Which of the following is incorrect…
(a)
(b)
(c)
(d)
MOV @R0, A
MOVX @R0, A
MOV @DPTR, A
MOVX @DPTR, A
Answer…
(a)
(b)
(c)
(d)
Important Type
MOV @R0, A
MOVX @R0, A
MOV @DPTR, A
MOVX @DPTR, A
Video Reference: 8051 | Addressing Modes
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26
8051 Microcontroller
MCQ 2020-21
Q22) Which of the following is incorrect…
(a)
(b)
(c)
(d)
(e)
ANL 30H, A
ORL 30H, A
XRL 30H, A
ADD 30H, A
All are incorrect
Answer…
(a)
(b)
(c)
(d)
(e)
Important Type
ANL 30H, A
ORL 30H, A
XRL 30H, A
ADD 30H, A
All are incorrect
Video Reference: 8051 | Instructions Part 1 & 2
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27
8051 Microcontroller
MCQ 2020-21
Q23) Which of the following is incorrect…
(a)
(b)
(c)
(d)
(e)
DEC A
DEC R0
DEC 30H
DEC @RO
DEC DPTR
Answer…
(a)
(b)
(c)
(d)
(e)
Important Type
DEC A
DEC R0
DEC 30H
DEC @RO
DEC DPTR
Video Reference: 8051 | Instructions Part 1
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28
8051 Microcontroller
MCQ 2020-21
Q24) Which of the following is correct…
(a)
(b)
(c)
(d)
MOV A, #255H
MOV A, #255
MOV A, 2000H
MOVX A, 2000H
Answer…
(a)
(b)
(c)
(d)
Important Type
MOV A, #255H
MOV A, #255
MOV A, 2000H
MOVX A, 2000H
Video Reference: 8051 | Instructions Part 1
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29
8051 Microcontroller
MCQ 2020-21
Q25) How many iterations will this loop have…
MOV R7, #0FFH
Back: …
DJNZ R7, Back
(a)
(b)
(c)
(d)
255 Iterations
256 Iterations
257 Iterations
1 Iteration
Important Type
of Question
Answer…
(a)
(b)
(c)
(d)
255 Iterations
256 Iterations
257 Iterations
1 Iteration
Video Reference: 8051 | Instruction Set Part 4
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30
8051 Microcontroller
MCQ 2020-21
Q26)
How many iterations will this loop have…
MOV R7, #00H
Back: …
DJNZ R7, Back
(a)
(b)
(c)
(d)
255 Iterations
256 Iterations
0 Iterations
1 Iteration
Important Type
of Question
Answer…
(a)
(b)
(c)
(d)
255 Iterations
256 Iterations
0 Iterations
1 Iteration
Video Reference: 8051 | Simulation Programs
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31
8051 Microcontroller
MCQ 2020-21
Q27) MOV A, #25H
CJNE A, #24H, Down
Show effect on CF and PF…
(a)
(b)
(c)
(d)
CF = 0, PF= 1
CF = 0, PF= 1
CF = 1, PF= 0
No relation with flags
Answer…
(a)
(b)
(c)
(d)
CF = 0, PF= 1
CF = 0, PF= 1
CF = 1, PF= 0
No relation with flags
Important Type
of Question
Video Reference: 8051 | Simulation Programs
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32
8051 Microcontroller
MCQ 2020-21
Q28) MOV A, #24H
CJNE A, #25H, Down
Show effect on CF and PF…
(a)
(b)
(c)
(d)
CF = 0, PF= 1
CF = 0, PF= 1
CF = 1, PF= 0
CF = 1, PF= 1
Answer…
(a)
(b)
(c)
(d)
CF = 0, PF= 1
CF = 0, PF= 1
CF = 1, PF= 0
CF = 1, PF= 1
Important Type
of Question
Video Reference: 8051 | Simulation Programs
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33
8051 Microcontroller
MCQ 2020-21
Q29) MOV A, #7FH
ADD A, #01H
Show effect on CF and Overflow (OV)…
(a)
(b)
(c)
(d)
CF = 0, OV= 0
CF = 0, OV= 1
CF = 1, OV= 0
CF = 1, OV= 1
Answer…
(a)
(b)
(c)
(d)
CF = 0, OV= 0
CF = 0, OV= 1
CF = 1, OV= 0
CF = 1, OV= 1
Important Type
of Question
Video Reference: 8051 | Simulation Programs
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34
8051 Microcontroller
MCQ 2020-21
Q30) MOV A, #0FFH
ADD A, #01H
Show effect on CF and Overflow (OV)…
(a)
(b)
(c)
(d)
CF = 0, OV= 0
CF = 0, OV= 1
CF = 1, OV= 0
CF = 1, OV= 1
Answer…
(a)
(b)
(c)
(d)
CF = 0, OV= 0
CF = 0, OV= 1
CF = 1, OV= 0
CF = 1, OV= 1
Important Type
of Question
Video Reference: 8051 | Simulation Programs
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35
8051 Microcontroller
MCQ 2020-21
Q)
We cheat and learn by piracy because…
(a) We are cheap
(b) We are educated thieves
(c) We were raised with low morals
(d) We love to backstab our teacher!
Answer…
All of the above
Learn the full subject here...
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36
8051 Microcontroller
MCQ 2020-21
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37
8051 Microcontroller
MCQ 2020-21
Section 3
8051 Timer Section
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38
8051 Microcontroller
MCQ 2020-21
Q31)
8051 has …
(a) 2, 16-bit up counters
(b) 3, 16-bit up counters
(c) 2, 16-bit down counters
(d) 3, 16-bit down counters
Answer…
(a) 2, 16-bit up counters
(b) 3, 16-bit up counters
(c) 2, 16-bit down counters
(d) 3, 16-bit down counters
Video Reference: 8051 | Timmer Section
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39
8051 Microcontroller
MCQ 2020-21
Q32) One Machine cycle has ___ T states?
(a) 4
(b) 6
(c) 12
(d) undefined
Answer…
(a) 4
(b) 6
(c) 12
(d) undefined
Video Reference: 8051 | Timer Section
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40
8051 Microcontroller
MCQ 2020-21
Q33)
We use hardware delay because?
(a) It is Cheap
(b) It is faster
(c) Smaller Circuit
(d) Keeps processor free
Important Type
Answer…
of Question
(a) It is Cheap
(b) It is faster
(c) Smaller Circuit
(d) Keeps processor free
Video Reference: 8051 | Timer Section
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41
8051 Microcontroller
MCQ 2020-21
Q34)
TCON is used to decide Modes of Timers
(a) True
(b) False
Answer…
(a) True
(b) False
Video Reference: 8051 | Timer Section
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42
8051 Microcontroller
MCQ 2020-21
Q35)
TF1 and TF0 indicate timer overflow
(a) True
(b) False
Answer…
(a) True
(b) False
Video Reference: 8051 | Timer Section
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43
8051 Microcontroller
MCQ 2020-21
Q36)
To count 5 pulses we load a count of…
(a) 5
(b) Max count – 5
(c) Max count – 5 + 1
(d) Max count – 4 + 1
Answer…
Important Type
(a) 5
of Question
(b) Max count – 5
(c) Max count – 5 + 1
(d) Max count – 4 + 1
Video Reference: 8051 | Timer Section
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44
8051 Microcontroller
MCQ 2020-21
Q37)
Which is a continuous mode of Timer?
(a) Mode 0
(b) Mode 1
(c) Mode 2
(d) Mode 3
Answer…
(a) Mode 0
Important Type
(b) Mode 1
of Question
(c) Mode 2
(d) Mode 3
Video Reference: 8051 | Timer Section
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45
8051 Microcontroller
MCQ 2020-21
Q38)
Which mode produces the biggest delay?
(a) Mode 0
(b) Mode 1
(c) Mode 2
(d) Mode 3
Answer…
(a) Mode 0
(b) Mode 1
Important Type
of Question
(c) Mode 2
(d) Mode 3
Video Reference: 8051 | Timer Section
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46
8051 Microcontroller
MCQ 2020-21
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47
8051 Microcontroller
MCQ 2020-21
Section 4
8051 Serial Port and Interrupts
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48
8051 Microcontroller
MCQ 2020-21
Q39)
8051 has ___ interrupts
(a) 2
(b) 5
(c) 13
(d) 8
Answer…
(a) 2
(b) 5
(c) 13
(d) 8
Video Reference: 8051 | Interrupts
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49
8051 Microcontroller
MCQ 2020-21
Q40)
INT0 and INT1 can be made edge or level
triggered using bits of ____ SFR?
(a) IE
(b) IP
(c) TCON
(d) SCON
Answer…
(a) IE
(b) IP
(c) TCON
(d) SCON
Important Type
Video Reference: 8051 | Interrupts
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50
8051 Microcontroller
MCQ 2020-21
Q41)
Which is a full duplex serial port mode?
(a) Mode 0
(b) All Modes
(c) Mode 1 and Mode 2
(d) All except Mode 0
Answer…
(a) Mode 0
Important Type
(b) All Modes
(c) Mode 1 and Mode 2
(d) All except Mode 0
Video Reference: 8051 | Serial Port
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51
8051 Microcontroller
MCQ 2020-21
Q42)
Which serial port modes have programmable
Baud Rate?
(a) Mode 0
(b) All Modes
(c) Mode 1 and Mode 3
(d) All except Mode 1 and Mode 3
Answer…
(a) Mode 0
Important Type
(b) All Modes
(c) Mode 1 and Mode 3
(d) All except Mode 1 and Mode 3
Video Reference: 8051 | Serial Port
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52
8051 Microcontroller
MCQ 2020-21
Q43)
To produce standard UART Baud Rates of
9600, 4800, etc. we use a crystal of ____?
(a) 11.0592 MHz
(b) 12 MHz
(c) 12.0592 MHz
(d) 11.9592 MHz
Answer…
(a) 11.0592 MHz
(b) 12 MHz
Important Type
(c) 12.0592 MHz
(d) 11.9592 MHz
Video Reference: 8051 | Serial Port
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53
8051 Microcontroller
MCQ 2020-21
Q44)
SMOD is used to _____?
(a) Decide Serial Mode
(b) Decide Error Checking Mode
(c) Decide UART Mode
(d) Double the Baud Rate
Important Type
Answer…
(a) Decide Serial Mode
(b) Decide Error Checking Mode
(c) Decide UART Mode
(d) Double the Baud Rate
Video Reference: 8051 | Serial Port
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54
8051 Microcontroller
MCQ 2020-21
Q45)
Which Serial Modes use Timer 1?
(a) Only Mode 1 and 3 use Timer 1
(b) All use Timer 0
(c) All use Timer 1
(d) Only Mode 0 and 2 use Timer 1
Answer…
(a) Only Mode 1 and 3 use Timer 1
(b) All use Timer 0
(c) All use Timer 1
(d) Only Mode 0 and 2 use Timer 1
Video Reference: 8051 | Serial Port
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55
8051 Microcontroller
MCQ 2020-21
Q46)
MOV IE, #10010101B will _____?
(a) Enable INT0, INT1, Serial Interrupt
(b) Enable INT0, INT1 interrupts
(c) Disable all interrupts
(d) Enable Timer 0, Timer 1 Interrupts
Important Type
Answer…
(a) Enable INT0, INT1, Serial Interrupt
(b) Enable INT0, INT1 interrupts
(c) Disable all interrupts
(d) Enable Timer 0, Timer 1 Interrupts
Video Reference: 8051 | Interrupts
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56
8051 Microcontroller
MCQ 2020-21
Q47)
MOV IE, #00010001B will _____?
(a) Enable all interrupts
(b) Enable INT0, Serial interrupts
(c) Disable all interrupts
(d) Enable Timer 0, Timer 1 Interrupts
Important Type
Answer…
(a) Enable all interrupts
(b) Enable INT0, Serial interrupts
(c) Disable all interrupts
(d) Enable Timer 0, Timer 1 Interrupts
Video Reference: 8051 | Interrupts
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57
8051 Microcontroller
MCQ 2020-21
Q48)
MOV IP, #00010001B will _____?
(a) Enable all interrupts
(b) Enable INT0, Serial interrupts
(c) Make INT0 and Serial int high priority
(d) Invalid Instruction
Important Type
Answer…
(a) Enable all interrupts
(b) Enable INT0, Serial interrupts
(c) Make INT0 and Serial int high priority
(d) Invalid Instruction
Video Reference: 8051 | Interrupts
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58
8051 Microcontroller
MCQ 2020-21
Q49) The Vector address of Serial Interrupt is…
(a)
(b)
(c)
(d)
(e)
0003H
000BH
0013H
001BH
0023H
Answer…
(a)
(b)
(c)
(d)
(e)
0003H
000BH
0013H
001BH
0023H
Important Type
Video Reference: 8051 | Interrupts
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59
8051 Microcontroller
MCQ 2020-21
Q50) CLR IE.7 will …
(a)
(b)
(c)
(d)
Disable all interrupts
Have no effect on interrupts
Invalid Instruction
Disable Serial Port Interrupt
Answer…
(a)
(b)
(c)
(d)
Important Type
Disable all interrupts
Have no effect on interrupts
Invalid Instruction
Disable Serial Port Interrupt
Video Reference: 8051 | Interrupts
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60
8051 Microcontroller
MCQ 2020-21
Q51) On Reset which interrupts are disabled…
(a)
(b)
(c)
(d)
All interrupts except Serial Port
All interrupts except Timers
All interrupts except INTX
All interrupts
Important Type
Answer…
(a)
(b)
(c)
(d)
All interrupts except Serial Port
All interrupts except Timers
All interrupts except INTX
All interrupts
Video Reference: 8051 | Interrupts
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61
8051 Microcontroller
MCQ 2020-21
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62
8051 Microcontroller
MCQ 2020-21
Section 5
Ports and Interfacing
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63
8051 Microcontroller
MCQ 2020-21
Q52) 8051 uses…
(a)
(b)
(c)
(d)
Memory Mapped I/O
I/O Mapped I/O
Both
None
Answer…
(a)
(b)
(c)
(d)
Memory Mapped I/O
I/O Mapped I/O
Both
None
Video Reference: 8051 | Pin Diagram
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64
8051 Microcontroller
MCQ 2020-21
Q53) Look up tables are accessed using ____ ?
(a)
(b)
(c)
(d)
MOV A, @R0
MOVX A, @R0
MOVX A, @DPTR
MOVC A, @A+DPTR
Answer…
(a)
(b)
(c)
(d)
MOV A, @R0
MOVX A, @R0
MOVX A, @DPTR
MOVC A, @A+DPTR
Important Type
Video Reference: 8051 | Any Interfacing Video
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65
8051 Microcontroller
MCQ 2020-21
Q54) Which ports are Quasi-Bidirectional ____?
(a)
(b)
(c)
(d)
All ports
Ports 1,2,3
Ports 0,1,2
Ports 0,2,3
Answer…
(a)
(b)
(c)
(d)
All ports
Ports 1,2,3
Ports 0,1,2
Ports 0,2,3
Important Type
Video Reference: 8051 | I/O Ports
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66
8051 Microcontroller
MCQ 2020-21
Q55) In LCD interfacing the role of RS signal is?
(a)
(b)
(c)
(d)
To Switch on the LCD
To Switch off the LCD
To decide Data or Command
To go to next line
Answer…
(a)
(b)
(c)
(d)
Important Type
To Switch on the LCD
To Switch off the LCD
To decide Data or Command
To go to next line
Video Reference: 8051 | LCD Interfacing
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67
8051 Microcontroller
MCQ 2020-21
Q56) MOV P1, #0FFH
The above line will ____?
(a)
(b)
(c)
(d)
Switch OFF Port 1
Switch ON Port 1
Make Port 1 Output
Make Port 1 Input
Important Type
Answer…
(a)
(b)
(c)
(d)
Switch OFF Port 1
Switch ON Port 1
Make Port 1 Output
Make Port 1 Input
Video Reference: 8051 | I/O Ports
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68
8051 Microcontroller
MCQ 2020-21
Q57) PSEN (bar) is used for _____?
(a)
(b)
(c)
(d)
Read signal for External RAM
Read signal for External ROM
Write signal for External RAM
To Turn on On-Board LEDs
Answer…
(a)
(b)
(c)
(d)
Important Type
Read signal for External RAM
Read signal for External ROM
Write signal for External RAM
To Turn on On-Board LEDs
Video Reference: 8051 | Memory Interfacing
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69
8051 Microcontroller
MCQ 2020-21
Q58) EA (bar) decides if _____ will be used or not?
(a)
(b)
(c)
(d)
Internal RAM
Internal ROM
External ROM
External RAM
Important Type
Answer…
(a)
(b)
(c)
(d)
Internal RAM
Internal ROM
External ROM
External RAM
Video Reference: 8051 | Memory Interfacing
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70
8051 Microcontroller
MCQ 2020-21
Q59) ALE is used to…
(a)
(b)
(c)
(d)
Latch Lower byte of address
Latch Lower byte of data
Latch higher byte of address
Latch higher byte of data
Answer…
(a)
(b)
(c)
(d)
Latch Lower byte of address
Latch Lower byte of data
Latch higher byte of address
Latch higher byte of data
Video Reference: 8051 | Pin Diagram
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71
8051 Microcontroller
MCQ 2020-21
Q60) Chip number 6264 is of size…
(a)
(b)
(c)
(d)
64 bit
64 KB
8 KB
insufficient information
Answer…
(a)
(b)
(c)
(d)
64 bit
64 KB
8 KB
insufficient information
Important Type
Video Reference: 8051 | Memory Designing
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72
8051 Microcontroller
MCQ 2020-21
Q61) Chip number 17128 is of size…
(a)
(b)
(c)
(d)
64 bit
64 KB
8 KB
16 KB
Answer…
(a)
(b)
(c)
(d)
64 bit
64 KB
8 KB
16 KB
Important Type
Video Reference: 8051 | Memory Designing
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73
8051 Microcontroller
MCQ 2020-21
Q62) (4K x 8) means…
(a)
(b)
(c)
(d)
8 chips of 4B
4KB
32KB
Wrong notation
Answer…
(a)
(b)
(c)
(d)
8 chips of 4B
4KB
32KB
Wrong notation
Important Type
Video Reference: 8051 | Memory Designing
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74
8051 Microcontroller
MCQ 2020-21
Q63) 8KB chip needs …
(a)
(b)
(c)
(d)
10 address lines
11 address lines
12 address lines
13 address lines
Answer…
(a)
(b)
(c)
(d)
10 address lines
11 address lines
12 address lines
13 address lines
Important Type
Video Reference: 8051 | Memory Designing
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75
8051 Microcontroller
MCQ 2020-21
Q64) What is mapped at RESET Vector address
0000H?
(a)
(b)
(c)
(d)
RAM
ROM
Doesn’t matter
There is no such address
Important Type
Answer…
(a)
(b)
(c)
(d)
RAM
ROM
Doesn’t matter
There is no such address
Video Reference: 8051 | Designing
www.BharatAcharyaEducation.com
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76
8051 Microcontroller
MCQ 2020-21
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8051 Microcontroller
MCQ 2020-21
Useful Links…
My Recommended
Reference books
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8051 Microcontroller | Bharat Acharya
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COA | William Stallings
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COA | John Hayes
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COA | Tanenbaum
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8051 Microcontroller
MCQ 2020-21
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8051 Microcontroller
MCQ 2020-21
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80
8051 | SQUARE WAVE PROGRAM
Using Timer Interrupt
Q: Write a program to generate a square wave of 1KHz on P0.0 while
simultaneously reading data from P1 and sending it to P2.
org 0
sjmp main
;goto main
org 000bh
sjmp T0ISR
; goto T0 ISR
org 0030h
main:
mov p1, #0ffh
mov ie, #82h
mov tmod, #01h
mov tl0, #0ch
mov th0, #0feh
setb tr0
clr p0.0
again:
mov a, p1
mov p2, a
sjmp again
; P1 input port
; enable T0 int
; T0 - M1
; count LB
; count HB
; start timer
; make P0.0 = 0
; A <-- P1
; P2 <-- A
; loop
T0ISR:
cpl p0.0
clr tr0
mov tl0, #0ch
mov th0, #0feh
setb tr0
reti
; compl. p0.0
; make run bit 0
; load count LB
; load count HB
; start timer 0
; return from isr
end
Delay calculation
Frequency of square wave = 1KHz
Time period = 1 ms
Delay = 0.5 ms
Delay = 500 microsec
Hence we need 500 counts
Count to be loaded = 65535-500+1 = 65036 = FE0CH
Count = FE0CH
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On the Simulator
Load the exact same program…
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8051 | SQUARE WAVE PROGRAM
Using Timer Interrupt
Run it… You will see P0.0 toggling between 0 and 1… that’s the square wave output as desired…
You can also change the switch inputs on P1 and see the changed output on P2
Observe p1.3 (switch 3) is off (default logic 1 )
In that case P2.3 will also be 1
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M: 9820408217
But when we press switch 3 (we have made p1.3 = 0)
As a result P2.3 will also become 0
This shows that we are doing both operations simultaneously. While a square wave is being produced
on p0.0 at the same time we are transmitting value from p1 to p2
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8051 | SQUARE WAVE PROGRAM
Using Timer Interrupt
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8051 | ARM7 | COA
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