IET Circuits, Devices & Systems
Research Article
Symbiotic organisms search algorithm for
optimal design of CMOS two-stage op-amp
with nulling resistor and robust bias circuit
ISSN 1751-858X
Received on 6th June 2018
Revised 4th February 2019
Accepted on 20th February 2019
E-First on 12th July 2019
doi: 10.1049/iet-cds.2018.5259
www.ietdl.org
Sumalya Ghosh1 , Bishnu Prasad De2, Rajib Kar1, Ashis Kumar Mal1
1Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India
2School of Electronics Engineering, Kalinga Institute of Industrial Technology, Bhubaneswar, India
E-mail: sg.12ece1106@phd.nitdgp.ac.in
Abstract: This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal
designs of two different analogue very-large-scale integration circuits. The configurations considered here are nulling resistor
compensation based complementary metal–oxide–semiconductor (CMOS) two-stage op-amp and two-stage CMOS op-amp
with robust bias circuit. The prime goal of this work is the sizing of metal–oxide–semiconductor (MOS) transistors employing the
SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are
authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for
both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the
earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op-amp circuits.
1
Introduction
Design of analogue integrated circuit is a complex procedure that
includes the composite agreements between non-linear objectives.
The objective consists of design parameters, and the set of optimal
design parameters is searched. Due to the increase in circuit
complexity, the search space is expanded, and it becomes
challenging to find the optimal set of design parameters manually.
Therefore, automated circuit sizing based on evolutionary
techniques may be used for the design of analogue circuits.
Some of the recent articles which describe analytical equation
based optimisation approaches to design several analogue verylarge-scale integration (VLSI) circuits are as follows: Articles [1,
2] present an algorithm called particle swarm optimisation (PSO)
[3, 4] to optimise the metal–oxide–semiconductor (MOS) area of a
two-stage op-amp. PSO has also been applied for the maximisation
of unity gain bandwidth (UGB), and gain of an analogue folded
cascode op-amp [5]. A technique called hybrid evolutionary
optimisation is proposed for the design of five different analogue
circuits in [6]. Using the geometric programming, a
complementary metal–oxide–semiconductor (CMOS) op-amp
sizing has been estimated as a convex optimisation problem [7]. A
transconductance amplifier with multiple-inputs is proposed using
neural network in [8]. An efficient approach for the extraction and
optimisation of MOSFET model parameters is developed in [9].
Sizing of analogue circuits using thin-film transistors is suggested
in [10] for the application of flexible electronics. Different
algorithms have been used to design several CMOS analogue
circuits in [11, 12]. CMOS folded-cascode op-amp and comparator
circuits are optimally designed using ALC-PSO in [13]. Design of
CMOS inverter using ALC-PSO is presented in [14] for high-speed
symmetrical switching application.
The literature which include the symbiotic organisms search
(SOS) algorithm in solving the various types of optimisation
problem in different engineering fields recently are as follows.
Article [15] applied the SOS algorithm to design a PID controller.
In [16], the SOS algorithm is applied to solve the transmission
congestion problem in power system. Article [17] suggested the
SOS algorithm for the demand side management modelling in the
power industry. In [18], the SOS algorithm is applied to determine
the coefficients of an optimal fractional order digital integrator. The
SOS algorithm has been adopted to design an optimal active
analogue filter in [19]. To enhance the power supply stability, the
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
SOS algorithm is explored in [20] for the optimum placement of
distributed generators in the distributed network. The model in [21]
presents the optimisation of directional overcurrent relays in the
power system utilising the SOS algorithm.
This paper investigates the optimal design of two different opamp circuits [22–25] using the SOS algorithm. The effective
contribution made in this work is the optimal designs of analogue
circuits with better performance parameters as compared to the
earlier reported literature.
This paper is organised as follows. Section 2 describes the
design steps of two different op-amp circuits and formulates the
cost functions (CFs) for each of the circuit. Section 3 concisely
describes the SOS algorithm. The simulation results are discussed
in Section 4. Lastly, the conclusion has been made in Section 5.
2 Design steps and formulation of objective
function
In CMOS integrated circuit, the circuit sizing technique is a
constructive process where the design specifications like gain,
power dissipation, area and so on are formulated in terms of the
design parameters. Design parameters like the size of the devices
and bias current have to be tuned under different design
constraints. Equations defining each specification are used for the
CF of the SOS-based circuit design. In this paper, two different
CMOS two-stage op-amps have been considered which are shown
in Figs. 1 and 2, respectively. SOS algorithm should minimise the
CF and attain the optimal values of the design parameters within
the given ranges for the individual circuit.
2.1 Design steps for CMOS two-stage op-amp with nulling
resistor compensation
The op-amp is considered as the fundamental building block for
several analogue integrated circuits. CMOS two-stage op-amps
find wide applications for the designs of analogue-to-digital
converters, filters and mixed mode systems.
The following electrical specifications have been considered for
the op-amp circuit presented in Fig. 1: small-signal voltage gain
( Av),UGB, slew rate (SR), maximum and minimum input common
mode voltages (V IC(max), V IC(min)) and power dissipation (Pdiss).
Compensation capacitance (CC) and the dimensions (W and L) of
679
V DS5(sat) = V IC(min) − V SS − V tn −
• Calculate (W 6 /L6) from
ID5L1
K′nW 1
(8)
W6
W 4 gm6
=
L6
L4 gm4
(9)
gm6 ≥ 10gm1
(10)
where
and
Fig. 1 Basic CMOS two-stage op-amp with nulling resistor compensation
gm4 = K′ p
• Compute ID6, needed for Pdiss.
W4
I
L4 D5
gm2 6
2K′ p(W 6 /L6)
• Calculate (W 7 /L7) from the current ratio of ID6 to ID5
(11)
ID6 =
(12)
W7
W 5 ID6
=
L7
L5 ID5
(13)
• Check Av and Pdiss as given in (14) and (15), respectively
Av =
Fig. 2 Basic CMOS two-stage op-amp with robust bias circuit
the MOS transistors are taken as design parameters for the op-amp
circuit.
The design steps of nulling resistor compensation based op-amp
circuit [26] are as follows:
• Select CC at a minimum value and keep the output pole ( p2) at
2.2 times higher than UGB to achieve a 60° phase margin
CC > 0.22CL
gm6
CL
• Compute ID5 to satisfy SR and Pdiss using
p2 = −
(1)
(2)
ID5 = SR × CC
(3)
• Calculate the transconductances of M1 and M2 (refer to Fig. 1)
from CC and UGB using
gm1, 2 = 2π . UGB . CC
• Compute the values of (W 1 /L1) and (W 2 /L2) from
(4)
gm1
W2
W1
=
=
(5)
L1
L2
K′nID5
• Calculate (W 3 /L3) and (W 4 /L4) from the specification of ICMR,
V IC(max) using
ID5
W3 W4
=
=
L3
L4
K′ p(V DD − V IC(max) − Vt p + V tn)2
(6)
• Compute (W 5 /L5) and (W 12 /L12) from the specification of ICMR,
V IC(min) using
2ID5
W 12
W5
=
=
L5
L12
K′n V DS5(sat) 2
where
680
(7)
2gm2 gm6
ID5 ID6(λn + λp)2
Pdiss = (ID5 + ID6)(V DD + V SS )
• To set V A = V B, V SG10 must be equal to V SG6. Therefore
ID11 W 6
W 11
=
L11
ID6 L6
(14)
(15)
(16)
• Choose
I D5
(17)
2
• Set (W 10 /L10) = 1. The ratio (ID10 /ID5) determines the aspect ratio
of M9 and is given as
ID11 = ID10 = ID9 =
ID10 W 5
W9
=
L9
ID5 L5
• The aspect ratio of M8 is given as
CC
W8
(W 10 /L10)(W 6 /L6)
=
I D6
L8
CC + CL
ID10
• V SG8 is equal to V SG10. V SG10 is given by
(18)
(19)
2 ID10
(20)
+ Vt p
K′ p(W 10 /L10)
• Determine the active resistor (Rz), implemented by the transistor
M8, using
V SG10 =
1
K′ p(W 8 /L8)(V SG10 − V t p )
• Zero (z1) can be computed as
Rz =
z1 = −
1
RzCC − (CC /gm6)
(21)
(22)
Here, the zero (z1) is placed in such a way that it will cancel out
the non-dominant output pole ( p2).
The design parameters for this circuit are given below.
V DD and V SS are the supply voltages at the positive and negative
end, respectively. V GS and V DS denote the voltage measured across
the gate-source and drain-source terminals of a MOS device,
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
respectively. Parameters V t, K′ and λ represent the threshold
voltage, transconductance and channel length modulation factor,
respectively. K′ = μCox, where μ denotes the mobility of carrier
and Cox denotes the oxide capacitance. Subscripts ‘n’ and ‘p’ with
each parameter represent the parameter corresponding to NMOS
and PMOS device, respectively. gm represents the input
transconductance. ID is the drain current flowing through MOS
device.
For the SOS algorithm, the eco-size (i.e. population size) is
taken as 40, and the dimension (d = 16) of the optimisation
problem can be defined as
Step 13: RB =
1
2μn Cox(W 8 /L8)CCSR
The population size for the SOS algorithm has been taken as 40
and the dimension (d = 13) of the optimisation problem can be
defined as
Y = [SR, ωu, V IC(min), V out(max), ϕM , CL, L1, L3, L5, L7,
L9, L10, L14] .
The CF is given as
X = [Av, UGB, SR, V IC(min), V IC(max), Pdiss, CC, L1, L3,
14
CFrobust_bias_circuit = ∑ (W i × Li)
L5, L6, L7, L8, L9, L10, L11] .
(25)
i=1
The CF is formulated as the sum of the areas occupied by each
transistor present in the op-amp circuit and is presented as
12
CFnulling_registor_compensation_circuit = ∑ (W i × Li)
(23)
i=1
To construct the nulling resistor compensation based op-amp
circuit, the number of transistors required is 12. The target value of
CFnulling_registor_compensation_circuit is intended to be lesser than
14.87 μm2 which is achieved in [23]. Here, the SOS algorithm has
been applied to optimise the CFnulling_registor_compensation_circuit.
Figure-of-merit (FOM) [27] for the designed circuit is given as
FOMnulling_registor_compensation_circuit =
CL . UGB
I0
(24)
2.2 Design steps for CMOS two-stage op-amp with robust
bias circuit
The electrical specifications like SR, unity gain frequency ( f u),
V IC(min), V out(max), phase margin (ϕM ) and the design parameters, i.e.
load capacitance (CL), structural parameters (W, L) of transistors
involved in the circuit are reserved within certain limits.
The design steps for the robust bias based op-amp circuit [24]
are listed as follows:
16kT
SR
1+
3ωuSn( f )
ωu(V DD − V IC(max) + V tn)
Step 2: ID7 = SR × (CC + CL)
3μp(V DD − V out(max))CC
Step 3: L6 =
2ωu(CC + CL)tan(ϕM )
2SR × (CC + CL)
Step 4: W 6 =
L6
μpCox(V DD − V out(max))2
Step 5: ID5 = SR × CC
ωu2 CC
W
=
Step 6:
L 1, 2 μnCoxSR
Step 7:
Step 1: CC =
2SR CC
W
=
L 5, 8 μnCox(V IC(min) − V SS − V tn − (SR/ωu))2
CC + CL W
W
=
Step 8:
L 7
CC
L 5
(W /L)6 W
W
=
Step 9:
L 3, 4 2(W /L)7 L 5
CC
W
W
Step 10:
=
L 9
CC + CL L 6
W
W
W
W
(W 6 /L6) W 8
Step 11: 10 = 11 = 12 = 13 =
L10
L11
L12
L13
(W 7 /L7) L8
W 14
W
Step 12:
=4 8
L14
L8
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
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The number of transistors required to construct the robust bias
based op-amp circuit is 14. The value of CFrobust_bias_circuit is aimed
to be lesser than 100.5 μm2 [24]. The SOS algorithm is used to
optimise the CFrobust_bias_circuit. FOM [28] for this circuit is
presented as
FOMrobust_bias_circuit =
3
Gain . UGB
IRN
(26)
SOS algorithm
The SOS algorithm operates on symbiotic relations noticed in the
ecosystem between two organisms. Cheng and Prayogo [29] have
proposed the SOS algorithm. The idea of ‘symbiosis’ and a brief
description of the SOS algorithm are given in the subsequent two
subsections, respectively.
3.1 Symbiosis: a concept
In 1879, de Bary, a German mycologist first used the Greek term
‘symbiosis’, that implies ‘living together’, to illustrate the
connection between two non-identical organisms which are
interconnected. Symbiotic interactions are mainly classified into
two categories, obligatory and facultative. Two organisms rely on
each other for their existence in case of obligate interaction,
whereas for the other case, two organisms may rely on each other,
but it is not essential. Three kinds of symbiotic interactions have
been noticed in nature, namely mutualism, commensalism and
parasitism. In mutualism, both the particulars will be benefitted
from the interaction of two different organisms. Commensalism
happens when one gets profit, and the other becomes neutral from
the interaction between two different organisms. In parasitism, one
will be benefitted, and the other will severely suffer from the
interaction of two different species. For their existence in the
ecosystem over a long time, the living organisms will go through
symbiotic interactions to adjust themselves to the environment.
3.2 Features of the SOS algorithm
The SOS algorithm finds the relationship between organisms that
are involved in discovering the better-fitted organism within a
search space. To locate the optimal global solution, the population
of candidate solutions (which is termed as the ecosystem) is
randomly generated at the beginning of the SOS algorithm. Each
organism is taken as a candidate solution to the corresponding
optimisation problem. The SOS algorithm produces a new solution
by mimicking the symbiotic relationship between the two
organisms. In an ecosystem, each organism is connected with three
symbiotic relationships. This connection process will be continued
until the termination criterion is satisfied. The next three
subsections describe the three different phases of symbiotic
relationship in brief.
3.2.1 Mutualism interaction: In mutualism, both the organisms
get benefitted from the mutualistic relationship between the
organisms simulated through the SOS algorithm. An interaction
between oxpecker and zebra is a basic example of mutualism
681
Table 1 Inputs and technology considered
Inputs/technology
Nulling resistor compensation based op-amp [22, 23]
V DD, V
Robust bias based op-amp [24]
1.2
2.5
V SS, V
−1.2
−2.5
V t p, V
−0.379
−0.901
V tn, V
0.305
0.711
Kn′, μA/V2
260
182
2
K ′p, μA/V
82
41.6
technology
0.13 μm standard CMOS
0.5 μm HP's CMOS 14TB [30]
Table 2 Constraints of the design specifications for nulling resistor compensation based CMOS two-stage op-amp
Design constraints
Ranges considered
≥ 40
SR
Av
Unit
V/ μs
dB
>86
CL
0.05
pF
CC
0.011 < CC ≤ 10
pF
UGB
ICMR
Pdiss
≥ 100
−1 ≤ ICMR ≤ 1
≤ 20
MHz
V
μW
L1 − L12
0.13 ≤ L1 − L12 ≤ 1
W 1 − W 12
0.5 ≤ W 1 − W 12 ≤ 10
μm
μm
X j, new = X j + rand(0, 1) × (Xbest − Mutual_Vector × BF2)
(28)
where
Mutual_Vector =
Fig. 3 Plot of convergence profile of the SOS algorithm for nulling resistor
compensation based CMOS two-stage op-amp
Xi + X j
2
(29)
In (27) and (28), rand(0, 1) is a randomly generated data which lies
between 0 and 1, and the values of two benefit factors, denoted by
BF1 and BF2, are either 1 or 2. As the organisms may get benefitted
fully or partially from the relationship, hence these two factors
(BF1 and BF2) express the benefit level of each organism.
Mutual_Vector describes an interaction between the organisms (Xi
and X j) and is defined in (29). In (27) and (28), the remaining parts
indicate the mutualistic effort due to the organisms to improve their
adaptation level into the ecosystem (highest level of adaptation is
implied by Xbest). If they provide better values of CF as compared
to the previous solutions, then only the new solutions are accepted.
3.2.2 Commensalism interaction: A simple example of
commensalism is the interaction between the spider and the trees.
Spiders trap the insects by creating the net on the trees. Thus, the
spider acquires food and trees are not affected. To mimic the
commensalism phase, randomly choose an organism X j to relate to
the organism Xi. Hence, organism Xi achieves profit from the
relationship while X j remains unaffected. The new value of Xi can
be evaluated using the expression given in the following equation
[29]:
Fig. 4 Simulated SR response for nulling resistor compensation based opamp
where oxpeckers eat parasites from zebra's skin. Thus, the zebras
are getting free from parasites and oxpeckers are getting food.
Oxpeckers will fly and shout when feels something wrong that
guides the zebra to be aware of and rescue. In this interaction, the
ith organism in the ecosystem is denoted by Xi, and randomly
picked up another organism X j to relate with Xi. Both the
organisms will take the advantages to survive inside the ecosystem
using the mutualistic interaction. The new values of Xi and X j are
evaluated using (27) and (28), respectively
Xi, new = Xi + rand(0, 1) × (Xbest − Mutual_Vector × BF1)
682
(27)
Xi, new = Xi + rand( − 1, 1) × (Xbest − X j)
(30)
where (Xbest − X j) describes the profit offered by X j to help Xi. As
a result, the organism Xi will survive better within the ecosystem.
3.2.3 Parasitism interaction:
An interaction between
Plasmodium parasites and the human being is a simple example of
the parasitic relationship. These parasites come into the human
body through the mosquitoes, and they propagate through the
human host. Due to this, the human host will be affected by several
diseases which may lead to death. Here, an organism Xi is taken as
the mosquito which generates an artificial parasite called as
Parasite_Vector. This Parasite_Vector is constructed by
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
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Table 3 Design parameters obtained for nulling resistor compensation based CMOS two-stage op-amp
Design variables hierarchy particle swarm ant colony optimisation genetic algorithm
craziness based particle
optimisation (HPSO) [22] (ACO) [23]
(GA) [23]
swarm optimisation
(CRPSO) [25]
SOS
I0, μA
4.5
4.38
4
1.1
1.05
(W /L)1, 2
2.5 /0.75
0.5/0.81
2/0.93
0.96/0.75
0.9/0.75
(W /L)3, 4
1.5/0.5
1.3/0.64
1.7/0.9
0.5/0.5
0.5/0.5
(W /L)5, 12
5.5/0.75
2.8/0.58
6/0.46
0.76/0.58
0.7/0.55
(W /L)6
3.8/0.5
6.8/0.64
5.7/0.9
9.0966/0.5
8/0.5
(W /L)7
7/0.75
4.6/0.58
9.7/0.46
4.95/0.5
5.25/0.5
(W /L)8
1.5/0.25
1.6/0.68
8.8/0.98
1.115/0.25
1.2/0.25
(W /L)9
3/0.75
1.5/0.58
4.2/0.46
0.58/0.58
0.8/0.8
(W /L)10
4/0.75
0.5/0.17
6.5/0.76
0.53/0.53
0.52/0.52
(W /L)11
4/0.75
0.5/0.17
5.1/0.76
0.57/0.57
0.55/0.55
CL, pF
0.05
0.05
0.05
0.05
0.05
CC, pF
0.09
0.11
0.1
0.0275
0.027
(W /L) measured in (μm/ μm).
Fig. 5 Simulated result of Pdiss for nulling resistor compensation based
op-amp
Fig. 7 Simulated ICMR response of nulling resistor compensation based
op-amp
Fig. 8 Simulated CMRR response of nulling resistor compensation based
op-amp
Fig. 6 UGB, gain and phase plots for nulling resistor compensation based
op-amp
reproducing Xi with a randomly selected dimension, changed
through a random number. Then, randomly choose another
organism X j (host to the parasites) from the ecosystem. The
generated parasite (Parasite_Vector) will ruin out X j and takes
place the present location of X j in the ecosystem if the CF value of
Parasite_Vector is comparable to that of X j. Otherwise, it will
immune against the Parasite_Vector, and hence the parasites will
leave the ecosystem.
3.3 Computing steps of SOS algorithm for the analogue
circuit design
The algorithmic steps are given below.
Step 1 – Initialisation: Initially create an ecosystem utilising the
design constraints.
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
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Step 2 – Evaluation of CF: Evaluate the CF for each organism to
find out the best organism.
Step 3 – Mutualism phase: With the mutualistic interaction
between each other, the organisms are updated, and the weaker
organism is replaced by the fitter organism.
Step 4 – Commensalism phase: The organisms are updated by
performing the commensal interaction, and the updated organisms
with better CF values are considered.
Step 5 – Parasitism phase: Generate a Parasite_Vector, and if the
CF value produced by the Parasite_Vector is comparable to the
random organism then it replaces the random organism.
Step 6 – Termination criterion: The programme is terminated when
it is reached to the maximum number of iteration; otherwise, it
goes to step 2.
3.4 Advantages of SOS algorithm
The paramount feature of the SOS algorithm is that it is
independent of specific algorithm parameters. The SOS uses two
683
Table 4 Comparison of design specifications of nulling resistor compensation based CMOS two-stage op-amp
Design criteria
Unit
Specifications
HPSO [22]
ACO [23]
GA [23]
CRPSO [25]
SR
≥ 40
Pdiss
V/ μs
μW
ϕM
(°)
SOS
<20
50.33
21
38.49
19.75
39.44
20.20
90.53
19.61
40.58
18.65
>65
61.79
56.26
55.85
68.56
67.9
fu
MHz
≥100
101
0.1
0.1037
111.2
111.9
Av
dB
>86
86.16
77.21
80.55
88.61
90.29
V IC(min)
V
≥ −1
NR
NR
NR
−0.7507
−0.998
V IC(max)
V
≤1
NR
NR
NR
0.9372
0.6372
CMRR
dB
dB
>60
>70
NR
NR
NR
NR
NR
NR
87.91
83.22
93.23
82.98
dB
>70
NR
NR
NR
97.06
105.9
2
<250
29.275
14.87
41.264
11.065
10.7579
—
1.12a
0.00114a
0.00129a
5.05
5.32
PSRR+
PSRR−
total area
FOM
μm
pFMHz
μA
NR: not reported.
aCalculated using the reported value.
Fig. 9 Simulated PSRR+ response of nulling resistor compensation based
op-amp
Fig. 11 Layout view of nulling resistor compensation based CMOS twostage op-amp
Fig. 10 Simulated result of PSRR– for nulling resistor compensation based
op-amp
parameters: (i) maximum iteration cycle and (ii) no. of population.
So, it has a lesser chance to get entrapped by local optima due to
improper parameter tuning. To obtain better candidate solutions,
SOS applies three interaction strategies, mutualism, commensalism
and parasitism. Mutual_Vector helps in exploring new regions in
solution space when the two organisms are situated far away from
each other. Commensalism alters a solution by computing the
deviation between the best solution and other solution.
Commensalism helps to find optimistic regions nearby the best
solution, and as a result, the convergence speed will increase.
Parasitism helps to preserve diversity and avoids premature
convergence.
4
Simulation results and discussions
SOS algorithm is implemented in MATLAB R2013a version on
CPU Intel core i5-2430M @ 3.00 GHz processor with 4 GB RAM.
Cadence (IC 5.1.41) software is used for the validation purpose.
The supply voltages and technology parameters considered for
684
Fig. 12 Plot of convergence profile of the SOS algorithm for two-stage
CMOS op-amp with robust bias circuit
both the designs are presented in Table 1. The task of the SOS
algorithm
is
to
minimise
the
value
of
CFnulling_registor_compensation_circuit and CFrobust_bias_circuit, individually.
For the design of nulling resistor compensation based op-amp, the
SOS algorithm has been utilised to achieve the optimal design
parameters I0, CC, W 1 − W 12 and L1 − L12. SOS is also employed to
achieve the optimal design parameters CL, RB, W 1 − W 14 and
L1 − L14 for the robust bias based op-amp. The SOS algorithm has
been executed for 50 times for each op-amp circuit to evaluate the
best set of optimised design parameters. In this section, SOS
algorithm based design results for both the circuits are compared
with the results reported in earlier research [22–25].
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
Table 5 Constraints of the design specifications for twostage CMOS op-amp with robust bias circuit
Parameters
Ranges considered
Units
≥ 5
≥ 5
SR
fu
V/ μs
MHz
≥ − 2.25
V
V out(max)
≤ 2.2
V
ΦM
>60
°
CL
≤ 10
pF
V IC(min)
CC
0.5
pF
L1 − L14
0.5 ≤ L1 − L14 ≤ 5
μm
W 1 − W 14
0.75 ≤ W 1 − W 14 ≤ 100
μm
Fig. 14 Simulated result of Pdiss for robust bias based op-amp
Table 6 Design parameters obtained for two-stage CMOS
op-amp with robust bias circuit
Design variables
[24]
SOS
(W /L)1, 2
1/1
1/1
(W /L)3, 4
1/1
1/4
(W /L)5, 8
1/3
1/2
(W /L)6
31/2.5
9.9/2.5
(W /L)7
3/1
5.4/1
(W /L)9
1/1
1.1/2
(W /L)10 − 13
1/1
1.1/2
(W /L)14
2.5/2
1.28/1
CL, pF
0.5
0.5
CC, pF
5
4.5
RB, kΩ
NR
39.9
Fig. 15 UGB, gain and phase plot for robust bias based op-amp
NR: not reported; (W /L) measured in (μm/ μm).
Fig. 16 Simulated result of ICMR for robust bias based op-amp
Fig. 13 Simulated result of SR for robust bias based op-amp
4.1 Simulation results for nulling resistor compensation
based op-amp circuit
For the nulling resistor compensation based CMOS two-stage opamp circuit, the design constraints are taken as Av > 86 dB,
UGB ≥ 100 MHz,
SR ≥ 40 V/ μs,
−1 V ≤ ICMR ≤ 1 V,
Pdiss ≤ 20 μW. Constraints of the design parameters are as follows:
CL = 0.05 pF, 0.011 pF < CC ≤ 10 pF, 0.13 μm ≤ L1 − L12 ≤ 1 μm,
0.5 μm ≤ W 1 − W 12 ≤ 10 μm. Standard 0.13 μm CMOS technology
is used to implement the circuit. The design constraints are given in
Table 2. SOS-based design results in a total transistor area of
10.7579 μm2 with the optimal design parameters (W 1 − W 12,
L1 − L12, I0, CC) in 8.323 s. Fig. 3 demonstrates the plot of
convergence profile for the SOS algorithm. The optimal design
parameters are given in Table 3.
SPICE simulation has been done by utilising the SOS-based
optimal design parameters to validate the performance
specifications. SPICE results are presented in Figs. 4–11. The
SPICE simulation attains SR of 40.58 V/ μs, power dissipation of
18.65 μW, gain of 90.29 dB, phase margin of 67.9°, UGB of 111.9
MHz, V IC(min) of −0.998 V, V IC(max) of 0.6372 V, CMRR of 93.23
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
dB, PSRR+ of 82.98 dB, PSRR− of 105.9 dB, and the layout area
of 10.7579 μm2. SOS-based performance parameters for the circuit
are compared with other existing techniques [22, 23, 25] in
Table 4. The gain ( Av), UGB, Pdiss and the total MOS area obtained
from the HPSO [22] technique are 86.16 dB, 101 MHz, 21 μW and
29.275 μm2, respectively. The results obtained using ACO, GA
[23] and CRPSO [25] are given in Table 4. SOS-based optimal
design of nulling resistor compensation based CMOS two-stage
op-amp yields remarkably better results as compared to the
previous literature [22, 23, 25] regarding Av, UGB, Pdiss, total MOS
area and FOM, as presented in Table 4.
4.2 Simulation results for robust bias based CMOS two-stage
op-amp circuit
For the op-amp with robust bias circuit, the design constraints are
considered as SR ≥ 5 V/ μs, f u ≥ 5 MHz, V IC(min) ≥ − 2.25 V,
V out(max) ≤ 2.2 V, ϕM > 60°. Constraints of the design parameters
are as follows: CL ≤ 10 pF, CC = 0.5 pF, 0.5 μm ≤ L1 − L14 ≤ 5 μm,
0.75 μm ≤ W 1 − W 14 ≤ 100 μm. To design the robust bias based opamp, 0.5 μm HP'S CMOS 14TB [30] process parameters are used.
Table 5 presents the ranges of the design constraints. SOS-based
design of the op-amp results in a total MOS area of 56.43 μm2 with
the optimal design parameters (W 1 − W 14, L1 − L14, RB and CL) in
7.524 s. The convergence profile plot of the SOS algorithm is
given in Fig. 12. The optimal design parameters are given in
Table 6.
685
Fig. 17 Output voltage swing for robust bias based op-amp
Fig. 21 Delay plot for robust bias based op-amp
Fig. 18 Simulated result of CMRR for robust bias based op-amp
Fig. 22 Simulated noise for robust bias based op-amp
Fig. 19 Simulated result of PSRR+ for robust bias based op-amp
Fig. 23 Layout view of the op-amp with the robust bias circuit
Fig. 20 Simulated result of PSRR– for robust bias based op-amp
SOS algorithm based SPICE simulation results are presented in
Figs. 13–23. In this paper, SOS-based designed results in a gain,
phase margin, unity gain frequency, SR and the total MOS area of
81.61 dB, 65.56°, 12.2 MHz, 11.85 V/ μs and 56.43 μm2,
respectively. The simulation results stated in [24] are the gain of
85 dB, phase margin of 65°, unity gain frequency of 6.15 MHz, SR
of 6.21 V/ μs and the total area of 100.5 μm2. The performance
parameters are given in Table 7. From Table 7, it is clear that the
SOS-based design satisfies all the design specification with the
lesser area for two-stage CMOS op-amp with robust bias circuit.
686
Fig. 24 Box and whisker plots for SOS algorithm based design of nulling
resistor compensation based CMOS two-stage op-amp over 50 runs
4.3 Statistical results for SOS algorithm
Statistical performances of the SOS algorithm are measured over
50 runs for each analogue circuit. The CF values achieved in each
run are considered to implement Box and Whisker plots for the
individual circuit to demonstrate the median performance. The Box
and Whisker plots for nulling resistor compensation based CMOS
two-stage op-amp and two-stage CMOS op-amp with robust bias
circuit are given in Figs. 24 and 25, respectively. For nulling
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
Fig. 25 Box and whisker plots for SOS algorithm based design of two-stage CMOS op-amp with robust bias circuit over 50 runs
Table 7 Comparison of design specifications for two-stage CMOS op-amp with robust bias circuit
Design criteria
Unit
Specifications
[24]
SOS
CL
pF
≤ 10
5
4.5
SR
Pdiss
V/ μs
μW
≥ 5
<350
6.21
NR
11.85
351.2
ΦM
deg
>60
65
65.56
fu
MHz
>60
6.15
12.2
Av
dB
>80
85
81.61
V IC(min)
V
≥ − 2.25
−2.2
−1.693
V IC(max)
V
≤ 2.25
2
1.374
V out(min)
V
≥ − 2.2
−2.15
−2
V out(max)
V
≤ 2.2
2.15
2.2
CMRR
dB
dB
>70
>70
NR
NR
87.91
83.22
dB
>70
NR
106.9
μs
nv/ Hz
<1
<45
NR
44
0.183
43.85
μm2
<101
100.2
56.43
1015 × Hz3/2
V
—
2485.55a
3348.81
PSRR+
PSRR−
propagation delay
input referred noise (IRN) at 1 MHz
total area
FOM
NR: not reported.
aCalculated using the reported value.
Table 8
Circuit
Statistical results of SOS algorithm for both the circuits over 50 runs
Best value, Worst value, Mean, μm2 Median, μm2
Lower
Upper
Standard
μm2
μm2
quartile, μm2 quartile, μm2 deviation, μm2
nulling resistor compensation based
CMOS two-stage op-amp circuit
robust bias based CMOS two-stage
op-amp circuit
10.7579
11.0974
10.92
10.90
10.82
11.01
0.0201
56.43
56.7441
56.5681
56.567
56.4961
56.626
0.0961
resistor compensation based op-amp circuit, the median value is
10.9 × 10−12, and the range of variation of CF is 10.7579 × 10−12 to
11.0974 × 10−12. For the op-amp with the robust bias circuit, the
median value is 56.567 × 10−12, and the range of variation of CF is
56.43 × 10−12 to 56.7441 × 10−12. As the CF values vary within a
small range for both the op-amp circuits, SOS algorithm gives the
stable performance. Statistical results of the SOS algorithm are
given in Table 8 for both the circuits. The standard deviation values
for each op-amp circuit are small as shown in Table 8. So, it is
proved that the SOS algorithm is highly consistent in producing the
output for each circuit.
simulation results confirm that the SOS algorithm is better than the
other algorithms in terms of MOS area, gain, power dissipation and
so on for the abovementioned op-amp circuits. The simulation
results achieved for the op-amp circuits demonstrate the efficiency
of the SOS algorithm over HPSO, GA, ACO and CRPSO
regarding consistency, convergence speed and design
specifications.
6
[1]
[2]
5
Conclusions
The contribution of this study is the ‘application’ of the new stateof-the-art algorithm for the design of the analogue VLSI circuit,
obtaining much better results for analogue circuit design, which is
validated well by SPICE simulation. In this study, the authors
applied SOS algorithm in VLSI domain for the optimal designs of
nulling resistor compensation based CMOS two-stage op-amp and
two-stage CMOS op-amp with robust bias circuit. The SPICE
IET Circuits Devices Syst., 2019, Vol. 13 Iss. 5, pp. 679-688
© The Institution of Engineering and Technology 2019
[3]
[4]
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