On the Greater Acceptance of Functional Test
of PCB Assemblies.
Billy Fenton & Chris Hammond
EBTW 2005, Tallinn, Estonia
Slide 1
Is there a problem?
“Functional test is set to re-emerge as the primary test method
for assembled printed circuit boards.”
Bernard Sutton, GenRad Europe -Test & Measurement World,
10/1/1999
“…board access for electrical test will continue to be at a
premium and imaging inspection will help fill the gap. But,
ultimately, functional testing and/or BIST will have to provide
electrical verification.”
NEMI Roadmap, 2002 Edition.
EBTW 2005, Tallinn, Estonia
Slide 2
Why?
Disappearing Test Access
Area-Array Packaging (e.g. BGA)
Increasing Board Operating Speeds
Board Strain? Lead-free solder?
Hidden Vias
Other Issues, now above the horizon
Complexity
Cost
The BIG Paradox - Boards becoming more complex, with
limited test access, and test cost must be lowered with less
available test tools!
EBTW 2005, Tallinn, Estonia
Slide 3
Electrical Test Methods
ICT
MDA
Functional Test
•Rack/Stack, PXI, VXI
•BIT
•CPU Emulation
Boundary Scan
EBTW 2005, Tallinn, Estonia
Slide 4
The Rise & Fall(?) of ICT/MDA
The Rise
A component test, not a system test.
Test Programming using the netlist and ATPG.
Diagnostics to component or node level.
Automatic Coverage Report(?)
The Decline?
Test Access
IC Test
EBTW 2005, Tallinn, Estonia
Slide 5
The Rise of BST
The Rise
Test programming from netlist and BSDL.
Diagnostics to pin level.
Automatic coverage report.
The Limitations
Digital Only – limits coverage.
DFT required – can limit coverage.
Will security prevent it being a panacea?
EBTW 2005, Tallinn, Estonia
Slide 6
The Reluctant Rise of FT
The Reluctant Rise
Test Programming is slow and difficult. Extensive UUT knowledge needed.
This is exacerbated by increasing complexity.
Diagnostics are poor.
No coverage report.
So Why Now?
Test access is not an issue.
Test coverage is high.
DFT is low.
EBTW 2005, Tallinn, Estonia
Slide 7
FT for Electrical Test??
ICT/MDA/BST advantages are FT disadvantages – ATPG, Diagnostics, Coverage
report.
But, on newer boards, FT can go where ICT/MDA/BST cannot go, but it lacks the
advantages that made these methods attractive.
So, what we need is a FT, that provides ATPG, diagnostics, and coverage
reports. Otherwise the acceptance of FT will be slow.
FT as a supplement or replacement to traditional electrical type tests???
Functional Test
Electrical Test
ICT/MDA/BST
EBTW 2005, Tallinn, Estonia
FT
Slide 8
Summary of our Approach
Initial Architecture
Uses CPU Emulation.
Standard Architecture Boards.
3 Steps
ATPG using a known-good board.
Using the BOM to:
• Create diagnostics.
• Generate a coverage report.
EBTW 2005, Tallinn, Estonia
Slide 9
1. ATPG for FT?
1. Boot good UUT
2. Run ATPG
Chipset Library
ATPG has a library of
chipset drivers.
It searches the UUT
for known devices.
It then extracts the
correct chipsets drivers
or generic tests, and
assembles a test
program.
Undetected chips can
be manually added.
User can maintain their
own libraries also.
EBTW 2005, Tallinn, Estonia
Slide 10
Chipset Test Driver (FTDL??)
1. Header Information
Description
Revision
Relevance
ID Sequence
2. Learn Sequence
Information to extract from known good board. This is stored in some
variables.
3. Generation Sequence
Chipset test sequence. Information extracted under 2 is inserted as required.
EBTW 2005, Tallinn, Estonia
Slide 11
ATPG Example
1.
2.
3.
4.
5.
6.
7.
8.
Audio Codec
PXA 255 ASP
SDRAM
EBTW 2005, Tallinn, Estonia
Flash
USB Controller
CPU Test.
ASP Initialise.
Memory Controller Initialise.
Bus Test.
SDRAM Test.
Flash Test.
USB Access Test.
USB connection and/or
transfer test.
9. Audio Codec Access Test.
10. Audio generation &
measurement test.
Slide 12
2. Diagnostics for FT?
Boards are becoming more complex, but skill level of
technicians is often reducing.
Approaches:
Don’t!!
Technician Skill
• Low skilled labour
• Low cost products
‘Shotgun’
• Quality
• Cost
Historical Information
• If available, and if recorded
Guided Fault Isolation
Probabalistic Methods
EBTW 2005, Tallinn, Estonia
Slide 13
Guided Fault Isolation (GFI)
Traditional GFI used probing,
but this is often not possible on
modern boards.
During development, test
execution is related to a block
diagram, and suggested fixes
and help can be associated
with specific test failures.
Additonally, a PCB layout can
be loaded to locate suggested
fixes.
EBTW 2005, Tallinn, Estonia
Slide 14
Probabalistic Methods
During the test development stage:
Use netlist to extract BOM.
Associate components with tests, and
include failure probability, and identify
which tests are the primary test(s) for each
component.
Primary Test?
During diagnosis:
If a test fails each associated component is
scored appropriately.
After overall test completion each
component is given a final score. Method
TBD.
A list of components is presented, the one
with the highest score is the most likely
defect.
Real-time data could be used to adjust
probabilities.
EBTW 2005, Tallinn, Estonia
Probability
BOM Filter
Slide 15
Diagnostic Example
Component
Score
Description
U5
80%
Intel PXA255
U6
15%
17C51 Audio Codec
U20
5%
74ACT04
EBTW 2005, Tallinn, Estonia
Slide 16
3. Test Coverage Report for FT?
What is test coverage?
Fault universe represents all possible faults.
Coverage is the % of coverable faults.
How does this relate to different test methods.
For FT how do you define the fault universe??? How do you know what faults
are covered by a particular functional test? Must tests be weighted? Etc. It’s
all largely subjective.
FT coverage report
Is a % style report meaningless? But, it can be what the customer wants?
Is a yes/no report more meaningful, possibly with a high/medium/low
coverage metric?
Can this be extracted from the BOM/Test Matrix?
EBTW 2005, Tallinn, Estonia
Slide 17
Coverage Report Example
EBTW 2005, Tallinn, Estonia
Slide 18
Suitable Boards?
PC Style – Notebook, Server, Embedded.
PowerPC
Intel PXA Series (for PDA & Display Centric Apps)
Intel IXP (for networking apps)
TI OMAP (PDA/Smartphone)
Etc., Etc.
EBTW 2005, Tallinn, Estonia
Slide 19
Deficiencies
Discretes.
ATPG for non-library components.
Diagnostic are probabilistic.
Report is not the familiar %.
EBTW 2005, Tallinn, Estonia
Slide 20
Further Work
Adding custom components. Clearer definition of FTDL?
Netlist Analysis
Automatic block diagram generation
Determining component complexity automatically
Can it be extended to other FT approaches?
EBTW 2005, Tallinn, Estonia
Slide 21
Conclusions
As test access becomes more difficult, inspection, BIST, and
FT will become more important.
FT need to incorporate some of the advantages of ICT/MDA
and BST.
ATPG.
Diagnostics to component level.
Automatic generation of a test coverage report.
Is this a real problem? Can it be solved?
Is greater effort needed to define the approach, and/or to
consolidate the various test approaches?
EBTW 2005, Tallinn, Estonia
Slide 22