A Micro Project Report on
VHDL Code for 8-bit Comparator
Submitted in partial fulfillment for
Diploma in Electronics and Telecommunication Engineering
Department of Electronics and Telecommunication Engineering
Government Polytechnic, Yavatmal.
Submitted by1.
2.
3.
4.
Ritesh S. Chavhan
Tejas S. Khobragade
Rohit R. Gole
Sahil R. Rathod
(2101350377)
(2101350335)
(2101350325)
(2101350351)
Project Guide
Mr. S. S. Tiwari
Course: VLSI (22062)
Academic year: 2023-24
CERTIFICATE
This is to certify that a micro project titled “VHDL Code for 8-bit Comparator” has been duly
completed by the following students in satisfactory manner as part of the course VLSI (22062) in
Electronics and Telecommunication Engineering department, Government Polytechnic, Yavatmal.
Submitted by1.
2.
3.
4.
Project Guide
Mr. S. S. Tiwari
Ritesh S. Chavhan
Tejas S. Khobragade
Rohit R. Gole
Sahil R. Rathod
HOD
Mr. P. P. Pawar
(2101350377)
(2101350335)
(2101350325)
(2101350351)
Principal
Dr. R. P. Mogre
ACKNOWLEGEMENT
It is an incident of pleasure for submitting this Micro-Project we take this opportunity to express
our deep sense of gratitude and great thanks to guide us Mr. S. S. Tiwari who has been a constant
source of guidance and inspiration through the micro-project work. We shall ever be grateful to
him for the encouragement and suggestion given by time to time. It is grateful to thanks all teaching
members of Electronics and Telecommunication Department and sincere thanks to our HOD Mr.
P. P. Pawar who always inspire us. We also thank our friends and library staff members whose
encouragement and suggestion helped us to complete our micro-project. Last but not least we are
thankful to our parents whose best wishes are with us.
Branch: Electronics and Telecommunication Engineering
Annexure - I
Micro-Project Proposal
Title of Micro-Project: VHDL Code for 8-bit Comparator
1.0 Aim/Benefits of the Micro-Project:
The development of an 8-bit comparator using VHDL aims to leverage the language's rigorous
specification capabilities for creating accurate and reliable digital comparison circuits. By
employing VHDL, designers are equipped to meticulously model the comparator's behaviour,
ensuring that it precisely meets the required operational specifications. This process inherently
supports the goals of achieving high simulation fidelity, facilitating exhaustive preimplementation testing, and ensuring the design is synthesis-ready for various hardware
platforms like FPGAs and Asics. Secondly, VHDL's simulation capabilities allow for the early
detection of errors and behavioural verification under diverse conditions, significantly
reducing the time and cost associated with physical prototyping and debugging.
2.0 Course Outcomes Addressed:
a) Develop design flow for the given application using VLSI tools.
b) Debug VHDL program for the given application.
3.0 Proposed Methodology:
To create a project on “VHDL Code for 8-bit Comparator” firstly, we collected the
information via standard books and internet. After collecting required material and
information, we started our project. Then we wrote a report and showed it to our course faculty
and asked for the necessary correction if required. Then we finalized the project report and
submitted to the course faculty.
4.0 Action Plan:
Sr. No.
Details of Activity
Planned
Start date
Planned
Finish date
Week 1
Topic Selection
24/07/23
30/07/23
All Members
Week 2
Literature Review
31/07/23
06/08/23
All Members
Week 3
Confirmation of topic
07/08/23
13/08/23
All Members
Week 4
Make the list of required
components
14/08/23
20/08/23
All Members
Week 5
Purchase the
components
Understood the working
of topic
21/08/23
27/08/23
All Members
28/09/22
03/09/23
All Members
Analyse all the
components required for
the circuit
implementation
Implementation on
breadboard
04/09/23
10/09/23
All Members
11/09/23
17/09/23
All Members
Week 9
Report writing
18/09/23
24/09/23
All Members
Week 10
Made final report
25/09/23
01/10/23
All Members
Week 11
Made final presentation
09/10/23
15/10/23
All Members
Week 12
Confirmation of Report
and Presentation
16/10/23
22/10/23
All Members
Week 13
Viva
30/10/23
05/11/23
All Members
Week 14
Final submission
06/11/23
10/11/23
All Members
Week 6
Week 7
Week 8
Name of
Responsible
Team
Members
5.0 Resource Required:
Sr.
No.
1.
2.
Name of
Resources/Material
Computer
Website Links
Specification
Qty
I5/ MS-Office/ w-10
https://www.fpga4student.com/2016/11/verilog-code-for8-bit-74f521-identity.html
1
❖ Name of Team Members with Roll No.
1.Ritesh S. Chavhan
(18)
2.Tejas S. Khobragade
(07)
3. Rohit R. Gole
(06)
4.Sahil R. Rathod
(11)
Annexure - II
Micro-Project Report
Title of Micro-Project: VHDL Code for 8-bit Comparator
1.0 Rationale:
In the present scenario of electronic technology, CMOS is a vital important and basic needs
in the design/development of almost all project in the range from consumer to the individual
and telecommunication engineer area. Functional capabilities of this technology lead to
advanced Very Large-Scale Integration, large density of component, high speed of operation,
less area with less power dissipation. Therefore, impacting knowledge of VLSI and its tools
is need of today. After completion of this course, student will be able to develop application
in the area of digital electronic using VLSI design tools.
2.0 Aims/Benefits of the Micro-Project:
The development of an 8-bit comparator using VHDL aims to leverage the language's rigorous
specification capabilities for creating accurate and reliable digital comparison circuits. By
employing VHDL, designers are equipped to meticulously model the comparator's behaviour,
ensuring that it precisely meets the required operational specifications. This process inherently
supports the goals of achieving high simulation fidelity, facilitating exhaustive preimplementation testing, and ensuring the design is synthesis-ready for various hardware
platforms like FPGAs and Asics. Secondly, VHDL's simulation capabilities allow for the early
detection of errors and behavioural verification under diverse conditions, significantly
reducing the time and cost associated with physical prototyping and debugging.
3.0 Course Outcomes Achieved:
a) Develop design flow for the given application using VLSI tools.
b) Debug VHDL program for the given application.
4.0 Literature Review:
His Micro Project we have gathered all the information by using different types of educational
resources like reference book, internet.
Professional Website
Book: Very Large Scale Integration
5.0 Actual Methodology Followed:
Firstly, we collected all the information via standard books and internet. After collecting
required material and information, we started our chart. Then we wrote a report and showed
it to our course faculty and asked for the necessary correction if required. Then we finalized
the chart report and submitted to the course faculty.
6.0 Actual Resources Used:
Sr.
No.
1.
2.
Name of
Resources/Material
Computer
Website Links
Specification
Qty
I5/ MS-Office/ w-10
https://www.fpga4student.com/2016/11/verilog-code-for8-bit-74f521-identity.html
1
7.0 Outputs of the Micro-Project:
• Introduction
In the field of digital electronics, comparators play a critical role by enabling the
comparison of binary values, thus facilitating decision-making processes within digital
systems. An 8-bit comparator, specifically, compares two 8-bit values, providing outputs
that indicate the relationship between these two values—whether one is greater than, less
than, or equal to the other. The design and implementation of such a comparator using
VHDL (VHSIC Hardware Description Language) represent a foundational exercise in
understanding digital logic and circuit design. VHDL, a powerful hardware description
language, offers a formal way to describe the behaviour and structure of electronic systems,
allowing for the precise modelling, simulation, and synthesis of digital circuits.
1. Truth Table:
2. Logic Symbol for the comparator:
3. Logic diagram for comparator:
4. VHDL code for comparator:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- VHDL project: VHDL code for comparator
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
entity comparator is
port (
clock: in std_logic;
-- clock for synchronization
A,B: in std_logic_vector(7 downto 0);
-- Two inputs
IAB: in std_logic; -- Expansion input ( Active low)
Output: out std_logic -- Output = 0 when A = B
);
end comparator;
architecture Behavioral of comparator is
signal AB: std_logic_vector(7 downto 0); -- temporary variables
signal Result: std_logic;
begin
AB(0) <= (not A(0)) xnor (not B(0));
-- combinational circuit
AB(1) <= (not A(1)) xnor (not B(1));
AB(2) <= (not A(2)) xnor (not B(2));
AB(3) <= (not A(3)) xnor (not B(3));
AB(4) <= (not A(4)) xnor (not B(4));
AB(5) <= (not A(5)) xnor (not B(5));
AB(6) <= (not A(6)) xnor (not B(6));
AB(7) <= (not A(7)) xnor (not B(7));
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
process(clock)
begin
if(rising_edge(clock))then
if(AB = x"FF" and IAB = '0') then
-- check whether A = B and IAB =0 or not
Result <= '0';
else
Result <= '1';
end if;
end if;
end process;
Output <= Result;
end Behavioral;
5. Testbench VHDL code for the comparator:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for comparator
ENTITY tb_comparator IS
END tb_comparator;
ARCHITECTURE behavior OF tb_comparator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comparator
PORT(
clock : IN std_logic;
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
IAB : IN std_logic;
Output : OUT std_logic
);
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal IAB : std_logic := '0';
--Outputs
signal Output : std_logic;
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comparator PORT MAP (
clock => clock,
A => A,
B => B,
IAB => IAB,
Output => Output
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
A <= x"AA";
B <= x"BB";
wait for clock_period*10;
B <= x"AA";
-- insert stimulus here
wait;
end process;
-- fpga4student.com FPGA projects, Verilog projects, VHDL projects
END;
6. Simulation waveform for the comparator:
7. Conclusion:
•
•
•
•
The utilization of VHDL for the design and implementation of an 8-bit comparator
underscores the significant advantages this hardware description language offers in the
realm of digital electronics.
Through a detailed examination of its aims and benefits, it's clear that VHDL not only
facilitates a more precise and efficient design process but also enhances the overall
reliability and functionality of digital circuits.
The ability to accurately model, simulate, and test comparators before physical
implementation reduces development time and costs, while ensuring that the final
product meets the required specifications.
As technology continues to advance, the role of VHDL in fostering innovation and
efficiency in digital design becomes increasingly important, highlighting its
indispensable contribution to the development of complex electronic systems.
8.0 Skill Developed/Learning outcome of this Micro-Project:
1. Communication skill and planning skill and planning for micro project with group
members skill developed.
2. Presentation skill developed how to present our topic and perform the action of micro
project.
3. Learned to work in group.
4. Learned to explain things.
.