CS256 Digital Design and Computer Architecture
3 Sequential Circuits Recap
Suhaib Fahmy
suhaib.fahmy@kaust.edu.sa
From combinational to sequential
▶︎
The output of a combinational circuit is defined purely as a function of its
current inputs
▶︎
Sequential circuits produce outputs that also depend on previous inputs
▶︎
They manifest a form of “memory”
▶︎
The state of a sequential circuit encodes sufficient information about the
past to determine its future behaviour in response to inputs
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The need for memory
▶︎
▶︎
When you worked with algorithms you saw that they consisted of more
than just computation functions:
▶︎
Keeping intermediate values between steps
▶︎
Iterating over a collection of items
▶︎
Breaking down a complex computation into smaller simpler ones
So in addition to combinational circuits, we need a way to store
information to enable us to construct compute systems
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From combinational to sequential
▶︎
Consider two styles of car fan control
▶︎
For the first, I know what state the circuit will be in when I change the knobs
▶︎
For the second, a specific input means nothing without knowing the current
state (the display)
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Describing sequential circuits
▶︎
▶︎
For combinational circuits we use truth tables and
equations to define the outputs as a function of the inputs
For sequential circuits, outputs also depend on the state
of the circuit
▶︎
Usually the output is the state
▶︎
We typically use the letter Q to represent the current state
▶︎
E
D
Q
0
0
Q
0
1
Q
1
0
0
1
1
1
A state transition table describes what the next state will
be based on the previous state
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Timing considerations
▶︎
▶︎
▶︎
A
We have assumed so far that
outputs change instantaneously
when inputs change
This is not realistic, since signals
take time to travel
When dealing with sequential
circuits this is more important.
Y
delay
A
Y
Time
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Timing considerations
▶︎
▶︎
▶︎
Propagation delay is the maximum
delay from the input to the output
Contamination delay is the
minimum delay from the input to
the output
These can be different due to
various low level factors affecting
rise and fall times, different paths,
etc.
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A
Y
tpd
A
Y
tcd
Time
7
Timing considerations
▶︎
In a circuit there can be multiple paths from inputs to output
▶︎
The critical path is the longest path from any input to any output
▶︎
We will learn more about how delays affect our design process later
Critical Path
A
B
n1
n2
C
Y
D
Short Path
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Timing considerations
▶︎
Consider the below circuit with no inputs and 3 outputs
▶︎
It is astable: it does not stay in one state
▶︎
It oscillates with a period that depends on the inverter delay
X
X
Y
Z
Y
Z
0 1 2 3 4 5 6 7 8 time (ns)
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A simple bistable
▶︎
With an even number of inverters, the circuit would stay in the same state
▶︎
Two outputs, the inverse of each other
▶︎
But no way to control it
I2
Q
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I1
Q
I1
Q
I2
Q
10
The SR latch
▶︎
▶︎
▶︎
▶︎
The simplest circuit for storing a
bit of data
The R input sets the output to 0
The S input sets the output to 1
When both R and S are
deasserted, the circuit maintains
its previous output
S
R
Q
Q’
0
0
Q
Q’
0
1
0
1
1
0
1
0
1
1
0
0
“deasserted” Means that a high true (active high) signal is low or that a
low true (active low) signal is high. Examples: Signal/Symbol. Logic State.
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The SR latch
▶︎
▶︎
▶︎
▶︎
The simplest circuit for storing a
bit of data
The R input sets the output to 0
The S input sets the output to 1
When both R and S are
deasserted, the circuit maintains
its previous output
CS256 Digital Design and Computer Architecture
S
R
Q
Q’
0
0
Q
Q’
0
1
0
1
1
0
1
0
1
1
0
0
11
The SR latch
▶︎
The SR latch has a problem when
both S and R are asserted then
deasserted
▶︎
▶︎
▶︎
Q and Q’ are no longer opposites
R
1
N1
0
Q
0
S
0
1
N2
0
Q
If S and R are both deasserted
there is unpredictable behaviour
The two outputs begin to oscillate
until they settle to a stable output
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The D latch
▶︎
▶︎
▶︎
This is a safer element as we can
control when inputs are seen by
the S and R inputs of the latch
As long as EN is low, both R and S
are deasserted
If we can ensure that EN is only
high when only one of S and R is
asserted, that prevents the
previous issue
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EN
EN
D
S
R
Q
Q’
0
X
X
X
Q
Q’
1
0
0
1
0
1
1
1
1
0
1
0
13
The D latch
▶︎
The output of a D latch is held while the EN input is low
▶︎
When EN is high, D flows to Q (Q “follows” D)
▶︎
We call this a level-triggered latch
clk/en
d
q
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Constructing a flip-flop
▶︎
▶︎
The main problem we have with
latches is their control/enable/
input affects the output whenever
it is high
Flip-flops work differently by
changing outputs only at a
particular instant in time
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Constructing a flip-flop
▶︎
▶︎
▶︎
▶︎
▶︎
Two opposing latches are coupled so that they are
active on opposite edges of the control signal
L1 is active/open when CLK is low, while L2 is
closed
Hence, input data flows in (N1) when CLK is low, but
nothing flows out
When CLK goes high, L2 is active/open
and L1 is closed
Hence, whatever is in N1 flows out
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d
clk
mode
n1
q
master open
slave open
master open
slave open
16
The D flip-flop
▶︎
▶︎
▶︎
▶︎
▶︎
A D flip-flop “copies” D to Q or samples D at
the moment the control input goes high
Otherwise, Q holds its value
Q does not change at any time between the
rising edges of clock/control
This is an edge-triggered flip-flop — it is
activated on the clock “edge”
Easy to understand when outputs will change
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Flip-flop variants
▶︎
▶︎
An enable input can be added to decide
when to store – important in the design of
datapaths
▶︎
EN=1: D passes to Q on the clock edge
▶︎
EN=0: Q retains its value
A reset signal can also be added to force the
output to zero
▶︎
RESET=1: Q forced to 0
▶︎
RESET=0: D passes to Q on the clock edge
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Flip-flop variants
▶︎
▶︎
An enable input can be added to decide
when to store – important in the design of
datapaths
▶︎
EN=1: D passes to Q on the clock edge
▶︎
EN=0: Q retains its value
A reset signal can also be added to force the
output to zero
▶︎
RESET=1: Q forced to 0
▶︎
RESET=0: D passes to Q on the clock edge
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Flip-flop designs
▶︎
▶︎
Usually we practically build flip
flops directly using transistors
rather than out of latches
This design has two halves:
▶︎
▶︎
First acts as an inverter when CLK
is low placing D’ on D1H and D1L
When CLK goes high one of D1H
or D1L will enable a transistor
that outputs D’’ onto Q’
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Flip-flop designs
CLK = 0
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CLK = 1
20
Registers
▶︎
▶︎
▶︎
▶︎
A flip-flop stores a single bit each
time the clock goes from 0 to 1
A bank of flip-flops with a common
clock allows us to store multiple bits
We call this a register
Registers are essential building
blocks in all types of computing
circuits
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Register timing
▶︎
▶︎
▶︎
d[2:0]
Values move from register inputs
to outputs at the clock edges
Only inputs that are present at a
rising edge will reach the output
The output will never change in
between rising edges
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D
Q
q[2:0]
Clk
clk
d[2:0]
q[2:0]
1
4
6
4
5
6
2
2
22
Shift registers
▶︎
▶︎
When multiple flip-flops are
placed in a chain, this is called a
shift register
At each rising edge
▶︎
▶︎
Sin moves to Q0
the values at Q0, Q1, Q2, and so
on move along to the right by
one position
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Shift registers
▶︎
▶︎
When multiple flip-flops are
placed in a chain, this is called a
shift register
N clock edges
At each rising edge
▶︎
▶︎
Sin moves to Q0
the values at Q0, Q1, Q2, and so
on move along to the right by
one position
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FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
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Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
CS256 Digital Design and Computer Architecture
Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
CS256 Digital Design and Computer Architecture
Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
CS256 Digital Design and Computer Architecture
Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
CS256 Digital Design and Computer Architecture
Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
FIFOs
▶︎
▶︎
▶︎
When we connect registers in the
same manner, we have a First-InFirst Out (FIFO) buffer
This behaves in the same way as a
shift register, but the input,
internal signals, and output are
multiple bits wide
You will see these often in
datapath design
CS256 Digital Design and Computer Architecture
Y
D1
Q1
D2
Q2
D3
Q3
D4
Q4
Clk
Clk_A
clk
y[2:0]
q1[2:0]
q2[2:0]
q3[2:0]
q4[2:0]
1
Clk_B
4
6
4
5
2
7
0
3
6
2
7
0
4
6
2
7
4
6
2
4
6
24
Synchronous circuits
▶︎
▶︎
▶︎
A synchronous circuit combines edge-triggered sequential elements and combinational logic
Breaks cyclic paths by inserting registers that store the state of the system, this changes at
clock edges only
Rules:
▶︎
Every element is either a register or a combination circuit
▶︎
At least one element is a register
▶︎
All registers receive the same clock signal
▶︎
Every cyclic path contains at least one register
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Counters
▶︎
▶︎
▶︎
Counters are important circuits that
generate a sequence of outputs in order
Usually, this is a rising (or falling) sequence
of binary numbers
A register’s input is connected to the
output of an adder that adds 1 to the
register’s output
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Counters
▶︎
▶︎
▶︎
▶︎
The same design can be applied to
an arbitrary width of bits
The counter will count up to the
maximum value (all 1s), then loop
back to zero
The current count (q) is
combinationally added to produce
inc
At the rising edge, inc becomes q
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Counters
▶︎
▶︎
▶︎
▶︎
The same design can be applied to
an arbitrary width of bits
inc
The counter will count up to the
maximum value (all 1s), then loop
back to zero
The current count (q) is
combinationally added to produce
inc
At the rising edge, inc becomes q
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Counters
▶︎
▶︎
▶︎
▶︎
The same design can be applied to
an arbitrary width of bits
inc
The counter will count up to the
maximum value (all 1s), then loop
back to zero
The current count (q) is
combinationally added to produce
inc
clk
q[3:0]
inc[3:0]
0
1
2
3
4
1
2
3
4
5
At the rising edge, inc becomes q
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Analysing a sequential circuit
▶︎
Considering the following circuit:
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Analysing a sequential circuit
▶︎
Considering the following circuit:
Flip-flops
connected
in a chain
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Analysing a sequential circuit
▶︎
Considering the following circuit:
Flip-flops
connected
in a chain
Internal bits connected
so contents can be read
Q bits are state
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Analysing a sequential circuit
▶︎
Considering the following circuit:
Mux chooses
between
previous
output and
D inputs
Flip-flops
connected
in a chain
Internal bits connected
so contents can be read
Q bits are state
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Analysing a sequential circuit
▶︎
Considering the following circuit:
D inputs allow data
to be loaded into all
intermediate postions
Mux chooses
between
previous
output and
D inputs
Flip-flops
connected
in a chain
Internal bits connected
so contents can be read
Q bits are state
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Analysing a sequential circuit
▶︎
When Load is high at the rising edge, the D inputs go to the Q outputs (like
a register) – this is called a parallel load
▶︎
When Load is not high, it behaves like a shift register
▶︎
The Q outputs allow all the bits to be seen at the same time
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Synchronous memory
▶︎
▶︎
▶︎
▶︎
▶︎
Registers allow us to store a piece of information
To be able to store multiple pieces and fetch them, we require multiple
registers and a way to share a single data line between them
We introduce the concept of an address to allow us to select which location
we are interested in
When the address is set, the content of that location should be output on the
data line
A separate signal can be used to control when we are writing (storing) data
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Synchronous memory
▶︎
The number of address bits
determines the number of
memory locations:
▶︎
▶︎
N bits means there are 2N
locations
The number of data bits can be
set as required for the application
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Synchronous memory
▶︎
The number of address bits
determines the number of
memory locations:
▶︎
▶︎
N bits means there are 2N
locations
The number of data bits can be
set as required for the application
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Synchronous memory
▶︎
The number of address bits
determines the number of
memory locations:
▶︎
▶︎
N bits means there are 2N
locations
The number of data bits can be
set as required for the application
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Synchronous memory
▶︎
▶︎
▶︎
A memory cell is a single bit
storage location
This is replicated to create a
memory array
When the wordline is asserted, all
bits on that row are selected
The bitlines are used to either
output the memory contents or
store new contents
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……
……
▶︎
32
Types of memory
▶︎
▶︎
Random Access Memory (RAM) is volatile
▶︎
Can be read and written quickly, but loses information without power or refresh
▶︎
Dynamic RAM (DRAM) stores data in a capacitor
▶︎
Static RAM (SRAM) stores data in cross-coupled inverters
Read-Only Memory (ROM) is non-volatile
▶︎
Retains its stored values
▶︎
Modern types like Flash can be written to (but not as fast as RAM)
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DRAM
▶︎
Data bits are stored in on a capacitor
▶︎
Value must be refreshed periodically and after reading
▶︎
Charge leakage degrades value over time
▶︎
Reading destroys the value
bitline
wordline
stored + +
bit = 1
CS256 Digital Design and Computer Architecture
bitline
wordline
stored
bit = 0
34
SRAM
▶︎
▶︎
▶︎
Value is stored in a cross-coupled
inverter arrangement and
remains until power is switched
off
bitline
bitline
wordline
SRAM can be written to much
faster than DRAM
But it has higher area (6T design
is 6 transistors per bit)
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Synchronous memory
▶︎
▶︎
▶︎
▶︎
CS256 Digital Design and Computer Architecture
The a decoder takes the address
and activates a single wordline
If writing, values are placed on the
bitlines
That enables a row of the memory
and those values are stored in the
cells on that row
If reading, the values in the cells on
that row are sensed on the bitlines
36
The clock
▶︎
▶︎
▶︎
We have seen that synchronous circuits use a clock to control the
movement of data over time
This is a signal that oscillates between 0 and 1 at a fixed frequency, hence
it is like the tick-tock of a clock
This is where the MHz and GHz numbers come from – the frequency of the
clock
clk
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The clock
▶︎
▶︎
The period of the clock is the time it takes to complete one complete
cycle – we call this a cycle
The frequency is the inverse of the period:
▶︎
10ns period = 10x10-9s, 1/10x10-9 = 108Hz = 100MHz
▶︎
1ns period = 1x10-9s, 1/1x10-9 = 109Hz = 1GHz
▶︎
4ns period = 4x10-9s, 1/4x10-9 = 2.5x108Hz = 250MHz
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clk
38
The clock
▶︎
▶︎
The period of the clock is the time it takes to complete one complete
cycle – we call this a cycle
The frequency is the inverse of the period:
▶︎
10ns period = 10x10-9s, 1/10x10-9 = 108Hz = 100MHz
▶︎
1ns period = 1x10-9s, 1/1x10-9 = 109Hz = 1GHz
▶︎
4ns period = 4x10-9s, 1/4x10-9 = 2.5x108Hz = 250MHz
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clk
38
The clock
▶︎
▶︎
The period of the clock is the time it takes to complete one complete
cycle – we call this a cycle
The frequency is the inverse of the period:
▶︎
10ns period = 10x10-9s, 1/10x10-9 = 108Hz = 100MHz
▶︎
1ns period = 1x10-9s, 1/1x10-9 = 109Hz = 1GHz
▶︎
4ns period = 4x10-9s, 1/4x10-9 = 2.5x108Hz = 250MHz
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clk
One clock
period
38
The clock
▶︎
▶︎
The source of this oscillation is usually external to the circuit, such as a crystal
oscillator
In synchronous design, we generally use one clock for all the sequential
components in our circuit
▶︎
Hence, the outputs of all those blocks will only update at the clock (rising) edge
▶︎
That way, we can more easily analyse our circuit, and model its behaviour
▶︎
More complex designs might include multiple clocks derived from the same
source clock
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Summary
▶︎
▶︎
▶︎
▶︎
▶︎
In order to build systems capable of implementing algorithms, we need a way to
store data
Feedback allows us to store state in circuits
In modern design, we are usually concerned with synchronous components,
where the output changes only at the rising edge of a clock
This makes analysing data movement in the circuit much easier than circuits using
latches
Memories can be constructed to store larger quantities of data in an organised
manner
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