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IEEE TRANSACTIONS ON ELECTRON DEVICES
1
High-Frequency Switching Properties and Low
Oxide Electric Field and Energy Loss in a
Reverse-Channel 4H-SiC UMOSFET
Zhanwei Shen, Feng Zhang , Member, IEEE, Guoguo Yan, Zhengxin Wen, Wanshun Zhao,
Lei Wang, Xingfang Liu, Guosheng Sun, and Yiping Zeng
Abstract — A reverse-channel 4H-SiC trench gate metaloxide-semiconductor field-effect transistor (UMOSFET)
(RC-MOS) is proposed in this article. The RC-MOS is
demonstrated to have low specific ON-resistance (RON,sp )
by numerical simulation. The trench oxide in the RC-MOS
is fully protected by the n+ source, the p-shield, and the
p-base regions. Thus, a reduced trench corner field far
below 3 MV/cm can be achieved in both the OFF- and ON-state.
Furthermore, the gate-to-drain charge (QGD ) of the RC-MOS
is 33 nC/cm2 , which is much lower than that of the dual buffer
layer MOSFET (DB-MOS), owing to little overlap between
the gate and drain electrodes. Consequently, the RC-MOS
exhibits the superior figures of merit QGD × RON,sp =
82 m·nC. Due to the low reverse transfer capacitance
and gate charges in the RC-MOS, the total switching
loss of 570 μJ/cm2 is decreased by 64.5% in comparison
to that of the DB-MOS. These superior properties show
that the proposed UMOSFET can be a good candidate
for further improvements in the gate oxide reliability and
high-frequency performance of SiC MOSFETs.
Index Terms — Capacitance, electric field, gate charge,
reverse-channel, silicon carbide, trench gate metal-oxidesemiconductor field-effect transistor (UMOSFET).
I. I NTRODUCTION
OWER MOSFETs in 4H-SiC (SiC-MOSFET) offer great
system advantages for high-voltage switching applications
due to their high conversion efficiency and superior cooling
P
Manuscript received February 6, 2020; revised May 13, 2020; accepted
June 24, 2020. This work was supported in part by the Beijing Natural
Science Foundation under Grant 4194094, in part by the Science
Challenge Project under Grant TZ2018003, and in part by the National
Natural Science Foundation of China under Grant 61574140 and Grant
61804149. The review of this article was arranged by Editor D. Sheridan.
(Corresponding author: Feng Zhang.)
Zhanwei Shen, Xingfang Liu, Guosheng Sun, and Yiping Zeng are
with the Key Laboratory of Semiconductor Material Sciences, Institute of
Semiconductors, Chinese Academy of Sciences, Beijing 100083, China,
and also with the College of Materials Science and Opto-Electronic
Technology, University of Chinese Academy of Sciences, Beijing 100049,
China (e-mail: zwshen@semi.ac.cn).
Feng Zhang is with the Key Laboratory of Semiconductor Material
Sciences, Institute of Semiconductors, Chinese Academy of Sciences,
Beijing 100083, China, and also with the Department of Physics, Xiamen
University, Xiamen 361005, China (e-mail: fzhang@semi.ac.cn).
Guoguo Yan, Zhengxin Wen, Wanshun Zhao, and Lei Wang are with
the Key Laboratory of Semiconductor Material Sciences, Institute of
Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2020.3005899
abilities [1], [2]. Compared with the planar gate doubleimplanted MOSFETs (DMOSFETs), trench gate metaloxide-semiconductor field-effect transistors (UMOSFETs)
are preferred because of the smaller cell pitch and higher
channel mobility along the nonpolar faces of 4H-SiC [3]–[5].
However, a number of potential issues need to be addressed
for UMOSFET, including the damaged surfaces on the trench
sidewall, the gate oxide reliability, and threshold voltage
instability [6]–[10]. Among them, one of the critical issues
is to lower the maximum electric field in the gate oxide
(E ox−max ) at the trench bottom. In general, the p-regions
underneath the trench bottom are adopted for benefits.
Nonetheless, the junction field-effect transistor (JFET) effect
is introduced by the p-shield regions and thereby increase
the total ON-resistance of the device. Aside from the doubleUMOSFET proposed by Nakamura et al. [11], many groups
have reported novel UMOSFETs with reduced E ox−max and
low specific ON-resistance (RON,sp ), like the fin-shaped and
L-shaped gate UMOSFETs [12]–[16]. However, the reduction
in the gate oxide electric field was at the added expense of the
device’s ON-resistance or power loss, and more attention must
be paid to the high-frequency properties of these devices.
Thus, another significant issue is that large miller capacitance
(CGD ) introduced by the gate-to-drain overlap can strongly
degrade the switching performance of SiC UMOSFETs.
Recently, the newly developed Infineon MOSFET had only
one side of the trench sidewall and showed low gate-to-drain
charge (Q GD ) [17]. A V-groove SiC MOSFET was achieved
with reduced CGD owing to the thick bottom oxide layer
using the C-face 4H-SiC substrate [18]. The deep-P-type
encapsulated SiC UMOSFET was also proposed and exhibited
low Q GD and superior switching performance [19]. Studies
on SiC UMOSFETs are going even further and are quite
encouraging. It is believed that with the advent of deep
trench etching and ultrahigh-energy implantation processes
in wide bandgap materials, SiC UMOSFET can be designed
and fabricated using new method to further protect the trench
oxide, reduce the ON-resistance, overcome the JFET effect,
decrease the feedback capacitance, and improve the switching
capability of the device.
In this article, a novel reverse-channel SiC UMOSFET
(RC-MOS) is proposed. The RC-MOS structure differs from
the conventional UMOSFET in the carrier conduction path.
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2
IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 1. Schematic cross section of (a) DB-MOS and (b) RC-MOS.
Both the devices feature an n-drift region with a thickness of 10 µm
(from the trench bottom to the n-buffer region), a doping concentration
of 7 × 1015 cm−3 , a p-shield doping concentration of 2 × 1018 cm−3 ,
a p-base with a doping concentration of 1017 cm−3 , and a channel
length of 0.5 µm. The DB-MOS presents dual BLs under the p-base and
involves a JFET region (first BL) with the same doping concentration of
2 × 1016 cm−3 as the RC-MOS.
In the ON-state, the electrons are injected into the inversion
channel from the n+ source at the trench bottom. After that,
the electrons pass upward the mesa side and then toward the
drain side, as shown in Fig. 1(b). In the OFF-state, the gate
oxide can be strongly protected by the grounded p-shield
regions. Therefore, the reliability of the gate oxide is not
compromised in the newly proposed structure. Meanwhile, the
RC-MOS features significantly low Q GD due to little space of
gate overhang into the n- drift region, and thus the reduction
in high-frequency switching losses can be obtained. All the
studies are conducted via simulation using Sentaurus TCAD
[20]. Shockley–Read–Hall, Auger, and incomplete dopant
ionization models are enabled in all structures. Moreover,
a positive charge of 1 × 1012 cm−2 , trapped at the SiC–SiO2
interface, is included in the simulated devices. A discussion
of the possible fabrication process is described in detail. The
parameters used in the simulation are carefully optimized to
achieve low E ox−max and RON,sp devices. The structure in [4]
features dual buffer layers in the trench regions (DB-MOS) and
is chosen to compare the parameter tradeoffs and the switching
performances in this article.
II. D EVICE S TRUCTURES AND S IMULATION R ESULTS
A. Structures and Manufacturability
Fig. 1 shows the schematic cross section of DB-MOS
[Fig. 1(a)] and RC-MOS [Fig. 1(b)]. The channel mobility is
assumed to be 50 cm2 /V·s for all structures. In the DB-MOS,
the mesa width is L mesa . With respect to the RC-MOS,
the width between two adjacent p-shield regions is L JFET ,
and the vertical distance between the p-base regions and
the mesa surface is d. The first buffer layer (BL) in this
conventional structure is the doped n-type and has the same
dopant concentration of 2 × 1016 cm−3 as the JFET regions of
the proposed device. The second BL is highly doped and can
minimize the depleted area between the p-base and the p-shield
regions. In addition, the second BL in the DB-MOS needs an
appropriate design in doping concentration (D2nd ) to achieve
excellent blocking performance. The RC-MOS and DB-MOS
feature a cell pitch of 5 μm. All the devices have the same gate
oxide thickness of 50 nm in the trench sidewall. Meanwhile,
the structures have the same oxide thickness and curvature
radius at the corners of the trench and gate electrodes, so that a
fair comparison of RON,sp and E ox−max can be ensured between
the two devices. The gate oxide thickness at the trench bottom
is increased to be 100 nm for the DB-MOS. The fabrication
process of the DB-MOS can be well-developed. The possible
process used in the fabrication of the RC-MOS is presented
in detail in the next paragraph.
First, the active regions are formed by high-energy multiple implantation. The active regions, including the p-base,
the p-shield, the n+ source, and the p+ base regions are
similar to the well regions of the conventional DMOSFET
[3], except that the active regions are beneath a main surface
of the substrate. The megaelectronvolt-class implantation or
the epitaxial regrowth techniques can be used to form the
buried well regions [12], [18]. It is of great significance to
control the precise formation of the deep well regions with
a depth of above 2 μm in the proposed structure, so as
to obtain a workable solution for SiC UMOSFET. Thus,
either the high-energy implantations or the epitaxial regrowth
technique should be carefully conducted due to the pattern
shifts which have an influence on the device performance
[21]. The Monte Carlo (MC) simulated implant profiles of
the p-shield, the n+ source, and the p-base are presented in
the next paragraph. The oxide spacers can be formed to make
submicrometer patterns [Fig. 2(a)]. Then, the gate trenches are
etched using reactive ion etching (RIE) followed by posttrench
annealing to form corner rounding [Fig. 2(b)] [22]. Next, it is
proposed to use deposition and etch-back of SiO2 to form
the thick oxide at the trench bottom [Fig. 2(c)] [13]. Gate
oxidation is carried out followed by postoxidation annealing
(POA). Afterward, doped polysilicon is deposited to fill the
trenches with the etch-back planarization process [Fig. 2(d)].
Thereafter, the gate electrodes are formed on the side wall
due to the anisotropic etching techniques [Fig. 2(e)] [23]. The
partially oxidized poly-Si is formed to make a round gate
electrode corner [Fig. 2(f)]. Then, a thick oxide is deposited
and contact opening is performed [Fig. 2(g) and (h)]. Finally,
the source and drain electrodes are defined by the ohmic alloy
[Fig. 2(i)]. The developed self-aligned implantation and selfaligned trench etching techniques can be used to solve the
fabrication issues that impact on the key parameters used in
the simulation [24], [25].
The tails of high-energy buried implantations are always
present in SiC and may have significant effects on the critical
dimension of d for the proposed device. The MC model
has been incorporated into the Sentaurus Process simulator
[26]. Here, we use the MC simulation to predict the key
dopant profiles of the well regions. Fig. 3(a) shows the final
2-D well regions formed by the MC process simulation. The
implanted profiles of the aluminum and nitrogen dopants,
along the slice directions of A–A’ and B–B’ in Fig. 3(a), are
shown in Fig. 3(b) and (c), respectively. The first p-shield
implantations have an approximate box profile at energies
of 180, 375, 700, and 1150 keV with doses of 2.9 × 1013 ,
4.15 × 1013 , 4.7 × 1013 , and 5.1 × 1013 cm−2 , respectively.
A thin SiO2 shield layer can minimize the reduction in the
surface doping concentrations. The tails of the p-shield bottom
regions exhibit approximately similar trends to those of the
p-well regions in DMOSFET [27], [28]. Likewise, the first
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Fig. 2. Fabrication process flow for the RC-MOS. (a) Formation of
the active regions. (b) Trench fabrication. (c) SiO2 deposition and etchback. (d) Gate oxide, POA, and poly-Si deposition. (e) Etching of poly-Si.
(f) Gate definition. (g) Oxide deposition. (h) Contact opening. (i) Formation of the active electrodes.
Fig. 3. (a) 2-D well regions formed by the MC process simulation.
Implanted profiles of (b) aluminum and (c) nitrogen dopants.
n+ source implantations feature a box profile at energies
of 100, 190, 350, and 630 keV with doses of 0.95 × 1015 ,
1.2 × 1015 , 1.36 × 1015 , and 1.45 × 1015 cm−2 , respectively.
The n+ source regions boast neglected tailing behaviors
in both the directions. Thereafter, the p-base regions are
implanted into the 1-μm thick regrowth layer via buried
implantations at energies of 700 and 1050 keV with doses
of 1.55 × 1012 and 2.66 × 1012 cm−2 , respectively. It is noted
from Fig. 3(b) that the simulated p-base implants show a long
tail at the surface of the wafer. However, the dopants’ level is
lower than that of the background doping concentration which
has a value of above 2 × 1016 cm−2 . Thus, the n-type conduction layer can be identified in the top regions of the SiC wafer.
The critical dimension “d” for the RC-MOS can be determined
by simultaneously controlling the thickness of the regrowth
layer, the n-type dopants’ level of the top JEFT regions,
and the energies/doses of the buried p-base implantations.
Furthermore, the accumulation mode MOSFET developed by
W. Sung exhibits the p-well underneath the n-type layer [28],
[29], which also provides guidance for the p-base engineering
in RC-MOS. These buried implants’ studies and the primary
MC simulated implant profiles are beneficial for the proposed
device to achieve a manufacturable solution in the future.
It should also be emphasized that the RC-MOS may require
a larger cell pitch compared with the DB-MOS and other
developed structures in [17] and [18] when the same design
rule is applied, because large trench width is needed to
ensure isolation between the gate and source electrodes in
3
the trench. Even though RON,sp can be continuously reduced
by scaling down the design rules and improving the cell
density, the dynamic properties may be degraded due to the
increased gate capacitances and charges when the chip area is
the same. In this article, the device cell pitch is fixed at 5 μm
to attain the same channel density between the two devices.
Meanwhile, in the RC-MOS, the trench width is 1.6 μm so
as to retain enough room for the deposition of the isolation
layer, and different values of L JFET are obtained by altering
the well region’s window. The controllability of the well
region’s window relies on advanced photolithographic and
self-aligned masking technique. With regard to the dimensions
of the trench, it can be determined by optimizing the etching
technologies and layout in the z-direction. The contacts to the
p-shield and n+ source regions can be located at selective
position orthogonal to the trench, which is similar to that
in [19]. Furthermore, according to the suggestions in [30],
miniaturized patterns can be achieved on rough SiC using a
proper small numerical aperture in photolithography. These
approaches may be used to provide guidance for the RC-MOS
in realizing 5-μm cell pitch and manufacturability.
B. Tradeoffs Between RON,sp and Eox-max
The essential models have been covered in the calculations
of RON,sp , for instance, channel mobility degradation, carrier
recombination, doping-dependent transport of the carriers, and
anisotropic material properties in 4H-SiC [31]–[34]. Because
the channel parameters have been assumed to be the same
values for all structures. The channel resistance is expected
to be nearly the same between the two. In addition, the estimated RON,sp does not include a contribution of approximately
0.7 m·cm2 from the 0.02-·cm and 350-μm substrate. Since
all the devices own the same n-drift region and contact
resistance, the difference in the total resistance may be a result
of the variation in the JFET resistance in the two devices.
As shown in Fig. 4(a), different values of L mesa , D2nd , L JFET ,
and d significantly impact on the tradeoffs between E ox−max
and RON ,sp . E ox−max is intentionally reduced below 3 MV/cm
which is commonly accepted for long-term reliability [35].
In the DB-MOS, when D2nd is 2 × 1016 cm−3 , it means
no second BL in the device. Then, the decreasing width of
the p-shield regions can result in very small E ox−max while
RON,sp is increased due to the narrow carriers’ conduction
paths, and the tradeoff is depicted by the blue short dotted
line in Fig. 4(a). When D2nd is 1 × 1017 cm−3 , the DB-MOS
exhibits better tradeoffs than the structure with high D2nd
because over-doped BL increases the electric field in the trench
corner. Fig. 4(b) also shows the effects of the trench depth
over the p-base (Dover ) on the DB-MOS’s Baliga’s figure of
merit (BFOM). When Dover is decreased, the DB-MOS with
no second BL exhibits severe degradation in BFOM due to
the increased JFET resistance between the p-base and the
p-shield regions. It is therefore preferred for the DB-MOS
with the second BL since BFOM is always kept at a high
value. In the RC-MOS, as shown in Fig. 4(a), the reduction
in RON,sp tends to saturate with d beyond 0.4 μm, because
the total resistance is mainly determined by the channel
resistance, the drift resistance, and the JFET resistance. The
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IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 4.
(a) Tradeoffs between RON,sp (VGS = 15 V) and Eox-max
(VDS = 1200 V) for the two devices. Lmesa is 2.0, 1.8, 1.6, 1.4, 1.2,
and 1.0 µm for the DB-MOS, and LJFET is 2.5, 2.30, 2.20, 2.0, and
1.5 µm for the RC-MOS. (b) BFOM for SiC MOSFETs. Full symbols
17
cm−3 ,
represent optimized structures with Lmesa /Dnd
2 = 1.0 µm/1 × 10
and d/LJFET = 0.5 µm/2 µm, which have RON,sp = 2.42 mΩ·cm2 and
RON,sp = 2.49 mΩ·cm2 , for the DB-MOS and the RC-MOS, respectively.
RC-MOS with d = 0.5 μm presents similar tradeoffs to
the DB-MOS with D2nd of 1 × 1017 cm−3 . However, it is
worth to note that the RC-MOS features smaller E ox−max than
the DB-MOS when they have the same p-shield gap of 2
μm. Meanwhile, using the same cell pitch and trench depth,
the proposed device can be designed to achieve comparable
RON,sp and BFOM with the DB-MOS. Finally, the optimized
structures are obtained with L mesaa /D2nd = 1.0 μm/1 ×
1017 cm−3 and d/L JFET = 0.5 μm/2 μm, for the DB-MOS and
the RC-MOS, respectively. The RC-MOS has a high value of
BFOM = 1054 MW/cm2 as indicated in Fig. 4(b) and exhibits
improved device performance in terms of lowering both RON,sp
and E ox−max at large JFET width scales.
The output characteristics at VGS = 15 V and the breakdown
characteristics of the two devices are shown in Fig. 5(a).
In the ON-state, the DB-MOS and the RC-MOS have RON,sp
of 2.42 and 2.49 m·cm2 , respectively, at VGS = 15 V and
IDS = 1 kA/cm2 . In addition, the DB-MOS has decreased saturation current (Isat ) compared with the RC-MOS as shown in
Fig. 5(a). This stems from the fact the DB-MOS has parasitic
JFET resistance between the p-shield and p-base regions, and
the JFET resistance between the neighboring p-shield. High
drain voltage results in more depletion layer extension and the
carrier conduction path is severely narrowed in the DB-MOS.
Therefore, during a short-circuit event, the DB-MOS may
feature smaller power consumption and better short-circuit
ruggedness than the RC-MOS [36]. However, in the OFFstate, because of large JFET width and reduced electric
field crowding in the RC-MOS, it shows higher breakdown
voltage (BV) than the DB-MOS. Furthermore, it is clear from
Fig. 5(b) that the RC-MOS exhibits less crowding current lines
than the DB-MOS at the trench corner as indicated by the
dashed box. If the avalanche current location is shifted close
to the SiC–SiO2 interface of the corner, it may lead to a high
electric field and high lattice temperature and cause thermal
rupture of the gate oxide. In addition, due to the probability
of hot carrier injection into the corner oxide, the device may
have poor long-term reliability. From this result, it can be
concluded that the proposed RC-MOS can effectively prevent
device failure and enhance the device’s avalanche ruggedness
due to the improved heat relaxation capability at the trench
corner in comparison to the DB-MOS.
As shown in Fig. 6(a) and (b), the maximum field is located
at the p-n junction for all the devices. Thus, the same behavior
Fig. 5. (a) Output characteristics (VGS = 15 V) and the breakdown
characteristics of the optimized devices and (b) total current density
distribution when avalanche breakdown occurs.
Fig. 6. Electric field distributions in SiC MOSFETs at VDS = 1200 V in
(a) and (b). Electric field distributions in SiC MOSFETs at VGS = 15 V
and VDS = 4 V in (c) and (d). (a) DB-MOS. (b) RC-MOS. (c) DB-MOS.
(d) RC-MOS.
of avalanche breakdown will occur in the body region of
4H-SiC. The peak electric field in the gate oxide occurs at
the corner of the trench for the DB-MOS due to 2-D field
crowding. With respect to the specific trench configuration,
the RC-MOS shows the value of E ox−max = 1.25 MV/cm
at VDS = 1200 V, which emerges in the upper portion of
the gate trench. Furthermore, the maximum electric field is
approximately 0.4 MV/cm in the oxide of the delicate and
well-protected trench corner, which is the lowest value in
comparison to that of 1.27 MV/cm for the DB-MOS. More
importantly, in the ON-state, high electric field can be formed
in the gate oxide of SiC MOSFETs due to positive gate
bias ranges from 15 to 25 V and thin oxide thickness of
approximately 50 nm. The devices’ failure may always occur
owing to an abrupt increase in the gate leakage current. In this
study, the ON-state gate voltage is kept at 15 V so as to
intentionally reduce the oxide field below 3 MV/cm. However,
because of the small curvature of the trench corner and 2-D
overcrowded field lines from the n-drift and the p-shield,
the DB-MOS exhibits E ox−max of 3.16 MV/cm at VGS = 15 V
and VDS = 4 V as shown in Fig. 6(c). For comparison,
the RC-MOS boasts E ox−max of 2.79 MV/cm as shown in
Fig. 6(d), and the point is located at the n+ source/p-base
regions rather than at the trench corner. The simulation results
indicate that the trench corner engineering approach can be
simplified in terms of ensuring oxide reliability in both the
ON - and OFF -state of the proposed device.
C. Methods to Reduce RON,sp of the RC-MOS and Traps
in the Intermetal Dielectric Layer
As mentioned above, the RC-MOS shows slightly higher
RON,sp than DB-MOS. However, owing to the relatively low
oxide field and large JFET width, there is still enough scope
for the ON-state resistance optimization of the RC-MOS.
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Fig. 7. (a) Effects of the doping concentration of the JFET regions and
LJFET on RON,sp and Eox-max of the RC-MOS at a given drift layer doping
level of 7 × 1015 cm−3 and (b) tradeoffs between RON,sp (VGS = 15 V)
and Eox-max and the doping concentration of the drift region, when the
JFET doping is 4 × 1016 cm−3 and LJFET is 1.5 µm in the RC-MOS.
In other words, RON,sp of the RC-MOS can be reduced
by increasing the doping concentrations of the drift region
(Ddrift ) and the JFET region (DJFET ) without significant
degradation of the gate oxide reliability in the OFF-state.
Fig. 7(a) shows the effects of DJFET and L JFET on RON,sp
and E ox−max of the RC-MOS at a Ddrift of 7 × 1015
cm−3 . As DJFET increases, RON,sp becomes smaller because
amounts of conductive carriers can be generated in the
JFET regions. RON,sp can be further reduced with large
value of L JFET , and E ox−max does not increase beyond
3 MV/cm even with L JFET = 1.8 μm and DJFET = 5 × 1016
cm−3 . On the basis of 1200-V power MOSFET designs,
we have continued increasing Ddrift at DJFET = 4 ×
1016 cm−3 and L JFET = 1.5 μm in the RC-MOS. As plotted
in Fig. 7(b), with the Ddrift range from 8 × 1015 cm−3 to
1.2 × 1016 cm−3 , RON,sp can be reduced below 2.0 m·cm2
while E ox−max is always kept at a low value of approximately
1.6 MV/cm. Meanwhile, the peak electric field still manifests
in the upper corner of the gate electrode as shown in Fig. 5(b).
The maximum field in the middle of the JFET region is only
increased from 0.5 to 0.7 MV/cm (not shown) owing to the
thick intermetal dielectric layer (IDL) and the strong protective
effect of the deep p-shield regions. This phenomenon is
distinguished from that in the planar DMOSFET with high
Ddrift /DJFET . Therefore, there will be a superior compromise
between RON,sp and E ox−max in the RC-MOS.
In addition, it is possible that charges or traps may exist
in the IDL on the top of the JFET area of RC-MOS in
real fabrication. In the simulation, we have added the trapped
charges of 1 × 1012 cm−2 at the SiC–SiO2 interfaces in the
device. However, different types of charges in the IDL may
have an influence on the device performance.
Fig. 8(a) shows the effects of the positive charges on the
output characteristics of the RC-MOS, and the traps’ density
(T ) in the IDL is varied in the range from 1 × 1012 cm−2
to 7 × 1012 cm−2 . These traps induce a positive electrostatic
potential in the IDL and are beneficial for electron transport.
However, due to high DJFET and thick IDL, the potential
fluctuation is neglected when compared with the positive drain
voltage change, leading to little variation in the I − V curves.
Nevertheless, as shown in Fig. 8(b), E ox−max increases with
increasing traps’ density, because more electric field lines
produced by the positive trapped charges are terminated in the
p-channel and the gate electrode in the OFF-state. Meanwhile,
it is noted that with increasing trench depth, E ox−max can be
5
Fig. 8. (a) Effects of the positive trapped charges in the IDL on (a) output
characteristics and (b) Eox-max .
Fig. 9. (a) Effects of the negative trapped charges in the IDL on the output
characteristics of RC-MOS with (a) d = 0.5 µm and (b) d = 1.1 µm.
(c) ON-state current density distributions and (d) tradeoffs in SiC MOSFET with different values of d.
reduced below 3 MV/cm owing to the strong charge compensation effect between the p-shield and the JFET regions.
Fig. 9 shows the effects of the negative charges on the
device performances of the RC-MOS. The values of d are
0.5 and 1.1 μm, respectively, as shown in Fig. 9(a) and (b).
These traps act as a negative potential point and severely
deplete the electrons between the upper JFET regions and
the p-channel regions, resulting in dramatically reduced drain
current in the RC-MOS. Nonetheless, the ON-state I − V
characteristics can be gradually recovered with increasing d.
As shown in Fig. 9(c), more positively charged donors can
compensate the negative trapped charges, and the extension
of the depletion is inhibited at the upper portion of the
JFET region. Therefore, a wide carrier conduction path is
produced for the RC-MOS with d = 1.1 μm. In addition,
the tradeoff curves are presented in Fig. 9(d), and E ox−max is
reduced below 1 MV/cm due to the shielding effect between
the negative trapped charges and the p-channel regions. The
negative charges almost show no influence on the tradeoffs for
RC-MOS with d = 1.1 μm.
D. Comparisons of Dynamic Performance
for the UMOSFETs
Fig. 10 shows the dynamic performance of the MOSFETs, which is mainly characterized by miller capacitance
and total gate charges (Q G ). All the dynamic simulations
for the UMOSFET structures are performed using optimized
parameters obtained in Fig. 4(a). The feedback capacitances
shown in Fig. 10(a) decrease with an increase in the dc drain–
source voltage due to the extension of the depletion layer.
The DB-MOS would exhibit low CGD because of the effective
shielding effect of the p-shield regions at the trench bottom.
However, the large depth of the trench overhang into the
drift regions of the DB-MOS creates a heavy burden on the
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Fig. 10. (a) CGD as a function of VDS at VGS = 0 and (b) VGS versus
QG . The inset in (b) is the testing circuit for QG .
dynamic performance of the device. The effective gate-to-drain
capacitance per unit area is not fully reduced in DB-MOS
when compared with the novel UMOSFET. A strong reduction
in CGD is achieved by the RC-MOS, due to the significantly
small overlap between the split-gate electrode and the n-drift
layer.
Furthermore, the gate charges are obtained using mix-mode
simulation, and the testing circuit for Q G is shown in the inset
of Fig. 10(b). The differences in the miller charges provide
validation for the differences in the feedback capacitances,
which is detrimental in reducing the switching losses of the
devices. The RC-MOS features the extremely lower miller
charge (Q GD ) of 33 nC/cm2 when compared with that of 443
nC/cm2 for the DB-MOS. Thus, it is demonstrated that superior figures of merit of Q GD × RON,sp = 82 m·nC can be
obtained by the RC-MOS.
A simple testing circuit, as shown in Fig. 11(a), is used
to achieve the switching losses of SiC MOSFETs. The SiC
diode is used to conduct the freewheeling current during
each cycle. Even though the proposed device may have large
internal gate resistance in real fabrication and hence some
additional switching losses. The issue can be addressed using a
silicided gate electrode or multiple-gate runners’ design which
exhibits excellent compromise between static and switching
performances [37]. Fig. 11(b) shows the switching waveforms
of the RC-MOS when a double pulse is applied using the
input voltage for the circuit. The maximum gate voltage
and the drain voltage are 15 and 800 V, respectively. From
Fig. 11(c), the turn-on and turn-off energy loss values can
be achieved by integrating the product of ID and VD over
the corresponding time intervals. The RC-MOS has a smaller
switching time owing to the lower gate capacitances between
the two devices. It is also due to the low gate charges in the
RC-MOS that the switching time and power dissipation can be
effectively reduced during the turn-on and turn-off transients.
As shown in Fig. 11(d), the total switching loss (E total ) of the
proposed structure is 570 μJ/cm2 , which is lower by 64.5%
in comparison to that of the DB-MOS.
E. Optimization for High-Frequency Applications
In addition, from Fig. 10(b), it is noted that the RC-MOS
shows smaller prethreshold and postthreshold gate charges
than the DB-MOS, which are defined as the charges required
to reach the gate plateau voltage. This is mainly because a
part of CGD in the DB-MOS is converted into the component
of the gate–source capacitance (CGS ) via a large coupling
Fig. 11. (a) Schematic of the testing circuit used to simulate the switching
characteristics and (b) simulated switching waveforms for a double-pulse
input. (c) and (d) Comparison of the switch losses for the two.
between the gate electrode and the bottom grounded p-shield
[Fig. 1(a)]. As indicated in Fig. 12(a), the input capacitance
(Ciss ) is the sum of CGS and CGD . The proposed RC-MOS
features low Ciss by making the minimized gate overlaps with
both the n-type and p-type regions in SiC. Therefore, it is
apparent that a much smaller Q GS , Q GD , and Q G can be
obtained in the RC-MOS when compared with the DB-MOS.
More significantly, for high operating frequency applications,
such as high-speed photovoltaic grid-connected inverters and
switch-mode power supplies, it is of great importance to
reduce the total power loss (Ptotal ) within the power MOSFETs. With a duty cycle δ, Ptotal involves in the ON-state power
loss and the switching power dissipation [38]
RON,sp
2
+ ACiss
VGS f
(1)
A
where δ represents the ratio of the ON-state interval to the
switching cycle, A is the device active area of the MOSFET,
VGS is the operating gate voltage, f is the switching frequency,
and Ion is the ON-state current. We have calculated the total
power loss as a function of the device active area as shown
in Fig. 12(b), where Ion is 10 A, δ is 0.5, RON,sp is the
value obtained in Fig. 4(a), VGS is 15 V, and Ciss is the
value at low drain–source voltage in Fig. 12(a). As shown in
Fig. 12(b), the DB-MOS boasts low Ptotal for small die area,
which is good for the cost reduction of the devices. However, significantly large Ptotal is obtained with the increasing
operating frequency, leading to a detrimental factor in the size
and weight reduction of passive components. Fortunately in
the RC-MOS, the total power loss is less than that of the
DB-MOS. Thus, the proposed structure will show superior
heat sinking capability for high-efficiency and high-frequency
power conversion applications.
Eventually, the static and dynamic characteristics of the
above UMOSFETs are summarized in Table I. Between the
two devices, the DB-MOS has lower saturation current and
RON,sp , which are balanced by increasing Q GS and Ciss . With
respect to the RC-MOS, it exhibits comparable RON,sp to
the DB-MOS and features both the lower OFF-state E ox−max
(1.25 MC/cm) and ON-state electric field in the trench corner
2
Ptotal ≈ δ ION
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SHEN et al.: HIGH-FREQUENCY SWITCHING PROPERTIES AND LOW OXIDE ELECTRIC FIELD AND ENERGY LOSS
7
R EFERENCES
Fig. 12. (a) Comparisons of the input capacitance for the SiC UMOSFETs and (b) optimization of the total power losses for the UMOSFET
structure with different active areas and operating frequencies.
TABLE I
C OMPARISONS OF THE C HARACTERISTICS FOR THE DB-MOS AND
THE RC-MOS
(E ox−corner is below 0.5 MV/cm). Thus, the RC-MOS significantly improves the trench corner oxide reliability which is
the specific threat to the commercialization of SiC UMOSFET.
Furthermore, the RC-MOS shows the best high-frequency
figures of merit of Q GD × RON,sp and lower Q G and E total in
comparison to the DB-MOS. Therefore, the RC-MOS makes
considerable enhancements to the high-frequency switching
performance of the device and enriches the trench topologies
on the future of SiC MOSFETs.
III. C ONCLUSION
The 4H-SiC UMOSFET with RC-MOS is characterized
by simulation using Sentaurus TCAD. The novelty of the
RC-MOS lies in the p-shield regions introduced in the bottom
of the trench, which is also considered as the source region
to form an upside down carrier conduction paths in the
channel region. The RC-MOS features low RON,sp with the
gate oxide field at the trench corner far below 3 MV/cm.
Moreover, due to strong screening effect of the p-shield
regions, the RC-MOS has smaller Q GD of 33 nC/cm2 and
reverse transfer capacitance (CGD ) when compared with the
DB-MOS. Consequently, the total switching loss of the proposed structure is 570 μJ/cm2 , which is 64.5% lower than that
of the DB-MOS. This is a huge benefit because the RC-MOS
improves both the oxide reliability and the dynamic characteristic of the device, which provides superior advantages
to the next-generation SiC-UMOSFETs for high-frequency
application.
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