1/19
Fall, 2010 RF CMOS Tranceiver Design
Tutorial-2
Low Noise Amplifier (LNA) Design
Written By: Rashad.M.Ramzan
rashad.ramzan@nu.edu.pk
Objective:
Low noise amplifiers are one of the basic building blocks of any communication system.
The purpose of the LNA is to amplify the received signal to acceptable levels with
minimum self generated additional noise. Gain, NF, non-linearity and impedance
matching are four most important parameters in LNA design.
The objective of this tutorial is to outline the basic tradeoffs between different amplifying
topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded
that inductor degenerated common source topology gives the best performance to meet
the gain, NF, and impedance matching goals with minimum power consumption in case
of narrow band designs.
Goals:
After this tutorial, students should be able to

Calculate the gain, input impedance and NF of common gate, common source,
and shunt feedback amplifiers.

Understand the basic equations and tradeoff between different LNA topologies.
 Perform the calculation for inductor degenerated common source topology and
understand the tradeoff between the gain, NF, and impedance matching.
A supplement tutorial LNA lab is also part of this course which takes the circuit
from Problem-2.8 and guides through different analysis to design and practical
LNA.
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
2/19
Fall, 2010 RF CMOS Tranceiver Design
Problem-2.1(Tutorial)
T is single figure of merit for high frequency transistors. This is defined as frequency at which
current gain is extrapolated to fall to unity.
Although the dc gate current of an MOS transistor is essentially zero, the high- frequency
behavior of the transistor is controlled by the capacitive elements in the small- signal model,
which cause the gate current to increase as frequency increases.
a) Derive the expression for T.
b) For RF design we always use minimum length transistors. Why?
Solution:
a).
Io
Iin
Iin
G
Vgs+
-
Vgs+
-
Cgd
D
Cgs+Cgb
Io
gmVgs
S
Vsb = Vds = 0
So gmb, ro, Csb, Cdb have no effect on calculations. (This is drawback of
 t definition)
ii  j (C gs  C gb  C gd )Vgs
ii  g mVgs
io
gm

iin j C gs  C gb  C gd 
According to definition
  T 
io
 1 at T
iin
gm
C gs  C gb  C gd
Cgb and C gd are small compared to Cgs
So,
T 
b). I D 
gm 
gm
g
 m
C gs  C gd C gs
oCox W
2
L
V
-----------------------(1)
 VT 
2
gs
I D
W
  o Cox Vgs  VT 
L
Vgs
-----------------------(2)
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
3/19
Fall, 2010 RF CMOS Tranceiver Design
And
Cgs  Co  WL
-----------------------(3)
Put (2) & (3) in (1)
T 
T 
g m  o CoxW Vgs  Vt   o Vgs  Vt 


C gs
L.C ox .W .L
L2
 o Vgs  Vt 
L2
This means that
T 
1
L2
so that’s why minimum L is preferred. But this approximation holds
for long channel devices for short channel
T 
1
1
instead of 2
L
L
.
Problem-2.2(Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to
PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS
transistor is in saturation.
a) Consider simplified square law model. (HW)
ID 
Kn
(VGS  VT )2
2
b) Consider the short channel effects as (Tutorial)
K n  (VGS  VT )2 


2 1   (VGS  VT ) 
  Velocity Saturation, Mobility Degradation
ID 
VGS  VT  0.2V
and   0.1V 1
c) What conclusion can be drawn from part b) about the bias current and transconductance
of transistor for higher IP3?
Solution:
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
4/19
Fall, 2010 RF CMOS Tranceiver Design
a). Home work Ans: IP3  
b). From Razavi
y ( x)   1 x(t )   2 x 2 (t )   3 x 3 (t )
---------------(1)
VDD
4 1
3 3
x (t )  A cos 1t  A cos 2t  IP3 
RL
2
K VGS  VT 
ID  n
2 1   (VGS  VT )
X(t)
NMOS
VGS
Here we assume that small signal x(t) over-rides (VGS – VT).
DC-bias
So,
K VGS  VT   x (t )
ID  n
2 1   (VGS  VT  x(t ))
2
& VGS
 VT  V
X(t)
--------------- Small signal
--------------- Large signal
x(t )  V 
K
ID  n
2  ( x(t )  V )  1
2
2
K R  x(t )  V 
Vo  I D RL  Vo  n L
2 1    x (t )  V 
  1 So  x( x)  V  is also small 
put
K n RL
K
2
1
x
1
1 x
2
1
  x(t )  V 
1
1    x (t )  V 
2
  x(t )  V  
2
Vo  K  x(t )  V  1 

2


2
3 K
Vo  K  x(t )  V    x (t )  V 
2
K
3K 
3 K
K 3




Vo  KV 2 
x (t )
V  x 2 (t ) 
V 3   2 KV 
V 2  x(t )   K 
2
2
2
2




---------------(2)
Small signal components
3 K
3K 
K 3




V 2  x(t )   K 
V  x 2 (t ) 
Vo   2 KV 
x (t )
2
2
2




EE Department, FAST-NU, Islamabad, Pakistan
---------------(3)
rashad.ramzan@nu.edu.pk
5/19
Fall, 2010 RF CMOS Tranceiver Design
Comparing (1) & (3)
1  2 KV 
3K
3K
V
V 2 ,  2  K 
2
2
,
3  
K
2
3
2 Kv  KV 2
4 1
4
8  2V

2
IP3 



 3V 2 

K
3 3
3
3 

2
IP3 
8 2 V
16 V

3 
3 
2
As   1 3V can be ignored.
16 V
16 VGS  VT 

3 
3

V  0.2V ,   0.1
IP3 
Put
IP3 
---------------(4)
 ID 
gm 
16 0.2
 3.27Volts
3 0.1
 o C ox W
2
L
VGS
2
 VT 
W
I D
  n Cox VGS  VT 
VGS
L
gm
2
2


I D VGS  VT V

 3.27  2 1 
IP3(dBm )  10 log 
 .  1mW   20dBm This is just an approximation with ID

 2  50 
& gm
gm
2
2


I D VGS  VT V
 IP3 
32 I D
3 g m
 g m   n C ox
W
ID
L
c).
- To increase IIP3 ID
 (high power) or gm 
- gm also depends upon ID, so when ID
- When W increases gm


gm
(high noise)

but at that rate
 ID
for same ID (Power consumption) so this decreases IP3
- The above observations are for long-channel. But for short channel
ID
4  VGS  VT   then
 any how.
Problem-2.3 (Tutorial)
It is preferred in current RF designs that the input of LNA be matched to 50 Ω (Razavi, Pg168).
The easiest way is to shunt the gate with a resistor of 50 Ω.
a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that Rsh=RL
for NF derivation.
b) What are the disadvantage of shunt resistor with reference to gain and NF?
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
6/19
Fall, 2010 RF CMOS Tranceiver Design
Solution:
a). (Please read assumption in problem statement carefully)
VDD
V 2 n ,Rs
Rs
G
Rsh
V
2
Vout
D
gmVgs
n , Rsh
i2d
RL
Vin
RL
Vout
Rs
Rsh
S
Zin
RL is noiseless
F
(Baising not shown)
Total output noise power
Output noise due to input source
V 2 m, Rs  4 KTRs f
Gain Gate   g m RL
V 2 m, Rsh  4 KTRsh f
 Rsh 

A  g m RL 

R
R
sh 
 s
i 2 d  4 KTg m f
A  gm
for Rsh = Rs
RL
2
Using superposition, considering one at a time and shorting / opening other sources.
V
2
V
2
on , Rs
on , Rsh
 Rsh 

 V n ,Rs  g m RL  
 Rs  Rsh 
2
2
2
2
 Rs 

 V n , Rsh  g m RL  
 Rs  Rsh 
2
2
2
2
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
7/19
Fall, 2010 RF CMOS Tranceiver Design
V 2 no,d  i 2 d  R 2 L
F
V 2 on ,Rs  V 2 on ,Rsh  V 2 no ,d
V 2 on , Rs
1
V 2 on ,Rsh  V 2 o ,d
V 2 on,Rs
g 2 m R 2 L  R 2 sh
4 KTRsh f 
Rs  Rsh 2
4 KTg m f  R 2 L

F 1
g 2m R2L  R2s
g 2m R2L  R2s
4 KTRs f 
4 KTRS f 
Rs  Rsh 2
Rs  Rsh 2
In case of impedance match Rs = Rsh
R 2 Lg m
R 2 Lg m
4
2
2
F 11
2
2
2
2
2
g mR s  R L
g mR L
g m Rs

Rs 
R
s
2
4R s
4
b).
- Poor Noise Figure
- Input signal attenuated by voltage divider
- Rsh adds extra noise.
- At high frequency, shunt L is needed to tune out Cgs
- Reduced gain
Problem-2.4 (Tutorial)
Another approach to get 50 Ω input impedance match is shunt feedback amplifier shown below.
a) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
8/19
Fall, 2010 RF CMOS Tranceiver Design
Solution:
VDD
V
Rs
2
n , RF
RF
Vout
RL
Vout
RF
V
2
I 2 nD
gmVgs
n , Rs
Rs
RL
Vin
Zin
(Equivalent noise model ignoring gate noise), RL is noiseless
(Baising not shown)
I 2 nD  4 KTg m f ,V 2 RS  4 KTRS f
NF 
V 2 n,out
A2 v ,tot V 2 RS

Total input noise power
Output noise power due to input source
Here Av,tot = Gain from Vin to Vout
Again using superposition theorem
NF 
V 2 n,out
A2 v ,tot V 2 RS

Vn
2
RS ,out
 Vn
2
RF ,out
 Vn
2
D ,out
A 2 v ,tot V 2 RS
Gain Calculation
Vin  iin RS  RF   Vout
Iin RF
Vout  iin  g mVgs RL
Av ,tot 
Rs
Iin
Vgs  iin RF  Vo
Vout
RL
Vout
RL 1  g m RL 

Vin RS  RF  RL  g m RS RL
If RF>>RS & gmRF>>1
Av ,tot 
 g m RL
  g m RL
RS
1  g m RS
 1  RL 
RF
RF
iin
Vin
Rs
Vgs
RF
Vout
gmVgs
Av ,tot   g m RL
Also
Z in 
RF  RL
1  g m RL
By ignoring C gs, we have considered real part only.
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
RL
9/19
Fall, 2010 RF CMOS Tranceiver Design
For source resistance
V 2 nRS ,out  A 2 v ,tot V 2 nRS
---------------(1)
For feedback resistance
RF V
Rs
i
2
V 2 RF ,out
RF
gmVgs
Vgs
RL
Vgs  iRS  iRF  VRF  VRF ,out
VRF ,out  RL i  g mVgs 
1
VRF ,out  VRF
1
V
2
n , RF ,out
RS  RF
RL 1  g m Rs 
 VRF

R
 V n ,RF  L 1  g m RS 

 RF
RL
1  g m RS 
RF
2
2
---------------(2)
Similarly
Rs
i
Vgs
VnD ,out
RL
VnD ,out 
I 2 n ,D
gmVgs
VnD ,out
 I nD  g mVgs 
Vgs  RS
V 2 nD ,out
RF
RS  R F
RL
0
VnD ,out
RS  RF
I n ,D
g R
1
1

 m S
RL RS  R F RS  RF
 I nD RL
So,
V 2 nD ,out  I 2 nD RL
2
---------------(3)
Combaining (1) (2) & (3)
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
10/19
Fall, 2010 RF CMOS Tranceiver Design
2
R

V n ,RF  L 1  g m RS 
RF
I 2 nD R 2 L


NF  1 
 2
A 2 v ,tot V 2 n ,RS
A v ,tot V 2 n , RS
2
Av ,tot   g m RL , V 2 n, RS  4 KTRS f
R
NF  1  S
RF

1
1 
g m RS

,
V 2 M ,RF  4 KTRF
&
I 2 nD  4 KTg m
2


 
g m RS

b).
NF

gmRS

& RF  usually
RS  50
- Better performance than CS amplifier
- RF induces noise
- At f
 need shunt inductor to tune out Cgs
- Broadband Amp @ Lower frequency
- To make NF

RF > RS gmRS >> 1
Problem-2.5 (HW)
Common gate amplifier also offers 50 Ω input impedance match and solves the input matching
problem.
c) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
a) What are the disadvantage of common gate amplifier with reference to gain and NF?
Problem-2.6 (Tutorial)
The disadvantages of three types of amplifiers in Problem-3, 4 & 5 can be circumvented by using
source degenerated LNA shown below.
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
11/19
Fall, 2010 RF CMOS Tranceiver Design
a) Calculate the input impedance. This inductor source degenerated amplifier presents a
noiseless resistance for 50Ω for input power match. How we can cancel the imaginary
part of complex input impedance so that the LNA presents 50Ω real input resistance at
input port.
b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to
source capacitance.
c) Cgd bridges the input and output ports. The reverse isolation of this LNA is very poor.
Why reverse isolation is important? Suggest the modification to improve reverse
isolation.
Solution:
a).
VDD
VS
Rs
Lg
iin
io
Vout
gmVgs
Zin
Vin
Vgs
Rs
VS
Ls
Lg
RL
Vout
Ls
(Baising not shown)
From model above we can write
 1 
Vin  iin  jLg  jLs   iin 
  io jLs
 jc 
1
io  g mVgs  g m iin 
---------------(2)
jC gs
---------------(1)
Substituting (2) in (1)

g L 
1
Vin  iin  j Lg  Ls  
 m s
jC gs
C gs 

EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
12/19
Fall, 2010 RF CMOS Tranceiver Design
Z in 
Vin
g L
1
 j Lg  Ls  
 m s
iin
jC gs
C gs
Z in  j Lg  Ls  
g L
1
 m s
jC gs
C gs
For matching Lg + Ls are canceled out by C gs. So at frequency of interest
o Lg  Ls  
And
1
1
2
 o 
 o C gs
Lg  Ls C gs
RS  50 
gm
Ls
C gs
Notes:
a). Ls is typically small and may be realized by bond wire.
b). Lg can be implemented by spiral/external inductor.
b).
From part a)
Z in  j Lg  Ls  
Reference:
For series RLC Circuit
R
L
g L
1
 m s
jC gs
C gs
We can draw this circuit as
Rs
Vin
Vin
Lg + Ls
gm
Zin
Ls
Cgs
1 L o L
1


R C
R
o RC
And VC  QSVin
Qs 
Cgs Vgs
Here
Qin 
 T 
Qin 
For problem (1)
 o Lg  Ls  o Lg  Ls 
RS 
C VC
g m LS
C gs

T 
RS  WT LS
gm
Unity gain frequency
C gs
for current
gm
C gs
1

 o  RS 

g m LS
C gs

C gs


For match load
EE Department, FAST-NU, Islamabad, Pakistan
RS 
g m LS
C gs
rashad.ramzan@nu.edu.pk
13/19
Fall, 2010 RF CMOS Tranceiver Design
Qin 
1
2o Rs C gs
Gain
Vgs  QinVin
Vout
Rs
V
g m  out
Vgs
Vin
Vgs g m
V
Gm  out 
 Qin g m
Vin
Vin
Lg
Vgs
Zin
RL
Ls
Gm  Qg m
So,
Gain  Gm RL
or
 Qin g m RL
Gm  Qin g m
&
Noise Figure:
NF 
Total noise power at output
noise power at output due to input source
For this calculation we ignore channel noise.
F
V 2 nRS ,OUT  V 2 nD ,OUT
V 2 nRS ,OUT
1
V 2 nD ,OUT
V 2 nRS ,OUT
V 2 nD ,OUT  i 2 n ,D R 2 L
i 2 n, D  4 KTg m f
V 2 nRS ,OUT  V 2 n ,RS G 2 m R 2 L
V 2 n, RS  4 KTRS f
F 1
F 1
i 2 n, D R 2 L
V 2 n, RS Q 2 in g 2 m R 2 L
&
Gm  Qin g m
i 2 n, D  4 KTg m , V 2 n, RS  4 KTRS

g m RS Q 2 in
Notes:
- Very good NF value
- Narrow band matching
- NF
 with Q 2
- The Q is dependent upon L g + Ls, Ls is small so Q depend upon Lg
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
14/19
Fall, 2010 RF CMOS Tranceiver Design
C). Draw Backs
i).
VDD
VS
Rs
VDD
RL generates noise so replace
RL with LD so that’s
RL
Vout
Lg
o 
1
LD C L
LD
VS
Rs
CL
Lg
Ls
Ls
The CL can be the input capacitance of mixer or filter.
ii).
VDD
Reverse Isolation
Cgd
LD
Vout
CL
Vb
Rs
Lg
Lo
Ls
Reverse isolation depends upon Cgd to make it better cascade input device
(Final Design)
Problem-2.7 (HW)
Fill-in the Table below, use the data from Problem-2.4, 2.5, 2.6 and 2.7
Type of LNA
Shunt Resistor
Zin
Noise Factor
Rsh
2
4
g m RS
Gain
NF (dB)
 g m RL
2
Common Gate
Shunt Feedback
Source Degenerated
a) Calculate the NF for all above amplifiers. Assume γ=2, gm = 20mS, Rs = 50Ω, RF =
500Ω, and Qin = 2.
b) Which is best topology for Narrow Band LNA design at high frequency?
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
15/19
Fall, 2010 RF CMOS Tranceiver Design
Problem-2.8 (Tutorial)
Real Design: We will design the inductor source degenerated LNA shown in Fig below to meet
the specification outlined for IEEE802.11 (b) standard. The first cut approximate values are
calculated as a starting point for simulation. In LAB3: Design of LNA you will take the same
design and modify these component values to meet the specification.
LNA Specification:
NF < 2.5 db, Gain > 15dB, IP3 > -5dBm, Centre Frequency = 2.4 GHz
S11 < -20dB, S22 < -10dB, Load Capacitance = 1pF
Technology Parameters for 0.35um CMOS:
Leff  0.35 m,  n Cox  170  A V 2 , Cox  4.6 mF m 2 ,  p Cox  58  A V 2 ,   2
Solution:
 oCox  170 A V 2 ,  pCox  58 A V 2 ,0.35m

2
Technology: CMOS , Cox  4.6 mF m ,   2, f o  2.4GHz
 IEE 802.11(b) S tan dard ,  C  170 A V 2

o ox





Design Parameters
RS  50, VDD  3.3V , CL  10 PF , NF  2.5dB
VDD
RREF
LD
M3
M2
RBIAS
Vout
Lg
M1
Vin
RS
CB
EE Department, FAST-NU, Islamabad, Pakistan
CL = 10pF
Ls
rashad.ramzan@nu.edu.pk
16/19
Fall, 2010 RF CMOS Tranceiver Design
Component Description
Ls – Matches input impedance
Lg – Set the Resonant Frequency fO = 2.4 GHz
M3 – Biasing transistor which forms current mirror with M1
Ld – Tuned output increases the gain and also work as band pass filter with CL
M2 – Isolate tuned input and tuned output increases reverse isolation, also reduces the effect of
Miller capacitance Cgd
CB – BC Blocking capacitor chosen to have negligible reactance at fO = 2.4 GHz
RBIAS – Large enough so that its equivalent current noise is small enough to be ignored. (Don’t
consider it as voltage noise source. Why??)
Design Procedure
Size of M1:
We will not go for global minimum noise figure as given by two-point noise theory (See lecture
on LNA Slide # 10)
Gopt   C gs

1
2
1 C 
50
5


---------------(1)
C gs  4 pF  WM 1  4mm!! (not possible)
Solution:
A & B are from Thomos. H. Lee book (LNA Chapter)
LNA NF will be optimized for given Power
* It will not be best NF globally.
Wopt 
1
3o Leff Cox RS
Fmin, p  1  2.4
 

 Fmin, p  1  5.6
 T
T
---------------(A)
From (1) we can derive
Fmin, p  1 
2 

2
C 1  C  1  2.3
T
5 T
Fmin, p  1  2.3


T

---------------(B)
(a) is minimum NF for a given power consumption.
(b) is global minimum noise figure.
The difference is usually 0.5dB to 1dB (no big deal for Lower Power)
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
17/19
Fall, 2010 RF CMOS Tranceiver Design
Step - 1:
I1  I 2  5mA (Low Power consumption)
Step - 2:
1
3WLeff Cox RS
WM 1 
WM 1 
1
3  0.35  4.6m  50  o

 RS  50, Cox  4.6 mF m 2 ,


  n Cox  170 A V , Leff  0.35m, 



 o  2f o , f o  2.4GHz
WM 1  3.9  104
WM 1  3.9  104  390m
Step - 3:
2
C gs1  WM 1 Leff C ox
3
C gs1 
2
 390  0.35  4.6m  0.41 pF
3
W 
g m1  2  n Cox   I DM 1
 L M 1
 390 
g m1  2  170  
  5m  43 mA V
 0.35 
T 
g m1 43 mA V

 104G rad Sec
C gs1 0.41 pF
Assuming
Now
 2
Fmin  1  5.6
Fmin  1  5.6
o
T
2 2.4G
 2.55dB
104G
NF  2.55dB
It’s very close to what we derive, if the value is higher we can increase ID to increase
hence low NF on expense of power.
EE Department, FAST-NU, Islamabad, Pakistan
T and
rashad.ramzan@nu.edu.pk
18/19
Fall, 2010 RF CMOS Tranceiver Design
Step - 4:
Source and gate inductance such that they cancel Cgs and set
50 input impedance
o  2f o  2 2.4  15G rad Sec
From previous problem
RS  RTransformed  g
LS 
RS
T

LS
 LS T
C
gs
m
50
 0.5nH
100G
LS  0.5nH can be implemented using Band wire.
Now
Lg  Ls 
Lg  Ls 
1
 o C gs1

2

1
 10.81nH
15G   0.41 pF
2
Lg  10nH
Step - 5:
Ld 
1
 o 2C L
Ld 
1
 4.4nH
15G 2  1 pF
 C L  1 pF
Ld  4.4 nH
Step - 6:
Size of M3 is chosen to minimize power consumption
WM 3  70 m, RREF  2 K  I 3  0.6mA
RBIAS  2 K
(Large enough so that it’s equivalent current noise can be neglected)
C B  10 pF ( X C  6.6
so good value @ 2.4G
XB 
1
 6.6 )
2f o C B
Step - 7:
Size M2 = M3
So that they can have shared Drain Area..
(Note: We will simulate same design in LAB # 2)
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk
Fall, 2010 RF CMOS Tranceiver Design
19/19
Problem-2.9 (Point to Ponder):
Connecting two Inductor source degenerated LNA as shown in Figure make the differential LNA.
Differential LNA has many advantages: higher common mode rejection ratio, less sensitivity to
the ground inductance variation Ls compared to single ended counterpart..
a) Compare intuitively the NF of single ended and differential if both have same power
consumption.
b) If low power is not parameter on interest, which LNA has lower NF?
Instructions:
For hand calculation of NF you can ignore the gate noise of the device and noise generated by the
load resistance RL.
Acknowledgement: The major part of this tutorial was developed, while author was employed by
Linkoping University, Sweden.
EE Department, FAST-NU, Islamabad, Pakistan
rashad.ramzan@nu.edu.pk