ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / OVERVIEW
Session 3 Overview: Analog Techniques
ANALOG SUBCOMMITTEE
Session Chair: Jiawei Xu
Fudan University, Shanghai, China
Session Co-Chair: Jens Anders
University of Stuttgart, Germany
This session highlights advances in the state-of-the-art in various analog techniques. This includes a high-performance current reference and
deeply scaled temperature sensors (Papers no. 3.1, 3.7, and 3.8), energy-efficient precision frequency references (Papers no. 3.2 and 3.3),
scalable and high-performance sensor interfaces (Papers no. 3.4 through 3.6 and Paper no. 3.10) as well as a new bootstrap switch architecture
for deeply scaled CMOS technology nodes (Paper no. 3.9).
1:30 PM
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C
Pangi Park, Korea Advanced Institute of Science and Technology, Daejeon, Korea
In Paper 3.1, KAIST presents a PVT-insensitive sub-ranging current reference that achieves a low average temperature
coefficient of 11.4ppm/°C over a wide temperature range from -20°C to 125°C using a single batch calibration.
1:55 PM
3.2 A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS with ±900ppm Inaccuracy from -40°C to 125°C
and ±1600ppm Inaccuracy After Accelerated Aging
Yihang Cheng, Tsinghua University, Beijing, China
In Paper 3.2, Tsinghua University and TU Delft introduce a compact RC frequency reference based on N-diff resistors,
which uses a BJT-based temperature compensation circuit to cancel its first and second-order temperature coefficients.
It achieves a 0.028mm2 area in a standard 0.18um technology and an inaccuracy of ±1600ppm from -40°C to 125°C
after accelerated aging.
2:20 PM
3.3 A 0.5V 6.14µW Trimming-Free Single-XO Dual-Output Frequency Reference with [5.1nJ, 120µs] XO Startup and
[8.1nJ, 200µs] Successive-Approximation-Based RTC Calibration
Rui Luo, University of Macau, Macau, China,
In Paper 3.3, the University of Macau presents a 0.5V single-crystal dual-output frequency reference that features an
on-chip real-time clock (RTC), which is periodically calibrated against the crystal oscillator (XO) in a successiveapproximation manner. In combination with a frequency multiplier, the RTC is used to kickstart the XO.
2:45 PM
3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BW/Power Scalable Sensor Interface with a Dynamic Bandgap Reference
and an Untrimmed Gain Error of ±0.26% from -40°C to 125°C
Zhong Tang, Vango Technologies, Hangzhou, China
In Paper 3.4, Vango Technologies, Zhejiang University, and TU Delft introduce a BW/power scalable sensor interface,
including a fully dynamic ΔΣ modulator with an embedded bandgap reference (BGR). By employing a time-domain
TC compensation scheme, it has an untrimmed gain error of ±0.26% from -40°C to 125°C. It maintains ~85dB
SNDR over a scalable BW ranging from 98Hz to 5.9kHz and a dynamic power ranging between 1.7μW and 50.8μW.
52 • 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 1:30 PM
3:35 PM
3.5 A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ Magnetometer with Background Gain Calibration and ShortTime CDS Techniques
Ippei Akita, AIST, Tsukuba, Japan
In Paper 3.5, AIST and Aichi Steel present a 3.96mW ΔΣ magnetometer with 45pT/√Hz input-referred noise. The
design displays gain-robustness and low-power operation by using both a novel CDS technique and a new
background calibration scheme. The proposed magnetometer achieves an FoM of 1.25fW/Hz.
4:00 PM
3.6 An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW Power all over 129.5dB Dynamic Range for
Electrochemical Biosensing
Muhammad Abrar Akram, New York University Abu Dhabi, Abu Dhabi, United Arab Emirates
In Paper 3.6, New York University, Abu Dhabi, the Catholic University of Korea, and New York University, New York
propose a new potentiostat architecture based on digital LDO structures, which removes the need for amplifiers
and passive elements. With its largely digital architecture, the proposed IC consumes 3.7 nW of dynamic power
and an area of 0.266 mm2 in 0.18μm CMOS, while providing a dynamic range of 129.5 dB.
4:25 PM
3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy from -55°C to 125°C and a
200fJ∙K2 Resolution FoM
Nandor G. Toth, Delft University of Technology, Delft, The Netherlands
In Paper 3.7, TU Delft proposes an NPN-based temperature sensor that achieves both state-of-the-art energy
efficiency (200fJ∙K2 FoM) and inaccuracy (0.1°C (3σ) from -55°C to 125°C). It does so by combining a low-noise
current-mode front-end with a beta-compensation scheme, dynamic error correction techniques, and room
temperature calibration.
4:50 PM
3.8 A 0.65V 900μm2 BEoL RC-Based Temperature Sensor with ±1°C Inaccuracy from -25°C to 125°C
Bei-Shing Lien, TSMC, Hsinchu, Taiwan
In Paper 3.8, TSMC presents a Back-End-of-Line (BEoL) RC-based temperature sensor for hot-spot thermal detection
realized in a 3 nm FiNFET node. Operating with a supply voltage below 1V, the sensor achieves an inaccuracy of
±1°C with a room-temperature 1-point calibration and a compact sensor footprint of 900μm2.
5:05 PM
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA’s 0.7V
Thin-Gate-Oxide Transistor
Sangheon Lee, Samsung Electronics, Hwaseong, Korea
In Paper 3.9, Samsung Electronics introduces a new bootstrapped sampler architecture capable of sampling input
levels up to 1.2V inputs with a 0.7V supply, without reliability and leakage issues. The bootstrapped sample is then
used to build the first reported 0.7V 12-bit SAR ADC in a 3nm GAA process.
5:20 PM
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted
First Stage in 22nm/180nm CMOS
Xinhang Xu, Peking University, Beijing, China
In Paper 3.10, Peking University and Nano Core Chip Electronic Technology present a capacitively coupled
instrumentation amplifier (CCIA), which provides a power-efficiency factor (PEF) of 0.69/0.58 with a power
consumption of 1.6nW/24nW in 22nm and 0.18μm CMOS, respectively. This is achieved by an input-boosted first
stage, effectively lowering the IRN for a given supply current. Compensation circuits are used to address the leakage
current issues over a wide temperature and voltage range.
DIGEST OF TECHNICAL PAPERS •
53
3
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.1
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving
11.4ppm/°C from -20°C to 125°C
Pangi Park1, Junghyup Lee2, SeongHwan Cho1
Korea Advanced Institute of Science and Technology, Daejeon, Korea
Daegu Gyeongbuk Institute of Science and Technology, Daegu, Korea
1
2
Improving the temperature stability of the reference current (IREF) is essential for the
reliable operation of precision electronics for various applications, including automotive
and industrial sensors. There are several approaches to generate a temperature-stable
IREF, which include a weighted sum of PTAT and CTAT currents, dividing a reference
voltage by a resistor with a similar temperature coefficient (TC) [1-3], and biasing a
MOSFET at its zero-temperature-coefficient bias point [4]. While these techniques can
remove the first-order TC, the remaining curvature due to the second-order TC limits the
achievable temperature stability. In [5], the curvature in a reference current is corrected
by using a curvature-corrected bandgap reference voltage and a switched capacitor
resistor. However, it requires a stable and bulky reference oscillator (e.g., crystal).
An alternative way to reduce the curvature is to exploit the fact that the impact of
curvature is less significant in a narrower temperature range. Therefore, by dividing the
wide temperature range and applying TC compensation to each sub-range, the curvature
can be reduced. In a voltage reference [6], the curvature is segmented and compensated
segment-wise to reduce the temperature range. However, abrupt voltage changes occur
at the segment boundaries where the transition occurs, which limits the temperature
stability. In addition, multi-point trimming is required due to process variation. In a
reference oscillator [7], a piecewise-linear curvature correction technique is proposed,
but it relies on a predefined lookup table (LUT) that stores internal parameters obtained
by chip-by-chip multi-point trimming. In this paper, we propose a sub-ranging current
reference implemented in a 0.18μm CMOS that achieves an average TC of 11.4ppm/°C
from -20°C to 125°C over five different process corners, with seamless transition
between sub-ranges, and without requiring any LUT or chip-by-chip trimming.
The concept of the proposed sub-ranging current reference is shown in Fig. 3.1.1, where
the temperature range is divided into two sub-ranges. In each sub-range, one of two
reference currents, both of which are designed to remove the first-order TC in their
respective sub-ranges, is selected. Note that when the transition temperature TX is at the
midpoint of the temperature range, the effect of the second-order TC is minimized.
However, in a practical implementation, a couple of issues must be considered, especially
when trying to avoid trimming. First, there can be a discontinuity of current at the midtransition point TX due to process variation. This discontinuity can be avoided if the
transition occurs at the crossing of the two currents, but this will move the TX away from
the midpoint and degrade the TC. Second, even if we could achieve a seamless transition
at the midpoint, we must ensure that this is process-invariant. In order to achieve these
goals, we propose a current reference based on the concept shown in Fig. 3.1.1 (bottom),
where the IREF is determined by a weighted sum of the PTAT and CTAT voltages divided
by a weighted sum of two resistors. The reference current depends on the parameter α
which is configured for each sub-range (i.e., IREF(α1) when T<TX and IREF(α2) when T>TX).
Since both the numerator and the denominator have the same algebraic form with respect
to α, it can be derived that IREF becomes independent of α at a temperature where
VPTAT/VCTAT is equal to R1/R2. This implies that, at this particular temperature, IREF is the
same regardless of α. Therefore, by setting an appropriate R1/R2 and designing VPTAT/VCTAT
to be process insensitive, we can achieve a midpoint transition that is seamless and
insensitive to process variations. It is important to note that due to this property that TX
is independent of α, designers are given the freedom to choose any α that minimizes the
TC for each sub-range.
Based on this concept, a sub-ranging current reference is designed as shown in Fig.
3.1.2. It consists of three current branches where the first-second branch mimics a
typical PTAT current generator and the first-third branch is similar to a CTAT current
generator of a current-mode bandgap reference [6]. The difference is that the positive
input node of the error amplifier (VOP+) is from a voltage (V3) divided between V1 and V2
by k (i.e. V3 = k∙V1 + (1–k)∙V2, note: k = α/(1+α)). Therefore, the TC of the reference current
lies between that of the PTAT and CTAT current generators and we can choose an optimal
k to minimize TC for a given temperature range. Assuming R3 >> R1, R2, the output
current IREF can be expressed as
k ∙ ΔVBE + (1 − k) ∙ VBE
(1)
IREF (k) =
,0 ≤ k ≤ 1
k ∙ R1 + (1 − k) ∙ R2
where VBE=VBE1 and ΔVBE=VBE1–VBE2 which have CTAT and PTAT characteristics,
respectively. As explained earlier, at a particular temperature TX where ΔVBE/VBE=R1/R2 is
satisfied, IREF is a constant regardless of k and becomes IREF=ΔVBE/R1=VBE/R2. Since a
seamless transition is inherently achieved, we can set R1/R2 such that TX is at the
midpoint of the temperature range, and select appropriate k for each temperature range
by changing the internal division point of R3. Note that the k and TX are process
insensitive, since k is determined by the internal division ratio of R3, and TX is determined
by ΔVBE/VBE and R1/R2, all of which are process insensitive [8].
54 • 2024 IEEE International Solid-State Circuits Conference
For seamless transition between the sub-ranges, an accurate 1b temperature sensor is
required for the transition between k1 and k2 at TX. Instead of designing an additional
temperature sensor, we utilize two temperature-dependent voltages that cross at TX,
which are V1 and V2. Since IREF is independent of k at TX, VOP+ is also independent of how
R3 is divided by k, which implies that V1=V2 at TX. In detail, V1 and V2 can be expressed
as V1=VBE2+IREF∙R1 and V2=IREF∙R2, respectively, and since IREF=ΔVBE/R1=VBE1/R2 at TX, V1
and V2 both become VBE at TX. Note that VBE2 typically has a more negative TC than IREF∙R1
or IREF∙R2 and thus, V1 has a more negative TC than V2. Therefore, just by comparing V1
and V2, it can be determined whether the current temperature is above or below TX, and
the proposed circuit can accordingly switch between k1 and k2 at TX.
The detailed schematic of the proposed current reference is shown in Fig. 3.1.3. Since
the channel-length modulation and mismatch of the current mirrors degrade the line and
load sensitivities and temperature stability of IREF, cascode mirrors are used with dynamic
element matching (DEM) at 16kHz. The error amplifier is chopped at 4kHz to avoid
nonlinear TC in the amplifier offset [8]. Note that the DEM and chopping also reduce 1/f
noise. The error amplifier is self-biased based on a beta-multiplier circuit, which is formed
by the bias generator and the amplifier’s common-mode equivalent circuit. To mitigate
the effect of the temperature-dependent current gain (β) of Q1 and Q2, RB is added at the
base of Q1 [9]. The block diagram of the k-selector, which compares V1 and V2 and selects
the appropriate value of k for each sub-range, is shown in Fig. 3.1.3 (bottom). A portion
of resistor R3 is designed as a 6-bit RDAC, which uses a folded resistor string array for
small area. For the comparator, large-size transistors are used to achieve a small offset.
The proposed sub-ranging current reference is implemented in a 0.18μm CMOS process.
It occupies 0.08mm2 as shown in Fig. 3.1.7 and it draws 43.5μA from a 1.8V supply. The
measured IREF is shown in Fig. 3.1.4 (top-left), where it is plotted for different values of
k. It can be seen that they all cross at TX, as expected. The best-case TC of the IREF with
the proposed curvature correction is 7.81ppm/°C, which is a 3.7× improvement over the
best case TC without curvature correction. Figure 3.1.4 (top-right) shows the
measurement results of V1, V2, and the output of the comparator (SELK), where it can be
seen that V1 and V2 cross at TX. Figure 3.1.4 (bottom) shows the measured line and load
sensitivities with samples from different process corners (TT, FF, SS, FS, SF). The
proposed current reference shows low and consistent sensitivities across all process
corners. The average line sensitivity is 365ppm/V in the supply range of 1.3 to 2.4V with
a 0.3V load voltage, and the average load sensitivity is 181ppm/V in the load range of 0
to 0.7V with a 1.8V supply voltage.
Figure 3.1.5 shows distributions of IREF and TC measured from 45 chips in five process
corners (TT: 25, FF/SS/SF/FS: 5 each). They are measured in a temperature range of -20
to 125°C, with a supply voltage of 1.8V and a load voltage of 0.3V. Note that all the chips
are tested with a fixed, same k1 and k2, which are determined based on a batch calibration.
With the proposed curvature correction technique, the current reference achieves an
average TC of 11.4ppm/°C without chip-by-chip calibration. To show the process
tolerance of TX, the measured results are normalized by IREF measured at 50°C (Fig. 3.1.5,
top-right). It can be seen that the locations of TX are process-insensitive even without
any trimming.
The performance of the proposed current reference is summarized and compared with
the state-of-the-art low-TC current references in Fig. 3.1.6. The proposed current
reference achieves a low TC over a wide temperature range, without requiring an LUT or
chip-by-chip calibration, and exhibits low line and load sensitivities, as well as low noise.
Figure 3.1.7 shows the chip micrograph.
Acknowledgement:
This work was supported in part by the NRF (No. NRF-2021R1A2B5B01002874) and in
part by the IITP (No. 2023-00262634), funded by the MSIT. The chip fabrication and
EDA tool were supported by IDEC, Korea.
References:
[1] J. Lee and S. Cho, “A 1.4-μW 24.9-ppm/°C Current Reference With ProcessInsensitive Temperature Compensation in 0.18-μm CMOS” IEEE JSSC, vol. 47, no. 10,
pp. 2527-2533, Oct. 2012.
[2] Y. Ji et al., “A 9.3nW All-in-One Bandgap Voltage and Current Reference Circuit”
ISSCC, pp. 100-101, 2017.
[3] M. Lefebvre et al., “A Family of Current References Based on 2T Voltage References:
Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs,”
IEEE TCAS-I, vol. 69, no. 8, pp. 3237-3250, Aug. 2022.
[4] Q. Dong et al., “A 1.02nW PMOS-Only, Trim-Free Current Reference with 282ppm/°C
from -40°C to 120°C and 1.6% within-Wafer Inaccuracy,” ESSCIRC, pp. 19-22, 2017.
[5] S. Danesh et al., “An Energy Measurement Frontend with Integrated Adaptive
Background Accuracy Monitoring of the Full System Including the Current and Voltage
Sensors,” IEEE JSSC, vol. 54, no. 12, pp. 3269-3280, Dec. 2019.
[6] C.-W. U et al., “An 1 V Supply, 740 nW, 8.7 ppm/°C Bandgap Voltage Reference With
Segmented Curvature Compensation,” IEEE TCAS-I, Early Access, DOI:
10.1109/TCSI.2023.3301736, 2023.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 1:30 PM
3
Figure 3.1.1: Concept of sub-ranging curvature correction for a current reference Figure 3.1.2: Simplified schematic of the proposed sub-ranging current reference
(top), and the proposed scheme for sub-ranging current reference (bottom).
and its operation.
Figure 3.1.3: Schematic of the proposed current reference (top), and block diagram Figure 3.1.4: Measured IREF with different k (top-left), V1, V2, and SELK (top-right),
and line and load sensitivity (bottom).
of k-selector, comparator and 6b folded RDAC (bottom).
Figure 3.1.5: Measurement of process and temperature variations across 45 chips
from 5 process corners: Measured IREF (top-left), IREF normalized at 50°C (topright), and histograms of the average IREF and TC (bottom).
Figure 3.1.6: Performance summary and comparison table.
DIGEST OF TECHNICAL PAPERS •
55
ISSCC 2024 PAPER CONTINUATIONS
Additional References:
[7] S. Park et al., “A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear TemperatureCompensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance,” IEEE JSSC,
vol. 57, no. 4, pp. 1175-1186, April 2022.
[8] B. Yousefzadeh et al., “A BJT-Based Temperature-to-Digital Converter with ±60 mK
(3σ) Inaccuracy from −55°C to +125°C in 0.16-μm CMOS,” IEEE JSSC, vol.52, no. 4,
pp. 1044-1052, April 2017.
[9] B. Wang et al., “Subranging BJT-Based CMOS Temperature Sensor With a ±0.45°C
Inaccuracy (3σ) From -50°C to 180°C and a Resolution-FoM of 7.2 pJ∙K2 at 150°C,”
IEEE JSSC, vol. 57, no. 12, 3693-3703, Dec. 2022.
Figure 3.1.7: Die micrograph.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.2
3.2 A 0.028mm2 32MHz RC Frequency Reference in 0.18μm CMOS
with ±900ppm Inaccuracy from -40°C to 125°C and ±1600ppm
Inaccuracy After Accelerated Aging
Sining Pan1, Yihang Cheng1, Guohua Wu1, Zhihua Wang1, Kofi A. A. Makinwa2,
Huaqiang Wu1
Tsinghua University, Beijing, China
2
Delft University of Technology, Delft, The Netherlands
1
RC-based frequency references can achieve medium inaccuracy (~1000ppm) with small
chip area [1-6], and so can potentially replace bulky crystal- or MEMS-based frequency
references in cost-sensitive IoT applications. However, due to the large and nonlinear
temperature dependence of on-chip resistors, achieving lower inaccuracy requires
complex temperature compensation schemes, thus increasing chip area [1-4]. A further
challenge is their long-term frequency drift. Recently, it has been shown that P-type
polysilicon (P-poly) resistors, which are widely used because of their low temperature
coefficients, are highly susceptible to aging [4,6]. Although the resulting drift
(~5000ppm) of a P-poly-based RC frequency reference can be mitigated by periodically
calibrating it against a duty-cycled reference oscillator based on more stable diffusion
or via-metal resistors [4], this comes at the expense of much larger chip area.
This paper describes a compact RC frequency reference based on N-type diffusion
(N-diff) resistors, which uses a BJT-based temperature compensation circuit to cancel
its first and second-order temperature coefficients (TC1~1500ppm/°C and
TC2~0.5ppm/°C2). It achieves low inaccuracy (±900ppm) from -40°C to 125°C, stateof-the-art inaccuracy after accelerated aging (±1600ppm), and low area (0.028mm2) in
a standard 0.18μm technology. Compared to via-metal resistors, which are also robust
to aging, diffusion resistors have a larger sheet resistance and thus occupy less area.
Furthermore, they do not suffer from electromigration, and so no duty-cycling or AC
biasing [4] is required to enhance their stability. The versatility of the proposed TC
compensation scheme is validated by implementing a version based on P-poly resistors.
However, this version exhibits more initial inaccuracy (+2000/-2500ppm), and even more
(-2600ppm/-8100ppm) after accelerated aging.
Figure 3.2.1 illustrates the working principle of the proposed RC frequency reference,
which is built around a frequency-locked-loop (FLL). As in [4,6], an N-diff resistor
(190kΩ) and a periodically reset capacitor (4.8pF) are driven by different current sources,
generating a reference voltage VR and a sampled charging voltage VC. Their difference is
integrated and used to control the VCO, whose output is then used to control the timing
of the capacitive branch via a clock-generation block. Since the difference between VR
and VC is driven to zero by the large DC loop gain, the output frequency of the VCO will
eventually lock to a frequency determined by the value of RC and the ratio of the currents
applied to the two branches.
The FLL’s temperature dependence is compensated by a bandgap-like circuit that
generates voltages that are proportional and complementary to absolute temperature
(VPTAT and VCTAT). These are then forced across two N-diff resistors to generate two
currents IPTAT and ICTAT, which are scaled and combined before being used to drive the
resistive and capacitive branches. Denoting KR/C,P/C as the equivalent scaling factors of
the resistive/capacitive PTAT/CTAT branches, respectively, the FLL will be locked to
a frequency fVCO ∝
As shown in Fig. 3.2.1, the denominator
contains the product of the linear TCs of RC and of the (KRP∙VPTAT+KRC∙VCTAT) term,
resulting in a 2nd-order component that enables the simultaneous compensation of TC1
and TC2 with the proper choice of the four current scaling factors.
Figure 3.2.2 shows a more detailed system block diagram, as well as the FLL’s timing
diagram. A PTAT reference circuit with a PNP area ratio of 1:5 is used to generate IPTAT
= VPTAT/RBP, as well as ICTAT = VCTAT/RBC, where RBC = 140kΩ = 9∙RBP. These currents are
then copied to the RC front-end via coarse/fine mirrors with the appropriate scaling
factors, which were determined by simulation. For stability, the nominal ratios (KRP/KCP
= 1:3, KRC/KCC = 1:1) are defined by an array of dynamically matched coarse mirrors.
These are combined with an array of fine mirrors, which can be batch trimmed to
compensate for TC spread. Since the N-diff resistors are all operated at DC, their parasitic
capacitances do not affect the FLL’s output frequency. Also, the substrate leakage current
of R0 (<1nA over PVT) is negligible compared to its biasing current (~4μA). As in [6], VC
is generated in three phases. First, the top plate of capacitor C0 and the corresponding
current source output are connected to GND during the discharge phase ΦDSCH. Then,
the current source is directed to C0 during the subsequent charging phase ΦCH, and the
voltage VC at the end of this phase is sampled. During the next integration phase ΦINT,
the difference between VR and the sampled VC is processed by a Gm-C integrator (gm =
1.5μS, C = 4pF) that drives the VCO, resulting in a nominal output frequency of 32MHz.
To suppress the frequency error introduced by timing delays in the phase generation
circuit, ΦCH, which determines the FLL’s output frequency, is made 2× longer than ΦDSCH
and ΦINT. For the same reason, an 8:1 clock divider is inserted between the VCO output
and the phase-generation circuit. The ratio of 8 is chosen as a trade-off between
56 • 2024 IEEE International Solid-State Circuits Conference
frequency error and system stability. To maximize energy-efficiency, all the amplifiers
are telescopic OTAs, whose 1/f noise and offset are mitigated by chopping (2MHz).
Chopping ripple is suppressed by a compact single-ended switched-capacitor notch filter
[6], while the charge injection of the switches is compensated by dummy devices. The
VCO is a current-starved differential ring oscillator controlled by a resistive degenerated
PMOS transistor.
To compensate for process and temperature variations, the FLL’s TC and nominal
frequency must be trimmed. In this work, its TC2 is trimmed by adjusting RBC (3-bit) in
the CTAT generation branch, while its TC1 is trimmed by adjusting the PTAT current
(5-bit) injected into the capacitive branch. As shown in Fig. 3.2.3 (top), by combining a
CMOS direction-control MSB switch and PMOS/NMOS LSB switches, TC1 can be
adjusted in LSB steps of ~2.1ppm/°C (~350ppm from -40°C to 125°C). The nominal
frequency spread over process (30%) and within a batch (<2%) is trimmed by a 4-bit
coarse MIM cap array and an 8-bit fine MOM cap array, respectively. The two types of
capacitors are stacked to reduce chip area. The trimming steps are shown in Fig. 3.2.3
(bottom). After a batch calibration that determines the TC2 code, the FLL is individually
trimmed by sweeping the TC1 code at 105°C and -25°C, and then choosing the code
that minimizes the output frequency difference, its nominal frequency is then trimmed
at -25°C. To improve the trimming nonlinearity and thus facilitate the determination of
the proper f0 code, two bridge capacitors (MIM cap, CBRG = 1pF) are used to scale the
effective LSB CDAC (CU2) from 2.9fF to 0.7fF, which helps to achieve a near-linear
trimming resolution of 150ppm (Fig. 3.2.3, top).
Figure 3.2.7 shows the chip micrograph of the fabricated prototype. Each chip contains
four identical frequency references based on N-diff resistors (TC1 ≈ 1500ppm/°C), as
well as four others based on P-poly resistors (TC1 ≈ -240ppm/°C). The N-diff version
occupies 0.028mm2 in a standard 0.18μm CMOS process, and consumes 73μA from a
1.8V supply (48μA analog and 25μA digital). Due to its larger sheet resistance, the
P-poly version is slightly smaller, but its current consumption is similar (77μA).
Frequency references from seven ceramic packaged chips (28 samples of each type)
were trimmed and characterized in a temperature-controlled oven. As shown in Fig. 3.2.4
(left), the peak inaccuracy of the N-diff version is 900ppm, which corresponds to a
residual TC 10.6ppm/°C from -40°C to 125°C (box method). Due to process spread and
the limited TC1 tuning range, only 14 samples of the P-poly version could be properly
trimmed, resulting in a peak inaccuracy of 2500ppm. Both versions exhibited hysteresis
and spread as the oven temperature was cycled between hot and cold. On average, the
hysteresis of the N-diff version (~1000ppm) is much larger than that of the P-poly
version, while its residual TC (10.6ppm/°C) and spread are much less. After one week of
accelerated aging at 150°C [6], the N-diff version exhibits much less average drift
(200ppm nominal frequency and 3.3ppm/°C TC) than the P-poly version (-5200ppm
nominal frequency and -7ppm/°C TC). Together with its initial inaccuracy, this translates
into a total long-term inaccuracy of ±1600ppm for the N-diff version. From 1.7V to 2V,
the average supply sensitivity of both versions is ~3000ppm/V (Fig. 3.2.4, right). The
measured output period jitter and Allan deviation are 18.7psrms and 18.8ppm, respectively
(Fig. 3.2.5 top/bottom-left). After resetting the gm output to VDD (the worst-case
scenario), the frequency reference settles in about 80μs, as shown in Fig. 3.2.5 (bottomright).
Figure 3.2.6 summarizes the performance of the proposed RC frequency reference and
compares it to the state-of-the-art. Despite being fabricated in a mature 0.18μm CMOS
process, the circuit occupies the least chip area among RC-frequency references with
sub-1000ppm inaccuracy. It also achieves good inaccuracy after accelerated aging,
similar to that of [4], by using N-diff rather than P-poly resistors to set its output
frequency.
Acknowledgement:
This work was supported by the National Key R&D Program of China (2019YFB2204800).
References:
[1] Ç. Gürleyük et al., “A 16 MHz CMOS RC Frequency Reference with ±90 ppm
Inaccuracy From -45 °C to 85 °C,” IEEE JSSC, vol. 57, no. 8, pp. 2429-2437, Aug. 2022.
[2] K. -S. Park et al., “A 1-μW/MHz RC Oscillator with Three-Point Trimmed 2.1-ppm/°C
and Single-Point Trimmed 8.7-ppm/°C Stability From -40 °C to 95 °C,” IEEE JSSC, vol.
58, no. 7, pp. 2064-2074, Dec. 2022.
[3] Y. Ji et al., “A Second-Order Temperature-Compensated On-Chip R-RC Oscillator
Achieving 7.93ppm/°C and 3.3pJ/Hz in -40°C to 125°C Temperature Range,” ISSCC, pp.
64-65, Feb. 2022.
[4] K. -S. Park et al., “A 1.4 μW/MHz 100MHz RC Oscillator with ± 1030ppm Inaccuracy
from −40°C to 85°C After Accelerated Aging for 500 Hours at 125°C,” ISSCC, pp. 62-64,
Feb. 2023.
[5] J. Wang et al., “A 12.77-MHz 31 ppm/°C On-Chip RC Relaxation Oscillator with Digital
Compensation Technique, “ IEEE TCAS-I, vol. 63, no. 11, pp. 1816-1824, Nov. 2016.
[6] X. An et al., “A 0.01 mm2 10MHz RC Frequency Reference with a 1-Point On-ChipTrimmed Inaccuracy of ±0.28% from −45°C to 125°C in 0.18μm CMOS,” ISSCC, pp.
60-62, Feb. 2023.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 1:55 PM
3
Figure 3.2.1: Circuit model and temperature compensation principle of the proposed
Figure 3.2.2: System block diagram and timing diagram.
RC frequency reference.
Figure 3.2.3: Trimming circuits for nominal frequency (top-left) and linear TC (top- Figure 3.2.4: Temperature (left) and supply (right) dependencies of N-diff (top) and
P-poly (bottom) frequency references.
right). Two-point calibration steps (bottom).
Figure 3.2.5: Jitter (top), Allan deviation (bottom-left), and start-up behaviour Figure 3.2.6: Performance summary and comparison with state-of-the-art compact
frequency references.
(bottom-right) of the proposed frequency reference.
DIGEST OF TECHNICAL PAPERS •
57
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.2.7: Die micrograph (left) and zoomed-in view (right).
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.3
3.3 A 0.5V 6.14µW Trimming-Free Single-XO Dual-Output
Frequency Reference with [5.1nJ, 120µs] XO Startup and
[8.1nJ, 200µs] Successive-Approximation-Based RTC
Calibration
Rui Luo1, Ka-Meng Lei1, Rui P. Martins1,2, Pui-In Mak1
University of Macau, Macau, China,
Instituto Superior Técnico/Universidade de Lisboa, Lisbon, Portugal
1
2
For miniature IoT nodes, it is desirable to develop a multi-output frequency reference
from one quartz crystal to favor footprint and cost reduction. There have been attempts
to utilize the MHz-range crystal oscillator (XO) to calibrate the integrated oscillator [1,2],
or to generate clocks for multiple purposes [3,4]. The clock system in [1] provides an
on-demand 76.8MHz clock with XO startup time (ts) reduction, and an always-on
32.768kHz real-time clock (RTC) using a machine-learning-based RC oscillator. Yet, it
involves heavy training and poses a high sleep-mode power (48.2μW). The XO-assisted
RTC in [2] exhibits a 0.26ppm/°C TC, but its counter-based calibration takes a long time
(10ms) and consumes high energy (567nJ). Also, there is no technique to accelerate the
XO startup.
We report a 0.5V trimming-free single-crystal dual-output (SXDO) frequency reference,
achieving energy-efficient and quick startup/calibration metrics: [XO: 5.1nJ, 120μs] and
[RTC: 8.1nJ, 200μs]. Specifically, the XO generates a 16MHz on-demand clock, and a
digital-controlled ring oscillator (DCO) serves as a 1MHz always-on RTC (Fig. 3.3.1).
Using the XO as a reference, the circuit periodically calibrates the DCO frequency (fDCO)
in a successive-approximation (SA) manner in <200μs while consuming 8.1nJ, with a
TC of 2.5ppm/°C. Under a 0.1s calibration interval (tCAL), the RTC consumes 6.14μW in
the sleep mode. No trimming is required after fabrication. Also, we reuse the RTC to
generate a 16MHz signal to kickstart the XO. The achieved ts of 120μs and startup energy
(ES) of 5.1nJ improve by 96× and 71.2×, respectively, compared to those without startup
aid.
The SXDO frequency reference embodies an XO core, frequency multiplier, SA-based
frequency calibration module (FCM), finite-state machine (FSM), and the DCO controlled
by the 14-bit frequency control words (FCW) to generate the RTC. The system operates
in two modes: active and sleep. In the active mode, the 16MHz XO generates the highprecision reference clock (fXO), while the DCO concurrently generates a 1MHz RTC clock
(fDCO). Therein, the FCM intermittently refines the fDCO towards fXO/16 (1MHz) in the SA
approach. Unlike [1,2] that rely on counting the difference in the number of cycles
between the XO and RO that induces a long calibration time (>4ms), our FCM
incorporates a 5-bit counter and a time-to-digital converter (TDC) to accomplish
frequency calibration within 80μs. In the sleep mode, except during calibration, the circuit
only leaves the DCO enabled to provide the RTC. Besides, the SXDO periodically calibrates
the DCO against the XO. Owing to the fast startup XO and SA-based method, the total
duration for calibration is 200μs, corresponding to a duty cycle of <0.2% (with a 0.1s
tCAL), rendering the energy dissipation of the calibration negligible.
Figure 3.3.2 details the operation of the FCM. The phase-error detector (PED) estimates
fDCO by comparing it with fXO in 3 different phases: process (ST0), coarse (ST1), and fine
(ST2) calibration phases. The circuit only enables ST0 once after powering up, where the
counter tallies the number of XO cycles in one DCO cycle to estimate fDCO and tunes fDCO
from ±50% up to one XO cycle (i.e., ±62.5ns) by tuning FCW[13:9]. Then, the calibration
enters ST1, in which the FCM compares fDCO with fXO/16 using a phase-frequency detector
(PFD) and TDC (resolution: 500ps) between two consecutive fDCO rising edges. The TDC
obtains two delays, Δt1 and Δt2. The digital comparator compares Δt1 and Δt2 and updates
FCW[8:2] and fDCO in a binary-search manner. The divider that generates fXO/16 is enabled
by fDCO to limit the delay between the rising edges of fDCO and fXO/16 within one XO cycle,
relaxing the TDC detection range.
After ST1, fDCO will theoretically reach <±500ppm of fXO/16 (defined by the TDC). To further
improve fDCO without excessively refining the TDC resolution, which otherwise increases
the calibration energy and area overhead, we compare fDCO and fXO/16 in multiple (N)
cycles. As such, we can improve the frequency resolution by N with the identical PFD
and TDC. After ST1, the calibration phase enters ST2 to refine the fDCO further. The FCM
continues to perform 2-bit calibration in the SA approach by comparing fDCO and fXO/16
in 4 DCO cycles and adjusts FCW[1:0] to improve the frequency accuracy to ±125ppm.
The DCO does not require reset in ST0-2 to ensure time-keeping accuracy.
The DCO consists of 5 source-degenerated inverters and 4 delay cells (Fig. 3.3.2, topright). It has an intrinsic frequency stability of 5% from −40 to 125°C. The RC elements
in the delay cell set fDCO. The resistors R1 (180kΩ) are standard poly resistors. The
FCW[13:9] for ST0 adjusts fDCO by directing 31 MOSCAP units that yield a 3.125%
58 • 2024 IEEE International Solid-State Circuits Conference
resolution and ±50% tuning range. Similarly, FCW[8:2] for ST1 drives 127 MOSCAP units
that achieve a 500ppm resolution and ±3.2% tuning range. Finally, FCW[1:0] steers a
unit MOSCAP to attain a 125-ppm resolution for ST2. The FCW[13:2] are common for all
4 delay cells, while FCW[1:0] master the unit MOSCAPs in 4 delay cells in a unary way.
Due to the digital-intensive nature of the PED, the leakage of its digital cells dominates
the system’s power in the sleep mode. To mitigate this problem, we power-gate the PED
through a high-VT PMOS (MP) to reduce the leakage. When ENCAL=VDD, the negativevoltage generator (NVG), based on fDCO-clocked charge pump circuits, outputs a negative
voltage (−0.3V) to drive MP’s gate and ensure a low on-resistance. When ENCAL=0 and
PED is idle, the NVG outputs VDD to shut MP off. As such, the leakage of the PED reduces
from 20 to 1μA at 27°C. As the NVG does not drive a resistive load and is clocked by
fDCO, its power budget (227nW at 27°C) is negligible to the overall power consumption.
In the sleep mode, the XO is intermittently enabled to provide a timing reference for the
FCM. Yet, the slow XO startup limits the energy efficiency and available tCAL. The work in
[1] employs an auxiliary oscillator to excite the crystal, which increases the hardware
and power overhead. As fDCO has been calibrated within ±500ppm of fXO/16, we can
employ a frequency multiplier to multiply fDCO by 16 and inject the signal into the crystal
(Fig. 3.3.3). Prior to entering active mode or calibration, the FSM enables the delaylocked loop (DLL), which generates 16 phases of 1MHz clocks (Φ0-15) with a lock time
of 50μs. Then, the edge combiner (EC), consisting of a delay cell (nominal тd: 31.3ns),
4-bit counter, and a 16-to-1 multiplexer, selects one of Φ0-15 according to the counter
output (S[3:0]) to synthesize a pulse train with a period of 62.5ns. The delay cell defines
the duty cycle of the 16MHz pulse by delaying the transition from the multiplexer to the
counter. The duty cycle of the injection pulse varies between 46.2% and 54% amid
temperature (−40 to 85°C) variations, inducing ±3.1% variation on the crystal’s motional
current (iM).
The SXDO system prototyped in 65nm CMOS process occupies 0.057mm2 (Fig. 3.3.7).
The free-running DCO poses a TC of 280ppm/°C (Fig. 3.3.4, top-left). With the calibration,
the TC improves to 2.5ppm/°C. From 4 dies, the ΔfDCO varies <±303ppm and <±300ppm
over VDD (0.48 to 0.60V) and temperature (−40 to 125°C) variations (Fig. 3.3.4, bottom).
From 1,000 individual calibrations, 3% show Δf>500ppm after calibration (Fig. 3.3.4,
top-right), attributable to the incorrect comparison originating from the DCO’s jitter
(363ps). Each calibration spends 8.1nJ. For a 0.1s tCAL, the power in the sleep mode is
6.14μW.
During the XO startup, the system enables the DLL for 100μs to synthesize the 16MHz
signal and wait for it to settle (Fig. 3.3.5). Then, the circuit injects it into the crystal in
the final 30μs. Overall, the fXO reaches the steady state (Δf<±20ppm) in 120μs and
consumes 5.1nJ, being 96× and 71.2× lower compared to those without startup aid. The
ts is robust to temperature and voltage variations (<±2.1% and <±2.5%). In the steady
state, the XO consumes 16.7μW, with a phase noise of −135.3dBc/Hz at 1kHz offset.
This work shows two improvements compared to the prior art (Fig. 3.3.6): 1)
intermittently calibrating the RO against XO in 200μs with 8.1nJ to deliver an always-on
RTC, being >667× and >70× lower than those of similar SXDO systems [1,2], benefitting
from the fast startup XO and SA-based method; 2) exploiting the frequency multiplier to
reuse the high-precision RTC signal for XO fast startup, resulting in a state-of-the-art ES
of 5.1nJ [5]. Further, the SXDO system eliminates manual trimming after fabrication,
rendering it a low-cost and autonomous clock solution for widely disseminated IoT
nodes.
Acknowledgment:
The work is funded by The Macau Science and Technology Development Fund [SKLAMSV(UM)-2023-2025, 0071/2020/A2, and 0149/2022/A3] and the University of Macau
(File no.: MYRG2022-00034-IME). Corresponding author: Ka-Meng Lei.
References:
[1] J. Jung et al., “A Single-Crystal-Oscillator-Based Clock-Management IC with 18×
Start-Up time reduction and 0.68ppm/°C Duty-Cycled Machine-Learning-Based RCO
Calibration,” ISSCC, pp. 58-59, Feb. 2022.
[2] C.-Y. Lin et al., “A ±20-ppm -50°C-105°C 1-μA 32.768-kHz Clock Generator With A
System-HFXO-Assisted Background Calibration,” IEEE A-SSCC, pp. 1-3, Nov. 2021.
[3] L. Lin et al., “A sub-0.5V Crystal Oscillator-Timer (XO-Timer) Combining 16MHz
Reference and 32kHz Sleep Timer with a Single Crystal for Energy-Harvesting Radios in
28nm CMOS,” IEEE A-SSCC, pp. 1-3, Nov. 2022.
[4] D. Griffith et al., “A 37μW Dual-Mode Crystal Oscillator for Single-Crystal Radios,”
ISSCC, pp. 104-105, Feb. 2015.
[5] H. Li et al., “A 12/13.56MHz Crystal Oscillator with Binary-Search-Assisted Two-Step
Injection Achieving 5.0nJ Startup Energy and 45.8μs Startup Time,” ISSCC, pp. 64-65,
Feb. 2023.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 2:20 PM
3
Figure 3.3.1: Architecture of the proposed SXDO system. It delivers an on-demand
16MHz clock signal for high-resolution applications, and an always-on 1MHz RTC for Figure 3.3.2: The block diagram of the SA-based FCM with the timing diagram of key
signals and the flow of the calibration.
synchronization.
Figure 3.3.3: Schematic of the frequency multiplier for injecting energy to the crystal Figure 3.3.4: Measured fDCO against temperature with and without calibration
and the associated timing diagram. The frequency multiplier allows synthesizing a (top-left), distribution of fDCO in 1,000 runs (top-right), and fDCO against voltage and
temperature variations from 4 samples (bottom).
16MHz signal based on the 1MHz RTC for XO fast startup.
Figure 3.3.5: Measured XO startup sequence (top-left), transient fXO of 16 startups
from 4 different chips (bottom-left), and the startup time of the XOs (ΔfXO<±20ppm)
from 4 samples amid voltage and temperature variations (right).
Figure 3.3.6: Comparison with the state-of-the-art SXDO frequency references.
DIGEST OF TECHNICAL PAPERS •
59
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.3.7: Die micrograph (left), breakdown of power in the sleep mode
(top-right), and breakdown of the calibration energy, excluding that from the DCO
(bottom-right).
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.4
3.4 A 14b 98Hz-to-5.9kHz 1.7-to-50.8μW BW/Power Scalable
Sensor Interface with a Dynamic Bandgap Reference and an
Untrimmed Gain Error of ±0.26% from -40°C to 125°C
Zhong Tang*1, Yuyan Liu*1, Pengpeng Chen1, Haining Wang1, Xiaopeng Yu2,
Kofi A. A. Makinwa3, Nick Nianxiong Tan1
Vango Technologies, Hangzhou, China
Zhejiang University, Hangzhou, China
3
Delft University of Technology, Delft, The Netherlands
*Equally Credited Authors (ECAS)
1
2
To accommodate different use cases, the bandwidth (BW) and power dissipation of
sensor interfaces for IoT applications should be highly scalable. For example, Coulomb
counting requires precision current sensors with low BW and microwatt power for
extended battery life, while AC battery impedance measurements require sensors with
much higher BWs [1]. There is thus a need for precision ADCs that are BW/power
scalable. Although SAR ADCs can easily scale their BW and power by changing their
sampling frequency, they typically have a moderate resolution [2]. To achieve higher
resolution, BW/power-scalable Delta-Sigma ADCs can be used [3]. In both cases,
however, the ADC will typically be combined with an external band-gap reference (BGR)
(Fig. 3.4.1 top left), which, in turn, requires power-hungry reference buffers and/or large
decoupling capacitors to drive the ADC.
This work presents a BW/power-scalable sensor interface that consists of a fully dynamic
Delta-Sigma modulator (DSM) with an embedded BGR (Fig.3.4.1 top-right). It achieves
an SNDR of >84.5dB over a scalable BW from 98Hz to 5.9kHz with a dynamic power
ranging from 1.7μW to 50.8μW. Furthermore, by employing a time-domain temperaturecompensation scheme, it achieves an untrimmed gain error of ±0.26% from -40°C to
125°C.
Precision BGRs usually use BJTs biased by static-currents to generate PTAT and CTAT
voltages, which are then combined to generate a temperature-independent output. They
typically consume tens of microwatts of static power [4], thus limiting the power
scalability of the overall system. Although nanowatt BGRs have been reported, they
typically have a poor temperature coefficient (TC >20ppm/°C) and large spread (>1%)
[2]. In this work, these issues are addressed by implementing a fully dynamic BGR based
on the capacitively biased ‘diode’ (CBD) technique [5]. As shown in Fig. 3.4.1 (bottom),
this involves pre-charging a capacitor CS to the supply voltage VDD and then discharging
it via a diode. After a short settling time (tens of ns), the voltage VD on CS will be fully
determined by the diode’s I/V characteristic, resulting in a supply-independent
logarithmic function of time. For a fixed discharging time t, the resulting VD will be CTAT.
A PTAT voltage ΔVD can then be generated by subtracting the outputs of two CBDs with
a fixed diode area ratio. By passively summing the voltages on the various sampling
capacitors a BGR can be made [5]. Although this approach only consumes dynamic
power, it has limited driving capacity, because its output voltage is stored on the
capacitors.
As shown in Fig. 3.4.2 (top), the PTAT and CTAT voltages generated by the CBD
technique can also be summed by the 1st integrator of a switched-capacitor (SC) DSM,
thus realizing a dynamic BGR and avoiding the need for additional reference buffers. The
proposed dynamic BGR consists of two sub-DACs, namely a PTAT and a CTAT DAC (Fig.
3.4.2, bottom). At the beginning of the sampling phase Φ1, the capacitors CREF1 in the
PTAT CDAC are pre-charged to VDD by closing S1,2. During the discharging phase ΦDC,
they are separately discharged through two diode-connected PNPs with a fixed area ratio
p by turning off S2 and turning on S3. At the end of ΦDC, ΔVBE (=VBE1-VBE2) is sampled by
turning off S1,3. As in [6], the bases of the PNPs are connected to a higher cut off voltage
VDD to turn them completely off. Compared to the use of a time ratio to define ΔVBE [5,6],
the use of an area ratio simplifies the timing generation circuit. In the CTAT CDAC, VBE is
generated in one branch, while the other branch samples ground, thus generating a
differential charge proportional to VBE. During the integration phase Φ2, S2 is turned on
again, connecting the left plates of the CREF1/2 together to VDD. Depending on the
modulator’s bitstream output, S5,6 ensure that differential charges proportional to VBE
and ΔVBE are transferred with the appropriate polarity to the integration capacitor CINT1.
To generate a BGR voltage, the TCs of the PTAT and CTAT CDACs must be accurately
balanced. This is achieved by appropriately setting the BJT’s emitter area ratio p and the
capacitor ratio m (=CREF1/CREF2). In this work, p is 15 and m is 8 (CREF1=8CREF2=6.4pF),
thus facilitating common-centroid layouts for good matching. The TC of the BGR can be
fine-tuned by adjusting the discharging time t, thereby tuning VBE (Fig.3.4.1, bottom
right). In this work, instead of using an external clock [5,6], an on-chip RC delay
generator is used to set t, thus decoupling it from the DSM’s (scalable) sampling
frequency. By tuning t (100ns to 350ns) in steps of 5ns, the TC of the BGR can be tuned
in steps of ~0.5ppm/°C.
60 • 2024 IEEE International Solid-State Circuits Conference
As shown in Fig. 3.4.3 (left), the on-chip delay circuit consists of a modified RC polyphase
filter and an inverter-based comparator. In contrast to a conventional polyphase filter,
the addition of two extra capacitors C2 (=C1=500fF) prevents its output from exceeding
supply rails, thus allowing the inverter-based comparator to be realized with core devices.
The comparator’s supply current peaks when its inputs VP and VN are close to VDD/2,
which reduces its switching delay (<5ns), but increases its power dissipation. To save
power, an extra pair of reset switches are used to pull VP/VN up/down to VDD/ground,
respectively, shortly after the comparator switches. Also, VP/VN are tied to ground/VDD
when the input clock (CLK1) is low, and the comparator is not used. This further reduces
the comparator’s dynamic power consumption and ensures that the initial voltages of
the next cycle, and thus the RC delay, are independent of the input clock frequency. The
p-poly resistors R (190kΩ) are 6-bit tunable to compensate for RC spread and to fine
tune the BGR’s TC.
As shown in Fig. 3.4.2, the sensor interface employs a 3rd-order 1-bit SC DSM with a
feed-forward topology. To achieve BW/power scalability, its integrators are based on
floating-inverter amplifiers (FIAs) [3]. Cascoded transistors are added to achieve a DC
gain >60dB over corners. Compared to conventional FIAs, switches are added to reset
each floating node of the amplifier to the common-mode voltage (VDD/2) during the
sampling phase Φ1, thus avoiding any signal-dependent error due to the stored charge
on the parasitic capacitances of the floating nodes (Fig. 3.4.3, bottom-right). To reduce
1/f noise and offset, the amplifier of the first integrator is chopped at fs/2 (Fig. 3.4.2 top).
Any residual offset is further suppressed by applying nested low-frequency chopping
(CHL) to the first and second integrators at fs/128 (not shown). To compensate for the
reduced maximum stable signal amplitude of a 3rd-order DSM, the input sampling
capacitor CIN (0.64pF) is set to 0.8× of CREF2. Bootstrapped switches are employed for
the input signal sampling, thus achieving a rail-to-rail input range while maintaining good
linearity.
Implemented in a 0.13μm CMOS process, the sensor interface occupies an area of
0.2mm2 (Fig. 3.4.7). From a 1.2V supply, it realizes an equivalent BGR voltage (~1.22V)
and can tolerate a maximum input voltage of 1.5V. For flexibility, the sinc3 decimation
filter was implemented off chip. Figure 3.4.4 (top) shows the measured output spectra
when the DSM operates at fs=1MHz. Chopping significantly suppresses its in-band 1/f
noise and offset. Measurements on 10 samples show that the latter is reduced from
25mV to 100μV. With a 500Hz 1.2V-Vp input sinusoid signal and an oversampling ratio
(OSR) of 128, the DSM achieves 85.0dB SNDR and 105.8dB SFDR in a 3.9kHz BW. As
shown in Fig. 3.4.4 (bottom), the modulator achieves a DR of 87.1dB. Operating at
fs=1MHz, it consumes 35.8μW (including the BGR), which corresponds to a Schreier
FoMSNDR/DR of 165.3dB/167.5dB.
To verify their temperature dependency, 10 samples from one batch were measured from
-40 to 125°C. The RC trimming code was obtained by batch calibration, and was the
same for all samples. With a fixed 1V DC input, the interface achieves a gain error of
±0.26% from -40°C to 125°C using the box method (Fig. 3.4.5, top-left). Translated into
an equivalent BGR voltage, the untrimmed TC of 10 samples varies from 16ppm/°C to
29ppm/°C. With a supply ranging from 1.1V to 1.4V and a fixed 500Hz input, the interface
consistently achieves 14-bit linearity (SNDR > 84.5dB) (Fig. 3.4.5, top-right). Thanks to
the stable BGR, the gain variation is less than ±0.1% from 1.1V to 1.4V. Figure 3.4.5
shows the power dissipation (bottom left), SNDR, and gain variation (bottom right) as
the sampling frequency fs varies from 25kHz to 1.5MHz. As shown, the power
consumption of the interface (and the BGR) can be scaled from 1.7μW to 50.8μW without
degrading its accuracy. Thanks to the RC delay generator, the measured gain variation
is less than ±0.01% as fs changes by 60×.
Figure 3.4.6 summarizes the performance of this work and compares it to state-of-theart sensor-interfaces/ADCs with a similar BW. Compared to [1], this work achieves 60×
BW/power scalability and 7.5dB better FoMDR. Compared to a SAR ADC that includes a
BGR [2], it achieves >10× better accuracy and does not require external decoupling
capacitors. As a result, the proposed fully dynamic precision ADC (SNDR>84.5dB) with
an embedded BGR is well suited for use in low power and precision sensor interfaces.
References:
[1] Z. Tang et.al, “A 40A Shunt-Based Current Sensor with ±0.2% Gain Error from −40°C
to 125°C and Self-Calibration,” ISSCC, pp. 348-349, 2023.
[2] M. Liu et.al, “A 106nW 10 b 80 kS/s SAR ADC with Duty-Cycled Reference Generation
in 65 nm CMOS,” IEEE JSSC, vol. 51, no. 10, pp. 2435-2445, Oct. 2016.
[3] M. Zhao et al., “A 4-μW Bandwidth/Power Scalable Delta–Sigma Modulator Based
on Swing-Enhanced Floating Inverter Amplifiers,” IEEE JSSC, vol. 57, no. 3, pp. 709718, March 2022.
[4] J. -H. Boo et al., “A Single-Trim Switched Capacitor CMOS Bandgap Reference with
a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications,” IEEE JSSC,
vol. 56, no. 4, pp. 1197-1206, April 2021.
[5] M. Eberlein et al, “A 40nW, Sub-IV Truly ‘Digital’ Reverse Bandgap Reference Using
Bulk-Diodes in 16nm FinFET,” A-SSCC, Tainan, Taiwan, pp. 99-102, 2018.
[6] Z. Tang et al, “A Sub-1V 810nW Capacitively-Biased BJT-Based Temperature Sensor
with an Inaccuracy of ±0.15°C (3σ) from −55°C to 125°C,” ISSCC, pp. 22-23, 2023.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 2:45 PM
3
Figure 3.4.1: Conventional ADC with a static band-gap VREF and buffer (top-left); ADC
with an embedded dynamic VREF (top-right); capacitively-biased diode operation Figure 3.4.2: Circuit diagram of the 3rd-order 1-bit DSM with an embedded dynamic
BGR and its timing diagram.
principle (bottom).
Figure 3.4.3: On-chip RC-delay generator (left); diagram of the floating inverter Figure 3.4.4: FFTs of the bitstream output (Fin=500Hz, Vp=1.2V, top); measured
dynamic range plot (bottom).
amplifier with internal nodes reset (right).
Figure 3.4.5: Measured BGR over temperatures with a fixed 1-V DC input (10
samples, top-left); measured power consumption at different sampling frequencies
(bottom-left); measured SNDR and gain variations at different supplies (top-right)
Figure 3.4.6: Performance summary and comparison with the state of the art.
and sampling frequencies (bottom-right).
DIGEST OF TECHNICAL PAPERS •
61
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.4.7: Die micrograph.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.5
3.5 A 4mW 45pT/√Hz Magnetoimpedance-Based ΔΣ
Magnetometer with Background Gain Calibration
and Short-Time CDS Techniques
Ippei Akita1, Shunichi Tatematsu2
AIST, Tsukuba, Japan
Aichi Steel, Tokai, Japan
1
2
Low-noise, low-power digital-output magnetometers are essential for various
applications, including security-gate systems, non-destructive inspections, and
geomagnetic and biomagnetic measurement systems. To ensure accurate
measurements, it is crucial to maintain the robustness of the conversion gain from the
input magnetic field to the digital-output signal. This paper presents a 3.96mW ΔΣ
magnetometer with an input-referred noise of 45pT/√Hz. Gain robustness is realized via
a proposed background gain calibration and low-power CDS techniques. An FoM for the
proposed magnetometer is 1.25fW/Hz, setting a new benchmark for energy efficiency
among state-of-the-art designs with digital output, while maintaining low noise
characteristics.
Figure 3.5.1 shows the overall block diagram of the proposed magnetoimpedance (MI)based ΔΣ magnetometer. The sensor head is based on an MI element, which is composed
of an amorphous wire and a single coil. Magnetic-to-electric transducing, from Bin to
Vin,s, is realized by applying a rapid transient current pulse MIE to the wire and detecting
the corresponding induced voltage Vin. The peak voltage of Vin is proportional to the
strength of Bin [1]. This peak voltage is sampled by a clock SMPL with appropriate delay
timing from the rising edge of the MIE, resulting in the sampled voltage Vin,s. The
sampling delay of SMPL is controlled by DLL and MUX, and is adjusted to match the
peak of Vin through the digital code DSMPL [2]. The magnetometer’s architecture is based
on a 5th-order ΔΣ modulator, where the MI element is a part of the loop: the front-end
subtraction for negative feedback occurs in the magnetic field. A magnetic flux density
Bfb for negative feedback is generated in the direction opposite to Bin by the coil in the
MI element, using the feedback current Ifb from the resistor-based DAC (RDAC). This
allows the coil to serve dual purposes: peak sampling and magnetic-field generation for
negative feedback, thereby enabling a more compact design. The RDAC is composed of
12 unary cells, and it outputs a 12-step current Ifb through a 12-tap shift register driven
by a 1b digital output Dout, which corresponds to an FIR feedback DAC scheme in ΔΣ
modulators to reduce the voltage swing of Vin. Two main technical advancements
characterize the magnetometer design: background gain calibration for stable feedback
current Ifb and short-time CDS (ST-CDS) for low-power operation. The former is achieved
through a local feedback loop around the RDAC, while the latter is implemented at the
peak sampler using a modified clocking scheme, as will be described later.
Figure 3.5.2 details the circuitry and timing diagram of the proposed background gain
calibration. Since the magnetometer takes a fully differential configuration, RDAC is
implemented at both terminals of the coil. The RDAC consists of 12 cells, with each cell
containing a unit resistor RU and switches driven by the shift register output Do. The
resistance of RU can be digitally programmed using a digital code Dctrl. The feedback
current Ifb must be accurate to ensure robustness in the conversion gain from Bin to Dout.
This is because the gain is determined by a cascaded total conversion coefficient from
Dout to Bfb via Ifb in the feedback path. As a current-output DAC for generating Ifb, the
RDAC architecture offers a lower-noise implementation than a current-steering
architecture because of the challenges involved in achieving a current source with low
flicker and thermal noise in a current-steering DAC. However, the accuracy of Ifb
generated by the RDAC can be significantly impacted by supply voltage VDD and the
temperature-dependent resistance of RU. To address these limitations, a gain calibration
loop is introduced. This ensures stable Ifb and robust gain, even with PVT variations. The
loop consists of a replica of 2 cells, a reference current source Iref, calibration logic, and
a hysteresis comparator serving as the detector, as shown in Fig. 3.5.2. The comparator
indirectly determines whether Iref is larger than Ifb, activating only when the number of
selected cells in the RDAC matches to that of the replica Do=2. For instance, consider
the case of a VDD drop, as illustrated in Fig. 3.5.2. Initially, there is a decrease in Ifb (1).
If Do=2, the comparator activates (2), resulting in a low-state comparator output Vcmp
because Ifb < Iref (3). The calibration logic receives this Vcmp state and decrements Dctrl to
decrease RU, effectively increasing Ifb. If the number of selected cells in RDAC does not
match the replica Do≠2, then Dctrl remains unchanged and Ifb also remains stable, given
that a valid comparison between Iref and Ifb cannot occur (3)’. This process repeats until
Iref is approximately equal to Ifb, and a limit cycle is avoided via the hysteresis in the
comparator. The proposed gain calibration can operate in the background as it is
independent of the type of processed signal. Additionally, the coil has a parasitic resistor
Rp, which also complicates the prediction of Ifb. The background gain calibration
technique can therefore adjust the total resistance between power rails to generate a
desired Ifb, accounting for unexpected resistors, making it useful for mitigating the effects
of PVT variations.
62 • 2024 IEEE International Solid-State Circuits Conference
Figure 3.5.3 shows the peak sampling front-end circuit that incorporates ST-CDS. This
feature allows for duty-cycling operation of the RDAC and suppresses the influence of
Rp. Theoretically, in the peak sampling process of the MI-based analog front-end circuit,
the Ifb only needs to flow in the coil during wire excitation by the MIE and peak sampling
by the SMPL. To facilitate this, path switches controlled by the EN can be introduced in
the feedback path. However, Rp compromises gain robustness due to an intrinsic
sensitivity variation of the MI element, even when a magnetic feedback configuration is
used. This comes from an unintended voltage drop RpIfb, which is suppressed by the
proposed ST-CDS. In the ST-CDS operation, double sampling occurs over a short
duration (when EN=H) to enhance the duty-cycling’s effectiveness. To accomplish this,
two sets of capacitors are employed: one set samples the drop voltage RpIfb and the other
set performs peak sampling. Given that the latter includes the signal component Vin,s and
unintended drop voltage, RpIfb is cancelled out via a cross-coupled connection, extracting
only Vin,s for transfer to subsequent stages, as shown in Fig. 3.5.3. Although conventional
CDS could utilize only a single set of capacitors [2], its effectiveness in power reduction
is limited when considering duty-cycling control, because the conventional CDS operation
relies on the opamp’s driving capabilities, thus restricting the on-duration of Ifb.
The prototype magnetometer was fabricated using a 0.18μm CMOS technology. The
areas of the analog front-end chip shown in Fig. 3.5.7 and the MI element are
1.4×1.51mm2 and 0.6×6mm2, respectively. The power consumption excluding IOs was
3.96mW at a supply voltage of 1.5V and the reference current source Iref is externally
applied in this prototype. The measured DC transfer curve is shown in Fig. 3.5.4 and the
linearity error is less than ±0.6% for ±80μT input range. With the full-scale output range
in the digital domain set to ±1.0, the Bin-to-Dout gain becomes 6.1kT-1 for a typical sample,
and spreads from 6.01 to 6.14kT-1 for 10 sample testing. Figure 3.5.4 also illustrates the
measured output noise PSD; the input-referred noise floor within a 10kHz bandwidth
was 45pT/√Hz. The SMPL sampling delay should be adjusted to capture the peak of the
induced voltage Vin in the MI element, and this delay can be controlled by DSMPL, where
no automatic search engine for DSMPL is integrated in this prototype. Any deviation from
the optimal sampling delay has a direct impact on the loop gain, and thus noise floor
[2], as indicated in Fig. 3.5.5 (top-left), which plots in-band noise floors for 10 samples
as a function of DSMPL. It is worth noting that sweeping the DSMPL effectively simulates
the intrinsic sensitivity variations in the MI element. Figure 3.5.5 (bottom-left) also shows
the effectiveness of the ST-CDS in reducing relative gain error. Even if the loop gain
changes due to alterations in sampling delay, ST-CDS can decrease the relative gain error
to less than 20% around the optimal DSMPL value. Moreover, gain error due to VDD
variation is successfully mitigated using the calibration, as shown in Fig. 3.5.5 (right).
Figure 3.5.6 provides a performance summary of the presented magnetometer and
compares it to state-of-the-art designs. Although some analog-output magnetometers
have achieved low-noise characteristics on the order of a few pT with an input range
exceeding 100μT [2], [3], digital-output versions have been developed with various
features: one offers lower noise but has narrower bandwidth (30Hz) and smaller input
range (2μT) [4], whereas others feature larger input ranges (>1mT) but relatively higher
noise floors (>1nT/√Hz) [5], [6]. Power consumption in these designs varies widely,
ranging from a few mW to over a hundred mW. Compared to these state-of-the-art
designs, the presented digital-output magnetometer accomplished lower noise and power
consumption while maintaining a moderate input range and DR. The FoM, as defined in
[6], is the lowest among digital-output magnetometers [4-6]. Additionally, the proposed
prototype chip incorporates background gain calibration and ST-CDS techniques to
enhance robustness.
References:
[1] K. Mohri et al., “Recent Advances of Amorphous Wire CMOS IC Magneto-Impedance
Sensors: Innovative High-Performance Micromagnetic Sensor Chip,” J. Sens., vol. 2015,
no. 717069, 2015.
[2] I. Akita et al., “An Automatic Loop Gain Enhancement Technique in
Magnetoimpedance-Based Magnetometer, IEEE JSSC, vol. 57, no. 12, pp. 3704-3715,
Dec. 2022.
[3] B. Yan et al., “Coil Optimization In A Fluxgate Magnetometer with Co 68.2 Fe 4.3 Si
12.5 B 15 Amorphous Wire Cores for Geomagnetic Station Observation,” IEEE Trans.
Instrum. Meas., vol. 70, pp. 1-7, 2021.
[4] W. Magnes et al., “A 92dB-DR 13mW ΔΣ Modulator for Spaceborn Fluxgate Sensors,”
ISSCC, pp. 388-389, Feb. 2007.
[5] M. Kashmiri et al., “A 200kS/s 13.5b Integrated-Fluxgate Differential-Magnetic-ToDigital Converter with an Oversampling Compensation Loop for Contactless Current
Sensing”, ISSCC, pp. 490-491, 2015.
[6] P. Garcha et al., “A Duty-Cycled Integrated-Fluxgate Magnetometer for Current
Sensing”, IEEE JSSC, vol. 57, no. 9, pp. 2741-2751, Sept. 2022.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 3:35 PM
3
Figure 3.5.1: Overall block diagram of magnetoimpedance (MI)-based ΔΣ
magnetometer with a background gain calibration scheme to improve gain robustness
over PVT variation and a short-time CDS (ST-CDS) technique to suppress an influence
of parasitic resistor Rp in MI element with low power consumption.
Figure 3.5.2: Detailed circuitry (left) and timing diagram (right) of the
proposed background gain calibration scheme: unit resistors RU in each cell of
RDAC is automatically updated by the calibration loop with monitoring Ifb and
digital signal Do
Figure 3.5.3: Peak sampling front-end circuit combining ST-CDS for realizing duty- Figure 3.5.4: Measured DC characteristic and its non-linearity (left) and output noise
PSD (right).
cycling operation in RDAC and suppressing Rp-related influence.
Figure 3.5.5: Measured noise floor (top-left) and relative gain errors w/ and w/o CDS
(bottom-left) as a function of the MI sampling delay controlled through DSMPL, and
gain errors (top-right) w/ and w/o the background gain calibration for VDD variations
Figure 3.5.6: Performance summary and comparison with state of the art.
(top-right), where error reduction can be observed (bottom-right).
DIGEST OF TECHNICAL PAPERS •
63
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.5.7: Die micrograph.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.6
3.6 An Amplifier-Less CMOS Potentiostat IC Consuming 3.7nW
Power all over 129.5dB Dynamic Range for Electrochemical
Biosensing
Muhammad Abrar Akram1, Aida Aberra1, Soon-Jae Kweon2, Sohmyung Ha1,3
New York University Abu Dhabi, Abu Dhabi, United Arab Emirates
The Catholic University of Korea, Bucheon, Korea
3
New York University, New York, NY
1
2
Ultra-low-power potentiostats, which perform high-precision current measurements for
electrochemical biosensing, hold paramount importance in the development of healthmonitoring wearables, point-of-care (PoC), and implantable diagnostics. In this
application, the power budget is gravely limited (sub-μW), and the input current signal
varies from pA to μA range, which corresponds to a dynamic range (DR) of >120dB
[1,2]. These requirements become more stringent in some applications, such as singlemolecule biosensors, where the desired signal currents exist within the nA range amidst
the backdrop of background currents in the nA-to-μA range [1], and millimeter-sized
electrochemical sensors, where the power efficiency is crucial.
Many prior potentiostat ICs [2-6] are unable to achieve such a wide DR with a sub-μW
power budget. Conventional potentiostats [2,3] using a resistive-feedback
transimpedance amplifier (R-TIA) at the front-end stage and a separate analog-to-digital
converter (ADC) at the next stage offer straightforward circuit implementation, but at the
cost of high power consumption due to the TIA and large area overhead due to the explicit
ADC (Fig. 3.6.1 (top left)). When it measures a small current, the TIA needs a large
current consumption for low noise. When measuring a large current, the TIA also needs
to consume a large current to match the large input current. Furthermore, the DR of the
potentiostat is gravely limited either by the voltage headroom of the TIA or the total size
of the feedback resistor array, making it unsuitable for implantable diagnostics. As shown
in Fig. 3.6.1 (top right), a delta-sigma modulator (DSM) can be used in the potentiostat
structure to perform analog-to-digital conversion and widen the dynamic range. However,
its power consumption remains notably high because of the amplifier and high-precision
DAC. Alternatively, a current-mirror structure with a current-to-frequency (I-F) conversion
[4,6], shown in Fig. 3.6.1 (bottom left), eliminates the need for a TIA and directly digitizes
the sensor current IIN, achieving a good DR and noise performance. However, the I-F
conversion, which is typically based on a current-controlled oscillator, severely suffers
from non-linearity, which deteriorates the overall linearity of the potentiostat.
Furthermore, a wide DR of IIN requires a wide operation range of the I-F converter and
other circuits, increasing the total power consumption of the potentiostat. To address
all the aforementioned issues, this paper proposes an amplifier-less digitally controlled
potentiostat IC that achieves 129.5dB DR (from 80pA to 240μA) at less than 4nW power
overhead over the entire range. It includes two working electrodes (main (WEM) and
background (WEBG) electrodes) for the capability of differential sensing (Fig. 3.6.1
(bottom right)). The WEs and the counter electrode (CE) are connected to current
sources, which are digitally controlled by clocked comparators through feedback loops,
eliminating the need for a TIA and a separate control amplifier for CE, unlike [1,3,6]. The
digitally controlled feedback loops regulate the electrode potentials (VWE, VWEBG, and VCE)
according to the reference voltages VREF and VREF,RE, while supplying IIN and IINBG. This
digital control with voltage-current regulation offers precise current matching and high
linearity with a wide DR with no need for amplifiers, resulting in notably reduced power
consumption no matter the current to the sensor and thus making the proposed
architecture an energy-efficient solution for low-power electrochemical biosensing.
Figure 3.6.2 (left) shows the overall architecture of the proposed amplifier-less
potentiostat IC. It comprises dynamic-latch-based comparators, digital-loop filters
(DLFs), switch-driving buffers, and 10-bit current-steering DACs (IDACs). Instead of
amplifiers used in conventional potentiostats for VDIFF (VWE -VRE) and CE voltage (VCE)
maintenance, we employ only a comparator, a DLF, and an IDAC. By controlling the IDAC
based on the comparison results, it also measures the current simultaneously while
maintaining the voltage. The clocked comparator at the WE side senses the voltage
difference between VREF and VWE and sends the output to the DLF, which generates
DOUT[9:0]. The IDAC supplies a PMOS current IPM (= IIN). The DOUT [9:0] value corresponds
to the IIN value in digital. Once VWE reaches VREF, the loop enters a steady state, where
the LSB of DOUT continuously toggles (Fig. 3.6.2 (top right). To maintain VDIFF, which is
given as a requirement by the sensing application, VREF,RE is fed to the bottom comparator,
and VRE is then regulated by the feedback loop through another DLF and IDAC. It makes
the IDAC flow a current that matches with IIN for the case using a single WE and IIN + IINBG
for the case using both WEs for differential sensing. Once VRE reaches VREF,RE, this loop
also stabilizes. In this work, the PMOS-side IDAC sources IIN while the NMOS-side IDAC
sinks it, ensuring accurate IIN measurements. By changing the bias current of the IDACs,
the proposed structure can achieve a wide DR easily. Furthermore, the potentiostat
operates over a wide clock (FS) range (0.001MHz to 100MHz), and the overall power
64 • 2024 IEEE International Solid-State Circuits Conference
consumption is proportional to FS (Fig. 3.6.2 (bottom right). Thus, depending on the
sensor’s measurement time and power requirements, the proposed potentiostat can be
easily reconfigured by controlling FS.
Figure 3.6.3 shows circuit schematics of the dynamic-latch-based comparator, currentsteering DACs, and small-signal model of the potentiostat. The comparator is highly
power-efficient because of its zero-static power, and its input-referred offset is sufficiently
reduced by using precharge switches (P1−4). To further reduce the offset, programmable
arrays of small capacitors are attached to the X and Y nodes. The current-sourcing and
current-sinking DACs (Fig. 3.6.3 (right)) are optimized for fast switching speed and a
wide current range using binary-weighted transistor sizing. To achieve high resolution
at a small area, the LSB transistors of both IDACs are sized to have rON/8 (rON=onresistance) with serially connected eight transistors, making the MSB size 64×rON and
significantly reducing the silicon area. The small-signal model of this potentiostat (Fig.
3.6.3 (bottom left)) includes a comparator, an integrator modeling DLF because of its
accumulation behavior, a first-order plant with a zero-order-hold (ZOH), IDAC’s
equivalent gm, and the load. z−1 is added to represent the delay between the comparator
and the DLF due to their clock-synchronous operation. The root loci of the open-loop
transfer function given in Fig. 3.6.3 (bottom-right) intersects the unit circle at K = K1,
ensuring asymptotic stability when K is between 0 and K1.
This potentiostat IC was fabricated in a 0.18μm CMOS process and occupies only
0.266mm2 (Fig. 3.6.7) thanks to the proposed digital control architecture with no use of
amplifiers or bulky passive components. It operates at a wide VDD and FS ranges of 1V to
1.8V and 100Hz to 100MHz, respectively. At a nominal condition (VDD=1.2V, VREF =1.1V,
VREF,RE =0.6 V, and FS=1 kHz), the potentiostat maintains a constant power consumption
of 3.7nW across the entire current sensing range from 80pA to 240μA (129.5dB). Figure
3.6.4 (top) shows an oscilloscope capture of the transient waveforms of VWE and VRE. At
1kHz FS, it takes 10.5ms to reach the steady state while driving an IIN of 1μA. Figure 3.6.4
(bottom) shows the measured output of the potentiostat with different bias currents of
the IDACs over the input current. The potentiostat successfully detects IIN from 80pA to
240μA and converts it to digital outputs (DOUT). It results in an overall DR of 129.5dB.
The worst-case linearity of the proposed potentiostat at the peak biasing conditions is
0.998R2, as shown in Fig. 3.6.4 (bottom). These results demonstrate fast response, high
DR, and linearity of the proposed work. Figure 3.6.5 (top) shows the full-scale SNDR
results of the proposed potentiostat IC measured at various biasing currents with FS of
100kHz when the amplitude of input current sinusoidal waveform at 100Hz (FIN) is
changed. This work achieves a full-scale DR of 129.5dB while maintaining more than
23dB SNDR over the entire range. To validate the proposed work’s application capability
to electrochemical sensing, the potentiostat is tested with a commercial three-electrode
glucose-oxidase-based biosensor (AC1.GOD, BVT Technology, Czech Republic), which
has a platinum WE and silver RE. Figure 3.6.7 (bottom) shows the measurement setup.
The chronoamperometry (CA) measurements are performed at a cell potential VDIFF of
0.5V regulated from the proposed potentiostat circuit with 1-kHz FS. The biosensor is
immersed in solutions with various glucose concentrations. The measured results for
glucose concentration from 1mM (18mg/dL) to 5mM (90mg/dL) are shown in Fig. 3.6.5
(bottom left). Figure 3.6.5 (bottom right) shows measured results from the proposed
potentiostat when the glucose concentration is increased at an interval of two minutes.
With each addition of glucose, the proposed IC and sensor operate as expected while
the output rises and then stabilizes at a new value within approximately one minute. The
proposed work is compared with other state-of-the-art potentiostat ICs in Fig. 3.6.6.
Even with a very small area and a very minimal overhead power consumption of 3.72nW,
the proposed IC achieves a DR or 129.5dB. The proposed work eliminates the
requirements of amplifiers, explicit ADCs, and complex DSM controllers from the
potentiostat architecture while achieving simple implementation, lower power
consumption, and wider DR.
References:
[1] C.-L. Hsu et al., “A Current-Measurement Front-End with 160dB Dynamic Range and
7ppm INL,” ISSCC, pp. 326-327, Feb. 2018.
[2] K. A. Al Mamun et al., “A Glucose Biosensor Using CMOS Potentiostat and Vertically
Aligned Carbon Nanofibers,” IEEE TBioCAS, vol. 10, no. 4, pp. 807-816, Aug. 2016.
[3] Q. Lin et al., “A 22μW Peak Power Multimodal Electrochemical Sensor Interface IC
for Bioreactor Monitoring,” ISSCC, pp. 314-315, Feb. 2023.
[4] S.-Y. Lu et al., “A 19μW, 50 kS/s, 0.008-400 V/s Cyclic Voltammetry Readout
Interface with a Current Feedback Loop and On-Chip Pattern Generation,” IEEE TBioCAS,
vol. 15, no. 2, pp. 190-198, Apr. 2021.
[5] S. Yu et al., “A Reconfigurable Tri-Mode Frequency-Locked Loop Readout Circuit for
Biosensor Interfaces,” IEEE TBioCAS, vol. 17, no. 4, pp. 768-781, Aug. 2023.
[6] S.-Y. Lu et al, “A Wireless Multimodality System-on-a-Chip with Time-Based
Resolution Scaling Technique for Chronic Wound Monitoring,” ISSCC, pp. 282-283, Feb.
2021.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 4:00 PM
3
Figure 3.6.1: Prior potentiostats: resistive-feedback TIA (top left), continuous-time Figure 3.6.2: Proposed amplifier-less potentiostat block diagram with
DSM-based (top right), and I - F converter (bottom left); and the proposed amplifier- electrochemical sensor model (left); operating waveforms (top right); measurement
time and power tradeoff over the clock frequency (bottom right).
less digitally controlled potentiostat (bottom right).
Figure 3.6.4: Measured transient response waveforms of VWE and VRE (top); output
Figure 3.6.3: Circuit diagrams of dynamic-latch-based comparator (top left) and versus input current at different bias currents (bottom left); output linearity at
minimum (10pA) and maximum (5µA) bias currents (bottom right).
current-steering DACs (right); small-signal model (bottom left).
Figure 3.6.5: (top) SNDR versus input current when a sinusoidal input current at
100Hz is applied. (bottom) Glucose concentration measurement results of the IC with Figure 3.6.6: Performance summary and comparison with state-of-the-art
potentiostat ICs.
a glucose sensor.
DIGEST OF TECHNICAL PAPERS •
65
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.6.7: Die micrograph and measurement setup using an electrochemical
sensor in various glucose concentrations.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.7
3.7 A β-Compensated NPN-Based Temperature Sensor with ±0.1°C
(3σ) Inaccuracy from -55°C to 125°C and a 200fJ∙K2 Resolution
FoM
Nandor G. Toth, Kofi A. A. Makinwa
Delft University of Technology, Delft, The Netherlands
The two key performance metrics of BJT-based temperature sensors are their accuracy
and energy efficiency. Although NPN-based temperature sensors achieve the best energy
efficiency [1], they have not been able to combine this with the accuracy of their PNPbased counterparts [2,3,4]. This paper presents an NPN-based sensor that achieves both
state-of-the-art energy efficiency (200fJ∙K2 FoM) and inaccuracy (0.1°C (3σ) from -55°C
to 125°C). It does this by combining a low-noise current-mode front-end with a
β-compensation scheme, dynamic-error-correction techniques, and room temperature
(RT) calibration. Compared to sensors with high accuracy and energy efficiency [2,3,4,6],
the proposed sensor is 2× smaller as well as 2× more energy efficient.
A simplified block diagram of the proposed sensor is shown in Fig. 3.7.1 (top). Two
NPNs Q1 and Q2 with an emitter area ratio ‘r’ are biased at identical collector currents,
thus establishing a well-defined base-emitter voltage difference ΔVBE and generating a
PTAT current IPTAT in resistor R1. In contrast, IPTAT generation in PNP-based sensors
typically requires an opamp [2,4,7], whose noise and power dissipation lowers their
energy efficiency. Although switched-capacitor biasing obviates the need for an opamp
[3], it comes with a kT/C noise penalty. As in [2], a digital representation of temperature
is obtained by using a ΔΣM to balance a bitstream-modulated copy of IPTAT against a
CTAT current ICTAT. The latter is efficiently generated by re-using the modulator’s 1st
integrator to force a base-emitter voltage VBE across resistor R2.
Due to its finite current gain (β~20), however, the collector current of Q1 (IC1) is less than
IPTAT (Fig. 3.7.1, bottom left). Since β is non-PTAT and spreads, the PTAT DAC current
(IPTAT’) required by the ΔΣM must be generated by adding the missing base current (IB1)
[5]. In this work, this is done by mirroring the average base current (IB1 + IB2)/2 and
adding it to the mirrored collector current IC1. Since β depends on the NPN’s collectorcurrent density (Fig. 3.7.1, bottom right), however, a residual Δβ error remains, resulting
in a trade-off between sensing accuracy (smaller r) and resolution (larger r). Monte Carlo
simulations show that r = 7 is a good compromise, resulting in a Δβ-related error of
<0.1°C (3σ) from -55°C to 125°C.
Figure 3.7.2 shows a detailed block diagram of the sensor. Together with Ru = 130kΩ,
the NPNs generate IPTAT = 390nA at RT. To minimize the sensor’s power supply sensitivity,
their collector currents are provided by a cascoded PMOS current mirror, while their
collector voltages are regulated by two feedback loops, which set their voltages to the
VGS of a high-Vt NMOS (M1). The feedback loop (around A1) is stabilized by a Miller
capacitor Cm (800fF) and a nulling resistor Rn (450kΩ). Since A1 has relaxed
requirements, it is realized as a 5-transistor OTA drawing only 0.5∙IC1. The second loop
(around M1) incorporates a 2:1 PMOS current mirror, which copies (IB1 + IB2)/2 to the
ΔΣM.
The ΔΣM employs a 1-bit DAC that switches between 0 and IPTAT. Compared to the DAC
in [2], which switches between IPTAT and 4IPTAT, this reduces the input current of the 1st
integrator by 4×, thus enabling a similar reduction in its power consumption and the size
of its integration capacitor Cint (15pF). To minimize switching transients, IPTAT is switched
to a replica of Q2 when it is not connected to the ΔΣM. With R2 = 24∙R1, the bitstream
(BS) average μ varies from 0.06 to 0.71 from -55°C to 125°C and is a non-linear function
of temperature (Fig. 3.7.2). However, it is a linear function of X = VBE/ΔVBE, and so the
PTAT spread of VBE can be corrected by a digital offset trim, and a linear function of
temperature can be expressed as μlin = α/(α + X) where α is a constant [2].
To ensure that the PTAT spread of VBE is the dominant source of error, dynamic-errorcorrection techniques are used to mitigate other sources of error. As shown in Fig. 3.7.2,
the mismatch of the NPNs and the current mirrors is mitigated by dynamic element
matching (DEM). Furthermore, the current-mirror DEM switches are placed above the
cascodes to reduce switching transients [1], while clock-boosters are used to reduce
the RON of the NPN DEM switches. The offset of A2 is mitigated by chopping (at fs to
prevent quantization-noise folding) and thus adds negligible error (<5μV) to the copy of
VBE that it forces across R2.
Since μ is a function of R1/R2 (Fig. 3.7.2), the spread in this ratio is another source of
error. In [2], a resistor-ratio calibration technique is proposed in which this ratio is
digitized by reconfiguring the ΔΣM and performing two conversions. The result is then
used to trim μ in the digital domain. To achieve sufficient resolution and accuracy,
however, this required a long calibration time (0.8s) at a stable temperature. In this work,
the resistor ratio is directly digitized by using switch S2 to force ΔVBE across R2 (Fig.
3.7.2). As a result, μ = 1 - R1/R2, which is independent of temperature and thus enables
a much shorter calibration time (0.1s) without the need for temperature stabilization. In
66 • 2024 IEEE International Solid-State Circuits Conference
a similar manner, voltage calibration can be implemented by forcing an external reference
voltage VEXT across R2. As a result, μ becomes a linear function of VEXT/ΔVBE, from which
ΔVBE, and hence die temperature, can be accurately determined [2].
The ΔΣM employs a single-ended 2nd-order loop filter, which is sampled at fs = 80kHz.
Its 1st integrator is built around an opamp A2, which must have enough DC gain (> 80dB)
to ensure that VBE (and ΔVBE in resistor-ratio calibration mode) is accurately copied across
R2, and enough GBW (> 350kHz) to mitigate integrated errors due to DAC and DEM
switching transients. To meet these requirements, A2 is a 2-stage Miller-compensated
opamp with a PMOS-input folded-cascode 1st stage and a common-source 2nd stage. Its
bias current (2∙IC) is efficiently mirrored from the NPN front-end. The switched-capacitor
2nd integrator consumes 3.5× less power than the continuous-time 1st integrator.
The sensor’s resolution is determined by the noise of the NPNs (27%), the resistors
(47%), and the PMOS collector-current mirrors (25%). The latter is mitigated by using
long devices biased in strong inversion (gm/ID≈1). Since the DAC current IPTAT is generated
by the IC and IB current mirrors, their mismatch and 1/f noise are mitigated by bit-streamcontrolled (BSC) DEM. This prevents quantization-noise folding by rotating their unit
elements only when IPTAT is connected to the ΔΣM [2]. The mismatch and 1/f noise of
the 8 unit-NPNs are suppressed by barrel-shifting them slowly (at fs/1536), thus causing
negligible quantization-noise folding.
The sensor was implemented in 0.18μm CMOS and occupies 0.07mm2. Each die contains
two sensors, which facilitates the use of differential measurements to suppress ambient
temperature drift. Each sensor draws 2.5μA from a 1.4V supply. 20 samples (40 sensors)
packaged in ceramic DIL were characterized from -55°C to 125°C in a temperaturecontrolled oven. To further suppress ambient drift, the samples were mounted in good
thermal contact with a large aluminium block.
FFTs of the sensor’s bitstream output are shown in Fig. 3.7.3 (top). Without DEM, the
sensor’s resolution is limited to a few mK by the 1/f noise of the current mirrors and the
NPNs. These are both effectively suppressed by DEM, resulting in a resolution floor of a
few hundred μK for long conversion times. The tones due to NPN DEM are removed by
the notches of the off-chip sinc2 decimation filter. Each conversion then consists of at
least two full NPN DEM cycles, resulting in a minimum conversion time of 38.4ms
(2∙1536/80kHz). As shown in Fig. 3.7.3 (bottom), the sensor achieves 1.22mK resolution
in 38.4ms, resulting in a resolution FoM of 200fJ∙K2.
Figure 3.7.4 (top left) shows the temperature spread after linearization (α=12.1) and
batch calibration. This results in a residual non-linearity of ±0.02°C and an untrimmed
inaccuracy of 0.6°C (3σ). This improves to 0.2°C (3σ) after an RT PTAT trim (Fig. 3.7.5
bottom left), and to 0.1°C (3σ) after resistor-ratio calibration (Fig. 3.7.5 top right). The
low-cost combination of voltage- and resistor-ratio calibration results in an inaccuracy
of 0.25°C (3σ) (Fig. 3.7.5 bottom right), which agrees well with prior art [2,4].
Figure 3.7.5 (top left) shows the temperature spread after β-compensation is deactivated
by opening switch S1 (Fig. 3.7.2). Due to the large change (~10% at -55°C) in DAC
current, the modulator now clips at temperatures below –25°C. Linearizing μ (α=11) then
results in a much larger residual non-linearity of ±0.2°C with a similar untrimmed
inaccuracy of 0.6°C (3σ) (Fig. 3.7.5, top left). Due to the roughly CTAT contribution of β
spread, an RT PTAT trim only results in an inaccuracy of 0.5°C (3σ). Better results are
obtained with an RT offset trim, which achieves 0.35°C (3σ) (Fig. 3.7.5, top right). These
results demonstrate the need for β-compensation in high-accuracy NPN-based
temperature sensors.
The measured power supply sensitivity of 16 samples is 0.04°C/V from 1.4V to 2.2V
(Fig. 3.7.5, bottom left). Furthermore, their clock frequency sensitivity is only 0.7mK/kHz
from 50kHz to 100kHz (Fig. 3.7.5 bottom right), demonstrating the sensor’s insensitivity
to switching transients.
In Fig. 3.7.6, the sensor’s performance is benchmarked against state-of-the-art BJTbased temperature sensors. It occupies the lowest area (0.07mm2), while achieving both
state-of-the-art energy efficiency (FoM = 200fJ∙K2) and inaccuracy (0.1°C 3σ from -55°C
to 125°C).
References:
[1] S. H. Shalmany et al., “A 620μW BJT-Based Temperature-to-Digital Converter with
0.65mK Resolution and FoM of 190fJ·K2,” ISSCC, pp. 70-71, Feb. 2020.
[2] N. G. Toth et al., “A BJT-Based Temperature Sensor with ±0.1°C (3σ) Inaccuracy
from -55°C to 125°C and a 0.85pJ·K2 Resolution FoM Using Continuous-Time Readout,”
ISSCC, pp. 358-359, Feb. 2023.
[3] Z. Tang et al., “A Sub-1V 810nW Capacitively-Biased BJT-Based Temperature Sensor
with an Inaccuracy of ±0.15°C (3σ) from −55°C to 125°C,” ISSCC, pp. 22-23, Feb. 2023.
[4] B. Yousefzadeh et al., “A BJT-Based Temperature-to-Digital Converter With ±60mK
(3σ) Inaccuracy From −55°C to +125°C 0.16-μm CMOS,” IEEE JSSC, vol. 52, no. 4, pp.
1044-1052, April 2017.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 4:25 PM
3
Figure 3.7.1: Operating principle of the proposed sensor (top), current signals vs. Figure 3.7.2: Block diagram of the proposed sensor (bottom), bitstream average vs.
temperature (top right).
temperature (bottom left), JC-dependency of NPN current gain (bottom right).
Figure 3.7.4: Measured temperature error of 40 samples without trimming (top left),
Figure 3.7.3: Bitstream FFTs for different types of DEM (top), resolution vs. with RT PTAT trim (top right), with RT PTAT trim and resistor-ratio calibration (bottom
left), with voltage- and resistor-ratio calibration (bottom right).
conversion time (bottom).
Figure 3.7.5: Temperature error of 40 samples without β-compensation and without
trimming (top left) and with RT offset trim (bottom left), power-supply and clock Figure 3.7.6: Performance summary and comparison with state-of-the-art BJT-based
frequency sensitivity at RT (right).
temperature sensors.
DIGEST OF TECHNICAL PAPERS •
67
ISSCC 2024 PAPER CONTINUATIONS
Additional References:
[5] F. Sebastiano et al., “A 1.2-V 10-μW NPN-Based Temperature Sensor in 65-nm
CMOS With an Inaccuracy of 0.2°C (3σ) From − 70°C to 125°C”, IEEE JSSC, vol. 45,
no. 12, pp. 2591-2601, Dec. 2010.
[6] R. K. Kumar et al., “An Energy-Efficient BJT-Based Temperature-to-Digital Converter
with ±0.13°C (3σ) Inaccuracy from -40 to 125°C,” IEEE ASSCC, pp. 107-108, Nov.
2019.
[7] B. Wang et al., “A BJT-Based CMOS Temperature Sensor Achieving an Inaccuracy
of ±0.45°C(3σ) from -50°C to 180°C and a Resolution-FoM of 7.2pJ·K2 at 150°C,”
ISSCC, pp. 72-73, Feb. 2022.
Figure 3.7.7: Die micrograph of the sensor.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.8
3.8 A 0.65V 900μm2 BEoL RC-Based Temperature Sensor with ±1°C
Inaccuracy from -25°C to 125°C
Bei-Shing Lien*, Szu Lin Liu*, Wei-Lin Lai, Yi-Chen Lu, Yung-Chow Peng,
Kenny Cheng-Hsiang Hsieh
TSMC, Hsinchu, Taiwan
*Equally Credited Authors (ECAs)
To maintain high-performance computing capacity and prevent chip overheating, it is
essential to minimize the gap between on-die thermal measurements and the actual
temperature at hotspots. This relies primarily on the inherent accuracy of the temperature
sensors and the distance to the heat sources. The latter factor is constrained by the
physical footprint of the sensor, which is generally determined by the complexity of the
sensor’s biasing and analog-to-digital conversion (ADC) schemes. In advanced FinFET
nodes, the scaling of the supply voltage (VDD) and the decreasing of passive device types
are other critical challenges for digital hot-spot sensors. Typical current-bias BJT sensors
still need VDD≥1V [4-6]. A sub-1V capacitive-bias bulk-diode sensor has been reported
in [9], but the extra keep-out zone between the bulk-diode and nearby PMOS logics may
be required due to different N-well biases. Poly-resistor-based sensors [2,3] can reach
comparable accuracy to that of BJT sensors, but these resistors will not be available in
advanced FinFET nodes.
Oscillator-based sensors can generate periodic signals with temperature-dependent
periods for thermal measurements. Their ADC architectures are simple and can achieve
a very compact footprint. For accurate temperature sensing, the oscillation source should
be less sensitive to logic process variations and supply change. With these considerations
in mind, this work presents a Back-End-of-Line (BEoL) RC-oscillator-based temperature
sensor. This sensor’s oscillating frequency is determined solely by the RC time constants
of the BEoL filter, making it insensitive to process-induced and supply-induced
transistor’s characteristic shifts and achieving <±1°C inaccuracy from core supply. Figure
3.8.1 shows the structure of the stacked BEoL RC-filter, where RPTAT is the proportionalto-absolute-temperature (PTAT) resistor, RTI is the near temperature-independent (TI)
resistor, and the shared Cs is a finger-type metal-oxide-metal (MoM) capacitor. To reduce
layout area, these R/C devices are stacked vertically. Figure 3.8.2 illustrates the
architecture of the RC-oscillator-based sensor that includes the BEoL RC-filter
aforementioned, a resistor-divider, a self-biased comparator, counter-based logic, and
switches. All the active function blocks are based on inverter-configurations and
transmission-gates and without using precision analog current-source and amplifiers.
When the system mode (Φ) is high or low, the charging/discharging on the BEoL RCfilter occur through RPTAT·CS and RTI·CS, respectively. The dynamic voltage on Cs (Vi,RC)
is compared to the reference voltage from the resistor-divider (Vi,REF). This comparison
results in the generation of the sensor’s output clock (CKTS), which can be derived from
either the PTAT-period clock (CKPTAT) or the TI-period clock (CKTI), depending on the
specific system mode. By counting the ratio of CKTS to a faster system clock (CKSYS), the
counter-based logic can convert the RC time constants (RPTAT·CS and RTI·CS) into digital
codes (DPTAT and DTI), respectively. Therefore, temperature information can be obtained
from DPTAT/DTI, which is proportional to (RPTAT·CS)/(RTI·CS), or simply RPTAT/RTI. The
temperature effect and the variation of the shared Cs can be cancelled out.
The operating concept of the RC oscillator is based on the charging and discharging of
Vi,RC between the two reference levels (i.e., Vi,REF=VREFH or Vi,REF=VREFL). While Vi,RC reaches
either one of the reference voltages, the comparator switches the charging and
discharging states from current one to the other. Typically, this continuous-time
comparison needs two amplifier-based comparators to compare Vi,RC with VREFH and VREFL,
respectively, since the occurrences of the comparison events is not determined by the
system clock, which significantly increases the overall footprint and power consumption.
Inspired by [10], we adopted a self-biased and inverter-configured comparator to address
these challenges (Fig. 3.8.3, top). The self-biasing principle is illustrated in the half-circuit
(Fig. 3.8.3, bottom-left), which comprises the inverter-configured transistors (MN,REF and
MP,REF) and their tail transistors (MN,tail and MP,tail). In this work, MN,REF and MP,REF are
biased by either VREFH=(3/5)·VDD or VREFL=(2/5)·VDD from the resistor-divider. This
selection alternates with the rising/falling edges of CKTS. Consequently, MN,tail and MP,tail
are in series with the small on-resistances of MN,REF and MP,REF (RON,N and RON,P), while
their gate-biases are provided by the inverter output (Vo,bias) through diode-connected
configurations. The continuous-time comparison can be depicted in the time-domain
waveform (Fig. 3.8.3, bottom-right). When Vi,RC reaches either VREFH or VREFL,
the inverter-configured comparator can switch both Vo,bias and Vi,REF states. The period
(TTS) of the sum of the charging and discharging phases can be written as:
68 • 2024 IEEE International Solid-State Circuits Conference
Since the difference between VREFH and VREFL is proportional to VDD and can be cancelled
out through the division, the period of CKTS is solely determined by the BEoL RC time
constants, making the period independent of logic process variations and supply change.
Chopping is applied to the comparator inputs and outputs to eliminate local mismatch
between the two inverters. The comparator can achieve continuous-time comparison
that is similar to what two amplifier-based comparators can provide but without the need
for current biasing. In contrast to other continuous-time-comparator-based sensors, the
total area is 0.072× that of [7], and it consumes 0.015× the power stated in [8].
This temperature sensor is fabricated in a 3nm FinFET CMOS process. The temperature
error is measured from -25°C to 125°C. After 1-point calibration at 25°C, the peak-topeak (p2p) inaccuracies in the output codes of 52 sensors are ±1°C (Fig. 3.8.4, left),
respectively, which corresponds to a 3σ inaccuracy of ±1.5°C. After 2-point calibration
at 25°C and 125°C, the p2p inaccuracies can be reduced within ±0.7°C (Fig. 3.8.4, right),
achieving 3σ inaccuracies of ±1°C. The supply sensitivity measured from 0.65V to 0.85V
is 0.6°C/V. The measurements are conducted through on-wafer testing using a probe
station, with temperature controlled by an on-station thermal chuck. The measured
inaccuracies therefore include non-uniform temperature distribution on the wafer. This
portion is potentially to be further improved after packaging.
Figure 3.8.5 (top) compares the supply voltage of this work with the state-of-the-art
FinFET temperature sensors. VDD≥1V is required for BJT sensors. Instead, the RC-type
[1], the bulk-diode [9] sensors, and this work can operate directly within the logic supply
domain. Figure 3.8.5 (bottom) further compares the sensor area of this work with that
of the FinFET temperature sensors. The sensor size of this work is 900μm² (Fig. 3.8.7),
which is around 0.36× to 0.075× the total area of BJT-based and bulk-diode-based
sensors used for local temperature monitoring [4,5,9], and is around 0.21× to 0.15× the
main sensor area of BJT- and RC-based remote sensors. The entire sensor size of this
work is only ~0.7× the area of the sensing cell area in [1]. Figure 3.8.6 compares the
performance of this work with the state-of-the-art temperature sensors of various types.
This sensor demonstrates significant benefits of an inaccuracy of ±1oC by a roomtemperature 1-point calibration, a compact footprint of 900μm², and sub-1V operation
for digital hot-spot thermal detection.
Acknowledgement:
The authors acknowledge C. H. Lee, Chester Kuo for assistance with the measurements
and express gratitude to J. J. Horng at this opportunity.
References:
[1] J. Park et al., “A 0.65V 1316μm2 Fully Synthesizable Digital Temperature Sensor Using
Wire Metal Achieving 0.16nJ·%2-Accuracy FoM in 5nm FinFET CMOS,” ISSCC, pp. 220221, Feb. 2022.
[2] A. Khashaba et al., “A 0.0088mm2 Resistor-Based Temperature Sensor Achieving
92fJ·K2 FoM in 65nm CMOS,” ISSCC, pp. 60-61, Feb. 2020.
[3] J. A. Angevare et al., “A Highly Digital 2210μm2 Resistor-Based Temperature Sensor
with a 1-Point Trimmed Inaccuracy of ±1.3˚C(3σ) from -55°C to 125°C in 65nm CMOS,”
ISSCC, pp. 76-77, Feb. 2021.
[4] M. C. Chuang et al., “A Temperature Sensor with a 3 Sigma Inaccuracy of ±2°C
Without Trimming from -50°C to 150°C in a 16nm FinFET Process,” ESSCIRC, pp. 271274, Sept. 2015.
[5] T. Oshita et al., “Compact BJT-Based Thermal Sensor for Processor Applications in
a 14nm tri-Gate Process,” IEEE JSSC, vol.50, no.3, pp. 799-908, Feb. 2015.
[6] C. Y. Liu et al., “An 8b Subthreshold Hybrid Thermal Sensor with ±1.07°C Inaccuracy
and Single-Element Remote-Sensing Technique in 22nm FinFET,” ISSCC, pp. 318-319,
Feb. 2018.
[7] J. J. Horng et al., “A 0.7V Resistive Sensor with Temperature/Voltage Detection
Function in 16nm FinFET Technologies,” IEEE Symp. VLSI Circuits, pp. 1-2, June 2014.
[8] J. Shor et al., “Ratiometric BJT-Based Thermal Sensor in 32nm and 22nm
Technologies,” ISSCC, pp. 210-211, Feb. 2012.
[9] M. Eberlein et al., “A No-Trim, Scaling-Friendly Thermal Sensor in 16nm FinFET Using
Bulk Diodes as Sensing Elements,” ISSCL, pp.63-66, Sept. 2019.
[10] S. Singh et al., “High-Speed and High-Resolution Self-Biased Differential Amplifier
Based Latch Comparator,” IJCA, vol.74, no.3, pp. 9-13, July 2013.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 4:50 PM
3
Figure 3.8.1: BEoL RC-filter (left, in colored region) used in oscillator-based
temperature sensor and its stacked structure (right). Cs=10pF, RPTAT=150kΩ and
RTI=100kΩ are formed by BEoL metal wires and high-resistivity-resistors,
Figure 3.8.2: RC oscillator-based temperature-sensor system diagram.
respectively.
Figure 3.8.3: Circuit implementation of the inverter-based comparator (top), half- Figure 3.8.4: Measured temperature errors after 1-point (left) and 2-point calibrations
(right).
circuit of self-biasing (bottom-left), time-domain waveform (bottom-right).
Figure 3.8.5: Supply range comparison for FinFET temperature sensors (top), and
Figure 3.8.6: Performance summary and comparison table.
the normalized layout area comparison (bottom).
DIGEST OF TECHNICAL PAPERS •
69
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.8.7: Die micrograph.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.9
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in
12-bit SAR ADC Using 3nm GAA’s 0.7V Thin-Gate-Oxide
Transistor
Sangheon Lee, Jinwoo Park, Junsang Park, Sangkyu Lee, Jungho Lee,
Youngjae Cho, Michael Choi, Jongshin Shin
Samsung Electronics, Hwaseong, Korea
Recently, as process refinement continues, the latest 3nm Gate-All-Around (GAA)
process utilizing the Multi-Bridge-Channel-FET (MBCFET) with nanosheet technology
enhances performance, power efficiency, and area (PPA) benefits by large effective
channel width and enhanced design flexibility compared to the previous FinFET
technology [1]. However, the 3nm GAA process provides only thin-gate oxide transistors
for a 0.7V low supply voltage and does not offer thick-gate oxide transistors for higher
supply voltages. Typically, a general-purpose analog-to-digital converter (ADC) needs
to sample inputs at higher levels, such as 1.2V, over the 0.7V low supply voltage (VDD)
in the 3nm GAA process. However, a conventional bootstrapped sampler can sample
inputs only up to VDD level, using 2×VDD internal node voltages. In the previous FinFET
processes with thick-gate oxide transistors for a 1.2V supply voltage, conventional
bootstrapped samplers are useful enough to sample 1.2V input without any reliability
and leakage issues. However, since the 3nm GAA process provides only thin-gate oxide
transistors for the 0.7V low supply voltage, this paper introduces an innovative tolerant
bootstrapped sampler architecture capable of sampling input levels up to 1.2V (1.7×VDD)
with maximum internal node voltages of 1.9V (2.7×VDD) without reliability and leakage
issues. Moreover, this paper also proposes a 0.7V 12-bit SAR ADC in a 3nm GAA
process, using this new tolerant bootstrapped sampler.
Figure 3.9.1 shows the conceptual scheme and circuit implementation of the conventional
bootstrapped sampler [2], which is useful to sample analog inputs equal to or lower than
the supply voltage level. Generally, since the VGS and VGD voltages of transistors should
not exceed the supply voltage (VDD) for reliability, the conventional bootstrap sampler
to sample VDD level input has additional M6 and M9 transistors to ensure that the VGD
voltage of M4 and M5 does not exceed VDD. However, if the conventional bootstrap
sampler in the 3nm GAA process with only thin-gate oxide transistors tries to sample
large inputs exceeding VDD, reliability and leakage problems occur because the VGD and
VGS of some transistors exceed VDD. As shown in Fig. 3.9.1, in the pre-charge (hold)
phase, if the VIN voltage is 1.2V, the gate voltages of MS and M3 are 0V. Therefore, MS
and M3 have VGD values exceeding 1.2V, which is greater than VDD, resulting in reliability
issues. In the sampling phase, if the VIN voltage is 1.2V, the voltage at the bottom plate
of the CB (node B) becomes 1.2V (1.7×VDD) and the voltage at the top plate of the CB
(node A) becomes 1.9V (2.7×VDD). Therefore, VGD voltages of the M1 and M2 also
exceed VDD. Additionally, since the VGS voltage of M4 becomes VDD, gate voltage of the
MS and M3 also becomes 2.7×VDD through M4 and the VGD voltage of the M6 also
exceeds VDD. Furthermore, if the VIN (1.2V) voltage is higher than VDD, the drain-body
diode of the M7 transistor becomes forward-biased. Consequently, leakage current
occurs through VIN through M3, M9, and M7. Therefore, in the 3nm GAA process, the
conventional bootstrap sampler cannot sample large inputs exceeding VDD without
reliability and leakage issues.
Figure 3.9.2 and Fig. 3.9.3 show a proposed tolerant bootstrapped sampler architecture
to sample large analog input over the 0.7V supply voltage, utilizing only thin-gate oxide
transistors. As shown in Fig. 3.9.2, in the pre-charge phase, the top plate of the CB
capacitor (node A) and gate of the dual-protection switches (M10, M11, M14, and M15)
become VDD. This ensures that even when the VIN voltage is 1.2V (1.7×VDD) over VDD,
the VGD voltage of M3 and MS does not exceed VDD. As shown in Fig. 3.9.3, in the
sampling phase, if the VIN voltage is 1.2V, the voltage at the bottom plate of the CB (node
B) becomes 1.2V (1.7×VDD) and the voltage at the top plate of the CB (node A) becomes
1.9V (2.7×VDD). To prevent the VGD voltage of M1 from exceeding VDD, the gate of M14
should be connected to VDD. Similarly, to ensure that the VGD voltage of M2 does not
exceed VDD, the gate of M15 should be connected to the bottom plate (node B) of the
CB. Adding a C1 capacitor to node C and node B ensures that when VIN is lower than
VDD, the node C maintains VDD. Conversely, when VIN exceeds VDD, the node C
approximately follows the VIN voltage. Therefore the node P is approximately VIN and the
VGD of M6 does not exceed VDD, because the node C is the gate of M16. The proposed
bootstrap sampler removes M7 in Fig. 3.9.1 to block the leakage current when the VIN
voltage exceeds VDD. Instead of M7, as shown in Fig. 3.9.3, it employs a new dynamic
floating level shifter to control the gate voltage of M4. Compared to the conventional
floating-level-shifter structure with the fixed level-shifting voltage [4], the new dynamic
floating level shifter changes the level-shifting voltage according to the VIN voltage level.
The dynamic floating level shifter connects the sources of M22 and M23 to the top plate
of the CB capacitor and connects the gate of M24 to the bottom plate of the CB capacitor.
In the sampling phase, the gate voltage of the M25 is VIN voltage and the VGD voltages of
70 • 2024 IEEE International Solid-State Circuits Conference
M24 and M26 do not exceed VDD, because the node D and node C follow VIN voltage.
Additionally, the proposed bootstrapped sampler prevents temporal reliability issues by
adding M17-M21 transistors and C2 capacitors. During the transition time between the
sampling and the pre-charge phases, the node B, O, and F can be discharged to 0V, while
the node E is connected to the node A (VDD+VIN). If the M17-M21 transistors do not
exist, VGD or VGS voltage of M4, M8, M9, M24, and M25 can become higher than VDD
with reliability risk. However, the M17-M21 transistors ensure that the transistors
connected to the node B, E, and O do not exceed VDD even during the temporarily
transition time. The C2 capacitor also protects the M24 and M25 transistors by
preventing the rapid discharge node F.
Figure 3.9.4 shows the 0.7V 12-bit SAR ADC in the 3nm GAA process. It consists of the
proposed bootstrapped input samplers, reference sampling switches, a capacitor DAC
array, a pre-amplifier, a comparator, and logic blocks. To sample and convert a 1.2V
input in the ADC, the capacitor DAC requires two-stacked single-protection reference
sampling switches, since the capacitor DAC array needs to sample either 0V or 1.2V
reference voltage. According to the comparison results between the ADC input and
reference voltages, the SAR logic sequentially generates Dn (n=1,2,…,12) signals. In the
reference sampling switches, the M1 transistor samples reference bottom voltage (0V)
using the Dn signal or the M3 transistor samples reference top voltage (1.2V) according
to the Dn,up signal, which is a level-up signal of Dn in the 0.5V~to~1.2V range, generated
by the limited level shifter. M2 with a VDD gate voltage and M4 with a VMID (0.5V) gate
voltage are protection transistors when the sampled output (Voutn) voltages are at 1.2V
and 0V levels, respectively. For stable 12-bit ADC performance, the ADC incorporates an
additional pre-amplifier. Even though the pre-amplifier consumes static current, the
signal gain and offset sampling scheme of the pre-amplifier can remove a complex offset
calibration scheme in the comparator. Moreover, a signal attenuation capacitor (CATT)
makes the pre-amplifier inputs less than VDD for reliability.
The 3nm GAA process ADC using the proposed sampler occupies 0.027mm2 as shown
in Fig. 3.9.7. The power consumption of the ADC is 0.34mW at 2MS/s based on 0.7V
supply and 1.2V reference top voltages. Figure 3.9.5 shows the measured differential
nonlinearity (DNL), integral nonlinearity (INL) and FFT spectrum of the ADC with a 1.2V
peak-to-peak and 0.1MHz analog input. The peak DNL and INL are 0.47LSB and 0.6LSB,
respectively. At 2MS/s, the measured SFDR and SNDR are 84dB and 63dB, respectively.
Figure 3.9.6 compares the proposed bootstrapped sampler with the previous ones
[2,3,5]. The conventional bootstrapped sampler with a voltage doubler [2] and the
alternating bootstrapped sampler without a voltage doubler [5] can only sample up to
the input signals at the same level as the supply voltage. The structure presented in [3]
can sample input signals over the supply voltage but relies on drain-extended MOS
(DEMOS) to endure high-voltage stress. The proposed tolerant bootstrapped sampler
can sample up to 1.2V level input over the 0.7V supply voltage by using only 3nm GAA
process thin-gate oxide transistors without reliability and leakage issues.
References:
[1] Taejoong Song et al., “3nm Gate-All-Around (GAA) Design-Technology CoOptimization (DTCO) for Succeeding PPA by Technology,” IEEE CICC, pp. 1-7, Apr. 2022.
[2] A. Abo et al., “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,”
IEEE JSSC, vol. 34, no. 5, pp. 599-606, May 1999.
[3] D. Aksin et al., “Switch Bootstrapping for Precise Sampling Beyond Supply Voltage,”
IEEE JSSC, vol. 41, no. 8, pp. 1938-1943, Aug. 2006.
[4] Y. Lu et al., “A Multiphase Switched-Capacitor DC-DC Converter Ring with Fast
Transient Response and Small Ripple,” IEEE JSSC, vol. 52, no. 2, pp. 579-591, Feb.
2017.
[5] C. Liu et al., “A 10-bit, 50-MS/s SAR ADC With a Monotonic Capacitor Switching
Procedure,” IEEE JSSC, vol. 45, no. 4, pp. 731-740, Apr. 2010.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 5:05 PM
3
Figure 3.9.1: Conventional bootstrapped sampler architecture.
Figure 3.9.2: Pre-charge (hold) phase operations of the proposed tolerant
bootstrapped sampler.
Figure 3.9.3: Sampling phase operations of the proposed tolerant bootstrapped
sampler.
Figure 3.9.4: Protection sampling switches and limited level shifter in SAR ADC.
Figure 3.9.5: Measured DNL, INL and FFT spectrum.
Figure 3.9.6: Comparison with the previous bootstrapped samplers.
DIGEST OF TECHNICAL PAPERS •
71
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.9.7: Die micrograph.
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / SESSION 3 / ANALOG TECHNIQUES / 3.10
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper
Instrumentation Amplifier with an Input-Boosted First Stage in
22nm/180nm CMOS
Xinhang Xu*1, Siyuan Ye*1, Yaohui Luan1, Jihang Gao1, Jie Li1, Jiajia Cui1,
Hao Zhang2, Ru Huang1, Linxiao Shen1, Le Ye1,3
Peking University, Beijing, China
Nano Core Chip Electronic Technology, Hangzhou, China
3
Advanced Institute of Information Technology of Peking University, Hangzhou, China
*Equally Credited Authors (ECAs)
1
2
The front-end amplifier typically determines the noise level of a sensor system. Therefore,
a highly power-efficient amplifier plays a critical role in Internet-of-Things (IoT)
applications with stringent power constraints and small input amplitude [1,2]. Due to
the physical limitation between transconductance and current consumption, there exists
a severe power-noise trade-off. Several approaches have been proposed to address this
issue. Inverter-stacking topologies in [3] concentrate on boosting the current efficiency
gm/Id, achieving high noise-efficiency factors (NEF) through current-reuse techniques.
However, the increased supply voltages result in worsened power-efficiency factors
(PEF). The tail-less inverter-stacking amplifier in [4] enables low supply voltage
operation, but the tail-less input stage makes it susceptible to common-mode and supply
fluctuations. The amplifier in [5] operates its input stage and following stages under 0.2V
and 0.8V separately. With a low-supply-voltage input stage, the power efficiency is
improved but at the cost of an extra DC-DC converter. The recently proposed passive
discrete-time amplifiers (DTA) achieve a PEF as low as 0.1 [6], but the sampling process
introduces aliasing problems, and using an anti-aliasing filter can bring about additional
noise and power-related issues.
This work presents a highly power-efficient capacitively-coupled chopper instrumentation
amplifier (CCIA). The proposed input-boosted inverter-based first stage increases the
gm/id with CMOS input pairs and doubles the signal-dependent voltage by coupling a pair
of differential inputs to the source and gate, effectively lowering the input-referred noise
(IRN) with the same supply current. A three-stage amplification scheme with a tailless
final stage is employed to achieve high loop gain and extensive output range. To address
leakage current issues under a wide temperature range, compensation circuits are also
adopted. Two prototype input-boosted CCIAs are implemented in 22nm and 180nm
CMOS processes. The former achieves 8.05uVrms IRN within 230Hz bandwidth (BW),
consuming 1.6nW, and the latter achieves 5.09uVrms IRN within 1.6kHz BW, consuming
24nW. Both prototypes achieve PEF below 0.7, validating the design’s effectiveness
across various power levels and processes.
Figure 3.10.1 shows the proposed input-boosted inverter-based amplifier. For each
transistor of the CMOS input pairs, differential signals are coupled to the gate and source
via Cg and Cs, respectively. Compared with the traditional inverter-based amplifier, the
input-boosted scheme accomplishes current reuse and input boosting at the same time,
achieving a 4-fold reduction in IRN with the same supply current and voltage. The
differential-mode (DM) transfer function reveals that the input-boosted amplifier has
doubled DM gain in the signal band. Concurrently, the common-mode (CM) input voltage
has the same polarity and amplitude at both the gate and source, effectively canceling
CM gain within the signal band. The biasing circuit is configured as a 1/12-width replica
of the main stage. It biases the input pairs in the deep subthreshold region to maximize
gm/Id, while biasing the tail-current transistors close to the saturation region to improve
matching. In this design, the PMOS input and tail transistors share the same voltage,
simplifying the biasing circuit design. The NMOS tail transistors are biased through
negative feedback loops so that the output DC voltage of each branch is guaranteed to
be Vcm. Additionally, the constant-gm biasing current Ib ensures its robustness across
PVT variations.
The block diagram of the overall 3-stage CCIA is shown in Fig. 3.10.2. Utilizing the inputboosted amplifier as the first stage, the gate and source coupling capacitors Cg and Cs
form the input capacitor Ci. The second stage and third stage are implemented for a high
loop gain, and the latter uses the tail-less topology for a wide output swing. The noise
and offset of these two stages are sufficiently suppressed by the first stage (gain ≈ 35).
Chopping is employed to modulate the input signal to the high-frequency signal band of
the first stage, concurrently mitigating offset and 1/f noise. A positive feedback loop
(PFL) is utilized to boost the input impedance by compensating for the input current [7].
AC coupling capacitors serve as DC blockers between stages, which not only eliminates
offset-induced ripples, but also allows for independent biasing of input pairs within each
stage, thereby maximizing the utilization of voltage headroom constrained by the low
supply voltage. The parasitic capacitance of the AC coupling capacitors deteriorates the
72 • 2024 IEEE International Solid-State Circuits Conference
BW of the preceding stage, necessitating their size to be constrained to tens of fF.
Pseudo-resistors with tens of GΩ are adopted to form a highpass corner well below the
chopping frequency.
To ensure that the pseudo-resistors maintain sufficiently high resistance across the wide
operational temperature range encountered in IoT scenarios, their resistance typically
reaches hundreds of GΩ at room temperature and increases even further at lower
temperatures. Therefore, even picoampere-level leakage currents can lead to significant
voltage droop. As depicted in Fig. 3.10.3, the leakage current mainly comes from 1) the
reverse-biased leakage current of the parasitic diode between wells and 2) the bulk
leakage current of the chopper switches. In a typical NMOS-based pseudo-resistor, two
transistors are biased in the cut-off region with their drain and bulk short-connected but
floated. To prevent the parasitic diode between the p-well and the deep n-well (DNW)
from being forward-biased, the DNW is connected to the supply voltage, which results
in the diodes’ reverse-biased leakage currents. The same happens to PMOS-based
pseudo-resistors. In this work, a well-biasing amplifier, implemented through a unit-gain
buffer, is introduced to align the voltage of the DNW with that of the p-well, effectively
reducing the leakage current flowing through the pseudo-resistor. Additionally, at the
input of the third stage, the pseudo-resistors are directly connected to the chopper
switches, whose bulk leakage current will flow through the resistor. To counteract this,
a bias-adjusting amplifier detects the common-mode voltage of the input pairs and
dynamically adjusts the bias voltage Vbp3 to compensate for the leakage current. The
well-adjusting amplifier and the bias-adjusting amplifier consume little power thanks to
the low noise limited by their ultra-low noise BW. Their power consumption is determined
by the minimum biasing current on the chip.
The proposed input-boosted CCIA is implemented in 22nm and 180nm CMOS processes,
and both prototypes achieve a PEF below 0.7, validating the design’s effectiveness across
different power levels and processes. Figure 3.10.4 shows the frequency response and
noise spectrum. The 22nm prototype occupies 0.042mm2 and draws 2.65nA from 0.6V
supply voltage. Chopping at 1.4kHz, the gain and BW are 31.5dB and 230Hz, with CMRR
and PSRR better than 81dB and 82dB below 100Hz. The measured IRN is 8.05uV,
referring to 1.07-NEF and 0.69-PEF. The total harmonic distortion (THD) is 1.3% with
an output swing of 75% of the supply voltage, and the input impedance is boosted to be
larger than 100MΩ with the PFL. The 180nm prototype occupies 0.4mm2 and draws
40nA from 0.6V supply voltage. Chopping at 12kHz, the gain and BW are 39dB and
1.6kHz, with CMRR and PSRR better than 83dB and 88dB below 1kHz. The measured
IRN is 5.1uV with a 1.6kHz BW, referring to 0.98-NEF and 0.58-PEF. The measured THD
is 0.5% (75% out) and the input impedance is larger than 75MΩ.
Figure 3.10.5 shows the temperature and supply robustness of the proposed inputboosted CCIA. The 1.6nW-22nm prototype shows a PEF better than 0.75 over -20°C to
70°C thanks to the leakage compensation circuits. A linear-to-supply PEF is also
measured from 0.55V to 0.70V supply voltage. Figure 3.10.6 summarizes the
performance and compares this work with the state-of-the-art. The proposed inputboosted CCIA shows the best PEF, with an inherent low-passing feature and no aliasing
concern, among continuous-time amplifiers (CTAs) in the comparison chart, providing
a promising solution for ultra-low-power IoT sensor systems.
Acknowledgement:
This work was supported by National Key R&D Program of China (No.
2022YFB4402001), National Natural Science Foundation of China (No. 92164301, No.
62225401), Beijing New-star Plan of Science and Technology (No. Z211100002121122),
and the 111 project (No. B18001). The corresponding authors are Linxiao Shen and Le
Ye (Linxiao.shen@pku.edu.cn, yele@pku.edu.cn).
References:
[1] P. Harpe et al., “A 0.20 mm2 3 nW Signal Acquisition IC for Miniature Sensor Nodes
in 65 nm CMOS,” IEEE JSSC, vol. 51, no. 1, pp. 240-248, Jan. 2016.
[2] Y.-P. Chen et al., “An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia
Monitoring,” IEEE JSSC, vol. 50, no. 1, pp. 375-390, Jan. 2015.
[3] S. Mondal and D. A. Hall, “A 13.9-nA ECG Amplifier Achieving 0.86/0.99 NEF/PEF
Using AC-Coupled OTA-Stacking,” IEEE JSSC, vol. 55, no. 2, pp. 414-425, Feb. 2020.
[4] L. Shen et al., “A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF,” IEEE
Symp. VLSI Circuits, pp. C144-C145, 2019.
[5] F. M. Yaul et al., “A sub-μW 36nV/√Hz Chopper Amplifier For Sensors Using a NoiseEfficient Inverter-Based 0.2V-Supply Input Stage,” ISSCC, pp. 94-95, 2016.
[6] G. Atzeni et al., “An Energy-Efficient Impedance-Boosted Discrete-Time Amplifier
Achieving 0.34 Noise Efficiency Factor and 389MΩ Input Impedance,” IEEE Symp. VLSI
Circuits, pp. 1-2, 2023.
[7] Q. Fan et al., “A 1.8 μW 60 nV/√Hz Capacitively-Coupled Chopper Instrumentation
Amplifier in 65 nm CMOS for Wireless Sensor Nodes,” IEEE JSSC, vol. 46, no. 7, pp.
1534-1543, July 2011.
979-8-3503-0620-0/24/$31.00 ©2024 IEEE
ISSCC 2024 / February 19, 2024 / 5:20 PM
3
Figure 3.10.2: The overall block diagram of the input-boosted capacitively-coupled
Figure 3.10.1: The proposed input-boosted inverter-based amplifier and its chopper instrumentation amplifier (CCIA) and the circuit implementation of the 2nd
comparison with prior arts.
and 3rd stages.
Figure 3.10.3: The illustration of the reverse-biased diode leakage current and the
bulk leakage current. The proposed well-biasing amplifier (WA) and the biasadjusting amplifier (BA) are adopted to compensate for the leakage current. The table Figure 3.10.4: The measured frequency response and the noise spectrum of the
proposed input-boosted CCIA implemented in 22nm and 180nm.
showing simulated power distribution.
Figure 3.10.6: The performance summary and comparison with the state-of-the-art.
Figure 3.10.5: The current consumption and noise performance of the 22nm The proposed input-boosted CCIA shows the best PEF among continuous-time
prototype, showing its robustness from -20°C to 70°C and 0.55V-to-0.70V supply amplifiers (CTAs) which has no aliasing concern across different power levels and
processes.
voltage.
DIGEST OF TECHNICAL PAPERS •
73
ISSCC 2024 PAPER CONTINUATIONS
Figure 3.10.7: Die micrographs: 22nm (left) and 180nm (right).
• 2024 IEEE International Solid-State Circuits Conference
979-8-3503-0620-0/24/$31.00 ©2024 IEEE