Integrated Devices, Electronics, And Systems (IDEAS) Group
Dept. of Information Technology and Electrical Engineering (D-ITET)
Fundamentals of RF and
mm-Wave Power Amplifier
Design
Hua Wang
Full Professor, Chair of Electronics
December 2021
Integrated Devices, Electronics, And Systems (IDEAS) Group
• BS from Tsinghua University, Beijing, China, in 2003
• MS and PhD from California Institute of Technology, Pasadena, CA, in 2007 and 2009, respectively
• Was with Intel Corporation, Hillsboro, OR, in 2010-2011 and Skyworks Solutions, San Jose, CA, in 2011
• 2012-2021, Associate Professor at School of ECE of Georgia Institute of Technology and Director of
Georgia Tech Center of Circuits and Systems (CCS)
• 2021-present, Full Professor and Chair of Electronics at ETH Zurich, D-ITET and Director of Integrated
Devices, Electronics, And Systems (IDEAS) Group
• DARPA Director’s Fellowship in 2020, DARPA Young Faculty Award in 2018, and NSF CAREER Award
in 2015
• My research interests are in integrated circuits and hybrid systems for wireless communication,
sensing, and bioelectronics applications
Outline
• Background and introduction
• Power Amplifier Design Considerations
— Active Device Designs
— Passive Network Designs
• Mm-Wave Power Amplifier Architectures and Examples
• Antenna-PA Co-Designs
— Merging Circuits with Electromagnetics and Radiation
• Conclusion
3
Background and Motivation
 Power amplifier (PA) is the last
active circuit stage of a transmitter.
 Ubiquitous in wireless systems

Mobile devices, access points, base
stations, backhaul

Automotive radar and imaging

Satellite communication
4
Fundamental Questions
 What is a power amplifier (PA)? When an amplifier should be called a PA?




Generating watt-level output power?
The designers should NOT follow conjugate matching?
Operation exhibits or requires some (large) nonlinearity?
An amplifier that can do damage to something?
VSupply
VSupply
PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
POut or PL
Loss = L
R0
• Device Gain/Efficiency/Linearity
• Impedance Transformation
• Operation Modes/Classes
• Power Combining
• Harmonics/Waveform Shaping
• Harmonics/Waveform Shaping
• Stability and Reliability
• Bandwidth and Filtering
5
Basic PA Performance Metrics (1 of 4)
 Basic performance metrics/values of a power amplifier (PA).
VSupply
VSupply
PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
Loss = L

PIn, PPA, POut (PL), PDC = PDC, PA + PDC, Driver

PA Power Gain: GP = POut/PIn

PA Drain Efficiency (DE or η): η = POut/PDC

Power Added Efficiency (PAE): PAE = (POut-PIn)/PDC
POut or PL
R0
6
Basic PA Performance Metrics (2 of 4)
 Basic performance metrics of a power amplifier (PA).
VSupply
VSupply
PIn, PPA, POut, GP,
PDC = PDC, PA + PDC, Driver

PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
Loss = L
POut or PL
R0
PA Drain Efficiency: η = POut/PDC
• If η = 40% and POut = 1W = +30dBm  PDC = 2.5W with 1.5W as heat!
• If VDD = 2.5V  total IDC = 1A!
DC IR Drop and
Reliability
Thermal Management,
Battery Life, etc…
7
Basic PA Performance Metrics (3 of 4)
 Basic performance metrics of a power amplifier (PA).
VSupply
VSupply
PIn, PPA, POut, GP,
PDC = PDC, PA + PDC, Driver

PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
Loss = L
POut or PL
R0
PA Drain Efficiency: η = POut/PDC
• If η = 40% and POut = 1W = +30dBm  PDC = 2.5W with 1.5W as heat!
• If VDD = 2.5V  total IDC = 1A!

Considering the output network loss: η = L×PPA/PDC
Low Loss Passive
Networks
• If L = 1dB ~ 80%  Required PPA/PDC = 50%
• For POut=1W  RF power loss in the output network = 250mW
8
Basic PA Performance Metrics (4 of 4)
 Basic performance metrics of a power amplifier (PA).
VSupply
VSupply
PIn, PPA, POut, GP,
PDC = PDC, PA + PDC, Driver

PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
Loss = L
POut or PL
R0
PA Drain Efficiency: η = POut/PDC
• If η = 40% and POut = 1W = +30dBm  PDC = 2.5W with 1.5W as heat!
• If VDD = 2.5V  total IDC = 1A!

Considering the output network loss: η = L×PPA/PDC
• If L = 1dB ~ 80%  Required PPA/PDC = 50%
• For POut=1W  RF power loss in the output network = 250mW

Power Gain: GP = POut/PIn
• If GP = 20dB  Input Power PIn = 10mW = +10dBm
Large Input
Driving Power
9
PA Efficiency Fundamental Limit
 Fundamental Limits on Power Amplifier Efficiency [Asbeck19].
VSupply
VSupply
PIn
Input
Matching
Interstage
Matching
Driver
PDC, Driver
Power
Stage
PPA
PDC, PA
Output
Matching
Loss = L
POut or PL
R0
𝑷𝑷𝑷𝑷 𝑷𝑷𝑷𝑷𝑷𝑷 = 𝜼𝜼𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫𝑫 × 𝜼𝜼𝑷𝑷𝑨𝑨 𝑴𝑴𝑴𝑴𝑴𝑴𝑴𝑴 × 𝜼𝜼𝑷𝑷𝑨𝑨 𝑮𝑮𝑮𝑮𝑮𝑮𝑮𝑮 × 𝜼𝜼𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝑶𝒕𝒕 𝑳𝑳𝑳𝑳𝑳𝑳𝑳𝑳 × 𝜼𝜼𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻𝑻 𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨𝑨
 Device Intrinsic η
• Knee Voltage
~ (1-VKnee/VDD)
• Large-Signal Output
Impedance
 PA Classes and
Harmonic
Shaping/Termination
― “Waveform
Engineering”
 Device Gain with
Input/Output Loading
 PA Output Network
= (1-1/GP)
• Differential Load
Balancing
• Loss = POut/PPA
~ ZOut/(ZOut+ZL)
10
Typical RF and Mm-Wave PA Power Levels
 PA Output Power POut by Link Budget
 RF-Frequency PAs
Friis Transmission Equation 𝑷𝑷𝑹𝑹 =
 Mm-Wave PAs
𝑨𝑨𝑹𝑹 𝑨𝑨𝑻𝑻
𝑷𝑷𝑻𝑻
𝒅𝒅𝟐𝟐𝝀𝝀𝟐𝟐
LTE: 23dBm/26dBm for Power
Class-3/-2 high-power UE

PA Pout vs. array size [Asbeck19]

Small/medium arrays  higher Pout

WLAN: 20-26dBm

Large arrays  lower Pout, system size/cost

NB IoT: 14dBm/20dBm/23dBm

Bluetooth: Class 1 (20 dBm),
Class 2 (4dBm), Class 3 (0
dBm), and Class 4 (-3 dBm)

Base station-1
Base station-2
Avg. Pout per element PA
11
PA SoA and Performance Trend
 Challenge: POut vs. Frequency ― State-of-the-Art (SoA) [Wang, PA Survey]
-20dB/dec
~ Johnson’s Limit
Need: High Power
at High Frequency
12
PA Output Power vs. Efficiency
 Challenge: POut vs. Efficiency


Limited device output power and
voltage swing (VDD-VKnee)
20-50GHz PAs in Silicon (2000-Present)
[Wang, PA Survey]
Device
Limited
POut = IRF×(VDD-VKnee)/2
Combiner/
Network Limited
= (VDD-VKnee)2/2RL

Larger devices or more devices

Lossy impedance transformation
Need: High-Power High-Efficiency
and Compact PAs
13
PA Spectrum, Linearity, and Efficiency (1 of 2)
 Challenge: Spectrum Efficiency vs. Linearity vs. Energy Efficiency

High-order QAM, OFDM, and Carrier Aggregation (CA)

Power amplifier linearity
16-QAM
4 bits per symbol
64-QAM
6 bits per symbol
256-QAM
8 bits per symbol
Need: High Linearity and
High Data Rate PAs
3GPP 38.101requirements on EVM
Parameter
Average EVM
π/2-BPSK
30%
QPSK
16 QAM
64 QAM
256 QAM
17.5%
12.5%
8%
3.5%
14
PA Spectrum, Linearity, and Efficiency (2 of 2)
 Challenge: Spectrum Efficiency vs. Linearity vs. Energy Efficiency

High-order QAM, OFDM, and Carrier Aggregation (CA)

High peak-to-average-power-ratio (PAPR)
 PA Back-off and averaged efficiency
Need: High Back-off
Efficiency and Linearity PA
15
PA Carrier Frequency Coverage
 Challenge: Crowded spectrum at GHz and
multiple non-contiguous bands at mm-Wave

Multi-band, multi-mode, international roaming
Need: Wideband or
Frequency Reconfigurable PA
Mm-Wave 5G Bands
US Spectrum Allocation
United States
24.25-24.45GHz
24.75-25.25GHz
27.5-28.35GHz
37-40GHz
47.2-48.2GHz
64-71GHz
Europe
24.25-27.5GHz
39GHz
China
24.75-27.5GHz
37-42.5GHz
India
24.25-27.5GHz
27.5-29.5GHz
37-43.5GHz
Japan
26.6-27GHz
27-29.5GHz
39-43.5GHz
South Korea
26.5-28.9GHz
16
PA Design Hexagon
 PA Design Hexagon and Tradeoffs
Carrier
Frequency
Reliability
Energy
Efficiency
Output
Power
Data Rate
Spectrum
Efficiency
17
Power Amplifier Survey V-6
• State-of-the-Art PA Psat vs. Freq. (All Technologies): 08/2021 (3813 data points)
• CW/Modulation Performance: Frequency (500MHz-1.5THz), Technologies, Pout, PAE, EVM, etc.
• Version-6 available to the public at http://gems.ece.gatech.edu/PA_survey.html
18
Power Amplifier Survey V-6
• State-of-the-Art PA Psat vs. Peak PAE (20-50GHz PAs)
Device Limited
[1]
[2]
[3]
[4]
[5]
Combiner/
Network Limited
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
[1] TCAS-I 19,
Washington State
[2] TMTT 19, Georgia
Tech
[3] ISSCC 18, UCSB
[4] ISSCC 19,
Georgia Tech
[5] RFIC 18, National
Taiwan
19
Power Amplifier Survey V-6
• State-of-the-Art PA Psat vs. Peak PAE (20-50GHz PAs)
PA Output Power vs. Array Size
[1]
[2]
[3]
[4]
[5]
Combiner/
Network Limited
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
[1] TCAS-I 19,
Washington State
[2] TMTT 19, Georgia
Tech
[3] ISSCC 18, UCSB
[4] ISSCC 19,
Georgia Tech
[5] RFIC 18, National
Taiwan
20
Power Amplifier Survey V-6
• State-of-the-Art PA Psat vs. Peak PAE (20-50GHz PAs)
GaAs +5 ~ +10dB
GaN +15 ~ + 20dB
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
21
Power Amplifier Survey V-6
PA Output Power vs. Array Size
• State-of-the-Art PA Psat vs. Peak PAE (20-50GHz PAs)
GaAs +5 ~ +10dB
GaN +15 ~ + 20dB
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
22
Power Amplifier Survey V-6
• State-of-the-Art PA Modulation Performance (High-Speed 64QAM)
Modulation and CW Performance Comparison for SiGe and CMOS (20-50GHz)
Averaeg Efficiency(%)
50
PAE=47
PAE=45
40
~1.7x PAE
Difference
30
Current-Mode Combing Outphasing
(DEavg) JSSC ’19
Class-F-1 JSSC ’16
(0.5GSym/s 64QAM) (8.4MSym/s 64QAM)
Mixed-Signal Doherty
ISSCC ’19
(1G/2.5GSym/s 64QAM)
PAEavg=28
Continuous Class-F
TCAS-I ’18
(250MSym/s 64QAM)
20
Triaxial Balun
Outphasing ISSCC ’18
(80MSym/s 64QAM
OFDM)
4-Stack Multigate
TMTT ’19
(5GSym/s 64QAM)
10
0
0
5
10
>12dB Power
Difference
15
20
25
Average Output Power Pout (dBm)
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
Modulation_CMOS
Modulation_CMOS(Since 2018)
Modulation_SiGe
Modulation_SiGe(Since 2018)
CW_Envelope_CMOS
CW_Envelope_SiGe
Modulation_Envelope
30
35
40
23
Power Amplifier Survey V-6
PA Output Power vs. Array Size
• State-of-the-Art PA Modulation Performance (High-Speed 64QAM)
Modulation and CW Performance Comparison for SiGe and CMOS (20-50GHz)
Averaeg Efficiency(%)
50
PAE=47
PAE=45
40
~1.7x PAE
Difference
30
Current-Mode Combing Outphasing
(DEavg) JSSC ’19
Class-F-1 JSSC ’16
(0.5GSym/s 64QAM) (8.4MSym/s 64QAM)
Mixed-Signal Doherty
ISSCC ’19
(1G/2.5GSym/s 64QAM)
PAEavg=28
Continuous Class-F
TCAS-I ’18
(250MSym/s 64QAM)
20
Triaxial Balun
Outphasing ISSCC ’18
(80MSym/s 64QAM
OFDM)
4-Stack Multigate
TMTT ’19
(5GSym/s 64QAM)
10
0
0
5
10
>12dB Power
Difference
15
20
25
Average Output Power Pout (dBm)
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
Modulation_CMOS
Modulation_CMOS(Since 2018)
Modulation_SiGe
Modulation_SiGe(Since 2018)
CW_Envelope_CMOS
CW_Envelope_SiGe
Modulation_Envelope
30
35
40
24
Power Amplifier Survey V-6
• State-of-the-Art PA Modulation Performance (High-Speed 64QAM)
Modulation and CW Performance Comparison for SiGe and CMOS (20-50GHz)
50
PAE=47
Averaeg Efficiency(%)
40 Architecture,
New PA
~1.7x PAE
Linearization…Difference
30
PAE=45
Current-Mode Combing Outphasing
(DEavg) JSSC ’19
Class-F-1 JSSC ’16
(0.5GSym/s 64QAM) (8.4MSym/s 64QAM)
Mixed-Signal Doherty
ISSCC ’19
(1G/2.5GSym/s 64QAM)
PAEavg=28
Continuous Class-F
TCAS-I ’18
(250MSym/s 64QAM)
20
Triaxial Balun
Outphasing ISSCC ’18
(80MSym/s 64QAM
OFDM)
4-Stack Multigate
TMTT ’19
(5GSym/s 64QAM)
10
0
0
5
10
Linearization,
Power
>12dB
Power
Difference
Combining,
Reconfiguration …
20
25
15
Average Output Power Pout (dBm)
• PA/TX survey 2000-present (version-6). http://gems.ece.gatech.edu/PA_survey.html
Modulation_CMOS
Modulation_CMOS(Since 2018)
Modulation_SiGe
Modulation_SiGe(Since 2018)
CW_Envelope_CMOS
CW_Envelope_SiGe
Modulation_Envelope
30
35
40
25
PAs in Mm-Wave Wireless Systems and Arrays
0
• Why beamforming? ─ TX
• Total Radiated Power = P0(dBm) + 10logN
• Total EIRP = P0(dBm) + 10logN + 10logN
0
Null @ -30°
30
30
-4
Null @ 30°
-8
60
60
-12
-16
• Why beamforming? ─ RX
•
•
•
•
Total Array SNR = Element SNR + 10logN
Total Array NF = Element NF - 10logN
Total Array P1dB = Element P1dB + 10logN
Total Array IIP3… Well, it depends…
90
90
• Focused TX radiation energy
• Enhance RX SNR
Link Budget + 30logN
• Spatial filtering: Null-steering, spatial
equalization, side-lobe apodizing, etc…
26
PAs in Mm-Wave Wireless Systems and Arrays
0
• Why beamforming? ─ TX
• Total Radiated Power = P0(dBm) + 10logN
power
consumption
×
• Total• Total
EIRP = DC
P0(dBm)
+ 10logN
+ 10logN
0
Null @ -30°
30
30
-4
Null @ 30°
-8
N  Thermal management
and operation time  Packaging and cooling capacity
60
60
-12
-16
• Total array ─
panel
• Why beamforming?
RX size × N  Form-factor limitation in UE
90
90
-1(2/N)• 
Focused
TX radiation
energy
•
Main
lobe
beamwidth
~
2sin
TX/RX
alignment
in
• Total Array SNR = Element SNR + 10logN
mobile
• Total Array
NF =applications
Element NF - 10logN
• Enhance RX SNR
• Total Array P1dB = Element P1dB + 10logN
• Total Array IIP3… Well, it depends…
Link Budget + 30logN
• Spatial filtering: Null-steering, spatial
equalization, side-lobe apodizing, etc…
27
Frequency Scaling to Sub-mm-Wave (Beyond-5G/6G)
• Scaling in frequency? Arrays for sub-THz/6G wireless?
• Friis transmission formula: PR=
PTGTGRC2
(4π×D×freq)2
 Path loss ~ 1/(freq)2
• Well… What if the array is also scaled but within the same panel size (area)?
 TX/RX array element N2 ~ (1/λ)2 ~ (freq)2
 TX EIRP ~ N4 and RX NF ~ (1/N)2
 Total link budget ~ N4 ~ (freq)4!
28
Frequency Scaling to Sub-mm-Wave (Beyond-5G/6G)
• Scaling in frequency? Arrays for sub-THz/6G wireless?
• Friis transmission formula: PR=
PTGTGRC2
(4π×D×freq)2
 Path loss ~ 1/(freq)2
• Well… What if the array is also scaled but within the same panel size (area)?
 TX/RX array element N2 ~ (1/λ)2 ~ (freq)2
 TX EIRP ~ N4 and RX NF ~ (1/N)2
 Total link budget ~ N4 ~ (freq)4!
• Well… There are several VERY important assumptions here…
(1) Constant TX element Pout
(3) Constant RX element NF
(2) Constant TX element efficiency
(4) Element size ~ (1/freq)
29
Array Element Size vs. Frequency
H. Wang, P. M. Asbeck, and C. Fager,
"Millimeter-Wave Power Amplifier
Integrated Circuits for High Dynamic
Range Signals," IEEE Journal of
Microwaves (the inaugural issue), vol.
1, no. 1, pp. 299 - 316, Jan. 2021.
(1) Constant TX element Pout?
(3) Constant RX element NF?
(2) Constant TX element efficiency?
(4) Element size ~ (1/freq)??
30
Where shall we put the antennas? On-chip or on-package?
Antenna too large to be on chip
Array lattice too small for
on-chip antenna
31
Power Density of Integrated Mm-Wave PAs
• Definitions of Power Density
• Power Capability = Psat/device_size = W/mm = F(drain voltage, drain current density, frequency)
Device-centric metric. Great for comparing device technologies and intrinsic behaviors
• Power Density = Psat/PA_core_size= W/mm2 = F(device W/mm, backend quality, layouts, topology)
Circuit-centric metric. Great for comparing circuits and planning system architectures
32
Power Density of Integrated Mm-Wave PAs
• Definitions of Power Density
• Power Capability = Psat/device_size = W/mm = F(drain voltage, drain current density, frequency)
Device-centric metric. Great for comparing device technologies and intrinsic behaviors
• Power Density = Psat/PA_core_size= W/mm2 = F(device W/mm, backend quality, layouts, topology)
Circuit-centric metric. Great for comparing circuits and planning system architectures
• Other useful applications of the W/mm2 metric:
(1) Compare different technologies for the area-efficiency to generate RF power
(2) Given the chip area, we can estimate the achievable PA output power Psat
Array frequency  Array lattice area  Assign % area for PA  Estimate Psat per PA  # of
array elements to meet a given array EIRP
(3) Given the chip cost/area ($/mm2)  Cost to generate certain output power (W/$)
33
Power Density of Integrated Mm-Wave PAs
• Power Density = Psat/PA_core_size= W/mm2 vs. technologies for >90GHz
• W/mm2 decreases over frequency and Psat
• Some InP PAs have the highest W/mm2 density
• Some GaN PAs achieve the highest Psat
• Some CMOS designs achieves similar
W/mm2 density than GaN PA designs. Why?
34
Power Density of Integrated Mm-Wave PAs
• Power Density = Psat/PA_core_size= W/mm2 vs. technologies for >90GHz
• W/mm2 decreases over frequency and Psat
• Some InP PAs have the highest W/mm2 density
• Some GaN PAs achieve the highest Psat
• Some CMOS designs achieves similar
W/mm2 density than GaN PA designs. Why?
• Layout compactness (Active + Passive)
• Backend options  Compact and highcoupling passives
35
Power Density of Integrated Mm-Wave PAs
• Power Density = Psat/PA_core_size= W/mm2 vs. technologies for >90GHz
• W/mm2 decreases over frequency and Psat
• Existing integrated TRX arrays result in a crossing point of 70• Some InP PAs have the highest W/mm2 density
100GHz.
• Some GaN PAs achieve the highest Psat
• High mm-Wave PAs (beyond-5G/6G) should
be compact
and similar
• Some CMOS
designs achieves
W/mm2 density than GaN PA designs. Why?
energy-area efficient.
• Layout compactness (Active + Passive)
• New innovations on devices, circuits, systems, packaging…
• Backend options  Compact and highcoupling passives
36
Outline
• Background and Motivations
• Power Amplifier Design Considerations
— Active Device Designs
— Passive Network Designs
• Mm-Wave Power Amplifier Architectures and Designs
• Antenna-PA Co-Designs and Examples
— Merging Circuits with Electromagnetics and Radiation
• Conclusion
37
Loadpull Contour (1 of 3)
 Loadpull contour: What happens for a complex load ZL ≠ Ropt?

𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜
For Re(ZL) = RL < Ropt : “Current limited regime”  Max Id swing, but not Max Vd swing
1
𝑅𝑅𝐿𝐿
1
2
2
𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚
= 𝑅𝑅𝐿𝐿 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 =
�
= 𝐾𝐾 � 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜
2
𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 2
VDD
RF
Choke
Vd
Vin
IL = Imax
Id V (f ) ≤ V
d 0
DD
𝑉𝑉𝑑𝑑 = 𝑍𝑍𝐿𝐿 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 =
jXL
RL
𝑋𝑋𝐿𝐿 ≤
2
𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜
− 𝑅𝑅𝐿𝐿2 =
K = RL/Ropt < 1 is the power
degradation factor.
𝑅𝑅𝐿𝐿2 + 𝑋𝑋𝐿𝐿2 � 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚 ≤ 𝑉𝑉𝐷𝐷𝐷𝐷
1 − 𝐾𝐾 2 � 𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜
ZL = RL + j√1-K2 × Ropt
ZL = RL
Ropt = 12.5Ω
for Max Pout
K × Max Pout
ZL = RL - j√1-K2 × Ropt
Following a constant resistance
circle on the Smith Chart
38
Loadpull Contour (2 of 3)
 Loadpull contour: What happens for a complex load ZL ≠ Ropt?

𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜
VDD
RF
Choke
Vd
Vin
For Re(ZL) = RL > Ropt : “Voltage limited regime”  Max Vd swing, but not Max Id swing
2
2
𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜 1 𝑉𝑉𝐷𝐷𝐷𝐷
1 𝑉𝑉𝐷𝐷𝐷𝐷
=
=
�
= 𝐾𝐾 � 𝑚𝑚𝑚𝑚𝑚𝑚 𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜
2 𝑅𝑅𝐿𝐿
2 𝑅𝑅𝑜𝑜𝑜𝑜𝑜𝑜
𝑅𝑅𝐿𝐿
𝐼𝐼𝑑𝑑 = 𝑌𝑌𝐿𝐿 𝑉𝑉𝐷𝐷𝐷𝐷 =
IL (f0) ≤ Imax
Id
Vd = VDD
jBL
GL=1/RL
𝐵𝐵𝐿𝐿 ≤
K = Ropt/RL < 1 is the power
degradation factor.
𝐺𝐺𝐿𝐿2 + 𝐵𝐵𝐿𝐿2 � 𝑉𝑉𝐷𝐷𝐷𝐷 ≤ 𝐼𝐼𝑚𝑚𝑚𝑚𝑚𝑚
2
𝐺𝐺𝑜𝑜𝑜𝑜𝑜𝑜
− 𝐺𝐺𝐿𝐿2 =
1 − 𝐾𝐾 2 � 𝐺𝐺𝑜𝑜𝑜𝑜𝑜𝑜
YL = GL - j√1-K2 × Gopt
Ropt = 12.5Ω
for Max Pout
K × Max Pout
YL = GL = 1/RL
YL = GL + j√1-K2 × Gopt
Following a constant conductance
circle on the Smith Chart
39
Loadpull Contour (3 of 3)
 Loadpull contours at different reference planes due to device output parasitics
Load Plane 1
VDD
Load
Plane 1
RF
choke
Vd
Vin
Load Plane 2
Loadpull Contours (45nm
CMOS SOI at 28GHz)
Load
Plane 2
Max Pout @
Ropt = 12.5Ω
Id
CD
Max Pout -1dB
Max Pout -2dB
Pout
Contour
PAE
Contour
Device size (W/L) : 1µm×25×4/40nm
40
Power Amplifier Nonlinear Distortions
 PA nonlinear distortions: AM-AM and AM-PM Distortions [Golara17]

LTI system, memoryless nonlinear system, and nonlinear system with memory
𝑽𝑽𝒊𝒊𝒊𝒊 = 𝑨𝑨 � 𝐜𝐜𝐜𝐜𝐜𝐜 𝝎𝝎𝟎𝟎 𝒕𝒕
𝑽𝑽𝒊𝒊𝒊𝒊 = 𝑨𝑨 � 𝐜𝐜𝐜𝐜𝐜𝐜 𝝎𝝎𝟎𝟎 𝒕𝒕
AM-AM Distortion
𝑯𝑯 ( 𝝎𝝎𝟎𝟎 , 𝑨𝑨 |
Q
∆r
r
LTI System H(s)
Nonlinear System
with Memory
AM-PM Distortion
∠(𝑯𝑯 ( 𝝎𝝎𝟎𝟎 , 𝑨𝑨)
Gain
Compression
𝑽𝑽𝒐𝒐𝒐𝒐𝒐𝒐 = 𝑯𝑯 ( 𝝎𝝎𝟎𝟎 , 𝑨𝑨 | � 𝑨𝑨 � 𝐜𝐜𝐜𝐜𝐜𝐜(𝝎𝝎𝟎𝟎 𝒕𝒕 + ∠𝑯𝑯 ( 𝝎𝝎𝟎𝟎 , 𝑨𝑨))
Q
∆r
r
θ
I
𝑽𝑽𝒐𝒐𝒐𝒐𝒐𝒐 = 𝑯𝑯 ( 𝝎𝝎𝟎𝟎 | � 𝑨𝑨 � 𝐜𝐜𝐜𝐜𝐜𝐜(𝝎𝝎𝟎𝟎 𝒕𝒕 + ∠𝑯𝑯 ( 𝝎𝝎𝟎𝟎 ))
I
 AM-AM Δr/r = 0.1 ≈ 1dB
Psat=18dBm
OP1dB = Psat-2.8dB
AM-PM = 6.3°
 AM-PM θ = 0.1 rad ≈ 6°
Constellation
Rotation
41
Power Amplifier Nonlinear Distortions
 PA AM-AM and AM-PM Distortions: In-Band Distortion  EVM (Error Vector
Magnitude)
 PA Spectral Regrowth: Out-of-Band Distortion  ACLR (Adjacent Channel
Leakage Ratio)
Lower
average Pout
EVMrms
= -28dB
Higher
average Pout
EVMrms
= -24dB
Higher ACLR due
to Out-of-Band
Distortions
-32dBc
-32dBc
-31dBc
-32dBc
-26dBc
42
Nonlinearity in a Physical Power Device
 Almost all the device elements are nonlinear  AM-AM and AM-PM distortions
 Large-signal model or bias-dependent small-signal model
 Taylor series or Volterra series [Razavi11]
G
Cgd
Rg
Rd
VL
Vgs
Cgs
gmVgs
Rs
Rds
Cjd
Cds
Rsub
D
 AM-AM: gm, Rds, Cgs, Cgd, Cds
 AM-PM: Cgs, Cgd, gm, Cds
S
43
Gm Nonlinearity and MGTR Technique
 Gm nonlinearity is bias dependent.
 Sweet spot gm biasing
ID
ID
 Multi-gated transistors (MGTRs)
44
gm
gm2
gm3
-2-2
-4-4
0
-1
Sweet spot
biasing
-2
-3
0
0.3
0.6
VGS (V)
0.9
freq
00
1
1.2
Conv
00
0.4
0.4
gm3 impulse
44
VVGS
(V)
GS (V)
0.8
0.8
Class-ABMGTR
22
Vbias_3
Vbias_4
IMD3L w/o MGTR
IMD3H w/o MGTR
IMD3L w MGTR
IMD3H w MGTR
1.2
1.2
freq
00
-2-2
-4-4
Vbias_2
ID_3
Pout
2
Class-ABconv
22
2) 2
ggm3m3(S/V
(S/V
)
3
Vbias_1
ID_2
gm3 impulse
2
ggm3m3(S/V
(S/V2))
gm (A/V), gm2 (A/V2), gm3 (A/V3)
4
Vbias
Pout
Gm nonlinearity
ID_1
Vin
Vin
M1
M3
MGTR
00
M2
M4
0.4
0.4
0.4
VVGS
(V)
(V)
V GS (V)
0.8
0.8
0.8
1.2
1.2
1.2
GS
44
ID_4
Nonlinear Capacitors Cgs
 Cgs nonlinearity can be linearized by NMOS/PMOS devices [Chowdhury09] [Vigilante18].
 Extra capacitance loading  input matching, matching loss, bandwidth
Cgd
𝐶𝐶𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛 2𝑊𝑊𝑛𝑛 𝐿𝐿𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜_𝑛𝑛
≈
𝐶𝐶𝑝𝑝𝑝𝑝𝑝𝑝𝑝𝑝 3𝑊𝑊𝑝𝑝 𝐿𝐿𝑝𝑝 𝐶𝐶𝑜𝑜𝑜𝑜_𝑝𝑝
𝐶𝐶𝑝𝑝𝑚𝑚𝑚𝑚𝑚𝑚 ≈ 𝑊𝑊𝑝𝑝 𝐿𝐿𝑝𝑝 𝐶𝐶𝑜𝑜𝑜𝑜_𝑝𝑝
2.6
Capacitance (pF)
𝐶𝐶𝑛𝑛𝑛𝑛𝑛𝑛𝑛𝑛
2
≈ 𝑊𝑊𝑛𝑛 𝐿𝐿𝑛𝑛 𝐶𝐶𝑜𝑜𝑜𝑜_𝑛𝑛
3
2.2
NMOS
PMOS
NMOS+PMOS
1.8
1.4
1
0.6
0
0.2
0.4
0.6
0.8
Vin (V)
1
1.2
45
2nd Harmonic Terminations
 2nd harmonic feedback remixing with the fundamental signal  IMD3 generation
 2nd harmonic termination for PA linearity improvement [Kang2006] [Li18].
RF
choke
2f0
Vin
f0
CN
+Vin
+Id
+Vout
+Id
2f0
Id
f0
Vd
-Vout
CN
+Vin
IMD3
-Id
-Vout
CN
+Vout
-Id
CN
-Vin
CN
-Vin
+Vin
+Id
+Vout
-Id
-Vout
CN
-Vin
IMD3(dBc)
VDD
2nd harmonic short
Pin(dBm)
46
Active Devices for Mm-Wave PA Design
 The fundamental challenges in mm-Wave PA
Design ― Limited active device gain

A two-port active device power gain
25
Gmax(dB)
Dependent on device configurations:
size/layout, biasing, matching

Limited fmax  Limited device gain
0<K<1
15
K>1
Fmax=262(GHz)
10
Fmax=334(GHz)
5
0

RF device (Class-A)
RF device (Class-AB)
20
(1) Conditionally stable region (0<K<1):
(2) Unconditionally stable region (K>1):
Power Gain vs. Freq. for a Typical
Scaled CMOS Device (45nm)
W/L=1µm×25×4/40nm
0

50 100 150 200 250 300 350 400
Frequency(GHz)
Gain @ 60GHz = 10dB  7.5dB
47
Mm-Wave PA Active Device Optimization
500
 Transistor speed metric
Fmax(GHz)
400
300
0.5um_finger
1um_finger
2um_finger
2.5um_finger
200
100
0
0.001
 Device Layout Optimization and Extraction
But Nf↑  other parasitics↑
Power combining multiple
smaller devices
 Combiner η and area, etc…
Fmax(GHz)
Wf ↓  Nf↑ and Rg↓
400
300
200
0.01
0.1
1
0.1
1
IDS/W(mA/µm)
PDK
RC exraction
EM extraction
100
0
0.001
0.01
IDS/W(mA/µm)
48
Mm-Wave PA Active Device Gain and Neutralization

Gmax ~ Device Unilateral Gain (U)

Gmax vs. CN with a “volcano” shaped function

High input impedance

Parasitics of CN are important at high mm-Wave
+Ifb
CN
+Vin
+Vout
-Id
-Vout
-Ifb
Cgd
Gmax (dB)
+Id
CN
Cgd
-Vin
15
2.5
Gmax
K-factor
Unilateral
Power Gain (U)
RF device (Class-A)
RF device Neutralized (Class-A)
1
10
5
0.5
0 10 20 30 40 50 60 70 80 90 100
CN (fF)
0
100
1000
Drain+
1.5
1
Fmax=334(GHz)
Frequency(GHz)
2
10
0
35
30
25
20
15
10
5
0
K-Factor
20
Gmax(dB)
 Cross-coupled capacitors CN to null the
feedback: Broadband Neutralization [Lee03]
Device size (W/L) : 1µm×25×4/40nm
Gate+
DrainNeutralization
Capacitors
Gate-
49
PA Output Passive Network Design Basics
 Load impedance and output power of silicon PAs
VDD
RF
choke
Vin

PA Output
Passive
Nework
Vd
Id
Vknee
For Pout = 30dBm = 1W = (1/2)×(VDD-Vknee)2/RL
RL=50Ω
PA Load
Example: A PA with VDD=2.5V and Vknee=0.2V
 RL ≈ 2.6Ω and×19 transformation from 50 Ω
 Challenge in passive network designs for silicon PAs

Limited voltage swing (CMOS 1V/2V, SiGe 2V/4V)  Needs small load RL

Large impedance transformation and/or power combining

Low loss, wideband, harmonic controls, compact …
50
Output Passive Network: L-Match
 Lumped LC passive impedance transformation network: L-match network
RL = RS
RL
CS
LP
L-Match
CS
LS = (1+QP2)/QP2
ω0 = 1/√ (LsCs)
R0=50Ω
RL = RS = R0/(1+QP2) < R0
QP = R0/ω0LS
 Impedance Down
Transformation
Rs =
R0/(1+QP2)
LP
CS
RL = RS
RL
LS
CP
L-Match
R0=50Ω
LS
R0 = 50Ω
CS = (1+QP2)/QP2
ω0 = 1/√ (LsCs)
QP = R0ω0CP
LS
Rs =
R0/(1+QP2)
RL = 12.5Ω
CP
 Distributed T-line based implementations [Pozar11]
51
Output Passive Network: High-Order L-Match
 One-Section L-Match

Direct tradeoff of transformation
ratio, Qnetwork, BW, and PE
RL
CS
Q=3
LP
L-Match
Q = 1.717
RL = R0/(1+Qnetwork2)
Passive Efficiency (PE) ~ [1+Qnetwork/Qunloaded]-1
RL
...
CS
R0=50Ω
LP
L-Match
CS
LP
L-Match
Q=3
Q = 1.07
R0=50Ω
R0 = 50Ω
RL = 12.5Ω
RL = 5Ω
R0 = 50Ω
RL = 5Ω
 Multi-Section L-Match

Lower Qnetwork and broader BW but with complexity, area, and loss
52
Output Passive Network: Transformer
 On-chip Transformers: Different compact lumped models [Long00].
P
LP - M
LS - M
S
Ideal Transformer
Rp
Cp
(1-km2)LP
km2LP
1: (n/km)
IP
IS
1:n
IS•M12/LP
M
P
P
LP
CS
S
P
C0/n
LS
1:n
Cp/n2
IP•M21/LS
LS
Ideal Transformer
Rs
S
n2RS
rs
S
Cs+
C0(n-1)/n
RS
53
Advantages of Transformer Networks
 Transformers are particularly suitable for RF or low/medium mm-Wave PAs.
RL
(1) Differential to SingleEnded Conversion + Power
Combining + Impedance
Matching
(3) Even-Order Harmonic
Controls (Class-F, F-1, J, J*,
etc.) or Linearity
(2) VDD Supply Feed with
No Need for RF Chokes
VDD
Even
Harmonic
Term.
CN
+Vout
-Vout
(4) Differential Operation
for Broadband Capacitive
Neutralization
CN
Even
Harmonic
Term.
(5) Common-Mode Isolation
for Stability + Input
Matching
VG
+Vin
-Vin
(6) Device Gate/Base
Biasing with No Need for
Large Biasing Resistors.
 Small Time Constant and
Low Memory Effect
 GHz Dynamic Biasing for
Mm-Wave 5G PAs
54
Transformer Matching Network Design Example
 On-chip transformer matching design example



Single-transformer footprint  compact chip area
Differential to single-ended conversion
Impedance down-transformation
Frequency = 28GHz
Z5
Device Parasitics and Output Matching Network
Z4
On-Chip Transformer Model
K:n
(1-k2)L/2
Output
Stage
k2L/2
Cdev
Cs
k2L/2
Cpad
Z3
ZOptimum=40Ω
Z1
Z0=50Ω
Z0
Z2
(1-k2)L/2
ZOptimum
Z5
Z4
Z3
Z2 Z1
• k: magnetic coupling coefficient • CS: extra matching capacitor
• n: transformer turn ratio
• Cpad: pad parasitic capacitor
• L: primary self-inductance
• Cdev: device output parasitic capacitor
55
Power Combining Networks
 Power combining networks to further boost PA output power
Direct Parallel Power
Combiners (Zero-Phase)
PA
Matching
PA
Matching
PA
Simple
Compact
No isolation



PA
λ/4
RL
λ/4
λ/4
PA
λ/4
RL
λ/4
Wilkinson, Gysel, quadrature combiners 
Good isolation and asymmetry


Bulky and bandwidth limitation
•••
RL
λ/4
•••



PA
Matching
•••
PA
PA
Transformer Power
Combiners
•••
PA
Distributed Power
Combiners
PA
PA
Compact and broadband
Impedance transformation
Many variations
56
Transformers as Power Combiners
 Transformers as power combiners
XFMR Series Power Combiners
XFMR Parallel Power Combiners
RL
RL
IL = I1+I2+I3+…+IN
1:n1
IL
IL
1:n2
1:n3
IL
...
1:nN
...
ZL,1
ZL,2
PA1



ZL,3
PA2
ZL,N
PA3
PAN
Adding voltages in the secondary
Constant secondary currents
PA load impedance down-scaling
1:n1
1:n2
1:n3
ZL,1
ZL,2
ZL,3
PA1



PA2
1:nN
...
ZL,N
PA3
PAN
Adding currents in the secondary
Constant secondary voltages
PA load impedance up-scaling
57
Transformer-Based Broadband Network
 Transformer for broadband PAs with high-order matching/filter networks
XFMR for Bandpass Ladder Filters [Wang10]
L2
R0
C1
L2a′
R0′
R0′
C1′
(3) Fitting as a
Physical Transformer
L2b"
C1"
L3
R0
C1
L1
L1′
R0
R0
L3
C1′
(3) Fitting as a
Physical Transformer
C2
C3
L3
R0
L3′
L1′
R0′
R0
L2b′
C1"
C3
R0
C3
R0
C3
R0
C3
R0
L2b"
L3′
Physical
Transformer
R0"
L3
L2′
C1
(2) Splitting L2’
C2
C3
L2b"
R0
(1) Δ-Y transformation
C3
L1′
Physical
Transformer
R0"
L2b′
L3
C2
L1′
L2a′
L2
C3
L2b
C1′
(2) Splitting L2b
C2
L1
(1) Splitting L2 +
Norton Transformation
XFMR for Coupled Resonator Filters [Bassi15]
L2b"
58
Coupler Baluns as High Mm-Wave “Transformers”
 Lumped transformers at high mm-Wave: small, sensitive to parasitics, and low coupling
 Distributed coupler baluns for high mm-Wave circuits  Magnetic & capacitive coupling
YL
Port (1)
𝑺𝑺𝟐𝟐𝟐𝟐 = 𝑺𝑺𝟑𝟑𝟑𝟑
𝑺𝑺𝟐𝟐𝟐𝟐 = − 𝑺𝑺𝟑𝟑𝟏𝟏
3D-EM model of
Coupler-Based Balun
66µm
LD = 4.1µm
6.1µm
OA = 3µm
196µm
Even/Odd-Mode
Analysis [Ang03]
180°
SC. or
OC.
Port (3)
S-Parameters(dB)
𝑺𝑺𝟏𝟏𝟏𝟏 = 𝟎𝟎
0° 180°
Port (2)
YS
0°
Plane of Symmetry
RL
Port (2)
Port (1)
Port (3)
0
0
Passive loss
-1
-5
Broad Passband
90-180 GHz
-2
-10
-3
-15
-4
-5
-20
Load Impedance Mismatch
70
90
110 130 150 170
Frequency(GHz)
190
-25
YS
5
4
3
2
1
0
-1
-2
-3
-4
-5
Amplitude/Phase
Imbalance(dB/degree)
θ, Zodd, Zeven
S-Parameters(dB)
θ, Zodd, Zeven
Amplitude imbalance
Phase imbalance
70
90
110 130 150
Frequency(GHz)
170
59
190
Coupler Balun Properties in Practice
 Properties of coupler baluns in practice

Low loss and broad bandwidth

Naturally absorbs PA device output capacitances  Compact size << λ/4

Ensures high CMRR and Teven ~ 0  Balanced differential impedance and transmission

Built-in impedance transformation and much more!
ΓS
Coupler Baluns for Impedance
Inverting or Scaling [Nguyen20]
Port (2)
Zin
Port (3)
Zin
ΓS
Port (1)
Coupler Baluns for Series
Power Combining [Nguyen19]
ΓL Z
L
Coupler Balun (N)
𝜞𝜞𝑺𝑺 = 𝜞𝜞𝑳𝑳𝒆𝒆−𝟐𝟐𝟐𝟐×𝑷𝑷𝒉𝒉𝒉𝒉𝒉𝒉𝒉𝒉 (𝑺𝑺𝟐𝟐𝟐𝟐)
ZL Inverting
Balun
ZL Scaling
Balun
θ, Zodd, Zeven
θ, Zodd, Zeven
θ, Zodd, Zeven
θ, Zodd, Zeven
Coupler Balun (1)
•••
•••
VDD
VDD
PA
(N)
VDD
•••
VDD
PA
(1)
60
RL
Outline
• Background and Motivations
• Power Amplifier Design Considerations
— Active Device Designs
— Passive Network Designs
• Mm-Wave Power Amplifier Architectures and Designs
• Antenna-PA Co-Designs and Examples
— Merging Circuits with Electromagnetics and Radiation
• Conclusion
61
Introduction
Examples from My Group: RF/Mm-Wave PAs with Pout, Efficiency and Linearity
A Digital Polar
Doherty PA in CMOS
A Hybrid-Mode Digital PA
in CMOS for Deep PBO
Dual-Band 2.4/4.8GHz
Digital PAs
RFIC 2014 Best
Student Award (1st
Place), JSSC 2015, TMTT 2015
ISSCC 2015, Microwave
Magazine 2015 (Best
Paper Award), JSSC 2016,
RFIC 2016, JSSC 2017
CICC 2015 Best Student
Paper Award (2nd
Place), JSSC 2016,
ISSCC 2018, JSSC 2018
World-First
28GHz/37GHz/39GHz
Multiband Doherty PA
for 5G Massive MIMO
A Highly Linear SuperResolution Mixed-Signal
Doherty PA for MmWave 5G
A Reconfigurable
Series/Parallel Doherty
PA with VSWR
Resilient Performance
A 26-60GHz
Continuous Mode
Coupler Balun
Doherty PA
ISSCC 2017, JSSC
2019
ISSCC 2019, JSSC 2019
ISSCC 2020
ISSCC 2021
650µm
RF_out
Output Network
Power Stage
Inter-Stage Network
Driver stage
950µm
Input Network
Quadrature Coupler
GND
VDD
An Instantaneously Broadband
Ultra-Compact Highly Linear
PA for 5G over 24-40GHz
A 28GHz Current-Mode
Inverse-Outphasing
Transmitter for 5G
Communication
A 24-30GHz Watt-Level
Broadband Linear
Doherty PA with MultiPrimary DAT
ISSCC 2020
ISSCC 2020
ISSCC 2020
ISSCC 2019
DC Bias
Main PA VDD2
0.55mm
ContinuousInput
mode
Matching PA Harmonicallytuned
Network
Network
Vin-
Transformer
balun
Vout+
2.30mm
Vin+
PA input
Transformer
balun
Transformer
balun
Multi-primary
DAT Doherty
output
network
Transformer
balun
0.98mm
Main PA VDD1
DC Bias
RC pairs
PA stage
Interstage
matching
RC pairs
driver stage
ISSCC 2021
Aux PA VDD2
PA output
Wilkinson
power divider
Vout-
Quadrature
hybrid
RC pairs
driver stage
Interstage
matching
RC pairs
PA stage
A 28GHz Class-W
Multi-Drive MmWave PA
1.38mm
GND
330µm
PA
PA
Cells Cells
RF_In
1900µm
PA Output
8-Bit AM Control Code
PA
Cells
World-First 60GHz 1-Watt CMOS PA
with Cascaded Asymmetric DAT
0.25mm
ISSCC 2018, RFIC
2018, T-MTT 2019
SPI
Continuous-Mode
Harmonically-Tuned
Ultra-Linear PAs
1.8mm
Transformer-based
digitally controlled
load modulation
network
RF power DAC
and its digital
drivers with
varactors
PA
Cells
Input Driver
Class-G
supply
modulator
Phase Modulated Differential Input
Adaptive Bias
VDD
1.8mm
Quadrature
hybrid
Aux PA VDD1
1.82mm
62
1200µm
Recently Reported Class-AB PAs in Silicon
• Balanced performance
of efficiency, linearity,
and modulation BW
• “RF-in-RF-out” PAs
 System integration
 Compact size
 “Workhorse” PAs
ST Microelectronics
• A. Larie, et al., IEEE ISSCC 2015.
• 60GHz Class AB/C in 28nm FD-SOI
NC
State
• A. Sarkar, B. Floyd, IEEE T-MTT 2017.
• 28GHz Class AB in 130nm SiGe
Qualcomm
& TAMU
• S. Shakib, et al., IEEE ISSCC 2017.
• 28GHz Class AB in 40nm CMOS
KU
Leuven
• D. Zhao, P. Reynaert, IEEE JSSC 2013.
• 60GHz Class AB in 40nm CMOS
UCSD
• A. Agah, et al., IEEE RFIC 2012.
• 45GHz Stacked Class AB in 45nm SOI
UC Berkeley
& Intel
• S. Thyagarajan, A. Niknejad, C. D.
Hull, IEEE TCAS-I 2014.
• 60GHz Class AB in 28nm CMOS
63
A Continuous-Mode F-1 Harmonic Tuning Wideband PA
• Continuous-mode harmonic tuning
• Harmonic load tuning by one on-chip transformer
Exploring and enhancing
transformer parasitics
• Ultra-compact with
0.29mm2 core area
• Global Foundries
0.13μm SiGe
• V. Carrubba, S. Cripps, et al, IEEE EuMC 2011, IMS 2011, and T-MTT 2011.
• S. Mortazavi, K. J. Koh, IEEE ISSCC 2014.
• T. Li, M. Huang, and H. Wang, IEEE ISSCC 2018 and IEEE T-MTT 2019.
64
A 24-42GHz “Large-Signal Linear” Broadband PA
• A broadband on-chip coupler vs. on-chip transformer
Cdev
Idev
D. Chowdhury et al., JSSC, Oct, 2009
PA OUTPUT
G S G
0.3mm
PA Stage VDD
VCAS_PA
VDD_PA
PA INPUT
82fF
473Ω
153µ
/40n
22f
414Ω 462µ
/40n
22f
67f
67f
447µ
/40n
Compensated
distributedbalun output
network
Driver Stage VDD
Interstage
Matching
Network
PA
OUTPUT
Driver Stage
Input Balun
Driver Stage
Interstage
Matching
Network
PA Stage
VCAS_PA
Proposed
Output Network
• F. Wang and H. Wang, IEEE ISSCC 2020.
Inductance (nH)
-4
-20
10
20
Imag(Zin)
Broadband balanced PA load
impedance over 24 ~ 50 GHz
10
20
30
40
Frequency (GHz)
30
G S G
• 45nm SOI CMOS
• 1.35mm2 total area (pad limited)
• Only 0.21mm2 core area
• Ideal for large scaled arrays
-10
30
50
60
40
Frequency (GHz)
50
>86% passive efficiency
over 24 to 42 GHz
80
70
60
10
20
30
40
Frequency (GHz)
150
100
S22
0
-10
50
0
S11
-20
-30
200
25.8 − 43.4GHz S21 BW-3dB
10
20
25
30
-50
S12
35
40
Frequency(GHz)
-30
90
S21
20
60
>90% peak passive efficiency
measurement(solid curves), simulation(dashed curves)
Input Balun
1.375mm
-2
Real(Zin)
-20
0
LP, LS
100
0
Driver Stage VDD
PA INPUT
0
Zin
20
10
SRF=27.2GHz
40
-40
PA Stage
0.7mm
VDD_DR VG_PA
0.979mm
VG_DR
PA Stage VDD
Compensated
Distributed Balun
Output Network
Zin
20
2
-6
Cdev
Cdev
4
S12 (dB)
2 V2
V3 3
Yin Yin
29µm
30
QP,QS
Passive efficiency (%)
Cdev
Idev
𝐼𝐼dev
−𝑗𝑗𝑌𝑌p cot𝜃𝜃 + 𝑗𝑗𝑗𝑗𝐶𝐶dev
=
𝐼𝐼L
𝑗𝑗𝑌𝑌m csc𝜃𝜃
𝑌𝑌m
csc𝜃𝜃 𝑉𝑉dev
𝑗𝑗
2
𝑉𝑉L
−𝑗𝑗𝑌𝑌p cot2𝜃𝜃
Impedance Zin (Ω)
Z0o, Z0e, θ
CL
IL
1 VL
300µm
Coupler Model
RL
DC supply feed
S11, S21, and S22 (dB)
Transformer Model
6
Output parasitic
capacitance is
absorbed into CL
Quality Factor
Output GSG pad
45
50
-100
65
50
60
My “Class-W” PA
• Proposed Class-W Dual-Drive PA: Treating the transistor as a 3-terminal device
Conventional Common-Source Topology
Vin
Vout
Vin
Vknee
Vout
GND
Proposed Dual-Drive
Class-W Power Amplifier Topology
Vout
Vout
Vin
Vin
Vknee
αVin
Vknee
2-Terminal Device
137fF
RFIN
64fF
VGSDR
GND
GND
3-Terminal Device
43fF VDDDR VGSPA
Dual-Drive
Coupling
Network
128µm/
40nm
550Ω
43fF
93fF
Vknee
αVin
VDDPA
268µm/
40nm
Vdd=1.9V
Fc=30GHz
64-QAM
1.5GSymbol/s
Vdd=1.7V
Fc=30GHz
64-QAM
1.5GSymbol/s
Pavg=15.05dBm
PAEavg=30.13%
ACPR=-28.85dBc
rmsEVM=-25.12dB
Pavg=14.33dBm
PAEavg=30.50%
ACPR=-29.30dBc
rmsEVM=-25.12dB
RFOUT
VCAS
Z0o=40Ω
Z0e,=15Ω
θ = 8º
• E. Garay and H. Wang, IEEE ISSCC 2021.
5G NR FR2
200MHz 1-CC
64QAM
Vdd=1.9V
Fc=30GHz
Pavg=11.39dBm
PAEavg=16.98%
ACPR=-26.5dBc
rmsEVM=-25.05dB
93fF
- 23-34GHz
- GFUS 45nm CMOS SOI
- Total area of 1.56mm2
- Core area of 0.21mm2
9.64dB PAPR at 0.01%CCDF
-42.6dBc
-26.5dBc
-28.6dBc
-42.7dBc
5G NR FR2
200MHz 1-CC
64QAM
Vdd=1.7V
Fc=30GHz
Pavg=10.72dBm
PAEavg=17.16%
ACPR=-26.0dBc
rmsEVM=-25.00dB
9.64dB PAPR at 0.01%CCDF
-42.1dBc
-26.0dBc
-28.8dBc
-42.3dBc
66
Limitations of “Class-W” PA
• Major Limitation: Input Impedance ↓  Device Power Gain ↓
 (1) Limiting PAE, (2) Larger Mixer/Driver Output Power ↑, (3) Challenges for
High-Frequency PA Designs
Common-Source vs. “Class-W” Dual-Drive PA @ 28GHz (GF45nm CMOSSOI)
~ 7.5dB Gain Drop
CS PA: OP1dB=14dBm/PAE=57.5%/DE=59.5%
Class-W: OP1dB=15.6dBm/PAE=59.3%/DE=72.4%
• E. Garay and H. Wang, IEEE ISSCC 2021.
67
Limitations of “Class-W” PA
• Major Limitation: Input Impedance ↓  Device Power Gain ↓
 (1) Limiting PAE, (2) Larger Mixer/Driver Output Power ↑, (3) Challenges for
High-Frequency PA Designs
Cascode vs. “Class-W” Dual-Drive PA @ 28GHz (GF45nm CMOSSOI)
~ 8dB Gain Drop
Cascode: OP1dB=16.2dBm/PAE=51.6%/DE=52.2%
Class-W: OP1dB=17.37dBm/PAE=54.1%/DE=58.44%
• E. Garay and H. Wang, IEEE ISSCC 2021.
68
Boosting Mm-Wave Silicon PA Output Power
• Stack-transistor PAs
• K. Datta, H. Hashemi, IEEE JSSC 2014.
• 130nm SiGe (BVCEO=1.7V, BVCBO=5.9V)
• 2-Stack Class-E @ 41GHz: Psat 23.4dBm,
Peak PAE 31-34.9%.
• Larger output Vswing
• Larger Zopt and simpler
Z-transformation
• High power density,
Pout, and PAE
• A. Chakrabarti and H. Krishnaswamy,
IEEE T-MTT 2014.
• 45nm CMOS SOI (nominal VDD=~1V)
• 2-Stack Class-E @ 47GHz: Psat
17.6dBm, Peak PAE 34.6%.
• H. Dabag, B. Hanafi, F. Golcuk, A. Agah, J. F.
Buckwalter, and P. M. Asbeck, IEEE T-MTT 2013.
• 45nm CMOS SOI (nominal VDD=~1V)
• 2-Stack/3-Stack/4-Stack Class-AB PA @ 4553GHz with 14.6/18.5/20.5dBm Psat and
32.7%/26.3%/25.1% peak PAE
69
Boosting Mm-Wave Silicon PA Output Power
• World-First 60GHz 1-Watt CMOS PA with Cascaded Asymmetric DAT
3dB Bandwidth
10
S21
0
S22
-10
30
29
25
28
20
27
15
25
-30
24
45
50
55
60
Frequency (GHz)
65
Psat
PAE
26
-20
52
54
56
58
60
10
5
62
Frequency (GHz)
66
64-QAM
Average Pout = 22.5dBm, Average PAE = 5.9%
EVM = -23.6 dB, SNR = 21.1dB
Average Pout = 20.9dBm, Average PAE = 4.3%
EVM = -27.1dB, SNR = 23.3dB
2Gsym/s 12Gb/s
2Gsym/s 8Gb/s
-27.7dBc
ACPR
-28.3dBc
ACPR
-29.3dBc
ACPR
-31.1dBc
ACPR
• Single-ended input/output
• H. Nguyen. D. Jung, and H. Wang, IEEE ISSCC 2019.
64
16-QAM
• 3×2.2mm2 active area
(GlobalFoundries 45nm
CMOS SOI)
• VDDPA = 2V, VDDDR = 1V
S11
Psat (dBm)
20
30
70
0
PAE (%)
S21, S11,S22 (dB)
30
Recently Reported Doherty PAs in Silicon
UCSD
• A. Agah, et al., IEEE JSSC 2013.
• 45GHz Doherty PA in 45nm FD-SOI
• Active phase-shift for auxiliary path
• Stacked transistor PA core
UCSD
• N. Rostomyan, et al., IEEE
MWCL 2018.
• 28GHz Doherty PA in 45nm
CMOS SOI
• Low loss Doherty power
combiner
KU Leuven
• E. Kaymaksut, D. Zhao, P. Reynaert,
IEEE T-MTT 2015.
• 72GHz Doherty PA in 40nm CMOS
• XFMR series Doherty combiner
Chalmers
University
• M. Özen, et al., IEEE MWCL 2017.
• 20GHz Doherty PA in 130nm SiGe
• Low loss Doherty power combiner
Princeton
• C. Chappidi, X. Wu, K.
Sengupta, IEEE JSSC 2018.
• 30-50GHz Doherty-like PA in
130nm SiGe
• RF power DAC • Multi-port
network
71
Recently Reported Outphasing PAs in Silicon
KU Leuven
• D. Zhao, S. Kulkarni, and P.
Reynaert, IEEE JSSC 2012.
• 60GHz transformer-based
outphasing transmitter in 40m
CMOS.
• 15.6dBm Psat
Georgia Tech
• S. Li, M. Huang, D. Jung, T.
-Y. Huang, and H. Wang,
IEEE ISSCC 2020.
• 28GHz Inverse Outphasing
PA in 45nm CMOS SOI
• 22.7dBm Psat
UCSB
UCSD/UCSB
• B. Rabet and P. Asbeck,
IEEE ISSCC 2018.
• 28GHz Outphasing PA with
triaxial balun in 130nm SiGe.
• 23dBm Psat
• K. Ning and J. F. Buckwalter, et al.,
IEEE JSSC 2020.
• 30GHz current mode outphasing
PA in 45nm CMOS SOI.
• 17dBm Psat
UCSD
• B. Rabet and P. Asbeck, IEEE JSSC
2020.
• 28GHz Single-Input Linear Chireix
(SILC) PA in 130nm SiGe.
• 19dBm Psat
• GaN Outphasing PAs and transmitters from
Chalmers, CU Boulder, OSU, Mitsubishi (MERL).
72
Mm-Wave Doherty Power Amplifiers in Silicon for 5G MIMO
• World-first mm-Wave Doherty PA in SiGe for multi-band 28/37/39GHz 5G MIMO
• Band reconfiguration by Main/Auxiliary amplifiers.
km1
VM
Main
I
PA M
km2
VM
C1
CP1
LP1
LS1
CS1
RL
CS2
LS2
LP2
−C1
Transformer
impedance inverter
Capacitive
impedance inverter
CP2
IA
Aux
PA
Transformer
impedance inverter
• S. Hu, F. Wang, and H.
Wang, IEEE ISSCC 2017
and JSSC 2019.
73
Mm-Wave Doherty Power Amplifiers in Silicon for 5G MIMO
• A 24-to-30GHz Watt-Level Broadband Linear Doherty PA
• Output matching network: Doherty + DAT + Balun
Aux2
Main4 Main2
Aux4
Aux2 Aux4
Aux1
Aux3
Main3 Main1
Main PA VDD2
Transformer
balun
PA input
Aux1 Aux3
Quadrature
hybrid
RC pairs
driver stage
Interstage
matching
RC pairs
PA stage
Aux PA VDD2
Transformer
balun
RC pairs
PA stage
Interstage
matching
RC pairs
driver stage
744μm
55fF
32fF
Transformer
balun
2x6x8μm
55fF
32fF
32fF
Driver
stage
Interstage
matching
2x6x8μm
32fF
55fF
2x6x8μm
2x2x12μm
2x6x8μm
PA stage
32fF
55fF
2x6x8μm
55fF
Transformer
balun
PA
output
55fF
32fF
2x2x12μm
2x6x8μm
55fF
32fF
55fF
2x6x8μm
2x2x12μm
Multi-primary
DAT Doherty
output
network
55fF
2x6x8μm
2x2x12μm
Transformer
balun
PA output
Wilkinson
power divider
50Ω transmission line
744μm
Quadrature hybrid
• Globalfoundries 130nm SiGe BiCMOS
• 1.35mm2 core area
• Double layer Aluminum PCB for
thermal conductivity
Differential output
50Ω transmission line
1.38mm
Main1
2.30mm
Main3
Wilkinson
power divider
Multi-primary distributed
active transformer (DAT)
Doherty output network
32fF
55fF
PA stage
Interstage
matching
Driver
stage
0.98mm
• F. Wang and H. Wang, IEEE ISSCC 2020.
Main PA VDD1
Quadrature
hybrid
1.82mm
50Ω transmission line Quadrature hybrid
504μm
Custom MOM cap
PA input
504μm
50Ω transmission line
Center tap and DC supply feed
Main2
372μm
Main4
Aux PA VDD1
74
Transformer
balun
Doherty PAs for High Mm-Wave Frequency
• A Coupler-Based Differential 60GHz Doherty Power Amplifier with IIB and ISB
• Global Foundries
45nm CMOS SOI
• H. Nguyen and H. Wang, IEEE RFIC 2019 and IEEE JSSC 2020.
75
A Continuous Mode Coupler Balun Doherty PA
• Load modulated balanced amplifier (LMBA)
90° coupler
[D. Shepphard MWCL16]
Broadband active load modulation
Single-ended PA operation
Unequal power dividing  further gain compression
Non-ideal coupling factor  possible negative impedance
76
A Continuous Mode Coupler Balun Doherty PA
• A Continuous-Mode Coupler Balun Doherty PA
I2
λ/4
λ/4
Coupling Factor = 1 2
jIa
A Balun
Coupler!
Un-Balanced
I1
Balanced Im
V1
V2
V3
Z0
I3
3
Z0
Impedance(Ω)
2
1
0
j
j
-j
0
0
-j
0
0
Broadband active load modulation
200
150
100
50
2
Im
Z0
P1 = P2 =
2
Z1
2Z0
Z2
Z0
0
Z0/2
Ia=0
Ia=Im/2
Active Load Modulation
Ia
j
(
1)
Z
Z
Z
Z
V1
I1
0
0
1
0
Im
j Z0 0
V2
I2
Im
,
Ia 0 2
Series Doherty
Port3 is Terminated
with Z0
I1
I2
I3
Differential PA operation
Equal power dividing  No theoretical gain compression
• T. Huang, N. Mannem, D. Jung, and H. Wang, ISSCC
77
2021 and IMS 2021 (Best Student Paper Award).
A Continuous Mode Coupler Balun Doherty PA
• A Continuous-Mode Coupler Balun Doherty PA
25
20
15
20
15
10
15
5
10
x1.15
26GHz (Mode2)
Inter-Stage Network
Driver stage
1200µm
950µm
Input Network
Adaptive Bias
Quadrature Coupler
0
RF_In
4
6
1900µm
25
PGain(dB)
10
Input
Balun
Interstage
Matching
VDD = 1V
Driver
Stage
PA
Input
2V
Z0 = 40Ω
θ = 30°@50GHz
Output
Stage
10pH
2V
Vin+
Vout+
PA Output
Z0e_1 = 129Ω =30°@40GHz
Z0o_1 = 22Ω θ1
2x43µ/40n
0
Vgs_pa
CMOS
Vgs_dr
50
Vin
Driver Stage
37fF
37fF
Vin
2x43µ/40n
Adaptive biasing BW
> 5GHz for ×3~×5
modulation BW
42.5GHz (Mode1)
5
SiGe
7
9 11 13 15 17 19 21 23
30
25
20
20
15
20
10
15
10
5
5
0
x1.2
10
60GHz (Mode2)
Psat/OP1dB=19.9/19.2dBm
PAEmax/PAEOP1dB=24.7/23.9%
PAE@OP1dB-6dB=14.8%
4
6
8 10 12 14 16 18 20 22
Pout(dBm)
PAE_OP1dB-6dB
20
0
Chappidi,
JSSC2018
5
10
15
20
25
30
35
40
45
Frequency(GHz)
50
25
9 11 13 15 17 19 21 23
Chappidi,
JSSC2017
10
30
32.5GHz (Mode1) 20
Comparison with
SOA Broadband PA
Li,
TMTT2019
30
7
35
Pout(dBm)
Pout(dBm)
PAE_OP1dB
5
40
25
15
x1.44
This work
40
VB = 0.1V
Vout
8x25µ/40n
Vin+
Adaptive Biasing VD = 0.3V
Vin 43µ/40n
8x43µ/40n
2V
Adaptive Biasing
Vcas
60fF 60fF
Vout
PAE(%)
Input
Coupler
Output
Stage
10pH
8x43µ/40n
VD = 0.3V
Driver
Stage
Vout+
VDD
Z0e = 120.7Ω θ=90°@50GHz
Z0o = 20.7Ω
VDD = 1V
Z0e_2 = 85Ω
Z0o_2 = 9Ω θ2=30°@40GHz
2V
VD = 0.5V
Proposed Output Network
Adaptive Biasing
0
PAE(%)
15
5
Output Stage
Pout(dBm)
(
)
x1.62
5
5
Psat/OP1dB=21.8/20.7dBm
PAEmax/PAEOP1dB=27.1/26.3%
PAE@OP1dB-6dB=19.5%
20
10
45
55
60
30
25
PAE(%)
• T. Huang, N. Mannem, D. Jung,
and H. Wang, ISSCC 2021 and IMS
2021 (Best Student Paper Award).
8 10 12 14 16 18 20 22
PAE(%)
Power Stage
PGain(dB)
20
Output Network
Psat/OP1dB=22/21.5dBm
PAEmax/PAEOP1dB=40.5/39.9%
PAE@OP1dB-6dB=32.8%
PGain(dB)
RF_out
650µm
PGain(dB)
25
Psat/OP1dB=20.8/18.3dBm
PAEmax/PAEOP1dB=23.3/20.4%
PAE@OP1dB-6dB=13.4%
PAE(%)
30
25
65
70
78
5
Mixed-Signal Doherty PAs at Mm-Wave
• Main Analog PA + Auxiliary Digital PA  Optimum Control + Super-Resolution
• Small input envelopes: Analog Regime
 No quantization error or LSB
• Large input envelopes: Mixed-Signal Regime
 Quasi FOH+ Non-uniform quantization
λ/4
Analog
PA
Input
Output
Aux PA path
1
2
N-1
Sub-PA
2
Sub-PA
Sub-PA
Bit0
Bit1
All Aux sub-PAs A<0>
BitN
A<1>
are turned off
A<N>
λ/4
envelopes
λ/4
Analog
PA
Input
Aux PA path
1
2
N-1
Sub-PA
2
Sub-PA
Sub-PA
Bit0
Bit1
Appropriate weightings of A<0>
BitN
Aux sub-PAs are
A<1>
A<N>
dynamically turned on
λ/4
RL
(50Ω)
Output
RL
(50Ω)
• F. Wang, T. Li, and H. Wang, IEEE ISSCC 2019 and IEEE JSSC 2019.
79
Mm-Wave + Signal Processing: Mixed-Signal Doherty PA
• Mixed-Signal Doherty PA (Only 3 Bits) ― Super-Res. Mm-Wave Digital PA
• Reconfigurable Back-Off
Quantization Error
1
-4
-6
-8
MSDPA AM-AM by gradually turning
on optimum Aux PA digital settings
MSDPA AM-AM by various
fixed Aux PA digital settings
Analog Regime
Mixed-Signal
Regime
0
0.4dB
-1
-2
Pout(dBm)
50
AM-PM<5°
MSDPA AM-PM by various
fixed Aux PA digital settings
Mixed-Signal
Analog Regime
Regime
Pout(dBm)
(c)
40
PAE(%)
AM-PM(°)
MSDPA AM-PM by gradually turning
on optimum Aux PA digital settings
30
20
10
𝝐𝝐𝟐𝟐𝑸𝑸 � 𝒑𝒑 𝝐𝝐𝑸𝑸 𝒅𝒅𝝐𝝐𝑸𝑸
0
-1
Turning-on points for Aux sub-PAs
with binary weightings.
Analog Regime
Mixed-Signal Regime
Pout(dBm)
(a)
−∞
1
Q
-2
AM-AM(dB)
AM-AM(dB)
0
𝑷𝑷𝑸𝑸 = �
Zoom-In MSDPA AM-AM response
3000
Histogram
2
+∞
2000
0
0.2
0.4
0.6
0.2
0.4
0.6
0.8
1
0.8
1
1GSym/s 64QAM
1000
0
(b)
0
Normalized amplitude (linear scale)
MSDPA PAE by gradually turning on
optimum Aux PA digital settings
1.9× PAE
enhancement
MSDPA PAE by various fixed
Aux PA digital settings
Normalized Class-B
PAE curve from P1dB
Analog Regime
Pout(dBm)
(d)
Mixed-Signal
Regime
80
A 28GHz Mixed-Signal Doherty PA in 45nm CMOS SOI
• Only 3-bit Auxiliary PA controls
• Small-Signal and Large-Signal CW Measurements at 28GHz
76.6µ
238µ
20
Aux PA digital controls
238µ
A<2>
RF
OUTPUT
A<1>
A<0>
CLK
SW
50Ω
1
Aux path
2
4
76.6µ
50Ω
76.6µ
25f
34µ
25f
34µ
11f
D
Q CLK
D
Q CLK
34µ
11f
85µ
34µ
4
2
D
Q CLK
1
Digital interface
S12
S12
S21
S21
16
14
(000): All the Aux
sub-PAs turned off
12
S22
S22
0
5
10
15
Pout (dBm)
21.30−39.46GHz S11 <−10dB bandwidth
-40
-20
-60
-40
20
40
30
20
MSDPA power gain
20
24
26
28
30
32
Frequency(GHz)
34
36
38
-80
40
0
20
(111): All the Aux
sub-PAs turned on
5
10
• F. Wang, T. Li, and H. Wang, IEEE ISSCC 2019 and IEEE JSSC 2019.
10
50
P1dB
(c)
25
20
20
35
Peak PAE
40
<0.4dB
15
Pout
out (dBm)
15
Pout (dBm)
(b)
Normalized Class-B
PAE curve from P1dB
5
PAE(100)
PAE(100)
PAE(000)
PAE(000)
(000): All the Aux
sub-PAs turned off
30
0
25
10
22
PAE(101)
PAE(101)
PAE(001)
PAE(001)
10
Power gain = 19.1dB
MSDPA PAE
PSAT = 23.3dBm
P1dB = 22.4dBm
Peak PAE = 40%
1.68× PAE
PAE@P1dB = 39.4%
enhancement
PAE@P1dB-6dB = 33.1%
Power Gain (dB) and PAE (%)
Power Gain (dB) and PAE (%)
-20
S12(dB)
S11, S21, and S22(dB)
0
PAE(110)
PAE(110)
PAE(010)
PAE(010)
(a)
20
22.35−34.50GHz S21 3dB bandwidth
40
18
10
S11
S11
50
(111): All the Aux
sub-PAs turned on
PAE (%)
238µ
77f
77f
PAE(111)
PAE(111)
PAE(011)
PAE(011)
Gain(100)
Gain(000)
Peak PAE (%)
238µ
25f
25f
Gain (dB)
76.6µ
50Ω
Gain(101)
Gain(001)
22
Main path
RF
INPUT
Gain(110)
Gain(010)
PSAT
25
30
PSAT
30
20
25
PSAT (dBm)
Gain(111)
Gain(011)
20
22-30GHz PSAT 1dB bandwidth
10
0
15
20
22
24
26
28
30
Frequency (GHz)
(d)
32
34
81
36
10
A 28GHz Mixed-Signal Doherty PA in 45nm CMOS SOI
2.0GSym/s (12Gb/s) 64-QAM without predistortion
2.0GSym/s (12G/s) 64-QAM
2.0GSym/s (12Gb/s) 64-QAM
ACPR_L
=−28.4dBc
Pavg=15.6dBm
PAEavg=27.8%
PDC,digital = 9mW
rms EVM=−24.4dB
EVM = 6.00 %rms
Mag Err = 3.92 %rms
Phase Err = 3.38 deg
MER = 24.4 dB
• F. Wang, T. Li, and H. Wang, IEEE ISSCC 2019 and IEEE JSSC 2019.
• 1G sym/s 64QAM with ×4 oversampling
• Resolution BW = 510 kHz
• Frequency Span = 20 GHz
• ~40dBc OOB floor without DPD
• No major sampling images observed
82
VSWR Challenges for Mm-Wave PAs in Phased Arrays
• The PAs and antenna arrays interact with each other
The array pattern depends on the phase/amplitude of the PA output signals.
The PA load vary with the element position and the beam angle due to element couplings.
Major
Challenges
Keeping linear output power and efficiency over antenna VSWR
2:1~3:1 VSWR at +/−60° beam angle
• C. Fager et al., IEEE Microwave Magazine, 2019.
• P. Asbeck, CICC Educational Session, 2020.
83
Post-Silicon AI + RF: An AI-Assisted Mm-Wave Doherty TX
• Phased array element coupling 
rapid and large beam-dependent
antenna VSWR ~3:1
Zant 50Ω  16.7Ω ~150Ω
Time-varying
Environment (~ms)
With Prof. Justin Romberg (GT ECE)
Change over antenna impedance and carrier frequency
Multi-Armed-Bandit (MAB) and Actor-Critic (AC) Algorithms
MSDPA no
VSWR mismatch
Gain = 14.2dB
PSAT = 24.5dBm
P1dB = 24.2dBm
20
18
Pout (dBm)
F. Wang, K. Xu, J. Romberg, H. Wang, GOMACTech 2019, IEEE IMC-5G 2019.
4.9dB P1dB
improvement
w.o. AI-assisted
Main Reconf
16
14
Pout (dBm)
w. AI-assisted
Main Reconf
PAE at P1dB(%)
Gain = 17.3dB
PSAT = 23.9dBm
P1dB = 21.9dBm
<0.6dB gain ripples
0
90
MSDPA no
VSWR mismatch
50
22
P1dB(dBm)
<0.6dB gain ripples
Power gain(dB)
Power gain(dB)
24
180
∠Γ (°)
270
360
40
w. AI-assisted
Main Reconf
30
7% PAE
improvement
20
10
w.o. AI-assisted
Main Reconf
0
90
180
∠Γ (°)
270
84
360
Pre-Silicon AI + RF: ML for Direct RF/Mm-Wave Synthesis
• Mm-Wave/RF circuits ≈ Analog circuits + EM passives
Existing EM Simulations (Analysis)
Proposed ML EM (Synthesis)
Design Experience/Intuition
Reduce Expert Knowledge “Intuition”;
Rapid Initial Design Synthesis
With Prof. Tuo Zhao (GT ISYE)
Models: Residual Network(RN), Feed-forward network
(FN), Gradient Boosting, Linear Regression.
Input: Target circuit parameters
F(X): HFSS, Sonnet,
Momentum, EMPro…
Residual Network with “shortcut”
• Easier to optimize.
• Better generalization ability
(performance on unseen data).
• Linear Regression/Gradient Boosting
• Neural Networks
Output: 3D EM geometrical parameters
Evaluation: 𝑅𝑅 2 score (how
well the model fits the data).
• D. Munzer, S. Er, M. Chen, Y. Li, N. S. Mannem, T. Zhao, H. Wang, "Residual Network Based Direct Synthesis of EM Structures: A Study
on One-to-One Transformers," IEEE RFIC, Jun. 2020.
85
# of layers
Mm-Wave MIMO Keyless Secured Communication
• Conventional digital encryption/decryption: Complexity, throughput, latency, key exchange 
Wireless physical layer security by asymmetric channels
• Mm-Wave MIMO  Constellation Decomposition Array (CDA)
Conventional
Phased Array
Bob
RX
64QAM
z
1
16QAM
b)
64QAM
1
TX-2
QPSK4
RX
RX
QPSK1
TX-2
QPSK2
TX-3
QPSK4
b) Secure communication of 64QAM signal
using QPSK4, QPSK2 and QPSK1 signals
Bob
QPSK
1
4
15
Eve @ θ˚
0
1
TX-2
Temporal
swapping
-30
0
30
Scan Angle (˚)
1
4
QPSK
2
QPSK QPSK
With Prof. Matthieu Bloch (GT ECE)
1
RX
Bob
Eve @ 10˚
RX
Eve
Bob
TX-2
-60
1
TX-1
2-way CDA
-90
16QAM
Bob
3-way CDA
30
1
TX-1
45
RX
RX
2
CDA + Temporal Swapping
60
EVM (%)
a) Secure communication of 64QAM
signal using 16QAM1 and QPSK4 signals
TX-1
QPSK
4
75
Eve @ θ˚
1
2
90
Bob
1
4
EVM vs Scan Angle
TX-1
c)
1
QPSK
Constellation Decomposition Array (CDA)c)
16QAM1
2
1
Constellation
Decomposition
of QAM signals
EVE
RX
Radiation Pattern:
a)
64QAM
Alice:
60
90
RX
Eve @ 10˚
RX
Improves security by
scrambling symbols
over time
N. S. Mannem, E. Erfani, T.
Huang, S. Li, M. Bloch, H.
Wang, IEEE RFIC 2021 Best
Student Paper Award, IEEE
JSSC 2022.
Mm-Wave MIMO Keyless Secured Communication
• A 25-34GHz 8-channel MIMO Tx with on-chip mismatch detection sensor in 45nm CMOS SOI.
PPF
0.3V
1.1:1
Phase shifter
IFIn,8
LO Wilkinson
Divider 1:8
LO_I+
LO_ILO_Q+
LO_Q-
Broadband IQ
generator
1.25V
VDD = 1V
VDD = 1.8V
LO_Q+
PA
8 TX channels
2
α| |
Buffer
α| |
TX2,Sense =
A2cos(ωt)
Rectifier-1 A1
Buffer
2
TX1,Sense =
A1cos(ωt+ΔΦ)
Rectifier 1-4
AMP1 = α|A1|2
ΔΦ
IN
ISO
85fF 4.25µ/
40n
A1=A2=A
THR
CPL
Rectifier-2 A2 0˚
Rectifier-3
α| |
2
α| |
2
VΔΦ = 2αA2sinΔΦ
TX-1
-1/0
1×
Outn
QPSK4
TX-3
QPSK4
PA OUT
Output Network +
sensor feeds
IF_In
2×
4×
8×
Outp
Outn
Outp
2.4µm/
40nm
-1/0
1×
IF_Qp
16QAM1
TX-2
IF_Ip
Outp
1.2nH
Rectifier-4
AMP2 = α|A2|2
a) 16QAM1
c)
198fF
RFin
+
-
DCout
3-stage/
7-stage
1.8V
b)
2×
4×
8×
IF_Qn
b)
EN_BEN
1×
IQp
EN
EN_B
2.4µm/
40nm
IQn
Outn
2.4µm/
40nm
1.8V
EN
EN_B
2.4µm/
40nm
EN_BEN
-1/0
IQp
Sensor
Evmrms = 6.3%
29.9GHz
IQn
8 element TX
MIMO chip
θ = 2˚
8 element patch
antenna array + routing
100MSym/s
Bottom view
Top view
EVMrms (%)
d)
θ = 7˚
Evmrms = 6.2%
30.1GHz
2.34mm
c)
EVMrms = 13.4%
θ = 0˚ Second Carrier
5.52mm
Phase Shifter
TX-4
θ = 10˚
First Carrier
IQ Mixer
Phase feed
OUT
Zoe = 107Ω
Zoo = 18.9Ω
θ = 30˚ @ 40GHz
174µ/40n
Driver
LO_Q-
Carrier Aggregation + Temporal Swapping
PA
VDD = 2V
1.25V
60fF
30fF
Φ
Q-path
20pH
1:1
LO_I0.3V LO_Q-
IQ Generation
174µ/40n
0.3V
1:8 Wilkinson Power Divider
IFIn,1
IFIn,2
Capacitively coupled sensing
LO_I+
Φ
d)
Amplitude and Phase Mismatch Sensor
16
QPSK_QPSK_QPSK
16QAM_QPSK_16QAM_QPSK
12
Limited by the TX array
SNR and HPBW as well
as RX noise floor
8
4
0
16QAM_16QAM_QPSK_QPSK
64QAM (No CDA)
0
2
4
6
Scan Angle (˚)
8
10
First Carrier
I-path
LO_I-
Second Carrier
Mixer
Mixer
IF amplifier
Amplitude feed
a)
θ = 4˚
θ = 6˚
θ = 8˚
Evmrms = 9.9%
Evmrms = 10.1% Evmrms = 10.8% Evmrms = 10.2%
Evmrms = 9.8%
Evmrms = 10.8% Evmrms = 11.4% Evmrms = 11.2%
N. S. Mannem, E. Erfani, T. Huang, S. Li, M. Bloch, H. Wang, IEEE RFIC 2021 Best Student Paper Award, IEEE JSSC 2022.
Outline
• Background and Motivations
• Power Amplifier Design Considerations
— Active Device Designs
— Passive Network Designs
• Mm-Wave Power Amplifier Architectures and Designs
• Antenna-PA Co-Designs and Examples
— Merging Circuits with Electromagnetics and Radiation
• Conclusion
88
Device Scaling, Speed, and System Size
Conventional Approach
Holistic Approach
Versatile BEOL
• Completely separated levels of abstraction
(devices ― EM/passives ― circuits ― antennas)
• Avoid EM coupling and standardized impedance
Unlimited and
costless transistors
• Exploit devices, circuits and EM co-designs
• Precisely controlled transistors as stimulations/terminations
Paradigm shift in RF/mm-Wave circuits and systems
Can we holistically design devices, circuits, EM structures, and systems?89
Always exploring the next-level of innovations
…No problem can be solved from the same
level of consciousness that created it…
― Albert Einstein (14 March 1879 – 18 April 1955), Nobel Prize Laureate in
Physics in 1921.
90
Merging Electronics with Antennas?
Goal: Intelligently generate, manipulate and receive EM signals. ― Merging
circuits with electromagnetics and radiation.
• Novel hybrid antenna-electronics with
versatile “On-Radiator” functionalities
(1) Signal combining/splitting and filtering
(2) Impedance scaling and V/I amplification
(3) Active load modulation
(4) Noise cancellation
(5) Reconfigurability
• R. King and T. Wu, “The Cylindrical Antenna with Arbitrary Driving Point,” IEEE T-AP, Sept. 1965.
• S. Bowers, A. Hajimiri, “Multi-Port Driven Radiators,” IEEE T-MTT, Dec. 2013.
• H. Wang, T. Chi, H. Nguyen, S. Li, J. Park, et al., IEEE APS/URSI 2016, T-AP 2017, ISSCC 2017, ISSCC 2018, RFIC 2018.
91
Hybrid Antenna-Electronics
Hybrid Antenna-Electronics for New Systems and Functionalities
A 60GHz Linear TX + Multi-Feed
Antenna with +27.9dBm Psat and
+33.1dBm Peak EIRP
ISSCC 2017
A 70GHz Linear TX with OnAntenna Doherty Modulation
A 60GHz 3-Way Linear Doherty
Radiator with Multi-Antenna Coupling
ISSCC 2018, JSSC 2018
ISSCC 2019
1.9mm
Main
A 340GHz THz Pico-Sized µWatt “Invisible”
Radio for IoT or Sub-Dermal Implants
CICC 2017, 2017 CICC Best Conference
Paper Award
0.95mm
VDD
GND
THz TRX
Active Core
TDC
0.6mm
GND
Slot Antenna
Aux 2
Aux 1
-4.8dB coupler
-3dB coupler
Current-Scaling
Antenna
A 28GHz Outphasing Transmitter with
On-Antenna Chireix Load Modulation
RFIC 2018, Best Student Paper Award,
JSSC 2019
Adaptive biasing
circuits
A 64GHz Full-Duplex
Transceiver Front-End with OnChip Multi-Port SIC Antenna
ISSCC 2018, JSSC 2018
A 75-85GHz Antenna-LNA FrontEnd with On-Antenna Noise
Cancellation and Gain Boosting
ISSCC 2020, JSSC 2020
92
Challenge: High-Power High-Efficiency Signal Generation
• Conventional power combining technique I: On-chip or on-package
passive networks
EIRP = Pout + 10logN – Loss + Gant
Single Antenna Footprint
Pout + 10logN – Loss
Passive Power Combining Network
Pout
Pout
Pout
PA #1
PA #2
PA #N
• Lossy passive combiner degrades efficiency, especially for large number of power devices
and high impedance-transformation ratio
93
Challenge: High-Power High-Efficiency Signal Generation
• Conventional power combining technique II: Spatial power combining
by large-scale antenna arrays
Single-Element 0.5λ Dipole
Half-Power Beamwidth = 78º
EIRP = Pout + 20logN + Gant
Single Antenna Footprint
-30
0 0dB
30
-10dB
Pout
PA
-60
60
-20dB
Array Element #1
Array Element #N
• Ideally lossless and 10logN + 10logN EIRP enhancement
• Large antenna panel size
• Narrow antenna beamwidth  complicates Tx/Rx
alignment in dynamic and mobile applications
90
-90
16-Element 0.5λ Dipole Array
Half-Power Beamwidth = 6º
-30
0 0dB
30
-10dB
-60
60
-20dB
-90
90
94
Direct On-Antenna Power Combining
• Multi-feed antenna (MFA) driven by multiple electronic amplifiers
Single-Element 0.5λ Dipole
Half-Power Beamwidth = 78º
Current
Distribution
-30
Single Antenna Footprint
0 0dB
30
-10dB
-60
60
-20dB
PA #1
•
•
•
•
PA #2
PA #N
• T. Chi, H. Wang, et al., AP-S 2016,
T-AP 2017, ISSCC 2017, IMS 2018
-90
Power combining direct on antenna  boost output power
Simplify impedance transformation  increase efficiency
Single antenna footprint  maintain field of view
Employed in an array  further increase EIRP or beam-steering
90
95
Circuit Models/Framework for Multi-Feed Antenna Analysis
• On-antenna series power
combining/dividing
• Solution 1: Multi-feed wire or loop
antennas
• Solution 2: Near-field coupled slot
antennas
• On-antenna parallel power
combining/dividing
• On-antenna transformer for
Z/voltage/current scaling
• Solution 1: Multi-feed slot antennas
• Solution 2: Near-field coupled wire/loop
antennas
• Alter antenna driving impedance
• Perform ideal voltage or current scaling
#N
#1
RN
• S. Li, H. Wang, et al. RFIC 2018 and JSSC 2019.
• B. Abiri and A. Hajimiri, ISSCC 2018.
• T. Chi, H. Wang, et al. ISSCC 2017.
• S. Li, H. Wang, et al. APS 2016, T-AP 2017
• H. Nguyen, H. Wang, et al. ISSCC 2019
96
On-Antenna Power Combining: 60GHz Linear Radiator
• Linear radiator (antenna + 16 PAs) at 60GHz in
Globalfoundries 45nm CMOS SOI
“On-Antenna” Parallel
Combiner Network
GND Plane (Top Aluminum
llel
Layer, Thickness = 2.2µm)
m
ara r
P
3.6e5
.5m
-1 bine
2
o
t
4- om
1.8e5
C
)
º
0
1.8e5
(18
0G
d4
e
0
at 6
e
F
Ω
)
13
(0º
0º)
0
d3
ZL
(18
e
2
e
d
F
e
e
F
º)
a
1 (0
n
d
n
e
te
Fe
An
lot
S
eed
4-F
Power Combining 16 Unit PAs To
Achieve 12dB Pout Enhancement
E-Field
3.6e5
(V/m)
ZL
4-to-1
Combiner Feed 1
Z4feed 4-Feed Slot Antenna
4-to-1
Combiner Feed 2
Rloss
4-to-1
Combiner Feed 3
Zant
4-to-1
Combiner Feed 4
Zoom-In View
2
d
Fee
)
0º
(18
Vias to Connect the
Top GND Plane
Signal Trace (Copper
Layer, Thickness = 1.2µm)
ield
E-F tion
l
a
i
dia
ent
fer or Ra
f
i
D tf
ite
lo
Exc the S
n
O
• T. Chi, H. Wang, et al., AP-S 2016, T-AP 2017, ISSCC 2017, IMS 2018
20µ
m
º)
1 (0
d
Fee
4-to-1 Parallel Combiner
52Ω, 120µm
26Ω, 220µm
13Ω, 370µm
GND Plane (Top
Aluminum Layer)
97
On-Antenna Power Combining: 60GHz Linear Radiator
• 60GHz linear
radiator in 45nm
CMOS SOI
23.4%
14
27.8dBm (TS Psat Based)
21
Meas. Peak EIRP
Psat = Meas. EIRP – Antenna Gain
Psat = Meas. TS Psat + 11.3dB
Meas. PAEmax
7
0
54
56
58
60
Frequency (GHz)
62
14
7
0
64
World record output power
and efficiency
Pout (dBm), Gain (dB)
21
PAEmax (%)
Psat (dBm), Peak EIRP (dBm)
27.9dBm (EIRP Based)
28
28
35
35
Freq. = 59GHz
PPout
out
PG
Gain
28
PAE
PAE
AM-PM
AM-PM
21 17.4dB
P1dB=25dBm
24
18
14
12
5.6º
7
0
-10
30
PAE (%), AM-PM (deg)
33.1dBm at 59GHz
35
-4
2
8
Pin (dBm)
6
14
High linearity
• T. Chi, H. Wang, et al., AP-S 2016, T-AP 2017, ISSCC 2017, IMS 2018
64QAM, Symbol Rate
0.5GSym/s, Data Rate 3Gb/s
Pavg = 20.1dBm
EVM = -27dB
-36.1dBc
20.1dBm
-35.8dBc
0
20
High-speed complex
modulation
98
Active Load Modulation Transmitter Architectures
• Doherty Linear TX Architecture
RFin
Main PA 0º
Vmain
Imain
λ/4
T-Line
λ/4
T-Line
Iaux
Vaux
Aux PA -90º
• Outphasing Nonlinear TX Architecture
PA
RFin1=
Acos(ωt+θ(t)+φ(t))
Zmain
0
VDD
Zaux
RFin2=
Acos(ωt+θ(t)-φ(t))
ZLoad
½ Vmax
Vmax
• B. Kim, et al., IEEE Microwave Magazine, Oct. 2006.
• H. Wang, et al., IEEE Microwave Magazine, Oct. 2015 (Best
Paper Award).
• S. Hu and H. Wang, IEEE ISSCC 2017, IEEE JSSC 2019.
• F. Wang and H. Wang, IEEE ISSCC 2019, IEEE JSSC 2019.
A
Out-Phasing
Network
RFout=
A(t)cos(ωt+θ(t))
A(t)
+φ(t)
-φ(t)
θ(t)
PA
• S. Li and H. Wang, IEEE RFIC 2018 (Best Student
Paper Award), JSSC 2019
• Hongtao Xu, et al., IEEE JSSC 2011.
• T. Barton, et al., IEEE T-MTT 2016.
• Complicated, lossy and narrow-band load modulation networks
99
A
On-Antenna Active Load Modulation: 60GHz Doherty TX
• On-Antenna Series Doherty PA/Transmitter Architecture
Node A
𝑍𝑍𝑜𝑜
Impedance
inverting
network
1
Main
2 I2
I1
Aux
𝑌𝑌
𝑌𝑌 = � 𝑜𝑜
𝑌𝑌𝑜𝑜
°
𝑌𝑌𝑜𝑜 𝑍𝑍𝑜𝑜 /2, 90
�
𝑌𝑌𝑜𝑜
Aux
90°
0° Main
VDD
On-chip
antenna as
a series
combiner
𝑤𝑤ℎ𝑒𝑒𝑒𝑒𝑒𝑒 𝑌𝑌𝑜𝑜 = 1/𝑍𝑍𝑟𝑟𝑟𝑟𝑟𝑟
Node B
𝝀𝝀𝒆𝒆𝒆𝒆𝒆𝒆
2
Node A
Standing-wave current distribution
On-Antenna Doherty Radiator
Impedance
inverting VDD
network
Aux 90°
55Ω,180µm
VDD
• H. T. Nguyen, T. Chi, S. Li, H. Wang, IEEE ISSCC
2018 and IEEE JSSC 2018.
𝑌𝑌𝑜𝑜
�
𝑌𝑌𝑜𝑜
1
I1
(𝑌𝑌𝑜𝑜 = 1/𝑍𝑍𝑜𝑜 )
VDD
Node A
𝑌𝑌𝑜𝑜
𝑌𝑌𝑜𝑜
EM structure
& near field
I2
Node B
0° Main
𝑌𝑌 = �
Far-field radiation
J(x,y)ejΩ(x,y)
Dual-feed loop antenna =
Radiator + Differential
series combiner
On-Antenna Active Load Modulation: 60GHz Doherty TX
• Large-signal CW testing
• Modulation testing
• +18.8 dBm OP1dB, 24% PAE 0dB PBO
and 18.3% PAE 6dB PBO
• Doherty signal conditioning on antenna
before radiation
• World-record 1.45-1.53 × PAE over
class-B at 6dB PBO at 62-68GHz
Carrier Frequency = 63GHz
Main PA
only
PG
30
PAE
25
Main
Aux1
• Undistorted over full FoV unlike spatial
I/Q TX (UC Berkeley, A. M. Niknejad) and
spatial outphasing TX (UCLA, B. Razavi)
Main + Aux
PA
E-plane
I
V
I
V
(N-2)V
Aux(N-3)
V
Aux(N-2)
I
IV
1:1 I
3V
2V
1:2
6
8
10 12 14 16 18 20
Pout (dBm)
EVM (dB)
-30
E-plane EVM
-60 -45 -30 -15
0
15
E-plane angle (deg)
30
45
60
NZopt
I (N-1)V
1:(N-1)
1:(N-2)
PAEmax
Theoretical PAE curve
20Log(N)
Power Back-Off (dB) 0
-20
-30
H-plane EVM
-60 -45 -30 -15
0
15
1.9mm
30
H-plane Angle (deg)
45
60
-3dB coupler
• H. T. Nguyen, T. Chi, S. Li, H. Wang, IEEE ISSCC 2018, IEEE JSSC 2018, IEEE ISSCC 2019.
Current-Scaling
Antenna
Aux 2
4
P1dB
-20
Power Back-Off (dB) 0
NV
-10
Aux 1
2
6dB PBO
-10
Main
3.04 ×
over class A
5
EVM (dB)
10
0
I
• Aux PAs turn-on in sequences
1,2,3,…, N-1.
• Drawing of current/voltage
magnitude at 0dB PBO
• Design values for equalweighting Main/Aux. PAs
Efficiency
1.52 ×
over class B
15
I (N-2)V
V
PA output currents
Imax
(N-1)V
Z , λ/4 (N-1)I
1:1 opt
Zopt, λ/4 (N-2)I
I Zopt, λ/4 2I
V
V
Aux(N-1)
H-plane
1:1
V
DE_PA
20
0
Proposed General N-way Doherty PA architecture
-4.8dB coupler
PG(dB), DE_PA(%),PAE(%)
35
• High-Order Doherty TX
Adaptive biasing
circuits
101
On-Antenna Active Load Modulation: 28GHz Outphasing TX
Dual-feed loop antenna = Radiator +
Outphasing TX Combiner
Psat ηD(PA) = 56%, 6dB PBO ηD(PA) = 38%
ηD(PA)
DE_PA
Class-A
Drain Efficiency
60%
50%
Class-B
AM-PM
AM_PM
5
1.36×
over Class-B
40%
0
30%
20%
-5
10%
0%
2.72×
over Class-A
0
3
6
9
12
Pout (dBm)
64-QAM 6Gbit/s
10
6dB PBO
AM-PM (°)
70%
64QAM 6Gbit/s and 15Gbit/s
15
18
2.5GSym/s
-28.01dBc
-10
102
• S. Li, H. Wang, IEEE RFIC 2018 and JSSC 2019. ― RFIC Best Student Paper Award
On-Antenna Noise Canceling and Gm Boosting: 80GHz RX
• Multi-feed slot antenna
as a low-loss transformer
On-Antenna
Noise Cancellation
Conventional Noise-Canceling Architecture
VDD
VDD
R1
Vb1 ●
Vout
Vn1
M1
Vsignal
Rs
●
Proposed On-Antenna Noise-Canceling Scheme
1:k
R2
Vn1
●
Vb1
Vout
...
M1
...
M2
L=0.5λ
Incident planewave signal
M2
Signal
Noise
Signal/noise
voltage distribution
On-Antenna
Gm Boosting
103
On-Antenna Noise Canceling and Gm Boosting: 80GHz RX
current density
• Applications: E-band MIMO backhaul, car radars, etc. (sensitivity,Surface
linearity,
& bandwidth)
At 79GHz
0
0
0
30
03
60
4-
8-
06
21-
61-
0
-4
-8
-12
-16
30
60
90
09
90
120
021
051
150
EVMRMS/-SNR/-MER (dB)
180
• S. Li, H. Wang, et al., IEEE ISSCC 2020, JSSC 2020 (invited special issue).
-20
Over-the-air modulation test
at 80GHz fcarrier
-22
-24
16QAM
64QAM
-26
-28
256QAM
3
6
9
12
15
Modulation Bandwith (Gbit/s)
104
18
On-Antenna Full-Duplex: World-First 60GHz Polarization
Duplex TRX + Chip-to-Chip Demonstration
• Globalfoundries 45nm CMOS SOI
• No digital pre-distortion (DPD),
channel equalization, or digital
cancellation
• T. Chi, J. Park, S. Li, and H. Wang,
IEEE ISSCC 2018, JSSC 2018.
105
105
THz Nano-Sized Micro-Watt “Invisible” Sensor Nodes
• THz for drastic antenna and form-factor reduction 
“Invisible” Sensor Nodes for massive sensor
network, micro-robots, sub-dermal implants, IoT
• 300GHz bidirectional regenerative radio + multi-feed
antenna: World-record 4.4Mb/s over 50cm at 30mW
4.4Mb/s and 50cm, Total TRX Peak PDC = 49.3mW
26.4
650
TX/RX Distance = 50cm
10-2
0
10-3
30
10-4
24
-5
18
-6
12
10
10
• T. Chi, M Huang, and H. Wang, CICC 2017 ― 2017 IEEE CICC Conference
Best Paper Award (Top 1 paper among all the paper categories).
36
10-7
6
-8
10
1
2
BER < 10-7
3
4
Data Rate (Mb/s)
5
0
Data Rate = 4Mb/s
10-2
10-3
10-4
10-5
10-6
18.2mW
1300
a
Dat
18.7
mW
Ra
TX Peak PDC =
)
Jsurf (A/m)
/s)
17.1mW
Feed2
cm
5
(Mb
11.6mW
Feed1
40
TX Peak PDC =
GND Plane
Current Null
BER
TDC
Current Null
50
1Mb/s and 17cm, Total
4
-7
3
TRX Peak PDC = 18.7mW
RX
10
Dis
30
<
2
R
tan
E
tB
ce
20
1
(
te a
TX/
BER
GND
GND
10
0.6mm
THz TRX
Active Core
20
4mW
Slot Antenna
34.0
TX Peak PDC = 15.
Bypass
Caps
Minimum RX PDC (mW)
VDD Plane
30
TX Peak PDC =
)
Total TRX Peak PDC (mW
Bypass
Caps
41.7
40
0.95mm
VDD
49.3
50
10-7
10-8
0
10
BER < 10-7
20
30
40
TX/RX Distance
106(cm)
50
60
Outline
• Background and Motivations
• Power Amplifier Design Considerations
— Active Device Designs
— Passive Network Designs
• Mm-Wave Power Amplifier Architectures and Designs
• Antenna-PA Co-Designs and Examples
— Merging Circuits with Electromagnetics and Radiation
• Conclusion
107
Conclusion
• Power amplifiers (PAs) are the key building blocks for wireless systems.
• PA design fundamentals
Active device design, large-signal operation, and linearity
Passive network design
• Mm-Wave PA architectures and designs: back-off efficient PAs, stacked PAs,
AI + PA, security, and more…
• Antenna-PA co-designs
Thank you!
108