SAME 2012
Conference
Session 4 : Packaging Solutions
Technology details on TSV solutions and its
practical use in CERN’s ATLAS experiment
Torsten Krause-Dukart, EquipIC
Motivation to look at TSV ..
Its potential for some disruptive innovations and ability
to overcome classic, padring based die connections
TSV allows 10-100x faster inter-die signal frequencies
(the usual 2x 2-3pF pad pin-cap + signal routing to padring is overcome)
TSV allows new product designs & architectures
Its use in silicon interposers (low warpage, thermal)
Main driver for 2D scaling is dead (unit costs), not the
growth of functional complexity & performance
EquipIC engagement in multiple SIP projects (F, D, BR)
CPPM collaboration with Global Foundries & Tezzaron
Session Title P 2
Session Title P 3
Challenges on the way ahead ..
Manufacturing yield (esp. bonding)
EDA flow for multi active layer (true 3D place & route,
verification like IR-drop etc), press release Cadence ..
DFT before/after bonding
Cost still high, optimizations
only started, e.g. multiple
layer/wafer (right) approach
Thermal (stack heats quickly
up to hottest component)
Session Title P 4
Detail & origin of TSV
TSV are unisotropic etched holes in
silicon (s. beam / plasma enhanced
chemical etching with SiO2 masks)
Pict.: 150nm, 3um deep after 4:21min
(obviously you can have many of them ..)
Long known as trench isolation or trench capacitance
used in embedded DRAM, also often used in MEMS
Other applications in MEMS, silicon interposers (2.5D
packaging) and for true 3D packaging
Div. options in 3D flow: via-first / via-last processing,
many bond-technlogies and wafer-2-wafer / die-2-wafer
Session Title P 5
Wafer vs. diedie-level bonding
Wafer-2-Wafer
Wafer level bonding is fast & low cost (all die at once)
Naturally done at foundry site (experts in wafer handling)
BUT, both die MUST have same size!
Yield issue ! (both die lost, if one doesn’t work)
Die-2-Wafer
Naturally done by assembly/packaging houses
Allows different technologies/foundries per die (e.g. 55nm memory
process, fast 130nm SiGe analog, dense 22nm digital CPU-die)
Better yield aspects, but much slower => more expensive
Session Title P 6
Patrick Pangaud - CPPM-IN2P3-CNRS
3-D integration
integration:: Via First Approach
Through silicon Via formation is done either before or
after CMOS devices (Front End of Line) processing
Form vias before transistors
IBM, NEC,
Elpida, OKI,
Tohoku, DALSA….
Tezzaron, Ziptronix
Chartered, TSMC,
RPI, IMEC……..
Form transistors before vias
Session Title P 7
Patrick Pangaud - CPPM-IN2P3-CNRS
3-D integration
integration:: Via Last Approach
Via last approach occurs after wafer fabrication and
either before or after wafer bonding
Zycube, IZM,
Infineon, ASET…
Samsung, IBM,
MIT LL, RTI,
RPI….
Notes: Vias take space away from all metal layers! The assembly process
is streamlined if you don’t use a carrier wafer.
Session Title P 8
Patrick Pangaud - CPPM-IN2P3-CNRS
3-D methods
methods:: Bonding Choices
1) Bonding between Die/Wafers
a) Adhesive bond
Polymer
(BCB)
SiO2
bond
b) Oxide bond (SiO2 to SiO2)
c) CuSn Eutectic
Sn
Cu
d) Cu thermocompression
Cu3Sn
(eutectic bond)
Cu
bond
Cu
e) DBI (Direct Bond Interconnect)
Metal
Oxide
bond
Metal bond
For (a) and (b), electrical connections between layers are
formed after bonding. For (c), (d), and (e), the electrical
and mechanical bonds are formed at the same time.
Session Title P 9
Patrick Pangaud - CPPM-IN2P3-CNRS
The LHCLHC-ATLAS experiment at CERN
First beam during fall of 2008
LHC is designed
to collide up to
1011 protons at a
rate of 40M/sec to
provide 14 TeV
proton-proton
collisions.
LHC also collides
heavy ions (A), in
particular Lead
nuclei, at 5.5 TeV
per nucleon pair.
Session Title P 10
Patrick Pangaud - CPPM-IN2P3-CNRS
Inner Tracking ATLAS detector (1)
Session Title P 11
Patrick Pangaud - CPPM-IN2P3-CNRS
Inner Tracking ATLAS detector (2)
Straw tubes
Silicon strip
Silicon pixel
Session Title P 12
Patrick Pangaud - CPPM-IN2P3-CNRS
ATLAS Silicon Pixel detector (1)
Session Title P 13
Patrick Pangaud - CPPM-IN2P3-CNRS
ATLAS Silicon Pixel detector (2)
Session Title P 14
Patrick Pangaud - CPPM-IN2P3-CNRS
ATLAS Silicon Pixel detector (3), today
Read-Out electronic:
50µm * 400 µm pixel size (FEI-3 circuit : IBM 0.25 µm)
Collaboration institutes
Bonn University, Germany ; LBNL, USA ; CPPM, France (in the initial stages)
Like a big camera with a 1.7 m2 area and 86 Million of Pixels
with a snapshot every 25ns
Session Title P 15
Patrick Pangaud - CPPM-IN2P3-CNRS
Hybrid Pixels Detector for particles trackers
An early 3-D approach!!
–
–
–
–
Sensors (Si, CdTe, GaAs,
Diamond…) for ionizing particles
Electronic pixel readout
Monolithic device
Analog detection (low noise, low power)
Discriminator
Digital readout
Session Title P 16
Sensor for particles detection
Dedicated electronic chip
AND
A bump-bonding solder for
interconnection
Patrick Pangaud - CPPM-IN2P3-CNRS
LHC and ATLAS upgrades
∫ L dt
Possible upgrade timeline
→ 5x1034cm-2s-1
luminosity leveling
→14 TeV
7 TeV
1x1034 →
~2x1034cm-2s-1
3000 fb-1
phase-2
→ 1x1034cm-2s-1
1027 →
2x1033cm-2s-1
~300 fb-1
phase-1
~50 fb-1
phase-0
~10 fb-1
2013/14
Now
Session Title P 17
T. Kawamoto, TIPP2011, Chicago, USA
2018
~2022
Year
Patrick Pangaud - CPPM-IN2P3-CNRS
Motivations for readread-out chip upgrades
Phases 1 and 2
Decrease pixel size
50 µm
Improve spatial resolution
Deal with an increasing counting rate
FEFE-I3 ,
250 nm
(2008)
400 µm
FEFE-I4 ,
130nm
(2013)
25 µm
250 µm
Vertical stacking
50 µm
50 µm
Technology shrinking
FEFE-x5 ,
65nm
ANALOG
DIGITAL
FEFE-TC4 ,
130 nm
(2018)
125 µm
100 µm
First MPW run for High Energy Physics organized by
FNAL with a consortium of 15 institutes.
The proposed 3-D process combines :
GLOBAL FOUNDRY 130nm technology
TEZZARON 3D technology
Session Title P 18
3-D benefits :
Pixel size reduction
Functionalities splitting
Technologies mixing
Patrick Pangaud - CPPM-IN2P3-CNRS
GF--Tezzaron 3-D technology
GF
Main characteristics :
2 wafers (tier 1 and tier 2) are
stacked face to face with Cu-Cu
thermo-compression bonding
10µm
Via Middle technology :
Super-Contacts (Through
Silicon contacts) are formed
before BEOL (backend layers) of
Globalfoundries (GF) technology.
5µm
Wafer to wafer bonding
M6
GF 130nm technology limited to
5 metal levels
1.2µm
12µm
2.5µm m in
One tier
Session Title P 19
Bond
Interface
M5
M4
M3
M2
M1
Wafer is thinned to access
Super-Contacts
Back-side metal for bonding
(after thinning)
Bond interface
layout
Super Contact
Patrick Pangaud - CPPM-IN2P3-CNRS
3D solution & Detector long term plan
• Tezzaron design 3D solution
• Considered integration of sensor
chip and smaller 65nm technology
(pitch size of 25µm x 80 µm)
M6
M6
M5
M4
M3
M2
M1
Super Contact
Session Title P 20
Digital tier
Tier 1
(thinned
thinned wafer)
M1
M2
M3
M4
M5
Back Side Metal
M1
M2
M3
M4
M5
Bond Interface
M6
M6
M5
M4
M3
M2
M1
Analogl tier
Tier 2
Super Contact
Tier 1
(thinned
thinned wafer)
Back Side Metal
HV sensor
Bond Interface
Tier 2
sensor
Advantages of sensor integration
no need for sensor and bump-bonding,
small HV CMOS sub-pixel pitch,
radiation hardness and rapidity,
DC transmission of signals from analog tier to digital tier by
surface contacts (signals smaller than in AC connection),
flexibility to put DACs and other service blocks on digital tier
and using surface connection to analog tier,
use of TSVs for one side wire bond connection.
Pitch size of 25µm x 80 µm could be in reach
Session Title P 21