NMJ20503
DIGITAL ELECTRONIC II
Revision
Digital Design Concepts
Analog signal
• An analog signal has continuous values.
• Most signal are analog by nature.
• Examples of analog signals are temperature, voltage,
current, pressure and sound.
Figure 1: Analog signal
Digital signal
• A digital signal has a discrete set of values.
• Computers and microcontrollers operate on digital signal.
Figure 2: Example of a digital signal
Ideal digital pulse
• A digital pulse has two edges: a leading edge that occurs first at
time t0 and a trailing edge that occurs last at time t1.
• For a positive-going pulse, the leading edge is a rising edge, and
the trailing edge is a falling edge.
• The pulses in FIGURE 5 are ideal because the rising and falling
edges are assumed to change in zero time (instantaneously).
FIGURE 5: Positive- and negative-going pulses
Non-ideal digital pulse
• In practice, transitions on the pulse edges do not instantaneously.
• FIGURE 6 shows the characteristics of an non-ideal digital pulse.
• The overshoot and ringing are sometimes produced by stray
inductive and capacitive effects. The droop can be caused by stray
capacitive and circuit resistance that forms an RC circuit with a low
time constant.
FIGURE 6: Non-ideal
pulse characteristics
Non-ideal digital pulse
rise time (tr)
• time required for a pulse to go from its LOW level to its HIGH level
• commonly measured from 10% of the pulse amplitude (height from baseline) to 90% of the pulse amplitude
fall time (tf)
• time required for transition from HIGH level
to LOW level
• commonly measured from 90% to 10% of
the pulse amplitude
Bottom 10% and top 10% of the pulse are not
included in the rise and fall times because of the
nonlinearities in the waveform in these areas.
pulse width (tW)
• measure on duration of the pulse
• time interval between the 50% points on the
rising and falling edges
Propagation delay time
• When a signal passes (propagates) through a logic circuit, it always
experiences a time delay, as illustrated in Figure 5(a). The delay in signal
is due to stray resistance and capacitance in the circuit.
• A change in the output level always occurs a short time, called the
propagation delay time, later than the change in the input level that
caused it.
• There are two propagation delay times specified for logic gates:
➢tPHL: The time between a designated point on the input pulse and the
corresponding point on the output pulse when the output is changing from
HIGH to LOW.
➢tPLH: The time between a designated point on the input pulse and the
corresponding point on the output pulse when the output is changing from
LOW to HIGH.
Figure 5(a): Basic illustration of propagation delay time
Propagation delay time
• Propagation delays, tPHL and tPLH, are measured between the 50% points of
the corresponding edges of the input and the output pulses.
• Propagation delay time limits the switching speed or frequency at which
a logic circuit can operate.
• The shorter the propagation delay, the higher the speed of the circuit and the
higher the frequency at which it can operate. Thus, a higher speed circuit is
one that has a smaller propagation delay time.
(a)
(b)
Figure 5: (a) Basic illustration of propagation delay time (b)
propagation delay times defined for H-L and L-H transitions at output.
Propagation delay time
Propagation delay time
Input
Find:
(i) pulse width, tW, of the
input voltage waveform.
(ii) rise time, tr, of the output
voltage waveform.
(iii)fall time, tf, of the output
voltage waveform.
(iv)propagation delay from
HIGH-state to LOW-state,
tPHL, of the output voltage
waveform.
(v) propagation delay from
LOW-state to HIGH-state,
tPLH, of the output voltage
waveform.
100%
VIH
90%
90%
50%
50%
10%
10%
VIL
12 20 28
time (ms)
52 60 68
Output
VOH
90%
90%
50%
50%
10%
10%
VOL
28 38 48
78
98
118
time (ms)
Propagation delay time
Find:
(i) pulse width, tW, of the input voltage waveform.
(ii) rise time, tr, of the output voltage waveform.
(iii)fall time, tf, of the output voltage waveform.
(iv)propagation delay from HIGH-state to LOW-state, tPHL, of the output voltage waveform.
(v) propagation delay from LOW-state to HIGH-state, tPLH, of the output voltage waveform.
Input
100%
VIH
Answer
i. 20µs → 60µs = 40µs
ii. 78µs → 118µs = 40s
iii. 28µs → 48µs = 20µs
iv. 20µs → 38µs = 12µs
v. 60µs → 98µs = 38µs
90%
90%
50%
50%
10%
10%
VIL
12 20 28
time (ms)
52 60 68
Output
VOH
90%
90%
50%
50%
10%
10%
VOL
28 38 48
78
98
118
time (ms)
Propagation delay time
Propagation delays are additive, so the more gates or inverters between
input and output, the greater the propagation delay time.
Critical path – the path with the longest propagation delay.
For example,
Figure 5: (c) Critical path
• The critical path in Figure 5(c) is the path highlighted in blue.
• Propagation delay from input A/B to output Y = propagation delay
AND1 + OR1 + AND2
• For example, if propagation delay of AND1 = 2ns, OR1 = 1ns and
AND2 = 3ns, total propagation delay from input A/B to output Y is
2ns + 1ns + 3ns = 6ns.
Propagation delay time
• Given that the propagation delay of the NOT, 2-input NAND, 2-input NOR,
3-input NOR logic gates are 30 ns, 43 ns, 55 ns and 70 ns respectively. Find:
• critical path and
• propagation delay
Propagation delay time
30 ns
43 ns
43 ns
30 ns
30 ns
70 ns
55 ns
55 ns
propagation delay = 30ns + 43ns + 43ns + 70ns = 186ns
NOT = 30ns
2-input NAND = 43ns
2-input NOR = 55ns
3-input NOR = 70ns
Function Simulation
Timing Simulation
Propagation delay time
Video
Digital waveform
• Digital waveforms are composed of series of pulses, sometimes
called pulse trains with voltage levels that are changing back and
forth between the HIGH and LOW levels or states.
• A periodic pulse waveform is one that repeats itself at a fixed
interval, called a period (T). The frequency (f ) is the rate at
which it repeats itself and is measured in hertz (Hz).
FIGURE 7: Periodic pulse waveform
Digital waveform
• frequency (f) of a pulse (digital) waveform is the reciprocal of the
period (T).
• duty cycle is the ratio of the pulse width (tW) to the period (T). It can
be expressed as a percentage.
Digital waveform
• A non-periodic pulse waveform does not repeat itself at fixed
intervals and may be composed of pulses of randomly differing
pulse widths and/or randomly differing time intervals between the
pulses.
FIGURE 8: Non-periodic pulse waveform
Serial data transfer
FIGURE 11: Serial transfer
Serial transfer
• Data is sent one bit at a time along a single line.
• For example, during the time interval from t0 to t1, the first bit is
transferred. During the time interval from t1 to t2, the second bit is
transferred, and so on.
• To transfer eight bits in series, eight time intervals is required.
Parallel data transfer
Parallel transfer
• All the bits in a group are sent
out on separate lines at the
same time.
• One line for each bit.
• To transfer eight bits in
parallel, only one time interval
is required.
FIGURE 12: Parallel transfer
Serial vs parallel transfer
Serial transfer
Advantage
➢ Minimum of only one line is required.
Disadvantage
➢ It takes longer to transfer a given number of bits than with parallel
transfer at the same clock frequency.
Parallel transfer
Advantage
➢ transfer data within one time interval.
Disadvantage
➢ A number of lines equal to the number of bits to be transferred at
one time is required.
Basic system function
• Storage - a function that is required in most digital systems, and its purpose is to retain
binary data for a period of time.
• A storage device can “memorize” a bit or a group of bits and retain the information as
long as necessary.
Common types of storage devices are
oflip-flops - D FF; J-K FF; T-FF; S-R FF
oRegisters – serial shift register; parallel
shift register
osemiconductor memories
➢Random access memory (RAM)
➢Read-only memory (ROM)
➢Solid State Drive – SSD, M.2
omagnetic memories
➢magnetic disks - HHD
➢magnetic tape
➢and optical disks (CDs).
Digital hardware system
Integrated circuit
Logic gates
Integrated circuit,
connectors and
components
Motherboard
Transistor circuit
Figure 1: Example of a hardware system
Transistor
IC packages
Figure 5: Other SMT packages
•
•
•
•
•
•
SSOP - shrink small-outline package (pins are in “gull-wing” shape)
PLCC - plastic-leaded chip carrier (pins are in a J-type shape)
LCC - leadless ceramic chip (metal contacts are molded into its ceramic body)
LQFP - low profile quad flat package (pins are in “gull-wing” shape)
CSP - chip scale package (contacts embedded in the bottom of the package)
FBGA - fine-pitch ball grid array (contacts embedded in the bottom of the package)
IC complexities
The complexity of digital IC is measured by the number of logic gates in a single package.
The complexity figures stated here for SSI, MSI, LSI, VLSI, and ULSI are generally
accepted, but definitions may vary from one source to another.
• Small-scale integration (SSI) - up to ten equivalent gate circuits on a single chip, and
they include basic gates and flip-flops.
• Medium-scale integration (MSI) -10 to 100 equivalent gates on a chip. They include
logic functions such as encoders, decoders, counters, registers, multiplexers, arithmetic
circuits, and small memories.
• Large-scale integration (LSI) - 100 to 10,000 equivalent gates per chip, including
memories.
• Very large-scale integration (VLSI) - 10,000 to 100,000 equivalent gates per chip.
• Ultra large-scale integration (ULSI) - very large memories, larger microprocessors,
and larger single-chip computers. Complexities of more than 100,000 equivalent gates
per chip are classified as ULSI.
IC technologies
• IC consists of many tiny transistors that are used to construct the digital circuit in IC.
The transistors can be either
➢metal oxide semiconductor field effect transistor (MOSFET)
➢bipolar junction transistor (BJT)
• IC fabrication technology, which is named after the type of transistor used to construct
the internal digital circuit of the IC (refer the transistor circuit in #slide 2), are
commonly
➢Complementary MOS (CMOS) technology – uses p- & n-type MOSFETs
➢TTL technology – uses BJT transistors
• Other IC fabrication technology includes
➢BiCMOS technology – uses combination of both CMOS and bipolar
➢Emitter-coupled logic – BJT based
Digital integrated circuits
• Digital integrated circuit can be broadly classified as
•Fixed function (standard) integrated chip (IC)
➢logic functions are set by manufacturer and cannot be altered by end user
➢Examples: IC-555, IC-741, Johnson counter, full adder, parallel adder, etc.
•Programmable logic
➢capable of being programmed by end users to perform specified functions
➢Examples: Logic gates, multiplexers, demultiplexers, arithmetic circuits,
Altera Stratix V FPGA, Stratix 10 SoC FPGA SOM, etc.
Programmable logic
• Programmable logic requires both hardware and software.
• Programmable logic can be programmed to perform specified logic
functions by the manufacturer or by the end user.
• Advantages of programmable logic over fixed-function logic:
• Programmable logic devices use much less board space for an
equivalent amount of logic.
• Another advantage is that, with programmable logic, designs can be
readily changed without rewiring or replacing components.
• Also, a logic design can generally be implemented faster and with
less cost with programmable logic than with fixed-function ICs.
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
Programmable array logic (PAL)
A programmable array is essentially a
grid or matrix of conductors that form
rows and columns with a programmable
link at each cross point.
The original PAL, which was one time
programmable (OTP), uses a fuse link,
as the programmable link.
programmable link
The purpose of programmable links
is to either make or break a
connection between a row line and
a column line. For each input to an
AND gate, only one programmable
link is left intact in order to connect
the desired variable to the gate
input.
X
FIGURE 9: Simple PAL structure with 2 input variables and 1 output (a)
unprogrammed (b) programmed for sum-of-product (SOP) implementation
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
Generic array logic (GAL)
• The GAL is essentially a PAL that can be reprogrammed.
• It consists of a reprogrammable array of AND gates and a fixed
array of OR gates with programmable outputs.
• The basic difference is that a GAL uses a reprogrammable
process technology, such as EEPROM, instead of fuses.
• MOS transistor, known as floating gate transistor, is used as
programmable link.
FIGURE 11: Basic GAL array
Simplified schematic notation for PAL/GAL
The input variables to a PAL or GAL are
usually buffered (by input buffer) to prevent
loading by a large number of AND gate inputs
to which they are connected.
FIGURE 13: Schematic representation of PAL/GAL
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
EPROM technology
• Floating-gate transistor acts as a switch to connect the row line to either a
HIGH or a LOW, depending on the input variable.
• For input variables that are not used, the transistor is programmed to be
permanently off (open).
0 → transistor on → input AND gate LOW
1 → transistor off → input AND gate HIGH
FIGURE 12: EPROM technology
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
Complex programmable logic device (CPLD)
• As technology progressed and the amount of circuitry that could be put on
a chip (chip density) increased, manufacturers were able to put more than
one SPLD on a single chip.
• CPLD is a device containing multiple SPLDs.
• Most CPLDs are reprogrammable and use EEPROM or SRAM process
technology for the programmable links.
input
SPLD
SPLD
SPLD
SPLD
output
FIGURE 17: General block diagram of CPLD with logic array blocks
24
(LABs) & 1 programmable interconnection array (PIA). Depending on the
specific CPLD, there can be from 2 to 64 LABs. Each logic array block is
roughly equivalent to 1 SPLD.
Programmable logic
FIGURE 7: Programmable logic
Programmable
Logic Devices
Simple PLDs:
• Programmable array logic (PAL)
• Generic array logic (GAL)
Field Programmable
Gate Arrays
Complex PLDs
Programmable ROMs (PROM)
Field programmable gate array (FPGA)
• FPGA is generally more complex and has much higher density than CPLD.
• Three basic elements in an FPGA are the logic block, the programmable
interconnections, and the input/output (I/O) blocks.
programmable
interconnection
matrix
FIGURE 18: Basic structure of an FPGA.
FPGA
• The logic blocks in an FPGA are not as complex as the logic array
blocks (LABs) in a CPLD, but generally there are many more of them.
• The logic blocks are programmed to perform specific functions.
• The I/O blocks are on the outer edges of the structure and provide
individually selectable input, output, or bidirectional access to the
outside world.
• The distributed programmable interconnection matrix provides for
interconnection of logic blocks and connection to inputs/outputs.
• Large FPGAs can have tens of thousands of logic blocks in addition to
memory and other resources.
• FPGAs are reprogrammable and use SRAM or antifuse process
technology for the programmable links.
Fuse technology
The fuse is a metal link that connects a row and a column in the
interconnection matrix.
Before programming, there is a fused connection at each
intersection.
To program a device, the selected fuses are opened by passing a
current through them sufficient to “blow” the fuse and break the
connection. The intact fuses remain and provide a connection
between the rows and columns.
FIGURE 10: Fuse technology
Antifuse technology
• An antifuse programmable link is the opposite of a fuse link.
• Instead of breaking the connection, a connection is made during
programming.
• Before programming, there are no connections between the rows and
columns in the interconnection matrix. An antifuse is basically two
conductors separated by an insulator.
• To program a device with antifuse technology, a programmer tool applies
a sufficient voltage across selected antifuses to break down the insulation
between the two conductive materials, causing the insulator to become a
low-resistance link.
• An antifuse device is also a one-time programmable (OTP) device.
FIGURE 19: Programmable antifuse link
Basic programmable logic design flow
Design Entry
• Schematic design
• Source Codes (HDL, hardware description
language)
Functional Simulation
- verify that the circuit functions as expected.
Synthesis
-Converts schematic or HDL codes into
netlists that describe the electrical
connectivity of the circuit.
Implementation
- Logic structures described by the netlist are
mapped into the actual structure of the
specific device being programmed.
Timing Simulation
-Simulation to confirm no design flaws and
timing problems due to propagation delay.
Program the PLD chip
FIGURE 21: Basic programmable logic
design flow block diagram
Download
-The generated code is downloaded to the
programmable device to implement the
software design in hardware.
Loading and fan-out
• When the output of a logic gate is connected to one or more inputs of
other gates, a load on the driving gate is created, as shown in Figure 6.
• There is a limit to the number of load gate inputs that a given gate can
drive. This limit is called the fan-out of the gate. In other words, it is the
maximum number of load gate inputs that can be connected to the
output of the driving gate without adversely affecting the operational
characteristics of the driving gate.
• Fan out is expressed in unit load.
FIGURE 6(a): Load gates acting as a load to the driving gate
Digital logic families
• Logic family - a group of compatible integrated circuit (ICs) with the
same logic levels and supply voltages for performing various logic
functions and have been fabricated with specific circuit technology.
• The types of transistors implemented in integrated circuits (ICs) includes
➢metal oxide semiconductor field effect transistor (MOSFET)
➢bipolar junction transistor (BJT)
• 2 major logic families (IC fabrication technology) are
➢Complementary MOS (CMOS) technology – uses p- & n-type
MOSFETs
➢TTL technology – uses BJT transistors
• Other logic families includes
➢BiCMOS technology – uses combination of both CMOS and bipolar
➢Emitter-coupled logic – BJT based
Transistor-transistor logic (TTL) logic levels
• TTL family uses bipolar junction transistor (BJT) technology.
• The nominal value of the DC supply voltage for TTL (transistortransistor logic) devices is +5 V.
Figure 1: Input and output voltage levels for TTL
Complementary MOS (CMOS) logic levels
• CMOS (complementary metal-oxide semiconductor) family uses complementary (p-and n-type) MOSFET technology.
• CMOS devices are available in different DC supply voltage categories: +5 V, +3.3 V, +2.5 V, and +1.2 V.
• CMOS devices generally consumes less power than TTL.
(a) +5V
(b) +3.3V
Figure 2: Input and output voltage levels for CMOS operated with DC
supply voltages (a) +5 V and (b) +3.3V
Loading and fan-out
• When the output of a logic gate is connected to one or more inputs of
other gates, a load on the driving gate is created, as shown in Figure 6.
• There is a limit to the number of load gate inputs that a given gate can
drive. This limit is called the fan-out of the gate. In other words, it is the
maximum number of load gate inputs that can be connected to the output
of the driving gate without adversely affecting the operational
characteristics of the driving gate.
• Fan out is expressed in unit load.
FIGURE 6(a): Load gates acting as a load to the driving gate
Fan-Out Example
Refer to the 7400 NAND gate data sheet determine the
fan-out of the 7400 NAND gate
=
=
Fan-In
• Fan-in - the number of inputs a gate has. For example,
➢ a two-input AND gate has fan-in of two,
➢ a three input NAND gate as a fan-in of three.
➢ a NOT gate always has a fan-in of one.
• It is the number of inputs, which the logic gate can control or handle
properly.
a two-input AND gate has fan-in of two
a three-input NAND gate has fan-in of three
THE END