IPC-7093A
Design and Assembly Process
Implementation for Bottom
Termination Components (BTCs)
2020 – October
Supersedes IPC-7093
March 2011
An international standard developed by IPC
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IPC-7093A
®
Design and Assembly
Process Implementation
for Bottom Termination
Components (BTCs)
Developed by the Bottom Termination Components (BTC) Task
Group (5-21h) of the Assembly and Joining Committee (5-20) of IPC
Users of this publication are encouraged to participate in the
development of future revisions.
Contact:
IPC
3000 Lakeside Drive, Suite 105N
Bannockburn, Illinois
60015-1249
Tel 847 615.7100
Fax 847 615.7105
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October 2020
IPC-7093A
Acknowledgment
Any document involving a complex technology draws material from a vast number of sources across many continents. While
the principal members of the Bottom Termination Components (BTC) Task Group (5-21h) of the Assembly and Joining
Committee (5-20) are shown below, it is not possible to include all of those who assisted in the evolution of this standard.
To each of them, the members of the IPC extend their gratitude.
Assembly and Joining
Committee
Bottom Termination
Components (BTC) Task Group
Technical Liaison of the
IPC Board of Directors
Chair
Daniel Foster
Missile Defense Agency (MDA)
Chair
Ray Prasad
Ray Prasad Consultancy Group
Bob Neves
Microtek (Changzhou) Laboratories
Vice Chair
Karen Tellefsen
MacDermid Alpha
Electronics Solutions
Vice Chairs
Matt Kelly
IBM
Udo Welzel
Robert Bosch GmbH
Bottom Termination Components (BTC) Task Group
Wallace Ables, Dell Inc.
Dudi Amir, Intel Corporation
Gaston Hidalgo, Toyota Motor North
America
Richard Arnold, Continental
Automotive Systems
David Hillman, Collins Aerospace
Raiyomand Aspandiar, Intel
Corporation
Constantin Hudon, Varitron
Technologies Inc.
Paul Austen, ECD
Jennie Hwang, H-Technologies
Group
Mike Bixenman, Kyzen Corporation
Gerald Bogert, Bechtel Plant
Machinery, Inc.
Edgar Butron, Lockheed Martin
Eric Camden, Foresite, Inc.
William Cardinal, Collins Aerospace
Stephen Chavez, UTC Aerospace
Systems
Beverley Christian, HDP User Group
Robert Cochran, Mind Chasers Inc.
Scott Decker, UTC Aerospace
Systems
Gerjan Diepstraten, Vitronics Soltec
Joe Fjelstad, Verdant Electronics
Dennis Fritz, MacDermid Enthone
Electronics Solutions
John Ganjei, MacDermid Alpha
Electronics Solutions
Ife Hsu, Intel Corporation
Agnieszka Ozarowski, BAE Systems
Keith Peterson, Missile Defense
Agency
Ray Prasad, Ray Prasad Consultancy
Group
Jagadeesh Radhakrishnan, Intel
Corporation
Mark Jeanson, IBM
Thorsten Rother, YXLON
International GmbH
Sharissa Johns, Lockheed Martin
Missiles & Fire Control
Robert Rowland, Axiom Electronics,
LLC
Michael Johnson, M/A-COM
Technology Solutions, Inc.
Kunal Shah, LiloTree
Matt Kelly, IBM
Vern Solberg, Solberg Technical
Consulting
Robert Kinyanjui, John Deere
Electronic Solutions
Bhanu Sood, NASA Goddard Space
Flight Center
Leo Lambert, EPTAC Corporation
Rainer Taube, Taube Electronic
GmbH
Dale Lee, Plexus
David Lober, Kyzen Corporation
Karen McConnell, Northrop
Grumman Corporation
Michael Moore, U.S. Army Aviation
& Missile Command
Richard Otte, PROMEX Industries,
Inc.
Kristen Troxel, HP Inc.
Hector Valladares, Honeywell
Aerospace
Mark Waterman, ECD
Udo Welzel, Robert Bosch GmbH
Linda Woody, LWC Consulting
Thomas Hausherr, PCB Libraries
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iii
IPC-7093A
October 2020
Special Recognition
IPC recognizes the following group of people who showed exceptional leadership and effort in the development of
IPC-7093A.
Dudi Amir, Intel
Matt Kelly, IBM
Raiyomand Aspandiar, Intel
Corporation
Robert Kinyanjui, John Deere
Electronic Solutions
Mike Bixenman, Kyzen Corporation
Robert Cochran, Mind Chasers Inc.
Ray Prasad, Ray Prasad Consultancy
Group
David Hillman, Collins Aerospace
Jagadeesh Radhakrishnan, Intel
Michael Johnson, M/A-COM
Technology Solutions, Inc.
Thorsten Rother, YXLON
International GmbH
iv
Copyright IPC
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Rob Rowland, Axiom Electronics,
LLC
Kunal Shah, Lilo Tree
Udo Welzel, Robert Bosch GmbH
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October 2020
IPC-7093A
Table of Contents
1
SCOPE ...................................................................... 1
1.1
1.2
Purpose ................................................................. 1
Classification ........................................................ 1
1.3
1.4
1.5
1.6
1.6.1
1.7
Measurement Units ..............................................
Definition of Requirements .................................
Process Control Requirements ............................
Order of Precedence ............................................
Clause References ................................................
Use of ‘‘Lead’’ .....................................................
1.8
1.9
Abbreviations and Acronyms .............................. 2
Terms and Definitions ......................................... 2
1.9.1
1.9.2
1.9.3
1.9.4
1.9.5
Bottom Termination Component (BTC) .............
Wettable Side Flank .............................................
Exposed Die Paddle .............................................
Thermal Pad .........................................................
Thermal Via .........................................................
2
1
1
2
2
2
2
2
2
2
2
2
APPLICABLE DOCUMENTS .................................... 2
2.1
IPC ....................................................................... 2
2.2
Joint Standards ..................................................... 3
2.3
ASME ................................................................... 4
2.4
IEC ....................................................................... 4
2.5
JEDEC .................................................................. 4
3.4
3.4.1
3.4.2
Inspection and Rework ...................................... 11
Quad Flat No-Lead (QFN) Solder
Joint Inspection .................................................. 11
Automated X-Ray Inspection (AXI) ................. 11
3.4.3
3.4.4
3.5
Failure Analysis ................................................. 12
Rework Considerations ...................................... 12
Needs and Expectations ..................................... 12
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
General Description of Different BTC
Packages .............................................................
Detailed Description and Standards for
BTCs ..................................................................
Single-Row Molded Lead-Frame-Based
Packaging
...............................................................
Multiple-Row Molded Lead-Frame-Based
Packaging ...........................................................
Plastic-Quad, Dual-Inline, Square and
Rectangular No-Lead Packages .........................
Punch-Singulated Fine Pitch Square Very
Thin and Ultra-Thin Profile Lead-FrameBased Quad No-Lead Staggered Dual-Row
Packages .............................................................
Quad No-Lead Staggered and In-Line
Multiple-Row Packages .....................................
14
16
16
16
16
20
23
3.1
BTC Types ........................................................... 5
4.3.1
Detailed Description of Quad Flat No-Lead
(QFN) and Small Outline No-Lead (SON) /
Dual Flat No-Lead (DFN) Packages ................. 26
Manufacturing Methods ..................................... 26
3.1.1
BTCs with Thermal Die Paddle .......................... 5
4.3.2
Types of Defects ................................................ 30
3.1.2
BTCs without Thermal Die Paddle ..................... 5
4.3.3
Marking Alternatives ......................................... 32
3.1.3
Flip Chip QFN (FC-QFN) ................................... 5
4.3.4
Materials Used ................................................... 32
3.1.4
Land Grid Array (LGA) ...................................... 5
4.3.5
Solderability Testing .......................................... 32
3.1.5
Other BTC Designations ..................................... 5
4.4
3.1.6
BTC Device Manufacturer Acronyms ................ 6
3.1.7
Description of Different Component
Structures ............................................................. 6
Custom Quad Flat No-Lead (QFN) and Small
Outline No-Lead (SON) / Dual Flat No-Lead
(DFN) Packaging ............................................... 33
4.5
Description of Commercial Variations .............. 33
3.2
Total Cost of Ownership ..................................... 9
4.5.1
3.3
Design and Assembly Process Considerations
for QFN Type BTC Packages ............................. 9
Detailed Description of Micro Lead Frame
(MLF), Micro Lead Package (MLP)
and Micro Lead Frame Plastic (MLFP)
Components ....................................................... 33
3.3.1
Current-Carrying Requirements and Thermal
Dissipation ........................................................... 9
4.5.2
3.3.2
Electrical Performance ....................................... 10
Detailed Description of Leadless Lead Frame
Package (LLP) and Lead Frame Chip Scale
Package (LFCSP) Components ......................... 36
3.3.3
Selection of Solder Paste Type, Stencil
Design and Solder Paste Printing ..................... 10
4.6
Land Grid Arrays (LGAs) ................................. 38
4.6.1
Land Grid Array (LGA) Construction .............. 39
3.3.4
Single Thermal Pad Design ............................... 10
4.6.2
3.3.5
Multiple-Thermal-Pads Design ......................... 10
Manufacturing Methods for Substrate-Based
LGAs .................................................................. 41
3.3.6
Wettable Side Flank ........................................... 10
4.6.3
Types of Defects ................................................ 42
3
4.3
COMPONENT CONSIDERATIONS ........................ 14
GENERAL OVERVIEW OF BTCs ............................ 5
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v
IPC-7093A
4.6.4
4.6.5
5
October 2020
Assembly Challenges Mounting Land Grid
Array (LGA) Packages ...................................... 42
HDI Process ....................................................... 42
PRINTED BOARDS AND OTHER
MOUNTING STRUCTURES .................................... 44
5.1
5.2
5.3
5.4
5.4.1
5.4.2
High-Density Interconnect (HDI) Build-Up
Layers .................................................................
Base Materials Considerations ..........................
Moisture Absorption ..........................................
Surface Finishes .................................................
Hot-Air Solder Leveling (HASL) .....................
Organic Solderability Preservative (OSP)
Coatings .............................................................
44
44
44
44
46
46
5.4.3
Electroless Ni/Immersion Au (ENIG) ............... 46
5.4.4
Electrolytic Ni/Electroplated Au (ENEG) ......... 46
5.4.5
Electroless Ni/Electroless Pd/Immersion Au
(ENEPIG) ........................................................... 47
5.4.6
Immersion Ag .................................................... 47
5.4.7
Immersion Sn ..................................................... 47
5.4.8
Solid Solder Deposition ..................................... 47
5.5
Silk Screen ......................................................... 49
5.6
Site Flatness, Bow and Twist ............................ 50
6
PRINTED BOARD DESIGN CONSIDERATIONS .. 50
6.11
Thermal Pad Design Options ............................
6.11.1 Solder Mask Defined (SMD) Thermal
Pad Design .........................................................
6.11.2 Open-Cu Thermal Pad Design ..........................
6.11.3 Via Tenting Thermal Pad Design ......................
6.11.4 Encroached Via Thermal Pad Design ...............
6.11.5 Via-in-Pad Plated-Over (VIPPO) Thermal
Pad Design .........................................................
6.11.6 Floating Mask Thermal Pad Design .................
6.12
Design for Cleaning Considerations .................
6.13
Stencil Design Considerations ...........................
6.13.1
6.13.2
6.14
6.15
Thermal Pad Stencil Design ..............................
Perimeter I/O Stencil Design ............................
Stencil Aperture Reductions ..............................
Important Considerations When Designing
for BTCs ............................................................
6.15.1 Ganged Solder Mask Openings on I/O
Terminals ............................................................
6.15.2 Mirrored Quad Flat No-Leads (QFN)
Constructions .....................................................
6.16
Random Via Locations ......................................
7
64
66
69
73
74
74
77
79
81
81
85
85
86
86
86
86
ASSEMBLY OF BTCs ON PRINTED
BOARDS ................................................................. 86
7.1
7.1.1
7.1.2
7.1.3
BTC Component Considerations .......................
Incoming Packaging Formats ............................
BTC Temperature Sensitivity ...........................
BTC Moisture Sensitivity Considerations ........
86
87
88
88
7.1.4
7.2
7.2.1
88
89
7.2.2
BTC Termination Finishes and Solderability ...
Printed Board Considerations ............................
Printed Board Design Impact on Solder
Joint Fillet Formation ........................................
Assembly-Induced Warpage ..............................
7.3
7.3.1
Assembly Materials ........................................... 90
Solder Alloy Mounting Methods ....................... 90
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.4
7.5
7.5.1
Solder Paste .......................................................
Solder Preforms .................................................
Solder Alloy .......................................................
Flux Chemistry Considerations .........................
Edge/Corner Bond Materials, Underfills and
Adhesives ...........................................................
BTC Cleaning Process .......................................
Solder Printing and Deposition .........................
Solder Stencil Printing Considerations .............
7.5.2
7.5.3
Jetting and Dispensing ....................................... 93
Solder Dipping of BTC Components ............... 94
6.10.4 Thermal Via Standard Grids .............................. 62
7.6
7.7
Solder Paste Inspection ..................................... 94
Component Placement ....................................... 95
6.10.5 Inadequate Via Quantity .................................... 64
7.8
Solder Joint Reflow ........................................... 95
6.1
Design for Assembly Considerations ................ 50
6.2
BTC Land Pattern Design Process ................... 50
6.3
Package Variations ............................................. 51
6.4
BTC Land Pattern and Component Symbol
Coding ................................................................ 52
6.5
Circuit Routing Considerations / Thermal
Via Keep-Outs ................................................... 53
6.6
Important BTC Package Elements for
Physical Design ................................................. 53
6.6.1
Termination Formats .......................................... 53
6.7
BTC Land Patterns and Component Symbol
Coding ................................................................ 53
6.8
Solder Mask Design .......................................... 54
6.8.1
Encroached Vias ................................................ 54
6.8.2
Solder Mask Design for I/O Cu Pads ............... 54
6.8.3
Solder Mask Design for Thermal Pads ............. 56
6.8.4
Perimeter I/O Cu Pad Design ........................... 57
6.9
HDI Considerations ........................................... 58
6.10
Cu Thermal Pad Design .................................... 59
6.10.1 Thermal Via Types ............................................. 59
6.10.2 Key Thermal Pad Design Elements .................. 60
6.10.3 Thermal Pad Via Counts and Arrangement ...... 62
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89
90
90
90
90
91
91
91
92
92
October 2020
7.8.1
7.8.2
7.8.3
IPC-7093A
Reflow Atmosphere ...........................................
Time and Temperature Profiles .........................
Unique Profile for Each Printed Board
Assembly ............................................................
7.8.4 Effects of Materials on Flux Activation,
Component Damage and Solderability .............
7.9
Thermal Profiling for BTCs ..............................
7.10
Process Control and Monitoring Points
for BTCs ............................................................
7.11
Production-Level Inspection ..............................
7.11.1 Automated Solder Paste Inspection (SPI) .........
96
96
8.4.1
Time Zero Assembly Analysis by
Endoscopy ........................................................ 111
8.4.2
Accelerated Life Testing for
Thermomechanical Reliability ......................... 112
Accelerated Lifetime Testing for
Reliability Under Damp Heat .......................... 113
97
8.4.3
97
98
99
99
99
7.11.2
7.11.3
7.11.4
7.12
7.12.1
7.12.2
7.12.3
Automated Optical Inspection (AOI) ..............
Automated X-Ray Inspection (AXI) ...............
Manual Visual Inspection ................................
Rework and Repair ..........................................
Hot-Air Rework ...............................................
Alternative Methods ........................................
I/O Lead Manual Touch-Up ............................
100
102
103
104
104
104
105
7.13
7.14
7.15
Conformal Coating of BTCs ........................... 105
Mechanical Heat Sink Usage .......................... 105
Production-Level Testing ................................. 106
9
9.1
9.1.1
TROUBLESHOOTING ........................................... 113
9.1.2
9.1.3
9.1.4
9.1.5
Assembly and Fabrication Issues ....................
Printed Board Supplier Solder Mask
Alterations ........................................................
SMT Stencil Alterations ..................................
Alternate SMT Stencil Printing Methods .......
Thermal Pad Voiding .......................................
I/O Pad Voiding ...............................................
113
114
114
114
114
9.1.6
9.2
9.2.1
9.2.2
I/O Opens and Bridging ..................................
BTC Assembly Troubleshooting .....................
BTC Open Joints .............................................
Solder Attachment Failures .............................
114
115
115
115
APPENDIX A
113
Index of Acronyms and
Abbreviations ................................... 118
7.15.1 Electrical Testing ............................................. 106
Figures
7.15.2 Functional Test (FT) Coverage ....................... 106
Figure 1-1
Various Forms of BTCs .................................... 1
Figure 3-1
Bottom Side of a Flip Chip QFN (FC-QFN)
Showing Irregular Solder Terminations ............ 5
RELIABILITY CONSIDERATIONS
FOR BTCs ............................................................. 106
Figure 3-2
BTC Packages without Thermal Pads
(Top and Bottom View) ..................................... 6
8.1
Introduction and Reliability Fundamentals
of BTCs ............................................................ 106
Figure 3-3
Single Thermal Pad QFN Device Example
(Top and Bottom View) ..................................... 7
8.1.1
Mechanical Reliability ..................................... 107
Figure 3-4
Multiple Thermal Pad Design Example ............ 7
8.1.2
Thermomechanical Reliability ......................... 107
Figure 3-5
Saw-Singulated BTC Packages ....................... 8
8.1.3
Electrochemical Reliability ............................. 107
Figure 3-6
Package Thickness Comparison ...................... 8
8.2
Designing for BTC Reliability –
Thermomechanical Loads ................................ 108
Figure 3-7
Example of a Printed Board Land Pattern
with a Single Thermal Pad Containing Vias ... 10
Figure 3-8
8.2.1
Printed Board Design Considerations ............. 108
Examples of Printed Board Land Patterns
with Multiple Thermal Pads ............................ 11
8.2.2
Printed Board Thickness ................................. 108
Figure 3-9
8.2.3
Wettable Side Flank Effect on Reliability ...... 108
Comparison of a Standard BTC Termination
and a Wettable Side Flank BTC Termination . 11
8.2.4
Land Size and Pitch ......................................... 109
Figure 3-10
Step-Cut Quad Flat No-Lead (QFN)
Package Assembly Process ........................... 12
8.2.5
BTC Package Stand-Off .................................. 109
Figure 3-11
8.2.6
Benefits of Reinforcement ............................... 110
Sn-Plated Step-Cut Quad Flat No-Lead
(QFN) Lead Frame ......................................... 12
8.2.7
Mold Compound Material ............................... 110
Figure 3-12
Concave Depression Etched into the
Bottom Surface of the Contact ....................... 13
8.2.8
Die Size ............................................................ 110
Figure 3-13
8.2.9
Solder Joint Microstructure Embrittlement ..... 110
8.3
Designing for BTC Reliability – Electrical
and Thermal Loads .......................................... 110
Cross-Sectional Representations of Wettable
Flank Terminations for Mechanical Precut
Process (Left) and Dimple-Formation
Chemical Etch Process (Right) ...................... 13
Figure 3-14
8.3.1
Voids in Thermal Pad ...................................... 110
Microscopic Images of Common Pin
Modifications ................................................... 13
8.4
Reliability Testing ............................................ 111
Figure 3-15
Transparent View of a DFN Package ............ 14
7.15.3 Burn-In Testing ................................................ 106
7.15.4 Product Screening Tests .................................. 106
8
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vii
IPC-7093A
Figure 3-16
October 2020
Detailed View on Side Wettable Flank
Features of a DFN Package .......................... 14
Figure 4-30
Example of Half-Etch Pull-Back Contact
and Full-Etch No-Pull-Back Perimeter
Contact Configurations ................................... 30
Figure 4-31
Plating Layer Construction Comparison ......... 32
Figure 4-32
Detailed View of a Custom Site for a QFN .... 33
Figure 4-1
Various Forms of BTC Parts .......................... 15
Figure 4-2
Singulated Land Grid Array (LGA)
(Bottom of Device) .......................................... 15
Figure 4-3
Basic Single-Row Lead-Frame-Based Small
Outline No-Lead (SON)-Quad Flat No-Lead
(QFN) Package Assembly Model ................... 16
Figure 4-33
Example 28 I/O Micro Lead Frame (MLF)
Package .......................................................... 33
Figure 4-34
Micro Lead Package (MLP) ............................ 33
Figure 4-4
Basic Multiple-Row Quad Flat No-Lead
(QFN) Package Assembly Model ................... 16
Figure 4-35
Micro Lead Frame Plastic Package (MLFP) .. 34
Figure 4-5
Terminal Configuration for Single-Row
Small Outline No-Lead (SON) and Quad
Flat No-Lead (QFN) Packaging ...................... 16
Figure 4-36
JEDEC MO-220 Package Outline .................. 34
Figure 4-37
QFN Contact Design ...................................... 35
Figure 4-38
Lead Frame Chip Scale Package (LFCSP) ... 36
Figure 4-6
Figure 4-7
JEDEC-Defined Package Outlines for
Single-Row Small Outline No-Lead (SON)
and Quad-Flat No-Lead (QFN) Packaging .... 17
Terminal Design Variations for Single-Row
Small Outline No-Lead (SON) and Quad
Flat No-Lead (QFN) Packaging ...................... 18
Figure 4-39
Leadless Lead Frame Package (LLP) ........... 36
Figure 4-40
Typical Leadless Lead Frame Package
(LLP) and Lead Frame Chip Scale
Package (LFCSP) Outline Detail .................... 37
Figure 4-41
Examples of Land Grid Array (LGA)
Packages ........................................................ 38
Figure 4-42
Air Cavity and Over-Molded Land Grid
Array (LGA) Constructions ............................. 39
Figure 4-43
Sample Ball Grid Array (BGA) Process
Flow ................................................................ 39
Figure 4-44
Sample Molded Land Grid Array (LGA)
Process Flow .................................................. 40
Figure 4-8
Terminal Contact Layout ................................. 19
Figure 4-9
Depopulation Schemes for Single-Row
Quad Flat No-Lead (QFN) Packaging ............ 19
Figure 4-10
Corner Terminals and Exposed Heat
Spreader ......................................................... 19
Figure 4-11
Metallized Terminal ......................................... 20
Figure 4-12
Fine-Pitch Two-Row Quad Flat No-Lead
(QFN) Packaging ............................................ 20
Figure 4-45
Sample Air Cavity Land Grid Array (LGA)
Process Flow .................................................. 40
Figure 4-13
Quad Flat No-Lead (QFN) Dual-Row
Package (Top and Side Views) ...................... 21
Figure 4-46
Top (Primary) View of Land Grid Array
(LGA) Printed Board ....................................... 41
Figure 4-14
Outer and Inner Terminal Layout Variations ... 22
Figure 4-47
Figure 4-15
Two-Row Terminal Layout .............................. 22
Bottom (Secondary) View of Land Grid
Array (LGA) Printed Board ............................. 41
Figure 4-16
Notch Feature on Exposed Die-Attach Pad ... 23
Figure 5-1
Figure 4-17
Two- and Three-Row Quad Flat No-Lead
(QFN) Package Examples .............................. 23
Cross-Section of HASL-Coated Lead;
Not Flat ........................................................... 46
Figure 5-2
Figure 4-18
Basic Two-Row Terminal Layout Variations ... 24
Nonuniform HASL Pads (Left) and Coordinate
Measuring Machine (CMM) Image Showing
HASL Coating Variation (Right) ...................... 46
Figure 4-19
Basic Three-Row Terminal Layout
Variations ........................................................ 24
Figure 5-3
Solid Solder Deposition (SSD) Application
Basic Fabrication Steps .................................. 48
Figure 4-20
Contact Geometry Variations .......................... 25
Figure 5-4
SSD Process Steps ........................................ 49
Figure 4-21
Basic Quad Flat No-Lead (QFN) Package
Outline Drawing .............................................. 25
Figure 5-5
Silk Screen Thickness Measurement on
Solder Mask .................................................... 49
Figure 4-22
Pin 1 Location Option ..................................... 26
Figure 6-1
Quad-Flat No-Lead (QFN) / SmallOutline No-Lead (SON) Family of
Bottom Termination Components (BTC) ........ 51
Figure 4-23
Various BTC Packages ................................... 26
Figure 4-24
Typical Die Attach Side Lead Frame with
NiPdAu Finish for QFNs ................................. 27
Figure 6-2
BTC Printed Board Land Pattern
Dimensions ..................................................... 52
Figure 4-25
Typical Solder Pad Side of a Quad Flat
No-Lead (QFN) Panel with Tape Over
the Lead Frame .............................................. 27
Figure 6-3
Comparing Pull-Back (Left) and No
Pull-Back Configurations (Right) .................... 53
Figure 4-26
Quad Flat No-Lead (QFN) Fabrication
with Saw Singulation ...................................... 28
Figure 6-4
Bottom (Left) and Inclined (Right)
Microscopic Images of Pull-Back Leads
on a Quad Flat No-Lead (QFN) Package ...... 53
Figure 4-27
Over-Molded Lead Frame Configuration ........ 28
Figure 6-5
Figure 4-28
Quad Flat No-Lead (QFN) Fabrication
with Punch Singulation ................................... 29
Cross-Sectional Microscopic Image of
Pull-Back ......................................................... 53
Figure 6-6
Figure 4-29
Comparing Punch-Singulated and
Saw-Singulated Packages with Wire
Bond Options .................................................. 29
Comparing Solder Mask Off Via Land with
a Solder Mask Encroached Via Land ............. 54
Figure 6-7
Comparing Optional Solder Mask
Variations ........................................................ 54
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IPC-7093A
Figure 6-8
NSMD I/O Design Example ............................ 55
Figure 6-9
Singulated and Ganged I/O Terminations ...... 55
Figure 6-10
Ganged I/O Terminations with Solder Mask
Opening .......................................................... 55
Figure 6-11
Surface Power/Ground Flooding into QFN
Device ............................................................. 56
Figure 6-12
Printed Board Supplier Removal of
Solder Mask Web ........................................... 56
Figure 6-13
Figure 6-38
Process Variation (Blue Gaussian Curve)
Results in Filled Vias if the Nominal Solder
Volume Is Set to Vmax .................................... 72
Figure 6-39
Micrograph of Quad Flat No-Lead (QFN)
Land with Open-Cu Thermal Pad Design
(Left), Solder Print Window Pattern (Middle)
and X-Ray Image After Reflow (Right) ........... 72
Figure 6-40
Solder Mask Defined (SMD) (Left) and
Non-Solder Mask Defined (NSMD) (Right)
Exposed-Pad Soldering Design Options ........ 56
Open-Cu Via Design without Solder Mask
(Left) and with Encroached Solder Mask
(Right) on the Bottom Side of the Printed
Board .............................................................. 72
Figure 6-41
Figure 6-14
Exposed-Pad Soldering Area Singulated by
Solder Mask Web ........................................... 57
Design with Top-Side Solder Mask Via
Tenting ............................................................ 73
Figure 6-42
Figure 6-15
Bulbus Solder Joint Formation (Left) Pin
Protrudes (Right) Beyond Package Body
Edge ............................................................... 57
Via-in-Pad Plated-Over (VIPPO) Thermal
Pad Illustration and Cross-Section ................. 75
Figure 6-43
Via-in-Pad Plated-Over (VIPPO) Pad
Example .......................................................... 76
Figure 6-44
Floating Solder Mask Via Design
Cross-Sectional and Planar Top Views .......... 77
Figure 6-45
Singulated Mask Location vs. Tied Mask
Location .......................................................... 78
Figure 6-46
Example Implementation of a Floating
Solder Mask Design ....................................... 78
Figure 6-16
Pad Larger Than Package Pin (Left)
and Pin Pulled Back from Package
Body Edge (Right) .......................................... 57
Figure 6-17
Concave Solder Joint Formation (Left)
and Pin Protrudes Beyond Package
Body Edge (Right) .......................................... 57
Figure 6-18
Pad Same Size as Package Pin (Left)
and Pin Pulled Back from Package
Body Edge (Right) .......................................... 57
Figure 6-47
Figure 6-19
HDI Build-Ups Possible with Laser-Via
Generation ...................................................... 58
Cu Area Printed with Single Bulk Aperture
(Left) and Cu Area Printed with Multiple
Apertures (Right) ............................................ 81
Figure 6-48
Figure 6-20
HDI Build-Ups Possible with Etching and
Mechanical Processes .................................... 59
Voiding Levels Using Single Bulk Apertures
(Left) and Voiding Levels Using Striped
Apertures (Right) ............................................ 82
Figure 6-21
Planarized and Capped Via Protection
Example .......................................................... 60
Figure 6-49
Figure 6-22
Via Protection Methods .................................. 61
Optimized Striped and Bulk Thermal Pad
Stencil Aperture Designs Based on Large
Body (Top) and Small Body (Bottom)
Package Sizes ................................................ 83
Figure 6-23
Cu Thermal Pad Design Showing Thermal
Via and Thermal Paddle ................................. 62
Figure 6-50
Example of Thermal Pad Basis Percentage
Coverage ........................................................ 84
Figure 6-24
Printed Board Mean Thermal Resistance of
an Array of Vias with a Given Via Density ..... 62
Figure 6-51
Solder Aperture Basis Percentage
Coverage ........................................................ 85
Figure 6-25
Orthogonal Array Structure (Left) and
Hexagonal Array Structure (Right) ................. 63
Figure 6-52
1:1 Stencil Aperture Reductions ..................... 85
Figure 6-26
Random Thermal Via Placement Example –
Not Recommended ......................................... 63
Figure 6-53
Mirrored Quad Flat No-Lead (QFN)
Example Structure .......................................... 86
Figure 6-27
Inadequate Via Quantity ................................. 64
Figure 7-1
JEDEC Tray Carrier Format ........................... 87
Figure 6-28
Heat Transfer Using Printed Board
Thermal Pad ................................................... 64
Figure 7-2
Elevated Process Windows Increasing
Temperature-Sensitive Component
(TSC) Risks .................................................... 88
Figure 6-29
BTC Thermal Pad Design Options ................. 65
Figure 7-3
Surface Defects Caused by Probe Marks ...... 89
Figure 6-30
Solder Mask Design (SMD) ............................ 66
Figure 7-4
Figure 6-31
Common Solder Mask Defined (SMD)
Layouts for Fewer Than Nine Vias ................. 68
Resultant Good (Left) vs. Bad (Right)
Solder Joint Formation for Pull-Back
and No Pull-Back BTC Configurations ........... 89
Figure 6-32
Common Solder Mask Defined (SMD)
Layouts Incorporating Nine Vias .................... 68
Figure 7-5
BTC with Outrigger Pads ............................... 90
Figure 7-6
Solder Preform in Tape-and-Reel Format ...... 90
Figure 6-33
Complex Solder Mask Defined (SMD)
Layouts with Via Counts Ranging from
Five to 31 or More .......................................... 68
Figure 6-34
Multiple Thermal Pad Design Example .......... 68
Figure 6-35
Open Thermal Through-Hole Via Structure ... 70
Figure 6-36
Solder Protrusion Under Quad Flat NoLead (QFN) Thermal Pad ............................... 70
Figure 6-37
Graph of Soldered Area and Filling of Vias ... 71
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Figure 7-7
Flux Residue Entrapment Area of Concern ... 91
Figure 7-8
Flux Residue Deposits Under a Dual-Row
QFN ................................................................ 91
Figure 7-9
Recommended Aperture Dimensions for
Commonly Used Stencil Thicknesses ............ 93
Figure 7-10
Comparison of Solder-Dipped and Not
Dipped BTCs and Resultant No Solder
Condition ......................................................... 94
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October 2020
Figure 7-11
Assessing Maximum Off-Land Acceptance
(Before Reflow) ............................................... 95
Figure 9-8
Insufficient Solder in Joint in QFN ................ 116
Figure 9-9
Open Due to Tilted BTC ............................... 117
Figure 7-12
Metal-Defined Land Solder Joint .................... 96
Figure 9-10
No Side Fillet ................................................ 117
Figure 7-13
Profile for SnPb Solder Reflow ...................... 97
Figure 9-11
Microvoids in a BTC I/O Solder Joint ........... 117
Figure 7-14
Profile for SAC Alloy Solder Reflow ............... 98
Figure 7-15
BTC Thermal Pad Thermocouple Location
for Profile Verification (Red Marker) ............... 98
Figure 7-16
Example Solder Paste Inspection Image
of a Quad Flat No-Lead (QFN) ...................... 99
Figure 7-17
Microscopy Images of Wetted (Top, Left)
and Nonwetted (Top, Right) Terminations
of a MLF Package ........................................ 100
Figure 7-18
Impact of Wetting Height .............................. 101
Figure 7-19
Good vs. Bad Wetted Pin (Side-Flank)
Detection Using AOI ..................................... 101
Figure 7-20
Tables
Table 3-1
Sample Listing of Some Common BTC
Designations ........................................................ 5
Table 3-2
Total Cost of Ownership of BTCs ....................... 9
Table 4-1
Commercially Available Quad-Flat NoLead (QFN) and Dual-Flat No-Lead (DFN)
Package Configurations .................................... 15
Table 4-2
Terminal Width Variations for Small Outline
No-Lead (SON) and Quad Flat No-Lead
(QFN) Packages ............................................... 20
Quad Flat No-Lead (QFN) with Wettable
Flanks ........................................................... 102
Table 4-3
Body Outline and Maximum Terminal Count .... 21
Figure 7-21
Cross-Section of Quad Flat No-Lead
(QFN) with Wettable Flanks ......................... 102
Table 4-4
Contact Geometries .......................................... 25
Table 4-5
Figure 7-22
X-Ray Images Using Various Techniques
to Detect Missing Solder .............................. 103
Lead Frame Package Defects and
Failure Modes ................................................... 31
Table 4-6
Plating Systems Used on Metal Lead
Frames .............................................................. 32
Figure 7-23
Example BTC X-Ray Images Using
Automated X-Ray Inspection (AXI)
After Assembly .............................................. 103
Table 4-7
Typical Package Outline and I/O for QFN ........ 35
Table 4-8
Leadless Lead Frame Package (LLP)
and Lead Frame Chip Scale Package
(LFCSP) Contact Pitch and Width Variations ... 37
Basic Material Elements for the Leadless Lead
Frame Package (LLP) and Lead Frame Chip
Scale Package (LFCSP) Devices ..................... 37
Figure 7-24
Solder Bumping Method Using a Stencil ..... 104
Figure 8-1
Solder Crack in an I/O BTC Solder Joint
Due to Coefficient of Thermal Expansion
(CTE) Mismatch After 1,000 Cycles ............. 107
Table 4-9
Figure 8-2
Weibull Plot Demonstrating Thinner Printed
Boards Result in Higher Fatigue Life ........... 108
Table 4-10 Substrate-Based Land Grid Array (LGA)
Defects and Failure Modes ............................... 43
Figure 8-3
Land Size Effect on Fatigue Life of 7-mm
BTC Packages .............................................. 109
Table 5-1
Key Attributed of Various Printed Board
Surface Finishes ............................................... 45
Figure 8-4
Plate-Up Bumped Option ............................. 109
Table 6-1
Common BTC Technology Ranges .................. 51
Figure 8-5
Stand-Off Effect on Fatigue Life of a BTC ... 109
Table 6-2
Figure 8-6
Heat Transfer with Exposed Pad Solder
Joints ............................................................. 110
BTC Thermal Pad Design Option Pros
and Cons ........................................................... 66
Table 6-3
Figure 8-7
Calculation of Void Influence Within
Exposed Pads on Overall Rth ....................... 111
Solder Mask Defined (SMD) Design Point
Parameters ........................................................ 69
Table 6-4
Open-Cu Thermal Pad Design Parameters ...... 73
Figure 8-8
Acceptable Thermal Pad Voiding Levels
(< 30 % by Cross-Sectional Area) ................ 111
Table 6-5
Via Tenting Thermal Pad Design
Parameters ........................................................ 75
Figure 9-1
Printed Board Manufacturer Removal of
Solder Mask Web ......................................... 113
Table 6-6
Via-in-Pad Plated-Over (VIPPO) Design
Parameters ........................................................ 77
Figure 9-2
Solder Deposits Not 1:1 with All Cu Pads .... 114
Table 6-7
Floating Solder Mask Design Parameters ........ 79
Zebra Printing on Open-Cu Thermal Pad .... 114
Table 7-1
Particle Size Comparisons ................................ 92
Figure 9-4
Cross-Section of BTC Open Joint ................ 115
Table 7-2
Figure 9-5
Open Shown in Cross-Section (Top) and
Dye and Pull (Bottom) .................................. 115
Pros and Cons of Common Stencil
Technologies and Options ................................. 94
Table 7-3
Design and Process Control Points for BTCs .. 99
Figure 9-6
Nonsolderable Land on LGA package .......... 115
Table 7-4
Figure 9-7
Nonwet Joints on a QFN .............................. 116
Production-Level Inspection Stages Ensuring
High-Quality BTC Manufacturing ...................... 99
Figure 9-3
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IPC-7093A
Design and Assembly Process Implementation for
Bottom Termination Components (BTCs)
1 SCOPE
This standard describes design and assembly guidance for implementing bottom termination components (BTCs). The focus
of the information contained herein is on critical design, materials, assembly, inspection, repair, quality and reliability issues
associated with BTCs.
This standard applies only to BTCs, which are components with planar terminations under the body with or without wettable side terminations or flanks. Examples of BTCs include small-outline no-lead (SON), dual-flat no-lead (DFN), quad-flat
no-lead (QFN), land grid array (LGA), etc. (see Section 4).
1.1 Purpose The purpose of this standard is to provide useful and practical information to those who use or are considering using BTCs. The target audiences for this document are
physical designers, process engineers, reliability engineers and
managers who are responsible for design, assembly, inspection and repair processes of printed boards and printed board
assemblies. Information described in this standard enables
high-quality and highly reliable BTC assembled devices operating within an electronic system.
This document also describes how to successfully implement
robust design and assembly processes for printed board
assemblies using BTCs as well as ways to troubleshoot some
common anomalies which can occur during BTC assembly.
For accept/reject criteria and requirements for BTC assemblies, see J-STD-001 and IPC-A-610.
Figure 1-1
Various Forms of BTCs
Figure 1-1 provides an example of various forms of BTCs.
1.2 Classification IPC standards recognize that electrical and electronic assemblies are subject to classifications by
intended end-item use. Three general end-product classes have been established to reflect differences in manufacturability,
complexity, functional performance requirements and verification (inspection/test) frequency. It should be recognized that
there may be overlaps of equipment between classes.
CLASS 1
General Electronic Products
Includes products suitable for applications where the major requirement is function of the completed assembly.
CLASS 2
Dedicated Service Electronic Products
Includes products where continued performance and extended life is required, and for which uninterrupted service is desired
but not critical. Typically, the end-use environment would not cause failures.
CLASS 3
High Performance/Harsh Environment Electronic Products
Includes products where continued high performance or performance-on-demand is critical, equipment downtime cannot be
tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life
support or other critical systems.
1.3 Measurement Units All dimensions and tolerances in this specification are expressed in hard SI (metric) units. Users
of this specification are expected to use metric dimensions. All dimensions ≥ 1.0 mm will be expressed in mm. All dimensions < 1.0 mm will be expressed in µm.
1.4 Definition of Requirements The words shall or shall not are used in the text of this document wherever there is a
requirement for materials, preparation, process control or acceptance. The word ‘‘should’’ reflects recommendations and is
used to reflect general industry practices and procedures for guidance only.
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Line drawings and illustrations are depicted herein to assist in the interpretation of the written requirements of this standard.
The text takes precedence over the figures.
1.5 Process Control Requirements The primary goal of process control is to continually reduce variation in the processes, products or services to provide products or processes meeting or exceeding user requirements. Process control tools
such as IPC-9191 or other user-approved system may be used as guidelines for implementing process control.
1.6 Order of Precedence
The contract shall take precedence over this standard, referenced standards and drawings.
In the event of conflict, the following order of precedence applies:
1. Procurement as agreed and documented between user and supplier.
2. Master drawing, design brief or tech pack reflecting the user’s detailed requirements.
3. When invoked by the customer or per contractual agreement, this standard.
When documents other than this standard are cited, the order of precedence shall be defined in the procurement documents.
The user can specify alternate acceptance criteria.
1.6.1 Clause References When a clause in this document is referenced, its subordinate clauses apply, unless the requirement references specific subordinate clauses.
For readability and translation, this document uses the word lead only to describe leads of a component (sometimes referred to as terminations).
1.7 Use of ‘‘Lead’’
1.8 Abbreviations and Acronyms Periodic table elements are written in their abbreviated form only in this standard. See
Appendix A for full spellings of these and other abbreviations and all acronyms used in this standard.
1.9 Terms and Definitions
Terms and definitions shall be in accordance with IPC-T-50 and 1.9.1 through 1.9.5.
Surface mountable electronic component with external connections consisting of planar metallized terminations on the underside that are an integral part of the component body.
1.9.1 Bottom Termination Component (BTC)
1.9.2 Wettable Side Flank
A BTC peripheral termination that is partially plated to improve solderability.
A metallic area on the bottom surface of a component that may or may not require soldering
to the printed board and which provides thermal conductivity and improves current carrying capability of the device.
1.9.3 Exposed Die Paddle
A Cu feature on a printed board that can be soldered to a BTC exposed die paddle to help conduct
heat from the device within the BTC to the printed board.
1.9.4 Thermal Pad
1.9.5 Thermal Via
Conventional Cu-plated through-hole via found within a thermal pad, which is used to dissipate heat
and carry current.
2 APPLICABLE DOCUMENTS
2.1 IPC1
IPC-A-610
IPC-CC-830
Acceptability of Electronic Assemblies
Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies
IPC-CH-65
Guidelines for Cleaning of Printed Boards and Assemblies
IPC-D-279
Design Guidelines for Reliable Surface Mount Technology Printed Board Assemblies
IPC-MS-810
Guidelines for High Volume Microsection
1. www.ipc.org
2
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IPC-SM-785
IPC-7093A
Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments
Terms and Definitions for Printed Boards and Printed Board Assemblies
IPC-T-50
IPC-TM-650
Test Methods Manual2
2.1.1
Microsectioning Manual and Semi or Automatic Method
2.4.53
Dye and Pull Test Method (Formerly Known as Dye and Pry)
IPC-1401
Corporate Social Responsibility and Sustainability Protocols for Electronic Manufacturing Industry
IPC-1601
Printed Board Handling and Storage Guidelines
IPC-2221
Generic Standard on Printed Board Design
IPC-2226
Sectional Design Standard for High Density Interconnect (HDI) Boards
IPC-4101
Specification for Base Materials for Rigid and Multilayer Printed Boards
IPC-4552
Performance Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Boards
IPC-4553
Specification for Immersion Silver Plating for Printed Boards
IPC-4554
Specification for Immersion Tin Plating for Printed Boards
IPC-4556
Specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Plating for Printed Circuit
Boards
IPC-4761
Design Guide for Protection of Printed Board Via Structures
IPC-6010 series
IPC-6012
Qualification and Performance Specification for Rigid Printed Boards
IPC-7094
Design and Assembly Process Implementation for Flip Chip and Die Size Components
IPC-7095
Design and Assembly Process Implementation for Ball Grid Arrays (BGAs)
IPC-7351
Generic Requirements for Surface Mount Design and Land Pattern Standard
IPC-7525
Stencil Design Guidelines
IPC-7526
Stencil and Misprinted Board Cleaning Handbook
IPC-7530
Guidelines for Temperature Profiling for Mass Soldering (Reflow & Wave) Processes
IPC-7711/7721
Rework, Modification and Repair of Electronic Assemblies
IPC-9191
General Guidelines for Implementation of Statistical Process Control (SPC)
IPC-9201
Surface Insulation Resistance Handbook
IPC-9203
Users Guide to IPC-9202 and the IPC-B-52 Standard Test Vehicle
2.2 Joint Standards3
J-STD-001
Requirements for Soldered Electrical and Electronic Assemblies
J-STD-002
Solderability Tests for Component Leads, Terminations, Lugs, Terminals and Wires
J-STD-004
Requirements for Soldering Fluxes
2. Current and revised test methods are available on the IPC website (www.ipc.org/test-methods.aspx)
3. www.ipc.org
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October 2020
Requirements for Soldering Pastes
J-STD-005
J-STD-006 Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic
Soldering Applications
J-STD-020
Handling Requirements for Moisture Sensitive Components
J-STD-033
Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices
J-STD-075
Classification of Non-IC Electronic Components for Assembly Processes
J-STD-609 Marking and Labeling of Components, Printed Board and Printed Board Assemblies to Identify Lead (Pb),
Pb-Free and Other Attributes
2.3 ASME4
ASME Y14.5
Dimensioning and Tolerancing
2.4 IEC5
Environmental Testing – Part 2-58: Tests – Test Td: Test Methods for Solderability, Resistance to Dissolution of Metallization and to Soldering Heat of Surface Mounting Devices (SMD)
IEC 60068-2-58
2.5 JEDEC6
JESD 30
Descriptive Designation System for Electronic-Device Packages
JEP 95 JEDEC
Registered and Standard Outlines for Solid State and Related Products
Plastic Quad and Dual Inline Square and Rectangular No Lead Packages (With Optional Thermal
Enhancements) (QFN/SON)
JEP 95, Section 4.8
JEP 95, Section 4.19 Quad No-Lead Staggered and Inline Multi-Row Packages (With Optional Thermal Enhancements)
(QFN)
JEP 95, Section 4.23 Punch-Singulated Fine Pitch Square Very Thin and Very-Very Thin Profile Leadframe-Based Quad
No-Lead Staggered Dual-Row Packages (With Optional Thermal Enhancements) (QFN)
4. www.asme.org
5. www.iec.ch
6. www.jedec.org
4
Copyright IPC
Provided by Accuris under license Copyright IPC International, Bannockburn,
No reproduction or networking permitted without license from Accuris
Order Number: W2478146
Sold to: "RADIOELEKTRONIKA V.I.SHIMKO" [345048100001] - SHINANO@YANDEX.RU,
Not for Resale,2023-12-05 08:06:37 UTC
October 2020
IPC-7093A
3 GENERAL OVERVIEW OF BTCs
This section provides a general overview of BTCs and implementing them into printed board assemblies. The remaining
sections of this guideline provide detailed information on the topics covered in this section.
3.1 BTC Types This section describes some of the most commonly known BTC technologies. See Section 4 for detailed
descriptions of these and other technologies.
BTCs with a thermal die paddle are BTCs incorporating perimeter input/output
(I/O) solder pads which also have an exposed die paddle (under the component body). Soldering of the I/O pads completes
signal, power and ground device connections, while the soldered die paddle enables thermal heat sinking from the device
within the component to the printed board.
3.1.1 BTCs with Thermal Die Paddle
BTCs without a
thermal die paddle are physically identical to BTCs with
soldered thermal die paddles. However, for BTCs without
soldered thermal die paddles, the perimeter I/O pads are
soldered only, as there is no die paddle for these device types.
3.1.2 BTCs without Thermal Die Paddle
Flip chip QFNs (FC-QFNs)
have a unique package construction which is generally outside
the scope of this standard. I/O pads of FC-QFNs have flip chip
bumps that are soldered directly to the printed board.
FC-QFNs do not contain a thermal pad. See Figure 3-1 for an
example of a FC-QFN.
3.1.3 Flip Chip QFN (FC-QFN)
Figure 3-1 Bottom Side of a Flip Chip QFN (FC-QFN)
Showing Irregular Solder Terminations
Note: The example shows three different pad sizes and nonsymmetrical pad orientation.
See IPC-7094 for more information on FC-QFNs.
3.1.4 Land Grid Array (LGA) LGAs are components with an organic laminate and metallic terminations on their bottom
side. These terminations are typically laid out in a regular array. LGAs can be installed in a specially designed LGA socket
or soldered to a printed board with lands that align with the terminations on the LGA.
3.1.5 Other BTC Designations This section outlines commonly known BTC designations. At the time of publication, there
are an estimated > 150,000 different BTC packages available on the market. For the most current listing of BTC types, refer
to JEP 95.
BTCs can be found in many form factors, including those found in Table 3-1. See JESD 30 for surface terminals and
additional classifications. All surface terminal devices are considered BTCs. This statement supersedes descriptions and
classifications in this section, because this component family is very dynamic and constantly evolving.
Table_3-1
Package
Name
Sample Listing of Some Common BTC Designations
Description
JEP 95 Designator
QFN
Quad Flat No-lead
MO-220, MO-241, MO-243. MO-248, MO-250, MO-251,
MO-254, MO-262, MO-263. MO-267, MO-288
PQFN
Power Quad Flat No-lead / Plastic Quad Flat No-lead
MO-208, MO-217, MO-239, MO-247, MO-255, MO-296
SON
Small Outline No-lead
MO-196, MO-197, MO-229, MO-232, MO-240, MO-245,
MO-287
PSON
Power Small Outline No-lead / Plastic Small Outline No-lead
MO-209, MO-252
DFN
Dual Flat No-lead (two, three, four and six pins)
MO-236, TO-276
SOFL
Small Outline Flat Lead (three, four, five, six and eight pins)
MO-293
SODFL
Small Outline Diode Flat Lead (two pins)
DO-219, DO-220, DO-221, DO-222
SOT89
Small Outline Transistor (three or five pins)
TO-243, EIAJ SC-62
TO-277
Transistor Outline (three pins)
TO-277
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Note: A primary reason for the large variety of package types and names is because there was no original standardization
for this package type. The guidance provided in this standard attempts to work within the proliferation of these package
designations.
Be aware that BTCs also may be labeled with a wide variety of industry trade
names. The following is a sample listing of commonly known device manufacturer acronyms. The list does not include all
package instances and is intended for general knowledge only.
3.1.6 BTC Device Manufacturer Acronyms
Note: Naming conventions are dynamic across the industry.
• AQFN – Advanced quad flat no-lead
• BCC – Bump chip carrier
• BCC+ – BCC with a center pad
• BCC++ – BCC+ with a ground ring
• HVQFN – Thermally enhanced very thin quad flat package
• LCC – Leadless chip carrier
• LLP – Leadless lead frame package
• MIS – Molded interconnect substrate
• MLF – Micro lead frame
• MLFD – Micro lead frame dual
• MLFQ – Micro lead frame quad
• MLP – Micro lead package
• MLPD – Micro lead frame dual
• MLFQ – Micro lead frame quad
• QFM – Quad flat module
• TDQFN – Thin dual quad flat no-lead
• TQFN – Thin quad flat no-lead
• UTQFN – Ultra thin quad flat no-lead
• VFQFN – Very thin fine pitch QFN
• VQFN – Very thin quad flat no-lead
• XSON – Extremely thin small outline no-lead
As mentioned in 3.1.6, there are many types of BTCs that go by
various trade names. Unlike the more traditional lead-frame-packaged semiconductors with protruding leads, BTCs are furnished with flat pads or terminations on the bottom of the package. Those terminations are provided on either two sides or
all four sides of the package, in single or multiple rows.
3.1.7 Description of Different Component Structures
BTCs are leadless, similar to a chip scale package (CSP) in
size, with a low profile (≤ 1 mm), excellent thermal dissipation and good electrical performance. Typical BTCs have
solderable terminations that are flush with the bottom of the
device. These devices can also have smaller solderable termination areas located along the perimeter sides, or flanks, of the
package near the bottom of the device.
BTC packages have two types of solderable areas:
1) Solderable I/O pads
2) Thermal pad(s)
Figure 3-2 shows the top of a BTC (left) and bottom of a BTC
(right) without thermal pads.
Figure 3-2 BTC Packages without Thermal Pads (Top and
Bottom View)
Packages can consist of one or more thermal pad areas (see Figure 3-3 and Figure 3-4). Design considerations for I/O and
thermal pad areas are needed. Robust connection for I/O locations is important to ensure adequate functional performance
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of the device. Properly designed thermal pads are required to manage thermal dissipation of the device and current carrying requirements.
Figure 3-4
A
Multiple Thermal Pad Design Example
B
Figure 3-3 Single Thermal Pad QFN Device Example (Top
and Bottom View)
A – Die paddle area
B – I/O (signal, power, ground)
One primary benefit of BTCs is a very low profile. This is a key requirement for newer generations of portable, wireless and
handheld electronic products in which weight and package thickness should be minimized. This trend reduces the semiconductor package outlines and profile for portable handheld devices.
The contact pitch for BTC packages is generally ≤ 1 mm, and the packages tend to be smaller. The body outline dimensions
can be ≤ 1 mm2 or as large as 12 mm2. Due to fine-pitch geometries, this package can accommodate a die element that is
nearly the same size as the package.
Traditional gull-wing leaded packages have very good, long solder joint reliability life compared to leadless components of
the same size. This is because they have very flexible leads. BTCs, however, are not as compliant and may exhibit a relatively shorter solder joint life when subjected to operation in harsh environments. This is because they do not have leads
that can take up stresses and strains introduced by differing coefficients of thermal expansion (CTE) between the package
and the substrate.
Many BTCs are furnished with a Cu lead frame substrate and offer a thermal enhancement by exposing the die-attach pad
on the bottom of the package surface. The die-attach pad provides an efficient heat (and electrical current) path when
soldered directly to the printed board. This enhancement also enables stable ground interface by use of down bonds or by
electrical connection through a conductive die-attach material. Such thermal pads have the potential for large voids and may
even lead to the package floating if the printed solder paste volume on the thermal pad is not tightly controlled.
BTCs come in two formats:
1) Punch-singulated
2) Saw-singulated
While punch-singulated packages are individually punched from a molded strip during final assembly, saw-singulated packages are assembled in array format and separated into individual components during the final sawing operation (see 4.3.1).
Either of these singulation methods can leave the terminal edges without a wettable surface finish.
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Saw-singulated packages are divided into two options:
• Full lead package
• Lead pull-back package
While the full lead package has the whole thickness of the lead exposed on the package sides, the lead pull-back package
has a bottom-half etch lead frame, resulting in only the top half of the lead thickness exposed to the sides of the package.
Figure 3-5 shows the differences in these package configurations.
A
Figure 3-5
B
IPC-7093a-3-5
Saw-Singulated BTC Packages
A - Saw-singulated, full lead
B - Saw-singulated, lead pull-back
As mentioned, one of the greatest benefits of BTCs is their thinness. BTC packages allow much thinner devices than are
possible when using other types of surface mount components. Figure 3-6 shows relative package thicknesses of various
component packages.
B
E
C
D
F
G
A
H
J
K
L
M
N
IPC-7093a-3-6
Figure 3-6
A
B
C
D
E
F
G
H
J
K
L
M
N
–
–
–
–
–
–
–
–
–
–
–
–
–
Package Thickness Comparison
Package height comparison
J-lead
Gull wing
No-lead BTC
PLCC (1.27 pitch, 4.57 height)
MQFP (0.80 pitch, 4.10 height)
LQFP (0.65 pitch, 3.40 height)
TQFP (0.50 pitch, 1.60 height)
TSQFP (0.40 pitch, 1.20 height)
QFN (0.65 pitch, 1.00 height)
QFN (0.50 pitch, 0.80 height)
QFN (0.40 pitch, 0.60 height)
DFN (0.30 pitch, 0.40 height)
While the lack of traditional leads or balls allows reduced package thickness and better electrical and thermal performance,
the low stand-off height makes it difficult to remove any trapped flux residues that remain in and around the solder joints.
If the flux is active, the potential for corrosion increases. It is necessary for the package and printed board to be very flat
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IPC-7093A
to achieve good interconnection, or the potential for opens in solder joints will increase. Since the stand-off height is very
low, solder joint reliability may be a concern in harsher environments.
3.2 Total Cost of Ownership Low package cost is a key driver for widespread use of BTCs. However, the low package
cost may not immediately translate into overall low assembly cost because this package can present challenges in assembly,
inspection and rework.
In practice, the total cost of the final assembly is often greatly impacted by decisions made early in the design process. Too
often, accounting systems track cost in the door but fail to track cost out the door. Purchasing is measured and rewarded by
identifying and procuring at the lowest price, without understanding and fully appreciating the impact on the manufacturing process and long-term reliability of the product and the implied cost of failures. It is incumbent for management to prudently consider and decide on the amount of effort to devote to up-front engineering, including component selection or
package design, solder joint design, printed board design and design verification. Management also should understand and
appreciate the actual piece part cost, which is comprised of several elements (e.g., cost of components, incoming inspection,
assembly, test and final inspection). The decisions made will directly impact product reliability. Table 3-2 lists the key cost
contributors and their impacts on total cost of ownership.
If via-in-pad plated-over (VIPPO) structures are included in the printed board design, expect a 15 % to 20 % increase in the
cost of the printed board assembly. The added cost is primarily associated with the additional process steps needed for
printed board fabrication. Efforts to understand the potential cost increase when using VIPPO via structures is recommended
when deciding upon which BTC design approach to use.
Table 3-2
Cost Contributor
Total Cost of Ownership of BTCs
Impact
Incoming inspection
The incoming component inspection level is a function of the confidence the buyer has in the supplier
being considered related to the cost of the different potential defects which might be encountered and
how they might be resolved. Rework is expensive, but product returns can damage a business.
Component or
package design
To meet cost and reliability targets, a reasonable rule to follow is to select or design the lowest-cost
package that meets the lead count requirement and power dissipation with the largest pitch tolerable
within design constraints. Consideration of the potential change to product specifications to improve
product cost and reliability may be desirable under certain circumstances.
Solder joint quality
The solder joint is the most critical factor in product reliability. Solder volume and solder placement
are critical to yield and reliability of the BTC assembly. The die-attach pad may be of high importance
because some data show reliability is reduced when it is not soldered in place.
Board design
Board materials, via type, layout and land pattern design are all vital and directly affect board cost,
assembly yield and reliability.
Assembly method
The assembly process has several steps, including solder paste deposition, component placement,
reflow and cleaning. The method chosen can represent a relatively minor percentage of overall cost
when done with a well-controlled process, but it can be costly otherwise. In some situations with BTCs,
supplementary process equipment may be needed. While this will add some cost, overall cost will be
reduced by improving yield.
Test and inspection
While it is impossible to inspect quality into a product, test and inspection are commonly used to ensure
process control. Some level of optical, X-ray and electrical test will verify the quality of assemblies.
Assembling BTC devices with solderable flanks can promote improved post-reflow inspection capabilities.
BTC processing steps do not guarantee solderable flanks. Requiring device suppliers to produce BTCs
with solderable flanks may lead to additional processing. Post-reflow inspection that allows bad or
marginal solder joint escapes results in lower end-user confidence and higher total cost.
Reliability
Rigorous design control reduces cost by ensuring reliability. Demonstrating the reliability of a design can
be an expensive process and represent a major upfront cost. However, a failure (especially a field failure)
has arguably even greater cost impact.
3.3 Design and Assembly Process Considerations for QFN Type BTC Packages
3.3.1 Current-Carrying Requirements and Thermal Dissipation The BTC package is often designed to provide excellent
thermal performance by incorporating an exposed die paddle on the bottom surface of the package. However, to take full
advantage of this, the printed board should have features to effectively conduct heat and current away from the package.
This can be achieved by incorporating a thermal pad and thermal vias within the printed board. While a thermal pad provides a solderable surface on the top surface of the printed board (to solder the package die pad to the printed board), thermal vias are needed to achieve a suitable thermal/current path to inner and/or bottom layers of the printed board to remove
the heat and to conduct current.
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Via count and size of vias placed in the exposed-pad soldering areas should be adapted to device requirements. Whereas a
high via count can in principle optimize the electrical and thermal performance of the land, careful balancing of the pros
and cons of different design options for the land needs to be conducted. An open-Cu design allows maximized via count at
low printed board cost, but it can have certain disadvantages. It can lead to solder in vias and the formation of solder protrusions on the opposite side of the printed board, which may be detrimental in double-sided assemblies or in the formation
of short circuits to a conductive housing. Alternative design options may provide a more adequate solution.
3.3.2 Electrical Performance To optimize electrical performance, all circuit traces should be as short as possible. To be
most effective, the input and output capacitors should be placed near the BTC device to minimize parasitic trace inductance.
Using wide conductors for higher voltage in, higher voltage out and ground will help minimize parasitic electrical effects
and enhance thermal transfer between the case and the ambient environment.
BTCs also have superior electromagnetic compatibility (EMC) / electromagnetic interference (EMI) performance over
leaded components.
BTCs will be assembled with other
surface-mount components, including ball grid arrays (BGAs), quad flat packs (QFPs), chip capacitors, resistors, etc. Solder
paste type (mesh size) and stencil thickness should typically be based on the component with the lowest pitch and/or smallest case size on the printed board. This component may or may not be a BTC.
3.3.3 Selection of Solder Paste Type, Stencil Design and Solder Paste Printing
It is important to carefully balance the amount of solder paste
(solder paste coverage) at the thermal pad land. Solder paste
at the thermal pad adjusts the stand-off of the package after
reflow, whereby an increased stand-off can have a positive
effect on thermal cycling life of the I/O solder joints.
Increased stand-off has a positive effect on thermal cycling
life of the I/O solder joints, but too much solder paste may
result in excessive voiding, depending on the land design (i.e.,
open Cu with thermal vias) to solder in vias, and lead to the
formation of solder protrusions. Moreover, floating of the
BTC may result in irregular stand-off, tilting, skew and open
solder joints at the I/O terminations. Section 6 provides information on various design options and their pros and cons.
For I/O solder joints, too little paste will create insufficient or,
most likely, open solder joints. Excessive paste will generate
squeeze balls (solder balls trapped underneath component)
and shorts.
3.3.4 Single Thermal Pad Design A single thermal pad
design entails one large Cu feature within the printed board
land pattern of the BTC. Via holes could also be placed within
this single thermal pad to enhance thermal conduction
(see Figure 3-7).
A
Figure 3-7 Example of a Printed Board Land Pattern with
a Single Thermal Pad Containing Vias
A – Via hole
A multiple-thermal-pads design entails distinct Cu features within the printed board
pad pattern of the BTC. These Cu patterns are separated by solder mask on the surface of the printed board. Figure 3-8
shows two examples of multiple-thermal-pad patterns.
3.3.5 Multiple-Thermal-Pads Design
The lack of a visible solder (toe) fillet on the edge surface of the pins of standard terminations
of BTCs (not plated after sawing or punching) has been a major impediment for the use of BTCs in high-reliability applications. This is because such applications have necessitated that a solder fillet be visible at the outer edge of each contact
to enable a robust inspection for wetting failures by automatic optical inspection (AOI). To enhance this inspection capability of BTC solder joints, notches are made in the standard termination to enable the terminal edge surface to remain plated
after singulation, thereby promoting surface wetting by molten solder during reflow. This termination design is known as a
wettable side flank. Figure 3-9 shows a comparison between a standard termination and an exemplary wettable side flank
termination.
3.3.6 Wettable Side Flank
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IPC-7093A
A
A
B
A
B
A
IPC-7093a-3-8
Figure 3-8
Examples of Printed Board Land Patterns with Multiple Thermal Pads
A – Thermal pad
B – I/O pads
B
A
C
D
E
G
D
F
Figure 3-9
A–
B–
C–
D–
E–
F–
G–
E
F
IPC-7093a-3-9
Comparison of a Standard BTC Termination and a Wettable Side Flank BTC Termination
BTC
Cross-section of a standard termination
Cross-section of a wettable side-flank termination
Mold
Termination
Solderable surface
Unplated Cu surface
3.4 Inspection and Rework
In mass production, in particular high-reliability electronic control units, 100 % solder joint inspection is typically implemented (see 7.11). Automated optical inspection (AOI) generally
is not capable of detecting all possible failure modes for I/O solder joints of BTCs, but it can detect bridging. However,
because the post-package assembly singulation process typically leaves a bare-Cu lead frame at the edge, which is not protected against oxidation and is not easily wetted by molten solder, a solder fillet (toe fillet) does not generally develop.
Therefore, no stable inspection for a visible (toe) meniscus and wetting failures of the component can be implemented. A
refinement of the lead frame structure, to enable a portion of the terminal edge surface to remain plated after singulation,
can overcome this limitation. See 3.5 and 7.11.2.
3.4.1 Quad Flat No-Lead (QFN) Solder Joint Inspection
Automated X-ray inspection (AXI) has the same limitations as AOI concerning
the inspection for wetting by detecting toe fillets. However, alternative inspection features (i.e., based on the capillary effect)
can be devised for AXI (having a much higher sensitivity for the presence/thickness of solder compared to AOI), which
enable inspection of proper wetting of the I/O terminations. AXI can also be used to assess voiding in I/O and exposed pad
solder joints. Whereas voiding in I/O solder joints is typically very limited (< 25 % of the area of the solder joint), higher
voiding levels can occur within the exposed pad solder joints depending on the exposed pad lands design due to their
extended size (i.e., the considerable amount of solder paste (and thus flux) deposited). See 7.11.3 for details about AXI and
8.3.1 for details on voiding.
3.4.2 Automated X-Ray Inspection (AXI)
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3.4.3 Failure Analysis Microsection analysis is a destructive analysis method enabling cross-sectional visualization of
solder joints and assessment of package stand-off heights. It can also be used for assessing relative crack lengths in solder
joints after assemblies have been exposed to field loads (e.g., thermal cycling). Relative crack lengths can also be investigated using the dye penetration technique discussed in 8.4.2.2.2. Neither method is intended for production inspection, but
they can be used for process development and solder joint life assessment.
Rework stations for BTC assemblies should be similar to other rework systems and have
suitable tools to remove and replace faulty components. Hot-gas and laser systems are used for removing components,
redressing the lands and adding the appropriate solder paste or performing and positioning the component before applying
heat.
3.4.4 Rework Considerations
BTCs removed during rework should not be reused within final assemblies. A package that has been removed has been subjected to two reflows. If the assembly is double-sided, the package has been subjected to three reflows. This means the
package is at or near the end of the tested and qualified range of known survivability. These removed BTCs should be properly disposed of so they will not be mixed with fresh equivalent BTCs. See 7.12 for more details on rework and repair of
BTC assemblies.
Polymer-molded Cu leadframe-based QFN and SON semiconductor package families
are the primary platform for low-cost, low-I/O, small-die
applications. When compared with fan-out QFPs and small
outline integrated circuit (SOICs), the bottom-terminal lead
frame design furnishes a significantly shorter conductive path
between the die element and circuit structure. Close coupling
of the die to associated components on the board-level assembly facilitates a positive impact on performance and power
management. Although these small package outlines furnish a
level of economy and enable higher component densities,
early generations of the package did not meet the requirements of all users.
3.5 Needs and Expectations
A primary detractor of the package has been the lack of a visible solder fillet on the edge surface of the Cu contact features.
Although solder joint robustness is not a main concern (number of cycles to failure under thermal cycling typically
decreases only marginally, by up to ~20 %, in the absence of
an outer, visible fillet), users, primarily those involved in
manufacturing products for Class 3 or higher applications,
have insisted that a solder fillet be visible at the outer edge of
each contact to enable a robust inspection of wetting failures
by optical inspection methods (e.g., AOI).
Requests from users to perform a secondary plating or coating process after singulation have been rejected due to cost
factors. Package suppliers have, however, responded with
refinement to the basic lead frame design that enables a
portion of the terminal edge surface to remain plated after
singulation.
Some approaches for introducing such pin modifications are
explained in the following.
A
B
F
C
E
D
Figure 3-10 Step-Cut Quad Flat No-Lead (QFN) Package
Assembly Process
A – Bare L/F strip format top view
B – Die attach and wire bond
C – Mold encapsulation
D – Step cut (additional process)
E – Electroplating (matte Sn)
F – Saw singulation (full cut)
A
B
C
D
Figure 3-11 Sn-Plated Step-Cut Quad Flat No-Lead (QFN)
Lead Frame
A – QFN case profile
B – Bare Cu lead frame end
C – Sn-plated step area
D – Edge visible solder fillet
After package assembly, mold and cure processes, a small-step feature can be established at the end on the Cu terminals by
application of a partial (with respect to the sawing depth) sawing operation. The final process step before singulation electroplates the exposed Cu terminals with a matte Sn alloy (package assembly sequence illustrated in Figure 3-10).
The step-cut lead frame enables the encroachment of the electroplated matte Sn alloy onto the outer edge of the QFN package outline (see Figure 3-11). The plating facilitates solder wetting during reflow solder attachment.
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Another solution can enable a visible toe fillet on the no-lead package. Following the chemical etch or stamp process of the
Cu lead frame array, the bottom surface within the contact area is masked to enable a secondary chemical etch process to
form a shallow concave depression (dimple) in which the plating remains intact during the final singulation operation.
During this singulation operation, the cut is made through the midpoint of the dimple formed in the lead frame array.
Figure 3-12 shows the cut lines for such operations.
IPC-7093a-3-12
Figure 3-12
Concave Depression Etched into the Bottom Surface of the Contact
Figure 3-13 shows cross-sections of a solder joint resulting from this dimple formation compared with that formed with
standard mechanical step-cut process.
A
C
B
C
D
D
E
E
IPC-7093a-3-13
Figure 3-13 Cross-Sectional Representations of Wettable Flank Terminations for Mechanical Precut Process (Left) and
Dimple-Formation Chemical Etch Process (Right)
A – Mechanical precut
B – Chemical etch (dimple)
C – Mold
D – Termination
E – Solderable surface
Figure 3-14 shows microscopic images of common pin modifications, enabling the formation of a visible outer solder fillet.
A
D
B
C
E
IPC-7093a-3-14
Figure 3-14
Microscopic Images of Common Pin Modifications
A – Dimple and punch
B – Saw-plate-saw
C – Dimple and saw
D – Side view
E – Bottom/Side view
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For such pin modifications to be useful in the context of AOI
under series production conditions, a certain minimum wetting
height should be ensured. This is required to distinguish a
wetted pin (good solder joint) from a nonwetted pin (defective
solder joint). Using state-of-the-art AOI systems, a minimum
wetting height of 100 µm enables a robust optical inspection
of solder joints for wetting failures (see 7.11.2).
Recently, BTCs with fully plated terminations, both on the
bottom and outer edges, have been made commercially available (see Figure 3-15 and Figure 3-16). This can be achieved
for some SON/DFN packages with geometrical restrictions as
follows:
• The pads to be plated have to be on two parallel and opposite sides of the package.
• Plating of terminations on all four sides of a package is not
possible with this approach.
A
C
B
Figure 3-15 Transparent View of a DFN Package
Figure Source: Nexperia
A – Chip
B – Metal connection features
C – Side flanks
• The methods require that individual packages are connected
by metal features to the lead frame, which are oriented perpendicular to the I/O pads.
• The metal features can be separated at the final singulation
step.
A possible future option could be the use of electroless
(immersion) Sn to achieve fully wettable flanks for more complex packages. The packages could be fully separated prior to
electroless immersion Sn plating. The challenge is the slow
growth of the Sn layer, limiting the achievable layer thickness
to < 3 µm. However, new Sn plating systems are under development, offering good wetting as plated and after storage.
Figure 3-16 Detailed View on Side Wettable Flank
Features of a DFN Package
Figure Source: Nexperia
4 COMPONENT CONSIDERATIONS
This section provides details on various BTCs from the point of view of the component manufacturer and describes common fabrication methods using lead frames and substrates and common defects associated with each of these processes. This
section also describes the manufacturing process flow for producing different packages as well as geometries, materials and
many standard variations.
Although several small outline semiconductor package innovations have been available (e.g., BGA and fine-pitch ball grid
array (FBGA)), an effective method to significantly reduce package area and cost was not available until the introduction of
SON and QFN package technologies. The most significant feature of these small-outline lead frame package families is their
power dissipation capability and minimal electrical parasitics. Improved thermal dissipation performance comes from the
exposed lead frame that is used to help pull heat out of the die to a mating thermal pad on the printed board. Electrical
parasitics are inherently low due to the small size and short wire bonds.
4.1 General Description of Different BTC Packages
• Package configuration
• Pitch (0.4 mm to 1 mm)
• Termination geometry
• Package thickness
• Thermal pad geometry
• Plating
14
There are several options available when specifying BTCs:
October 2020
IPC-7093A
Figure 4-1 shows examples of some BTCs. These parts are available in a variety of configurations. Table 4-1 shows the configurations of QFN and SON (DFN) that are available from one packaging foundry. Other foundries are likely to have many
of these, as well as some not described in this standard. JEDEC standards list many other size, lead and thickness combinations that result from a general approach. Most of those listed, however, are not in common use.
Figure 4-1
Various Forms of BTC Parts
Table 4-1
Commercially Available Quad-Flat No-Lead (QFN) and Dual-Flat No-Lead (DFN) Package Configurations
Size (mm)
QFN
2x2
3x3
8
3x3
12, 16,
3x3
20
4x3
DFN
Lead Pitch (mm)
Nominal Thickness (mm)
6, 8
0.50
0.90
0.65
0.90
8, 10
0.50
0.90
0.40
0.90
0.50
0.90
4x4
16
12
0.65
0.90
4x4
20,24
0.50
0.90
5x5
20
0.65
0.90
5x5
28, 32
0.50
0.90
6x6
40
0.50
0.90
7x7
48
0.50
0.90
7x7
56
0.40
0.90
8x8
52, 56
0.50
0.90
9x9
64
0.50
0.90
12 x 12
100
0.40
0.90
LGAs are built in comparable sizes to those in the JEDEC
standards and Table 4-1. LGA sizes range from 1 mm x 1 mm
to 30 mm x 20 mm, while LGAs < 5 mm x 5 mm often have
a sensor functionality (e.g., acceleration or pressure sensors)
and LGAs > 5 mm x 5 mm often have a connectivity functionality (e.g., Bluetooth) (see Figure 4-2). Many of the larger
LGA components include multiple-die elements and several
passive devices. These configurations may consist of several
different but complementary functions that together create a
product that can be classified as a system-in-package (SiP).
See 4.6 for more details on LGAs.
IPC-7093a-4-2
Figure 4-2
Device)
Singulated Land Grid Array (LGA) (Bottom of
15
IPC-7093A
October 2020
4.2 Detailed Description and Standards for BTCs
A
4.2.1 Single-Row Molded Lead-Frame-Based Packaging
The die-attach pad (DAP), when exposed outside the mold
compound, serves as a heat spreader. The die element is first
bonded to the DAP surface followed by wire-bond termination
from the die bond pads to the contact features at its perimeter
(see Figure 4-3). The package is completed when the plastic
casing is molded around the die and wire-bond area, exposing
only the bottom area of terminals for solder attachment.
To control the effects of the large surface area of the die-attach
pad feature during reflow, it is necessary to tailor the solder
stencil pattern or alter the mating thermal plane on the printed
board.
4.2.2 Multiple-Row Molded Lead-Frame-Based
Packaging Plastic quad-configured multiple-row no-lead
D
C
Figure 4-3 Basic Single-Row Lead-Frame-Based Small
Outline No-Lead (SON)-Quad Flat No-Lead (QFN) Package
Assembly Model
A–
B–
C–
D–
Die element attached to DAP feature
Wire-bond interface
Bottom exposed contact pads
Bottom exposed DAP
packages (QFNs) are plastic semiconductor packages with
metallized terminals. Terminal contacts are located along the
edges of the bottom surface of the package body arranged in
one, two or three rows. Typical of the single-row QFN, the
multiple-row QFN package is a lead-frame-based product.
Multiple-row QFN lead frames require careful design, are
fragile and are difficult to process. Instead of a lead frame, a
printed board substrate can be used to provide dual-row contacts as described below.
Before wire-bond, the die is bonded to the DAP surface followed by wire-bond termination from the die-bond pads to the
contact features at its perimeter (see Figure 4-4).
B
B
A
D
C
Figure 4-4 Basic Multiple-Row Quad Flat No-Lead (QFN)
Package Assembly Model
A–
B–
C–
D–
Die element attached to DAP feature
Wire-bond interface
Bottom exposed contact pads
Bottom exposed DAP
The package is completed when the plastic casing is molded
around the die and wire-bond area, leaving only the bottom
area of terminals and heat spreader exposed for solder attachment. The die-attach paddle, when exposed, also serves as a heat spreader.
4.2.3 Plastic-Quad, Dual-Inline, Square and Rectangular No-Lead Packages
This section provides some commonly
used names for BTCs. See also Table 3-1.
The plastic-quad, dual-inline, square and rectangular, no-lead packages (with optional thermal enhancements) described in
this section include JEDEC definitions for SON and QFN packaging.
Plastic DFN, which can also be referred to
as SON, is a semiconductor package with metallized terminals located on the bottom of the package. The SON has terminals on only two opposite sides of the bottom surface. By design, these terminals are flush with the bottom surface of the
plastic package body outline.
4.2.3.1 Small-Outline No-Lead (SON) / Dual Flat No-Lead (DFN) Packaging
4.2.3.2 Quad Flat No-Lead (QFN) Packaging Plastic QFN
packages have terminals on all four edges of the bottom surface of the package. The QFN can have a square or rectangular body outline and either symmetric or asymmetric terminal
patterns.
Single-row SON and QFN package technology has become a
viable low-cost methodology furnishing a package outline
only slightly greater than the die. JEDEC defines QFN/SON
as a plastic semiconductor package with metallized terminals
located on the bottom of the package body along its periphery, as detailed in Figure 4-5.
16
Figure 4-5 Terminal Configuration for Single-Row Small
Outline No-Lead (SON) and Quad Flat No-Lead (QFN)
Packaging
October 2020
IPC-7093A
As noted in earlier sections, because the terminal features are flush with the bottom surface of the plastic body and do not
protrude beyond the body outline, these packages are categorized as BTCs or no-lead. In addition, the supplier has the option
of producing an exposed heat spreader element on the bottom surface to assist in transferring thermal rise generated by the
die element into the host printed board structure using solder or thermally conductive compounds.
The JEDEC design guide defines the symbology, algorithms and recommended dimensions and tolerances for a family of
QFN and SON Packages. The guidelines are based on hard metric dimensions and adhere to the geometric dimensioning
and tolerancing principles defined in ASME Y14.5.
Regarding the contact numbering method for the SON package positions in Figure 4-6, Terminal #1 (viewed from the top
surface) is in the lower left corner. Dimension D should then be measured in the horizontal direction. Similarly, measure
dimension E in the vertical direction for both package types. For the QFN, the position of Terminal #1 is perpendicular to
the body edge in the upper left corner, as compared in Figure 4-6.
A
A
B
B
D
C
E
D
Seitenansicht
E
F
G
H
F
J
IPC-7093a-4-6
Figure 4-6 JEDEC-Defined Package Outlines for Single-Row Small Outline No-Lead (SON) and Quad-Flat No-Lead (QFN)
Packaging
A – Terminal #1 index area
B – Top view
C – Side view
D – See A1 detail
E – See exposed heat feature examples
F – See terminal detail
G – See corner terminal detail
H – Bottom view (both types)
J – Bottom view (all types)
17
IPC-7093A
October 2020
The Terminal #1 identifier and terminal numbering convention will conform to JEP 95, SPP-002. The Terminal #1 identifier will be located within the zone indicated on the outline drawing. Top-side Terminal #1 indicator may be a molded or
marked feature. Optional indicator markings or features may also be furnished on the bottom side.
The basic dimension for D and E suggested in the JEDEC design guide are to be in increments of 0.50 mm, ranging from
1 mm to 12 mm. Outlines with D and E increments < 0.50 mm should be registered as standalone outlines. These outlines
should use as many of the algorithms and dimensions stated in this guide as possible to ensure predictability in
manufacturing.
The JEDEC guide acknowledges that differing manufacturing processes by supplier companies will require some flexibility
in the package configuration. Although the primary controlling dimensions will remain common, the terminal geometry may
vary from supplier to supplier.
Figure 4-7 provides an example of two terminal design variations.
A
B
C
E
Figure 4-7
A–
B–
C–
D–
E–
D
IPC-7093a-4-7
Terminal Design Variations for Single-Row Small Outline No-Lead (SON) and Quad Flat No-Lead (QFN) Packaging
Standard (saw cut)
Flange type (molded)
Seating plane
Side view
See A1 detail
There are three terminal variations:
1) Pull-back – The terminals are located completely under the package body outline.
2) No pull-back – The terminals extend all the way to the edge of the package outline.
3) Extended – Terminals extend beyond the body outline (flange type molded version), but the overall measurements do not
exceed the D and E dimensions defined in the guideline.
The terminal contacts may be furnished as illustrated in Figure 4-8. The inner edge of corner terminals may be chamfered
or rounded to achieve minimum gap k. This feature should not affect the terminal width b, which is measured between
0.15 mm and 0.30 mm from the terminal tip, and it should not include the radiused area (if present).
Suppliers will generally furnish components with a balanced depopulation to reduce unequal surface tension forces that may
occur during reflow solder assembly processing. Nonsymmetric package configurations should be separate mechanical outline variations, including depopulation graphics (see Figure 4-9 for three examples). Corner population of terminal features
is also an option on the QFN package. SON and QFN, as mentioned, may be furnished with an exposed portion of the dieattach pad on the bottom surface as shown in Figure 4-10. The bottom exposed die-attach pad may be solid or segmented,
arranged in a matrix format and may have optional corner radii on each segment.
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October 2020
IPC-7093A
A
A
B
L1
(L)
e/2
e
Figure 4-8
L2
L3
e
C
IPC-7093a-4-8
Terminal Contact Layout
A – Datum A or B
B – Terminal tips (may be rounded)
C – Terminal tip
IPC-7093a-4-9
Figure 4-9
Depopulation Schemes for Single-Row Quad Flat No-Lead (QFN) Packaging
IPC-7093a-4-10
Figure 4-10
Corner Terminals and Exposed Heat Spreader
19
IPC-7093A
October 2020
4.2.3.3 Small Outline No-Lead (SON) / Quad Flat No-Lead
(QFN) Terminal Spacing and Dimensions In Figure 4-11,
b
the b dimension represents the width of the metallized terminals (including lead finish) exposed at the bottom surface of
the package. The terminal width (b) will vary as the pitch
dimension narrows as shown in Table 4-2.
The length (L) of the terminal is measured from the edge of
the plastic body. JEP 95, Section 4.8, allows two optional
length dimensions defined as short foot and long foot. The
terminal is classified as a short-foot variation when L nominal
is 0.35 mm to 0.45 mm. If the package terminal dimension L
nominal is 0.50 mm to 0.60 mm, it is classified as a long-foot
variation.
Regarding contact pitch, although six variations are included
in the guideline standard, most products reaching the market
have been supplied with either 0.65-mm or 0.50-mm pitch.
Devices with 0.40-mm pitch are also offered regularly; however, second-level assembly processing requires very strict
control.
Table 4-2
L
IPC-7093a-4-11
Figure 4-11
Metallized Terminal
b – Terminal width
L – Terminal length
Terminal Width Variations for Small Outline No-Lead (SON) and Quad Flat No-Lead (QFN) Packages
Contact Pitch (mm)
Terminal Width (b) (mm)
1.27
0.30
0.40
0.50
1.00
0.30
0.40
0.45
0.80
0.25
0.30
0.35
0.65
0.25
0.30
0.35
0.50
0.18
0.25
0.30
0.40
0.15
0.20
0.25
4.2.4 Punch-Singulated Fine Pitch Square Very Thin and
Ultra-Thin Profile Lead-Frame-Based Quad No-Lead Staggered Dual-Row Packages JEP 95, Section 4.23 applies to
punch-singulated, fine-pitch, square, very thin and ultra-thin
profile lead-frame-based, quad no-lead staggered dual-row
packages (with optional thermal enhancements). The
examples shown in Figure 4-12 represent dual- and triple-row
QFNs with and without optional exposed die-attach pad
features.
QFN is described as a plastic semiconductor package with
metallized terminals located along the peripheral edges of the
bottom surface of the package. As noted, the package terminals are flush with the bottom surface of the plastic package
body, so the packages are considered BTC or no-lead. This
package has two rows of terminals on all four peripheral
edges of the bottom surface of the package (see Figure 4-13).
Figure 4-12
Packaging
Fine-Pitch Two-Row Quad Flat No-Lead (QFN)
The dual-row QFN package may have either symmetric or asymmetric terminal patterns. The terminal A1 identifier should
be located within the zone indicated on the outline drawing. The top-side terminal A1 indicator may be a molded or marked
feature, and an optional indicator on the bottom surface may be furnished as a molded, marked or metallized feature.
20
October 2020
IPC-7093A
A
B
C
D
Figure 4-13
A–
B–
C–
D–
IPC-7093a-4-13
Quad Flat No-Lead (QFN) Dual-Row Package (Top and Side Views)
Terminal # A1 and B1 index area
Top view
Seating plane
Side view
Regarding the description of the package as very thin and ultra-thin, the overall component height is measured from the
seating plane (surface of the host substrate). The very thin (V) version will have a maximum dimension of 1 mm, while the
package defined as ultra-thin (W) configuration has a 0.8-mm height limitation. The uniform square body dimensions are
established in 1-mm increments from 3 mm to 12 mm and, depending on contact pitch (0.50 mm or 0.65 mm), an established maximum terminal count is possible in the two-row configuration (see Table 4-3).
Table 4-3
Body Outline and Maximum Terminal Count
Terminal Count by Pitch
Body Outline (mm)
0.65 mm
0.50 mm
5x5
36
52
6x6
44
68
7x7
60
84
8x8
76
100
9x9
84
116
10 x 10
100
132
11 x 11
108
148
12 x 12
124
164
Note: Maximum terminal counts are calculated using established formulas.
21
IPC-7093A
October 2020
Outlines with D and E increments < 1 mm will likely be registered as standalone outlines. These outlines should use as many
of the algorithms and dimensions stated in this standard as possible to ensure predictability in manufacturing.
Depopulation of terminal features is allowed, but only under the following conditions:
• Depopulation scheme should be consistent in each quadrant of the package.
• Nonsymmetric variations should be broken out as separate mechanical outline variations, including depopulation graphics.
Regarding terminal layout variations, terminals are defined as even- or odd-row spacing, as illustrated in Figure 4-14.
A
B
C
IPC-7093a-4-14
Figure 4-14
Outer and Inner Terminal Layout Variations
A – Datum A or B
B – Inner terminal tip
C – Outer terminal tip
The JEDEC design guide explains that the tolerance that controls the position of the entire terminal pattern (bbb) with
respect to datums A and B cannot exceed 0.10 mm. The center of the tolerance zone for each terminal is defined by the
basic dimension eT as related to datums A and B.
The bilateral profile tolerance (aaa) that controls the position
of the plastic body sides cannot exceed 0.10 mm. The centers
of the profile zones are defined by the basic dimensions
D and E. Center-line-to-center-line spacing between two adjacent rows of terminals (eR) is 0.65 mm for the 0.50-mm-pitch
terminals, and for the 0.65-mm-pitch variation, the spacing is
specified at 0.75 mm. The nominal length (L) specified for the
metallized terminals (including lead finish) exposed at the bottom surface of the package is 0.40 mm with a minimum/
maximum tolerance of 0.10 mm, as illustrated in Figure 4-15
and the dimension included in the figure key. The minimum
separation between the inner terminal tip and the heat spreader
feature and/or between the terminals at the package corners is
0.20 mm.
22
b
A
L
eR
eT
Figure 4-15
Two-Row Terminal Layout
eT – 0.65 mm basic or 0.50 mm basic
eR – 0.75 mm basic or 0.65 mm basic
L – 0.30 mm min. to 0.40 mm max.
b – 0.18 mm min. to 0.30 mm max.
A – Full R (optional)
IPC-7093a-4-15
October 2020
IPC-7093A
The tolerance that controls the position of the optional
exposed metal heat spreader feature is positioned so the center of the tolerance zone will be the datums defined by the
centerlines of the package body. Because the die element is
mounted to the inside surface of the heat spreader, thermal
transfer of any heat generated by the die can be effectively
transferred onto the surface of the host printed board structure.
Although the dimple detail on the top surface of the mold
compound clearly identifies the orientation of the device, the
addition of a small chamfer or notch feature on the exposed
die-attach pad (illustrated in Figure 4-16) further assists in
confirming the location of the A1 and B1 terminal.
4.2.5 Quad No-Lead Staggered and In-Line Multiple-Row
Packages JEP 95, Section 4.19 defines this package family
as a plastic quad no-lead (QFN) having staggered or in-line
multiple-row terminals. Typical of the preceding package configurations, this QFN family is classified as a plastic semiconductor package with metallized terminals located along the
edges of the bottom surface of the package body. The design
guide furnishes the primary outline features of the family of
packaging, which may be laminate-based or plastic molded
lead-frame-based. The primary difference of this variation
from the two previous guidelines is that this guideline details
the requirements for square or rectangular contact terminal
features arranged in two or three rows, typical of those shown
in Figure 4-17.
Figure 4-16
Notch Feature on Exposed Die-Attach Pad
By design, the package terminals are flush with the bottom
surface of the plastic package body, so the packages are considered BTC or no-lead and, as noted, the package has two or
three rows of terminals on all four edges of the bottom surface
of the package.
The package can have a square or a rectangular body as well
as symmetric or asymmetric terminal patterns as detailed in
Figure 4-18 and Figure 4-19.
Figure 4-17 Two- and Three-Row Quad Flat No-Lead (QFN)
Package Examples
23
IPC-7093A
October 2020
B
A
C
C
D
D
IPC-7093a-4-18
Figure 4-18
A–
B–
C–
D–
Basic Two-Row Terminal Layout Variations
Even terminal format
Odd terminal format
Datum A or B
Terminal tip
A
B
C
C
D
Figure 4-19
A–
B–
C–
D–
24
Basic Three-Row Terminal Layout Variations
Even terminal format
Odd terminal format
Datum A or B
Terminal tip
D
IPC-7093a-4-19
October 2020
IPC-7093A
Three contact pitch (e) variations are specified: 0.65 mm,
0.50 mm and 0.40 mm. The dimensions defined for the terminals are adjusted to allow clearance at various pitch conditions. The supplier has the option of selecting uniform or
nonuniform ‘b’ and ‘L’ dimensions to provide a square or
rectangular geometry (see Figure 4-20 and Table 4-4).
e
Table 4-4 Contact Geometries
Dimension b (mm)
L
Dimension L (mm)
Contact
Pitch (e)
min
nom
max
min
nom
max
0.65
0.35
0.40
0.45
0.35
0.40
0.45
0.50
0.25
0.30
0.35
0.25
0.30
0.35
0.50*
0.20
0.25
0.30
0.25
0.30
0.35
0.40
0.15
0.20
0.25
0.20
0.25
0.30
*Optional variation to expand the clearance between terminal features.
b
Figure 4-20
The tolerance that controls the position of the terminals to
each other (e) is nominally defined at 0.05 mm. The tolerance
that controls the position of the entire terminal pattern with
respect to datums A and B is 0.10 mm for 0.65-mm- and
0.50-mm-pitch packages and is reduced to 0.07 mm for the
0.40-mm-pitch package variation. The center of the tolerance
zone for each terminal is defined by the basic dimension e as
related to datums A and B.
Overall package outline dimensions are defined as D for package width and E for package length. The current JEDEC
guideline specifies that D and E dimensions be in increments
of 0.50 mm, ranging from 4 mm to 19 mm. Outlines with D
and E increments < 0.50 mm should be registered as standalone outlines. These outlines should use as many of the algorithms and dimensions stated in this standard as possible to
ensure predictability in manufacturing. The overall package
height is not defined, but the JEDEC guideline recommends a
profile no higher than 1 mm, where the overall component
height is measured from the seating plane (surface of the host
substrate). The unilateral tolerance located above the seating
plane, wherein the bottom surface of all terminals should be
located, is 0.08 mm. This tolerance is commonly known as the
coplanarity of the package terminals. The tolerance, which
controls the top surface of the package, is nominally 0.1 mm.
The basic QFN package outline shown in Figure 4-21 defines
the basic outline features referenced in the preceding for D
(package width), E (package length) and A (overall package
height).
IPC-7093a-4-20
Contact Geometry Variations
A
B
C
D
E
IPC-7093a-4-21
Figure 4-21 Basic Quad Flat No-Lead (QFN) Package Outline Drawing
A–
B–
C–
D–
E–
Terminal # A1 index area
Top view
Detail E
Seating plane
Side view
Terminal A1 identifier should be located within the zone indicated on the outline drawing. The top-side terminal A1 indicator may be a molded or marked feature. The optional indicator on the bottom surface may be a molded, marked or metallized feature. See Figure 4-22 for examples of pin 1 indicator.
25
IPC-7093A
October 2020
A
Figure 4-22
B
IPC-7093a-4-22
Pin 1 Location Option
A – Chamfer corner terminal A1 identifier
B – Circular pad terminal A1 identifier
4.3 Detailed Description of Quad Flat No-Lead (QFN) and Small Outline No-Lead (SON) / Dual Flat No-Lead (DFN)
Packages
4.3.1 Manufacturing Methods BTC package configurations
are frequently used for individual semiconductor chips and
less frequently to package multiple components (see
Figure 4-23).
The outline dimensions of the BTC package family range
from 1 mm x 1 mm outline having only four terminals to
12 mm x 12 mm outline with as many as 108 terminals. The
package height may vary between 0.4 mm to 1.5 mm, but
package heights 0.8 mm to 1 mm are more common. There
are several terminal spacing (pitch) variations allowed on
BTCs, with 0.4 mm, 0.5 mm and 0.65 mm being the most
common.
QFNs and SONs (DFNs) are most commonly assembled on an
etched or stamped metal lead frame that is 0.150-mm to
0.200-mm thick. Figure 4-24 shows the die-attach side of a
multiple-site lead frame panel. Figure 4-25 shows the bottom
side of the panel.
The lead frame panel shown in Figure 4-24 and Figure 4-25
measures 75 mm x 300 mm and includes four sections, each
having 42 QFN sites (7 mm x 7 mm). The bottom, or terminal side, of the lead frame panel will be covered with a protective film that prevents mold compound from encroaching
onto the terminals’ surface during the over-mold process.
Figure 4-23
Various BTC Packages
Lead frames are usually made from rolled sheet Cu etched from both sides with slightly different patterns. The difference
in etch pattern gives the undercut evident in the drawings and sketches in this section. The major purpose for the undercuts
is to provide mechanical interlocking of the mold compound, which leads to increased mechanical strength.
26
October 2020
IPC-7093A
Figure 4-24
Typical Die Attach Side Lead Frame with NiPdAu Finish for QFNs
Figure 4-25
Typical Solder Pad Side of a Quad Flat No-Lead (QFN) Panel with Tape Over the Lead Frame
In preparation for package assembly and to accommodate the eventual mounting of the BTC package, the lead frames are
electroplated with alloys compatible with wire-bond processing and reflow soldering (NiPdAu alloy composition being most
common).
Another option is to spot-plate the wire-bond sites with an Ag alloy, leaving the remaining area of the Cu-based lead frame
without plating until after the over-mold process. The remaining exposed contact and thermal pad features on the panel are
plated with a Sn alloy finish for solder attachment.
Cu is also used replace Au wire in high-volume wire bonding applications. In high volume, the cost savings of Cu vs. Au
is significant, which is why many wire-bonded packages, including BTCs, are produced using that material.
While Cu saves significant cost in volume, much tighter control over the bonding parameters (e.g., ball size, force, temperature, ultrasonic power, duration) is required for high-quality, robust Cu wire bonding for each specific assembly than for Au.
A careful set of experiments (design of experiments (DOE)) is often required to define these Cu bonding parameters for each
chip/substrate combination and assembly. The cost of this DOE is significant, so recovering that cost through the lower cost
of Cu vs. Au requires the production of many parts.
The BTC package assembly process may vary somewhat from one supplier to another, but the basic sequence of assembly
for the product described in the preceding will follow the flow of the diagram detailed in Figure 4-26.
27
IPC-7093A
October 2020
A
B
C
1
2
3
D
8
7
6
5
9
10
11
12
4
IPC-7093a-4-26
Figure 4-26
Quad Flat No-Lead (QFN) Fabrication with Saw Singulation
Note: Process temperatures used at the various assembly steps are dependent on the materials selected.
Blue – Raw material
Yellow – Assembly process step
Green – Finished part
A–
B–
C–
D–
Lead frame
Die-attach material
Die
Mold compound
1
2
3
4
5
6
– Dispense die-attach material
– Place die
– Cure die-attach material (125 °C to 200 °C)
– Au/Cu ball bond (150 °C)
– Place lead frame in cavity mold
– Transfer mold to lead frame (150 °C)
7–
8–
9–
10 –
11 –
12 –
Remove lead frame array from mold
Mark
Saw singulate
Test and bin
Bake (depending on MSL rating)
Package finished part for shipment
Figure 4-27 shows an over-molded version of the lead frame in Figure 4-24. The example is a four-section over-molded
array right after it was removed from the mold. The dark areas are the molding compound that form the four arrays, each
of which measures approximately 45 mm x 55 mm. The dark areas around the periphery and between the molded arrays are
mold compound that fills slots in the lead frame.
Figure 4-27
Over-Molded Lead Frame Configuration
After the over-mold process, individual devices will be marked and singulated from the panel format. The most common
method for singulation of BTCs is using a precision saw. An alternative method uses a punch press operation. For this
method, the mold design will be segmented at each device site to provide access for the die punch. Due to the high cost of
tooling and additional equipment required for punch singulation, this technique is typically reserved for very-high-volume
production.
Figure 4-28 shows the process flow for punch-singulated QFNs.
28
October 2020
IPC-7093A
A
B
C
1
2
3
D
8
7
6
5
9
10
11
12
4
IPC-7093a-4-28
Figure 4-28
Quad Flat No-Lead (QFN) Fabrication with Punch Singulation
Note: Process temperatures used at the various assembly steps are dependent on the materials selected.
Blue – Raw material
Yellow – Assembly process step
Green – Finished part
1
2
3
4
5
6
A – Lead frame
B – Die-attach material
C – Die
D – Mold compound
– Dispense die-attach material
– Place die
– Cure die-attach material (125 °C to 200 °C)
– Au/Cu ball bond (150 °C)
– Place lead frame in cavity mold
– Transfer mold to lead frame (150 °C)
7–
8–
9–
10 –
11 –
12 –
Remove lead frame array from mold
Mark
Punch singulate
Test and bin
Bake (depending on MSL rating)
Package finished part for shipment
The mold design for the punch singulation method is more complex and expensive than those used for saw singulation.
Punch singulation requires a mold with a cavity for each part so the web of the lead frame remains exposed between individual parts. This web is punched out in a single stroke with a die that matches the part.
Saw singulation and punch singulation leave bare Cu edges on the leads where they are cut from the lead frame. These bare
edges can serve as a surface for a solder fillet if the solder system will wet the bare Cu. Some users may also require BTC
suppliers to take additional measures, after singulation, to preserve flank solderability. These measures are intended to allow
users to rely on toe fillets formed along the BTC flanks as an aid to reliable assembly inspection.
The illustrations in Figure 4-29 show the detailed differences that result when using punch singulation and saw singulation.
While punch-singulated packages are individually punched from the molded strip during final assembly, the saw-singulated
packages are assembled in array format and separated into individual components during the final sawing operation.
Figure 4-29
C
C
A
B
IPC-7093a-4-29
Comparing Punch-Singulated and Saw-Singulated Packages with Wire Bond Options
A – Punch-press singulation
B – Saw-cut singulation
C – Die
The image on the left in Figure 4-29 is punch-singulated from an array of individually molded sites. The mold cavity walls
have some draft shown in the sketch to facilitate removing the molded parts from the cavities.
A second characteristic of punch-singulated devices evident in the image on the left in Figure 4-29 is the small lead frame
extension beyond the edge of the molding compound to provide space to prevent the die from cutting the mold compound.
The image on the right in Figure 4-29 shows the saw-singulated cross-section that lacks both draft and the extended lead.
29
IPC-7093A
October 2020
Figure 4-29 also shows the three common wire bond options:
1) Bonds between the die and the finger leads
2) Bonds between the die and the die-attach pad (also known as down bonds)
3) Bonds from the die pad to the finger leads
These wire bond options are used to make the required electrical connections.
Saw-singulated packages are further divided into two options as illustrated in Figure 4-30:
1) No-pull-back (full) lead package
2) Pull-back lead package
While the no-pull-back (full) lead package has the whole
thickness of the lead exposed on the package sides, the pullback lead package has a bottom half-etch lead frame, resulting in only the top half of the lead thickness exposed to the
sides of the package.
The pull-back approach is only viable when the package is
built into an etched lead frame. The pull-back approach provides better capture of the lead, which makes the package
stronger. One disadvantage is that some test sockets may not
be designed to make contact in this area.
A more important disadvantage of the pull-back configuration
is that the solder joint is not visible, making inspection more
difficult. The mold compound blocking access to the pull-back
terminal makes it impossible to form a solder fillet on the
outer edge of the device. While the unplated surface of these
edges that result from both the punching and sawing processes
makes solder wetting difficult, the pull-back configuration virtually guarantees that a fillet cannot form with any soldering
process.
4.3.2 Types of Defects
A
B
IPC-7093a-4-30
Figure 4-30 Example of Half-Etch Pull-Back Contact and
Full-Etch No-Pull-Back Perimeter Contact Configurations
A – Pull-back
B – No pull-back
The following are common defects that result from package fabrication methods:
• Delamination of the mold compound from the lead frame that sometimes results in wire bonds pulling loose from the lead
frame
• Mold compound flash on the leads or die pad that interferes with soldering, die attach or wire bonding
• Voids resulting from incomplete mold compound fill
• Bond wire sweep in the molding process resulting in shorted wires or, less frequently, broken wires
• Smear of Cu during the sawing process along the side of the package, sometimes severe enough to result in shorting, especially during surface mount technology (SMT) solder reflow
• Metallic burrs from the sawing or punching process interfering with the planarity of the part, the electrical clearance, the
wettability or the geometry of the solder joint
• Inadequate tolerance control of part dimensions, especially width and length, resulting in a poor fit to test sockets
• Incorrect marking of pin 1
Table 4-5 shows some examples of common lead frame package defects. The table provides three levels of defects and
highlights the possible causes.
30
October 2020
IPC-7093A
Table 4-5
Defect/Failure Mode
Lead Frame Package Defects and Failure Modes
Potential Failure
Detection Method
Cause
Level 1 – Within Package
Excess moisture due to
inadequate storage or
inadequate drying
Popcorning, delamination
during solder reflow
Hard to detect
Moisture absorption/intake
from the environment when
parts are not properly stored
or dried
Detrimental package
compound voids
Corrosion, delamination
Ultrasonic
Poor molding control or poor
handling
Cracked package
Mechanical and/or electrical
failure
Visual examination, dye
penetrant
Excess mechanical bending of
package, mold compound knit
line
Visual examination
Molding, sawing or punching
process defect
Lead-to-compound joint failure,
Lead falling off or breaking
potentially resulting in lead
wire bond
fall-out
Paddle-to-die delamination
Overheating, wire break, die
cracking
Ultrasonic, decapsulation
Poor wetting, incorrect cure
Broken wires
Electrical open
X-ray
Wire bonding process control
error, mold compound sweep
Lifted stitch / Broken heel to
lead frame
Electrical open
X-ray, electrical test
Wire bond process control
error, surface contamination,
inadequate plating
Lifted wire bond balls from die
Electrical open
X-ray, electrical test
Wire bond process control
error, surface contamination,
die metallization error
Shorted wire
Electrical short
X-ray, electrical test
Mold wire sweep, wire bond
process control
Level 2 – Outside of Package
Nonwetting lead surfaces
Open connection
Visual, X-ray
Oxidized surfaces, plating
contamination or incorrect
thickness
Out of dimensional spec
Poor contact in test socket
Measurement
Molding (thickness) or
singulation
Lead smear of Cu
Shorting of leads
Visual
Sawing conditions
Inadequate flatness
Open joints
Visual
Molding or singulation method
Burrs
Electrical shorts
Visual
Singulation process
Dimples on pads cause by test Void in solder joint and
socket contact
potential open connection
Visual
Aggressive probing breaks
through plating resulting in
nonwetting spot and void in
final joint
Marking defects
Visual
Poor marking, handling
damage
Wrong part or unknown part
Level 3 – Package to Board
Voiding in joints
Long-term electrical open
X-ray
Solder paste or reflow process
Nonwetting of pads
Electrical open
X-ray, electrical test
Part contamination or solder
process
Bridging under package
Electrical short
X-ray, electrical test
Part or board contamination,
solder process
Lift-off of package from printed
board due to floating on the
solder
Electrical open, less shock
resistance
Visual
Too much solder paste
Sinking of package into solder
due to its weight, causing
detrimental solder
displacement resulting in
bridges and/or poor joints
Electrical short
X-ray
Part too heavy for reflow
conditions, paste or solder
rheology at temperature
31
IPC-7093A
October 2020
4.3.3 Marking Alternatives
Common methods of marking BTC packages include:
• Pad printing with a high-contrast ink, usually white
• Laser marking to give finer features that often have low contrast
• Laser marking using an ink that provides good contrast as well as fine features
Plating characteristics are an important part of the lead frame BTC construction. Attachment within
the component package and with external terminations should be carefully addressed for the most robust joint structure.
4.3.4 Materials Used
Lead frames are most commonly made of Cu, and a variety of molding compounds are used. The compound used depends
not only on the part and components within the QFN-SON, but the mold design and molding machine. These molding compounds are formulated to have excellent flow characteristics to ensure fill while minimizing wire sweep.
A variety of lead finishes are used. The most common are NiPdAu and Sn. SnBi is also sometimes used as a plating finish,
as is plated solder using other alloys. Table 4-6 shows some plating variations, while Figure 4-31 shows the thickness relationships of some of the plating combinations.
Table 4-6
Plating Systems Used on Metal Lead Frames
Plating Types
Characteristic Descriptions
Sn plate (10 µm min.)
Most common
NiPdAu (0.508 µm, 0.013 µm and 0.005 µm)
0.4-mm pitch are all NiPdAu
Larger pitches are other systems
(Often called the Samsung finish)
Sn finish with Ag on bond sites
Post-mold Sn plate of bare Cu
NiPdAu (1.02 µm, 0.08 µm and 0.010 µm)
0.4-mm pitch are all NiPdAu
Larger pitches are other systems
(Often called the Shinko finish)
A4
A3
B4
C4
B3
C3
B2
C2
A1
B1
C1
A
B
C
A2
Figure 4-31
IPC-7093a-4-31
Plating Layer Construction Comparison
A – Conventional NiPdAu
A1 – Base material (Cu exclusively)
A2 – Ni 1.020 µm
A3 – Pd 0.080 µm
A4 – Au flash 0.010 µm
B – Ultra-thin pyrolyzed photoresist film (PPF)
B1 – Base material (Cu or alloy 42)
B2 – Ni 0.508 µm
B3 – Pd 0.013 µm
B4 – Au 0.005 µm
C – Enhanced ultra-thin PPF
C1 – Base material (Cu or alloy 42)
C2 – Ni 0.508 µm
C3 – Pd 0.013 µm
C4 – Au 0.008 µm
Solderability testing of BTC components should be conducted in accordance with J-STD-002
and reflow processes (e.g., SnPb, Pb-free or others).
4.3.5 Solderability Testing
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October 2020
IPC-7093A
4.4 Custom Quad Flat No-Lead (QFN) and Small Outline
No-Lead (SON) / Dual Flat No-Lead (DFN) Packaging One
feature of the lead-frame-based QFN family of BTCs is the
relatively low cost and minimal time required to design and
fabricate a custom version. All processes, materials, etc., for
QFNs are described in 4.3. The major method of customizing
is modifying the lead frame.
Figure 4-32 shows several modifications built into one lead
frame. This lead frame is not square, measuring 5 mm x 7 mm
and has seven leads on one side and nine on the other. In
addition, leads on two sides are tied directly to the die paddle.
Another alternative is to split the thermal die pad, which
allows some thermal isolation of individual dies.
Many detailed
variations of QFN and SON (DFN) BTCs have been developed. These are now marketed under a broad number of trademarks and acronyms by various companies, a few of which
are described in this section.
4.5 Description of Commercial Variations
Figure 4-32
Detailed View of a Custom Site for a QFN
4.5.1 Detailed Description of Micro Lead Frame (MLF),
Micro Lead Package (MLP) and Micro Lead Frame Plastic
(MLFP) Components
MLFs, MLPs and MLFPs are all
near-CSP-size plastic-encapsulated quad-contact configured
no-lead (QFN) packages with a Cu lead frame substrate. This
package family uses perimeter lands on the bottom of the
package to provide electrical contact to the printed board.
Typical of all QFN packaging, these variations offer a thermal
enhancement by having the die-attach paddle exposed on the
bottom of the package surface to provide an efficient heat path
when soldered directly to the printed board (see Figure 4-33).
4.5.1.1 Part Descriptions
MLFP are near-chip-size plastic-encased packages that are
JEDEC MO-220 and MO-229 compliant QFN and SON
(DFN) plastic packages. The high-density lead frame package
design is furnished with Restriction of Hazardous Substances
(RoHS)-compliant Pb-free plating and meets the most stringent moisture sensitivity level (MSL) 1. To provide even
greater utilization of package space and enhanced performance, MLPs have the bottom-exposed thermal feature.
Figure 4-34 shows an MLP, a thermally enhanced SON for
power switch technology. Figure 4-35 shows a quad no-lead
MLFP.
Figure 4-33
Package
Example 28 I/O Micro Lead Frame (MLF)
MLFP is a family of JEDEC-compliant QFN plastic packages.
This near-CSP package is available in three versions:
1) The quad (MLPQ) has four sides of I/Os with a body size
range of 3 mm x 3 mm with eight I/Os to 9 mm x 9 mm
with 64 I/Os and body thickness options of 0.9 mm,
0.75 mm and the ultra-thin 0.5 mm.
2) The micro (MLPM) has two sides of I/Os with a body size
range of 2 mm x 2 mm with three I/Os to 3 mm x 3 mm
with 10 I/Os and a thickness of 0.9 mm.
Figure 4-34
Micro Lead Package (MLP)
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IPC-7093A
October 2020
3) The dual (MLPD) versions are designed to provide a footprint compatible replacement for SOIC, shrink small outline package (SSOP), thin shrink small outline package
(TSSOP) and micro small outline package (MSOP).
Typical of most QFN and SON devices, MLPs have an
exposed die-attach pad for improved thermal performance.
However, nonexposed pad options are available, such as chip
on lead (COL), flip chip on lead frame (FCOL) and other special applications.
The MLFP is also a JEDEC standard package outline (MO220). Figure 4-35 illustrates a section view of a 16-lead MLFP
package. The die pad and perimeter I/O pads are fabricated
from a planar Cu lead frame substrate. This family is
described as a plastic-encapsulated device with a bottom dieattach pad and contacts.
IPC-7093a-4-35
Figure 4-35
Micro Lead Frame Plastic Package (MLFP)
The die pad and perimeter I/O pads are fabricated from a planar Cu lead frame substrate. This is encapsulated in plastic
with the bottom of the DAP and I/O pads exposed to create a very small package outline. In addition to furnishing a small
outline, the package has minimal mass and can be processed using existing package assembly infrastructure.
Dimensions and tolerances conform to ASME Y14.5, all dimensions are in mm and angles
are in degrees. Figure 4-36 represents the basic QFN package outline.
4.5.1.2 Package Tolerances
0.60
MAX.
C
0.60
MAX.
A
D
B
5
6
IPC-7093a-4-36
Figure 4-36
A–
B–
C–
D–
34
JEDEC MO-220 Package Outline
Chamfered corner optional 4X
Datum A
Datum B
See detail B (Figure 4-37)
October 2020
IPC-7093A
The QFN family detailed in JEDEC MO-220 ranges in size
from 2 mm x 2 mm to 12 mm x 12 mm, graduating in 0.5-mm
increments. For each outline there are two lead spacing formats: odd and even. The illustration shown in Figure 4-37
represents the even-row variation. There are five contact pitch
variations allowed for the QFN: 1 mm, 0.8 mm, 0.65 mm,
0.5 mm and 0.4 mm. The length (L in Figure 4-37) and width
of the contact can vary significantly between suppliers.
Although square outlines are most common, rectangular outlines are allowed. The examples shown in Table 4-7 represent
some available square and rectangular QFN package outlines.
A
L
5 L1
e/2
Figure 4-37
IPC-7093a-4-37
QFN Contact Design
A – R is optional
Table 4-7
B
e
B – Terminal tip
Typical Package Outline and I/O for QFN
Body Size (mm)
QFN Lead Counts
(0.8-mm, 0.65-mm,
0.5-mm and 0.4-m pitch)
DFN/SON Lead Counts
(1.27-mm, 0.95-mm and
0.5-mm pitch)
Dual-Row Lead Counts
(0.5-mm pitch)
< 2 x 2 (saw only)
–
4/6/8
–
2x3
–
6/8
–
3x3
4 / 8 / 10 / 12 / 16
8 / 10
–
4x4
12 / 16 / 20 / 24 / 28
–
–
5x5
16 / 20 / 28 / 32 / 36
–
44 / 52
6x5
36
8
–
6x6
20 / 28 / 36 / 40 / 48
–
60 / 68
7x7
28 / 32 / 44 / 48 / 56
–
76 / 84
8x8
32 / 40 / 52 / 56 / 68
–
92 / 100
9x9
36 / 44 / 60 / 64 / 76
–
108 / 116
10 x 10
44 / 52 / 68 / 72 / 88
–
124 / 132
11 x 11
–
–
140 / 148
12 x 12
48 / 60 / 84 / 88 / 100
–
156 / 164
4.5.1.3 Material Specification QFN packages are available in several alloy finishes: post-plated SnPb, matte Sn, SnBi and
preplated NiPd with Au flash. Studies on parts plated with NiPd and matte Sn have shown no significant difference compared to SnPb finish parts. The following are typical of the basic materials used for QFN package assembly:
• Die thickness: 250 µm ± 50 µm (thinner for special applications)
• Plating: SnPb, matte Sn, SnBi, NiPd (flash Au)
• Marking: Laser
• Lead frame: Cu alloy, dual gauge
• Die attach: Conductive epoxy
• Bond wire: 25 µm low loop
• Mold compound: Pb-free / Green capable
35
IPC-7093A
October 2020
4.5.2 Detailed Description of Leadless Lead Frame Package (LLP) and Lead Frame Chip Scale Package (LFCSP)
Components
4.5.2.1 Part Description LLPs and LFCSPs are near-chipscale plastic-encapsulated wire-bond QFN packages with a Cu
lead frame substrate in a BTC package format.
LLPs and LFCSPs are available in two thicknesses variations.
The most prevalent thickness is 0.8 mm, but the packages are
also available in a 0.6-mm profile thickness. Perimeter I/O
pads are located on the outside edges of the package. Electrical contact to the printed board is made by soldering the
perimeter pads and exposed paddle on the bottom surface of
the package to the printed board. Heat is efficiently conducted
from the package by soldering the exposed thermal paddle to
the printed board, as illustrated in Figure 4-38.
Stable electrical ground connections are provided through
down bonds and conductive die-attach material. Wire bonding
is provided using Au wires. Perimeter and thermal pad finish
are plated as 100 % Sn, but SnPb also is available. Packages
are punched or sawed from a molded strip during final assembly. Half-etching the lead frame provides mold compound
locking features for the perimeter pads and die thermal
paddle. This package is currently characterized as MSL 3. See
J-STD-020 for MSL levels.
B C
A
D
E
F
IPC-7093a-4-38
Figure 4-38
A–
B–
C–
D–
E–
F–
Lead Frame Chip Scale Package (LFCSP)
Die pad
Gold wire
Molding compound
Exposed thermal paddle
Pin 1
Perimeter I/O pads (leads)
Terminal contacts:
• The contact pads (or solder pads) are located peripherally in
a single-row format depending on the specific number of
pins and body size.
• For certain specific applications, the packages are incorporated with common power and/or ground pins.
• All contacts are plated with matte Sn solder for ease of surface mount processing.
The bottom termination QFN package family (JEDEC
MO-220) furnishes enhanced chip speed, reduced thermal
impedance and, because of its small outline, minimized
printed board area required for mounting. The small size and
very low profile make this package, shown in Figure 4-39,
ideal for high-density printed boards used in small-scale electronic applications (e.g., handheld devices).
Figure 4-39
Leadless Lead Frame Package (LLP)
In addition to their small package outline and low profile, LLPs and LFCSPs have low thermal resistance and reduced electrical parasitic.
36
October 2020
IPC-7093A
4.5.2.2 Package Tolerances The JEDEC design guideline
for this package family applies to packages with optional thermal enhancements as well as various height profiles and
pitches. This package has terminals on all four edges of the
bottom surface of the package. LLPs and LFCSPs can have a
square or rectangular body outline as well as symmetric or
asymmetric terminal patterns. Versions of the package may
also have terminals placed in the corners at 45° to neighboring leads. The basic dimensions for the package outline are
shown in increments of 0.5 mm, ranging from 1 mm to
12 mm. The outline detail shown in Figure 4-40 illustrates the
primary dimensions used when developing the land pattern
and thermal paddle geometries.
D
BSC
C
E
BSC
A
Table 4-8 details the width of the metallized terminals (including lead finish) exposed at the bottom surface of the package.
D
For component tolerances and profile tolerances usually given
in the package outline, drawings are converted into maximum
material condition (MMC)- and least material condition
(LMC)-based tolerances.
37
36
C
48
1
b
Table 4-8 Leadless Lead Frame Package (LLP)
and Lead Frame Chip Scale Package
(LFCSP) Contact Pitch and Width Variations
B
E2
Terminal Dimensions (mm)
Contact Pitch
(mm)
Minimum
Nominal
Maximum
0.65
0.25
0.30
0.35
0.50
0.18
0.25
0.30
0.40
0.15
0.20
0.25
L
25
24
12
13
0.25 MIN
5.50
REF
4.5.2.3 Material Specifications To comply with RoHS and
the Waste Electrical and Electronic Equipment (WEEE)
Directive, companies modified molding compounds and, in
some cases, die-attach materials. In addition, they converted
mold compounds to more robust versions, so packages are
compatible with higher temperatures required for reflow with
Pb-free alloys. The data supplied in Table 4-9 are typical of
the device packaging materials listed in LLP and LFSCP
materials declaration forms.
A
IPC-7093a-4-40
Figure 4-40 Typical Leadless Lead Frame Package (LLP)
and Lead Frame Chip Scale Package (LFCSP) Outline Detail
Figure source: Analog Devices
A – Top view
B – Exposed pad (bottom view)
C – Pin 1 indicator
D – Pitch
Table 4-9 Basic Material Elements for the Leadless Lead Frame
Package (LLP) and Lead Frame Chip Scale Package (LFCSP) Devices
Category
Mold compounds
Die-attach material
Lead frame
Materials
Content (%)
SiO2 fillers
Epoxy and phenol resins
C black
86.9
12.8
0.3
Ag
Epoxy resin
Metal oxide
Curing agents
Gamma-Butyrolactone
73.4
18.35
2.75
2.75
2.75
Cu
Fe
Zn
P
97.5
2.35
0.12
0.03
37
IPC-7093A
October 2020
The change to RoHS-compliant elements has resulted in base material sets that demonstrate the capability to meet elevated
reflow conditions of 255 °C (+ 5 °C / - 0 °C) for Pb-free reflow. Additionally, most suppliers offer Pb-free lead finish on
all plastic-encased LFCSP packages from SnPb15 to 100 % Sn (Sn plating) to eliminate Pb from these package types. Other
material elements:
• Ag internal lead frame plating
• Sn external lead frame plating
• Au bond wires
• Si die element
Although no change may be made to a component part number, products converted to Pb-free should be identified in accordance with J-STD-609.
4.6 Land Grid Arrays (LGAs) LGAs typically consists of a
substrate with metallized pads on the secondary side to make
connection to the next-level assembly. LGAs may consist of
active and passive components, which are protected using
either an over-mold or air-cavity lid. The basic benefit of
LGAs is the ability to assemble multiple components
(e.g., die, passives) into one package with the ability to route
on multiple layers without the need to separately package each
individual component. This normally would constitute a larger
overall footprint on a next-level assembly. LGAs have many
aspects to their construction:
• Package configuration
• Pitch (varies)
• Termination geometry
• Land pattern geometry
• Package thickness
Figure 4-41
Examples of Land Grid Array (LGA) Packages
• Thermal pad geometry
• Plating
Termination geometry, land pattern geometry, package configuration, etc., typically are custom to the specific part due to
electrical performance requirements.
Figure 4-41 shows examples of LGAs.
LGAs have an advantage over BGAs in terms of heat dissipation, because they use a thermal pad rather than relying on
individual spheres to assist in the thermal dissipation. Because there are no protruding leads, LGAs exhibit minimal parasitic losses due to their very low electrical resistance and capacitance. Heat transfer from the package to the printed board,
however, is primarily dependent on the construction of the substrate and whether a thermal pad or other heat sink technology is used in the package (i.e., thermal slug to dissipate heat to the next-level printed board).
Inspecting LGAs poses challenges, because the operator may not be able to see side solder fillets, which may be seen on
other BTCs with cut-metal lead frames, and they may look nonwetted or dewetted. If plating is on the side metal, dewetted
and nonwetted side fillets may indicate solder bonding problems. This is in contrast to BGAs, which allow inspection by
endoscope.
Although some users select LGAs for their favorable versatility and potential reduction in footprint area on a next-level
assembly, their cost factor, similar to BGAs, is typically higher than other standard BTC lead frame components.
LGAs have become widely used for semiconductors requiring electrical performance and improved thermal management.
Assembly processing, however, requires careful attention to process control, from solder material selection, deposition,
package placement to solder reflow profile. To ensure reliable mounting and assembly of LGAs, printed boards should
exhibit minimal warp, and the land patterns should provide a uniform surface finish.
One drawback with LGAs is the potential for flux entrapment under LGAs. This is a concern in any BTC package, but it
is of major concern when using LGAs since they tend to be larger. If the manufacturing facility uses aggressive watersoluble flux or solder paste, it is advisable to consider changing to no clean solder paste or flux when using LGAs.
38
October 2020
IPC-7093A
LGAs are available in sizes comparable to those in JEDEC standards. LGAs
are typically larger than 3 mm x 3 mm and can be built using
a double-sided or multilayer substrate. Many laminate-based
LGAs include multiple die elements and a number of passive
devices. These configurations may consist of several different
but complementary functions that together create a product
that can be classified as a SiP. Figure 4-42 shows an example
of air cavity and over-molded LGA constructions.
4.6.1 Land Grid Array (LGA) Construction
LGAs are constructed very similar to BGAs. The main difference is the termination connection to the next-level printed
board. Figure 4-43 shows a typical process flow for the
assembly of a BGA. The process steps highlighted in yellow
show the main differences between the process used to
assemble BGAs vs. those used for LGAs. Figure 4-44 shows
a sample process flow of an LGA using a molded package. In
comparison, Figure 4-45 shows an LGA process flow that uses
a lid-attach process instead of using an over-mold.
C
D
E
G
F
A
B
Figure 4-42 Air Cavity and Over-Molded Land Grid Array
(LGA) Constructions
A – Air cavity LGA
B – Over-molded LGA
C – Lid
D – Wire bond
E – Die
F – Substrate
G – SMT component
H – Mold compound
C
A
H
E
G
B
D
H
L
F
J
M
K
N
O
P
IPC-7093a-4-43
Figure 4-43
A–
B–
C–
D–
E–
Sample Ball Grid Array (BGA) Process Flow
Start
Known good die
Die attach
Chip attach using flip chip process
Wire bond
F – Underfill die
G – Mold package
H – Apply flux or paste on BGA substrate lands
J – Place balls on BGA substrate lands
K – Reflow balls on BGA substrate lands
L–
M–
N–
O–
P–
Perform AOI
Perform electrical test
Inspect
Pack
Ship
39
IPC-7093A
October 2020
A
B
C
1
2
3
4
D
9
8
7
6
5
10
11
12
13
14
16
15
E
IPC-7093a-4-44
Figure 4-44
Sample Molded Land Grid Array (LGA) Process Flow
Note: Process temperatures used at the various assembly steps are dependent on the materials selected.
Blue – Raw material
Yellow – Assembly process step
Green – Finished part
A–
B–
C–
D–
E–
Printed board
Solder paste
SMT components
Die
Mold compound
1
2
3
4
5
6
7
– Deposit solder paste (stencil/dispense)
– Place SMT components
– Reflow solder (183 °C to 260 °C)
– Aqueous clean
– Dispense die-attach material
– Place die
– Cure die-attach material
(125 °C to 200 °C)
8 – Wire bond (150 °C)
A
B
C
1
2
E
9–
10 –
11 –
12 –
13 –
14 –
15 –
16 –
3
4
D
9
8
7
6
5
10
11
12
13
14
15
Figure 4-45
Place circuit array in mold
Transfer mold circuit array (150 °C)
Remove array from mold
Mark
Saw singulation
Test and bin
Bake (depending on MSL rating)
Package finished part for shipment
IPC-7093a-4-45
Sample Air Cavity Land Grid Array (LGA) Process Flow
Note: Process temperatures used at the various assembly steps are dependent on the materials selected.
Blue – Raw material
Yellow – Assembly process step
Green – Finished part
A–
B–
C–
D–
E–
40
Printed board
Solder paste
SMT components
Die
Lid
1
2
3
4
5
6
7
– Deposit solder paste (stencil/dispense)
– Place SMT components
– Reflow solder (183 °C to 260 °C)
– Aqueous clean
– Dispense die-attach material
– Place die
– Cure die-attach material
(125 °C to 200 °C)
8 – Wire bond (150 °C)
9 – Attach lid
10 – Cure/Reflow lid attach material
(depends on material used)
(125 °C to 260 °C)
11 – Mark
12 – Saw singulation
13 – Test and bin
14 – Bake (depending on MSL rating)
15 – Package finished part for shipment
October 2020
IPC-7093A
4.6.2 Manufacturing Methods for Substrate-Based LGAs This section provides more detail on some of the main areas
that make up the construction of the LGA as shown in the process flows and construction variables options in 4.6 and 4.6.1.
4.6.2.1 Substrate Construction Substrate-based packages are similar to lead-frame-based packages in many ways. Many
devices that can be packaged using the lead frame approach can also be packaged using a substrate. Due to cost and reliability, substrates are used as an alternative to lead frames.
Substrates are sometimes used for individual die but more
commonly to interconnect and package multiple active and
passive components. Many of these assemblies are SiPs,
implying at least two active components. Others that do not
comply with the SiP definition are simply high-density electronic assemblies. The density is increased by using direct die
attach, stacking die, flip chip assembly or SMT components.
Substrates used for LGAs can be double-sided or multilayer
printed boards, often built with BT dielectric and frequently
implemented utilizing HDI technology. Figure 4-46 and
Figure 4-47 show both sides of a typical substrate for an LGA
part. Depending on the design requirements the laminate
structure may or may not contain a center thermal pad to dissipate heat. Some constructions may also incorporate embedded heatsink technology to dissipate heat.
Depending on the performance requirements of the LGA, an
HDI process may be needed in the overall design, which may
include filled microvias, planarized surface, thin line or the
use of high-performance thin materials.
Figure 4-46 Top (Primary) View of Land Grid Array (LGA)
Printed Board
Figure 4-47 Bottom (Secondary) View of Land Grid Array
(LGA) Printed Board
A variety of board finishes are used for LGA assembly. Since most LGA substrate-based packages incorporate some wirebonded die, Au finish on at least the component surface of the substrate is common. A typical system is NiPd with an Au
flash that is wire-bondable, solderable and avoids the risk of solder embrittlement.
The substrate shown in Figure 4-46 and Figure 4-47 measures ~75 mm x 300 mm. The bottom surface of the substrate is
eventually soldered to the printed board. Sites marked with an X were found to be defective during board test and will not
be populated. This substrate does not have a large pad in the center, as many QFNs have, because the final package does
not dissipate a lot of heat, so a good thermal connection between the LGA and printed board is not required.
Figure 4-46 shows the top surface of the substrate where parts are placed. SMT parts from 0402 down to 01005 are commonly used, although components smaller than 01005 are also used in some cases. Die interconnect is either wire bond or
flip chip, often with multiple die. Twenty-five parts in a 7 mm x 7 mm size is common. Many of these assemblies are SiP.
4.6.2.2 Sealing As described in 4.6, LGAs may be over-molded or contain a lid which protects the components inside. A
variety of molding compounds are used. The choice of molding depends not only on the part and components within the
LGA, but the mold design and molding machine. These molding compounds are formulated to have excellent flow characteristics to ensure fill while minimizing wire sweep. They also are formulated to have a CTE that is close to Cu and to comply with environmental requirements. If the LGA is constructed using a lid, the lid may be made from metal, laminate or
some other polymer material, and it may be attached to the substrate using epoxy or solder. One common issue with an
epoxy attach is the epoxy tends to outgas during the attachment process, so a vent hole in the lid is sometimes used to allow
the gases to escape. That vent hole may be sealed later or left unsealed depending on the application.
4.6.2.3 Marking Alternatives
Common methods of marking LGAs are:
• Pad printing with a high contrast ink, usually white
• Laser marking to give finer features (often furnishes a low-contrast image)
• Laser marking onto a printed ink background (provides good contrast and fine features)
• Vibro peen marking (line quality may depend on material/plating)
41
IPC-7093A
4.6.3 Types of Defects
October 2020
Some common defects associated with LGA assembly include:
• Delamination of the mold compound from the substrate that results in pulling parts off the substrate
• Cracking, separation or voids in the lid-attach medium
• Mold compound flash on the leads that interferes with soldering
• Voids resulting from complex internal geometry that is hard to fill or from mold compound that does not flow for some
reason
• Wire sweep in the molding process resulting in shorted wires or, less frequently, broken wires
• Saw-singulation-induced defects such as delamination of the mold compound from the substrate
• Warpage from the molding process or inherent in the substrate that interferes with the planarity of the part or geometry of
the solder joint
• Movement or sweeping off of SMT parts due to excessive temperature rise during the molding process
• Moisture ingression by the part during storage resulting in delamination during solder reflow
Table 4-10 provides some examples of common substrate-based package defects across three levels of defect potential and
highlights the possible causes. Many of the defects are similar to what would be seen with the use of BGA packages. The
main differences, however, are the defects associated with coplanarity in terms of the spheres and shape differences of the
spheres, which are now dictated by the terminations on the bottom of the LGA.
4.6.4 Assembly Challenges Mounting Land Grid Array (LGA) Packages When attaching an LGA, some of the same concerns need to be addressed as compared to attaching a standard QFN or BGA device, with some added challenges. LGAs
may be warped as received due to inherent flatness issues associated with the laminate/substrate material or CTE-related
issues. This warpage can lead to opens and shorts during solder attach or voids in the thermal plane attach. Additional warpage can also occur during reflow when the device is exposed to added heat, causing further CTE issues or bowing of the
substrate due to a volumetric air expansion within the device (if the device is an air-cavity component). There are various
ways to help improve the attachment process. See 4.6.4.1 and 4.6.4.2 for information on solder paste selection, solder dispense and stencil design.
4.6.4.1 Solder Paste Selection As with soldering standard BTC components such as QFNs, flux can get trapped under
the LGA device during solder attachment. Paste with a no clean flux should be used when attaching LGA devices to the
next-level assembly. The type of paste is primarily determined by the aperture opening in the stencil and whether the paste
is Type III, Type IV, Type V, etc. Other components on the assembly may dictate the type of paste to be used.
4.6.4.2 Solder Dispense / Stencil Printed When attaching the LGA to the next-level assembly, solder deposited on the
mating land can be dispensed or stencil printed. If a stencil is used, the typical thickness is 0.1 mm to 0.15 mm. The aperture design is contingent on the land pad layout and any warpage in the LGA device. The solder volume deposited should
be balanced across the device. If no solder mask is used in the ground plane, a windowpane construction should be used to
help minimize voiding. Depending on the aperture sizes, a nanocoating may be needed on the screen to help the paste-release
process.
It is recommended to print the solder paste in a pattern that will avoid covering via holes to avoid solder filling of vias during printing. The amount of solder paste should be carefully balanced. It is important to assess how much solder (volume V)
needs to be applied for an exposed-pad solder joint to provide sufficient soldering area and no excess solder in the vias.
Solder in vias carries the risk of solder protrusions. If such protrusions cannot be tolerated, solder penetration into the vias
should be avoided.
Careful analysis of the overall thermal performance is required to determine an appropriate minimal solder coverage.
4.6.5 HDI Process As in the construction of the LGA, depending on the performance requirements of the LGA, an HDI
process may be needed, which includes thermal pad structures on the mating printed board incorporating filled microvias
and planarized surfaces. Inclusion of HDI vias in thermal pads is becoming more important as component package sizes
continue to shrink.
42
October 2020
IPC-7093A
Table 4-10
Defect/Failure Mode
Substrate-Based Land Grid Array (LGA) Defects and Failure Modes
Potential Failure
Detection method
Cause
Level 1 – Within Package
Excess moisture content
due to inadequate storage
or drying
Popcorning, delamination
during solder reflow
Hard to detect
Moisture absorption/ingression
from the environment when
parts are not stored or dried
properly
Detrimental package
compound voids
Corrosion, delamination
Ultrasonic
Poor molding control
Cracked package
Mechanical and/or electrical
failure
Ultrasonic
Poor molding control or poor
handling
Substrate-to-compound failure
Broken connection, corrosion
from water ingress
Visual examination, dye
penetrant
Molding or sawing process
defect
Part-to-substrate delamination
Open circuit, die overheating,
bond wire break, part cracking
Ultrasonic, decapsulation,
cross-sectioning
Inadequate mold compound
flow, poor wetting of parts
and substrate, surface
contamination
Broken wire bonds
Electrical open
X-ray
Wire bonding process control
error, mold compound sweep
Lifted wire bond stitch /
Broken heel-to-substrate
Electrical open
X-ray, electrical test
Wire bond process control
error, surface contamination,
inadequate plating
Lifted wire bond ball from die
Electrical open
X-ray, electrical test
Wire bond process control
error, surface contamination,
die metallization error
Shorted wire
Electrical short
X-ray, electrical test
Mold wire sweep or wire bond
process control
Cracked lid-attach seal
Lid falls off
Visual inspection
Reflow process causing CTE
issues
Level 2 – Outside of Package
Nonwetting lead surfaces
Open connection
Visual, X-ray
Oxidized surfaces, plating
contamination or thickness
Out of dimensional spec
Poor contact in test socket
Measurement
Molding (thickness) or
singulation
Inadequate flatness
Open joints
Visual
Substrate defect, molding or
singulation method
Dimples on pads caused by
test socket contact
Void in solder joint and
potential open connection
Visual
Aggressive probing breaks
through plating resulting in
nonwetting spot and void in
final joint
Marking defects
Wrong or unknown part
Visual
Poor marking, handling
damage
Level 3 – Package to Board
Voiding in joints
Long-term electrical open
X-ray
Solder paste or reflow process
Nonwetting of pads
Electrical open
X-ray, electrical test
Part contamination or solder
process
Bridging under package
Electrical short
X-ray, electrical test
Part or board contamination,
solder process
Lift-off of package from printed
board due to floating on the
solder
Electrical open, less shock
resistance
Visual, cross-section
Too much solder paste
Sinking of package into
solder due to its weight
causing detrimental solder
displacement and resulting
in bridges and/or poor joints
Electrical short
X-ray, cross section
Part too heavy for reflow
conditions, paste or solder
rheology at temperature
43
IPC-7093A
October 2020
5 PRINTED BOARDS AND OTHER MOUNTING STRUCTURES
Printed boards and other similar types of interconnection platforms serve as mounting structures for BTCs and other components. There is a wide variety of mounting structures available to fulfill various interconnection substrate requirements.
These structures use many types of organic and inorganic materials and have a wide range of physical properties. Materials
are normally chosen based on cost/performance needs of the finished product. Interconnect structures used for mounting and
assembling BTCs should meet the requirements of the IPC-6010 series, based on the type of structure being used (e.g., rigid
printed board, flexible printed board, HDI). See IPC-7095 for more details about substrates.
While single- and two-metal-layer boards are common, multilayer
interconnection structures are commonly required to support the interconnection of BTCs for high-performance electronics.
High-density routing difficulties associated with BTCs may also require the use of build-up layers using microvias. The types
of microvias which can be created for the build-up HDI layers depend on the equipment used by the manufacturer. See
IPC-2226 for design requirements and standardized design types for HDI printed boards.
5.1 High-Density Interconnect (HDI) Build-Up Layers
The base materials used to produce the mounting structure for the BTC assembly
should meet the requirements of IPC-4101. That standard provides specific details and dozens of technical specification
sheets for ordering base materials. It is important to discuss these attributes with the printed board manufacturer to ensure
the most appropriate and cost-effective materials will be used for the base mounting structure. These attributes include thermal expansion, glass transition temperature (Tg) and time to delamination (Td).
5.2 Base Materials Considerations
5.3 Moisture Absorption Most organic materials are hygroscopic to some degree and soak up moisture at different rates;
some do so relatively rapidly. Moisture absorption changes electrical properties (e.g., loss tangent) and processing characteristics (e.g., outgassing, which can result in blisters) of materials, and it can affect physical dimensions and laminate
weight.
IPC-1601 defines handling and storage guidelines to reduce moisture absorption as well as test procedures to determine the
moisture content in a printed board. It also provides baking recommendations to remove moisture from printed boards before
assembly.
5.4 Surface Finishes The primary purpose of a surface finish is to prevent oxidation of exposed Cu on the printed board.
This ensures the surface is solderable when BTCs are mounted. Surface finishes should also provide a flat surface for solder
paste printing and BTC mounting. Although BTCs are the focus of this standard, other components and the assembly process should be considered when choosing the most appropriate surface finish.
There is no ideal surface finish that is best suited for all applications. Table 5-1 provides some of the application features
that need to be considered in selection of a suitable surface finish.
Use caution when handling printed boards, because salts from hands can damage the surface finish, especially organic
solderability preservatives (OSPs). To achieve maximum shelf life with any surface finish, proper packaging and storage is
a requirement. IPC-1401 provides guidelines and requirements for proper handling of printed boards.
44
October 2020
IPC-7093A
Table 5-1
Key Attributed of Various Printed Board Surface Finishes
Immersion Ag
Electroless
Ni/Electroless
Palladium/
Immersion Au
(ENEPIG)
Immersion Sn
One year
One year
One year
Six months
Normal
Normal
Avoid physical
contact
Normal
Avoid physical
contact
Flat
Flat
Flat
Flat
Flat
Flat
Good
Good
Good
Good
Good
Good
Good
Hole fill after
multiple reflow
cycles (two
times)
Good
May have
problems after
two reflows
Good
Good
Good
Good
May have
problems after
two reflows
Use on thick
printed boards
No Holes
difficult to fill
and clear
Yes
Ni improves
hole reliability
Ni improves
hole reliability
Yes
Ni improves
hole reliability
Yes
Use on thin
printed boards
No
Prone to
warping
Yes
Yes
Yes
Yes
Yes
Yes
Good
BGA black
pad concerns
Au
embrittlement
concerns
Planar
microvoid
concerns
Pd
embrittlement
concerns
Good
Hot-Air Solder
Leveling
(HASL)
(SnPb/SnCu)
Organic
Solderability
Preservative
(OSP)
Electroless
Ni/Immersion
Au (ENIG)
Electrolytic
Ni/
Electroplated
Au (ENEG)
Shelf life
proper
handling
One year
Six to
nine months
One year
Handling
Normal
Avoid physical
contact
SMT land
surface
topology
Domed/Flatter
Solderability
after multiple
reflow cycles
(two times)
Attribute
Solder joint
reliability
Good
Sporadic brittle fracture failure
Additional
plating
operation
Additional
plating
operation
Additional
plating
operation
No additional
plating
Additional
plating
operation
Additional
plating
operation
Additional
plating
operation
No
No
No
Yes
No
Yes
No
Good
Poor, unless
solder
applied during
assembly
Good
Good
Good
Good
Good
Exposed Cu
after
assembly
No
Yes, along
land edges
No
No
No
No
No
Switches/
Contacts
No
No
Yes
Yes
Yes
Yes
No
Waste treatment and
safety in
printed board
fabrication
Poor/Fair
Good
Fair
Fair
Good
Fair
Good
Process
control
Thickness
control
concerns
Good
Phosphorus
content
concerns
Au thickness
control
concerns
Good
Good
Thickness
control
concerns
Coating
thickness
(µm)
0.38 to 0.8
0.2 to 0.5
0.05 to 0.10
0.8 to 2.5
0.07 to 0.10
0.05 to 0.10
1.0 to 1.3
1.0
0.4 to 0.6
2.0 to 3.0
2.0 to 3.0
1.1 to 1.6
2.0 to 3.0
to 1.5
Card edge
contacts
Wire bonding
Test point
probing
General cost
comparison
(using HASL
as baseline)
45
IPC-7093A
HASL uses a molten
bath of solder (SnPb or Pb-free) and hot-air knives to apply
solder to exposed printed board surfaces. HASL solder thickness varies widely from 0.8 µm to 0.38 µm. A low thickness
is not acceptable because the very thin layer of solder is completely transformed into Sn-Cu intermetallic, which has very
poor solderability. The wide variation in HASL thickness can
also cause component coplanarity and solder paste printing
problems. The uneven surface makes solder paste printing
more difficult because it is difficult to achieve a good seal with
the stencil. The result is more frequent stencil cleaning or an
increased potential for bridging.
October 2020
5.4.1 Hot-Air Solder Leveling (HASL)
HASL is compatible with SMT and through-hole components;
however, it can be problematic with BTCs because it is not
flat. Pb-free HASL is smoother and less domed than SnPb
HASL (see Figure 5-1 and Figure 5-2), but coating thickness
uniformity is still a concern for BTCs. HASL printed boards
have a 12-month shelf life, and they typically can withstand
four to five heating cycles without affecting solderability.
Excess HASL deposits on pads can lead to opens, tilt or skew
of the BTC, while insufficient HASL deposits can lead to
wettability issues and a reduction in solderability, due to intermetallic compound (IMC) penetration in areas of low coating
thickness.
Figure 5-1
Cross-Section of HASL-Coated Lead; Not Flat
Figure 5-2 Nonuniform HASL Pads (Left) and Coordinate
Measuring Machine (CMM) Image Showing HASL Coating
Variation (Right)
5.4.2 Organic Solderability Preservative (OSP) Coatings OSP is an antitarnish coating of an organic compound (e.g., a
benzimidazole-based compound) which is applied over exposed Cu surfaces to prevent oxidation. Various chemistries are
available; common ones are benzotriazole, imidazole and benzimidazole. The coating thickness can range from thin (0.2 µm)
to relatively thick (0.5 µm). Thicker coatings are preferred if there is a need for multiple reflow cycles and/or a long wait
(24-hour maximum) between soldering cycles.
OSP coatings are compatible with SMT, BTC and through-hole components. OSP-coated printed boards have a shelf life of
six to nine months if they are stored properly. OSP provides a flat surface which reduces stencil printing and component
coplanarity issues. Misprinted paste should be processed in accordance with IPC-7526.
ENIG is applied through the deposition of an initial layer of Ni followed by
a thin, protective layer of Au onto the exposed Cu surfaces of a printed board. The thin layer of immersion Au preserves
solderability by preventing oxidation of the highly active Ni surface. The presence of Ni plating provides extra strength for
the through-hole barrels during multiple reflow, wave and hand soldering cycles. IPC-4552 is a valuable reference for ENIG
coatings.
5.4.3 Electroless Ni/Immersion Au (ENIG)
ENIG is compatible with SMT, BTC and through-hole components. ENIG-coated printed boards have a shelf life of
12 months. Typically, they can withstand four to five heating cycles without affecting solderability. It provides a flat surface
which reduces stencil printing and component coplanarity issues.
Traditional ENIG is prone to black-pad defects (hyper-corrosion-related failures) associated with dewetting of solder, and it
is prone to brittle solder joints failures. Due to these reasons, there are field failures and reliability concerns of electronic
assemblies, as well as component disconnection which leads to overall malfunction of electronic assemblies. New ENIG
plating chemistry formulations have been introduced to the market which reduce the occurrence of black-pad corrosion
issues in traditional ENIG, achieve robust solder joints and provide improved quality/reliability of the electronic assembly.
Many of these plating formulations also use cyanide-free chemistry for immersion Au processes, making them ecofriendly.
5.4.4 Electrolytic Ni/Electroplated Au (ENEG) ENEG is similar to ENIG; however, it results in a different grain structure.
ENEG is applied after pattern plating and most often before solder mask; therefore, it carries some risk of surface contamination. Solder mask applied over ENEG exhibits lower solder mask adhesion than other surface finishes, which can create
problems during rework if the solder mask dams between lands that peel off.
46
October 2020
IPC-7093A
ENEG printed boards have a shelf life of 12 months. It is compatible with SMT, BTC and through-hole components. It can
withstand four to five heating cycles without affecting solderability and it provides a flat surface which reduces stencil printing and component coplanarity issues.
5.4.5 Electroless Ni/Electroless Pd/Immersion Au (ENEPIG) ENEPIG is similar to ENIG, except that a Pd layer is placed
between the electroless Ni layer and the immersion Au layer. The Pd thickness should be 0.05 µm to 0.3 µm for optimum
solder joint reliability. The Pd layer creates a barrier between the Ni and Au layers to prevent oxidation of the Ni layer and
interdiffusion between the Ni and Au layers.
ENEPIG printed boards are compatible with SMT, BTC and through-hole components. ENEPIG provides a flat surface,
which reduces stencil printing and component coplanarity issues, and it can withstand four to five solder reflow cycles without affecting solderability. ENEPIG-coated printed boards have a 12-month shelf life.
See also IPC-4556.
5.4.6 Immersion Ag Immersion Ag is produced by selective displacement of Cu atoms with Ag atoms on the exposed
metal (Cu) surface of the printed board. An organic substance is deposited as part of the process, which reduces the oxidation that would be expected with a pure-Ag surface. IPC-4553 is a valuable reference for immersion Ag.
Immersion Ag finishes are compatible with SMT, BTC and through-hole components. Immersion Ag printed boards have a
shelf life of one year if they are stored properly. It provides a flat surface which reduces stencil printing and component
coplanarity issues, and it typically can withstand four to five heating cycles without affecting solderability.
Immersion Sn utilizes a displacement reaction between the Cu surface and Sn ions in solution to
reduce a layer of Sn onto the Cu surface of the printed board. An organic substance is deposited as part of the process that
reduces the oxidation that would be expected with a pure-Sn surface. Immersion Sn is compatible with SMT, BTC and
through-hole components.
5.4.7 Immersion Sn
Immersion Sn printed boards have a shelf life of six months. At one time, shelf life was very limited (less than six months);
however, it has improved considerably (see IPC-4554). It provides a flat surface which reduces stencil printing and component coplanarity issues. Immersion Sn finishes typically can only withstand three heating cycles without affecting
solderability. After multiple reflow cycles, the immersion Sn coating is compromised by the growth of Cu-Sn intermetallic.
Although not widely used, solid solder deposition (SSD) is a method for preloading the
surface mount lands with all the solder needed—in a solid form—to complete the component attachment. SSD uses an
adhesive flux coating to hold the components in place during the final reflow cycle. The adhesive flux, once dried, has a
much higher holding power than solder paste, and it does not matter if it is smeared because it is nonconductive and noncorrosive. Because of this, placing components with lead styles that are blind or underneath the component body can be done
with more predictability and achieve better yields. The basic steps for the SSD application are shown below. The first four
steps are demonstrated in Figure 5-3.
5.4.8 Solid Solder Deposition
47
IPC-7093A
October 2020
1
2
3
4
IPC-7093a-5-3
Figure 5-3
1.
2.
3.
4.
48
Solid Solder Deposition (SSD) Application Basic Fabrication Steps
Print the surface mount lands with a stencil and solder paste.
Reflow the solder paste without placing the components.
Wash away the residue that is released from the solder paste.
Flatten the rounded SSD bumps. Stencil print the adhesive flux on to the pad surfaces and apply a paper to protect the tacky surface until
assembly.
October 2020
IPC-7093A
The manufacturing considerations for an SSD product are:
• Using the SSD application process sequence demonstrated in
Figure 5-4.
1. Stencil print solder paste on the BTC land pattern and
DAP (Figure 5-4B).
2. Reflow solder and clean to remove flux residues
(Figure 5-4C).
3. Flatten the SSD surface and stencil print adhesive flux
(Figure 5-4D).
A
• Printing paste onto pads and reflowing it without disturbing
it is an easier method for applying solder paste. All defects
associated with z-axis pressure from component placement
is eliminated.
B
• Reflowing solder paste onto surface mount lands highlights
solderability issues associated with the surface finish. Dewetting is easily identified without the components in the way.
• Reflowing solder without components allows proper outgassing of flux. As a result, the formation of voids is decreased
or eliminated.
C
• Cleaning flux residue from bare boards is easier and more
efficient without components in the way.
• Adhesive flux supplied with SSD is tackier than solder paste
and can last up to six months.
• Design of SSD printed boards is no different than standard
printed boards.
The design considerations for an SSD product are:
D
• Completely surround every surface mount feature with
solder mask. Use dams between all pads to help shape the
SSD during flattening.
• Isolate all holes, including via holes, so paste does not drain
during reflow.
• Identify lands with via holes in them to modify the SSD
process to accommodate solder-filled via holes in surface
mount lands.
Figure 5-4
A–
B–
C–
D–
SSD Process Steps
Coated or plated BTC land pattern and DAP
Stencil print solder paste on land pattern and DAP
Reflow solder and clean to remove flux residues
Flatten the SSD surface and stencil print adhesive flux
• Step small boards into arrays for handling. Depending on the
design, some boards can be separated from the array and
fluxed as single images before shipping.
Cross-sectional thickness of silk screen can
range from 20 µm to 25 µm as shown in Figure 5-5. As previously mentioned, final collapse height of BTC devices range
from 50 µm to 75 µm; nearly 40 % to 50 % of the collapse
height. With this very small gap, silk screen contributes to
component tilt, opens, pad contamination and first-pass yield
issues. Users should be aware of the negative effects silk
screen may have and assess if it can be used for a particular
application. If you use silk screen, ensure it is outside the
package keep-out area. Caution and careful review with small
BTC stand-off heights is recommended.
A
5.5 Silk Screen
Typically, the OEM makes the decision on incorporating silk
screen onto a printed board.
B
C
Figure 5-5
Mask
Silk Screen Thickness Measurement on Solder
A – Silk screen (20.2 µm)
B – Solder mask (22 µm)
C – Cu (30 µm)
49
IPC-7093A
October 2020
The planarity of 1.5-mm-, 2.25-mm- and 3-mm-thick boards varies, especially considering the ability to assemble BTC components. Flatness is measured in relationship to the length and width of the laminate
or the complete printed board. Bow is applied to the longest dimension of the part, and twist is applied to the length across
the diagonal distance. These requirements are usually set as a percentage allowance of the distance in question. Thus, the
allowable bow of a printed board might be specified as 0.5 % of the length of the longest dimension. For details, reference
IPC-A-610.
5.6 Site Flatness, Bow and Twist
Specific to mounting BTCs, flatness needs to be evaluated based on localized measurement with such techniques as shadow
moiré imaging. This technology allows local flatness measurement at room temperature and at the elevated temperatures
(e.g., 245 °C) for implementing Pb-free soldering. Traditional techniques of measuring overall board flatness do not reflect
the problems in attaching high-terminal-count BTCs to local areas of a board.
Site flatness should be < 51 µm per 2.5 cm. This flatness requirement applies for both initial attach and for rework processes.
For rework, this requirement is after site dress. It is recommended that site flatness be measured using a laser profilometer,
contact profilometer or other z-displacement tool to assess any possibility of local site warping after module removal.
6 PRINTED BOARD DESIGN CONSIDERATIONS
IPC-7351 may be used as the starting point for land pattern design of BTCs; however, this standard contains the detailed
rules and guidelines about design of BTCs. In case of conflict with IPC-7351, the guidelines in this standard are recommended.
This section provides information on the design principles for incorporating BTCs onto electronic product board designs,
including physical design, solder mask design, thermal pad design, I/O design and stencil design considerations. A listing of
known issues will help the user avoid problems encountered at various stages of printed board fabrication and assembly
(see 6.15).
Decisions made during the design phase have direct effect on numerous aspects
of the hardware assembly process. BTC designs should adhere to component supplier requirements, meet application-specific
electrical and mechanical requirements and enable robust assembly, test, rework and manufacturing operations. Designs that
can meet these requirements can deliver high-quality, high-reliability BTC interconnect structures. In addition, higher
throughput and first-pass yields can be attained during manufacture of the hardware.
6.1 Design for Assembly Considerations
As stated in other sections of this standard, BTC package sizes continue to shrink, but larger packages continue to be used.
For all BTC packages—large and small—there are many aspects of design, assembly, test and cleanliness that need to be
considered for balancing various trade-offs. In addition to package size, power consumption within BTCs is increasing with
some very small packages (2 mm x 2 mm to 4 mm x 4 mm) operating at 60 W. Heat dissipation of BTCs is also very
important and prioritizes the need for robust BTC designs.
6.2 BTC Land Pattern Design Process
Use the following process to help with the design of BTC packages onto a printed
board assembly:
1. Determine the application’s functional requirements (thermal, power, signal integrity).
2. Select the appropriate BTC part that meets the electrical, thermal and mechanical size constraints.
3. Review the supplier component print and ensure all requirements are met (form, fit, function).
4. Review the printed board stack-up and general requirements (i.e., understand Cu shapes and routing).
5. Start with supplier physical and logical layout requirements; however, follow the guidelines in this standard:
• Design integrates BTC and printed board requirements
• Number of vias, via types, via sizes, via grid, thermal pad area coverage
• I/O configuration (pad dimensions, singulated or ganged solder mask) (see 6.8.2)
• Thermal pad configuration (select from options depending on application/cost)
• Available routing space near BTC devices
• Design BTC stencil apertures, ensuring nominal I/O and thermal pad solder volumes
6. Result: Create and store BTC physical and logical symbol
• Place component symbol on printed board assembly design
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6.3 Package Variations BTCs are available in various lead formats and package thicknesses. In general terms, the family of BTC components includes:
• Peripherally leaded dual (DFN) and quad (QFN) sided
• Peripheral multirow (in-line and staggered leads)
• Full and partial area array devices
Leads on the bottoms of the packages can be rectangular or round depending on the type of lead frame devices (e.g., QFN),
typically represented by the former and substrate devices represented by the latter (see Figure 6-1). Lead frame devices often
feature an exposed die paddle on the bottom surface of the package, but small DFN-style devices without such an exposed
pad in particular are becoming more common.
Electrical contact to the printed board is made by soldering the perimeter pads and, if present, exposed paddle on the bottom surface of the package to the printed board. Heat can be efficiently conducted from the package by soldering the exposed
thermal paddle to the printed board.
Because BTCs do not have solder ball terminations, the electrical connection between the package and the printed board
should be made using only the solder deposited on the printed board. Obtaining sufficient solder on the lands and making
reliable solder joints is one of the significant challenges for this type of component, so special attention is needed when
designing the land pattern. The component land pattern for the printed board is commonly predicated either on guidelines
developed by the component manufacturer, within a company or by following established industry standards such as
IPC-7351.
SON and QFN versions are of high interest (see Figure 6-1). Body sizes for these devices have a very large range from
2 mm x 2 mm to as large as 25 mm x 25 mm. It should be noted that corresponding thermal pad areas for these devices can
be as small as 1 mm x 1 mm. Table 6-1 shows most commonly used package constructions. The values in the table are
denoted as square dimensions, so be aware that not all packages are square; therefore, denoted ranges may not be square.
At the time of publication, the most commonly used formats are medium and small formats; accounting for an estimated
90 % of package supply (highlighted in grey in Table 6-1). See Section 4 for more information on BTC packages.
Table 6-1
Package
Size Range
Common BTC Technology Ranges
Number of
Thermal Vias
I/O Pin
Count
1 mm x 1 mm to
2 mm x 2 mm
1 to 2
6 to 20
3 mm x 3 mm to
6 mm x 6 mm
2 mm x 2 mm to
5 mm x 5 mm
3 to 9
20 to 40
Regulators (primary)
6 mm x 6 mm to
12 mm x 12 mm
5 mm x 5 mm to
11 mm x 11 mm
10 to 30
30 to 80
Regulators (primary)
12 mm x 12 mm to
25 mm x 25 mm
11 mm x 11 mm to
24 mm x 24 mm
20 to 30+
20 to 30
Typical Package Function
Body Size
Thermal Pad Size
Small
Regulators, controllers, high-speed
switches, logic, clocking
2 mm x 2 mm to
3 mm x 3 mm
Medium
Regulators, controllers, high-speed
switches, logic, clocking
Large
Very Large
A
Figure 6-1
A–
B–
C–
D–
B
C
D
IPC-7093a-6-1
Quad-Flat No-Lead (QFN) / Small-Outline No-Lead (SON) Family of Bottom Termination Components (BTC)
SON (DFN)
QFN
QFN (multirow)
QFN (multirow staggered)
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6.4 BTC Land Pattern and Component Symbol Coding BTC land pattern rules described in this section supersede rules
for BTCs outlined in IPC-7351. BTC layouts need to follow IPC-2221 for minimum electrical conductor spacings.
There are three governing elements that should be defined to code a BTC land pattern / component symbol. They include:
1) Integrated BTC design land pattern
2) I/O perimeter pads
3) Thermal pad region found under the device
Once all regions are defined, a unique BTC component symbol can be generated and stored within a CAD component symbol library. First, the integrated land pattern area needs to be defined. Key elements are listed below:
• 0,0 reference point created
• Defines the full area where I/O and thermal pad connect
• Defines component place-bound, via keep-outs, and rework keep-outs
• Defines proximity of all I/O and thermal pad(s) relative to each other
Next, I/O areas can be defined. Key elements are listed below:
• Defines single pad dimensions
• Defines multiple I/O pad layout (groupings of I/O pads and x/y package arrangement)
• Incorporates Cu features and solder mask details
• Includes HDI via placement in I/O pads (if required)
Finally, the thermal pad area can be defined. Key elements are listed below:
• Defines single thermal pad dimensions
• Defines multiple thermal pad dimensions (if multiple pad areas are required)
• Incorporates Cu features and solder mask details
• Incorporates thermal via parameters including via type, size, count and grid arrangement
Figure 6-2 incorporates all key regions as described in the preceding. Dimensions for the nominal component body, I/O pads,
thermal pads and thermal vias are included. The figure and dimensions can be used when defining BTC land patterns for a
specific application. Definition of all parameters is required to sufficiently code a BTC device.
The following defines the dimensions and designations listed in Figure 6-2:
Xbody / Ybody – Nominal Component Body
X Body
X, Y
PP
PM
PH
HH
D
TH
PH
Y
PP
Thermal Pad2, 3
Width, Length
Thermal Pad to I/O Heel
D, E
TH
Thermal Via4
Min Via Center to Cu Shape Edge
Thermal Via Diameter (FHS)
V1, V2
VDia
Y Body
I/O Pad1
Width, Length
Pitch
Pitch max
Pad Side to Corner Heel
Pad Heel to Heel
HH
E
X
PM
V1
V Dia
Notes:
V2
1. I/O pads are preferred as singulated solder
mask webs, NSMD when possible. Solder Figure 6-2 BTC Printed Board Land Pattern Dimensions
mask pull-back from Cu typically ranges
from 0.0508 mm to 0.0762 mm (see 6.11).
2. Thermal pad design can be selected from one of six options (see 6.11).
3. Thermal pads are preferred to be SMD; no solder mask pull-back is required.
4. It is important to determine proper via type, finished hole size (FHS), count, quantity and grid arrangement (orthogonal,
hexagonal).
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6.5 Circuit Routing Considerations / Thermal Via Keep-Outs If thermal pads have been incorporated into the BTC
printed board design, thermal vias may be present. Typically, thermal vias are through-hole vias connecting multiple ground
planes, acting as a thermal sink from the BTC to the printed board. Therefore, inner layers may need to have wiring considerations and constraints added to the printed board signal and power routing to manage thermal pad / thermal via areas.
During physical design stages of product development, it is
important to understand basic BTC construction options available from component suppliers. See Section 4 for elements
important to physical design activities, including general BTC package description, package variations, termination formats,
supplier component prints, component symbol coding and circuit routing considerations.
6.6 Important BTC Package Elements for Physical Design
6.6.1 Termination Formats SON and QFN packages are available in pull-back and no pull-back I/O lead configurations
(see Section 4). In the pull-back configuration, the standard solder pads are typically offset from the edge of the package up
to 0.15 mm (based on JEDEC MO-220; L1 in Figure 4-37) as shown by arrow locations in Figure 6-3. See Figure 6-4 for
microscopic bottom- and inclined-view images of pull-back leads on a QFN package. Figure 6-5 shows a cross-sectional
microscopic image of an I/O solder joint with pull-back lead geometry.
In the no pull-back configuration, the standard solder pads extend and terminate at the edge of the package. The advantage
of the no pull-back design is the end-exposed contact feature can offer a visible solder fillet (that can be optically inspected)
after board mounting (see 7.11.2 for details on optical inspection), which is impossible in pull-back lead designs (see
Figure 6-3, Figure 6-4 and Figure 4-29).
D
C
F
Figure 6-3
D
C
E
E
H
H
J
J
A
F
G
B
G
Comparing Pull-Back (Left) and No Pull-Back Configurations (Right)
A – Pull-back terminal
B – No pull-back terminal
C – Die-attach material
D – Mold compound
E – Gold wire
F – Exposed contacts
G – Exposed die-attach pad
H – Die
J – Cu
Figure 6-4 Bottom (Left) and Inclined (Right) Microscopic
Images of Pull-Back Leads on a Quad Flat No-Lead (QFN)
Package
Figure 6-5
Back
Cross-Sectional Microscopic Image of Pull-
6.7 BTC Land Patterns and Component Symbol Coding The first step in adding a BTC device to a printed board assembly is to identify the specific device(s) to be used within the design. A component print (also called a component outline
drawing) should be obtained from the component supplier. This print outlines various electrical function and physical
dimension parameters for the device. The supplier print will provide details on component dimensions and the preferred Cu
land pattern footprint for the component to be properly mounted to the printed board.
See IPC-7351 for recommended BTC land pattern guidance. Additional information is provided below to help guide the
physical designer during printed board design steps for BTCs. There are two different regions that should be defined for BTC
land patterns:
1) Thermal pad region found beneath the device
2) I/O perimeter leads
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See 6.11 for details of various thermal pad design options. See 6.8 for details on preferred I/O design.
Once component selection is complete and supplier prints have been reviewed, a unique BTC component symbol can be
generated and stored within a computer-aided design (CAD) component symbol library.
Solder mask is a thin polymer layer that is applied to cover Cu traces on a printed board for
protection against oxidation and to prevent solder bridging between closely spaced component lands and vias. During thermal pad and I/O layout design, it is important to understand minimum solder mask web (dam) x and width y. It is important to ensure minimum web dimensions match printed board supplier capabilities. For example, a typical conventional
minimum liquid photoimageable (LPI) solder mask web is 0.15 mm. Minimum webs can be 76.2 µm.
6.8 Solder Mask Design
Solder mask needs to be properly cured. Uncured solder mask under BTCs can contribute to increased outgassing and voiding under the component, during SMT processing.
Encroached vias permit solder mask
on the land without filling the plated through-hole (PTH).
Encroached vias take the primary solder mask opening and
adjust it so it is slightly larger than the via hole size (typically
50 µm to 200 µm).
6.8.1 Encroached Vias
This concept will permit outgassing and proper cleaning of the
PTH, provide more surface coverage and increase adhesion
between the solder mask and Cu of the annular ring. It also
will provide a larger web between the land and via, so it
should minimize solder mask removal during BTC removal
for rework (see Figure 6-6).
A
B
C
Figure 6-6 Comparing Solder Mask Off Via Land with a
Solder Mask Encroached Via Land
A – Drilled and plated via hole
B – Solder mask overlaps onto the via land
C – Via land outline
6.8.2 Solder Mask Design for I/O Cu Pads
6.8.2.1 Solder Mask Defined (SMD) vs. Non-Solder Mask Defined (NSMD) Pad Definition Two types of land patterns are
used for surface mount packages: NSMD and SMD. For SMD-type land patterns, the solderable surface on the printed board
is defined by the solder mask aperture (i.e., the solder mask aperture is smaller than the metal land geometry). For NSMDtype lands, the solder resist aperture is larger than the metal land geometry. Figure 6-7 illustrates the two different types of
solder mask to land pattern geometries.
D
D
C
C
E
A
Figure 6-7
A–
B–
C–
D–
E–
54
Comparing Optional Solder Mask Variations
NSMD
SMD
Solder mask
Land
Substrate
B
IPC-7093a-6-7
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IPC-7093A
The typical solder-mask registration tolerance capability of
printed board suppliers ranges from 25 µm to 100 µm,
whereby higher printed board material and fabrication costs
are to be expected because registration tolerance decreases.
Because solder mask pull-back from Cu I/O pads should be
equal to or exceed solder-mask registration tolerance (to
ensure no solder mask covers the Cu land in case of a NSMD
design), the solder mask pull-back from Cu is in the 25 µm to
100 µm range, depending on the specified solder mask registration tolerance.
The use of NSMD design for I/O terminals is generally preferred because it provides significant advantages over the
SMD design regarding dimensional tolerances and registration
accuracy. Because the Cu etching process has tighter control
than the solder masking process, the NSMD design provides a
more robust soldering process specific to positional precision.
Moreover, the NSMD design allows the solder to adhere to
the sides of the Cu land and avoids stress concentration in the
solder joint related to the notching effect imposed by the
solder mask protruding into the solder joint for an SMD Figure 6-8 NSMD I/O Design Example
design, thereby improving solder joint fatigue (thermal
cycling) reliability of solder joints. Figure 6-8 shows a practical example of a NSMD-type I/O-design.
For fine-pitch devices (e.g., 0.4-mm pitch), it may not be to possible to maintain a solder resist dam (solder mask web)
between neighboring I/O Cu pads due to requirements for minimum thickness of a solder mask dam. Conventional solder
mask dams typically exhibit a minimum width of 0.150 mm to ensure robust solder mask adherence, but widths can be as
low as 0.075 mm for suppliers that can produce state-of-the-art solder mask webs. If a solder mask dam is not possible
between neighboring pads, singulated solder-mask apertures for each I/O termination could be replaced by an aperture
encompassing all neighboring I/O termination Cu features. See Figure 6-9 for a schematic and Figure 6-10 for a practical
example.
A
C
B
Figure 6-9 Singulated and Ganged I/O Terminations
Source: Analog Devices
Figure 6-10
Opening
Ganged I/O Terminations with Solder Mask
A – Singulated
B – Ganged
C – Solder mask
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For applications such as voltage regulators, which is a common use case for this device type, circuit designs often integrate surface power and ground shapes as shown in
Figure 6-11. If the component symbol is not designed to
include SMD I/O pins, ganged opening areas will occur as
denoted by the arrows in Figure 6-11.
Since there is no solder mask in these ganged area openings,
adjacent I/O solder joints have been shown to flow and bridge
together during reflow. Although this has minimal power/
ground electrical impact, this is considered a defect according
to IPC-A-610. These bridged solder joints can reduce overall
second-level interconnect reliability. It is recommended that
SMD I/O Cu pad geometries be used for these applications as
long as issues with adhesion, flaking and rework can be reliably avoided.
6.8.2.2 Printed Board Manufacturer Solder Mask Alterations It is important to ensure printed board suppliers do not
modify solder mask web designs per original design file artwork to accommodate internal board fabrication process capability. Figure 6-12 shows an example of a SMD thermal pad
structure that was modified by a printed board supplier (not
desired). In this example, important solder mask webs
required by the design were removed from the thermal pad. In
addition, such changes were not communicated to the customer. While a SMD thermal pad structure was intended, a
modified design resembling a hybrid open-Cu design was fabricated. As this example illustrates, it is important to review
and verify actual printed board constructions produced by the
supplier to ensure desired BTC thermal pad structures are
fabricated.
6.8.3 Solder Mask Design for Thermal Pads Solder mask
design for thermal pads depends on the thermal pad design
option adopted. See 6.11 for design-specific details. In general, the basic NSMD and SMD design options, discussed in
6.8.2.1 for I/O Cu pads, can also be distinguished for thermal
pads (see Figure 6-13).
A
B
Figure 6-11
Device
Surface Power/Ground Flooding into QFN
A – Ground
B – Power
Figure 6-12
Mask Web
Printed Board Supplier Removal of Solder
A
A
B
B
B
B
IPC-7093a-6-13
Figure 6-13 Solder Mask Defined (SMD) (Left) and
Non-Solder Mask Defined (NSMD) (Right) Exposed-Pad
Soldering Design Options
Orange – Cu
Green – Solder mask
56
A - Exposed pad land pattern solderable area
B - Minimum spacing
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IPC-7093A
For SMD and NSMD designs, minimum spacing should be
adopted to ensure the absence of bridging between the
exposed pad and the I/O Cu. For this purpose, a nominal
spacing between 200 µm and 250 µm can be sufficient. However, depending on the relevant electrical potentials, larger
clearances may be required. The solderable area can be singulated into individual, smaller solderable areas using a solder
mask web (see Figure 6-14). Such singulation can be beneficial because it provides channels for degassing volatile solder
flux residues during reflow and can thereby prevent excessive
voiding.
Conventional solder mask webs typically exhibit a minimum
width of 0.15 mm to ensure robust solder mask adherence, but
widths can be as low as 0.075 mm for suppliers that can produce state-of-the-art solder mask webs (including annular ring
minimum web widths for tented-via designs). If a solder mask
web design is adopted, care should be taken to avoid any supplier design CAD review deletions of solder mask webs. Such
alterations result in changes to the solderable area (and thus
incorrect measurement of solder paste volume) and potentially
excessive voiding due to the lack of channels for degassing.
A
A
IPC-7093a-6-14
Figure 6-14 Exposed-Pad Soldering Area Singulated by
Solder Mask Web
A - Solder resist web width
6.8.4 Perimeter I/O Cu Pad Design For additional information regarding Cu pad design, refer to 6.10. If HDI (VIPPO) /
stacked microvias are used within I/O pads refer to 6.9.
There are four different types of perimeter I/O pad configurations found on
BTC packages. The list below includes packages with pullback and without pull-back from the Cu lead frame. This section highlights the different types of I/O pad configurations
found within BTC package constructions and provides some
important considerations when designing perimeter Cu pads
for a particular application. Detailed dimensions and requirements should be determined by the designer, and the designer
should follow design recommendations from the component
supplier’s print (outline drawing) for the BTC being designed.
6.8.4.1 Pad Formats on BTC Packages
IPC-7093a-6-13
Figure 6-15 Bulbus Solder Joint Formation (Left) Pin Protrudes (Right) Beyond Package Body Edge
IPC-7093a-6-13
Figure 6-16 Pad Larger Than Package Pin (Left) and Pin
Pulled Back from Package Body Edge (Right)
I/O pad configuration 1 – Outer pin, with no pull-back, that is
soldered to a perimeter pad location without a toe fillet. There
is no wettable side flank to create a toe fillet. See Figure 6-15.
I/O pad configuration 2 – Outer pin, with pull-back, that is
soldered to a perimeter pad location without a toe fillet. There
is no wettable side flank to create a toe fillet. See Figure 6-16.
IPC-7093a-6-13
Figure 6-17 Concave Solder Joint Formation (Left) and
Pin Protrudes Beyond Package Body Edge (Right)
I/O pad configuration 3 – Outer pin, with no-pull-back, that is
soldered to a perimeter pad location with a toe fillet. There is
a wettable side flank that creates a toe fillet (plated lead frame
required). See Figure 6-17.
I/O pad configuration 4 – Inner pin is soldered to an inner
perimeter 1:1 pad location; creating a lap joint with no side,
toe or heel fillets. This typically applies to multiple-row configurations. See Figure 6-18.
IPC-7093a-6-13
Figure 6-18 Pad Same Size as Package Pin (Left) and Pin
Pulled Back from Package Body Edge (Right)
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Regardless of the style, the layout recommended on the component supplier print should be followed. Modifications beyond
the print are up to the discretion of the designer based on application needs.
In addition to the pad style, the listing below provides additional key variables that need to be considered when designing
perimeter I/O copper pads:
• Pad styles – Refer to pad formats discussed in this section.
• Pad geometry – Pads can be D-shaped, rectangular or rounded on both ends.
• Land pattern – I/O land pattern designs should follow 6.7.
• x/y dimensions – Determined by the component manufacturer print.
• Cu – Standard electroless / electrolytic plated Cu with final surface finish applied on top.
• Solder mask – Standard LPI or film mask; NSMD or SMD structures; singulated or ganged solder mask.
• Solder joint – Formation as outlined in IPC-A-610.
• Symbol coding – See 6.7.
• Preferred pad – Singulated NSMD I/O pads recommended.
• Side flank / Fillet – Dependent on component terminal plating. Some BTCs have this, others do not. Affects final solder
joint formation, heel, toe, side.
While single- and two-metal-layer circuits are still common, multilayer interconnection structures
are commonly required to support the interconnection of BTCs for high-performance electronics. High-density routing difficulties associated with BTCs may also require the use of build-up layers using microvias.
6.9 HDI Considerations
The types of microvias which can be created for the build-up HDI layers will depend on the equipment used by the manufacturer. Figure 6-19 shows typical build-ups which can be achieved with laser technology. Figure 6-20 shows build-ups
which can be achieved with etching and mechanical processes.
See IPC-2226 for design requirements and standardized design types for HDI.
A
B
C
D
IPC-7093a-6-19
Figure 6-19
HDI Build-Ups Possible with Laser-Via Generation
A – Thin-film HDI ceramic substrate
B – Anisotropic conductive material bonded flex
C – Laser blind vias
D – Sequential build-up
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A
C
B
D
IPC-7093a-6-20
Figure 6-20
A–
B–
C–
D–
HDI Build-Ups Possible with Etching and Mechanical Processes
Sequential bonded film (plasma etched)
Sequential bonded firm (micropunched)
Sheet build-up (microdrilled)
Roll sheet build-up (chemical etched)
BTCs are often designed with an exposed die paddle on the bottom surface of the package
to enhance thermal performance. However, to make use of the exposed die paddle for heat dissipation, the printed board
design should have features to effectively conduct heat. This can be achieved by incorporating a thermal pad and thermal
vias on the printed board. While a thermal pad provides a solderable surface on the top surface of the printed board (to solder
the package die pad to the board), thermal vias can be used to achieve a thermal path to inner and/or bottom layers of the
printed board to remove heat (see 6.10.1).
6.10 Cu Thermal Pad Design
Generally, the size of the thermal pad on the printed board should match the exposed die paddle feature provided on the
device. The die paddle can be soldered to the printed board to help with heat transfer during component operation. The direct
thermal conduction path helps to dissipate heat from the component to inner-layer ground planes using thermal vias, acting
as a large heat sink path for the device. Additionally, connection between the die paddle and printed board Cu pad helps
with electrical current carrying capability of the device. Therefore, it is important to balance thermal and electrical requirements during BTC printed board assembly design and layout.
There are several key elements of thermal pad design that should be defined including:
• Selection of an application-appropriate thermal pad design option
• Whether a single thermal pad or multiple thermal pads are required under a BTC
• Access to internal ground planes acting as an internal heat sink
• Thermal pad via type, size, quantity, pitch and arrangement
• Use of via standard grids (orthogonal or hexagonally closed packed arrays)
• Solder mask coverage and webs (applied to thermal pad and I/O locations)
• Impacts to the SMT solder stencil aperture design (aperture ratio, solder volume)
The most basic thermal via is a PTH, in which the Cu barrel provides a pathway for conducting heat to inner layers and the bottom side of the printed board. Depending on the chosen land design for the exposed-pad
soldering area, capped or filled vias may be required. Via filling, capping, flooding, tenting and plugging (conductive or
nonconductive) are some of the processes applied to cover or fill vias with different materials, respectively. Materials used
to protect vias include:
6.10.1 Thermal Via Types
• Standard LPI and non-imageable solder masks
• Dry-film solder masks
• Specially formulated hole-plugging inks
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• Conductive inks
• Liquid dielectric materials
• Materials not used in other printed board constructions
Via plugging serves different purposes, such as avoidance of solder wicking, enhancement of the via thermal conductivity,
etc. Via filling is also performed on boards that use reflow soldering and wave soldering. When a board with BTCs on the
first side is processed through wave soldering, a large amount of heat can transfer through the vias. This can be very significant because some BTCs can have very high via densities beneath them.
IPC-4761 addresses three basic characteristics of via protection:
1) Bumped via, in which the hole plug or fill material protrudes above the surface of the hole interface producing a
convex shape
2) Dimple in the construction, whereby the hole plug or fill
material recedes below the hole interface producing a concave shape
3) Planarized via, in which the excess hole plug or fill material protruding above the hole interface has been removed
by a subsequent process which produces a coplanar surface
(see Figure 6-21)
IPC-4761 identifies seven different methods of via plugging
and capping. These are shown in Figure 6-22. It is important
to realize that the choice of tented, plugged and filled vias for
via protection can have direct effects on the subsequent
assembly processes.
Figure 6-21
Example
Planarized and Capped Via Protection
IPC-4761 also indicates pros and cons for each of the options. The preference of the plugging method among the options
presented will depend on the capabilities of the fabricator and assembler. To avoid complications during assembly, it is
imperative that all involved in the manufacturing process understand the trade-offs among the options.
For printed boards with HASL finish, the solder coating will effectively prevent most surface degradation due to chemical
exposure. HASL finishes also increase overall wall thickness of the via barrel. For vias that are solder coated before plugging, the solder coating will melt during second side reflow. As a result, the plugging material can become loose. In some
cases, when there is excessive solder coating thickness or solder entrapped within the via during fabrication, solder can
potentially outgas and spatter or drain to the remaining openings.
6.10.2 Key Thermal Pad Design Elements A key characteristic of BTC packages is the inclusion of a solderable die
paddle found on the underside of the component directly under the silicon die (within the package). Generally, the size of
the thermal pad on the printed board should match the exposed die paddle feature provided on the device. The die paddle
can be soldered to the printed board to help with heat transfer during component operation. However, the die paddle may
not always need to be soldered to the printed board. Consult the component supplier part drawing to confirm if a solder
connection to the die paddle is required.
When the die paddle is soldered to a printed board thermal pad, the direct thermal conduction path helps to dissipate heat
from the component to inner layer ground planes using thermal vias, acting as a large heat sink path for the device. Additionally, connection between the die paddle and printed board Cu pad helps with electrical current carrying capability of the
device. Therefore, it is important to balance both thermal and electrical requirements during BTC printed board assembly
design and layout. There are several key elements that should be defined for thermal pad design including:
• Select an application-appropriate thermal pad design option
• Determine if single or multiple thermal pads are required under a single BTC device (per supplier prints)
• Access to internal ground planes acting as an internal printed board heat sink
• Thermal pad via type, size, quantity, pitch and arrangement
• Use of via standard grids (orthogonal or hexagonally closed packed arrays)
• Solder mask coverage and webs (applied to thermal pad(s) and I/O locations)
• Affects to the SMT solder stencil aperture design (aperture ratio, solder volume)
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One Side – Type A
Two Sides – Type B
Tented Via (Type I)
A via with a dry-film mask material applied
bridging over the via wherein no additional
materials are in the hole. It may be applied to
one side (Type I-A) or both sides (Type I-B) of
the via structure.
Tented and Covered Via (Type II)
A Type I via with a secondary covering of mask
material applied over the tented via. The material
may be applied to one side (Type II-A) or both
sides (Type II-B) of the via structure.
Plugged Via (Type III)
A via with material applied and allowing partial
penetration into the via. The plug material may
be applied on one side (Type III-A) or both sides
(Type III-B) of the via structure.
Plugged and Covered Via (Type IV)
A Type III via with a secondary covering
of material applied over the via. The plug
and secondary covering material may be
applied on one side (Type IV-A) or both
sides (Type IV-B) of the via structure.
Filled Via (Type V)
A via with material applied into the via targeting
a full penetration and encapsulation of the hole.
Filled and Covered Via (Type VI), Dry Film
A Type V via with a secondary covering of
material (liquid or dry-film solder mask) applied
over the via. The covering material may be
applied from one side (Type VI-A) or both
sides (Type VI-B) of the via structure.
Filled and Covered Via (Type VI),
Liquid Cover Film
A Type V via with a secondary metallized
coating covering the via. The metallization
is on both sides.
Filled and Capped Via (Type VII)
A via filled with nonconductive epoxy and then
plated over with cu. This is commonly used for
via-in-pad applications.
Figure 6-22
Via Protection Methods
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See Figure 6-23.
6.10.3 Thermal Pad Via Counts and Arrangement To
effectively transfer heat from the top metal layer of the printed
board to the inner or bottom layers, thermal vias need to be
incorporated into the thermal pad design. The number of thermal vias will depend on the application, power dissipation and
electrical requirements. Although more thermal vias improve
the package thermal performance, there is a point of diminishing returns, because additional thermal vias may not significantly improve the performance.
6.10.3.1 Thermal Via Patterns Thermal vias are vias
intended to carry heat away from components to thermal
plains within the printed board structure or to the opposite
side of the printed board. They are commonly arranged within
the Cu thermal pad on the printed board under the QFN component die paddle. BTC suppliers recommend incorporating
an array of thermal vias ranging from 0.5-mm to 1.2-mm pitch
with via diameters ranging from 0.2 mm to 0.7 mm with
25 µm to 50 µm Cu plating thickness in the PTHs. The number of thermal vias should be determined for each application,
operating environment and condition. Vias should be systematically arranged (e.g., orthogonal matrix or hexagonally
closed packed via array) and not be placed randomly within
the thermal pad area. The component is often soldered directly
to the thermal pad to maximize thermal transfer away from
the die element. Vias are generally furnished in a cluster or
array pattern, sharing a common Cu plane area. The thermal
land is a metal (typically Cu) region centrally located under
the package and on top of the printed board. It is rectangular
or square and should match the dimensions of the exposed die
paddle on the bottom of the package (1:1 ratio).
As noted, BTCs are designed with an exposed thermal pad to
conduct heat away from the package and into the printed
board. By incorporating thermal vias into the printed board
thermal pad, heat is dissipated more effectively into the inner
metal layers of the printed board. Depending on the package
pad size, the thermal pad size is modified to avoid solder
bridging between the thermal pad and the perimeter pads. This
is done by defining a minimum clearance between the outer
edges of the thermal pad and the inner edges of the perimeter
pads. This minimum clearance is fixed at 0.2 mm.
A
B
Figure 6-23 Cu Thermal Pad Design Showing Thermal Via
and Thermal Paddle
A – Thermal via
B – Thermal paddle
A
B
IPC-7093a-6-24
Figure 6-24 Printed Board Mean Thermal Resistance of an
Array of Vias with a Given Via Density
A – Mean thermal resistance (mK/W)
B – Via density (1/mm2)
Via diameter 200 µm
Via diameter 300 µm
Via diameter 400 µm
Via diameter 500 µm
Via diameter 600 µm
Via diameter 700 µm
Feasible designs
6.10.3.2 Via Density and Thermal Resistance The diameter, number and type of thermal vias will depend on the application, power dissipation and electrical requirements. Increasing the number (density) of thermal vias decreases the mean
thermal resistance of an exposed-pad solder area. See Figure 6-24 which shows the average thermal resistance has been
plotted against the via density for vias of different diameter. However, there is a point of diminishing returns where additional thermal vias do not significantly improve the performance. Thermal vias may take several configurations
(e.g., orthogonal arrays, hexagonally closed packed via arrays).
Placement of through-hole thermal vias within a thermal pad area should follow standard grid patterns as shown in Figure 6-25, either as orthogonal arrays or hexagonally close-packed arrays. Placement of
through-hole thermal vias within a thermal pad area should follow standard grid patterns. Random via locations within a
thermal pad should be avoided. The image on the left in Figure 6-25 shows top-side thermal via placement only. At first
6.10.4 Thermal Via Standard Grids
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glance, all locations appear random; however, when Cu etch layers are revealed (Figure 6-25, image on the right), it can be
seen that six of the vias were located for close-proximity wiring of nearby I/O grounding pins.
IPC-7093a-6-25
Figure 6-25
Orthogonal Array Structure (Left) and Hexagonal Array Structure (Right)
On-grid via placement helps with several aspects of the overall design including:
• Enabling uniform solder deposits across the thermal pad
• Maximizing solder paste coverage on the thermal pad
• Enabling of different thermal pad design approaches
• Improved inner-layer signal routing capability under thermal pads for other components
Figure 6-26 illustrates an example of a standard grid pattern not being followed. The illustration on the left in Figure 6-26
shows the top-layer view of thermal vias within a QFN thermal pad. This view appears to show random placement of the
vias. However, the illustration on the right shows the same footprint when top-layer etch is displayed. This view shows five
of the vias placed as close as possible to ground return pins (highlighted in green) within the device. While these selected
locations are helpful for electrical function, they do not enable an overall high-quality and reliable design point.
A
Figure 6-26
B
IPC-7093a-6-26
Random Thermal Via Placement Example - Not Recommended
A – Top layer
B – Top etch displayed
If standard grids are not used, the following issues can arise:
• Inner-layer signal routing limitations
• Thermal pad stencil design limitations, resulting in poor solder connection coverage
• Nonsymmetric deposits (skew, float, tilt), resulting in I/O shorts, opens and reliability issues
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6.10.5 Inadequate Via Quantity Inadequate thermal via
quantity can significantly affect thermal transfer efficiency
across the interconnect structure. When there are not enough
vias furnished within the thermal pad area, heat transfer into
subsurface ground layers will be inadequate and may result in
the device overheating (and possibly failing) during operation.
See 6.4 for guidance on how to determine the number of thermal vias to include within a thermal pad to sufficiently transfer generated heat from a device into the printed board Cu
layer structure. Low via counts can increase electrical
impedance-to-ground connections, affecting device power and
signal integrity performance.
While Figure 6-27 illustrates the effect of via counts regarding thermal heat transfer from a device, it is also important to
know additional vias may be required for other reasons,
including power dissipation and signal integrity needs. To
ensure a proper design, thermal, power and signal integrity
requirements should be considered.
Figure 6-27
Inadequate Via Quantity
6.11 Thermal Pad Design Options Regardless of the application, QFN packages need to be designed with thermal and
power dissipation requirements considered. Over-powering or over-heating a device can lead to internal package failure or
downstream device errors. As noted in this standard, a majority of BTC packages are furnished with an exposed metal dieattach pad on the bottom surface that should be joined to a thermal pad located on the printed board surface. The thermal
pad is commonly furnished with a pattern of plated via holes to dissipate heat away from the components base. These vias
holes can be either filled or left as open (see 6.10.1).
To enable thermal and power dissipation, these thermal vias
are commonly connected to subsurface power/ground layers.
By design, most of the heat will be transferred away from the
device using via-in-pad structures. Figure 6-28 shows various
heat flux paths, including radiation, from the package body
conduction through the printed board as well as conduction
through thermal vias.
The resulting thermal transfer structure is very efficient and
provides greater design flexibility and low thermal resistance
in a standard-size QFN device package. Due to minimal lead
lengths, the plated vias can be expected to meet both electrical and thermal dissipation criteria.
IPC-7093a-6-28
Figure 6-28
Pad
Heat Transfer Using Printed Board Thermal
There are several parameter inputs to consider when optimizing a QFN thermal pad design including:
• Thermal pad and I/O dimensions
• Thermal vias (quantity, size, pitch, location and type)
• Number of thermal pad regions required under a single BTC device
• Solder mask coverage (thermal pad and I/O)
• SMT solder stencil apertures (solder volume)
Monitored output responses include:
• Component stand-off (reliability)
• Thermal pad coverage percentage (thermal/power dissipation)
• Solder voiding levels (thermal pad and I/O)
• Solder wicking down thermal vias
• I/O opens and shorts
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There are several thermal pad design options available (see Figure 6-29).
A
B
D
Figure 6-29
C
E
IPC-7093a-6-29
BTC Thermal Pad Design Options
A – Open Cu (current
common practice)
B – Via tenting
C – VIPPO
D – Floating mask
E – SMD window
Exposed copper
Solder mask
Solder Print Deposit
Open through-hole via
Tented via
VIPPO
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The challenge with BTC printed board design is balancing assembly, rework, power, thermal and signal integrity requirements to sufficiently dissipate heat and electrical current while ensuring the device is easily manufacturable. Table 6-2
provides factors to consider when choosing a thermal via design for an application.
Table 6-2 BTC
Thermal Pad Design Option Pros and Cons
Pad Design Option
Pros
Cons
Open Cu
Standard technology
High percentage coverage
Low cost
Solder down vias
Single-sided assembly
Rework difficulty
Excessive touch-up
Via tenting
No solder down vias
Low cost
Printed board reliability
Top mask adhesion
VIPPO
No solder down vias
Added coverage percentage
Enables rework
Higher via counts
Printed board added costs
Smaller supply base
Reliability unknowns
Floating mask
No solder down vias
Enables rework
Low cost
Top mask adhesion
Stencil design
Outgassing channels
Voiding
SMD
Wide printed board range
Consistent stand-off
Good coverage percentage
No solder down vias
Double-sided assembly
Process window
Enables rework
Minimal touch-up
Low cost
Wireability reduction
Stencil design
Minimum solder mask web
A
SMD thermal pad design point is similar to a floating mask
thermal pad approach but includes additional solder mask
trench features between thermal vias. By design, the SMD
thermal pad approach slightly reduces overall solder paste
percentage coverage of the thermal pad (with the addition of
solder mask keep-outs), but it can significantly reduce part-topart variability. The design point minimizes the risk of solder
wicking down thermal vias during printing, placement and
reflow of the BTC. The design point also enables a more
robust hot-gas rework process should device removal and
replacement be required.
6.11.1 Solder Mask Defined (SMD) Thermal Pad Design
Figure 6-30 illustrates an example of a SMD printed board
design. The first features of the design to note are the singulated I/O pads using solder mask. BTCs are frequently used
for voltage regulation and may have surface layer power/
ground islands connecting with the device. Singulating I/O
pads will ensure unique I/O solder joints will be formed independent of power/ground shape addition. The next feature to Figure 6-30 Solder Mask Design (SMD)
note with this design has to do with the thermal pad structure.
As with the floating-mask design point, the SMD approach incorporates solder mask rings around through-hole thermal vias
but also includes connecting solder mask trenches between vias. This added trench creates very distinct polygon solderable
Cu pad shapes. These shapes have become the signifying feature of this design point and are easily detected during solder
paste and X-ray inspection processes. Solder is printed only within the polygon Cu shapes.
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The added solder mask trenches have been shown to:
• Help with flux outgassing, which helps reduce thermal pad solder joint voiding
• Enable a more robust hot-gas rework process operation (i.e., trenches reduce solder mask peeling and lift-off during rework
(site redress))
• There are multiple goals with this approach including:
• Utilize low-cost open through-hole vias
• Eliminate solder wicking down thermal vias
• Ensure proper via counts to manage heat and power requirements
• Reduce stand-off variability, improving reliability
• Provide proper ground return paths, ensuring long-term electrically stable system operation
• Enable safe, repeatable rework process windows
There are numerous benefits associated with this approach. This design point offers high-quality, high-reliability manufacturability. Combining conventional through-hole vias with custom solder mask windows within the thermal pad area is the
essence of the design. This simple approach has technical and commercial procurement benefits. Integrating qualified
through-hole via and solder mask technologies enables more printed board suppliers to fabricate boards with this design,
which helps to spread demand over a wider supply base and helps lower the overall cost of the solution.
The use of SMD helps reduce part-to-part variation in multiple ways. Since solder cannot travel down vias, thermal pad
stand-off (after reflow) is more consistent, voiding levels are reduced since solder is not being taken from the thermal pad
and the SMD outgassing channels are embedded. Symmetrical solder pad print layouts minimize component tilting or skewing during reflow, reducing I/O shorts and opens risks. The result is more effective thermal and power management of the
device, with a high level of thermomechanical reliability. Another benefit to this approach is the design’s wide application
window. Using 203-µm, 254-µm or 305-µm finished hole size vias with solder mask can enable SMD window designs spanning printed board thicknesses of 1 mm to 6.35 mm. Via padding options are aspect ratio dependent and do not offer this
range.
The design also enables a safe and high-quality rework solution. With solder not able to travel down vias, component
removal and site redress operations are simplified. The risk of back-side solder protrusions during defective part removal is
eliminated, reducing the need for dangerous operator hand-iron touch-up actions. The use of standard 0.15-mm solder mask
webs helps ensure solder mask peeling does not occur during site redress.
6.11.1.1 Benefits
There are several advantages to using this design approach including:
• Can be applied across wide printed board thickness, size and complexity ranges
• Consistent, low-variability stand-off after soldering
• Good percentage thermal pad coverage, which meets or exceeds minimum component supplier requirements
• Drives elimination of solder wicking down vias (primary attach and rework operations)
• Enables dual-sided SMT assembly, avoiding back-side solder protrusions
• Open SMT process windows overall
• Rework enablement
• Minimal operator touch-up required
• Low cost, utilizing conventional through-hole and solder mask technologies
6.11.1.2 Drawbacks
It should be noted that there are some known drawbacks when using this approach:
• Inclusion of through-hole vias on grid can decrease wireability options and freedom around BTC locations
• Stencil design complexity increases, requiring increased stencil designer skill and stencil fabricator quality
• SMD trenches use minimum solder mask webs; 0.15-µm webs require added printed board supplier capabilities
• Slight reduction in thermal pad percentage coverage when soldered (variation improved but with slightly less coverage)
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6.11.1.3 Implementation and Example Layouts The shape
and number of solder windows using this design point depend
on:
• Overall size of the BTC
• Number of thermal vias required to dissipate heat and
current
• Thermal via size and pitch selected for the design
Figure 6-31 Common Solder Mask Defined (SMD) Layouts
for Fewer Than Nine Vias
Resulting geometry examples using this approach are shown
in Figure 6-31, Figure 6-32 and Figure 6-33 (figures not to
scale). Thermal solder pad windows can be rectangular or a
variety of polygon shapes, as illustrated in the figures.
Next-generation designs are being produced with multiple
thermal pad areas requiring special design considerations for
each segment. Figure 6-34 shows an example BTC thermal
pad with three distinct thermal pad areas. Via counts, pitch
and locations as well as solder percentage coverage and stencil aperture design all should be considered when designing
the thermal pad for these types of devices.
Figure 6-32 Common Solder Mask Defined (SMD) Layouts
Incorporating Nine Vias
Figure 6-33 Complex Solder Mask Defined (SMD) Layouts
with Via Counts Ranging from Five to 31 or More
Figure 6-34
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6.11.1.4 Design Parameters Table 6-3 provides guidance on the various printed board design, material and process
parameters that have been successfully implemented using the design point. While thorough, it may not be considered
exhaustive, and ranges may be further expanded as user experience levels increase.
Table 6-3
Solder Mask Defined (SMD) Design Point Parameters
Parameter
Design Recommendation
Printed board surface finish
Cu-OSP
Laminate type
Pb-free qualified
Printed board thickness range
1 mm to 6.35 mm
Printed board surface Cu foil
17.1 µm to 51 µm
Printed board subsurface Cu
17.1 µm to ≥ 68.6 µm
Solder paste alloy
SAC 305 / SAC 405
Powder mesh size
Type 3 / Type 4
SMT reflow soldering
Convection or vapor phase
Reflow atmosphere
N (< 1000ppm O2)
Reflow maximum peak temperature
250 °C
Reflow maximum TAL
60 to 200 seconds
Flux chemistry
No clean / Water soluble
Package size range
1.2 mm2 to ≥ 9mm2
Thermal via type
SMD open through-hole
Via plugging
None
Via connection type
Solid plane / No thermal relief
Via quantity range
1 to ≥ 30
Via finished hole size range
203 µm / 254 µm / 305 µm, up to 0.7 mm
Via locations
Evenly distributed orthogonal arrays; maximizes wireability
Minimum via pitch
0.8 mm
Minimum solder mask web
152 µm under thermal pad
I/O solder mask definition
SMD; no ganged openings
Printed board thermal pad size
Equal to component die paddle size
Thermal pad geometry
Symmetric, evenly distributed, multiple smaller windows
Thermal pad coverage
50 % to 75 %
Stencil aperture ratios
> 0.67; 0.80 target
Stencil print windows
1:1 with printed board Cu shapes
Standard electronics manufacturing services (EMS) print capabilities
Final soldered stand-off
50 µm to 75 µm
Thermal pad voiding*
< 30 %
*Typical voiding levels. See IPC-A-610 and J-STD-001 for voiding requirements.
6.11.2 Open-Cu Thermal Pad Design For an open-Cu thermal pad design, through-hole vias are placed within the Cu
thermal pad soldering area of the printed board (see Figure 6-35). Thermal vias can be connected to internal grounding layers subsurface within the printed board. The vias are neither padded nor tented for this design option. Moreover, no solder
resist barriers are used to restrict solder flow during the reflow operation. During the reflow solder process, the printed
deposits will reflow, outgas and eventually merge with adjacent deposits to create a printed board thermal pad structure that
is completely soldered to the exposed die paddle, maximizing the thermal connection area under the package.
6.11.2.1 Benefits
There are two main benefits in selecting this design option:
• They are a low-cost solution. Because this design option uses standard printed board technology, including the use of
simple through-hole vias placed within a Cu area, it is cost-neutral when the printed board already features PTHs.
• They provide excellent thermal conductivity for printed-board-based heat dissipation. Since the majority of the thermal pad
soldering area can be used for placing vias, this design option provides a high degree of freedom. Vias can be placed
directly below the die enabling highly optimized thermal paths. For example, using vias with a finished hole size of 500 µm
in a hexagonally close-packed array with pitch 1 mm, thermal conductivities exceeding 30 W / (m K) can be realized.
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Figure 6-35
Open Thermal Through-Hole Via Structure
6.11.2.2 Drawbacks
In practice, when using an open-Cu pad design, printed solder paste, which cannot be accommodated within the stand-off of the component on the exposed-pad soldering area, may penetrate into open through-hole
vias (solder wicking). The notion solder wicking has become widely used, but it is, strictly speaking, not correct under most
circumstances. Wicking suggests that the vias draw in solder by a capillary action. However, if the radius of the vias is bigger than the stand-off, the equilibrium capillary pressure for solder inside the via is higher than for solder in the stand-off;
therefore, filling vias is not a spontaneous process (i.e., the vias do not wick solder, but excess solder gets pushed into the
vias). Solder wicking by itself is not a problem, but it involves a risk for the formation of solder protrusions, which is discussed in 6.11.2.2.2.
6.11.2.2.1 Solder Wicking
How solder protrusions (see Figure 6-36 for an example) are formed is not fully understood. What is known is that they only occur for vias with at least a partial solder filling. The solder then is pushed out of
the via due to formation of large volumes of gas which could either result from outgassing of flux trapped in the via or by
outgassing of the printed board base material through plating voids in the via walls during the reflow process
(see Figure 6-36). If such a protrusion is present after reflow, solder paste stencil printing on the reflow side opposite the
device is not possible. The gap created by opposite protrusions will not allow the solder stencil to properly gasket the printed
board; therefore, restricting the print operation. Solder protrusions on the opposite surface can also leave behind dangerous
solder shards that may become a subsequent shorting risk. Protrusions also lead to increased rework and touch-up operations; introducing operator handling, additional flux application and heat cycles, all of which should be well controlled.
6.11.2.2.2 Solder Protrusions
T
T
Figure 6-36
IPC-7093a-6-36
Solder Protrusion Under Quad Flat No-Lead (QFN) Thermal Pad
Note: Opposite side of the board (left) and schematic cross-section of a thermal pad solder joint exhibiting a solder protrusion. Voiding is caused by outgassing
plating voids (left via) and outgassing flux (right via).
6.11.2.3 Component Stand-Off For this design option, component stand-off will be determined by the components’
printed board coplanarity limit when a design avoiding solder wicking is adopted. It will be at the lowest physically possible limit. Because stand-off affects the (thermal cycling) reliability of the I/O solder joints, choosing this design option
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may negatively affect the components’ board-level reliability (see Section 8). By applying excessive solder and accepting
solder wicking, a larger stand-off can be adjusted, but this may be paralleled by increased thermal pad voiding levels and
component stand-off variations, including tilting and floating.
In principle, open-via structures provide an efficient path for outgassing (i.e., venting of gaseous species
originating from flux). However, if via density is low and solder volume is high, extended continuous areas of solder without vias in them may exhibit excessive voiding levels (e.g., > 30 % of soldered area). A high density of vias generally avoids
excessive voiding.
6.11.2.4 Voiding
If BTCs using an open-Cu thermal pad require rework, additional
care and attention should be used. Removal of the defective device using a hot-gas rework tool is easily accomplished; however, site clean-up, redress and new component attachment should be implemented to not allow excessive paste or flux to
wick down vias and transfer to the back side of the assembly. Solder that travels down vias after site redress is very likely
with this design point and may lead to back-side solder protrusions, which can pose a reliability hazard over the longer term,
at the system level. Increased operator touch-up instances during final visual inspection of product are common when using
open-Cu pad designs. More flux is often added during touch-up operations and can lead to other potential flux-induced
assembly defects if not properly controlled (e.g., dendritic growth, electrochemical migration under voltage bias, humidity
in field operation).
6.11.2.5 Rework Difficulties and Excessive Touch-Up
Since solder-resist barriers are not required, this design option provides
total freedom for placing vias. Usually, a regular and symmetric via arrangement is chosen, but this is not mandatory
see 6.10.4).
6.11.2.6 Implementation and Example Layouts
To avoid solder filling of vias during printing, print the solder paste in a pattern that will avoid covering via holes. The
amount of solder paste should be carefully balanced. Assess how much solder (volume V) has to be applied for a thermal
pad solder joint to provide sufficient soldered area (A) and no excess solder in the vias. A careful analysis of the overall
thermal performance is required to determine an appropriate minimal solder coverage. Typically, a coverage of at least 10 %
of the component’s thermal pad area is recommended to avoid a negative effect on thermal performance. Even such a low
solder coverage will be sufficient under most circumstances because the overall thermal resistance between the junction and
the side of the printed board opposite the device is still largely determined by the thermal resistance of the thermal vias.
Solder in vias carries the risk of solder protrusions. If such protrusions cannot be tolerated, solder penetration into the vias
should be avoided (see 6.11.2.2).
For a component with nominal component stand-off (h) and
thermal pad area Amax, the maximal solder volume can be
calculated as Vmax = Amax (h). Since most thermal pads are
sufficiently large edge, effects can be neglected in this equation. The optimum solder joint is formed if the complete solderable area Amax is soldered and the filling (f) of the vias is
zero (see Figure 6-37). An optimal design is achieved if the
solder volume Vmax is applied.
Unfortunately, achieving this ideal target condition is not possible under practical circumstances. First of all, a BTC has no
defined stand-off at the exposed pad, as compared to components with gull-wing I/O solder terminals (e.g., QFPs). For a
BTC with the exposed thermal pad soldered to an open-Cu
land with vias, the stand-off will decrease down to a limiting
stand-off determined by the components and the printed board
coplanarity. In equilibrium, the component’s lower surface
will rest on solder resist, and a typical stand-off between
10 µm and 40 µm will result. Due to variation of the component stand-off (h) and the additional variation of the printed
1
2
A
A Max
2
1
V
f
2
V
1
V Max
Figure 6-37
IPC-7093a-6-37
Graph of Soldered Area and Filling of Vias
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solder volume (V), it is not possible to always achieve the
optimal solder volume. If solder in the vias and the potential
formation of protrusions cannot be tolerated, measures to
avoid a situation with solder in the vias (see Figure 6-38 (a))
would be a reduction of solder paste volume (see Figure 6-38)
or the usage of solder resist around the vias (see Figure 6-38
(c)), both resulting in a great reduction of soldered area and
significant restriction for the density of the via placement.
An example for the consequence of excessive solder volume
is shown in Figure 6-39, which contains a micrograph of the
soldering area of a QFN, which has five open thermal vias
(left side). The corresponding SMT solder stencil print layout
is shown in the middle. The solder print window pattern
shown has been designed to furnish a path for outgassing and
minimizing solder migration into the plated vias during reflow
processing (shown as white areas in the middle image). However, the X-ray image on the right side demonstrates that all
five vias have been at least partially filled with solder during
reflow.
A variant of the open-Cu via design is the use of encroached
vias (see Figure 6-40). In this design, solder mask is applied
October 2020
A
A Max
f
a
V
A
A Max
f
b
V
A
A Max
c
f
V
IPC-7093a-6-38
Figure 6-38 Process Variation (Blue Gaussian Curve)
Results in Filled Vias if the Nominal Solder Volume Is Set
to Vmax
Note: This can be avoided by reduction of the nominal solder volume and
application of solder resist.
Figure 6-39 Micrograph of Quad Flat No-Lead (QFN) Land with Open-Cu Thermal Pad Design (Left), Solder Print Window
Pattern (Middle) and X-Ray Image After Reflow (Right)
to the bottom side of the thermal pad soldering area. Solder
mask encroachment implies the solder mask aperture is larger
than the finished hole size by ~100 µm to 200 µm to avoid the
penetration of primary solder mask into the via.
The presence of solder mask on the bottom side restricts the
flow of solder and suppresses the formation of bulbous protrusions. However, it cannot fully eliminate solder protrusions;
therefore, it is of limited use.
Table 6-4 provides guidance on the various printed board
design, material and process parameters that have been successfully implemented using this design point. While thorough, it may not be considered exhaustive and ranges may be
further expanded as user experience levels increase.
72
Figure 6-40 Open-Cu Via Design without Solder Mask
(Left) and with Encroached Solder Mask (Right) on the
Bottom Side of the Printed Board
October 2020
IPC-7093A
Table 6-4
Open-Cu Thermal Pad Design Parameters
Parameter
Design Recommendation
Printed board surface finish
No restrictions
Laminate type
Pb-free qualified
Printed board thickness range
No restrictions
Printed board surface Cu foil
No restrictions
Printed board subsurface Cu
No restrictions
Solder paste alloy
No restrictions
Powder mesh size
No restrictions
SMT reflow soldering
Convection or vapor phase
Reflow atmosphere
No restrictions
Reflow maximum peak temperature
No restrictions
Reflow maximum TAL
No restrictions
Flux chemistry
No restrictions
Package size range
1.2 mm2 to ≥ 9 mm2
Thermal via type
SMD open through-hole
Via plugging
None
Via connection type
Solid plane / No thermal relief
Via quantity range
1 to ≥ 30
Via finished hole size range
0.2 mm to 0.7 mm
Via locations
Typically, evenly distributed
Minimum via pitch
2X via diameter for a hexagonally close-packed via arrangement
Minimum solder mask web
NA
I/O solder mask definition
NSMD (recommended)
Printed board thermal pad size
Equal to component die paddle size
Thermal pad geometry
NA
Thermal pad coverage
10 % to 100 %
Stencil aperture ratios
> 0.67
Stencil print windows
Depending on via arrangement and intended solder volume, printing on via apertures
is to be avoided
Final soldered stand-off
Not defined, lower limit given by coplanarity limit
Thermal pad voiding*
Typically < 30 %
*Typical voiding levels. See IPC-A-610 and J-STD-001 for voiding requirements.
6.11.3 Via Tenting Thermal Pad Design For a design based
on via tenting, through-hole vias are placed within the Cu
thermal pad soldering area of the printed board, which can be
connected to subsurface internal grounding layers within the
printed board for spreading heat from the device mounted also
within the printed board. The vias are covered (i.e., tented by
solder mask) (see Figure 6-41). During reflow, printed solder
deposits will reflow, outgas and eventually merge with adjacent deposits to create a printed board thermal pad structure
that is soldered to the exposed die paddle, except for the area
of the tented vias.
B
A
IPC-7093a-6-41
6.11.3.1 Benefits There are benefits to this design option. Figure 6-41 Design with Top-Side Solder Mask Via Tenting
B – BTC topside placement area
As the solder mask seals off the via from the solder volume at A – Printed board topside
the exposed-pad solder joint, any solder in the via can be reliably excluded. The application of dry-film solder mask for via tenting requires an additional process step. Via tenting is not
cost-neutral, but the cost adder is lower compared with other design options, such as VIPPO.
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6.11.3.2 Drawbacks
6.11.3.2.1 Printed Board Reliability Via tenting can entrap printed board etch chemistry during the printed board laminate fabrication process and/or assembly chemistries (primarily flux leaching) during printed board assembly. Entrapped
chemistry within tented vias can be a reliability hazard or risk depending on application requirements.
This design option requires stable top-mask adhesion to reliably separate solder from
the vias. This is usually not a concern during up to three reflow cycles, but the adhesion may become critical during rework
operations, which may result in solder mask flaking off Cu via annular rings.
6.11.3.2.2 Solder Mask Adhesion
Compared with the open-Cu thermal pad design option, tented via structures cannot provide a path for
outgassing (i.e., venting of gaseous species originating from flux). If a high volume of solder is applied, excessive voiding
levels (e.g., > 40 % of soldered area) may occur. In this case, a reduction of the solder volume is recommended.
6.11.3.2.3 Voiding
For tented vias, secondary solder mask is applied locally by using a
screen mesh. This secondary solder mask is a dry-film solder mask with high solid (nonvolatile) content between 75 % and
90 %, which does not drip into a via. Wet-film solder mask cannot successfully tent via holes. The degree of fill needs some
control to develop a pad that prevents chemistry from going through a via. Partially filled vias trap process chemicals and
are difficult to clean. To ensure adhesion of the solder mask, the solder mask diameter should be at least 100 µm larger than
the finished hole diameter.
6.11.3.3 Implementation and Example Layouts
Table 6-5 provides guidance on the various printed board design, material and process parameters that have been successfully implemented using this design point. While thorough, it may not be considered exhaustive, and ranges may be further
expanded as user experience levels increase.
6.11.4 Encroached Via Thermal Pad Design The concept of encroached vias permits solder mask being on the land without filling the plated through-hole. Encroached vias take the primary solder mask opening and adjust it so it is slightly (typically, 50 µm to 200 µm) larger than the via hole size. The concept permits outgassing and proper cleaning of the PTH,
provides more surface coverage and increases adhesion between the solder mask and Cu of the annular ring. It also provides
a larger web between the land and the via, so it should minimize solder mask removal during BTC removal for rework.
See 7.12.
The use of encroached vias is a variant of the open-Cu thermal pad option. The design point is similar, with the exception
of back-side encroached via additions. See 6.8.1 for design details.
A VIPPO thermal pad design point incorporates VIPPO via
structures within the BTC thermal pad. Because thermal vias are plated over with Cu, there is no risk of solder wicking
using this design option. With VIPPO thermal pad vias added, the resulting structure is similar to the open-Cu option
(see 6.11.2) with no solder mask applied to the thermal pad area under the device.
6.11.5 Via-in-Pad Plated-Over (VIPPO) Thermal Pad Design
The difference with this design point is the via type used. Since VIPPO vias are filled and Cu-capped, solder can be applied
freely to the thermal pad area. While the risk of solder wicking is eliminated, efforts to minimize thermal pad solder voiding remain a challenge with this option. Placing VIPPO vias on-grid is still important for this design point. Although not
needed to help with device soldering, on-grid VIPPO arrays help with sublayer wire routing under the device.
It is important to note that inclusion of VIPPO vias can increase printed board fabrication costs 15 % to 20 %. It is recommended that the need for VIPPO via integration be well understood and can be supported from a cost perspective. VIPPO
addition can be quite costly over the duration of a program, dependent on the volume of boards assembled.
VIPPO vias are constructed using conventional through-hole vias that are epoxy-filled and Cu-capped (see Figure 6-42).
They are typically fabricated using an FHS range of 203 µm to 305 µm. The resulting structure is a planar solderable surface that is electrically and thermally connected to internal layers spanning the printed board cross-section. See IPC-6012
for further detail on VIPPO construction and control features.
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Table 6-5
Via Tenting Thermal Pad Design Parameters
Parameter
Design Recommendation
Printed board surface finish
No restrictions
Laminate type
Pb-free qualified
Printed board thickness range
No restrictions
Printed board surface Cu foil
No restrictions
Printed board subsurface Cu
No restrictions
Solder paste alloy
SAC 305 / SAC 405
Other pastes (e.g., low-temperature solder) may require further characterization
Powder mesh size
No restrictions
SMT reflow soldering
Convection or vapor phase
Reflow atmosphere
No restrictions
Reflow maximum peak temperature
No restrictions
Reflow maximum TAL
No restrictions
Flux chemistry
No restrictions
Package size range
1.2 mm2 to ≥ 9 mm2
Thermal via type
Via, tented (Type 1 via)
Via plugging
None
Via connection type
Solid plane / No thermal relief
Via quantity range
1 to ≥ 30
Via finished hole size range
0.2 mm to 0.7 mm
Via locations
Typically, evenly distributed
Minimum via pitch
2X via diameter + 100 µm
Minimum solder mask web
NA
I/O solder mask definition
NSMD (recommended)
Printed board thermal pad size
Equal to component die paddle size
Thermal pad geometry
NA
Thermal pad coverage
Typically, 10 % to 80 %
Stencil aperture ratios
> 0.67
Stencil print windows
Depending on via arrangement and intended solder volume, printing on via apertures
is to be avoided
Final soldered stand-off
Minimum is coplanarity limit (height of solder mask used for via tenting) or higher
Thermal pad voiding*
Typically, < 50 %
*Typical voiding levels. See IPC-A-610 and J-STD-001 for voiding requirements.
A
B
IPC-7093a-6-42
Figure 6-42
Via-in-Pad Plated-Over (VIPPO) Thermal Pad Illustration and Cross-Section
A – Cu capped
B – Epoxy filled
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There are several goals with this approach including:
• If VIPPO vias are required elsewhere on the printed board, can also use VIPPO vias in thermal pad areas
• Offers complete elimination of the risk of solder wicking down vias; only option that fully eliminates this risk
• Enables a simplified stencil design point
6.11.5.1 Benefits
There are several advantages to using this design approach including:
• VIPPO completely eliminates the risk of solder wicking down vias; no other option offers this.
• It enables maximum percentage solder coverage for the thermal pad, and the entire die paddle can be soldered to the
printed board.
• During rework, there is no risk of solder wicking and no solder mask damage risk for thermal pad (site redress).
• It enables higher via counts if needed.
6.11.5.2 Drawbacks
It should be noted that there are some known drawbacks when using this approach:
• Adding VIPPO vias to a design is a printed board cost adder and can be significant (15 % to 20 % increase).
• There is a limited printed board fabrication supply base that can produce high-quality, high-reliability VIPPO structures.
• VIPPO has limited printed board thickness usage (typically 1.6 mm to 2.8 mm).
• There are reliability unknowns when introducing VIPPO vias.
6.11.5.3 Implementation and Example Layouts
Figure 6-43 shows VIPPO vias implemented within a printed
board assembly. This image shows through-hole vias that have
been filled and Cu-capped. This back-side image (under the
BTC) shows these via locations look like SMT pads, but they
are not. Looking closely at the figure, through-hole via outlines can be observed, now capped and planarized.
Table 6-6 provides guidance on the various printed board
design, material and process parameters that have been successfully implemented using this design point. While thorough, it may not be considered exhaustive, and ranges may be
further expanded as user experience levels increase.
Figure 6-43
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IPC-7093A
Table 6-6
Via-in-Pad Plated-Over (VIPPO) Design Parameters
Parameter
Design Recommendation
Printed board surface finish
Cu-OSP
Laminate type
Pb-free qualified
Printed board thickness range
1 mm to 6.35 mm
Printed board surface Cu foil
17.1 µm to 51 µm
Printed board subsurface Cu
17.1 µm to ≥ 68.6 µm
Solder paste alloy
SAC 305 / SAC 405
Other pastes (e.g., low-temperature solder) may require further characterization.
Powder mesh size
Type 3 or Type 4
SMT reflow soldering
Convection or vapor phase
Reflow atmosphere
N (< 1,000 ppm O2)
Reflow maximum peak temperature
250 °C
Reflow maximum TAL
60 to 200 seconds
Flux chemistry
No-clean / Water soluble
Package size range
1.2 mm2 to ≥ 9 mm2
Thermal via type
VIPPO
Via plugging
None
Via connection type
Solid plane / No thermal relief
Via quantity range
1 to ≥ 30
Via finished hole size range
203 µm / 254 µm / 305 µm, up to 0.7 mm
Via locations
Evenly distributed orthogonal arrays; maximizes wireability
Minimum via pitch
0.8 mm
Minimum solder mask web
0.15 mm under thermal pad
I/O solder mask definition
SMD; no ganged openings
Printed board thermal pad size
Equal to component die paddle size
Thermal pad geometry
Symmetric, evenly distributed, multiple smaller windows
Thermal pad coverage
50 % to 75 %
Stencil aperture ratios
> 0.67; 0.80 target
Stencil print windows
1:1 with printed board Cu shapes
Standard EMS print capabilities
Final soldered stand-off
50 µm to 75 µm
Thermal pad voiding*
< 30%
*Typical voiding levels. See IPC-A-610 and J-STD-001 for voiding requirements.
6.11.6 Floating Mask Thermal Pad Design For a design
based on floating solder mask, through-hole vias are placed
within the Cu thermal pad soldering area of the printed board,
which can be connected to subsurface internal grounding layers within the printed board for spreading heat from the
device, which is also mounted within the printed board. The
vias are not covered by solder mask but are surrounded by a
circular solder-resist rim. This solder-resist rim acts as a barrier for liquid solder to prevent it from penetrating into the via
during reflow (see Figure 6-44).
6.11.6.1 Benefits
There are many benefits to this design
IPC-7093a-6-44
Figure 6-44 Floating Solder Mask Via Design CrossSectional and Planar Top Views
approach.
As the solder mask barrier prevents solder from penetrating into the via, solder in the via can be precisely mitigated in combination with proper solder stencil design. Because this design option uses standard printed board technology including the
use of simple through-hole vias placed within a Cu area and primary solder mask, it is cost-neutral when the printed board
already features plated through-holes.
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Floating solder mask rings around vias helps minimize the potential for solder traveling down vias during local hot-gas
rework of a BTC, site removal and redress operations.
6.11.6.2 Drawbacks
There are several known drawbacks to this design option.
If a high volume of solder is applied on extended areas without thermal vias, excessive voiding levels (e.g., > 40 % of soldered area) may occur. In this case, a reduction of the solder volume is recommended. Additionally, a higher density of vias
reduces voiding because the open vias provide channels for outgassing.
The solder-resist barrier may not be effective under all circumstances in mitigating solder penetration into the vias. Too
high of a solder volume, a solder mask barrier that is too narrow and a distance of the printed solder paste to the resist barrier that is too small are all design-related factors which can
increase the risk of spill-over (i.e., the penetration of solder
into the thermal via). Using an appropriate design based on a
statistical tolerancing of typical production tolerances, spillover can reliably be avoided.
A
Solder mask rings located within a thermal pad via array may
not connect to other solder mask locations (see Figure 6-45);
however, they can be singulated rings that adhere to the Cu
surface near thermal vias.
Therefore, the area available for floating solder mask adhesion
is low. This can pose potential problems during rework of the
BTC device. Excessive shear force during site redress (from
Cu braid solder wick) can damage floating solder mask rings
and in some cases may entirely remove a floating mask ring.
Care should be taken during rework (specifically site redress)
to not damage floating mask structures within the thermal pad.
Solder stencil apertures should be
designed to avoid floating solder mask locations and only
deposit solder onto Cu areas within the thermal pad. Since the
open-Cu area can be quite large, the stencil design should
incorporate multiple aperture windows to help with flux outgassing during reflow. If stencils are not properly designed,
large coalesced voids in the thermal pad solder joint may
occur.
6.11.6.3 Stencil Design
The solder
mask ring around vias can be applied as primary solder mask,
so no secondary solder mask deposition (like for the tented via
option) is required. The solder-resist barrier should have a
width of at least 150 µm to be effective in mitigating solder
fill of vias. If the width is too small, solder may spill over
the barrier during reflow, or the paste may even be squeezed
onto and over the barrier during pick-and-place, if the placement process is not well controlled. Solder paste should
normally be printed only onto Cu and not onto the solder
mask barrier. This is done by leaving a gap to the solder
mask barrier to ensure this condition is fulfilled under typical
solder mask registration and stencil displacement tolerances
(see Figure 6-46).
B
Figure 6-45
Location
Singulated Mask Location vs. Tied Mask
A – Singulated: less mask adhesion
B – Tied: more mask adhesion
6.11.6.4 Implementation and Example Layouts
Figure 6-46 Example Implementation of a Floating Solder
Mask Design
A – Singulated: less mask adhesion
B – Tied: more mask adhesion
Table 6-7 provides guidance on the various printed board design, material and process parameters that have been successfully implemented using this design point. While thorough, it may not be considered exhaustive, and ranges may be further
expanded as user experience levels increase.
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Table 6-7
Floating Solder Mask Design Parameters
Parameter
Design Recommendation
Printed board surface finish
No restrictions
Laminate type
Pb-free qualified
Printed board thickness range
No restrictions
Printed board surface Cu foil
No restrictions
Printed board subsurface Cu
No restrictions
Solder paste alloy
No restrictions
Powder mesh size
No restrictions
SMT reflow soldering
Convection or vapor phase
Reflow atmosphere
No restrictions
Reflow maximum peak temperature
No restrictions
Reflow maximum TAL
No restrictions
Flux chemistry
No restrictions
Package size range
1.2 mm2 to ≥ 9 mm2
Thermal via type
Open thermal via
Via plugging
None
Via connection type
Solid plane / No thermal relief
Via quantity range
1 to ≥ 30
Via finished hole size range
0.2 mm to 0.7 mm
Via locations
Typically, evenly distributed
Minimum via pitch
2X via diameter + 150 µm
Minimum solder mask web
150 µm
I/O solder mask definition
NSMD (recommended)
Printed board thermal pad size
Equal to component die paddle size
Thermal pad geometry
NA
Thermal pad coverage
Typically, > 60 %
Stencil aperture ratios
> 0.67
Stencil print windows
Depending on via arrangement and intended solder volume, printing on via
apertures is to be avoided.
Final soldered stand-off
Minimum is coplanarity limit (height of solder mask used for via tenting) or higher.
Thermal pad voiding*
Typically, < 50 %
*Typical voiding levels. See IPC-A-610 and J-STD-001 for voiding requirements.
6.12 Design for Cleaning Considerations There has been much debate about whether or not to clean flux residues from
under BTCs. Low component stand-off dimensions (typically ≤ 51 µm to 76 µm) after SMT reflow are of primary interest
for BTC cleaning. The technical risk of concern is SMT solder paste flux residue can be trapped within this very small
stand-off and may not be properly thermally activated, and cleaning agents may not be able to access and remove them.
Because the gap between the BTC and printed board is so small, when using water-soluble paste and flux, it is critical that
cleanliness testing is performed to ensure the board passes cleanliness requirements in J-STD-001. This condition can
potentially occur after SMT reflow primary attach processing or after local rework of a BTC device. These potentially
chemically active residues can lead to unwanted reliability issues including dendritic growth, conductive anodic filament
(CAF) formation or corrosion. The concern with these reliability failure modes is they are often latent defects not necessarily identified or corrected during assembly and test operations, and they are accelerated under product operating temperature, humidity and power-on voltage bias.
To help determine if cleaning BTCs is required for a particular application, it first should be determined which type of SMT
paste flux chemistry is being used on the assembly: no-clean or water soluble. According to J-STD-004, these flux chemistries are very different, with different levels of chemical activity and different residue structures. The decision to clean (or
not clean) BTC structures are dependent upon the flux chemistry used. When it comes to cleaning, there are three options:
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In this case, no cleaning steps or chemistry are added to the
assembly process. Flux residues left behind are left alone and not cleaned. This option can work well with a low risk of
dendritic growth or CAF based on the following elements:
Option 1: Cleaning Is Not Conducted Using No-Clean Flux
• BTC devices are of low thermal mass and tend to not be among the coldest locations on a printed board during SMT
reflow. Maximum peak temperatures generally range from 235 °C to 250 °C, and TAL (217 °C) values range from 60 to
150 seconds when using a conventional SAC Pb-free SMT reflow process. If using a SnPb solder process, the same statement applies with maximum peak temperatures ranging from 205 °C to 225 °C and TAL (183 °C) values ranging from 60
to 150 seconds. These temperatures and times, if followed correctly, should be sufficient to thermally activate SMT
no-clean fluxes under BTCs.
• Sufficient thermal activation of SMT no-clean solder paste is very important and can be easily achieved with industrialgrade SMT reflow or vapor phase ovens. Thermal duty of these ovens can easily deliver the required temperature and
time-at-temperature required to properly activate SMT no-clean fluxes.
• Thermal profiling is critical to ensure proper temperatures and times are being met locally under a BTC. Thermocouples
should be affixed on BTC I/O joints, on the component body and under the device attached to the printed board thermal
pad. Low temperatures and times under BTCs can lead to nonactivated no-clean flux conditions. It is important to note
that a BTC thermal pad is connected to various ground layers within a printed board stack-up (connected by thermal vias).
This thermal pad location is a heat sink by design. Efforts to understand the temperature is this region is very important.
See 7.9.
• No-clean flux residues, once properly thermally activated, are protected (by design) with an outer resin shell. The resin
acts as a protective layer but needs to be properly activated and formed. If properly activated, no cleaning is required.
• There are several benefits with this approach. No additional cleaning process steps, cleaning equipment, cleaning chemistry consumable materials or cleaning waste stream disposal processes and costs are needed.
Option 2: Cleaning Is Conducted Using No-Clean Flux In this case, cleaning steps and cleaning chemistry are added to the
assembly process. Flux residues left behind are being cleaned at the assembly manufacturer, even though the no-clean
chemistry was formulated to not be cleaned. This option can work well with a low risk of dendritic growth or CAF based
on the following elements:
• Proper cleaning chemistry matched with flux chemistry is important.
• For some applications (e.g., implantable devices), ultra-cleanliness is a requirement.
• Add the type of chemistry used for cleaning no-clean residues (e.g., saponifier).
• Cleaning a no-clean chemistry can be very good, but cleanliness levels need to be quantitatively measurable.
• Be prepared to invest in washing equipment, consumables and added test measurement protocol as well as to allow for
process throughput detractors.
• Benefit: Removal of flux residues after cleaning helps to improve solder joint visual inspection quality.
• Concerns: Be aware that partially cleaning a no-clean chemistry can be dangerous. It is important to have a repeatable
cleanliness level technique developed. It is also important to know the ability of the chemistry to penetrate very tight
stand-offs of BTCs.
• The cleaning process itself should be analyzed to ensure no residual cleaning material is left behind under the parts.
Because of the low profiles and the geometry of the BTC, the cleaning solution may penetrate under the part but may not
always completely rinse out. Depending on the chemistry used, this could introduce long-term reliability concerns. Refer
to IPC-CH-65 and IPC-9201 for guidance on cleaning assemblies.
In this case, cleaning steps and cleaning chemistry are added to
the assembly process. Flux residues left behind are intended to be cleaned. This option can work very well with a low risk
of dendritic growth or CAF based on the following elements:
Option 3: Cleaning Is Conducted Using Water-Soluble Flux
• By design, water-soluble flux chemistry should be cleaned from the assembly. Failing to wash away weak organic acid
residues from the assembly (including from under BTCs) will lead to certain dendritic growth and/or CAF conditions and
corrosion.
• Deionized water (and saponifier) is used as the cleaning agent for this option.
• Cleaning a water-soluble chemistry can be very good, but cleanliness levels need to be quantitatively measurable (Sn salts).
• Be prepared to invest in washing equipment, consumables and added test measurement protocol as well as to allow for
process throughput detractors.
• Benefit: Removal of flux residues after cleaning helps to improve solder joint visual inspection quality.
• Concern: It is important to know the ability of the chemistry to penetrate very tight stand-offs of BTCs.
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BTCs devices have two distinct areas that require solder paste printing to form an
electrical connection between the component and the printed board. The following sections provide guidance for stencil
design considerations to solder paste print BTC thermal pads (see 6.13.1) and perimeter I/O solder pads (see 6.13.2). For
additional information regarding stencil design, refer to IPC-7525.
6.13 Stencil Design Considerations
To effectively remove the heat from the package and to enhance package electrical
performance, a BTC component die paddle should be soldered to the printed board using a Cu thermal pad. Not all BTC
packages require thermal pad soldering to the die paddle; specific constructions may not require such a connection. Consult
component supplier requirements to determine if the die paddle requires a soldered connection.
6.13.1 Thermal Pad Stencil Design
Primary stencil design considerations for thermal pads include:
• Minimization of part-to-part printing variation
• Percent solder coverage of the thermal pad area
• Target component stand-off
The following BTC stencil design standpoints guideline is based on area size of QFN thermal pad to select the stencil design
accordingly:
Larger pads
Smaller pads
> 4 mm2
< 4 mm2
Striped apertures are better than square/rectangle/polygon apertures.
Square/rectangle/polygon apertures are recommended design point.
1) Stencil apertures should be designed to always follow Cu geometry found on the printed board. It is recommended to
start with a 1:1 design with Cu features. However, if too much solder is printed, try to reduce aperture dimensions. Often
10 % reductions can reduce/eliminate excessive solder prints. Observations of solder down vias, bridging or solder balling can be an indicator of too much solder, requiring such stencil aperture reductions.
2) For larger thermal pad areas, ≥ 4 mm2, it is recommended to design the stencil to include multiple smaller apertures.
3) Stencil material types can include laser-cut stainless-steel foils or build-up foil technologies.
4) Stencil coatings (nanoparticulate or plasma) may or may not be needed but can be used. Be sure to determine if a coating is necessary for the application. Coating effectiveness has been shown to be a function of device/aperture size.
5) Typical stencil foil thicknesses range from 76 µm to 152 µm, depending on the application and the other components in
the assembly bill of materials (BOM).
6) Step-down stencils for BTCs are generally not recommended, but if needed, a maximum step thickness of 25 µm to
accommodate BTCs can be implemented (i.e., 0.13-mm-thick stencil, stepping down to 102 µm at BTC locations). The
need for a step-stencil design is dependent on the assembly BOM.
7) Target aperture area ratio = Area of aperture opening / Aperture wall area is > 0.66 (for all apertures).
8) Stand-off target range (after solder joint has been formed/collapsed): 50 µm to 76 µm.
When designing stencil apertures to print Cu thermal pads,
two different approaches can be used to attain proper solder paste coverage. Figure 6-47 shows both options. The figure is
not to scale and is intended to be general to show the basic elements of a Cu thermal pad area requiring solder paste printing.
6.13.1.1 Stencil Aperture Design Options for Thermal Pads
IPC-7093a-6-47
Figure 6-47
Cu Area Printed with Single Bulk Aperture (Left) and Cu Area Printed with Multiple Apertures (Right)
Green – solder mask
Orange – Cu area to be soldered
Grey – resulting solder paste deposit from stencil
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As mentioned in 6.13.1, it is important that stencil apertures always follow the Cu design dimensions. Apertures should be
designed 1:1 with a Cu feature, noting that stencil aperture reductions can be made as needed (i.e., 10 % reduction of x/y
Cu pad dimensions are common). Two different options can be utilized when designing stencil apertures, depending on the
size of the Cu area that is being printed. Option 1 is recommended for thermal pad areas < 4 mm2, and Option 2 is recommended for thermal pad areas ≥ 4 mm2.
Option 1 (see Figure 6-48, left) shows how a single bulk (or block) aperture has been implemented, delivering a single solder paste deposit onto a Cu pad. This option works well for BTC thermal pad areas < 4 mm2 with smaller deposit areas.
Option 2 (see Figure 6-48, right) shows how multiple apertures have been implemented, delivering multiple solder paste
deposits onto a Cu pad. This method is often referred to as a striped stencil aperture design (see Figure 6-47, right). This
solder deposit striping method works well for BTC thermal pad areas ≥ 4 mm2 with larger deposit areas. The benefit of using
this stencil design approach is that separating solder deposits helps to reduce large coalescence voids during reflow. As a
result, it helps to reduce overall voiding levels within the Cu thermal pad area because separating solder deposits creates
more outgassing channels. The channels allow volatiles from within SMT paste flux to more effectively escape during reflow.
Outgassing channels are shown as arrows in Figure 6-47, right. Variations of the striped stencil aperture design can include
horizontal, vertical or diagonal apertures.
IPC-7093a-6-48
Figure 6-48
Voiding Levels Using Single Bulk Apertures (Left) and Voiding Levels Using Striped Apertures (Right)
Figure 6-48 shows resulting x-ray images of example of voiding improvements using a striped stencil aperture design with
a nine-via, 4 mm2 thermal pad application. In this example, the only change was the stencil aperture design. All other variables, including solder paste type, reflow profile, thermal pad footprint and component type, remained constant.
The example provided in Figure 6-48 integrates two important design concepts. The Cu thermal pad used was a SMD thermal pad as outlined in 6.11.1. A horizontal-striped stencil design was used to print solder onto the SMD layout. In this
example, thermal pad voiding levels were reduced from 25 % (using single bulk aperture) to between 5 % and 10 % (using
striped-stencil apertures). The combination of a SMD thermal pad and striped-stencil apertures achieved voiding levels
ranging from 5 % to 20 %.
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Figure 6-49 shows optimized results for large- and small-body QFN packages that can be achieved. Solder percent coverage
for all packages is > 50 %, and voiding levels are < 20 %. Stand-off range is 51 µm to 76 µm.
A
B
IPC-7093a-6-49
Figure 6-49 Optimized Striped and Bulk Thermal Pad Stencil Aperture Designs Based on Large Body (Top) and Small Body
(Bottom) Package Sizes
A – Stencil aperture
B – X-ray image
Solder paste coverage can be calculated using two different bases. It can be based on the
entire thermal pad area (see 6.13.1.2.1), or it can be based on an individual solderable area (see 6.13.1.2.2).
6.13.1.2 Percentage Coverage
In this case, percentage coverage is
calculated as a function of the base Cu thermal pad. The resulting solderable area is divided by the total available area as
determined by the component die paddle, as shown in the equation:
6.13.1.2.1 Percentage Coverage Based on Thermal Pad Area – Thermal Pad Basis
% Coverage (Thermal Pad Basis) =
Solderable Area
Total Component Die Paddle Area
Where:
• The solderable area is the total area of all solderable thermal pads.
• The component die paddle area is the area on the printed board that equals the component die paddle area.
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The following is an example calculation using the drawing in Figure 6-50. Percentage coverage using this basis is the ratio
of solder print deposits relative to the entire thermal Cu pad.
% Coverage (Thermal Pad Basis) =
6.53 mm2
= 0.68 = 68 % Coverage
3.099 mm x 3.099 mm
The example calculation of thermal pad area basis uses 6.53 mm2. Solder paste deposit area (denoted by grey regions) is
68 % coverage. Thermal pad Cu area is 3.099 mm2.
In this case, solder mask has been added by design and limits the thermal pad connection area. Be aware this calculation
assumes perfect transfer efficiency for each aperture. The recommended target solder paste coverage range using a thermal
pad basis is 45 % to 85 %.
3.099 mm
1.549 mm
0.497 mm
68%
0.753 mm
0.632 mm
0.444 mm
0.153 mm
0.277 mm
R 0.254 mm
0.727 mm
3.099 mm
0.2032 mm via X5.
0.50 mm
IPC-7093a-6-50
Figure 6-50
Example of Thermal Pad Basis Percentage Coverage
In this case, percentage coverage is calculated as a function of the wettable area of a single Cu pad. This is calculated as the actual print deposit
divided by the available Cu pad, as shown in the following equation:
6.13.1.2.2 Percentage Coverage Based on Individual Solder Area – Solder Stencil Aperture Basis
% Coverage (Solder Stencil Aperture Basis) =
84
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Total Wettable Area of Single Cu Pad
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The following is an example calculation using the drawing in Figure 6-51. Percentage coverage using this basis is the ratio of the actual amount of solder
paste printed on a single pad relative to the total wettable area of a single Cu
pad.
1.549 mm
Example calculation for solder aperture pad:
% Coverage (Solder Aperture Basis) =
2.15 mm2
= 0.90 = 90 % Coverage
2.40 mm2
0.444 mm
Solder paste actual deposit area (denoted by grey region within white pull-back
border) is 90 % coverage.
0.153 mm
In this case, a 10 % pull-back stencil aperture from a 1:1 design point is illustrated. This calculation incorporates solder paste deposition transfer efficiency
delivered by the stencil.
R 0.254 mm
The recommended target solder paste coverage range (solder aperture basis) is
45 % to 100 %.
The final total percentage coverage calculation is as follows. It should be noted
that the thermal pad and stencil aperture basis methods are based on
dimensional calculations only. They represent the maximum theoretical areas
achievable by a design. To obtain actual final total percentage coverage values,
assembly variation and voiding level reductions should be included. Final total
percentage coverage (% FTC) can be calculated as:
IPC-7093a-6-51
Figure 6-51 Solder Aperture Basis
Percentage Coverage
% FTC = Theoretical Design Coverage – Assembly Reductions – Voiding Levels
Where:
• Theoretical design coverage is the maximum coverage based on design dimensions selected.
• Assembly reductions are actual solder paste release rate, stencil reductions and stencil aperture ratio performance.
• Voiding levels are actual voiding levels observed as measured by cross-sectional area.
Perimeter I/O stencil
aperture openings should follow Cu dimensions as found on
the printed board. Stencil design dimensions for I/O pads
should be designed using BTC supplier part print requirements. Always consult the component supplier’s technical
data sheets to ensure I/O solder paste printing requirements
are met. As a starting point, I/O stencil apertures should be
designed 1:1 with Cu I/O pads. Stencil x/y aperture reductions
of 10 % to 20 % can be made if the user is experiencing
assembly-related yield issues (e.g., solder balling, I/O solder
joint shorting). As stated in 6.8.2, I/O solder joints are recommended to be singulated using solder mask webs between I/O
pad locations and individual stencil aperture prints.
6.13.2 Perimeter I/O Stencil Design
In some cases, aperture
reductions from 1:1 Cu geometries may be required by the
assembler to help with printing registration, solder slump or
other assembly line needs. As shown in Figure 6-52, such
aperture reductions are acceptable to meet manufacturer capabilities but need to be optimized and verified accordingly.
Aperture reductions can be made in thermal pad areas and I/O
pad areas. Typical aperture reductions from Cu pads range
from 10 % to 20 %.
6.14 Stencil Aperture Reductions
Figure 6-52
1:1 Stencil Aperture Reductions
Grey – Solder print deposit areas
Orange – Printed board Cu areas
Note: During the early manufacturing stage, it is important to verify that SMT stencil design windows match printed board
Cu thermal pads and I/O. If 1:1 reductions are required by the assembler, optimization and verification will be needed.
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6.15 Important Considerations When Designing for BTCs Widespread use of BTCs has led to the identification of many
issues to avoid when designing and manufacturing assemblies with these devices. See 6.15.1 and 6.15.2 for known issues
to avoid.
6.15.1 Ganged Solder Mask Openings on I/O Terminals Voltage regulation is a common application for BTC devices.
Therefore, circuit designs often integrate surface power and ground shapes as shown in Figure 6-11. If the component symbol is not designed to include SMD I/O pins, ganged opening areas will occur as shown by the arrows in Figure 6-11. Since
there is no solder mask in these ganged area openings, adjacent I/O solder joints have been shown to flow and bridge
together during reflow. Although this has minimal power/ground electrical impact, this is considered a defect according to
IPC-A-610. These bridged solder joints can reduce overall second-level interconnect reliability. It is recommended that SMD
I/O Cu pad geometries be used. This approach ensures singulated I/O connections independent of printed board surface
power/ground configurations.
6.15.2 Mirrored Quad Flat No-Leads (QFN) Constructions
A
Mirrored QFN constructions (see Figure 6-53) are not recommended. Concerns with this design point include:
C
• Excessive operational heat duties
• Sharing of thermal vias
B
• Lack of flux venting channels during second-side QFN
assembly
• Multiple reliability concerns with pinning BTC structures
IPC-7093a-6-53
Figure 6-53
Structure
Mirrored Quad Flat No-Lead (QFN) Example
A – Top-side QFN
As described in 6.10.4, place- B – Bottom-side QFN
ment of through-hole thermal vias within a thermal pad area C – Sharing same thermal vias
should follow standard grid patterns. Random via locations
within a thermal pad should be avoided. The image on the left in Figure 6-26 shows top-side thermal via placement only.
All locations may appear random, but when Cu etch layers are revealed (right side in Figure 6-26), six of the vias are located
for proximity wiring of nearby I/O grounding pins.
6.16 Random Via Locations
The remaining four vias were not wire-routed and were only connected to subsurface power/ground layers. They were placed
in random locations within the thermal pad area. The random via placement illustrated in Figure 6-26 relies on via padding
methods (e.g., tenting, VIPPO). If either of these methods is unacceptable for an application, solder stencil aperture design
is made much more difficult. Balancing thermal pad percent coverage and minimum stencil aperture ratios, while avoiding
open thermal vias, is extremely challenging and may not be possible in some cases. Asymmetric solder deposits on the thermal pad also can lead to other problems. Components have been observed to skew, float and/or tilt causing I/O shorts and
opens, reducing overall first-pass assembly yields. For these reasons, it is recommended to follow standard x/y grid arrays
with thermal via placement and to avoid random placement.
7 ASSEMBLY OF BTCs ON PRINTED BOARDS
The assembly processes for attaching BTCs requires careful process development and control. Process defect rates can be
significantly reduced, but good process control is a necessity. This section provides guidelines on assembly of BTCs,
following an assembly process flow.
7.1 BTC Component Considerations When setting up a robust SMT process with minimal defect rates and repeatable
solder joint formation for attaching BTCs, the following component considerations are crucial.
First, the delivery format into the SMT line (see 7.1.1) needs to be considered for planning the pick-and-place machines.
Next, temperature and moisture sensitivity need to be assessed, based on component supplier data sheets. BTCs generally
do not define the printed board assembly thermal profile for a product. Rather, they are considered part of the whole with
all other components on the board, because they usually are neither temperature-sensitive components nor do they exhibit
a very high thermal mass. However, certain specialized devices (e.g., sensors) may have a limited resistance to soldering
heat (see 7.1.2). Such components will require special considerations when setting up the temperature profile for reflow soldering. BTCs can be MSL 2 and higher. Such components are shipped in moisture-barrier bags and require special handling
to ensure proper surface mount conditions are met (see 7.1.3).
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7.1.1 Incoming Packaging Formats Packaging for BTCs can be tape-and-reel or tray formats. Since machines can pick
and place thousands of components per hour, the component-delivery system should be capable of feeding parts at high
speeds in a consistent orientation. The preferred packing material available to meet these demands, minimizing handling
efforts on the shop floor, is tape-and-reel.
In the tape-and-reel format, components are placed in specifically designed pockets embossed in a plastic carrier tape. A
cover tape is sealed to the carrier tape to keep the parts in place in these pockets in the same orientation. A row of sprocket
holes is provided along one edge of the embossed tape to facilitate indexing. This tape is then wound onto a rigid plastic
reel that provides mechanical stability during handling and storage.
Tray packaging also can be used. Trays are typically standardized JEDEC trays, which are also called matrix trays because
the components are placed in pockets in fixed-position rows and columns. The pitch of each component pocket is standardized. This allows pick-and-place machines to locate and pick up the components from the tray and place them onto a printed
board. The outline dimensions of JEDEC matrix trays are 322.6 mm x 135.89 mm. The low-profile tray, with a thickness
of 6.35 mm, can accommodate all BTCs. For identification of device orientation, a 45° chamfer in one corner provides a
visual indicator of pin 1 orientation of the components contained in the tray.
A major advantage of trays compared to tape-and-reel packaging is baking capability. Components can be baked in JEDEC
trays to reset the floor-life clock of moisture-sensitive components, which is usually not possible for tape-and-reel packaging. Typical temperature ratings for bakeable JEDEC trays are between 140 °C and 180 °C.
BTC parts are shipped in a variety of standard configurations designed for automated assembly system efficiency. QFNs and
BTCs built on substrates are shipped in tubes, stackable JEDEC tray carriers (see Figure 7-1) or tape-and-reel. SONs (DFNs)
are commonly shipped in tubes or tape-and-reel.
Figure 7-1
JEDEC Tray Carrier Format
The overall dimensions of the JEDEC shipping and handling tray carrier are 135.89 mm x 322.6 mm, with components
arranged in a column and row format. The matrix of the pocket pattern is fixed to a standard formula based on the outline
of the semiconductor package. Although the components mounted in the carrier are shipped with dry-pack wrapping, the
plastic material used to mold the carrier should withstand thermal exposure typical of that required for bake-out of components exposed to ambient conditions and prone to moisture retention.
All these package-delivery systems use electrostatic discharge (ESD)-safe materials.
The environmental conditions these devices are designed to tolerate are:
• MSL 1* characterization 85 °C / 85 % RH / 168 hours
• Highly-accelerated stress test (HAST) 130°C / 85 % RH / 96 hours
• Temperature cycle -65 °C / 150 °C / 1,000 cycles
• Temperature/Humidity 85 °C / 85 % RH / 1,000 hours
• High-temperature storage 150 °C / 1,000 hours
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7.1.2 BTC Temperature Sensitivity Temperature-sensitive component (TSC) scrubs should
be conducted on an assembly BOM. If not
managed properly, TSCs can pose significant
reliability risks to hardware. If there is a TSCrelated problem, it usually shows up as a latent
field failure. To ensure product reliability
requirements are met, the following actions are
recommended:
1) Identify TSC content on each design (TSC
BOM scrubs are critical.).
3
1
2
A
B
2) Ensure a variety of TSCs are monitored during thermal profiling and processing
definition/qualification.
3) Ensure TSC exposures remain within specified limitations as defined by J-STD-075
and J-STD-020.
BTCs are generally not considered TSCs;
however, with the growing number of BTC
packages on the market, TSC assessment is
recommended. Figure 7-2 shows how process
windows have increased in temperature with
the migration to Pb-free assembly processes,
while component temperature limits offered by
suppliers have not increased. This means that
many component families, including BTCs, are
being processed in much hotter environments.
This results in the need to confirm BTC part
temperature and time at temperature sensitivities by reviewing component supplier requirements. For more information on TSCs, refer to
J-STD-075 and J-STD-020.
7.1.3 BTC Moisture Sensitivity Considerations BTCs shipped in moisture-barrier bags
C
1
2
3
D
E
F
IPC-7093a-7-2
Figure 7-2 Elevated Process Windows Increasing Temperature-Sensitive
Component (TSC) Risks
A – Temperature (°C)
B – 217 °C SnAgCu melt temperature
C – 183 °C SnPb melt temperature
D – PTH and rework
E – SMT rework
F – SMT reflow
1 – SnPb
2 – Mixed
3 – SnAgCu
Notes:
1. While process windows have increased, time and temperature ratings for TSCs have
remained the same.
2. New SnAgCu Pb-free process windows now operate at component survival limits (primary
attach and rework operations).
3. Exposure during processing can lead to latent defects, which final functional testing will not
detect.
4. Significant time and temperature limitations for nonsemiconductor components between
230 °C and 250 °C
5. Nonsemiconductor TSC limits
• Crystals / Oscillators
• Molded polymer Al capacitors
• Film capacitors / Plastic inductors
• Polymer tantalum capacitors / Fuses
• SMT electrolytic capacitors
require special handling to ensure proper surface mount conditions are met. The moisturebarrier bag will be labeled with the proper
instructions concerning the correct handling of
the BTCs. BTCs exposed to room temperature
and humidity conditions beyond the cumulative
time specified on the label should be baked
prior to surface mount reflow. BTC size, thickness and MSL rating determine bake times and conditions. Industry standards organizations (e.g., JEDEC) publish tables
with bake times and temperatures. J-STD-033 should be followed to prevent damaging the BTC devices.
7.1.4 BTC Termination Finishes and Solderability Matte Sn is widely used as a Pb-free finish for BTC component
terminations. For Sn-based finishes on Cu-based lead frames, the risk of Sn whiskers may be introduced without implementation of proper risk mitigation protocols. Risk mitigation methodologies such as soldering process ‘‘poisoning’’ and/or conformal coating have been shown to mitigate Sn whisker risks. Such measures can include the use of galvanic Ni underlayers
or suitable heat treatments (i.e., post-bake treatments). NiPd-based preplated lead frame finishes have been introduced as one
Pb-free alternative with no associated Sn whisker risk. NiPdAu alloys are Pb-free finishes which can exhibit total cost of
ownership advantages over post-mold-plated finishes such as matte Sn and SnPb. NiPd-based preplated lead frame finish
implies that the solderable finish on the lead is applied at the lead frame maker, prior to IC assembly, which eliminates the
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need for post-mold plating. Wettability of common surface finishes is usually not an issue for Pb-free soldering using SAC
solder pastes, but special attention may be required when low-temperature solder alloys are employed.
There is usually no surface finish on the flank of a BTC I/O termination, because the singulation operation (sawing or
punching) results in a bare lead frame surface in the plane of singulation. See Section 4 for design options enabling a portion of the terminal edge surface to remain plated after singulation. As an alternative to these options, a secondary plating
process (typically electroless) is sometimes applied after singulation to obtain a solderable surface finish on the pin flank.
This approach, however, has the disadvantage that the solderability of the pin flank and the bottom side are not identical,
because the surface finishes solderabilities pertain to different plating processes. Therefore, the presence of an outer meniscus does not allow the conclusion that the bottom side of the termination has also been wetted. Therefore, the usefulness of
such pin modification in AOI is limited (see 7.11.2).
Solderability testing and dewetting and resistance to dissolution of metallization testing should preferably be performed
using reflow simulations following J-STD-002 or
IEC 60068-2-58, and not by dip-and-look testing. This is
because the sensitivity of the latter method to surface defects
affecting finish performance is limited. Figure 7-3 shows
examples of surface defects caused by probe marks from electrical testing, which were revealed by solderability testing.
BTCs may be incorporated into rigid or flexible printed board designs. See Section 6
for details on printed board design for BTCs. This section
focuses on assembly elements relating to BTC usage.
7.2 Printed Board Considerations
A
Figure 7-3
IPC-7093a-7-3
Surface Defects Caused by Probe Marks
A - Probe marks
7.2.1 Printed Board Design Impact on Solder Joint Fillet Formation As discussed in Section 6, proper land pattern
design is critical for maintaining high yields and good reliability of BTC solder joints. Figure 7-4 shows examples of good
and bad BTC land patterns.
The solder pad on the device should be aligned with the lands on the printed board so a complete solder connection is made
between the device pad and the printed board land. Also, it is recommended for pull-back packages that the printed board
land extends beyond the outer edge of the device package to allow visual access for inspection of solder joint flow.
A
A
B
C
B
C
F
G
H
J
D
D
E
E
C
C
F
G
K
L
IPC-7093a-7-4
Figure 7-4
A–
B–
C–
D–
E–
F–
Resultant Good (Left) vs. Bad (Right) Solder Joint Formation for Pull-Back and No Pull-Back BTC Configurations
Pull-back pad
Pull-back package
DAP
No pull-back pad
No pull-back package
Pull-back printed board design
G – No pull-back printed board design
H – Good solder joint, 1:1 ratio of printed board pad to
package pad
J – Weak solder joint/fillet, lower solder height
K – Good solder joint/fillet
L – Weak solder joint, solder overhang on both sides
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Warpage is another consideration as BTCs become larger. Flatness is important for
proper seating of the package and for solder joint reliability. The higher-temperature reflow profile required for Pb-free
soldering may cause excessive printed board warpage and should be evaluated.
7.2.2 Assembly-Induced Warpage
For lead frame packages (e.g., QFNs), warpage should be no more than 0.10 mm. For substrate packages (e.g., LGAs),
warpage should be no more than 0.15 mm.
7.3 Assembly Materials
There are many assembly materials to consider and qualify to ensure a robust BTC assembly
process including:
• Solder alloys
• Flux vehicles within solder paste formulations
• Liquid/Tack fluxes
• Wave bar alloy
• Wave flux
• Cleaning chemistries
This section provides key points for assembly materials as they relate to BTCs.
7.3.1 Solder Alloy Mounting Methods Soldering is the primary method to form BTC interconnects. Final solder joint volume after reflow comes from the amount of solder paste deposited onto SMT I/O and thermal pads. BTCs do not contribute any solder to the final joint. Pb-free alloys such as SnAgCu formulations are widely used to adhere to EU RoHS
requirements. BTCs can also be assembled using SnPb solders for products that are exempt from EU RoHS legislation.
7.3.2 Solder Paste BTCs are most often attached to a
printed board using a solder paste printing process. Stencil
apertures are designed based on the printed board Cu footprint
and are used to print a controlled amount of solder paste to the
target location (either I/O pads or thermal pad region). After
stencil printing, the BTC component is placed on top of the
wet paste using high-accuracy component placement equipment. The component sitting in the wet paste then enters the
reflow zone, where the solder joint is formed upon subsequent
cooling, exiting the reflow process step. See 6.13 for additional guidance on stencil design considerations.
Figure 7-5
BTC with Outrigger Pads
7.3.3 Solder Preforms Solder preforms can be used in
cases in which additional solder volume may be required. For
example, some BTCs contain outrigger pads, which are dual
pads on the left and right sides of a device, as shown
in Figure 7-5. Preforms can be incorporated using pick-andplace equipment, with preforms in tape-and-reel format
(see Figure 7-6).
Solder preforms come in standard shapes, such as squares and Figure 7-6 Solder Preform in Tape-and-Reel Format
rectangles. Typical sizes range from 0.25 mm to 51 mm.
Smaller and larger sizes, as well as custom shapes, are also
available. Dimensions can be held to tight tolerances to ensure volume accuracy. The location of the solder joint and the
volume of solder needed will determine the size and shape of the preform. Once the flat dimensions (diameter, length and
width) have been determined, the thickness can be adjusted to achieve the desired volume of solder.
Alloy selection for BTC devices should follow recommendations found in J-STD-006. In general, there
are no special requirements for soldering BTCs, beyond regular assembly processing considerations for other components
found on an assembly. The most commonly used alloys are SAC-based Pb-free solders and eutectic SnPb for RoHS-exempt
products. Alternatively, low-melt Pb-free alloys can also be used depending upon the application.
7.3.4 Solder Alloy
Type 3 or Type 4, low residue, no-clean solder paste (SnAg3Cu0.5 or SnPb37) is commonly used in mounting BTC packages; however, water-soluble flux materials are also widely used. Solder paste composition is often a compromise given the
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variety of components which should be placed on a printed board. Special SMT-specific solder pastes minimize voiding in
the solder joint. See J-STD-005 for solder particle size classifications.
7.3.5 Flux Chemistry Considerations Flux selection for BTC devices should follow recommendations in J-STD-004.
Important decisions to consider during the selection process include:
• No-clean vs. water-soluble flux formulation (dependent on product application and BOM)
• Flux composition (rosin, resin, organic or inorganic)
• Halide content and activity level
With BTC collapse stand-off heights ranging from 51 µm to 76 µm, it is important that flux is properly activated/consumed
so it does not induce potential dendritic-growth-related failures over time. To help safeguard against this, ROL0-based fluxes
with low activity (< 0.05 wt. % halide) are recommended for use with BTC assembly. Other formulations can be used, but
they should be adequately examined and qualified to ensure dendritic growth does not occur under electrical bias, temperature and humidity. Ask the solder paste supplier for recommendations on proper activation times/temperatures for specific
solder pastes. To assess flux performance, surface insulation resistance (SIR) monitoring is recommended with BTC components assembled with comb patterns under assembled parts.
The use of underfills and additional adhesives should be
thoroughly investigated before use with BTC assembly. Using solder mask in the printed board design may make the standoff distance between the printed board and BTC too small for most underfill materials to spread effectively under the part.
Test vehicle evaluation can determine if these materials are appropriate or required for the application and mission life of
the electronics assembly.
7.3.6 Edge/Corner Bond Materials, Underfills and Adhesives
If mechanical fragility issues are a concern, edge/corner-bond materials (without silica fillers) may be used to improve
mechanical reliability levels of the BTC soldered interconnect structure. Edge/corner-bond materials can extend the life during vibration and drop-shock exposures. Use of these materials adds another step to the manufacturing process and should
be tested/qualified prior to implementation.
7.4 BTC Cleaning Process BTCs are known to trap flux
residues under the component. The thermal lug during reflow
pulls the component down onto the pad area, which reduces
the stand-off gap. Common stand-off gaps for these component types range from 25 µm to 50 µm. As the component
pulls down during reflow, large voids can form within the
thermal lug. Flux residues trapped inside the components are
commonly active since the weak organic activators within the
no-clean flux do not adequately outgas. Soak reflow profiles
can be used to improve flux outgassing (see Figure 7-7).
Electrochemical reliability requires a design for reliability
(DfR) approach that factors in the component design, solder
paste, reflow conditions, cleaning, end-use environment and
complex interaction between these factors. Electrical and
chemical test methods on leadless and bottom-terminated test
boards enable the assembler to evaluate the activity levels
of the residue located at the pads and bottom termination
of the component. Proper testing should be used to determine
the cleanliness levels needed to achieve electrochemical
reliability.
When stand-off gaps are low (typically < 75 µm), a significant
amount of flux residue will accumulate under the bottom termination. This can trap a significant amount of flux residue
under the component termination (see Figure 7-8).
A
Figure 7-7
Flux Residue Entrapment Area of Concern
A – Area of concern: Active flux residues leading to dendritic growth
from grounded thermal pad to I/O locations (possible shorting)
Figure 7-8
Flux Residue Deposits Under a Dual-Row QFN
See 6.12 for more information.
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Paste print quality is a critical factor in producing high-yield, reliable assemblies that
use BTCs. Solder paste can be applied to the lands using several methods including screen or stencil printing, dispensing
or jetting.
7.5 Solder Printing and Deposition
Solder paste consists of a homogeneous mixture of metal powder particles and flux. The metal content (typically 90 % by
weight) in the solder paste determines the amount of solid alloy in the solder joint. Metal powder particles are generally
spherical in shape. A uniform powder shape aids the printing or dispensing process and decreases the surface area, which
minimizes oxidation.
Flux, solvent and jelling agents comprise the remainder of the solder paste volume. The activators in the flux remove oxides
from the solder particles, land patterns and BTC termination surfaces to promote good solderability during reflow. Solvents
have an important role in controlling the tackiness of the paste and affecting the rheological properties. Solvents with low
boiling points and/or improper reflow parameters can increase the incidence of voids in BTC solder joints.
For successful fine-pitch BTC printing, solder paste should pass through very small apertures in the stencil. The solder paste
needs to remain printable and tacky for an extended time, and it should maintain print definition prior to and during reflow.
Solder paste viscosity, particle size and stencil life are critical parameters for solder paste application. Table 7-1 provides a
comparison between mesh and particle size for paste types.
Table 7-1
Solder Past Type
Particle Size Comparisons
Mesh
Maximum Particle Size (µm)
Type 2
- 200 / + 325
80
Type 3
- 325 / + 500
50
Type 4
- 400 / + 500
40
Type 5
- 500
30
7.5.1 Solder Stencil Printing Considerations The following are key considerations to ensure an adequate BTC printing
process (see also IPC-7525 for stencil design best practices):
• Foil material – BTC stencil designs can be implemented on a variety of stencil material types including stainless steel,
laser-cut and nano/plasma-coated stencil constructions.
• Stencil aperture design – See 6.13 for BTC stencil design considerations.
• Step stencils – Localized step-up or step-down foil thicknesses should be minimized where possible. Uniform thickness
stencil is recommended for BTC printing. In cases where this is not possible, board-to-board print variation studies are
recommended to ensure consistent localized BTC printing is realized.
• Automated inspection – A solder paste inspection (SPI) process should be implemented to ensure actual solder paste volumes and heights are being achieved for all printed boards during the manufacturing process.
• Stencil thickness – BTC stencil thickness typically ranges from 76 µm to 152 µm.
• Area ratio – Ratios for I/O pads and the thermal pad should be calculated and monitored. The target range to ensure proper
release should be area ratios > 0.66 as directed with many other SMT devices.
• In-process stencil cleaning – Efforts should be made to ensure auto-wipe features (clean every 10 boards) are enabled. This
practice will help minimize stencil aperture clogging during volume manufacturing.
• Print strokes – Single or double print strokes can ensure adequate print deposits are achieved.
• Squeegee blades – Metal blades are recommended over plastic blades to print BTCs.
• Stencil health monitoring – Ongoing monitoring of stencil health should be implemented. Stencil damage in the area of
BTCs can lead to insufficient print deposits.
Forming reliable solder joints is a necessity, but the large numbers of terminal contacts on some BTCs can present a challenge in producing uniform solder print thickness, so carefully consider stencil design. The stencil thickness, as well as the
etched pattern geometry, determines the precise volume of solder paste deposited onto the device land pattern. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform reflow-solder processing. Stencils are usually
made of stainless steel or electroformed Ni. Apertures should be trapezoidal to ensure uniform release of the solder paste to
reduce smearing. Solder joint thickness for BTC attachment should typically be 50 µm to 75 µm after reflow.
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Specify 0.6-mm radius for inside corners of all apertures and reduce all 0.8-mm-pitch and finer aperture widths to 50 % of
pitch. Segment BTC thermal pad apertures to reduce printed solder volume by 50 % or less, or as specified by the manufacturer’s recommendation
Note: Segmented solder paste deposits may not be required on some components. Apertures with a dimension > 5 mm are
broken into multiple apertures.
It is recommended to use a 125-µm stencil thickness for ≤ 0.5-mm pitch and a 150-µm stencil thickness for larger pitches.
The stencil may require stepped areas to allow for small and larger pitches on the same board. Typical BTC arrays and passive components as small as 0402 and 0201 may also require a 125-µm-thick stencil.
All stencil thicknesses should be considered as recommendations for a laser-cut stencil. Thickness of the stencil is usually
100 µm to 150 µm. The actual thickness of a stencil is dependent on other surface mount devices on the printed board. A
squeegee durometer of 95 or harder or a metal squeegee should be used to distribute the paste. The blade angle, pressure
and speed needs to be fine-tuned to ensure even paste transfer. An inspection of the stenciled board is recommended before
placing parts, because proper stencil application is the most important factor with regards to reflow yields later in the process (see Figure 7-9).
125 µm
100 µm
150 µm
R0.08
R0.16
0.620
0.690
R0.06
0.565
A
B
Figure 7-9
IPC-7093a-7-9
Recommended Aperture Dimensions for Commonly Used Stencil Thicknesses
Note: Figure not to scale. Measurements on top are thicknesses.
A – Device and printed board pad size 0.635 mm2
B – Stencil aperture size
It is very important to design a stencil aperture that will provide good paste release. To ensure good paste release, a minimum aspect ratio of 1.5 is recommended for laser-cut foils. Aspect ratio is the ratio between stencil aperture width and stencil thickness. The aspect ratio relates to the manufacture of stencils and the solder paste stencil aperture and/or thickness
and may need to be modified to maintain acceptable aspect ratio.
Regardless of the stencil features, proper care should be given to the printing process at the assembler’s facility, and it is
best to be handled by qualified technical staff. The preparation, paste rheology, handling time, stand-off distance, blade
hardness/speed and reflow process details are critical in conjunction with careful stencil design to ensure maximum yield
and minimum failure rates. It is important to know which printing techniques are used at any assembly facility where the
BTC will be installed. Each of these sites should be able to provide recommendations for stencil design limitations.
Table 7-2 explains common stencil technologies and options (see also IPC-7525).
Solder paste dispensing is not as widely used as printing due to a reduction in throughput
speed; however, selective dispensing allows for more flexible paste volume deposition and placement for tighter process
7.5.2 Jetting and Dispensing
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Table 7-2
Pros and Cons of Common Stencil Technologies and Options
Stencil Manufacturing
Technology
Chemically etched
Laser-cut
Electroformed
Pros
Low cost if there are many thousands of
apertures on the stencil
Can produce rough aperture walls
Accommodates user-specified foil thickness
Typically limited to large aspect ratio and large
aperture designs
Oldest technology
Shrinking supplier base
Lowest-cost stencil for low-aperture-count
designs
Aperture cut quality depends on laser machine
and foil material properties
Cost effective for 10,000-aperture-count designs
Cost increase to manufacture as aperture count
exceeds 10,000
Most common stencil technology
Typically available in only fixed foil thicknesses
Cost effective for > 10,000-aperture-count
designs
Highest-cost stencil for medium- to
low-aperture-count designs
Smooth aperture walls
Typically requires longest lead time
Accommodates user-specified foil thickness
Supplier availability limited
3D stencil design compatible
Stencil thickness uniformity
Stencil Option
Electropolish (chemically
etched, laser-cut stencils)
Nanocoating (all stencil
technologies)
Fine-grain foil (laser-cut
stencils)
Cons
Pros
Cons
Smooths rough aperture walls
Method can produce inconsistent results
Permanent
May alter aperture shape and size
Reduces frequency of under-stencil wipe and
clean
Cannot smooth rough aperture walls
May improve solder paste volume and height
variation
Varied usage results, many proprietary materials
and application methods available
Minimal effect on aperture shape and size
Coatings may deteriorate with stencil use
Smoother aperture walls and cleaner raw-cut
finish
Difficult to know if actual cutting result reflects
optimum
control. Solder paste jetting has greatly increased solder deposition speed while still allowing for flexible volume and placement accuracy. Jetting requires specific solder paste formulations, which may have limited industry acceptance. Refinements
in equipment and dispensing methods could make this technology more viable and desirable as a way of maintaining tighter
process control.
Component solder dipping is not recommended for BTC terminal surface
preparation. Dip soldering will not maintain coplanarity and
makes the BTC unproducible during assembly. Inconsistent
solder on the thermal plane can raise the BTC and cause the
signal terminations to not make contact during reflow, which
creates solder opens. Nonuniform solder volume on signal
terminations can also create a noncontact condition resulting
in solder opens in random locations (see Figure 7-10).
7.5.3 Solder Dipping of BTC Components
A
B
Figure 7-10 Comparison of Solder-Dipped and Not Dipped
BTCs and Resultant No Solder Condition
A – Dipped
B – Not dipped
As with other component print
locations, it is important to inspect print quality of BTCs prior
to placement and reflow. Reworking defect locations early is made easier if detected prior to creating the soldered interconnect. Automated SPI equipment measures height, volume and area of paste deposits; computes stencil offsets/drifting and
can detect printing defects such as bridges, missing solder and insufficient solder. Print geometries found within BTCs generally fall within SPI equipment detection capability ranges and do not generally require changes to algorithms or programming steps. It is recommended that all BTCs on an assembly be included in SPI measurement protocols. Upper and lower
control limits of height and volume are recommended to follow ± 3 σ based on the statistical mean of I/O locations and the
thermal pad. If BTC locations fail SPI requirements, the printed board should be washed of wet solder paste, ensuring no
solder paste is left behind in thermal vias, prior to printed board reprinting/processing. See also 7.11.1.
7.6 Solder Paste Inspection
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Pick-and-place accuracy governs package placement and rotational alignment. This is equipment and process dependent. Slightly misaligned parts (< 25 % off the land center) will automatically self-align during
reflow (see Figure 7-11). Grossly misaligned packages (> 50 % off land and pad centers) should be removed prior to reflow,
because they may develop electrical shorts as a result of solder bridges during reflow.
7.7 Component Placement
A
B
< 25%
C
> 25%
IPC-7093a-7-11
Figure 7-11
Assessing Maximum Off-Land Acceptance (Before Reflow)
A – Target
B – Acceptable
C – Not acceptable
Placement accuracy is a very critical part of the BTC process. It is strongly recommended to not move a BTC after machine
placement to correct placement problems. This may cause solder bridging in adjacent solder joints because the connections
cannot be seen. The placement machine’s accuracy is largely dependent on the vision system and the ability of the nozzle
to hold the component. Matching the vision system to the application is also important. The vision system determines the
x, y and theta offset of each component prior to placement. In addition to determining the component offset, the vision system can inspect the component for dimensional integrity.
There are two popular methods for package alignment using machine vision:
• Package silhouette – vision system locates the package outline
• Terminal recognition – vision system locates the terminals or leads of the package
Some vision systems can directly locate the metallization pattern on the pad. Both methods are acceptable for BTC placement. The terminal recognition type alignment tends to be more accurate, but it is slower since more complex vision processing is required of the pick-and-place machine. The package silhouette method allows the pick-and-place system to run
faster, but it is generally less accurate. Both methods are acceptable and have been successfully demonstrated by pick-andplace equipment vendors and printed board assemblers. Depending on the type of pick-and-place system, a change in package carrier format may be required. Local fiducials may also help the vision systems recognize the exact location of the land
pattern for the BTC, similar to what is used for fine-pitch peripheral-leaded parts.
Placement machine nozzle designs vary. It is important to use a nozzle that will have sufficient surface area to hold the part
without any shifting during placement. The nozzle should gasket against the part, not allowing vacuum leakage. Tactile
sensing, which helps control the z-axis stroke of the spindle, is desirable because it prevents a component from being
crushed between the vacuum nozzle and the substrate.
Without leads or balls to act as a hard stop or stand-off, extra care should be taken to limit the z-axis pressure of the part
into the solder paste, which can result in solder shorts.
7.8 Solder Joint Reflow Reflow soldering is a complex process with many variables. All mass-reflow systems incorporate
convective, conductive and radiant means of heat transfer; to which degree depends on the design of the reflow system. As
with all SMT components, it is important that profiles be monitored on all new printed board designs. In addition, if there
are multiple package types on the printed board, the thermal profile should be measured at multiple locations. Component
temperatures may vary because of surrounding components, location of the device on the board and package densities. BTCs
generally do not define the thermal profile for a product because they are on the same printed boards as many other types
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of components. To maximize the self-alignment effect of a BTC (see Figure 7-12), it is recommended that the maximum
reflow temperature specified for the solder paste not be exceeded.
Figure 7-12
Metal-Defined Land Solder Joint
The actual temperature at the solder joint is often different than the temperature settings in the reflow system. This is due
to the location of the system thermocouple placement. The reflow system needs to be profiled using thermocouples at various
locations on the printed board. Thermocouples should be placed on one of the largest components and one of the smallest
components. Peak temperature differential between the smallest and largest package should be ≤ 10 °C for average-size
printed boards. BTCs are typically moisture sensitive and fall into level classifications defined by JEDEC. Specific levels
are stated on moisture-sensitive labels shipped with BTC devices. Commercial BTC devices may be compatible with SnPb
and/or Pb-free solder processing. The BTC supplier is responsible for defining the maximum reflow profile limit
(e.g., 215 °C to 245 °C peak body temperature).
7.8.1 Reflow Atmosphere The reflow furnace atmosphere will affect solder wetting. Reflowing in a N2 environment will
result in improved wetting of the solder joint. This will sometimes allow compensation for marginally wettable surfaces on
printed boards as well as oxidized solder balls. To obtain the maximum benefit of the solder paste in a N2 environment, it
is important to monitor the oxygen content and control it within the limits established for the process.
Solderability of Pb-free solder paste is not as good as that of SnPb. If the correct paste is not used, it is also possible to use
up solder paste activators, which clean oxides off the pastes prior to reflow. This can result in a nonuniform-shaped solder
joint and possible nonwetting of the land.
Solder profile, also known as thermal profile, significantly impacts product yield.
Conveyor speed and panel temperature are two variables in solder profile development. The solder profile is not only product specific; it is also flux dependent. Different pastes require different profiles for optimum performance, so it is important
to consult the paste manufacturer before developing a solder profile.
7.8.2 Time and Temperature Profiles
With SnPb, there is general industry consensus about the composition of solder to be used: eutectic SnPb37 with a melting
point of 183 °C. With this composition, there is a big difference between the melting point (183 °C) and peak temperature
(220 °C). Even though it has been the recommended practice to maintain the temperature between 210 °C and 220 °C across
the entire printed board assembly, it is possible to maintain a temperature between 190 °C and 225 °C (a variation of almost
35 °C) and still achieve good reflow soldering results.
In Pb-free assembly, the commonly used SAC solders contain 3 % to 4 % Ag, 0.5 % to 0.7 % Cu and the remainder Sn.
These alloys have a melting point ~220 °C. A few components (e.g., some Al electrolytic capacitors) have restrictions on
maximum temperature and duration to which they can be subjected above 230 °C. Additional constraints are dictated by
low-cost laminates, plastic connectors and moisture-sensitive components. To accommodate such constraints, the peak temperature in Pb-free assemblies should be maintained between 230 °C and 245 °C, a variation of only 15 °C and a tight process window. This is a nearly 60 % drop from 35 °C variation within SnPb printed board assemblies.
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7.8.3 Unique Profile for Each Printed Board Assembly Each unique printed board assembly needs to be profiled to prove
all locations on the assembly meet the various requirements for creating acceptable solder joints. A single reflow program
will produce very different profiles for different, unique assemblies. There is misunderstanding that one oven profile will
work for all assemblies, so there is no need to develop unique profiles for each assembly. This is not true, because each
printed board assembly has a unique thermal mass or different loading patterns (distance between assemblies as they are
loaded into the oven). A double-sided printed board assembly, depending on component placement and distribution of Cu
planes, will require a different profile for each side. Profiles may look the same for many assemblies but will generally
require different machine programs to create these similar profiles. It is common to have a small number of standard machine
programs, but it should be shown that a specific program produces an acceptable profile. Thermal profiling for BTCs should
be conducted in accordance with IPC-7530.
7.8.4 Effects of Materials on Flux Activation, Component Damage and Solderability A common mistake is to use a time
and temperature profile that consumes the flux before the solder melts. Ideally, the flux will be consumed just as the solder
begins to melt. Activation time should range from 90 to 120 seconds. Flux usually becomes active at ~130 °C for SnPb solder pastes. Typically, solder paste activation for Pb-free solder will be higher (~150 °C); however, it is recommended to work
with the solder paste supplier for recommendations on a specific solder paste.
Incorrect application of heat can damage components. All components have a heat exposure limit. Most SnPb SMT components should tolerate a peak temperature of 220 °C for up to 60 seconds. Pb-free BGAs will be rated to a higher temperature (~240 °C to 260 °C). Thermal shock, caused by the rapid application of heat, can crack certain components. However,
since peak temperature of reflow ovens varies, the intent is to heat the solder in a controlled, established profile to a solder
joint temperature of 210 °C to 220 °C for SnPb products (see Figure 7-13) and 235 °C to 245 °C for Pb-free products
(see Figure 7-14). Warpage is also a concern (see 7.2.2).
250
225
A
200
B
183
150
C
100
50
RT
0
0
60
120
180
D
Figure 7-13
A–
B–
C–
D–
240
300
360
IPC-7093a-7-13
Profile for SnPb Solder Reflow
Straight ramp
Low soak
°C
Seconds
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250
240
217
200
150
B
100
50
RT
0
0
60
120
180
240
300
360
A
IPC-7093a-7-14
Figure 7-14
Profile for SAC Alloy Solder Reflow
A – Seconds
B – °C
With a limited number of
thermocouple channels available with data recorders, it is
important to include at least one BTC reference designator
measurement (at a minimum) when defining the thermocouple
mapping for a printed board assembly. It also is important to
include at least one BTC device to verify that the component
falls within required process window limits. Any number of
thermocouples can be used, as determined by the user
(see Figure 7-15 for an example). The approach helps to
minimize the number of thermocouples needed to evaluate a
BTC location, and it ensures all solderable interconnects meet
minimum time and temperature requirements. This can be
applied to primary attach and rework thermal profile cards.
7.9 Thermal Profiling for BTCs
The red thermocouple location indicated in Figure 7-15
should be back-drilled through the printed board and should
come into contact with the Cu thermal pad and solder joint
stand-off gap. Since the thermal pad is heat-sinked to internal
ground layers with thermal vias (by design), recorded times
and temperatures will be the lowest obtained for the component location. Ensuring minimum requirements are met at this
thermal pad location will ensure I/O solder joints will meet
process window requirements.
Figure 7-15 BTC Thermal Pad Thermocouple Location for
Profile Verification (Red Marker)
See IPC-7530 for additional guidance on thermal profiling best practices.
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7.10 Process Control and Monitoring Points for BTCs As discussed in this standard, there are several key areas in which
design point, process control and monitoring of BTCs is important to ensure high-quality and high-reliability implementation of BTCs on a printed board assembly. A listing is provided in Table 7-3.
Table 7-3
Design and Process Control Points for BTCs
Area
Description
IPC-7093 Reference
Physical design
Thermal pad layout selection. Select one option depending on application
needs. This controls part-to-part voiding variation, solder wicking down vias,
voiding levels and percent coverage variation.
Section 6
Surface finish
Ensure planar solderable surfaces, free from contamination and handling
damage.
Section 5
Assembly materials
Ensure all materials are properly characterized and qualified.
Section 7
Thermal profiles
Thermal profile development and control during production. Ensure BTCs
are included in thermocouple mapping and are monitored during profile
development.
Section 7
Component MSL
Ensure MSL control for BTC packaging during assembly. Monitor open
package times and bake. Reset as necessary.
Section 4
Stencil design
Ensure proper BTC stencil aperture design; depending on size of thermal pad.
Section 6
In-Process inspections
Checkpoints include SPI, AOI and AXI.
Section 7
7.11 Production-Level Inspection BTC inspection is typically accomplished using a combination of tests during manufacturing, including those found in Table 7-4. Different test procedures and equipment within the manufacturing process flow
are required to monitor and control different defect types. When combined, a robust BTC inspection can be implemented to
ensure highest possible quality and yield levels are attained and to minimize BTC defect escapes. A focus on minimizing
card-to-card variation and feedback process control is recommended for each inspection stage.
Table 7-4
Production-Level Inspection Stages Ensuring High-Quality BTC Manufacturing
Production-Level Inspection Step
Defect Type(s) Being Inspected, Monitored and Controlled
Automated SPI
Focus: Solder paste print deposit quality
Printing = height, volume, area, registration, shift/misalignment, etc.
AOI
Focus: Soldering defects and component placement issues
Soldering = insufficient, bridging, missing, toe fillet formation*
Components = misaligned, wrong part, missing, polarity, lifted leads, etc.
AXI
Focus: Final solder joint formation and component placement issues
Soldering = voiding levels, insufficient, bridging, missing, etc.
Components = misaligned, missing, lifted leads, bent pins, etc.
Manual visual inspections
Focus: IPC-A-610 inspection to ensure adequate workmanship
Inspection = excessive flux application, debris, fibers, craftmanship, etc.
*See 7.11.2 for more information on detection of BTC toe fillets during AOI.
SPI
should be included as a first step to ensure high-quality
assembled BTC devices. Solder paste volume and height measurements should be taken for I/O perimeter lead locations as
well as thermal pad deposits, as illustrated in Figure 7-16,
which shows solder paste deposit variation. It is recommended
that upper and lower control limits be set using 3-sigma or
– ) for each pad type. BTC pad
better actual statistical means (x
sizes and pitches do not generally influence special requirements for SPI monitoring; however, it is recommended that all
BTC locations on a printed board assembly be included within
the SPI monitoring algorithm. Defects such as excessive solder, insufficient solder, bridging, slumping and missing deposits (among others) can be detected during this inspection step.
If defects are found at this stage, the board should be removed
7.11.1 Automated Solder Paste Inspection (SPI)
Figure 7-16 Example Solder Paste Inspection Image of a
Quad Flat No-Lead (QFN)
Figure Source: Ersa
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from the line, properly washed and dried and then reprinted. It should then continue on to subsequent component placement
and reflow operations. See also 7.6.
7.11.2 Automated Optical Inspection (AOI) In principle,
AOI can be used to detect failures such as bridging, no-solder
joints and open solder joints (i.e., nonwetting of component
termination) for single-row BTC packages with no pull-back
pins, because the terminals are visible for this package configuration. However, because the post-package assembly singulation process typically leaves a bare Cu lead frame at the
edge, which is not protected against oxidation (so it will not
easily solder-wet), a solder fillet (toe fillet) does not generally
develop. If no toe fillet can be discerned, it is impossible to
use AOI to decide if a pin has been wetted by solder, because
wetting may have occurred only for the bottom side of the
termination.
A
A toe fillet can typically be lacking for even a few percent of
the pins, whereas most of these pins without toe fillet would
still exhibit a robust solder connection at the bottom side of
the pin (not visible with AOI). This should be classified as a
good solder-joint during inspection, because the presence of a
toe fillet is not a requirement (see J-STD-001).
C
D
Scrapping or reworking all components where outer fillets are
missing would result in unacceptably high costs. This lack of
capability for AOI has therefore been a major detractor for
BTC packages.
With the advent of wettable flank single-row MLF packages
(see 4.5.1), characterized by the presence of at least a partially
continuous solderable surface, robust AOI has become a possibility that is likely to result in a more widespread package
use for high-reliability, Class 3 applications. To ensure a
robust AOI inspection for wetting failures under series production conditions, certain minimum height and width of the
wettable portion of the terminal-edge surface are required.
See Figure 7-17 for an AOI-inspection example of wetted and
nonwetted terminations on a MLF package with dimple and
punch type wettable flanks and corresponding AOI images
used in automated solder joint inspection (perpendicular, with
respect to the panel surface, camera view).
B
IPC-7093a-7-17
Figure 7-17 Microscopy Images of Wetted (Top, Left) and
Nonwetted (Top, Right) Terminations of a MLF Package
A – Microscopy
B – AOI
C – Good
D – Wetting failure
A robust AOI inspection with false-call and slip rates satisfying typical Class 3 requirements in mass production, in which
a full inspection of all solder joints is usually desired, becomes possible if wettable width exceeds 50 % of the full termination width and wettable height exceeds 100 µm (including tolerances). Larger wettable heights and widths simplify AOI
inspection and ensure a more robust distinction between good and bad solder joints (see Figure 7-18), but because solder
volume needs to be properly adjusted during land design, tight tolerances on the relevant geometrical parameters, as well as
the wetting height and the depth of the step-cut or the dimple, also are essential. Components satisfying these requirements
for continuous solderable surfaces of wettable flanks enable users in SMT manufacturing to fully exploit the intended benefit of robust AOI capability.
Figure 7-18 illustrates the impact of wetting height (as shown in exemplary, microscopic cross-section top left) on an AOI
image (representing a perpendicular camera view with respect to the panel surface) for a pin with a wetting failure (top right)
and wetted pins with different wetting heights (bottom).
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A
B
D
E
F
H
G
J
C
K
L
M
IPC-7093a-7-18
Figure 7-18
A–
B–
C–
D–
Impact of Wetting Height
Illustration of wetting
Wetting failure
Wetted pin with different wetting heights
Wetting height
E – Land
F – Solder
G – Pin
H – AOI
J –
K–
L–
M–
The AOI images have been calculated by using a ray tracing
method for solder-joint geometries with different wetting
heights, which have been obtained by simulating solder
reflow, adopting the principle of surface energy minimization
to determine the solder surface geometry, as shown in the perspective views for the termination of a MLF component
(solder geometry in Figure 7-19). A clear distinction of terminations with a wetting failure from wetted terminations is
possible only if the wetting height exceeds 100 µm.
Figure 7-17 shows an alternate illustration of this capability.
Solder geometry
No robust AOI process
Critical limit of wetting height
Robust AOI process possible
A
B
E
G
C
F
H
E
J
D
F
K
L
Figure 7-19 Good vs. Bad Wetted Pin (Side-Flank) Detection Using AOI
A – AOI evaluation
B – AOI result
C – Wetted pin (good)
D – Nonwetted pin (bad)
E – Ideal
F–
G–
H–
J –
K–
Increased solder volume
Good pin (correct inspection)
Bad pin (false call)
Bad pin (correct inspection)
Good pin (escape)
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Examples of wettable side fillets are shown in Figure 7-20 and
Figure 7-21. JEDEC MO-220 defines the basic characteristics
of QFN components, which generally should also apply to all
BTCs. In addition, the following are also required for specification purposes related to BTC flank wettability:
A
E
B
• Each I/O lead should have a visible flank at the side of the
component (no pull-back I/O leads).
C
• Each flank should be wettable.
• Mold compound is not allowed on any part of the flank of
the IO leads.
• Double or multiple rows with similarly blinded I/O leads are
not inspectable using the method described.
• Flanks need to meet the same solderability requirement as
the rest of the device.
Inspection of a
BTC on a printed board can be accomplished by using transmission type X-ray equipment. In most cases, 100 % inspection is not performed. Typically, X-ray inspection is used to
establish process parameters and then to monitor the production equipment and process. There are many different types of
X-ray inspection equipment available; functionality varies.
X-ray inspection system features range from manual inspection to AXI.
7.11.3 Automated X-Ray Inspection (AXI)
X-ray inspection is generally used when there is a high proportion of hidden solder joints that are not visually accessible
and when there are a significant number of untestable solder
joints. Examples of untestable solder joints are redundant connections and back-to-back BTCs where the fanout vias are
inaccessible and space does not allow for additional test
points. X-ray methods can complement the test process and
provide faster feedback to the manufacturing line; however,
solder bonding is not necessarily observable through X-ray, so
other testing may be necessary to prove metallurgical
bonding.
D
Figure 7-20
Flanks
Quad Flat No-Lead (QFN) with Wettable
A – QFN
B – QFN contact
C – Solder joint
D – Printed board
E – QFN with wettable flank
expected to have side fillets
E
B
D
A
C
Figure 7-21 Cross-Section of Quad Flat No-Lead (QFN)
with Wettable Flanks
A – Toe fillet length
B – Toe fillet height
C – Stand-off height
D – Heel fillet length
E – Termination height
Depending on the capability of the X-ray system, X-ray imaging can detect defects such as bridging, insufficient solder and
excessive solder volume. Inspection features (e.g., based on the capillary effect) can be devised for AXI, which enables a
robust inspection of proper wetting of the I/O terminations. However, to achieve such a robust inspection for wetting, the
component should have a suitable geometry (e.g., sufficient pin length, no pull-back leads, etc.). If the component geometry
is not appropriate, X-ray inspection may not generally be a reliable inspection technique to confirm good solder joints. Other
defect types (e.g., missing solder, misregistration, package popcorning) can also be identified. In addition to defect detection, X-ray can be used to provide trend analysis for solder volume, solder joint shape and solder joint voiding levels.
Real-time X-ray inspection systems utilize an X-ray source and a detector system which converts the invisible X-ray image
into a video display signal. These systems provide immediate imaging results of samples. The images produced from these
systems should not be distorted or include false artifacts induced by the X-ray system itself. Figure 7-22 illustrates a comparable level of image quality that should be expected from a manual X-ray inspection system. Real-time systems are available in a broad range of sizes, from small desktop systems to large console floor models. They are also available with a
broad range of X-ray tube voltages and tube currents or powers.
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IPC-7093a-7-22
Figure 7-22
X-Ray Images Using Various Techniques to Detect Missing Solder
There is not a specific X-ray tube voltage or current/power
needed to inspect BTCs. The settings required will, in part,
depend on the sensitivity of the X-ray system, the structure
and characteristics of the BTC under inspection and the thickness and features of the board upon which it sits. For example,
BTCs with Cu heat sinks will typically require higher tube
voltage and tube current/power settings. Conversely, BTCs
with Al heat sinks will typically require less tube voltage and
tube current/power settings since Al has a lower atomic number than Cu and is more transparent to X-rays.
A
B
From a production quality standpoint, it is important to establish an in-line AXI approach for each printed board assembly.
Considerations for defining an adequate X-ray inspection
approach for a single printed board assembly include:
• Identification of all BTC part numbers and thermal pad
shapes in the design
• Number of BTC locations (reference designators) to inspect
• Ensuring thermal pad solder application matches thermal
pad Cu features 1:1
• Defining maximum allowable percentage voiding levels and
calculation of actual voiding levels (I/O and thermal pad)
Figure 7-23 shows an example of how a resulting X-ray
inspection image can be compared to the original BTC
component Cu pad layout (orange pads) and solder paste
application (grey deposits). Algorithms to measure percentage
voiding levels should be applied to ensure thermal pad voiding levels remain below defined upper control limits.
7.11.4 Manual Visual Inspection Final workmanship and
craftsmanship of the printed board assembly with BTCs
should be conducted per IPC-A-610 as part of standard final
visual inspection operations. Focus items to include in BTC
inspection include identification of excessive flux residues and
I/O solder mask damage resulting from touch-up or rework
operations.
Figure 7-23 Example BTC X-Ray Images Using Automated
X-Ray Inspection (AXI) After Assembly
A – BTC layout design
B – Resulting X-ray image with same BTC
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7.12 Rework and Repair This section discusses key considerations for reworking BTC devices. See IPC-7711/21 for
details on rework procedures pertaining to BTCs.
7.12.1 Hot-Air Rework While there are several different methods to rework BTC devices (per IPC-7711/7721), the most
commonly used and preferred in volume manufacturing is to use an automated hot-air rework process and tooling; conducting the rework operation on the printed board assembly. The system should have a split-light system, an XY table for alignment and a hot-air reflow system with top and bottom heater for component removal.
The general process is as follows:
1. Printed board bake – Ensure the printed board assembly is sufficiently dry by performing prebaking at 125 °C for
24 hours to drive off residual moisture that could cause other component failures during the rework reflow process. Proper
handling of the printed board assembly during the bake cycle should also be considered.
2. BTC removal – Identify and remove the defective BTC device from the printed board assembly using a hot-gas nozzle
with vacuum pickup. Be sure to select an appropriate nozzle size. The reflow profile for removing the component should
be the same (or similar) as that used for its attachment. Due to the potential for internal damage during repeated thermal
exposure, removed components should not be reused.
3. Printed board site redress – Using solder braid or another approved method, clean, planarize and prepare the site for new
part attachment. Cleaning the site is done in two steps:
a. Desoldering, which is achieved using a desoldering braid in conjunction with a blade-type soldering iron.
b. Wiping the site clean using a lint-free cloth and solvent.
4. Apply new solder paste – Apply new solder paste volume to the BTC site on the printed board assembly using manual
mini-stencil process (see 6.13 for stencil design details). Manually place a mini-stencil with the same stencil thickness,
aperture opening and pattern as the primary attach stencil onto the component site. Using a mini-metal-squeegee blade,
deposit solder paste onto the rework location. Inspect the printed pad to ensure uniform and sufficient solder paste has
been applied before component placement. The correct amount of paste is critical for successful rework of the BTC.
5.
6.
7.
8.
Note: Other methods of new solder paste application may also be used including dispensing, jetting or other qualified
methods.
Align and place component – Place a new BTC onto the printed board assembly with the component coming into contact (using known/controlled placement force) with wet solder paste that was applied in step 4.
Implement rework thermal profile – Apply hot-gas rework thermal profile to the rework location, forming the new BTC
interconnect and resulting solder joints (I/O and thermal pad). Given the small size of the components, the vacuum pressure should be kept below 0.5 kg/cm2. This will prevent the component from being lifted out before all the joints have
been reflowed and will avoid pad lift.
Monitor and control TSC – Because BTCs are small in size and thermal mass and are often found in areas of high component placement density on a printed board assembly, it is important to identify, monitor and control any nearby TSCs.
See J-STD-075 for more information on TSCs.
Conduct final inspection of reworked location – Once the BTC rework location has sufficiently cooled to ambient temperature, inspect the rework site to ensure it is free of rework soldering
defects such as solder balling, excessive flux application, component skew
and proper orientation, etc.
7.12.2 Alternative Methods There are two alternative methods that may
be used to aid in the rework of BTCs.
The first alternative method consists of bumping of solder paste onto the
device. In this application, solder paste is applied to the BTC component
pads and then placed onto the printed board. Due to smaller geometries,
dense component population of the printed board and accurate and uniform
screen printing of solder paste, using a print and release stencil design can
be difficult and requires a high degree of operator dexterity and skill. In these
cases, solder paste can be applied to the underside of the BTC component
before placement. Metal stencils, paste dispensing or polyimide peel-andrelease stencils can be used. Once the device is ‘‘bumped’’ the component
can be precision placed and reflowed similar to other area array devices.
See Figure 7-24.
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Figure 7-24
a Stencil
Solder Bumping Method Using
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The second alternative method consists of using a laser rework system. In this case, the laser replaces hot-gas rework equipment and tooling, delivering localized heat in the area of the directed laser beam. A laser rework system has an advantage
in that it does not heat neighboring components, as would be the case when using hot-air systems. In addition, the laser
does not require different size nozzles for removal, helping to reduce rework tooling requirements.
Laser technology has gone through a tremendous change, from traditional yttrium aluminum garnet (YAG) and CO2 lasers
to semiconductor technology of diode lasers. Many applications exist where laser soldering will be more cost-effective than
traditional methods discussed in the preceding sections. Laser soldering has proven to be cost-effective for selective soldering of components when contact or convection reflow is not technically feasible.
Unlike hot-air/gas rework systems, laser soldering does not need special fixtures that add to variable cost. Focused-laser
soldering parameters are controlled in four stages:
1) Preheat temperature
2) Laser power (8 W to 30 W)
3) Wavelength (800 nm to 900 nm)
4) Time (milliseconds)
It generally takes less than one second for a typical solder joint, with or without the use of built-in preheat. In addition to
using traditional preheaters, the laser can be programmed for post-heat operations (just a few milliseconds) to achieve
desired solder joint quality.
Because laser soldering time is measured in milliseconds (as opposed to seconds), the intermetallic thickness is < 1 µm.
Touch-up of BTCs using a hand soldering iron is not recommended. Since BTCs often
do not have wettable side flanks for I/O pins, attempting to touch-up the device with additional solder (using cored wire or
wire and liquid flux) will not produce an improved solder fillet. Secondly, there is no access to the lap joint portion of an
I/O pad, and there is no access to the thermal pad under the device. Nearly all geometries involved require a very high
degree of hand soldering precision and excellent tooling, or damage to the component and nearby components is likely. For
these reasons, hand soldering touch-up is not a recommended practice for BTCs. Attempting BTC I/O pin touch-up may
introduce risk of dendritic growth if fluxes used during the operation are not fully activated.
7.12.3 I/O Lead Manual Touch-Up
Touching up BTCs is not recommended. The procedure can potentially introduce electrochemical reliability hazards from
additional flux applied to the touch-up location.
7.13 Conformal Coating of BTCs Conformal coatings protect parts from surface moisture and corrosion. Conformal coatings should be specified to meet the requirements of IPC-CC-830 and should be specified on the master assembly drawing.
The designer should be cognizant of compatibility issues with conformal coatings. Conformal coating is an electrical insulation material which conforms to the shape of the printed board assembly and its components. It is applied to improve
surface dielectric properties and to protect assemblies from the effects of a severe environment.
All conformal coating types provide various levels of protection from solvents, moisture, corrosion, arcing and other environmental factors which can jeopardize the circuit operation. Conformal coatings may be any of five types and recommended
thickness ranges:
1) Acrylic resin (AR) – 0.03 mm to 0.13 mm
2) Epoxy resin (ER) – 0.03 mm to 0.13 mm
3) Urethane resin (UR) – 0.03 mm to 0.13 mm
4) Silicone resin (SR) – 0.05 mm to 0.21 mm
5) Paraxylene resin (XY) – 0.01 mm to 0.05 mm
Special consideration should be taken when using conformal coatings with BTCs. Allowing coating material to wick underneath the package may cause early solder joint failures due to the z-axis expansion of the coating material during thermal
excursions.
By design, BTCs are connected to inner-layer printed board ground planes that help
to heat-sink the device as it heats up during operation, so mechanical heat sinks on top of BTCs is generally not required.
Studies conducted in this area suggest that adding external heat sinks (single or ganged) can have a negative effect on solder
joint (lap joint) reliability, so they are not recommended for use with BTCs.
7.14 Mechanical Heat Sink Usage
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7.15 Production-Level Testing
7.15.1 Electrical Testing Electrical testing is used to evaluate the functionality of the printed board assembly. Commonly
used electrical test approaches are probe testing, flying probe, in-circuit test (ICT) and functional test (FT).
Probe testing is used to detect faults caused by the manufacturing process and to isolate the majority of nonfunctional components. Flying probe testing uses electromechanically controlled probes to access components, while ICT uses a dedicated
bed-of-nails fixture. Flying probe testing is slower, but it does not require a dedicated fixture like ICT. Faults found by probe
testing include:
• Solder bridge
• Solder open
• Component misorientation
• Wrong component
• Component not functional
• Conductor short
Probe testing can be supplemented by complete FT at the end of assembly. This test for product functionality can, depending on type of product and the acceptability requirements, be as simple as a go/no-go test or as complex as a complete exercising of all circuit functionality. FT is used to detect device faults on the assembly at speed.
Given the current complexity in electronic assemblies, the level of coverage of test
has become an industry issue. The more complex a printed board or printed board assembly, the more difficult it is to fully
test. It may be difficult to test even a reasonable portion of the assembly in a reasonable (i.e., cost-effective) amount of time.
7.15.2 Functional Test (FT) Coverage
FT is performed during the last phase of the production line. It simulates the environment in which a product is expected
to operate. This is done to check and correct any issues with functionality, and it is usually effective only when yields are
high.
While printed board assembly test may be aided by incorporating testing into the silicon devices, this strategy is not
applicable to printed boards. The challenge of testing is to provide test coverage at a high level of confidence within a reasonable amount of time.
7.15.3 Burn-In Testing Burn-in testing is an operational and environmental test of the complete printed board assembly
at the upper limits of the application. This test typically finds more component-related problems than solder joint defects.
Burn-in testing is still in use for component evaluation, but it is decreasing for electronic assembly in favor of some form
of accelerated test exposure to screen out marginal results.
Environmental stress screening (ESS) is used during ongoing production for poor product quality and latent defects. ESS accelerates the latent defects to actual failures, eliminating these latent defects from causing failures in the field. Care should be taken so the ESS procedures are not sufficiently severe to damage good product and
produce new latent defects. Solder fatigue life on BTCs should be evaluated on the thermal cycling of these ESS tests, other
tests and operating life thermal environments.
7.15.4 Product Screening Tests
8 RELIABILITY CONSIDERATIONS FOR BTCs
8.1 Introduction and Reliability Fundamentals of BTCs
The following items need to be distinguished regarding reliabil-
ity of BTCs:
• Quality pertains to the as-produced assembly off the line and characterizes the fraction of devices assembled satisfying all
imposed acceptability criteria (particularly, in accordance with acceptability criteria per IPC-A-610 and, possibly, additional
acceptability criteria). See 6.15 for a discussion of known issues.
• Reliability is the ability of a product to function under given conditions and for a specified amount of time without
exceeding acceptable failure levels. Reliability pertains to the aged assembly, which has been subjected to field or fieldequivalent loads (in accelerated testing) and characterizes the fraction of devices that are functional after exposure to a certain load. This standard focuses on board-level reliability (i.e., the reliability of the connection between the BTC and the
printed board and the associated failures).
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In designing for BTC reliability, adherence to quality standards is necessary but not sufficient. For example, solder joint
quality is generally measured against criteria in IPC-A-610 (for overall workmanship) and J-STD-001. However, meeting
these criteria does not ensure reliable solder connections for a given product, but rather, only quality solder connections. In
the short term, reliability is threatened by infant mortality failures due to insufficient product quality. These infant mortalities, caused by defects, can be eliminated prior to shipping by using appropriate screening procedures.
Long-term failures are the result of premature wear-out damage caused by inadequate design of the assembly. This is why
IPC-D-279 was developed. Adopting Class 3 quality criteria for solder joints will ensure the optimum reliability of solder
joints for a given component, but reliability of a given BTC in a product will be affected by the overall assembly design,
for instance:
• Position of the BTC on the printed board
• Solder material
• Land design
• Printed board materials
• Stack-up
A thorough DfR approach should be followed to ensure a reliable product comprising BTCs.
The aspects of reliability discussed in 8.1.1 through 8.1.3 should be considered in the context of BTCs.
Mechanical reliability covers mechanical loads induced by mechanical shock or vibration
due to field use or accelerated lifetime testing. BTCs are small to medium-size components (typically, < 15 mm x 15 mm)
with limited height (typically, < 2 mm) and weight. Due to these constraints, their sensitivity to mechanical loads due to
mechanical shock and vibration is generally limited and can be ignored for most applications.
8.1.1 Mechanical Reliability
BTCs have absolutely no tendency to vibrate in eigenfrequency against the printed board (as it can occur for high components with limited I/O count; e.g., electrolytic capacitors) due to their rigid attachment by I/O, exposed-pad solder joints, not
being sensitive to oscillations of printed boards under mechanical shock or vibration excitation due to their small size (as
larger area-array components can be). A more detailed discussion of mechanical reliability is not necessary in the context of
this standard.
Thermomechanical
reliability covers thermomechanical loads induced by temperature variations due to field use, air temperature cycling,
highly-accelerated life-time testing, etc. BTCs consist mainly
of a lead frame, mold compound and one or multiple silicon
dies. The mold compound and die(s) have considerably lower
CTE than a typical FR-4-based printed board; therefore, any
changes in temperature with respect to a stress-free temperature will result in the exertion of stresses on the solder joints.
8.1.2 Thermomechanical Reliability
Due to the relatively low melting point of solder, even at room
temperature, the homologous temperature is above 0.5, which
means creep is the most important degradation mechanism in
the presence of thermomechanical loads. Cyclic thermomechanical loading will result in refinement of the grain structure
of solder joints by dynamic recrystallization and subsequently
the formation of intercrystalline cracks along grain boundaries, This will lead to failures of the mechanical and electrical
connection (see Figure 8-1).
Figure 8-1 Solder Crack in an I/O BTC Solder Joint Due to
Coefficient of Thermal Expansion (CTE) Mismatch After
1,000 Cycles
Mechanical and electrical connection failures occur mostly with peripheral I/O solder joints, because their distance to a neutral point on the package is largest and I/O solder joints are much smaller than the exposed-pad solder joint(s) (see 8.1.3).
8.1.3 Electrochemical Reliability Electrochemical reliability covers humidity, which can result in electrochemical migration phenomena between I/O solder joints and/or between I/O solder joints and the exposed-pad solder joint(s) induced by
the simultaneous presence of humidity, bias voltage and mobile ionic species. As BTCs generally have a small stand-off,
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compared to area-array components furnished with solder balls, SMT solder paste flux residue can be trapped within this
small stand-off and may not be properly thermally activated (see 6.12). This condition can potentially occur after SMT
reflow primary attach processing or after local rework of a BTC device. These potentially chemically active residues can
lead to unwanted reliability issues including electrochemical migration and/or corrosion. The concern with these reliability
failure modes is that they are often latent defects that are not necessarily identified or corrected during assembly and test
operations and are accelerated under product operating temperature, humidity and power-on voltage bias.
8.2 Designing for BTC Reliability – Thermomechanical Loads
8.2.1 Printed Board Design Considerations Printed board design is generally not driven by BTCs on the board, because
their I/O count is limited. Because of this, BTCs generally need to adapt to the board technology prescribed by the overall
assembly. The possibility to adjust printed board design for BTCs is very limited.
Obviously, CTE tailoring to reduce global expansion mismatch would be beneficial for improving board-level reliability
under thermal cycling. CTE tailoring involves choosing the materials or material combinations of the printed board and/or
the components to achieve an optimum difference in coefficient of thermal expansion (DCTE). An optimal DCTE for active
components dissipating power is ~1 to 3 ppm/°C (depending on the power dissipated) with the printed board having the
larger CTE, and 0 ppm/°C for passive components. Since an assembly has a multitude of components, full CTE optimization cannot be achieved for all components; it needs to be for the components with the largest threat to reliability.
If possible, unfilled microvias should not be placed under I/O
terminations, because these microvias can act as local sources
of voiding due to entrapment of flux residues in microvia
holes. The presence of additional voids caused by the presence
of microvias may have a negative effect on board-level reliability. When microvias need to be placed in the exposed-pad
soldering area on the printed board, it is recommended to
strive for a regular, centrosymmetric arrangement to avoid
irregular void distributions, which could result in nonconstant
stand-off by slight tilting of the component.
Thinner printed boards
result in better board-level reliability. FR-4 (~17 ppm/°C) has
a larger CTE than the package mold compound (~10 ppm/°C).
Thinner printed boards also reduce cyclic strains due to the
global CTE mismatch between the printed board and the package through flexing and increase solder joint fatigue life. Tests
conducted on 10-mm/68-lead and 5-mm/32-lead packages
using 0.8-mm- and 1.6-mm-thick printed boards demonstrate
at least 30 % improvement in fatigue life for the thinner board
(see Figure 8-2).
99
90
W2 RRX - SRM MED
F=26 / S=4
50
Thick
C
A
W2 RRX - SRM MED
D
F=29 / S=1
10
5
8.2.2 Printed Board Thickness
1
100
1000
10000
B
1=13.69, 1= 1254.23, = 0.97
2= 9.42, 2= 854.83, = 0.94
IPC-7093a-8-2
Figure 8-2 Weibull Plot Demonstrating Thinner Printed
Boards Result in Higher Fatigue Life
A–
B–
C–
D–
Cumulative percent failed
Cycles to failure
1.6-mm board
0.8-mm board
8.2.3 Wettable Side Flank Effect on Reliability The postpackage assembly singulation process (sawing or punching
the individual devices from the processed lead frame strip)
typically leaves a bare Cu lead frame at the singulation edge. Because bare Cu resulting from the singulation operation is
not protected against oxidation and does not easily solder-wet, a solder fillet (toe fillet) does not generally develop. Depending on parameters such as storage time and environmental conditions, wetting of the bare Cu at the toe may occur for more
than 90 % of the pins, but under standard mass-production conditions, a robust wettability of the bare Cu surfaces cannot
be ensured. J-STD-001, recognizing absence of a continuous solderable surface, does not require the presence of a toe fillet
for Pb-free BTC solder joints.
Post-singulation plating using electrodeposition is possible but can be used only for certain dual-flat no-lead packages. These
devices are only partially singulated at the time of plating, so an electrical connection of all pins is possible. In general, the
key to the generation of wettable flanks lies in the separation of a part of the flank from the plane by cutting or sawing.
Different strategies have been devised for accomplishing this (see Section 4).
Solder joint robustness is increased by the presence of a robustly wettable singulation edge. The number of cycles to failure under thermal cycling is typically increased by up to ~20 % in the presence of an outer fillet.
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8.2.4 Land Size and Pitch Another influence on reliability
is the geometry of the solder joint derived from the land metallization on the printed board. Since BTCs are leadless
devices, solder joint shape relates to the land. A larger land
under a BTC package provides better reliability in thermal
cycling, as shown on the Weibull plot in Figure 8-3. Comparing a 7-mm package with 28 terminations and with land sizes
0.28 mm x 0.6 mm with a 48-terminal package with land size
0.23 mm x 0.4 mm QFNs results in a 2X improvement in
fatigue life. The larger land results in a larger solder joint and
longer path for a complete crack to form. This implies that at
a given package size and pitch, the lead length will be a crucial parameter. The longer the lead, the better the reliability.
Package stand-off is a
parameter that affects the reliability of BTC solder joints.
Package stand-off for a BTC is defined as the distance
between the land on the bottom of the package substrate and
the land on the printed board surface. Based on continuum
mechanics, an increase in stand-off will result in lower strain
in the I/O solder joints upon a given temperature change, so
increased board-level reliability under thermal cycling is
expected. This expectation is generally confirmed by experimental results, but it has a limit when going to very low
stand-offs (e.g., < 30 µm). For these very low stand-offs, a
continuum-mechanics approach is no longer feasible, because
the microstructure of the solder joints changes due to dimensional constraints. A flattening-off of the linear relationship
between stand-off and reliability will occur. Additional
reduction in stand-off will not further reduce thermal cycling
reliability.
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For a given land design, increased stand-off can be achieved
by using a thicker stencil. There are limits to this option due
to aperture area and aspect ratio requirements for paste release
and floating risk of the center pad. Also, since multiple types
of components are mounted on the same printed board, using
a thicker stencil for one or two components is not desirable.
One alternative is to increase the thickness of the plating on
the thermal pad on the underside of the package. Figure 8-4
shows this plate-up bumped option. In this concept, a plating
thickness of 100 µm increased the stand-off height of the
package solder joints by 100 µm, which resulted in a 2X
increase in printed board reliability of the package as shown
in Figure 8-5.
F=30 / S=0
7mm-48
50
W2 RRX - SRM MED
A
F=23 / S=7
10
5
1
100
8.2.5 BTC Package Stand-Off
Stand-off can be adjusted by the amount of solder deposited
at the exposed pad solder joint and by using an exposed-pad
land design (see 6.8.4). Stand-off height on all BTCs should
be verified during process setup. It is recommended to establish the process to reproduce the stand-off height for specific
components.
7mm-28
90
1000
10000
B
β1=8.60, η1=2124.93, ρ=0.98
β2=9.61, η2=1106.65, ρ=0.93
Figure 8-3
Packages
IPC-7093a-8-3
Land Size Effect on Fatigue Life of 7-mm BTC
A – Cumulative percent failed
B – Cycles to failure
A
B
Figure 8-4
Plate-Up Bumped Option
A – Plate-up bump on lead
B – Plate-up bump on die paddle
99
90
W2 RRX - SRM MED
C
50
F=5 / S=25
D
A
W2 RRX - SRM MED
F=7 / S=23
10
5
1
1000
10000
B
β1=10.08, η1=4447.98, ρ=0.97
β2=14.00, η2=2255.67, ρ=0.97
Figure 8-5
IPC-7093a-8-5
Stand-Off Effect on Fatigue Life of a BTC
A – Cumulative percent failed
B – Cycles to failure
C – Nonbumped (Std)
D – Bumped
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BTC underfill can substantially enhance fatigue life. When underfill is applied correctly,
it reduces the solder joint strain level by constraining the expansion of the BTC interconnect to be used in a wider range of
environments, and larger device sizes can be accommodated. Underfill material should be carefully selected so it adheres to
the assembly surface but does not adversely stress the BTC interconnect joints. The material should have properties which
allow easy application to avoid process defects, and it also should not contain or trap contaminants, which could initiate
corrosion-related problems.
8.2.6 Benefits of Reinforcement
If an underfill fails, it will most likely lose adhesion to the device and/or substrate. This would lead to failure due to fatigue
or creep, and it could also increase chances of corrosion and other failure mechanisms.
Mold compound selection has an impact on package reliability. Selection of mold material should be based on meeting both package reliability requirements (e.g., moisture sensitivity level) and board-level reliability. Board-level reliability directly depends on the CTE of the mold compound. Mold compounds with lower CTE have
performed worse in reliability testing than those with higher CTE (similar to that of the printed board material). The mold
compound modulus also affects the stiffness of the package. Higher modulus will result in stiffer package and lower fatigue
life.
8.2.7 Mold Compound Material
Die size has a significant effect on board-level reliability. As the die-to-package ratio decreases, board-level
reliability increases. With smaller die, board-level reliability is better because the die edge, which has a low CTE, is farther
away from the peripheral solder joints.
8.2.8 Die Size
The solder joint stand-off of BTCs, compared to BGAs, is very small.
This results in the potential issue of solder joint embrittlement due to interactions with noble metal surface finishes. The
elements Au, Ag and Pd can form IMCs in the solder joint microstructure during soldering. These IMC phases, often in the
form of a platelet structure, can segregate to solder joint interfaces and weaken them.
8.2.9 Solder Joint Microstructure Embrittlement
As an example, 3 % to 5 % Au (by weight) in Sn results in the AuSn4 IMC structure that can embrittle a solder joint interface. It is critical that noble metal surface finishes are controlled, in combination with the intended soldering process, such
that solder joint embrittlement is avoided. ENIG and immersion Ag board surfaces finishes are not of sufficient plating
thickness to cause solder joint embrittlement for standard soldering processes.
8.3 Designing for BTC Reliability – Electrical and Thermal Loads
Voiding in BTC thermal pads
can have significant effects on the thermal dissipation and/or
electrical grounding functionality of BTC components.
Because the typical BTC package incorporates a large center
pad, controlling solder voiding within this region can be difficult. Within these large solder joints, the void content typically is significantly higher than in small I/O solder joints. The
range which usually can be found with standard production
parameters is between 10 % and 50 %. With good process
control, it is possible to achieve < 30 %.
8.3.1 Voids in Thermal Pad
Voids within solder joints can have an adverse effect on highspeed and radio-frequency applications. Voids within this center plane can increase the current path of the circuit. The
maximum size of a void should be less than the via pitch
within the plane. This recommendation can ensure any one via
would not be rendered ineffectual based on any one void
increasing the current path beyond the distance to the next
available via.
Another concern with voiding is a negative effect on heat
transfer in the vertical direction. This can be assessed by a
simple calculation of thermal resistivity. Figure 8-6 shows a
simplified model of this.
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A
B
C
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Figure 8-6
Heat Transfer with Exposed Pad Solder Joints
A – Component
B – Rth
C – Heat sink / Housing
October 2020
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Figure 8-7 shows the calculation of the influence of voiding in overall thermal resistance of solder joints and the printed
board for an exemplary 30 mm2 solder area with 25 PTHs of 0.5-mm diameter (unfilled and filled vias).
100
9
8
7
10
6
A 5
D
4
C
1
3
2
E
F
G
H
1
0
0%
10%
20% 30% 40%
50%
60% 70% 80%
B
Figure 8-7
A–
B–
C–
D–
0.1
90% 100%
IPC-7093a-8-7
Calculation of Void Influence Within Exposed Pads on Overall Rth
Overall Rth [K/W]
Void percentage pad
Rth ratio via/solder joint
Normal range of exposed pad voiding
E–
F–
G–
H–
Overall Rth via unfilled
Overall Rth via filled
Ratio Rth printed board / solder joint via unfilled
Ratio Rth printed board / solder joint via filled
This calculation clearly shows solder joints of exposed pads
on standard printed boards are not sensitive to voiding up to
~80 % or 90 % area. The main bottleneck for heat transfer is
the printed board base material. Thus, at least normal voiding
levels, up to ~60 % void area, can be considered as uncritical.
Figure 8-8 shows an example for actual voiding found in
standard Pb-free production.
One specific circumstance requires attention. When an
exposed pad of a BTC is soldered directly to a massive heat
sink (e.g., Cu inlay in a printed board), the preceding considerations on permissible voiding levels do not apply because
the solder joint can now become the bottleneck for thermal
transfer. In this case, lower limits may be required to ensure
sufficient thermal transfer between the component and heat
sink.
Figure 8-8 Acceptable Thermal Pad Voiding Levels
(< 30 % by Cross-Sectional Area)
8.4 Reliability Testing
Endoscopy is an optical inspection method that permits visual inspection of tiny objects in a small, confined area. This technology has been adapted and applied to BTC solder joint inspection.
Adding localized fiducial locations also can help in identifying accurate position for placing BTC devices.
8.4.1 Time Zero Assembly Analysis by Endoscopy
BTC solder joints can be inspected and analyzed for a variety of critical factors such as:
• Overall solder joint quality – evidence of proper wetting
• Solder joint shape – evidence of proper reflow
• Solder joint surface texture – smooth vs. irregular
• Overall solder joints appearance – flux residue, etc.
• Solder joint defects – solder shorts, opens and cold solder
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Endoscopic inspection technology is best suited for inspecting only the exterior row of BTC solder joints. A limitation of
this technology is the inability to view interior rows with the same level of quality and clarity. It is sometimes possible to
focus on interior solder joints but not at the same level of detail as the exterior rows.
Testing lifetime expectations of components under
actual use conditions would take as long as the design life of the component. For this reason, packages are tested by accelerating the thermal cycles (i.e., by increasing the temperature range and decreasing the hold times at each end of the cycle).
Increasing the temperature range subjects the joints to greater strain, the extent of which is determined by the thermal
expansion mismatch between the different materials. Increasing the temperature range should increase damage to the joints
if enough time is allowed for the elastic stresses generated in the solder joints to relax out by converting the elastic strains
into plastic deformations by creep. If enough time is not allowed during the hold times, which is typically the case with
accelerated tests, damage will not be equal to what it would be if the solder joints were allowed to creep completely. It is
important to note that increasing the temperature range of the test much beyond the temperatures in the field may cause a
confounding of multiple damage mechanisms. For example, changing the temperature rapidly during thermal shock testing
can cause high strain rates as well as high strains due to component warpage to be imposed on the solder, which changes
the failure mechanism.
8.4.2 Accelerated Life Testing for Thermomechanical Reliability
With near-eutectic solders it is necessary to have hold times ranging from five to 10 minutes to achieve significant, but still
incomplete, creep in the joints. Stress relaxation in high-Pb solders (e.g., PbSn10) is slower than that observed in eutectic
solders; therefore, hold times at the temperature extremes need to be greater. Thermal cycles represent the number of thermal excursions to which a device will be exposed during its lifetime. These excursions consist of power on/off cycles and
environmental temperature fluctuations. Temperature cycling will test the inelastic properties of the solder, namely stress
relaxation as a function of temperature and time.
Validation and qualification tests should follow the guidelines given in IPC-SM-785. However, for components with significant heat dissipation, components of asymmetric construction and for small global CTE mismatches, temperature cycling
tests may be inadequate to provide the required information. Full functional cycling, including external temperature and
internal power cycling, may be necessary.
Accelerated reliability testing typically is carried out to failure or until a predetermined reliability goal is achieved. The
appropriate reliability goal can be determined with an appropriate acceleration model (see IPC-D-279). Once failure occurs,
the resulting failure modes are analyzed as to the underlying failure mechanism(s). If it fails expectations, corrective action
is necessary. Either the assembly process needs to be improved or the product needs to be redesigned. In either case, retesting may be necessary after the corrective action has been implemented.
In nondestructive testing, the integrity of solder joints can be assessed by monitoring their electrical function. This can be done on the level of test boards, if appropriate BTCs with an internal daisy-chain
wiring are available, by electrical monitoring of the resistance of the daisy-chain channels while accelerated lifetime testing
is conducted.
8.4.2.1 Nondestructive Test Methods
Failure of the solder attachment of a component to the substrate to which it is surface mounted is commonly defined as the
first complete fracture of any of the solder joints of which the component solder attachment consists. Given that the loading of the solder joints is typically in shear, rather than in tension, the mechanical failure of a solder joint is not necessarily the same as the electrical failure. Electrically, the mechanical failure of a solder joint results, at least initially, in the
occasional occurrence of a short-duration (< 1 µs), high-impedance event during either mechanical or thermal disturbance.
From a practical point of view, solder joint failure is defined as the first observation of such an event.
For some applications, this failure definition might be inadequate. For high-speed signals with sharp rise times, signal deterioration prior to the complete mechanical failure of a solder joint might require a more stringent failure definition. Similarly, for applications which subject electronic assemblies to significant mechanical vibration and/or shock loading, a failure
definition that considers the mechanical weakening of the solder joints as the result of the accumulating fatigue damage
might be necessary (see 8.4.2.2).
If BTCs with a daisy-chain wiring are not available, functional devices may be subjected to accelerated lifetime testing at
the product level. In this case, not all solder joints may be testable (i.e., due to connection redundancy on multiple solder
joints).
If nondestructive methods are not applicable or such methods used to identify a malfunction do not elicit the cause of failure, destructive analysis techniques may be used. Such techniques will render the analyzed
assembly unusable. Once the cause of the failure has been identified, the information can be used to implement corrective
actions to eliminate the problem.
8.4.2.2 Destructive Methods
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8.4.2.2.1 Cross-Sectioning Cross-sectioning is one method traditionally used for failure analysis. It enables an operator
to analyze a specific section of a component, substrate and solder joint.
If more than one area is suspect, a determination needs to be made whether those areas can be accessed sequentially on the
same component. If not, the areas will need to be prioritized according to the possibility of finding the problem, or more
than one component will need to be analyzed.
If the problem area is a part of a larger assembly, it may need to be isolated into a small, more manageable portion by cutting
it out of the larger assembly. Care should be taken to ensure the area of analysis is not tampered with or destroyed during
the cutting and polishing process.
For proper sectioning, the sample should be molded in resin to alleviate chipping or destruction of the sample during crosssectioning. If fine-polishing the area of interest is required, the sample should be sectioned a reasonable distance away from
the interface of interest, providing sufficient distance for fine-polishing the interface.
In some cases, the entire component may need to be ground through and visually inspected for the integrity of various interfaces. A common failure analyzed through cross-sectioning is an open occurring in an assembly. Such opens may occur at
the solder interface.
Additional information on metallographic cross-sectioning can be found in the IPC-MS-810 and IPC-TM-650, Method 2.1.1.
8.4.2.2.2 Dye Penetrant Dye penetrant methods can be used during process setup and in failure analysis to detect solder
joint cracking, wetting problems and package delamination. In this process, the sample is immersed in a low-viscosity liquid dye which penetrates most cracks, delaminated areas or open voids. The sample component can then be peeled away
and examined for the presence of dye in the solder joints or at material interfaces.
If a fluorescent dye is used, the sample should be inspected under UV light. The dye enhances the visibility of flaws that
might otherwise be difficult to detect. The presence of dye on a solder land indicates poor wetting to the land and can be
used to estimate the portion of the land that was not wetted; however, very thin cracks may be so small that liquids cannot
completely enter because the surface tension of the liquid will not allow it. See IPC-TM-650, Method 2.4.53 for a dye and
pull (pry) test.
Due to the boundary conditions for BTCs relative
to potential entrapment of flux residues (see 7.4), thorough reliability testing under damp-heat conditions is advisable for all
mission-critical applications intended for operation under damp-heat conditions. It is advised to adopt an approach as
described in IPC-9203 to optimize and qualify a manufacturing process and materials resulting in acceptable levels of residues for a given product featuring BTCs.
8.4.3 Accelerated Lifetime Testing for Reliability Under Damp Heat
9 TROUBLESHOOTING
This section identifies anomalies related to BTC assembly and
provides some possible causes and solutions.
This section is
intended to help the user avoid known reported problems that
have been encountered at various stages of printed board fabrication and electronic card assembly processes using BTCs.
9.1 Assembly and Fabrication Issues
9.1.1 Printed Board Supplier Solder Mask Alterations It is
important to ensure printed board suppliers do not modify
solder mask web designs per original design file artwork to
accommodate internal printed board fabricator process capability. Figure 9-1 shows a SMD thermal pad structure that was
modified by a printed board manufacturer. Important solder
mask webs required by the design were removed from the
thermal pad. In addition, such changes were not communicated. While a SMD thermal pad structure was intended, a
modified design resembling a hybrid open-Cu design was fabricated. As this example illustrates, it is important to review
Figure 9-1 Printed Board Manufacturer Removal of Solder
Mask Web
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and verify actual printed board constructions produced by the printed board manufacturer to ensure desired BTC thermal
pad structures are fabricated.
Printed board Cu shapes
should be designed with stencil aperture ratios in mind. SMT
stencil aperture openings should be designed 1:1 with Cu thermal pad shapes and I/O pads. Figure 9-2 shows an example of
where significant SMT stencil aperture modifications were
made by a printed board manufacturer. Resulting thermal pad
print deposits do not match Cu windows. Low percentage
coverage, solder via wicking, signal opens, and increased risk
of intermittent ground failures have been reported with such
drastic modifications. As outlined in 6.13, stencil apertures
should be designed to always follow Cu geometry found on
the printed board.
9.1.2 SMT Stencil Alterations
9.1.3 Alternate SMT Stencil Printing Methods Alternate
SMT stencil printing methods have been implemented with
highly variable results. Zebra printing patterns on open-Cu
thermal pad designs (as shown in Figure 9-3) have been used
attempting to avoid printing solder down through-hole vias,
allowing proper outgassing channels to reduce voiding and
trying to ensure adequate thermal pad solder coverage.
Figure 9-2
Solder Deposits Not 1:1 with All Cu Pads
Figure 9-3
Zebra Printing on Open-Cu Thermal Pad
Unfortunately, resulting constructions using this approach
have not been very effective and are not well controlled. Minimum percentage solder coverage violations (< 45%),
increased stencil aperture clogging / reduced throughput and
via solder wicking have all been reported using this approach.
As a result, alternate stencil printing methods such as zebra
printing patterns are not recommended. See Section 6 for preferred thermal pad designs and stencil design approach.
Voiding should be minimized
by solder process development and recurring process controls.
For information on thermal pad voiding, see 8.3.1.
9.1.4 Thermal Pad Voiding
9.1.5 I/O Pad Voiding IPC-A-610 does not specify voiding
levels for BTC I/O pads, but a 20 % limit is a general target
for voiding. Higher voiding levels are a process indicator that
further optimization in the assembly process or assembly
materials used may be required.
Nonwetted I/O side flanks can be confused with I/O opens; however, this a function of the
incoming BTC component construction. Some suppliers do not offer solderable side flanks, which can lead to an open condition.
9.1.6 I/O Opens and Bridging
Solder opens are not acceptable. A combination of electrical testing, optical inspection (endoscope) or X-ray inspection is
usually necessary to detect solder opens. Poor solder paste printing, inaccurate placement and manual tweaking after placement are typical assembly-related causes of solder opens. Coplanarity and substrate solderability problems can also cause
opens. Excessive mechanical stress can also cause solder joints to crack and create opens.
Solder bridging is not acceptable. Electrical testing, optical inspection (endoscope) or X-ray inspection is necessary to detect
solder bridging. Poor solder paste printing, inaccurate placement, manual tweaking after placement and solder splattering
during reflow are typical causes of solder bridging.
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9.2 BTC Assembly Troubleshooting
The following sections provide some general troubleshooting topics related to BTC
assembly.
9.2.1 BTC Open Joints
Possible Cause
Insufficient solder paste volume during printing
Potential Solution
Check paste volume after printing
Check to be sure correct stencil was used
Check aspect ratio and area ratio
Check printer settings
Check solder paste expiration date
Figure 9-4
Cross-Section of BTC Open Joint
Possible Cause
A
Low-temperature solder (SnPb43Bi14) causing interfacial
fracture during vibration testing
Potential Solution
Use polymeric reinforcement, such as underfill
Change to vibration-resistant alloy (e.g., SnPb, SnPbAg, low-Ag
Pb-free)
Figure 9-5 Open Shown in Cross-Section (Top) and Dye
and Pull (Bottom)
Change surface finish of component pad
A – Separation
9.2.2 Solder Attachment Failures
9.2.2.1 Nonsoldered Land on LGA
Possible Cause
Printed board warpage
Package warpage
Printed board pad contamination
Potential Solution
Reduce warpage of package and printed board
Figure 9-6
Nonsolderable Land on LGA package
Increase paste volume
Use reflow fixture / printed board carrier
Change paste formulation
Check solderability of printed board surface
Check solderability of BTC package
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9.2.2.2 Nonwet Joint on QFN
Possible Cause
Nonwetting of the solder to the bottom land of the QFN
Potential Solution
Check solderability of package termination
Use more aggressive flux
Use N reflow
Change package land termination surface finish
Caution: Use of aggressive flux when using BTCs may cause
flux entrapment and potentially may cause corrosion. Use of
aggressive flux with BTC applications is not recommended.
Figure 9-7
Nonwet Joints on a QFN
9.2.2.3 Insufficient Solder in Joint on QFN
Possible Cause
Clogged aperture
Incorrect aperture design
Potential Solution
Check area ratio and aspect ratio to be sure it complies with
IPC-7525
Clean stencil
Use fresh solder paste
Ensure solder paste is not expired in shelf life
Figure 9-8
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9.2.2.4 Tilted Component
Possible Cause
Uneven paste
Board design
Board surface topography
Incorrect reflow profile
Misplacement during pick-and-place
Part coplanarity (package warpage)
Potential Solution
Reduce paste volume by using windowpane printing (area of
paste separated by no paste)
Try to achieve 50 % to 70 % area coverage by paste on
thermal pads
Figure 9-9
Open Due to Tilted BTC
9.2.2.5 No Side Fillet
Possible Cause
BTC design does not have a wettable flank
Potential Solution
This is not a defect, so no action required
If side fillet is required in the application, use BTCs with plated
terminations (higher cost)
If AOI-compatible solder joint is required, use BTC design with
a wettable flank
Figure 9-10
No Side Fillet
9.2.2.6 Microvoids in a BTC I/O Solder Joint
C
E
F
Figure 9-11
Possible Cause
Improper plating materials and/or process control for matte Sn
on the BTC terminations
D
Potential Solution
A
B
Optimization of the matte Sn plating process and/or materials at
the BTC manufacturer
Microvoids in a BTC I/O Solder Joint
A – Side view X-ray scan
B – Top view X-ray scan
C – BTC
D – Planar microvoids
E – Solder joint
F – Printed board
Note: Planar microvoids are visible at the BTC termination surface in a
functional solder joint. Since they occur in a plane of the solder joint, which
is in a location where thermomechanical stress cracks tend to develop,
the presence of these microvoids are a significant reliability risk.
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APPENDIX A
Index of Acronyms and Abbreviations
AOI – Automated optical inspection
AR – Acrylic resin
Au – Gold
AXI – Automated X-ray inspection
BGA – Ball grid array
Bi – Bismuth
BOM – Bill of materials
BT – Bismaleimide-triazine
C – Carbon
CAD – Computer-aided design
CMM – Coordinate measuring machine
COL – Chip on lead
CSP – Chip scale package
CTE – Coefficient of thermal expansion
Cu – Copper
DAP – Die-attach pad
DCTE – Difference in coefficient of thermal expansion
DFN – Dual-flat no-lead
DfR – Design for reliability
DOE – Design of experiments
ECM – Electrochemical migration
EMS – Electronics manufacturing services
ER – Epoxy resin
ESD – Electrostatic discharge
ESS – Environmental stress screening
FBA – Fine-pitch ball grid array
FC-QFN – Flip chip QFN
FCOL – Flip chip on lead frame
Fe – Iron
FHS – Finished hole size
FT – Functional test
FTC – Final total percentage coverage
HASL – Hot-air solder leveling
HAST – Highly-accelerated stress test
HDI – High-density interconnect
ICT – In-circuit test
I/O – Input/output
LFCSP – Lead frame chip scale package
LGA – Land grid array
LLP – Leadless lead frame package
LMC – Least material condition
LPI – Liquid photoimageable
MLF – Micro lead frame
MLFP – Micro lead frame plastic
MLP – Micro lead package
MMC – Maximum material condition
MSL – Moisture sensitivity level
MSOP – Micro small outline package
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Ni – Nickel
NSMD – Non-solder mask defined
O – Oxygen
Pd – Palladium
PPF – Pyrolyzed photoresist film
PQFN – Pull-back quad flat no-lead
PSON – Pull-back small outline no-lead
PTH – Plated-through hole
QFN – Quad-flat no-lead
QFP – Quad flat pack
RoHS – Restriction of Hazardous Substances
SiP – System-in-package
Si – Silicon
SIR – Surface insulation resistance
SMD – Solder mask defined
SMT – Surface mount technology
Sn – Tin
SODFL – Small outline diode flat lead
SOFL – Small outline flat lead
SOIC – Small outline integrated circuit
SON – Small-outline no-lead
SOT – Small outline transistor
SPI – solder paste inspection
SR – Silicone resin
SSOP – Shrink small outline package
Tg – Glass transition temperature
TO – Transistor outline
TSC – Temperature-sensitive component
TSSOP – Thin shrink small outline package
UR – Urethane resin
VIPPO – Via-in-pad plated-over
WEEE – Waste Electrical and Electronic Equipment
XY – Paraxylene resin
YAG – Yttrium aluminum garnet
Zn – Zinc
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This Page Intentionally Left Blank
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