Simultaneous
Switching Noise of CMOS
Devices and Systems
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ELECTRONIC PACKAGING AND INTERCONNECTS
Consulting Editor
John L. Prince
The University of Arizona
Center for Electronic Packaging Research
Simultaneous
Switching Noise of
CMOS Devices and
Systems
by
Ramesh Senthinathan
Advanced Packaging Development Center
(APDC)
Motorola, Inc.
John L. Prince
Center for Electronic Packaging Research
(CEPR)
The University ofArizona
"
~.
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
Senthinathan, Ramesh, 1961 •
Simultaneous switchîng noise of CMOS devices and systems 1 by
Ramesh Senthinathan, John L. Prince.
p. cm. -- (The Kluwer international series in engineering and
computer science. Electronic packaging and interconnects)
) and index.
Includes bibliographical references (p.
ISBN 978-0-7923-9400-6
ISBN 978-1-4615-3204-0 (eBook)
DOI 10.1007/978-1-4615-3204-0
1. Metal oxide semiconductors--Design and construction.
2. Electronic circuits--Noise. I. Prince, J ohn L., 1941 •
IL Ti tie. III. Series.
TK7871.99.M44S5 1994
621.3815--dc20
93-32572
CIP
Copyright © 1994 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1994
Softcover reprint of the hardcover 1st edition 1994
Al! rights reserved. No part of this publication may be reproduced, stored in a retrieval
This book is dedicated to the
Center for Electronic Packaging Research (CEPR),
Department of Electrical and Computer Engineering at the
University of Arizona,
Tucson, Arizona.
TABLE OF CONTENTS
Page
LIST OF FIGURES
LIST OF TABLES
PREFACE
ACKNOWLEDGMENTS
Xl
xv
XVll
XIX
CHAPTER 1 - INTRODUCTION
1
1.1 Background .
1
1.2 Introduction
3
CHAPTER 2 - PACKAGED/SCALED CMOS DEVICES
2.1 Introduction
9
9
2.2 Interconnect Scaling
10
2.3 Delays with Driver/Interconnect Scaling
13
2.4 Summary . . . . . . . . . . . . . .
17
CHAPTER 3 - METHODS OF CALCULATING SIMULTANEOUS
SWITCHING NOISE
19
3.1 Introduction
19
3.2 Theory and Modeling
23
3.3 Ground Noise and Vss Pad-Pin Connection Calculation
27
SSN OF CMOS DEVICES AND SYSTEMS
vIn
3.4 Results . . . . . . . . . . . . . . . . . . . . .
3.5 Behavior of Simultaneous Switching Noise with Scaling
3.6 Summary . . . . . . . . . . . . . . . . . . . .
CHAPTER 4 - POWER DISTRIBUTION INDUCTANCE MODELING
28
30
32
33
4.1 Introduction
33
4.2 Mathematical Formulation of UALGRL
35
4.3 Effective Inductance "Lvss" Modeling
37
4.4 Reference Plane Inductance Network Calculation
41
4.5 Results .
46
4.6 Summary
51
CHAPTER 5 - SIGNAL CONDUCTORS OVER A
PERFORATED REFERENCE PLANE
5.1 Introduction
53
53
5.2 Impact of Reference Plane Openings for Stripline Geometries 57
5.3 Connector Characterization Using S-Parameter Measurement
Techniques
. . . . . . . . . . . . . . . . . . ..
60
5.4 Modeling Using Two Dimensional (TEM) Approximation
64
5.5 Three-Dimensional Modeling Technique
67
5.6 Comparison Between Measurement and Simulations
72
5.7 Full-Wave Analysis of a Periodically Perforated Structure
80
5.8 Summary . . . . . . . . . . . . . . . . .
83
CHAPTER 6 - DYNAMIC NOISE IMMUNITY, AND
SKEWING/DAMPING SSN WAVEFORM
85
6.1 Introduction
85
6.2 Driver Switching Noise and Receiver Noise Immunity
87
6.3 Effects of Skewing Output Drivers . .
91
6.4 Trade-offs in Using Damping Resistors
93
CONTENTS
IX
6.5 Summary . . . . . . . . . . . . . . .
CHAPTER 7 - APPLICATION SPECIFIC OUTPUT
DRIVERS TO REDUCE SSN
7.1 Introduction
97
99
99
7.2 CMOS Output Driver Switching Current Components
100
7.3 Current Controlled Output Drivers .
103
7.4 Controlled Slew Rate Output Drivers
105
7.5 Summary . . . . . . . . . . . .
115
CHAPTER 8 - SSN SIMULATOR ARCHITECTURE
117
8.1 Introduction
117
8.2 SSNS Architecture
118
8.3 "Lv ss" Modeling for MCM Vss Connections
121
8.4 Simultaneous Switching Noise Calculation for CMOS MCM 123
8.5 Summary . . . . . . . . . . . . . .
CHAPTER 9 - SIGNAL CONDUCTORS OVER A
NOISY REFERENCE PLANE
128
129
9.1 Introduction and Motivation
129
9.2 Equivalent Electrical Circuit Model Formulation
131
9.3 Calculation of Lumped Circuit Elements
136
9.4 Transient Response Simulations
141
. . . .
9.5 Impact of Vss Package-Pin Placement on Noise Modeling
151
9.6 Summary . . . . . .
156
CHAPTER 10 - CONCLUSIONS
157
CHAPTER 11 - DISCUSSION AND FUTURE WORK
161
11.1 BiCMOS Outputs Simultaneous Switching Noise
161
11.2 Use of Substrate-Taps to Reduce SSN . . . . .
163
x
SSN OF CMOS DEVICES AND SYSTEMS
11.3 SSNS Architecture Improvement
165
APPENDIX A
167
APPENDIX B
173
APPENDIX C
177
APPENDIX D
181
APPENDIX E
183
REFERENCES
187
....
201
ABOUT THE AUTHORS
205
INDEX
LIST OF FIGURES
Page
Figure
2.1
Typical on-chip Si - Si0 2 interconnect structure
11
2.2
A CMOS Inverter with device/interconnect parasitics
14
2.3
Delays with [CV] scaling using exact, approximate, and no
interconnect parasitics values . . . . . . . . . . . .
15
2.4
Normalized capacitance and resistance with [CV] scaling
16
3.1
Typical multilayer chip-package interface parasitics
20
3.2
3.3
CMOS output driver with lumped package parasitics
Typical CMOS output driver switching characteristics
21
22
3.4
On-chip VDD/VSS bus, and noise feed through mechanisms
23
3.5
Ground noise vs.
#
#
of simultaneous switching drivers
28
of ground pad-pin connections
30
3.6
Ground noise vs.
3.7
Simultaneous switching noise as a function of [CV] scaling
31
4.1
Typical "direct-connection" package Vss connections
34
4.2a
Perforated Vss plane with multiple sink/source points [4.5]
38
4.2b
Contour "e" used in equation (4.7)
38
4.3a
Single chip-package interface model
39
4.3b
Equivalent inductance network . .
39
4.4a Current distribution on a Vss plane without perforations
4.4b Current distribution on a Vss plane with perforations . .
4.5 Perforated copper Vss plane with two arbitrary rectangular cuts
42
42
43
4.6a
A Vss plane with three Vss pins
4.6b
Equivalent inductance network of Figure 4.7 Vss plane
44
4.7
A non-perforated Vss plane with eight sink points
47
. . . . . . . . . .
44
xu
4.8
4.9
4.10
4.11
5.1
SSN OF CMOS DEVICES AND SYSTEMS
A perforated Vss plane with eight sink points
47
Comparison of perforated and non-perforated Vss plane
inductance vs. # of sink points
3 rnA drivers, 16 outputs simultaneous switching noise
12 rnA drivers, 32 outputs simultaneous switching noise
48
50
50
Equivalent circuit model of a perforated reference plane
strip line interconnect structure
. . . . . . . . .
54
5.2
Scaled-up, perforated reference plane stripline model
55
5.3
Scaled-up model crossection
55
5.4
Periodically perforated card structure
56
5.5
Card structure interconnect cross-section
5.6
5.7
5.8
Stripline, buried microstripline impedance vs. conductor height
Reflection coefficient (p), llZ vs. conductor height
Two-port network equivalent transmission line model
56
58
59
61
5.9
TDR measurement setup and connections
63
5.10
Two-dimensional (PUL) capacitance/inductance modeling
65
5.11
Total, scale model measured and calculated capacitance values
66
5.12
Three-dimensional inductance modeling . . . . . . . . . .
68
5.13
X-Y bar formations for 3-D inductance modeling
. . . . ..
69
5.14 Total, and llL inductance values vs. conductor/plane thickness
69
5.15
70
.....
Comparison between 2-D and 3-D inductance values
5.16 Total inductance with and without perforation vs. conductor height 71
5.17
Inductance modeling for "gap" type perforation discontinuity
5.18a Comparison between measurements and simulations for stripline
5.18b Measurements and simulations for 5x1 cm perforation size
5.19a Measurements and simulations for 5x4 cm perforation size
5.19b Measurements and simulations for 5x8 cm perforation size
5.20a Measurements and simulations for 10x1 cm perforation size
5.20b Measurements and simulations for 10x4 cm perforation size
5.21a Measurements and simulations for 10x8 cm perforation size
5.21b Measurements and simulations for 20.4x20.4 cm perforation size
72
73
73
75
75
76
76
77
77
5.22a Signal disturbance (ll V) vs. perforation length for 5 cm
perforation window width . . . . . . . . . . . . .
78
LIST OF FIGURES
5.22b
Ll V vs. perforation length for 10 cm perforation window width
Xlll
78
5.24
5.25
5.26
6.1
Ll V vs. perforation area (different widths)
79
Card structure, unit cell discontinuity inductance modeling
80
Return current path on the top perforated reference plane .
81
Measurement and simulation comparison for eleven perforated model 82
Typical input receiver noise immunity characteristics
86
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.1a
Ground noise vs. # of simultaneously switching outputs
TTL level compatible CMOS receiver noise immunity behavior
Effects of ground noise feed-through from D.C. "ON" drivers
Effects of skewing CMOS output drivers . . . . . . . . .
Performance vs. switching noise limitations on output drivers
Underdam ped oscillatory ground noise behavior
Effects of damping resistor on the switching noise
CMOS output driver switching characteristics
88
89
90
93
94
95
96
101
7.1b
Voltage switching characteristics . . .
101
7.1c
7.2
Current switching characteristics . . .
Current controlled CMOS output driver
101
104
7.3
7.4
7.5
7.6a
Switching current controlled/unregulated CMOS output driver
A typical tri-statable (enable high) CMOS output driver
High-speed, tri-statable (enable low) CMOS output driver
Tri-state output driver voltage switching characteristics
105
106
107
109
7.6b
7.7
7.8
Tri-state output driver current switching characteristics
Driver delay-switching noise limitations . . . . . . .
Tri-statable, Controlled Slew Rate (CSR) output driver
109
110
111
7.9
CSR output driver voltage switching characteristics . .
113
7.10
8.1
8.2
8.3
CSR output driver current switching characteristics
Simultaneous switching noise simulator (SSNS) trial architecture
Multi-chip module chip-package Vss connections . . . .
Multi-chip module "Lv ss" inductance network model . .
113
119
121
122
8.4
8.5
9.1
SSN vs. MCM integration level (10-5 % Vss connections)
SSN vs. MCM integration level (20-10 % Vss connections)
Interconnect cross-section geometry . . . . . .
126
127
131
9.2
A coupled transmission line interconnect model
132
5.23
XIV
SSN OF CMOS DEVICES AND SYSTEMS
9.3
9.4
9.5
9.6
9.7
9.8
A signal conductor over a very wide Vss conductor . . .
Lumped circuit model including plane parasitic
Two conductor model for UA2DL inductance calculation
Chip-package Vss connection: "Complete Isolation" (CIS) model
Chip-package Vss connection: "Isolation" (IS) model . . . .
Chip-package Vss connection: "Plane Connected" (PC) model
134
135
137
141
142
143
9.9
9.10
SSN vs conductor spacing (thin film technology) . . . . . .
SSN vs conductor spacing (thick film technology)
145
146
9.11
9.12
Near-end crosstalk vs conductor spacing (thin film technology)
Near-end crosstalk vs conductor spacing (thick film technology)
147
148
9.13
9.14
9.15
9.16
Far-end crosstalk vs conductor spacing (thin film technology)
Far-end crosstalk vs conductor spacing (thick film technology)
Effects of package-pins placement ("Plane Connected")
SSN on the Vss plane (110 package-pin placement)
149
150
151
152
9.17
SSN on the Vss plane (101 package-pin placement) . .
153
9.18
9.19
SSN on the Vss plane (111 package-pin placement) . .
154
Far-end crosstalk for the "Isolation" and "Plane Connected" model 155
11.1
A typical BiCMOS output driver circuit
11.2
11.3
B.1
Substrate-Taps current spreading
Chip-Package interface parasitics with substrate-taps
General N-Coupled Transmission Lines
C.1
D.1
E.1
E.2a
Signal conductor over a reference plane
Dispersion relation . . . . . . . . .
Simple CMOS inverter circuit . . . .
CMOS inverter voltage switching characteristics
182
183
185
E.2b
CMOS inverter current switching characteristics
185
162
163
164
174
178
LIST OF TABLES
Page
Table
2.1
Scaling rules used for this analysis
10
2.2
First order device performance with scaling
10
2.3
Driver-interconnect performance with scaling (approximate
calculation of parasitics) . . . . . . . . . . . . . . .
13
2.4
Six-cell chain delays, ).=1
. . . . . . . . . . . . . .
17
3.1
Ground noise with and without negative feedback influence
29
4.1
Effect of perforations on
values . . . .
41
. . . . . . . . . . . . .
45
Lpl ane
and
Rpl ane
4.2
[Lij] inductance calculations
5.1
Touchstone-calculated lumped-element values and optimization
5.2
error
62
Comparison of calculated lumped-element values
67
5.3
Comparison of calculated lumped-element values
7.1
7.2
Tri-statable(enable high) CMOS output driver
High-speed, tri-statable (enable low) CMOS output driver
108
108
83
7.3
Performance-SSN comparison of conventional and
eSR output drivers . . . . . . . . . . . . .
114
8.1
MCM CMOS chip integration parameters
125
8.2
MCM integration: Driver and package parameters
125
9.1
Thick film interconnect lumped element values
140
9.2
Thin film interconnect lumped element value .
140
PREFACE
This monograph presents our recent research on Simultaneous Switching
Noise (SSN) and related issues for CMOS based systems. Although some SSN
related work was previously reported in the literature, it were mainly for Emitter
Coupled Logic (ECL) gates using Bipolar Junction Transistors (BJTs). This present
work covers in-depth analysis on estimating SSN and its impact for CMOS based
devices and systems. At present semiconductor industries are moving towards scaled
CMOS devices and reduced supply voltage. SSN together with coupled noise may
limit the packing density, and thereby the frequency of operation of packaged
systems. Our goal is to provide efficient and yet reliable methodologies and
algorithms to estimate the overall noise containment in single chip and multi-chip
package assemblies.
We hope that the techniques and results described in this book will be useful
as guides for design, package, and system engineers and academia working in this
area. Through this monograph, we hope that we have shown the necessity of
interactions that are essential between chip design, system design and package design
engineers to design and manufacture optimal packaged systems.
Work reported in this monograph was partially supported by the grant from
Semiconductor Research Corporation (SRC Contract No. 92-MP-086).
Ramesh Senthinathan
John L. Prince
ACKNOWLEDGMENTS
Our most sincere thanks to Prof. Andreas C. Cangellaris for his valuable
advice, comments and suggestions. We also thank Professors Olgierd Palusinski,
Michael Scheinfein, Douglas Hamilton, and Ronald Schrimpf for their help and
advice in many areas. Thanks to Semiconductor Research Corporation (SRC) for
their support for this work.
We thank many of our SRC member company mentors for their guidance
in steering this research work. The authors are thankful to many students and
faculty in the electrical and computer engineering department and Professors M.
Scadron, J. Leavitt, S. Koch and C. Falco in the physics and optical sciences
department at the University of Arizona for their constructive criticism and advice.
We thank Arun Vaidyanath for his help in formatting this monograph. Authors
acknowledge Srinivas Nimmagadda for his help on several SPICE simulations. We
thank our CEPR administrative advisor Kristin Kreamer for her help.
Ramesh Senthinathan is very thankful to many members from APDC
Motorola, especially his managers Mali Mahalingam, Kent Hansen and Barry
Johnson for their encouragement. Ramesh thanks his previous manager George
Katopis (IBM) for his encouragement. He is also thankful to IBM (Fishkill, New
York) and Intel (Chandler, Arizona) corporations for very valuable experience.
Thanks to IBM (Yorktown), Hestia (Sunnyvale), GTE (Phoenix), and Honeywell
(Minnesota) corporations for valuable summer intern experience.
At Kluwer Academic Publishers, we wish to acknowledge Ken Tennity
who encouraged us to undertake this project. A very special thanks to our wives
Logini and Martha for their patience, support, and encouragement.
SiInultaneous
Switching Noise of CMOS
Devices and SysteIns
CHAPTER 1
INTRODUCTION
1.1 BACKGROUND
Simultaneous Switching Noise (SSN) (also known as delta-I noise or
ground bounce) is a voltage glitch induced at the chip-package power distribution connections, due to an inductively induced voltage drop, when internal
gates and/or output drivers switch simultaneously. In reality, output driver
current drive capability (measure of delay to drive a specific capacitive load)
is much greater than the internal gates. This is because output drivers have
to drive output loading as well as package and board parasitics. This results
in the rate of change in output drivers switching current being much greater
than the rate of change in switching current in internal gates,
t; (di)
dt (outputs) > > f; (di)
dt (internal gates)
n
m
Here within the time interval To - 8t to To
+ 8t
(1.1 )
(where 8t is very small time)
there are n number of output drivers and m number of internal gates switching
from logic "1" to logic "0" or vice versa. Because of the condition described by
equation (1.1), SSN is often associated solely with the output drivers switching
simultaneously.
SSN OF CMOS DEVICES AND SYSTEMS
2
There are several inductances that are inherent in the power distribution network from the external power sources to the on-chip power connections. In order to calculate the SSN at the chip-package interface, it is
essential to calculate the associated inductances. Note that, the definition of
inductance is not a very precise concept unless one introduce a complicated
topological description. However, a simple definition of inductance rests on
the concept of flux linkage [1.1]. Self inductance L of a current carrying circuit
can be defined as the flux linkage per unit current [1.1],
L
= ~z
(1.2)
where e/; is the magnetic flux and i is the current. From Faraday's Law, induced
voltage due to the time rate of change in magnetic flux is given by [1.2]
V -
de/;
dt
.
(1.3)
From equations (1.2) and (1.3),
V
=
L di .
dt
(1.4)
This voltage drop appears in series with the ground and in series with power
connections to the voltage source outside the package. Thus the on-chip supply voltage is decreased, and the on-chip ground voltage is increased (the
ground voltage "bounces up") by this mechanism. A detailed discussion of
the origin and of the circuit effects of SSN (for CMOS circuits) is contained
in Chapter 3.
Note that, the inherent chip-package inductances and the rate of
change in the total switching current contributes to the switching noise. Due
to the complex chip-package power distribution connections in present state of
the art packaged systems, it is necessary to model these inductances that are
inherent in the power distribution connections using rigorous modeling tools.
This is because the accuracy of calculated SSN values very much depend on
the accuracy of the calculated inductance values. Since multiple current paths
exists from ideal power sources to the chip power rails (or buses), an inductance network is in order to study the impact of each path on the effective
inductance.
3
INTRODUCTION
Initial work on modeling , and calculating SSN for digital systems
were given by G. A. Katopis [1.3], A. J. Rainal [1.4], and E. E. Davidson [1.5].
However, in the past it was assumed that SSN is directly proportional to the
number of outputs switching simultaneously. For example, when n number of
outputs switch simultaneously, each with identical di/ dt, the SSN was wrongly
taken to be
di
Vn=nLeffdt
(1.5)
Here Lef f is the effective lumped inductance obtained from the inductance
network. In this work, a detailed method of calculating SSN for CMOS based
systems is given. This methodology includes the negative feedback effects
which are very important in calculating SSN. Previous models do not include
these effects, and in their methodology SSN is calculated using equation (1.5).
This work will present an important, accurate equation to replace equation
(1.5).
To study the performance and SSN for future CMOS based systems,
a detailed analysis of device and interconnect scaling was performed using rigorous parasitic extraction software tools. A systematic approach to modeling
the inductance network associated with the power distribution, and a method
of reducing this inductance network to an equivalent effective inductance is
explained. Some techniques to reduce SSN are explored in this work. A detailed methodology and a Simultaneous Switching Noise Simulator (SSNS)
based on a trial architecture were developed to calculate, and to minimize
SSN for CMOS based systems. In the next Section, each of the Chapters are
introduced, and their contents are summarized.
1.2 INTRODUCTION
In order to obtain high speed and high density, MOS devices are
scaled down. Scaling schemes such as constant field [CE], constant voltage
[CV] , and quasi-constant voltage [QCV] have been analyzed. To achieve high
interconnect density, interconnects are also constantly scaled down with device
scaling. Due to increase in system speed and density, designers are confronted
4
SSN OF CMOS DEVICES AND SYSTEMS
with several practical problems imposed by interconnect structures and electrical connections at the chip-package interface. In addition to the maximum
operating frequency degradation due to the interconnect parasitics, when the
output drivers switch they generate noise at the chip-package interface as well
as at the on-chip VDD /Vss buses.
As the devices are scaled down in CMOS device packaged systems,
output driver delay to drive off-chip interconnects decreases. However the decrease in delays does not decrease linearly with device scaling. When we scale
down the channel lengths (Lejf) into sub-micron regions (Lejf
< IJ..lm) , the
dominant part of the overall delays in a system are due to off-chip interconnects. It is important to calculate interconnect parasitics with high accuracy
in order to calculate the maximum system operating frequency accurately.
In Chapter 2 the performance of scaled CMOS drivers together with off-chip
interconnect is calculated using the constant voltage device scaling scheme.
Results were compared using both approximate closed-form equations, and
more detailed VA software tools.
In present high-speed chips, the output driver is a major contributor
to the pin-to-pin delays because of capacitive output loading as well as package
and board parasitics. To obtain high speed from these output drivers, often
the drive current capabilities are increased by increasing the output driver circuit channel width. The increase in current drive capability may induce large
power/ground noise caused by "through-current" transients [1.6], due to many
outputs switching simultaneously. Since the input circuits are connected to
the same power/ground bus, power/ground noise must be controlled to avoid
any false switching. Often, internal power/ground buses are separated from
the external (I/O driver circuit) power/ground buses. However, these internal
and external buses are connected to VDD/VSS planes in multilayer packages.
Thus electrical decoupling is not assured. Detailed methods of calculating simultaneous switching noise (SSN), including the negative feedback influence
is explained in Chapter 3. For a given design, knowing the maximum tolerable noise levels, an algorithm is described which calculates the minimum
number of VDD /Vss bond-pad and package-pin connections required to avoid
any false switching due to SSN.
5
INTRODUCTION
Often VDD /Vss connections from a chip boundary are multiple connections (wire bonding, tape-automated-bonding, controlled collapse connection (C4)) to VDD/VSS planes. Package pins are connected to VDD/VSS
planes, and exact placements of these pins depend on the package type. For
example, Pin-Grid-Array (PGA) packages have pins placed in an array configuration, quad-flat-packs (QFP) have pins in all four perimeters, and dual-inline packages (DIP) have pins on two opposite long perimeters. Due to these
complicated connections, defining a single lumped resistance, inductance, and
capacitance from an on-chip VDD/VSS bus to the tip of a VDD/VS S package
pin is difficult. Especially, defining an equivalent effective inductance requires
a very good understanding of the current path in the plane. If any perforations are present in VDD /Vss planes, the current path will generally be
affected and this gives rise to increases in the effective inductance of these
VDD /Vss planes. In Chapter 4 a method of modeling effective inductance
including the effects of current distribution on VDD /Vss planes is analyzed.
The UA software tool called UALG RL [1.7] was used to calculate the plane
effective inductance. An inductance network is developed using superposition
theory to ascertain the impact of each of the package pin locations on the total effective inductance. Guidelines on VDD /Vss package-pin placements are
given to minimize SSN, and to decouple output driver SSN from input and
internal circuits. The methodology explained in Chapter 4 is also applicable
to perforated VDD/VSS (reference) planes.
Discontinuities to an ideal transmission line can degrade the signal
integrity of an output driver transmitted signal. When the supply voltages
are scaled down from 5 volts to 3.3 volts, as is currently happening, the noise
margin of CMOS circuits decrease.
In Chapter 5 signal propagation over
perforated reference planes is investigated. The perforations cause impedance
discontinuities which degrades signal quality. To avoid false switching, it is
essential to understand and estimate this noise within engineering accuracy.
A scaled-up model and a periodically perforated FR-4 card structure were
fabricated for this study [1.8]. Both 2-D, 3-D, and S-parameter modeling
tools were used to extract additional parasitics associated with perforations
[1. 9]. These parasitics (D..L, D..C) are used in conjunction with transmission
SSN OF CMOS DEVICES AND SYSTEMS
6
line models to compensate for additional delays caused by return current
discontinuity on the reference plane due to perforations. Simulations were
performed using a circuit simulator called ASTAP [1.10]. The simulation
results were compared with TDR (Time Domain Reflectometry) measured
values.
Due to size and/or cost requirements, a single chip or a multi-chip assembly system can be I/O pad-pin limited, i.e. the number of bond-pads and
package-pins may beat the maximum permitted. For such an I/O pad-pin limited system, the designer may be confronted with the problem of minimizing
the effective SSN by design methods other than simply decreasing inductance
by manipulating pads and pins. To use some other design techniques, one
needs to understand the noise immunity characteristics of the circuits that are
connected to noisy VDD/VSS on-chip buses or noisy VDD/VSS package planes.
Noise feed through mechanisms at the chip-package interface are explained in
Chapter 6. The characteristics of CMOS input receiver circuit noise immunity in a system are analyzed. Techniques of damping and skewing CMOS
output switching waveforms, to reduce SSN are explained and demonstrated.
Trade-offs and guidelines to use such design techniques to reduce effective SSN
are explained in Chapter 6. In Chapter 7, application specific circuit design
techniques to reduce SSN are explained.
As explained earlier, two methods of reducing SSN are used in practice. One method is to use circuit design techniques, and the other method
is to reduce the effective inductance (Lej j) seen by the output driver on
VDD /Vss paths. A trial architecture for a system called UASSNS (University
of Arizona Simultaneous Switching Noise Simulator) was developed to model
and verify SSN using both methods. This tool is developed to guide a system designer in calculating SSN at pre-design stages, and to cross-check for
possible false switching errors. This tool is also intended for a use by packaging engineer to minimize Lei I using optimal package-pin placement. The
UASSNS architecture is open, to allow adding any future modules (methods) to reduce SSN. Simultaneous switching noise simulator architecture is
explained in Chapter 8.
In high-speed, high-density digital systems, due to SSN, reference
INTRODUCTION
7
planes can be noisy instead of being at zero or constant D. C. voltage. In
Chapter 9, limitations in using conventional coupled transmission line simulators to model signal propagation over a noisy reference plane are explained.
A new model is proposed to analyze signal propagation characteristics over a
noisy reference plane including the impact on package-pin placement. Conclusions and future work on SSN modeling are discussed in Chapters 10 and
11.
CHAPTER 2
PACKAGED/SCALED CMOS DEVICES
2.1 INTRODUCTION
In order to obtain high speed and high density, MOS devices are
scaled down. Scaling schemes such as constant field [CE], constant voltage
[CV], and quasi-constant voltage [QCV] have been analyzed [2.1]'[2.2]. These
schemes are shown in Table 2.1. Note that dimensions refer to all physical dimensions (except junction depths Xj and oxide thicknesses tax), doping
refers to the channel doping and voltage refers to the voltage applied to the
device. All the voltages are with reference to substrate which is grounded.
The following mechanisms are usually identified as the controlling performance and reliability factors in scaled circuits [2.3]: 1) velocity saturation, 2)
source/ drain parasitic resistance, 3) finite thickness ofthe inversion layer, and
4) Hot electron limitations. In this work, the effect of source/ drain resistance,
contact resistance and global interconnects (cell to cell on-chip interconnects)
on CMOS device performance under constant-voltage scaling is analyzed. In
practice, MOS devices do not perform in the simple manner as predicted
by first-order scaling theory (see first order scaling theory [2.4]'[2.5]) which
neglects parasitics associated with the interconnects and package interface.
These differences from first order scaling behavior increase as the channel
lengths are reduced (scaled system performance is mainly dominated by the
10
SSN OF CMOS DEVICES AND SYSTEMS
interconnects and package parasitics). In Table 2.2, the behavior of first order device performance parameters with scaling, but without the effects of
parasitics, are shown.
Table 2.1. Scaling rules used for the analysis.
Scaling Rule
[CE]
[CV]
IQQYl
Dimensions
1/0:
1/0:
1/0:
Gate Oxide
Doping
1/0:
l/fo
1/0:
Voltage
0:
0: 2
1/0:
1
0: 2
l/fo
Table 2.2. First order device performance with scaling.
Device Parameters
[CE]
[CV]
Current
Current Density
Power Dissipation
0:- 1
fo
0:
0: 3 / 2
0:- 2
Power Dissipation Density
Delay [minimum]
Power-Delay Product
Frequency Dependent Power
IQQYl
1
0: 2
fo
0:- 1 / 2
0: 5 / 2
0: 3 / 2
0:- 1
0:- 2
0:- 3 / 2
0:- 3
0:- 3 / 2
0:- 2
0:- 1
0: 5 / 2
0: 3 / 2
1
2.2 INTERCONNECT SCALING
In Figure 2.1, the typical on-chip interconnect structure is shown.
In this work, it is assumed that the operating frequency and the substrate
conductivity are such that the Si-Si0 2 interface behaves as a perfect ground
plane [2.6]. All the interconnect geometries are scaled by 0: (0: > 1). Oxide
PACKAGED/SCALED CMOS DEVICES
thickness (toa;) is scaled by
1/...;c;. for
11
constant-voltage scaling. The relative
dielectric constant 3.5 is used for Si0 2 . Actual on-chip interconnect structures
may have other dielectrics (e.g.,polyimide) covering metal-2, metal-l and poly
interconnects. In this work, a simple microstrip-like interconnect structure is
chosen to demonstrate the trends. Recently, software tools have been developed which are very useful in extracting the parasitics for multi-dielectric,
multi-conductor interconnect structures including three dimensional geometries [2.7]'[2.8]. As the geometries are scaled down, accurate parasitic extraction tools are required to give meaningful system timing estimations. Detailed
analysis of coupled microstrip-like structures with multi-dielectric media are
given in [2.9].
I
I
fOX
1
;:k CL
I
I
Cr 2 =3.5
~ CL
I
I
Si0 2
///7//7/7/77//7//77//7777~/7///77777
Si
Figure 2.1 Typical on-chip Si - Si0 2 interconnect structure.
12
SSN OF CMOS DEVICES AND SYSTEMS
Historical and future predicted behavior of scaling for integrated circuits shows that as minimum dimensions are scaled down, the maximum chip
size is scaled up. For example, for DRAMs (Dynamic Random Access Memory) each generation increases memory size by x 4, and takes three years.
In this time period a=1.43, and chip area increases by >.=1.6 [2.9]. When
the minimum device size decreases and the die area of the chip increases, the
maximum cell to cell interconnect length generally increases. To first order,
using statistics from the past chips, a simple empirical relationship is found
between the chip area and the maximum interconnect length [2.5]:
L
,. . ., vchip area
max""'"
2
.
(2.1)
Thus as the devices are scaled down by a, the maximum global interconnect
length is scaled up independently by>., where>. is greater than unity for
leading edge chips. Even though there may be a direct relationship between a
and >., different technologies may have different dependency. In this work, all
the interconnect lengths are assumed to be scaled separately from the device
scaling. For approximate parasitic calculations, the following equations are
used:
CL
Cc
RL
W Lmax
tox
(2.2)
t Lmax
Ls
(2.3)
Lmax
,
= p Wt
(2.4)
fr2
fr2
where CL is the line capacitance to substrate, Cc is the interline (coupling)
capacitance and RL is the line resistance. For exact values of CL, Cc, and
RL, we have used a software tool based on the Method of Moments [2.7]
technique. Results from this parasitic extraction tool have been compared
with measurements and the results agree very well. The following closed-form
equation is used to calculate the diffusion+contact resistance Rc [2.11],
(2.5)
13
PACKAGED/SCALED CMOS DEVICES
Here Rs is the diffusion sheet resistance, Pc is the specific contact resistivity,
and Wand L are the contact rectangular dimensions.
Using the residue
expansion theorem for coth(Z),
coth( z)
= -z1 + E
00
[±/¥. + ...J
n=l
Rc
~ v'~Pc
- + -n11'1 J ,
z - n11'
[1
ex
~2
(2.6)
Experiments have demonstrated [2.12] that diffusion+contact resistance exhibits an exponential behavior with a for small contact windows (:::; 1
!lm) instead of an inverse square behavior with a (> 1 !lm). In Table 2.3, the
behavior of first order device performance parameters with scaling, including
the approximate effects of parasitics, are shown. From [2.11]' the parame-
ter a in Table 2.3 is 0.3 for N+ / Al and P+ / Al contacts, and is used in the
diffusion+contact resistance calculation for smaller geometries (Leff :::; Ipm).
Table 2.3. Driver-interconnect performance with scaling.
(Using approximate calculation of parasitics).
[CE]
ICV]
lQQYl
Line Resistance
Aa 2
Aa 2
Line Capacitance
A
Aa 2
Aa- 1 / 2
Interline Capacitance
A
Driver-Interconnect Parameters
A
A
A
A2 a 2
;..2 a 3/2
A2 a 2
Aa
1
Aa 3 / 2
a- 1j2
Aa 2
a- 1j2
Leff >1 pm
a2
a2
a2
Leff :::;1 pm
eaa
e aa
e aa
Time Constant
Line Voltage Drop
Channel Resistance
Contact+ Diffusion Resistance
2.3 DELAYS WITH DRIVER/INTERCONNECT SCALING
To demonstrate the variation of performance with scaling, a simple
inverter (for two micron L eff ; Wp = 28, WN = 15) as shown in Figure 2.2 was
SSN OF CMOS DEVICES AND SYSTEMS
14
used. The inverter is simulated (using SPICE) for one and two micron existing
technology parameters with 1 ns inverter rise/fall times. SPICE parameters
typical of 1J.lm and 2J.lm
Lej j
devices in the industry were used. Typical one
fanout interconnect and load capacitances were selected (CL=0.41 fF / J.lm and
CLOAD=3.8 fF for 2J.lm technology). Constant-voltage scaling scheme and the
following equations are used to calculate the average (tplh +tphl) /2 delays for
scaled geometries:
= (Rsp + RPchannel + RDP + RL) (CL + Cc + CLOAD),
tphl = (RSN + RNchannel + RDN + RL) (CL + Cc + CLOAD)
tplh
and (2.7)
.
(2.8)
WP/L
Figure 2.2 A CMOS Inverter with device/interconnect parasitics.
The average delays are plotted in Figure 2.3 for the following cases: 1) without
interconnect parasitics (device with load only), 2) using approximate interconnect parasitics and 3) using the exact interconnect parasitics. To show the
15
PACKAGED/SCALED CMOS DEVICES
performance dependency with interconnect parasitics, the maximum global
interconnect length is fixed (A = 1). As the devices are scaled down, the interconnect parasitics dominate in the delay calculations. Note that in Figure
2.3, the differences are only for a single inverter and these errors accumulate
for pin-to-pin timings in a system.
1.0
A= I
0.8
I'.
I'.
\
-l
06
-l
\ \
\
Vi
,.,
"
\\ \ .
\
'--v-'
S
- - Exoet Line Porosities
I, I,
,--A-,
:r:
+C\J
:r:
- - - Without Line Porosities
_. -. Approximote Line Porosities
0.4
'.
\
"
,,'.'. "-
" , ". '.
" ', ..........
............
E
Q)
0
02
.........
_-.- '-'- -'-'-'-
..........................
--- --- ----
-'-
0.0
Scaling Factor, a I
2
Leff(jJ-m) 2
4
0.5
6
8
10
0.25
-
----
12
14
0.17
16
0.125
Figure 2.3 Delays with [CV] scaling using exact, approximate, and no interconnect parasitics values.
To show the effect of estimating parasitics, the approximate interconnect capacitance normalized by the exact capacitance is plotted in Figure 2.4.
Also the diffusion+contact resistance normalized by the channel resistance is
plotted in Figure 2.4. It is clear from Figure 2.4 that for large
0:
accurate
parasitic extraction tools are essential to predict delays.
To study the chip level performance, a six-cell chain structure was
SSN OF CMOS DEVICES AND SYSTEMS
16
chosen. The reason for selecting a six-cell chain is because the input ramp
stabilizes after two to three stages, and using more than six cells is computationally expensive.
1.0
..,....
Q;
E
c
~
Approx. (C l +C c )
al 0.5
Exact(Cl+C C )
.~
c
E
....
o
Z
O.O~~~~----~----~------~-----L----~------~----~
Scaling Factor, a
Leff(fLm) 2
2
4
0.5
6
8
0.25
10
12
14
0.17
16
0.125
Figure 2.4 Normalized capacitance and resistance with [CV] scaling.
Four different gates were selected: 1) Nominal drive inverter, 2) nominal drive
2 input NAND, 3) nominal drive 2 input NOR, and 4) high drive inverter. In
general, these gates form the basis for large cells. Typically, nominal gates
drive one or two fanouts while high drive gates drive more than three fanouts.
These gates were simulated (using SPICE) for one and two micron CMOS
technologies using both approximate and exact interconnect parasitics. The
average (tplh +tphl)/2 delays are shown in Table 2.4, using global interconnect
length scaling ).=1.
17
PACKAGED/SCALED CMOS DEVICES
Table 2.4. Six-cell chain delays, ..\=1.
Cell Name
Cr (pf)
INV [nominal)
2 /Jm delays (ns)
Approx.
Exact
1 /Jm delays (ns)
Approx.
Exact
11.2
11.8
7.5
8.9
15.8
16.5
12.7
14.5
15.2
16.0
12.6
14.6
10.8
11.9
6.8
9.2
CLOAD=0.34 pf
NOR 2-input
CLOAD=0.34 pf
NAND 2-input
C LOA D=0.34 pf
INV [high-drive)
CLOAD=2.0 pf
As expected, the error in delay caused by using the approximate interconnect effects increases as we move from two micron to one micron technology. Note hat high drive circuits have significant differences over nominal
drive circuits. This is because high drive circuits have large current drive
capability with low channel resistance, but the contact+diffusion resistance
becomes relatively more important. Lesser differences were found for NAND
and NOR circuits, because these gates are highly resistive. This demonstrates
that for highly loaded interconnects driven by high drive circuits (e.g., clock
drivers), delays will be dominated very much by the parasitics, compared to
the nominal and low drive circuits in scaled devices. Often at VLSI level, average pin-to-pin number of gates are in the order of 10 2
-
10 3 . If approximate
interconnect parasitics were used, timing errors would accumulate resulting
in false chip timing for scaled device-interconnects. Note that ..\ >1 will cause
even larger effects in predicted delays
2.4 SUMMARY
An investigation into the behavior of delays and noise of CMOS devices with constant-voltage scaling was presented. It appears that interconnects playa major role in the delay calculations for small geometry devices.
18
SSN OF CMOS DEVICES AND SYSTEMS
As a result, accurate modeling of interconnect parasitics is essential for future
VLSI chips. Thus detailed modeling of device and also package interconnect
parasitics are required to predict the performance of the packaged small geometry CMOS devices/systems.
CHAPTER 3
METHODS OF CALCULATING
SIMULTANEOUS SWITCHING NOISE
3.1 INTRODUCTION
In present high-speed chips, the output driver is a major contributor
to the pin-to-pin delays because of output loading as well as package and
board parasitics. To get a good speed on these output drivers, often the
drive current capabilities are incre~~ed by increasing the channel width of
the output driver circuits. The increase in current drive capability induces
large power/ground noise due to outputs switching simultaneously. Since the
inputs and/or internal logic (if not separated by internal VDD/VSS buses) are
connected to the same VDD/VSS bus, power/ground noise must be controlled
to avoid any false switching.
Initial work on estimating Simultaneous Switching Noise (SSN) was
done by A. J. Rainal [3.1]' G. A. Katopis [3.2], and E. E. Davidson [3.3].
However in the past it was assumed that SSN was directly proportional to
the number of outputs switching simultaneously. Recent studies indicate that
CMOS circuits exhibit sub-linear behavior (due to negative feedback influence) of power/ground noise as a function of the number of outputs switching
simultaneously [3.4],[3.5]. In this chapter detailed electrical model of a typical
chip-package interface is explained. Several closed-form equations including
20
SSN OF CMOS DEVICES AND SYSTEMS
the negative feedback influence are derived to calculate SSN as well as the
minimum number of bond-pad/package-pin connections needed for a given
design [3.6].
Often in the literature SSN is also referenced to "ground bounce".
The reason ground noise is more crucial compared to the power noise is that
TTL-compatible input circuits have their switching point around 1.2 to 1.6
volts. Because of this, for a 5-V supply, more switching noise can be tolerated
on the power rails. In this work, ground noise and ground pad-pin calculations
are explained. Note that power noise and power pad-pin calculations are
similar.
A typical multilayer package parasitics with internal/external Vss
bus connection to the package ground pin is shown in Figure 3.1.
Internal
Logic
Celis
Output
Driver'
Celi
L I • RI,C I ' Bonding Porosities
L 2 • R2 • C2 ' Package Pin Porosities
Lp. Rp. Cp , Vss Plane Porosities
Figure 3.1 Typical Multilayer Chip-Package Interface Parasitics.
CALCULATING SIMULTANEOUS SWITCHING NOISE
Note that similar connections exist from
VDD
21
bus to the package power pin. A
lumped package parasitic electrical model of a CMOS output driver is shown
in Figure 3.2. The following lumped package parasitics values (Rvss=1 mn,
Lvss=5 nH, Cvss=3 pF) were selected from commonly used 160 to 256 I/O
pin ceramic pin-grid-array (PGA) packages for this work [3.7).
RVDD
LVDD
VIN C > - - - - - - - - t
RSIG
LSIG
~_~~~~~~~~VOUT
VDD
T
CS1G
LVSS
TClOAD
RVSS
Figure 3.2 CMOS Output Driver With Lumped Package Parasitics.
Note that Cvss=3 pF also includes Vss bond-pad area capacitance. In this
work, it is assumed that internal switching current is small compared to the
output driver switching current. However, as the drivers are scaled down
and the number of gates on a chip increases, the internal switching current
SSN OF CMOS DEVICES AND SYSTEMS
22
becomes comparable to the output driver switching current and can no longer
be ignored in the noise calculations. A typical CMOS output driver switching
characteristics are shown in Figure 3.3.
t rImA)
VOUT
(V)
v,{
I
I
I
I
I
I
I
I
I
~
S5
\
"
I
I
I
V1N(V)
Figure 3.3 Typical CMOS Output Driver Switching Characteristics.
23
CALCULATING SIMULTANEOUS SWITCHING NOISE
Input receiver/output driver circuits, and/or internal logic false switching
due to VDD/VS S on-chip bus fluctuations are shown in Figure 3.4. In the
following, the behavior of SSN for sub-micron channel length (Lei! < IJ-lm)
output drivers are explained using constant voltage scaling scheme and negative feedback effects.
v
ON
i
Vss
Figure 3.4 On-Chip VDD/VSS Bus, and Noise Feed-Through Mechanisms.
3.2 THEORY AND MODELING
Simultaneous switching for the worst case analysis is modeled. A level
1 SPICE-type device model with VTN
= IVTPi
is assumed.
SSN OF CMOS DEVICES AND SYSTEMS
24
It is assumed that the maximum worst case switching current is the
saturation current.
In practice, the switching current is smaller than the
saturation current. If n is the number of similar output drivers switching
together, the maximum current Ii sourced to ground by each driver is
Ii
J{
= "2
[Vin - \It - Vn]
2
(3.1)
where Vn is the ground noise produced by n output drivers switching simultaneously, \It is the threshold voltage, and
J{
=
J-tn Cox
r for the N-channel
output driver device. Note that, from (3.1), the current through each bond
pad is a non-linear function of ground noise. The maximum total current (It)
sourced to ground by n identical output drivers switching simultaneously is:
(3.2)
From Figure 3.2, ignoring the effect of resistance in the ground noise calculations (resistance is very small,
;:::;J
O.Ht), the ground noise appearing on the
chip ground bus, which is connected to the source of the N-channel transistor
IS:
=
Vn
LV55
dIt
dt .
(3.3)
Here Lv 55 = ;' is the total effective lumped inductance from bonding wires,
package plane and package pins, where one-to-one correspondence between
chip-plane bonds and package pins, with inductance L1 for each equal path
has been assumed. Also, let us assume the total current through the ground
bond pad has a triangular waveform for noise calculations. This would be the
approximate case, for example, if the transient switching current was all due
to CMOS driver "through-current". Then Vn is
v.
n
;:::;J
L1 It
p T'
(3.4)
where T is the time taken for the switching current spike to travel from zero to
its maximum peak value It. Note that T depends on whether the switching
current is controlled by the through-current (overlap current) or discharging current. T can be calculated from SPICE or UANTL [3.8], or obtained
CALCULATING SIMULTANEOUS SWITCHING NOISE
25
from experiment. Studies have shown that T remains almost constant with
n (number of outputs switching simultaneously) for commonly used package
parasitics and loads [3.9]. From equations (3.2) and (3.4), ground voltage as
a function of number of simultaneously switching signals is described by
(3.5)
where
Vk
= "\lin -
vt.
Often it is assumed that the ground noise is proportional to the number of output drivers switching simultaneously. It is clear from equation (3.5)
that the ground noise is not a linear function with respect to the number of
simultaneously switching CMOS outputs. This is because negative feedback
reduces the switching current when the ground noise increases. From equation
(3.5),
1
+
2 Vi L1 n
f{]
pT'
k
(3.5a)
Note that equation (3.5a) will always have a valid solution as long as the
output drivers are not in the cut-off region, and as n approaches infinity
will approach Vk . From equations (3.4),(3.5), a very useful
(~)
Vn
ratio, with
and without the effect of negative feedback, for a given output driver design
and package parasitics, can be calculated:
p
n
where
(Vk - V n )2
2 Vn
[ P]
;
Ll
f{
(Vk - Vn
T
w.o.feedback
Vk 2
=
Vk2
2
Vn
)2
[P]
;
Llf{
-r .
w.o·feedback
(3.6)
(3.6a)
It is clear from equation (3.6), either decreasing p or increasing n , and vice
versa, has similar trend in noise calculations. This is sensible because, increasing n or decreasing p both result in non-linear increase in total switching
current. That is, for a fixed number of outputs switching (n fixed) if one
increases or decreases the number of VDD /Vss pad-pin connections, negative
26
SSN OF CMOS DEVICES AND SYSTEMS
feedback influence must be used to calculate the new corresponding switching
nOlse.
In practice, more than one type of CMOS output driver may share
the same on-chip Vss bus. For example, consider n total number of CMOS
output drivers switching simultaneously with several different types (different
drive strengths) and switching speeds. Assuming that each output driver
is switching symmetrically around the point To (any arbitrary time) with
K
= Ki
and T
Vk
+
= Ti ,
1
p
[
£1 "'':' !S.i. 1-
(3.7)
L...,=1 Ti
and
=
(Vk - Vn )2 L1
(3.8)
2 Vn
Note, in the above ground noise calculations it is assumed that the current
through the capacitor (Cv ss) is very small compared to the total switching
p
2:7=1 t
current, and therefore can be ignored. This assumption must be checked for
consistency. Including the effect of current through the capacitor, the current
through Lv ss is
It(Lvss) = It
and
~~
Vn
[It -
C Vn
(3.9)
-T-
2"
C [n
1
(3.10)
Here it is presumed that Vn is actually a triangular waveform with full-width
f.
of T, and thus risetime of
This sort of sinusoid-like waveform is observed
experimentally for Vn , instead of a square pulse. From equations (3.2) and
(3.10) for n similar output drivers (including the current through the capacitor) switching noise can be described by
Vn 2
-
Vn[2 Vk
+ n2K(PL~ + 2~)] +
Vk 2
=
O.
(3.11)
From (3.11), current through capacitor Cvss is negligible only if
Cvss
«
T2 p
2 £1
T2
2 Lvss
(3.12)
CALCULATING SIMULTANEOUS SWITCHING NOISE
T = 1 ns, for 10 percent of the total
switching current to go through the capacitor requires Cvss ~ 50 pF. However when the rise times become smaller, the current through the capacitor
will increase and one has to take into account this effect in noise calculations.
For example, when L1
= 5 nH,
27
p
= 5,
3.3 GROUND NOISE AND Vss PAD-PIN
CONNECTION CALCULATION
Modeling and simulation of simultaneous switching was done using
both SPICE simulation and the negative feedback equations given in Section
II. Results from the two techniques are very close for a large number of output
drivers switching simultaneously. SPICE simulations are computationally expensive. It is important to accurately pre-estimate (before selecting a package
for a given chip design) the number of power and ground pad-pin connections
needed. This is because improper pre-estimation of power and ground padpin connections may force the design to demand a larger I/O pin count (due
to the increase VDD /Vss pad-pin connections requirement from the switching
noise) package finally. Note bonding, package plane, and/or pin inductance
for each path can be different due to their placements (due to the mutual
coupling). A recently developed package plane parasitic extractor (UALGRL
[3.10]) can be used to calculate the frequency independent plane parasitics for
different sink/source placements in power and ground planes.
The maximum allowable ground noise (Vmax ) for a given system design depends on the process and the geometry. Note that maximum tolerable
noise (maximum noise immunity of TTL compatible input receivers) not only
depends on the switching noise pulse amplitude but also on its width [3.9]. For
worst case, maximum allowable noise of 400 m V amplitude with a very small
pulse width was selected in this work. This is because more than 400 m V
ground noise may corrupt the output level of receiver TTL circuits. Knowing
p (# of pad-pin connections) and Vmax , substituting Vn
= Vmax
in equation
(3.7), one can calculate n (# of simultaneous switching outputs). Since n
must be an integer, one needs to round-off the answer to the nearest smaller
28
SSN OF CMOS DEVICES AND SYSTEMS
value integer. Now for this integer n, corresponding ground noise (Vn ) can be
calculated using (3.7) again. Similarly, knowing nand Vmax one can calculate
how many pad-pin connections (p) are required to control the ground noise
within the maximum allowable noise. In this case, p has to be round-off to the
nearest larger value integer. For this integer p, corresponding ground noise
(Vn) can be calculated. Note, equation (3.7) is only valid if all the output
drivers are switching symmetrically around a single point in time To. Note
that for skewed output drivers, one cannot use this simple approach, instead
an iteration scheme is required to calculate the switching noise.
3.4 RESULTS
( I Ground Pad-Pin)
PLI05· 12mA
PLI03· 8mA
PLI03.2mA
4
PLI05
~
o
>
or
'"o
PLI03
3
PLIO
Z
't:l
§
...
o
2
(!)
'=SPICE Simulations
2
4
6
8
10
12
14
16
Number of Outputs Simultaneous Switchings
Figure 3.5 Ground Noise vs. Number of Simultaneous Switching Drivers.
CALCULATING SIMULTANEOUS SWITCHING NOISE
29
In Figure 3.5, ground noise is plotted as a function of the number of
simultaneously switching outputs for three different types of CMOS output
drivers. The drive capabilities of these drivers are: 1) PLIO (3.2 rnA D.C. sink
with Vo/=O.4v), 2) PLI03 (8.0 rnA D.C. sink with Vo/=O.4v), and, 3) PLI05
(12.0 rnA D.C. sink with Vo/=O.4v). It is clear that the ground noise is a
sub-linear function of the number output drivers simultaneously switching.
Table 3.1 shows the percentage error if linear assumption is used
instead of the negative feedback equations. Note that, even for smaller drive
strength CMOS output drivers (e.g. PLIO: 3.2 rnA), four outputs switching
simultaneously produces more than 50 percent error in ground noise value if
the conventional (linear assumption) method is used.
Table 3.1 Ground noise with and without negative feedback influence.
CMOS Output
Driver
TYI~e
PLIO
No. of Simultaneous Switching Percentage Error Caused by
CMOS Out2ut Drivers
1
Neglecting Negative Feedback
2.2
"
2
8.3
"
"
4
52.9
8
1
116.6
PLI03
4.6
"
2
29.7
"
"
4
82.9
8
181.1
1
9.8
2
4
30.2
92.5
8
220.0
PLI05
"
"
"
In Figure 3.6, ground noise as a function of the number of ground pad-pin
connections (p) is shown for sixteen output drivers simultaneously switching.
As expected, when we increase p, ground noise does not decrease linearly. This
is because when p increases, the inductance ~' decreases, but the switching
SSN OF CMOS DEVICES AND SYSTEMS
30
current through each pad-pin connection increases, which tends to increase
Vn .
(16 PLIO 5 Output Pads Simultaneous Switching)
• = SPI CE Simutations
4.0
UI
~
.v
3.0
UI
o
Z
'0
c:
2 .0
...
::J
o
<.!>
PLI03
1.0
PLIO
2
4
6
8
10
Number of Ground Pads-Pins
12
Figure 3.6 Ground Noise vs. Number of Ground Pad-Pin Connections.
3.5 BEHAVIOR OF SIMULTANEOUS SWITCHING NOISE
WITH SCALING
To show the trends in simultaneous switching noise for scaled CMOS
outputs, constant-voltage [CV] scaling scheme was used to calculate the switching current. For this, a is the scaling factor (a > 1). Dimensions (except
junction depth and oxide thickness) are scaled down by ~. Gate oxide thick-
CALCULATING SIMULTANEOUS SWITCHING NOISE
ness is scaled down by
by
Cl:'2.
31
Ja. Doping refers to channel doping and is scaled up
Voltage refers to the applied voltage to the device and remains con-
stant. Note that all voltages are with reference to substrate which is grounded.
Under the above [CV] scaling scheme, the drive current capability of CMOS
output driver increases by
va [3.11].
In Figure 3.7, the ground noise is plotted as a function of channel
length for constant-voltage scaling.
2.5
M = # of Simultaneous Switching Drivers
N =# of Ground Pads and Pins
2.0.
>
1.5
Q)
'"
z
'0
>'"'"
1.0.
",/
--- -------- -- --
W4
-,./
\'11::\6, - _ -
,./
./
/
/
/
./'
_
/
/
I
.// '"
............
/
/
/
/
I
///
\'11=\6, 1'1 =8_ - - -
0..5
M=8,N=8
0.0. L -_ _.l.-_ _-L_ _--L_ _---lL-_ _..L.-_ _- ' -_ _- ' -_ _ __
0..875
0..75
0..625
0..5
0..375
0..25
0..125
LeI! (jLm)
Figure 3.7 Simultaneous Switching Noise as a Function of [CV] Scaling.
For demonstration a standard output driver (for 1 micron Leff: Wp
WN
= 160) is selected.
= 250,
This output driver was designed to switch a 100 pfload
32
SSN OF CMOS DEVICES AND SYSTEMS
in 6 ns. The total (bonding+plane+pin) parasitics are, L=5.5 nR, R=2 0,
and C=12 pF. For noise calculations (Leff
< 1 pm), the constant-voltage
scaling scheme and negative feedback noise equations are used. For the above
one micron output driver, eight and sixteen output drivers simultaneously
switching through four and eight ground pad-pin connections are simulated
using SPICE with 1 ns rise/fall times. This corresponds to a FF-OO and FFFF0000 switching case in a typical eight and sixteen bit data/address bus. As
expected, the noise increases when the output driver devices are scaled down.
It is clear from Figure 3.7 that the noise increases rapidly when Leff
< 0.5 pm.
This is because in going from one micron to smaller geometries, the scaling
factor increases rapidly, thereby causing the switching current to increase
rapidly.
3.6 SUMMARY
An investigation into the calculation of simultaneous switching noise
for packaged CMOS devices was presented. It was found that due to negative
feedback simultaneous switching noise exhibits a sub-linear behavior with the
number of outputs switching simultaneously. As a result, when calculating
the switching noise, negative feedback influence must be incorporated in the
equations. This effect must also be account for in the power and ground padpin connections calculations. The trends in output driver switching noise with
constant-voltage [CV) device scaling were explained.
CHAPTER 4
POWER DISTRIBUTION INDUCTANCE
MODELING
4.1 INTRODUCTION
Complex high density VLSI chips (i.e. mIcroprocessors, mIcro controllers, and digital signal processors) require packages with VDD /Vss plane(s)
and a large number (> 100) of I/O pins for controlled signal impedance and
external communications. However, in typical single layer packages, conductors are metalleadframe connected to the die (chip) with bond wires. Note
that single metal layer package does not contain a separate VDD /Vss reference
planes, and the current path is confined to the metal lines and bond wires.
Typical single layer packages are; 1) PDIP /CDIP (Plastic/Ceramic Dual-InLine Package), PLCC (Plastic Leadless Chip Carrieer, 3) PQFP (Plastic Quad
Flat Pack), and 4) CerQUAD (Ceramic Quad Flat Pack). In multi-layer packages, connections from the die to the external world may be through signal
traces, bond wires, metal planes, vias, and pins. Vias are used to connect
signals from plane-to-plane. Due to these complex VDD /Vss connections at
the chip-package interface, modeling "Lefj" (to a single lumped inductance)
involves a detailed understanding of the current path through these connections. A software tool describing the current distribution on the VDD/VS S
planes is essential to model the reference plane inductance, and thereby the
SSN OF CMOS DEVICES AND SYSTEMS
34
effective inductance "Lef /' .
In this Chapter, a method of modeling VDD/VSS plane inductance is
presented. In this work, it is assumed that there is only one Vss plane, and
package pins connect this plane to the ideal ground. Source points (current
entering points to the planes) are lumped into a single source point at the
center of a plane, and sink points (current leaving the plane) are the packagepins which are distributed over the plane. In reality, bonding wires (or TAB)
inject current into the Vss plane. Note that the above mentioned single source
point assumption is valid only if the chip die area is much smaller than the
VDD/VSS plane area. A typical "direct connection" package Vss connection
without vias is shown in Figure 4.l.
Vss Plane
C,a:LOW",
Bonding
Shelf
Bonding
Wire
@
t=O.05cm
Copper Plane
3cmx3cm
~VsSPins~
Figure 4.1 Typical "direct-connection" package V ss connections.
POWER DISTRIBUTION INDUCTANCE MODELING
35
A UA software tool called UALGRL [4.1] was used to calculate the
plane inductance under the assumption that magnetic diffusion effects on the
plane are negligible. This tool can be used to calculate both the resistance
and the inductance of reference planes with or without perforations. Even
if external and internal on-chip Vss buses are used, they may be connected
to the same Vss package plane connections, and decoupling is not assured.
In such cases, package plane parasitics playa major role in coupling output
driver switching noise to the internal gates and also to the input circuits [4.3].
In the past mutual elements of the package plane inductance network were
neglected, and it was assumed that plane inductance decreased inversely with
the increase in number of package-pins (sink points). Results have demonstrated that due to mutual inductance in the plane VDD /Vss plane inductance
saturates for large number of package-pin connections [4.2]'[4.4].
4.2 MATHEMATICAL FORMULATION OF UALGRL [4.1]
In UALGRL the mathematical constraint is that the current injected
into the plane is equal to the total current removed through all the packagepIllS,
q
p
L Ii (source)
L Ij(sink)
i=l
j=l
(4.1)
where q is the total number of source (bond-pad) points, and p is the total
number of sink (package-pin) points. Additional assumptions:
a)
if frequency (f) is such that skip depth > thickness of the plane, field
variation with thickness is neglected. Thus, fields are function of x,y where
x,y are the coordinates on the plane surface. In addition, fields are assumed
to have zero z components.
b) if frequency (f) is such that skin depth < thickness of the plane, it is
assumed that current flow is restricted within a skin depth and the assumption
of (a) still hold.
Inside the plane, the electric field is given by
E
= - \1 if;
- jw A ,
(4.2)
36
SSN OF CMOS DEVICES AND SYSTEMS
where <jJ denotes the electric potential and w is the radian frequency. Then
the expression for current density inside the plane is obtained from Ohm's law
as
J = -(J'\l<jJ - jwA ,
( 4.3)
where (J' is the conductivity of the plane. Next it is assumed that inside the
ground plane magnetic diffusion effects are negligible. The current density at
any given point can be approximated as
J = -(J'\l<jJ
(4.4)
Neglecting charge accumulation at the boundaries of the plane and using the
fact that J satisfies the continuity equation
(4.5)
we conclude that the potential <jJ satisfies Laplace's equation,
(4.6)
A finite element solution for the potential cP is obtained under the following
boundary conditions [4.2]:
1) At plane boundaries
0cP =
on
0,
(4.7)
2) At source and sink points cP is assigned a specific values. Once cP is calculated, the current leaving each sink point is easily obtained as
I
=
t
t
J . n dl .
(4.8)
Here t is the thickness of the plane. Knowing the current density from equation (4.4) and using the free-space Green's function O(r I r'), where
O(r I r')
=
411'
I r 1 r'l '
(4.9)
POWER DISTRIBUTION INDUCTANCE MODELING
37
the magnetic vector potential A is
A
=
J-l
1
J(r') G(r 1 r')dv' .
(4.10)
Resistance and inductance of a plane are calculated from,
..!.1
R 1 Itot 12 =
L 1 I tot 12
=
(T
Re
v
J*. J dv ,
1
J* . A dv .
(4.11)
(4.12)
A perforated plane structure with multiple sink/source points is shown
in Figure 4.2a [4.5]. In Figure 4.2b [4.2]' the contour "e" used in equation
(4.7) is shown.
4.3 EFFECTIVE INDUCTANCE "Lvss" MODELING
Using UALGRL one can calculate the reference plane inductance and
resistance for an arbitrary number of sink/source points. Some restrictions
apply on the placement of perforations near the plane boundary, and on the
discretization distance [4.6]. In reality for a given chip-package interface there
could be q number of bond-pad connections and p number of package-pin
connections. In this work, a single (no double or triple) bonding connection
is assumed. Note that, as mentioned earlier, it is assumed that all bonding
connections are to an area small enough to be approximated as a point. Single
chip-package interface model and it equivalent inductance network is shown
in Figures 4.3a and 4.3b, respectively. For p
Lvss
=
Lbond(q)
+
i-
Lplane(P)
q,
+
Lpin(P) .
(4.13)
Here L bond (q) is the effective inductance of q number of bond-pad connections,
Lplane(P) is the effective inductance of Vss plane with p number of package
Vss pins, and Lpin(P) is the effective inductance ofp number of package-pins.
It is assumed that the Vss bond-pads and the package pins are separated by
38
either
SSN OF CMOS DEVICES AND SYSTEMS
VDD
or signal bond-pads and package pins respectively. With this as-
sumption, mutual inductance between Vss bonding connections, and between
package pins are negligible. Equation (4.13) can thus be written as
LVS5
(a)
/
~
L'bond
q
•
Sources
0
511lks
L
+
E!
()
plane P
+
L'pin
P
(4.14)
Metlll Removed (19.1 Po)
~
• source (or sink)
(b)
"
V
Figure 4.2 a) Perforated V 55 plane with multiple sink/source points [4.5].
b) Contour "c" used in equation (4.7).
POWER DISTRIBUTION INDUCTANCE MODELING
39
(a)
Vss Bus
Bonding
Wires
Plane
Pins
(1),(2),(3): Sink Points
(b)
Figure 4.3 a) Single chip-package interface model. b) Equivalent inductance
network.
SSN OF CMOS DEVICES AND SYSTEMS
40
and L~in are the partial self-inductance for a single connection
bond-pad and package-pin, respectively. Closed-form equations have been
L~ond
derived to approximately calculate the bond-pad [4.7J and package-pin [4.8J
inductance. However, when the pitch of Vss bond-pads and/or package pins
is reduced significantly, the mutual inductive coupling between neighboring
connections will increase, and must be included in Lv ss calculations. Note
that neighboring VDD bond-pad or package-pin connections always reduce
the Vss path effective inductance, whereas neighboring signal bond-pad or
package-pin connections can either reduce or increase the effective inductance.
This is because current paths in VDD and Vss connections are always in
opposite directions, and current paths in signal and Vss connection can be
either in the same or the opposite direction for bi-directional I/O drivers.
The objective of this work is to model and calculate the effective
inductance Lvss for a given chip/package design. Knowing the maximum
allowable switching noise, the minimum number of Vss connections required
to assure zero (or low) probability false switching can be calculated. With the
assumption that there is one-to-one mapping between bond-pad and packagepin connections (i.e. p=q),
L vss
~
L'bond
---
+
P
( )
Lplane P
L'pin
+ -
P
(4.15)
For single metal-layer packages (no Vss reference planes) with the above assumptions equation (4.14) reduces to
L VSS
~
L' bond
---
P
L' pin
+-
P
(4.16)
where L~in corresponds to the leadframe plus the pin inductance for a single
Vss pin connection. Note that, mutual inductance between lead frame ele-
ments are neglected in equation (4.15). However, leadframe elements can be
long and mutual inductance must be included. Impact of various lead frame
structures to minimize SSN in high-speed SRAMs (Static Random Access
Memory) have been analyzed [4.9J.
Again, in deriving equation (4.14) it is assumed that the chip die area
is much smaller than the Vss plane area, and the source points are lumped
POWER DISTRIBUTION INDUCTANCE MODELING
41
into a single equivalent source point at the center of Vss plane. It is also
assumed that all sink points are at an equipotential, and all source points are
at a different equipotential. From Section 4.2 (equations (4.8) and (4.12)),
it is clear that Lpl ane (p) not only depends on the number of package pins
p, but also on the placement of these pins. Because of this, different Vss
package-pin placements have different Lpl ane values. Even with the same
number of Vss package-pins and for a fixed package-pins placement, Lpl ane
values can vary significantly if anyone of the current paths between source
and sink points are perturbed due to the perforations. This effect is explained
qualitatively in Figures 4.4a and 4.4b using three sink points on the Vss plane
with and without perforations respectively.
Note that perforations in the
Vss plane always increase the effective plane inductance, so that in Figures
4.4a and 4.4b L' p(3) > Lp(3). To demonstrate this effect, .a copper plane
(0'::::: 5.8 X 10 7 Slm, /J::::: 12.56 X 10- 7 Him) was selected and the inductance
was calculated with and without perforations. A 2 cm x 2 cm ground plane
with 0.05 cm thickness was selected for this analysis. Sixteen sink points
were selected and placed around the source point (located at the center) as
shown in Figure 4.5. For the perforated ground plane model, two arbitrary
rectangular cuts (metal removed from the copper planes) were selected ·as
shown in Figure 4.5 with dotted lines. The calculated plane inductance values
are given in Table 4.1. Impact of individual package-pin placement on the
effective Lv ss is explained in the following section using superposition theory
and the equivalent inductance network.
Table 4.1. Effect of perforations on Lplane and Rpl ane values.
Ground Plane Model
Inductance (nR)
Resistance (gO)
Ground Plane without perforations
2.615
12.63
Ground Plane with perforations
6.132
23.12
4.4
REFERENCE PLANE INDUCTANCE NETWORK
CALCULATION
Consider a Vss plane with a single perforation and three V ss pins
42
SSN OF CMOS DEVICES AND SYSTEMS
Vss Plane without Perforations
® Source
o Sink
(a)
Vss Plane with Perforations
Note: Lt (3) ¢ Lp(3)
(b)
Figure 4.4 Current distribution on a V55 plane a) without perforations and
b) with perforations.
43
POWER DISTRIBUTION INDUCTANCE MODELING
0
0
E
0
0
0
,--------.......,
I
IL-
I
I
0
_ _ _ _ _ _ .--J
®
0
U
0
C\J
0
,---------,
0
0
I
I
IL- _ _ _ _ _ _ _ ....JI
0
0
0
0
I·
0
·1
2cm
® Source
0
Sink
r--I
I __ j
Hole
Copper Plane:
<T=5.8XI0 7 Sim
fL = 12.566 X 10- 7 Him
thickness = 0.05 cm
Figure 4.5 Perforated copper V 55 plane with two arbitrary rectangular cuts.
as shown in Figure 4.6a. A copper plane with the area 2 cm x 2 cm, and
thickness of 0.05 cm was selected for this analysis. The inductance model corresponding to the Figure 4.6a package
V55
plane is shown in Figure 4.6b. To
calculate the equivalent inductance network, the following superposition technique was developed. Plane inductance values are calculated using UALGRL
by connecting all possible combination of VI, V2, and V3 (taken one
SSN OF CMOS DEVICES AND SYSTEMS
44
E
u
C\J
Source
HOle/
~--~----,I
IL
_ _ _ _ _ _ _ _ ...J
v~
2 '~Sink
(a)
~OV
___
3
11-oII1Ili----- 2 cm ----~~I
(b) '--_ _ _ _ _ _ _ _ _ _ _ _ _ _....
Figure 4.6 a) A V ss plane with three Vss pins. b) Equivalent inductance
network of Figure 4.7 V ss plane.
POWER DISTRIBUTION INDUCTANCE MODELING
45
at a time, two at a time, or all three) to ground and performing the inductance
calculations. Sink point combinations for three package pins, and the corresponding inductance values (not necessarily the network element values) are
shown in Table 4.2. The inductance values corresponding to sink points VI,
V2, and V3 individually at ground potential are the element values L 11 , L 22 ,
and L33 respectively. The superscript in Table 4.1 corresponds to the sink
points grounded to calculate the inductance values (marked with subscript)
which will later be used to calculate the inductance network element values.
Note that
(4.17)
and by equating the stored energy of a physical system using two representations,
(4.18)
Table 4.2. [Lij] inductance calculations.
Sink Points
Inductance Notation
Inductance (nH)
VI
L1
7.681
V2
L2
8.398
V3
L3
8.376
Vl,V2
L(1,2)
5.391
Vl,V3
L(1,3)
5.394
V2,V3
L(2,3)
6.074
L(1,2,3)
4.743
Vl,V2,V3
where I is the total current into the plane, and Ii, and Ij are the partial
currents through ith and ph sink points, respectively. Partial current through
each sink points (Ii and Ij) are extracted from UALGRL simulations, and the
following inductance network matrix [Lij] is calculated from Table 4.2 and,
7.681 2.764 2.770)
[Lij] = ( 2.764 8.398 3.762
2.770 3.762 8.376
(4.19)
SSN OF CMOS DEVICES AND SYSTEMS
46
It can be shown by using mathematical induction theorem that in order
to calculate the inductance matrix elements [Lij) for p number of packagepin connections, one needs to run UALGRL for p(p+l)/2 different ground
connections. Note that proper utilization of any existing symmetry in the
package-pin connections reduces the computational labor significantly. For
example, utilizing the symmetry between sink points (2) and (3) in this example would reduce six UALGRL computations to four computations (i.e.
=
=
L22
L33, L12
L13). The plane inductance value with all sink point (VI,
V2, and V3) grounded corresponds to L(1,2,3), and this value is used for consistency check to verify the calculated inductance network matrix elements.
4.5 RESULTS
A typical 168 pin Pin-Grid-array (PGA) package Vss copper plane
with area of 3 cm x 3 cm and a thickness of 0.05 cm was selected for this
analysis. Eight Vss package-pins were placed around the source point (again
source points are lumped into a single source and placed at the center of the
plane) as shown in Figure 4.7. Each sink point location is numbered and
the sink points are referenced by these numbers in later discussions. The
inductance network is calculated using the methodology described in Section
4.4, and the corresponding inductance network is,
14.07
[Lij)
=
Since Lij
=
7.10
12.28
5.74
7.10
14.07
4.85
5.47
7.10
12.28
4.71
4.85
5.74
7.10
14.07
4.85
4.55
4.85
5.47
7.10
12.28
5.74
4.85
4.71
4.85
5.74
7.10
14.07
7.10
5.47
4.85
4.55
4.85
5.47
7.10
12.28
(nH).
(4.20)
Lji, only part of the matrix in equation (4.20) is filled.
To
study the effects of perforations on the Vss plane inductance, the inductance
network is calculated for the perforated Vss plane structure shown in Figure
4.8. Note that these two planes (Figures 4.7 and 4.8) are identical except the
47
POWER DISTRIBUTION INDUCTANCE MODELING
perforations. Inductance network element values for the perforated Vss plane
structure are given in equation (4.21).
..
3 om
(7)
(6)
o
o
o
( 1.5,2.5)
(2.5,2,5)
(05,2.5)
(8)
(0.5, 15)
o
sink
•
source
o
(15,15)
(II
(2)
o
o
(0,5,0.5)
(,)
•
o
3 om
(5)
(2.5, \.5)
(3)
o
( 1.5,0.5)
(2.5,0.5)
0,05 em copper plone
Figure 4.7 A non-perforated V ss plane with eight sink points.
..
..
30m
.75)
(7)
0
(O.5,2S)
(5)
(6)
0
( 1.5,2.5)
( 1.75,
(8)
(1.5,1.5)
•
0
(0.5,1.5)
3 om
(I)
0
(0.5,0.5)
o
sink
•
source
( 1.25,0.75)
(1.75,1.25)
12)
0
( 1.5,0.5)
(4)
0
(2.5,1.5)
(3)
0
(2.5,0.5)
0.05 em copper plene
Figure 4.8 A perforated V ss plane with eight sink points.
SSN OF CMOS DEVICES AND SYSTEMS
48
15.01
[Lijl'
=
8.59
14.62
6.18
8.54
14.95
4.93
6.17
7.50
12.58
4.94
5.72
6.44
7.81
15.93
5.04
5.00
4.90
5.05
6.29
12.61
6.01
5.28
4.54
4.41
5.31
7.34
14.00
7.53
6.12
4.83
4.28
4.65
5.62
7.15
12.41
(nH).
(4.21 )
By comparing both the inductance network matrices (equations (4.20) and
(4.21)), it is clear that perforations perturb the current distribution on the
ground plane, and thereby the self and mutual inductance values are larger in
[Lij]' compared to [LijJ. For example, the perforation placed between source
point and the sink point number (2) not only increases the self inductance
L22 but also increases the mutual inductance L12, L 23 , and L 13 . Perforations
placed between two neighboring sink points increase the mutual inductance
between these points. This effect is clear by comparing
tions (4.20) and (4.21).
L~6
with
L56
in equa-
16
60~--~----~2----~3~--~4-----5~--~6-----L7----~8-'
Numberof Sink Points
Figure 4.9 Comparison of perforated and non-perforated Vss plane inductance vs. Number of sink points.
49
POWER DISTRIBUTION INDUCTANCE MODELING
In Figure 4.9, the plane inductance of these two ground planes are
compared. Note that the number of sink points on the x-axis of the Figure
corresponds to 1,2,3, ... ,N sink points with their exact placement as shown
in Figures 4.7 and 4.8. As expected, the plane inductance of the perforated
Vss plane is larger than the non-perforated Vss plane. Notice due to the
perforation placed between source point and the sink point number (2), the
difference between L'plane(P) and Lplane(P) is the largest when the number
of sink points equal to 2. These difference decreases as the number of sink
points increase from 4 to 8. This is because, as we increase the number of sink
points, due to the other sink points contribution, L' plane approaches Lpl ane .
To study the effect of package plane inductance on the simultaneous
switching noise, L'bond=2.5 nH, and L'p;n=2.5 nH were used. Simultaneous
switching noise for two cases, sixteen 3 rnA (D.C. sink with VO l=O.4V) CMOS
outputs, and thirty-two 12 rnA (D.C. sink with Vol=O.4V) CMOS outputs was
studied. For 3 rnA and 12 rnA CMOS outputs, T=l.O ns (defined in Section
3.2) was used in this analysis. The effective inductance Lv ss was calculated
using equation (4.14) with p=q for one to eight Vss package-pins. Plane
inductance Lplane(P) was calculated using UALGRL.
Simultaneous switching noise (including the negative feedback effects)
is calculated using equation (4.22),
Vn
=
Vk
+
-L-1 ",n 1
v ss L..o;=l
K
"K
[I-
1
+
n K
2VkLvssL:::-'
;=1
T,
1.
(4.22)
The results are shown for: 1) a model with negative feedback effects including
plane mutual inductance effects, 2) a model with negative feedback effects
without plane mutual inductance, and 3) a model without negative feedback
effects and with plane mutual inductance. Note that Lv ss is given by the
equation (4.15).
Simultaneous switching noise for sixteen 3 rnA output drivers, and
thirty-two 12 rnA output drivers is shown in Figures 4.10 and 4.11 respectively.
As explained in Chapter 3, to have meaningful ground noise calculations, not
only an accurate Lv ss model is essential but also detailed (including negative
feedback effects) circuit models are essential. In Figure 4.10 and 4.11, the
SSN OF CMOS DEVICES AND SYSTEMS
50
(16 Outputs SimultaneQus Switching)
(I) Negative Feedback with Plane Mutual Inductance
(2) Negative Feedback without Plane Mutual Inductance
(3) Plane Mutual Inductance without Negative Feedback
2.0
T= 1.0ns
L~ond=2.5nH
L~in=2.5nH
1.5
~
Q)
(/)
·0
ZI.O
1:1
c
e
::J
~
0.5
(3)
0..0
L -_ _- ' -_ _--'-_ _ _L -_ _..1-_ _--'-_ _--1_ _ _.l...-_ _....L.._
a
2
3
4
5
Number of Vss Pins
7
6
8
Figure 4.103 rnA drivers, 16 outputs simultaneous switching noise.
(32 Outputs Simultaneous Switching)
3.0.
2.5
~
?
2.0
Q)
(/)
·0
Z 1.5
1:1
c
:J
a...
<.!)
10
(I) Negative Feedback with Plane Mutual Inductance
(2) Negative Feedback without Plane Mutuallnduclance
(3) Plane Mutual Inductance without Negative Feedback
0.5
0.0
T = 1.0ns
L~ond =2.5 nH
L~in =2.5nH
L -_ _.l...-_ _..1-_ _....L.._ _--'-_ _--"-_ _-.l._ _ _' - -_ _..........
o
2
34
567
Number of Vss Pins
Figure 4.11 12 rnA drivers, 32 outputs simultaneous switching noise.
B
POWER DISTRIBUTION INDUCTANCE MODELING
51
plane mutual inductance, and also the negative feedback effect, saturates the
ground noise for large numbers of Vss connections and/or for large numbers
of drivers switching simultaneously. Note that when both the plane mutual
inductance, and the negative feedback effects are considered, the ground noise
saturates for a lower number of Vss bond-pad/package-pin connections due to
the additive effects. The errors in calculating ground noise values without the
plane mutual inductance or without the negative feedback effects increase as
the number of simultaneously switching outputs increase, and/or with increase
in the drive strength of these output drivers. This effect is clear by comparing
the curves (1), (2), and (3) of Figures 4.10 and 4.11.
4.6 SUMMARY
A method of calculating the effective VDD /Vss chip-package interface
inductance
"Lejf"
was presented. It was found that package-pin placement
has a strong influence in the plane inductance (especially for a small number
of package Vss pins). Perforations on the Vss plane perturb the current
distribution in the ground plane, and these perturbations increases the plane
inductance. Unpublished results have also shown that having symmetrical
connections in the sink points greatly reduces the package plane inductance.
The effect of Lplane on simultaneous switching noise was explained, and errors
associated with neglecting plane mutual inductance were discussed.
CHAPTER 5
SIGNAL CONDUCTORS OVER A
PERFORATED REFERENCE PLANE
5.1 INTRODUCTION
Due to increases in system speed and density, designers are confronted
with several practical problems imposed by interconnect structures. In short,
miniaturization can force different types of transmission-line discontinuities.
Deviations from an ideal transmission line can be thought of as belonging to
one of two categories: (1) the signal conductor departs from the reference
plane (e.g. package leads, sockets, and connectors); and (2) the reference
plane is not continuous (e.g. mesh planes, isolated ground regions, and multiple supply regions)[5.1]. The first category of discontinuities has been wellcharacterized, and it has been shown that lumped-element models can be used
to represent these structures [5.2],[5.3]' [5.4]. In this work, a detailed analysis
of the effects on signal propagation of reference plane openings is attempted.
The intent is to establish which modeling tools and methods can be used to
extract equivalent circuits that accurately predict time-domain waveforms in
cards, boards, and modules containing reference plane openings. Results to
within engineering accuracy are required, with minimum model complexity
and analysis time. In Figure 5.1, the cross-section of a srtipline interconnect
structure with an opening in the top reference plane is shown. Two electrical
SSN OF CMOS DEVICES AND SYSTEMS
54
test structures have been designed specifically for this work.
----.. Direction of Propagation
1111111111111111111111///1/1
111///11////1//////1//1//
•
•
77117177117777111171/711/71/71/711777177777777177111711
I..
.1 I"
I,
~L
2
12
.1
~L
2
~~l===~~~l==~
Figure 5.1 Equivalent circuit model of a perforated reference plane strip line
interconnect structure.
These have been constructed with the recognition that TDR measurements of
small discontinuities are often difficult. Typically, other discontinuities which
are difficult to eliminate from the experimental set-up (such as connectors),
can mask the discontinuity reflections one tries to measure. For this reason, a
scaled-up model containing a single reference-plane opening was constructed
for initial measurements. The second test structure is an actual FR-4 card
containing many small openings in the reference planes. After discerning the
general features of the discontinuity from the scaled model, one can more
SIGNAL OVER A PERFORATED REFERENCE PLANE
55
easily isolate and understand the discontinuity effects in realistic structures.
Photographs of the scaled model and the FR-4 card measured in this work are
shown in Figures 5.2 and 5.4. Cross-sections and dimensions for both models
are given in Figure 5.3 and Figure 5.5.
Figure 5.2 Scaled-up, perforated reference plane stripline model.
..
30.5
o
/
/
/
/
/
/
/
I
1
L...--!-_-,L-l_/-J'
1
I
I
/
~04
~~---7r/~.~
/ 1204
.
/
/
/
2.5
1
Figure 5.3 Scaled-up model cross-section.
0
Signal Trace Length =61cm
Distance from Gap = 20.1 CrT
Connectors at Ends = 4 cm
56
SSN OF CMOS DEVICES AND SYSTEMS
Figure 5.4 Periodically perforated card structure.
(Cross-section)
:.: 0 0 0 0 0 0 0 :-:
(Top View)
Figure 5.5 Card structure interconnect cross-section.
SIGNAL OVER A PERFORATED REFERENCE PLANE
57
The basic modeling approach followed in this work is to construct
lumped-element equivalent circuits which represent the transmission-line over
the small region containing an opening in the reference plane. By "represent", we mean that the time-domain waveforms predicted from circuitsimulation match the measurements obtained to within 5-10 %. The circuit
simulations are performed using ASTAP [5.5]. The lumped-element models
for the reference openings are extracted using four distinct techniques: (1)
S-parameter measurements, (2) two-dimensional and (3) three-dimensional
inductance and capacitance extraction programs, and (4) a full-wave electromagnetic parameter-extraction program. In order to fully characterize their
impact on propagating signals, reference plane openings of different size and
shape are studied. Another objective of this study is to determine the limits
of applicability of the four techniques mentioned above. Finally, guidelines
are presented for package designers which indicate when routing signal lines
over reference plane openings will have a significant noise impact and when
they can be ignored.
5.2
IMPACT OF REFERENCE PLANE OPENINGS FOR
STRIP LINE GEOMETRIES
The opening in the top reference plane introduces an inductive discontinuity in the stripline since return current is forced to flow around it. The
signal reflection produced by an opening in one reference plane of a strip line
structure depends on the distance between the signal conductor and the discontinuous reference plane, since a larger return current will be present in the
reference plane closest to the signal line. For a buried microstrip line (no top
reference plane), it has been shown there exists a critical conductor height
above the single reference plane (he), below which the effect on transmissionline parameters L, C, and Zo of adding a top reference plane are negligible
[5.6]. Detailed analyses of buried microstrip electrical characteristics were also
shown in [5.7].
As the conductor height increases above he, however, a larger fraction
SSN OF CMOS DEVICES AND SYSTEMS
58
of the E-field lines are not collected on the bottom plane, and the effect of
adding a top reference plane become significant. Furthermore, if an opening
is present in the top plane, some of these fields will escape into air (outside
the strip line structure). In this case, the stripline will suffer a significant
impedance discontinuity in the region of the reference plane opening. In Figure
5.6, the calculated impedances for a stripline and a buried microstrip are
compared as a function of normalized conductor height.
80
70
_60
q
w- I
H
~
h
Stripline
~r~~;:\~
- - - - ) - Buried
_____ Microstrip
Buried
Microstrip
OJ
U
§ 50
'0
OJ
a.
E
- 40
Stripline
30
20L---------L---------L---------L---------L-______~
0.0
0.2
0.4
06
0.8
1.0
Normalized Ratio, ~
Figure 5.6 Stripline, buried microstripline impedence vs. conductor height.
These impedances were calculated using a two dimensional, TEM approximation transmission-line parameter extraction tool [5.9]. The dielectric is
assumed to be Plexiglass, which has a relative dielectric constant of 2.6 over
SIGNAL OVER A PERFORATED REFERENCE PLANE
59
commonly-used frequency ranges [5.8]. From the figure, it is clear that 6..Z,
which we define as the difference between the buried microstrip and stripline
impedances,
6..Z = Z(bmsl) - Z(sl) ,
(5.1)
increases rapidly as the conductor height increases. Here Z(bmsl) is the buried
microstrip line impedance and Z(sl) denotes the stripline impedance. In Figure 5.7, 6..Z is plotted for two different normalized linewidths to indicate the
sensitivity expected.
30.
. - p=+o..375(5o..o.stripline)
~--~~~--~~~--~
Stripline
25
920.
Buried
Siripline
Microstrip
. - p=+o..286 (50..0. slripline)
Q)
0'1
c:
c
.s::.
U
15
Q)
0
c:
C
'0
Q)
0.
10.
-+--
p= +0..167 (50..0. stripline)
E
5
0.
0.0.
0.2
0..4
0..6
Normalized Ratio,
~
D.B
Figure 5.7 Reflection coefficient (p), 6..Z vs. conductor height.
1.0.
60
SSN OF CMOS DEVICES AND SYSTEMS
Note that the reflection coefficient (Pd)
IS
directly proportional to
(~Z):
Z(bmsl)
+
Z(sl) .
(5.2)
This expression is only rigorous for the case where the upper reference plane
is completely split, since the region containing a finite-size opening is only
approximated by a microstrip line. This figure can be used for estimating an
upper bound on reflection coefficients associated with narrow reference plane
openings. In common packaging structures, X-Y wiring pairs are used in a
stripline configuration; most nets will be affected by openings even if they
occur in only one plane.
From an estimate of the reflection coefficient associated with a reference plane opening, the noise pulse amplitude for digital signals can be
estimated based on the risetime. Specifically, it can be shown that an inductive discontinuity will produce a reflection with magnitude greater than
roughly one-tenth of the incident voltage when
(5.3)
where Tr is the incident signal risetime, Ld is the discontinuity inductance,
and Zo is the nominal characteristic line impedance. Provided the effect is
deemed to be significant, the techniques described in the next sections can be
used to build accurate ASTAP or SPICE models of the stripline interconnects.
5.3
CONNECTOR
CHARACTERIZATION
S-PARAMETER MEASUREMENT TECHNIQUES
USING
Frequency-domain, two-port measurements are used in this work primarily to characterize the connectors used to bring signals to the scaled model
and the test card. Since we are not interested in studying the connectors explicitly, the S-parameter technique provides a quick way for extracting their
lumped-element equivalent circuits. However, an attempt was made to characterize the strip lines containing the reference discontinuities as well, in order
SIGNAL OVER A PERFORATED REFERENCE PLANE
61
to check the feasibility of using the approach to measure such small discontinuity effects.
The connectors used in the scaled model and test card introduce parasitic capacitance and inductance, which have to be calculated and incorporated into an ASTAP or SPICE model to simulate the correct time-domain
signals. Measurements of the two-port S-parameters for a calibration line
containing only connector discontinuities can be matched to simulations performed in the frequency-domain for a lumped-element model of the connector
having variable element values. This is essentially performed automatically
using the Touchstone(TM) software [5.10]' together with a network analyzer
(HP 8753A) and an S-parameter Test set (HP 85046A). Both the magnitude and angle are measured for all four S-parameters, after a proper twoport calibration is conducted to eliminate the influence of the cable. The
S-parameters are measured across the frequency range from 10 Mhz to 1.1
Ghz. The frequency-domain, two-port circuit model for the calibration line
and connectors is shown in Figure 5.8.
Connector
Connector
Perforation
Two-port Model
A?
S;j(w)
~B
Figure 5.8 Two-port network equivalent transmission line model.
SSN OF CMOS DEVICES AND SYSTEMS
62
This model is fed to Touchstone, which then optimizes the lumped-parameter
values to achieve convergence with the S-parameters measured from the actual
structure. A buried microstrip line (without a top reference plane) is used in
addition to the stripline to check for consistency between calculated connector
values. Good agreement for the connector lumped-element values is obtained
for the two different structures. The optimization procedure is allowed to
run until the error E: converges to its minimum value. Touchstone uses both
random and Quasi-Newton optimization methods to minimize E:, defined as
11
2
L L
k=l i,j=l
[Sijm(Wk) - Si/(Wk)]2 .
(5.4)
Here sijm(Wk) are the measured and 8 i/(Wk) are the calculated two-port
S-parameters. Optimization is performed over eleven different frequencies,
from 10 Mhz to 1.1 Ghz in 100 Mhz steps. Several different lumped-element
topologies (e.g. Tee and Pi) were tried to best-fit the connector model.
With the connectors well-characterized, the S-parameter technique
was used to extract equivalent circuit models for the reference plane discontinuities in the scaled model. Results from the Touchstone optimizations, along
with the errors associated with each calculation, are shown in Table 5.1.
Table 5.1 Touchstone-calculated lumped-element values
and optimization error.
Discontinuity
connector
L(nH) I C(pF)
12.7/5.2, R=4.4
Error (6)
n
0.11
perforation 5x1 cm
1.52/0.95
0.21
perforation 5x4 cm
perforation 5x8 cm
perforation 10x1 cm
7.20/1.82
9.52/2.54
1.37/0.89
0.40
0.52
0.31
perforation 10x4 cm
12.56/1.73
0.48
perforation 10x8 cm
13.25/3.42
0.67
27.42/6.86
1.21
perforation 20.4x20.4 cm
SIGNAL OVER A PERFORATED REFERENCE PLANE
63
Note that for larger perforation sizes the error increases. This is because
for large perforation areas (more than 15 % of the total top reference plane
area), simple lumped-element models for the discontinuity become inadequate.
Another comment on this technique is that it is observed upon minimizing
the error c, that different sets of lumped element values (not one unique
solution) can give comparable error values. One way to select the best set
is to use each in ASTAP simulations and compare with TDR measurements.
The TDR measurement setup used in this study was shown in Figure 5.9.
BNC ----+
L
~
T
Connector
R
L
~
L
R
Stripline
Stripline
1
1
~
T
L
L
~
T
Figure 5.9 TDR measurement setup and connections.
Results which can be identified by visual inspection as unphysical are
discarded. In general, it is found that the S-parameter matching technique
64
SSN OF CMOS DEVICES AND SYSTEMS
is useful for calculating the connector parasitics, which are large, but for the
smaller effects produced by discontinuities such as ground plane openings, the
methods described later in this work are more effective. This is due to the
fact that it is difficult to resolve the added reflection due to the discontinuities
of interest in the frequency-domain when other, larger sources of reflections
(namely, the connectors) are present. Also, this technique is dependent on
measurement data and is therefore not appropriate for pre-hardware analysis
and has no predictive capability.
5.4
MODELING USING A TWO DIMENSIONAL (TEM)
APPROXIMATION
In Figure 5.10, a strip line with and without a perforated reference
plane is shown. The general technique for constructing an L-C circuit to represent the transmission-line in the region of a reference-plane perforation is
now described.
First, the Per- Unit-Length (PUL) parameters for the cali-
bration stripline (without perforations in the reference planes) are calculated
using parameter extraction programs. If the width of the perforation (Wp ) is
very large compared to the width of the signal line conductor (We), that is
then two-dimensional extraction programs may be used. Note that in practice,
perforations are often small (compared to the total plane area) in size, and
may be repetitive. For example, let the top plane perforation window width be
Wp (arbitrary units). If Wp is not greater than several signallinewidths, three-
dimensional extraction programs should be used. Once the PUL inductance
(Ls) and capacitance (C s) are calculated for the calibration stripline, the
appropriate 2-D or 3-D tools are used to re-calculate the PUL parameters for
the actual structure. The difference in PUL transmission-line parameters is
due to the presence of the perforation in the reference plane.
The 2-D capacitance and inductance extraction programs are simplest
to use. For the perforated-plane case shown in Figure 5.10(b), the PUL induc-
SIGNAL OVER A PERFORATED REFERENCE PLANE
65
tance (Lp) and capacitance (Cp) have been calculated using a 2-D program
internal to IBM.
1/11/1II111I/1Iij1
11111111//111111
__________ c::::::::J _________ _
7////////7///7/777/7777/777//
Stripline
Perforated Stripline
Per-unit-Iength Parameters
Per-unit-Iength Parameters
Ls= nH/cm
Lp= nH/cm
Cs = pF/cm
Cp=pF/cm
Discontinuity Parameters
6L=(L p-L S )·1
16CI = (C p - Cs)·l
Where
1 = Perforation Length
Figure 5.10 Two-dimensional (PUL) capacitance/inductance modeling.
The top reference plane is modeled as two distinct grounded conductors separated by a distance equal to the perforation window width (Wp). Knowing the
66
SSN OF CMOS DEVICES AND SYSTEMS
PUL inductance and capacitance values for the two structures, the differences
due to the discontinuity, 6.L and 6.C, can be computed:
(5.5a)
(5.5b)
6.C
Note that 6.C will be negative for this type of discontinuity. These values
are compared in Table 5.2 with the values obtained using the S-parameter
matching technique described earlier. A separate check on these calculations is
provided by capacitance measurements, which were carried out using a capacitance meter (@ 1 Mhz). The total capacitance (between signal and ground)
was measured for different perforation sizes in the scaled model. These values
are compared with the 2-D calculated values in Figure 5.11.
J
r><--x---------x
~.9: 80~
LL
-~_ •
___
~
Cut Width = 5 em
•
Cut Width = [Oem
---------x
.
.j75
~~
g
x
~
~
u 70
•
65
60~--~~--~~--~----~----~~--~-----L-----L--+
o
[0
20
30
40
50
60
70
80
Cut Open Area (cm 2 )
Figure 5.11 Total, scale model measured and calculated capacitance values.
SIGNAL OVER A PERFORATED REFERENCE PLANE
67
Table 5.2. Comparison of calculated lumped-element values.
Discontinuity Model
connector
!!.L/ !!.C
S-Parameter
12.7/5.2, R=4.4
n
!!.L/ !!.C
!!.L
L2DLC2D
L3D
N/A
2.67
perforation 5x1 cm
1.52/0.95
N/A
1.29/0.56
perforation 5x4 cm
7.20/1.82
5.11/2.25
6.73
perforation 5x8 cm
perforation 10x1 cm
9.52/2.54
10.23/4.49
11.69
1.37/0.89
12.56/1.73
4.68/0.63
10.68/2.53
5.38
11.24
13.25/3.42
27.42/6.86
15.35/5.05
39.45/13.09
17.99
44.67
perforation 10x4 cm
perforation 10x8 cm
perforation 20.4x20.4 cm
Units:
!!.L = nH, !!.C = pF, N/A = Not Applicable.
As expected, due to the edge and connector effects, the 2-D calculated values
underestimate the total capacitance. However, when the perforation discontinuity inductance (!!.L) and capacitance (!!'C) are calculated using the 2-D
approach, the edge and connector effects are cancelled out in the subtraction. In the next section, 3-D calculations are performed to further refine this
approach.
5.5 THREE-DIMENSIONAL MODELING TECHNIQUE
Three-dimensional parameter extraction programs [5.11] are used to
calculate the inductance values for different size perforations. As shown in
Figure 5.12, total inductance is calculated with and without the perforation in
the top reference plane. Because computed inductance values strongly depend
on the current path, it is necessary to use a finer modeling grid in the vicinity
of the opening for both planes. The calculated inductance values are tested for
convergence by reducing the grid size. The partial-element inductance bars
used in the 3-D scaled model calculation are shown in Figure 5.13. In the
simulation, the signal line and the two reference planes are shorted together
68
SSN OF CMOS DEVICES AND SYSTEMS
at one end, while the two reference planes alone are tied at the other end, as
shown in Figure 5.12.
Perforotion
cb
Perforated Stripline
Stripline
Discontinuity in Ground Plane
cSl-------e)
Inductance = LSG'
Inductance =LSG
Discontinuity Elements
6L = L SG ' - LSG
Figure 5.12 Three-dimensional inductance modeling.
The total loop inductance (LsG) for the strip line structure without perforations, and for the perforated structure (L~G) are calculated for several different perforation sizes. Using these values, the discontinuity inductance (!:lL)
is calculated:
(5.6)
69
SIGNAL OVER A PERFORATED REFERENCE PLANE
Figure 5.13 X-Y bar formations for 3-D inductance modeling.
I
c
200
25
190
20
~
I
Q)
u
S
u
c
c
Q)
0
~
"0
E:
u
15 E
u
180
~
"0
0
E:
+-
~
..J
~ 170
10
..J
<1
160~------~--------~--------~---------L--------~5
0.0
0I
Figure 5.14 Total, and
0.2
0.3
04
Conductor /Plane Thickness, t(cm)
~L
0.5
inductance values vs. conductor/plane thickness.
70
SSN OF CMOS DEVICES AND SYSTEMS
In Figure 5.14, L'sG and ilL are plotted as a function of conductor/plane
thickness (assuming the reference plane and signal conductors have the same
thickness). This data is for the lOx8 cm opening. The fact that 6..L is observed
to be constant over a wide range of conductor thicknesses indicates that the
values obtained for 6..L will be insensitive to skin effect. In Figure 5.15, 2-D
and 3-D calculated 6..L values are compared for different perforation areas.
b.
Cut Width = 5em
•
Cut Width = IOem
20
•
•
15
L3D
/6~~
I
c
:; 10
<l
5
00
/ /6
b.
•
10
20
L2D
50
40
30
Cut Open Area (em 2 )
60
70
80
Figure 5.15 Comparison between 2-D and 3-D inductance values.
Notice that in the limit of large perforation areas, the 2-D and 3-D
calculated values begin to converge. It is observed that the 2-D calculation
should only be used for large-area perforations, specifically when the opening
is very wide compared to the signal line width (as discussed earlier).
71
SIGNAL OVER A PERFORATED REFERENCE PLANE
The 3-D total loop inductances
L~G
and
LSG
are plotted as a function
of signal line height in Figure 5.16.
220
200
:c
c
~
...J
180
oJ
0
c
.....c0
160
::J
'0
.E
.....c 140
~
120
100
0.0
0.5
1.0
1.5
2.0
Conductor Height, h (cm)
2.5
3.0
3.5
Figure 5.16 Total inductance with and without perforation vs. conductor
height.
For the strip line structure (without perforation), symmetrical inductance values are observed about the midpoint height (h = H /2). For the perforated
structure, larger inductance values are obtained as the signal line is moved
closer to the top reference plane. In Figure 5.17, non-rectangular fixed-width
"gap" perforations are shown. Discontinuity inductance values are calculated
for these structures using the 3-D method. Results show that these discontinuities generally introduce a larger inductive discontinuity compared to a
SSN OF CMOS DEVICES AND SYSTEMS
72
rectangular hole of identical area, however, lower capacitance values are obtained.
Top Reference Plane
~
rzzm
Gap Size,h Inductanee,6L
(cm)
(nH)
1.0
2.0
22.60
26.26
Direction of Transmitted Pulse
Reference Plane Perforation
GapSize,h Inducta nce, 6L
(nH)
(em)
1.0
2.0
22.66
26.29
Figure 5.17 Inductance modeling for "gap" type perforation discontinuity.
As the gap width increases, the inductance and capacitance values for these
slotted structures approach the values associated with equal-area rectangular
openings.
5.6
COMPARISON BETWEEN MEASUREMENTS AND
SIMULATIONS
The TDR measurement setup used in this study was shown in Figure
SIGNAL OVER A PERFORATED REFERENCE PLANE
73
5.9. Figure 5.18(a) shows the ASTAP simulation (smooth solid line) and the
measured (ragged line) waveforms for the calibration line.
2.0
1.5
~
1.0
OJ
OJ:)
.:g
"0
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
xl0-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 1.0
(a)
2.0
1.5
~
1.0
OJ
OJ:)
jg
0
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
xl0-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 2.0
(b)
Figure 5.18 a) Comparison between measurements and simulations for stripline.
b) Measurements and simulations for 5xl em perforation size.
Signal reflections received from the scaled model are shown within the high-
74
SSN OF CMOS DEVICES AND SYSTEMS
lighted box. Notice the two different discontinuities: 1) BNC connector Tjunction, and 2) connector (including a BNC connector) to the scaled model.
The risetime at the end of the launching cable was measured to be 920 ps. It
is observed that it is almost impossible to match exactly the connector transients with simulation. The reason is that the bandwidth of the oscilloscope
used is limited to 1 GHz with a T-junction connection (R=lmn, C=10 pF).
However, in the scaled model, the distance between the connector and perforation discontinuity is large enough so that each of the different discontinuities
can be identified uniquely in the TDR measurements.
In Figures 5.18(b), 5.19(a), and 5.19(b), comparisons between measurements and simulations are shown for a 5x1 cm, 5x4 cm, and 5x8 cm
perforation, respectively. The total top reference plane area is (30.5x61 cm)
1860.5 cm 2 • Here the 3-D inductance and 2-D capacitance values are used
with a lossless transmission line in all of the ASTAP simulations. In Figure
5.20(a), 5.20(b), and 5.21(a), comparisons are shown for 10xl cm, IOx4 cm and
IOx8 cm perforations. Good agreement on signal reflection
(~V)
amplitudes
and general waveform characteristics are obtained between measurements and
simulation for all structures. In these figures, 1.0 V corresponds to a 50 n
impedance. The measured impedance of the model is 45.8 n, compared to a
calculated value of 42.4 n. A launching-cable impedance of slightly less than
50 n is observed due to the T-junction, high-impedance connection to the
scope.
In Figure 5.21(b), signal propagation over a large (> 20 % of the total
reference plane area) perforation is shown. As expected,
~V
increases with
perforation area. In Figure 5.22(a), the effect of perforation size is shown for
a 5 cm perforation width. A similar set of waveforms are shown in Figure
5.22(b) for a 10 cm-wide perforation. The TDR measurements demonstrate
that for very small perforation widths and/or lengths, a narrower ~ V (spike)
is observed. In Figure 5.23, the effect of perforation area on ~ V is shown
for three different perforation widths (5cm, 10cm, and 20.4 cm). In Figure
5.20(a), 5.20(b), and 5.21(a), comparisons are shown for 10xi cm, perforations. Good agreement on signal reflection
(~V)
amplitud es and general
waveform characteristics are obtained between measurements and simulation
75
SIGNAL OVER A PERFORATED REFERENCE PLANE
2.0
1.5
~
1.0
(I.)
co
til
.....
"0
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
xlO-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 3.0
(a)
2.0
1.5
~
1.0
(I.)
co
til
,:!:;
0
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
xlO-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 4.0
(b)
Figure 5.19 a) Measurements and simulations for 5x4 em perforation size. b)
5x8 em perforation size.
SSN OF CMOS DEVICES AND SYSTEMS
76
2.0
1.5
~
1.0
Q)
bD
2
"0
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
x10-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 5.0
(a)
2.0
1.5
:>
1.0
Q)
bD
....
>
OJ
"0
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
x10-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 6.0
(b)
Figure 5.20 a) Measurements and simulations for 10xl em perforation size. b)
10x4 em perforation size.
SIGNAL OVER A PERFORATED REFERENCE PLANE
77
2.0
1.5
~
1.0
(l)
OJ)
.r3
(3
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
x10-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model 7.0
(a)
2.0
1.5
~
1.0
(l)
OJ)
m
.....
(3
>
0.5
0.0
-0.5
-0.5
0.0
0.5
1.0
1.5
xlO-8
2.0
Time (sec)
Scale Model: TDR-ASX Plot Model S.O
(b)
Figure 5.21 a) Measurements and simulations for 10xS em perforation size. b)
20.4x20.4 em perforation size.
SSN OF CMOS DEVICES AND SYSTEMS
78
2.0
1.5
~
1.0
Q)
bI)
.8
0
>
0.5
0.0
-0.5
-5
0
5
10
15
20
Time (ns)
Scale Model: Effect of Perforation Size (Width=5 em)
(a)
2.0 , - - - - - - - r - - - - . . , - - - - - - r - - - . . . . , - - - - - - - - - ,
1.5
~
1.0
Q)
bI)
.8
0
>
0.5
0.0
-0.5
-5
0
10
5
15
20
Time (ns)
Scale Model: Effect of Perforation Size (Width=10 em)
(b)
Figure 5.22 a) Signal disturbance (.6. V)
VS.
perforation length for 5 em per-
foration window width. b) .6. V vs. perforation length for 10 em perforation
window width.
SIGNAL OVER A PERFORATED REFERENCE PLANE
79
2.0
1.5
--->
'-'
1.0
(l)
b1J
.....
..til
0
>
0.5
0.0
-0.5
-5
0
5
10
15
20
Time (ns)
Scale Model: Effect of Perforation Area
Figure 5.23
~V
vs. perforation area (different widths).
s for all structures. In these figures, 1.0 V corresponds to a 50 n
impedance. The measured impedance of the model is 45.8 n, compared to a
calculated value of 42.4 n. A launching-cable impedance of slightly less than
50 n is observed due to the T-junction, high-impedance connection to the
scope.
In Figure 5.21(b), signal propagation over a large (> 20 % ofthe total
reference plane area) perforation is shown. As expected, ~ V increases with
perforation area. In Figure 5.22(a), the effect of perforation size is shown for
a 5 cm perforation width. A similar set of waveforms are shown in Figure
5.22(b) for a 10 cm-wide perforation. The TDR measurements demonstrate
SSN OF CMOS DEVICES AND SYSTEMS
80
that for very small perforation widths and/or lengths, a narrower
is observed. In Figure 5.23, the effect of perforation area on
~V
~V
(spike)
is shown for
three different perforation widths (5cm, 10cm, and 20.4 cm).
5.7
FULL-WAVE ANALYSIS OF A PERIODICALLY
PERFORATED STRUCTURE
A three-layer FR-4 test card has been built and studied which contains
periodic ground plane openings located directly beneath a stripline (see Figure
5.4). This test line is amenable to study using in-house full-wave EM tools
which require that the structure to be analyzed fits on a uniform, periodic
grid [5.12]. Two major test lines are designed into the 62-mil thick card: (1)
a stripline with six (300x50 mil) perforations; and (2) a strip line with eleven
(225x25 mil) perforations. The perforations are on a 1 inch and 0.5 inches
pitch for the two cases, respectively. A unit cell discontinuity model used in
the 3-D inductance calculation is shown in Figure 5.24.
Top Reference Layer
f--- -- -~- - -~ -- ~- -- ~ ---0 --~- --~TD-'r~---O--D-
-- ---l
L__________________________________ ·_______________ ~
I
:
:
I
• . . . • ,OOO •.•
:
:
4~g!
:A
22511
J./
~: J ---]
:~'B:
.D#.·
Bottom
Reference
Layer
Signal
Layer
~"7\4'OO
Connection Scheme
200 225
Figure 5.24 Card structure, unit cell discontinuity inductance modeling.
SIGNAL OVER A PERFORATED REFERENCE PLANE
81
Using the full-wave program, both structures are analyzed, resulting in values
for the per-unit-length inductance, capacitance, and impedance for the lines.
Current distributions for the conductors are also obtained, as exemplified in
Figure 5.25.
Figure 5.25 Return current path on the top perforated reference plane.
The connectors are not modeled, but lumped-element equivalent circuits are
obtained for them using the S-parameter approach described in section 5.3. It
is found that the SMA connector and plated-through hole are well-represented
by a single inductance and capacitance with values of 0.11 nR and 1.06 pF,
respectively.
The creation of a mixed transmission-line/lump ed-element model for
82
SSN OF CMOS DEVICES AND SYSTEMS
the strip lines proceeds in a similar way to the methods described earlier.' First,
the Land C values obtained from simulation for the lines, both with and without the ground plane perforations, are compared. Any additional inductance
observed for the former case is due to the presence of the openings. The
change in per-unit-length inductance is divided by the number of openings
per unit length in order to arrive at a lumped-element, additional inductance
for each opening. This value is added to the nominal inductance associated
with a length of line equal to the length of the opening. The resulting inductance is placed in series with transmission-line segments at the location of
every opening. A similar exercise is performed to derive the shunt capacitance
at each opening. The inductance values obtained using the full-wave method
are compared to values obtained using a straightforward, 3-D partial-element
equivalent circuit modeling program. The data are given in Table 5.3.
0.24
0.22
~ 0.20
Cl.i
00
.....co
"0 0.18
>-
0.16
0.14
21
22
23
24
25
26
Time (sec)
Card Model: Periodic Perforation (11 perforations)
Figure 5.26 Measurement and simulation comparison for eleven perforated
model.
SIGNAL OVER A PERFORATED REFERENCE PLANE
83
The final measure of the accuracy of this approach is in how well the
measured TDR waveforms can be duplicated in time-domain circuit simulation. In Figure 5.26, TDR-measured transients are compared with ASTAP
simulations for the eleven-perforation model, using the lumped-element values
obtained from the full-wave tool. It should be noted that the periodic structure provides a very stringent test of this approach, since any small deviation
in lumped parameters results in a significant change in not only the amplitude
of the reflections, but in their occurence in time as well.
Table 5.3 Comparison of calculated lumped-element values.
Lgap(nH)/Cgap(pF)
N/A
Lgap(nH)/Cgap(pF)
Full-Wave Method
L3D Method
225x25 mil
0.65 nH/0.058 pF
0.63 nH/(N/A)
300x50 mil
0.81 nH/0.063 pF
0.87 nH/(N/A)
Discontinuity Model
= Not Applicable
5.8 SUMMARY
Successful package engineering relies on accurate and rapid prediction
of time-domain waveforms inside real structures. A method for constructing
equivalent circuit representations for signal propagation over non-continuous
reference planes has been described. The method can employ a number of
very different tools, including partial-element and full-wave tools, and arrive
at the same equivalent circuit. Through comparisons with measured data,
confidence in the ability of this approach to provide acceptable accuracy has
been shown. Appropriate ranges of applicability have been established to
aid in selecting the best combination of modeling tools. For example, it was
shown that when the perforation area becomes small (relative to the reference
plane total area), detailed 3-D inductance modeling is essential for accuracy.
Design guidelines were also presented to help estimate when perforation discontinuities can be safely ignored. In high-speed applications where they are
84
SSN OF CMOS DEVICES AND SYSTEMS
important, the method described here can be used to predict time-domain
waveforms accurately prior to hardware prototyping.
CHAPTER 6
DYNAMIC NOISE IMMUNITY, AND
SKEWING/DAMPING SSN WAVEFORM
6.1 INTRODUCTION
In high-speed, high-density CMOS VLSI chips, many output drivers
may switch simultaneously. Due to package parasitics, when these outputs
switch simultaneously, a significant amount of power/ground noise may be
generated in the package VDD /Vss planes and also in the internal (on-chip)
VDD/VSS busses. Note that simultaneous switching noise characteristics (i.e.,
amplitude, width and damping behavior) not only depend on the drive strength
ofthese output drivers, but also depend on the package parasitics [6.1]. Unless
these power/ground noise fluctuations are controlled, simultaneous switching
noise can degrade or even limit the system performance.
In practice, several inputs (both TTL compatible and CMOS) may
share the same power/ground busses with the output drivers on chip. Note
that even if separate external (for output drivers) and internal (for input
receivers and logic) VDD /Vss busses are used, they may be connected through
the same VDD /Vss plane connections in multichip modules. Thus electrical
decoupling is not assured. Since TTL compatible input switching points are
centered around 1.2-1.6 volts, ground noise must be controlled carefully to
86
SSN OF CMOS DEVICES AND SYSTEMS
avoid false switching on TTL receiver inputs. To avoid such disaster, one has
to take into account the maximum noise immunity of these receivers. Due to
the device and associated parasiitcs, input receiver noise immunity depends
on both the amplitude and width of the noise spike. A general noise pulse
width vs. amplitude noise immunity curve is shown in Figure 6.1.
-->
Internal Logic
«
a.
E
«
Q)
Unsafe Region
If)
'0
Z
"'0
C
e
::J
19
Ground Noise Width, W (ns)
Figure 6.1 Typical input receiver noise immunity characteristics.
Recent studies have shown that when we scale down devices, due to the parasitics associated with CMOS circuits [6.2] noise immunity of these receivers
do not scale down linearly. To demonstrate this non-linear behavior, CMOS
receiver noise immunity design curves (for both CMOS and TTL compatible
inputs) are shown for different channel lengths in the following sections.
87
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
One way to control switching noise is to increase of bond connections
and package pins connected to power and ground. However, if the multichip
module is bond pad-package pin limited, the system designer may be confronted with the problem of having to minimize the power/ground fluctuations
by indirect reduction in the number of outputs switching simultaneously realized by delaying switching of some outputs. Usually high speed designs require
that many outputs be able to switch within one clock wait cycle (for example,
eight or sixteen bit data/address bus switching from FF-OO or FFFF-OOOO).
Because of (bonding+plane+pin) parasitics connected through the source end
of the output transi.stors, both power and ground noise generally exhibit underdamped oscillations. Underdamped oscillatory switching noise waveforms
are generated from each output, and noise from "early switching" outputs
generally superposes on noise generated by the switching of the "later switching" skewed outputs. The damping coefficient and frequency is a function of
multichip module parasitics. In order to damp out power and ground noise,
additional damping resistors may be used at the source end of both P and
N channel transistors of output drivers [6.3]. Design curves are shown to explain the trade-offs in using an additional damping resistor and the effects of
skewing outputs in high-speed output driver designs.
6.2 DRIVER SWITCHING NOISE AND RECEIVER NOISE
IMMUNITY
Consider n CMOS output drivers switching simultaneously with several different (drive strengths) and switching speed. Assume each output is
switching symmetrically around the point To (any arbitrary time). Using an
equivalent lumped (R,L,C) model for package parasitics from on-chip Vss bus
to the end of the package Vs s pin, it can be shown that the ground noise produced by n number of output drivers simultaneous switching noise Vn is given
by [6.4]
Vn
Vk
+
1
L1
p
n
L:;=1
K·
T;
[1 -
1
+
2 Vk
n &
L: ;=1
Ti
p
L1
(6.1)
88
SSN OF CMOS DEVICES AND SYSTEMS
where Ki
= J-!nCox(Wj L)
for the
ith
N-channel output driver device and
p is the number of Vss bond pad-package pin (one-to-one correspondence
between chip-plane bond and package pin) connections. Here T; is the time
taken for the
ith
switching current spike to travel from zero to its maximum
peak value, Ll is the effective inductance of each Vss pad-pin connection and
Vk = Vin - Vi (Vi is the threshold voltage of the N-channel device). A very
useful ratio (relating nand p) can be derived [6.4],
p
",n
(6.2)
K;
L.,i=l T;
From here on only ground noise and ground noise immunity is analyzed. It
is clear from equations (6.1) and (6.2) that ground noise exhibits sub-linear
behavior as a function of both n (number of outputs switching) and p (number
of pad-pin connections). The negative feedback mechanics which cause such
sub-linear behavior are explained detail in [6.1],[6.4].
5.0
40
c
OJ
(/)
'03.0
z
'C
c:
e 2.0
::l
<.!)
1.0
Wp/WN =303/196
CL = 25pF
0.0 ' - - - - - - ' - - - - - - ' - - - - ' - - - - - - ' - - - ' - - - - - ' - - - - - - ' - 5
10
15
20
25
30
o
35
Numberof Simultaneous Switching, N
Figure 6.2 Ground noise vs. number of simultaneously switching outputs.
89
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
In Figure 6.2, ground noise is plotted as a function of number of simultaneously switching outputs for different channel lengths. A 1.0 ns rise time and
L 1 /p=2.5 nH were used for SPICE (with typicallevel-2 device parameters)
simulations. Note that L is used for output driver channel length in Fig-
ure 6.2. Note that from equation (1) as n approaches infinity, ground noise
approaches Vk (:::::: 4.0 V). As we scale down the output devices (to minimize
delay), ground noise approaches Vk at a faster rate for small geometry devices.
When the drive strength and/or the number of outputs simultaneously switching increases, ground noise increases. A detailed analysis of
switching noise behavior with device scaling is contained in [6.2]. From equation (1), one method to reduce the ground noise is to increase the number of
Vss pad-pin connections. This method can be expensive due to the increase
in number of Vss chip-bond pads and package pins. To have a reliable system,
one needs to specify the maximum tolerable ground noise. To specify such
values, it is essential to understand the noise immunity of the devices which
are connected through the same Vss busses and planes.
2.5
2:
«
W
"02.0
.~
Ci
E
«
Q)
en
1.5
'0
Z
"0
C
:::J
e
t!>
0
.~
1.0
,r-W-P;-W-=-10-/-35-'1
L=0.25fLm
N
~ ~ Multiehip Module Porosities
00 '--_ _-'---_ _..I-_ _..I-_ _-'--_ _---1-_ _---1-_
o
234
5
6
_+_
Noise Width, W (ns)
Figure 6.3 TTL level compatible CMOS receiver noise immunity behavior.
SSN OF CMOS DEVICES AND SYSTEMS
90
In Figure 6.3, TTL level compatible (switching point around l.2-l.6
V) CMOS receiver noise immunity characteristics are shown. This receiver is
connected to internal logic. A CMOS inverter (switching point around 2.22.S V) was used as a representative of internal logic. Typical lumped package
parasitics (R=l mQ, L=5 nR, and C=l pF) were used for SPICE simulations.
Note that the critical noise amplitude and width curve is where the receiver
triggers the internal logic. The region (corresponding amplitude and width)
above the immunity curve will lead to false switching, while below the curve
it is safe. For noise pulse widths less than 2 ns the receiver can tolerate larger
noise amplitudes compare to widths greater than 2 ns. For widths greater
than 3 ns, the noise immunity is fixed at a certain amplitude. This makes
sense since the noise levels the receiver sees are a constant voltage level for a
"long" period of time.
G
c:{
4
a>
'0
::J
:!::
0. 3
E
<{
Q)
II)
'0
z
'0
L= 5fLm
2
C
::J
.:::::::::===~ L = 2 fLm
<.9
-.::============:'!'" L =0.5 fLm
L= IfLm
....
0
0
u
,'--W-p/-W-N-=-30-3-/-19--'61
+-
'':
'L= 025 fL m
U
0
0
23456
Ground Noise Width, W (ns)
Figure 6.4 Effects of ground noise feed-through from D.C. "ON" drivers.
In the previous noise immunity curves, the ground noise was injected
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
91
into the input of the receiver. The reason for this is that while many outputs
are switching simultaneously some of the outputs can be D.C. "ON". These
D.C. "ON" drivers can permit feed through of the ground noise (N-channel
device acts as a resistor) onto the input of the receivers. In Figure 6.4 the
D.C. "ON" driver ground noise feed through is shown. It is assumed (for
worst case) that this driver is connected to a TTL compatible CMOS receiver
placed close to the driver (neglect the attenuation and dispersion of noise
spikes due to traces connecting them) in a multichip module. As expected,
ground noise with pulse widths less than 3 ns can tolerate larger amplitudes
compared to pulse widths greater than 3 ns. The exact cut-off point can vary
for different technologies. This is because the cut-off point depends on the
parasitics associated with the device. However the trend is similar and it is
shown in Figure 6.4 for different device channel lengths.
6.3 EFFECTS OF SKEWING OUTPUT DRIVERS
If a system design permits the designer to skew (within one clock wait
cycle) some of its outputs, then not all outputs are switching together at point
To. For the simplest case, consider two outputs with one switching at To and
the other at To + /j.T (skewed by /j.T time). Due to the R,L,C circuit on the
ground path, switching current obeys the differential equation [6.5]
L d2 I(t)
---;;;r +
R dI(t)
dt +
cI(t)
== 0
(6.3)
Notice, for most package parasitics,
L
R2 - 4 -
C
<
0 ,
and the waveform follows an underdamped oscillatory behavior. This underdamped current waveform damps out with a damping coefficient of R exp( :if)t
and has period which decreases with time. The quasi-period (T/) for an impulse response is [6.5]
T/
(6.4)
92
SSN OF CMOS DEVICES AND SYSTEMS
where the quasi-period is defined as the first (maximum) period of the underdamped current waveform. Knowing the underdamped characteristics for
the switching current and neglecting the effect of resistor
(~
1mn) on ground
nOIse
(6.5)
one can calculate the oscillatory behavior of ground noise. The corresponding
quasi-period for damped ground noise (Td) is Td ~ T/ /2 [6.4].
Note that ifthe oscillation is a periodic waveform (without damping),
when outputs are skewed by ilT time, the minimum ground noise would occur
at ilT=T, 3T, 5T, ... where T is defined in Chapter 3.0. However, for a quasiperiodic waveform (damping), there will be a global minimum followed by
several local minima. This is because amplitude of an underdamped ground
noise waveform decreases with time.
To minimize the switching noise by
skewing outputs, it is important to skew the outputs with appropriate ilT
to achieve this global minimum. For quasi-periodic underdamped oscillations
described by equation (3), the global minimum occurs at ilTs , where
ilTs
and
T/
T{
~ '12
[T
+
fT '] '
(6.6)
is an average half quasi-period of the damped ground noise. Notice
only depends on the package parasitics, and T depends on both package
parasitics and output driver strength. To demonstrate the effects of skewing,
a case of eight similar outputs switching was simulated using SPICE. In this
example four outputs switch simultaneously at To and the other four outputs
switch simultaneously at To
+ ilT.
Using equations (6.4), (6.6) and with
lumped package parasitics R=l mn, L=5 nH, and C=l pF, the global minimum ground noise occurs when ilTs=0.78 T. In Figure 6.5, ground noise is
plotted as a function of ilT, where T for 2.0 pm and 0.25 pm channel length
output drivers are different. Results from SPICE simulations and use of the
quasi-periodic waveform technique agrees well. For scaled devices, and/or
more than four outputs simultaneously switching, ground noise can be reduced significantly by skewing half of the output drivers with ilTs time. For
commonly used packages and typical drive speeds, ilTs is in the order of 1-2
93
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
ns. When the output switching speed increases, T decreases and thereby
flTs
decreases.
Wp/WN=303/196
CL=25pF
Cl.
.a 3
OJ
en
'0
Z
-g2
e
<.9
~
E
~
E
x
o
~
O~------------~------------~------------~--~
o
T
2T
Skewed Time, 6T (ns)
3T
Figure 6.5 Effects of skewing CMOS output drivers.
6.4 TRADE-OFFS IN USING DAMPING RESISTOR
For a given CMOS technology, once the device sizes are chosen for
speed, switching noise is limited by that output driver device size. To show
this limit, a simple CMOS output driver was simulated for a specific load
(CLoad=O.25 pF) with different drive strengths (Wp varied while Wp/Wn =
1.54 and L=1.0 pm). The output driver was simulated with and without
damping resistors using 1 ns rise/fall times. Notice when Rd
= 0 (see
Fig-
SSN OF CMOS DEVICES AND SYSTEMS
94
ure 6.6 for definition of Rd), the trade-off between speed and ground noise
(proportional to dI/dt) is limited by the top curve in Figure 6.6.
(Output Driver Final Stage)
250
Rd
200
+----0 Out
Ii>
c
"-
<I: 150
Rd
E
+-
"0
"-
H
"0
100
50
CL=25pF
L = 10fLm
Wp/WN =1.54
Rd
=Damping Resistor
O~--------~--------~--------~----------L---~
00
0.5
10
Average Delay
<t
15
+t
>
PHL
PLH
(ns)
2
2.0
Figure 6.6 Performance vs. switching noise limitations on output drivers.
Use of an additional damping resistor at the source end of the output driver
transistor can reduce the ground noise without any trade-off in speed. However output driver device sizes have to be increased to achieve the desired
speed and sink/source current capabilities. These damping resistors (10-100
[2) can be realized with small silicon area using diffusion resistors. If silicon
area is not a criteria, poly interconnect resistor can be used as a damping resistor. Poly interconnect resistors provide smaller variations on the resistance
values with process/temperature variations compare to diffusion resistors [6.3].
95
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
In Figure 6.7, the two output drivers simultaneously switching case
was simulated to show the trends in ground noise behavior with and without
damping resistors.
(2 Output Drivers Simultaneously Switching)
0.8
Wp/WN = 303//96
0.6
>
........
L =1.0fLm
CL =25pF
Rd=on
0.4
Q)
(/)
0
z
0.2
-0
c
~
0
~
0.0
(,9
-0.2
-0.4
0.0
0.5
/.0
Time (sec
1.5
X 10- 8 )
2.0
2.5
Figure 6.7 Underdamped oscillatory ground noise behavior.
The output driver sizes (Wp=303 /Jm, Wn=196 /Jm, and L=1.0 /Jm) were
selected to drive CLoad=25 pF with an average delay [(tpLH
+ tpHL)/2]
of 2
ns. Note that ground noise reduces by 40 % when a 50 r2 resistor is used, and
for a 100 r2 resistor the noise reduces by 75 %. Even with 100 r2 damping
resistor, to drive the same load (CLoad=25 pF) in 2ns average delay time,
the drivel' sizes only need to be increased to Wp=345 /Jm and Wn=224 /Jm.
96
SSN OF CMOS DEVICES AND SYSTEMS
It is clear from Figure 6.7, as we increase the number of outputs switching
simultaneously, the use of an additional damping resistor can greatly reduce
the noise without degrading the switching speed. The trade-off is in silicon
area to increase the channel widths of the output driver circuit and realization
of damping resistors using either poly interconnect or diffusion resistors. In
Figure 6.8, ground noise is plotted as a function of the number of outputs
switching simultaneously for different values of damping resistors.
(With and Without Damping Resistor)
5.0
4.0
Wp/WN=303/196
L = 1.0fLm
CL=25pF
>
~
<I>
'6
z
3.0
'0
C
::J
o
15
2.0
Rd=50n
Rd=loon
1.0
0.0 '-'-_ _"--_ _-'--_ _-'--_ _--'--_ _-'--_ _--L-_ _--L-+o
5
10
15
20
25
30
35
Number of Simultaneous Switching, N
Figure 6.8 Effects of damping resistor on the switching noise.
A 1.0 ns rise time and L 1 /p=2.5 nH were used for SPICE simulations. As
expected, the ground noise decreases for larger values of damping resistors.
NOISE IMMUNITY, AND SKEWING/DAMPING SSN
97
Selection of damping resistor value to reduce the ground noise depends on
specific system requirements on speed, noise levels, area, and sink/source
capabilities of output drivers.
6.5 SUMMARY
A detailed investigation into the maximum tolerable ground noise was
presented using noise immunity curves. A rule-of-thumb on skewing outputs
was derived to minimize the switching noise by skewing outputs. Use of an
additional damping resistor in the output driver circuit to reduce the switching
noise was demonstrated. Trade-off's in using an additional damping resistor
were analyzed.
CHAPTER 7
APPLICATION SPECIFIC OUTPUT
DRIVERS TO REDUCE SSN
7.1 INTRODUCTION
As we scale down CMOS devices into the sub-micron region, the
operating frequency of an output driver increases (frequencies over 60 MHz)
which translates to reduction in rise/fall times and pulse width. For a 5 V
supply, this corresponds to an output transient time less than 0.4 VIns for
=
=
a given load capacitance (i.e. 7 r
7J < 2.0 ns for CLoad
25 pF). As
explained in the previous chapters, SSN must be limited within the maximum
allowable noise level. Unless power and ground noise are controlled, reliable
operation of logic devices that are connected to the same VDD /Vss busses is
not guaranteed. Some of the en counted problems with false-operations due
to simultaneous switching noise are; 1) false triggering, 2) double clocking,
and/or 3) missing clocked pulses [7.1].
Some techniques to reduce simultaneous switching noise are explained
in the previous Chapters. Notice that each technique has its own advantages
and its limitations. As we switch more and more high current drive outputs,
not only a low effective inductance "Lv ss" is essential, but also clever circuit designs to control the rate of change of switching current (di/ dt) through
device-package VDD /Vss is essential to reduce SSN. Two different custom
SSN OF CMOS DEVICES AND SYSTEMS
100
output driver design methodologies are often practiced in Application Specific Integrated Circuits (ASIC'S) [7.1J; 1) Current Controlled (CC) output
driver [7.2]' and 2) Controlled Slew Rate (CSR) output driver [7.3J. In this
Chapter both the current controlled, and the controlled slew rate output driver
design methodologies are investigated in detail. In addition to reduce SSN,
circuit design techniques have also been used to control the reflection noise by
controlling the output rise/fall times of the output drivers [7.4],[7.5J. Circuit
design techniques are often used to minimize SSN in high-speed, packaged
CMOS memory devices [7.6][7.7]. Application specific, tri-statable controlled
slew rate CMOS output drivers were designed, and their performance and SSN
are analyzed in detail. Performance and SSN ofCSR output drivers were compared with conventional (current unregulated) output drivers. Advantages in
using these CSR output drivers to switch a large number of outputs (> 32)
are explained.
7.2
CMOS OUTPUT DRIVER SWITCHING CURRENT
COMPONENTS
In order to design application specific Current Controlled (CC) or
Controlled Slew Rate (CSR) output drivers, it is essential to understand the
output driver switching current components. Note that the rate of change
of switching current (di/dt) is proportional to the ground noise for a given
package design (Lvss fixed). As explained in Chapter 3, both the through
current (also known as the overlap current) Ir, and the charging/discharging
current ID contributes to the total switching current through the VDD /Vss
device-package interface. To demonstrate the impact of these current components on the total switching current, a standard CMOS output driver (for
1-/-l m Lefj: Wp=250, WN=160) with 1 ns input risetime was used [7.1J.
The simple final stage of a CMOS output driver circuit is shown in Figure
7.1a. Three different capacitive loadings were selected for this study. Output
voltage switching characteristics are shown in Figure 7.1b for CLoad=O, 25,
100 pF using curves A, B, and C respectively. Switching current through the
Vss device-package interface path (source end of the N-channel transistor) is
plotted in Figure 7.1c.
Notice that since both the final stage P-channel and
APPLICATION SPECIFIC OUTPUT DRIVERS
In~
101
Oul
(0 )
6
5 I--_t"oo...
>4
-'------,:-----:-
Input
~3
~2
1
O~~~~-~~~-~-+
o
2
4
6
Time (ns)
8
10
(b)
28
24
x-x_x©
"x
-<t 20
16
E 12
H
8
.........
4
O~----LJ'----'L-...I_----'-~-...L
o
2
4
6
Time (ns)
8
_
_L___+
10
(c)
Figure 7.1 a) CMOS ouput driver switching characteristics. b) Voltage switching characteristics. c) Current switching characteristics.
SSN OF CMOS DEVICES AND SYSTEMS
102
N-channel transistor inputs are connected to the same node (gates are tied
together), and therefore through current is not minimized. This effect is
illustrated in Figure 7.lc where the rising edge of the total switching current
is controlled by the through current for all three capacitive loadings. Because
of this, the maximum di/dt is almost same for CLoad=O, 25, and 100 pF.
However, when the through current is turned-off, total switching current is
controlled by the discharging current, and this effect is evident from the falling
edge of the total switching current shown in Figure 7.1c.
The through current is the component of the output driver current
that flows directly from the Vvv to Vss. Note that this current does not
contribute to charge or discharge the load capacitance, but contributes to
the switching noise. This through current is present when both the P-channel
and the N-channel transistors are in saturation region and momentarily "ON" .
For a clean (not noisy) Vvv and Vss on-chip buses, the N-channel saturation
current is [7.8]
(7.1)
where J{N = J-!nCox('Y), Vg is the gate voltage, and vtn is the N-channel
transistor threshold voltage. Similarly, the P-channel saturation current IS
[7.8]
(7.2)
where J{p = J-!pCox('Y), and vtp is the P-channel transistor threshold voltage.
It has been shown that by requiring that Ip = IN, the switching voltage VGT
is [7.9],
v,
GT
- VKP Vvv + VKN vtn - VKP vt p
)J{p + -jJ{N
(7.3)
The maximum through current h(max) is given by [7.9],
(7.4)
The discharging current (Iv) when the output switches from Vvv to 0 volts
IS,
Iv = CLoad
dV
dt '
(7.5)
APPLICATION SPECIFIC OUTPUT DRIVERS
or, approximately,
ID
where
7]
~
VDD
CLoad - -
(7.6)
7]
is the output fall time. Notice that
7]
103
is a function of CLoad.
7.3 CURRENT CONTROLLED OUTPUT DRIVERS
The objective of a Current Controlled (CC) output driver is to control
the maximum switching current Imax of the switching output. Here
Imax
=
max [Ir, ID] .
(7.7)
Notice, controlling the switching current also limits the switching speed of the
output driver. For example, if the maximum switching current is limited to
Imax then for a given load capacitance CLoad, the output switching transient
is limited by,
7
=
(7.8)
In Figure 7.2, a typical current controlled CMOS output driver circuit is
shown. For the current controlled output driver circuit shown in Figure 7.2,
the charging and discharging currents are limited by Ip(max) and IN (max).
Here Ip(max) and IN(max) are realized using simple current mirrors [7.10].
From equation (7.8), the output driver rise/fall times are limited to,
7r
=
CLoad VDD
Ip(max)
(7.9a)
7]
=
CLoad VDD
IN(max)
(7.9b)
and
The increase in output transient time, and the realization of a low Vol for a
given 101 are major limitations in using current controlled output drivers. Note
that the switching speed of a fully current controlled output driver is always
less than or equal to the switching speed of an equivalent current unregulated
output driver.
104
SSN OF CMOS DEVICES AND SYSTEMS
In.---------------------~
- - - - - - - - - - - - Out
Vss
Figure 7.2 Current controlled CMOS output buffer.
To have both the current unregulated (when switching current is lower
than Imax) for the slower switching conditions, and the controlled (switching
current is equal or greater than Imax) for the faster switching conditions, a
complimentary switch is designed. In Figure 7.3, due to symmetry, only the
sink portion of the current controlled output driver circuit with a complementary switch is shown. Notice that input signal to the output driver controls
the switch to turn ON and OFF the unregulated (P2, N3, and N1 OFF) and
the controlled (P2, N3, and N1 ON) switching current.
105
APPLICATION SPECIFIC OUTPUT DRIVERS
-----.q
t------Out
I n - -....
Figure 7.3 Switching current controlled/unregulated CMOS output driver.
7.4 CONTROLLED SLEW RATE OUTPUT DRIVERS
The objective of a Controlled Slew Rate (CSR) output driver is to
control the output driver's switching rise and fall times. To control the rate
change in switching current (di/ dt) by controlled slew rate, designer has to
make sure that the output driver design is not limited by the through current.
This can be achieved by not connecting the gate terminals of the output stage
106
SSN OF CMOS DEVICES AND SYSTEMS
P-channel, and the N-channel transistors and making sure that there is a skew
between the P-channel and the N-channel turning OFF JON and ON/OFF
times. In Figure 7.4, a commonly used tri-statable (with enable high) CMOS
output driver circuit is shown.
Out
Data
Enable
1-01.--------- Pre-driver-------1..~II-O.-f--- Driver~
Figure 7.4 A typical tri-statable (enable high) CMOS output driver.
In practice, the pre-driver VDDjVSS are connected to the internal (also called
clean) VDDjVSS buses, and final stage output driver VDDjVSS buses are connected to external (also called noisy) VDDjVSS buses. This is because, final
stage driver device sizes (channel width) are very large compared to the internal or even to the pre-driver device sizes. As explained in Chapter 3, increase
in channel width increases the drive strength, and also increases the switching
APPLICATION SPECIFIC OUTPUT DRIVERS
107
nOIse.
However, increase in final stage output driver device sizes also increases the input capacitance of these devices. The increase in input capacitance of the final stage may demand a larger drive strength pre-driver's
compared to the internal gates drive strength to minimize the delay of the
overall output driver [7.1]. Note that NAND, NOR, and other logic gates (except inverters and pass transistors) require larger silicon area with high input
capacitance compared to simple inverter to achieve a certain current drive. A
high-speed, tri-statable (with enable low) CMOS output driver circuit utilizing the inverters for pre-driver's is shown in Figure 7.5.
Enable
Out
Data
1-0.1------1
Pre-driver------.H-ol.I---Driver----+l
Figure 7.5 High-speed, tri-statable (enable low) CMOS output driver.
The functionality of these tri-statable drivers shown in Figures 7.4 and 7.5
SSN OF CMOS DEVICES AND SYSTEMS
108
are given in Tables 7.1 and 7.2 respectively.
Table 7.1 Tri-statable (enable high) CMOS output driver (Fig. 7.4).
Enable
1
o
o
Out
x
Z
1
1
o
o
Table 7.2 High drive, tri-statable (enable low) CMOS output driver (Fig. 7.5).
Enable
Here x
Data
Out
0
x
Z
1
1
0
0
1
1
= don't care and Z = high-impedance or high-Z state.
It is important to skew the arrival times of the input signals of the
final stage to minimize the output driver through current component. This
can be realized by selecting an appropriate pre-driver device sizes. Skewing
the switching time at the final P-channel and N-channel transistors give rise to
the overall delay. However, for high current drive output drivers, with a little
trade-off in delay, significant reduction in switching noise can be realized. In
Figure 7.6, a typical tri-statable output driver voltage and current switching
characteristics are shown for a standard, and reduced through current output
drivers.
Even with reduced through current output drivers, there exist a
delay-SSN limitation. This is because increase in final output driver device
channel widths to reduce the overall delay increases the switching noise. In
Figure 7.7, delay-SSN curve for a 8.0 rnA (D.C. sink for Vo /=O.4 v) tri-statable
output driver is shown. This delay-SSN limitation can be a major limiting
factor in a system design, especially when a large number of high current
drive outputs switch simultaneously. It is important to control the maximum
switching current
Imax,
and also the time it takes for this current spike to
109
APPLICATION SPECIFIC OUTPUT DRIVERS
v
(Volts)
Time (ns)
(a)
I
(rnA)
Time (ns)
A: Standard Output Driver
B: Reduced Through-put Current Output Driver
(b)
Figure 7.6 Tri-state output driver (a) voltage, and (b) current switching characteristics.
SSN OF CMOS DEVICES AND SYSTEMS
110
ai
at
(~:)
100
80
60
40
20
OL-----~----~------~--
o
2
4
6
__
~
______
8
L __ _ _ __ L_ _ _ __ .
D
(Pre-driver + Driver) Average Delay (ns)
12
Figure 7.7 Driver delay-switching noise limitations.
reach its maximum value (T) to reduce the "effective" simultaneous switching
nOISe.
In Figure 7.8, Controlled Slew Rate (CSR) tri-statable CMOS output
driver circuit is shown. Functionality ofthis driver is given in Table 7.1. These
CSR output drivers were designed for the following drive strengths; 1) PLIO
(3.2 rnA D.C. sink for Vo l=O.4 v), 2) PLI03 (8.0 rnA D.C. sink for Vo l=O.4
v), and 3) PLI05 (12.0 rnA D.C. sink for Vo l=O.4 v). As shown in Figure
7.8, in these CSR output driver designs, final output stage of these drivers
are split into several driver segments. It was found, when the current drive of
the drivers increase, the number of optimal segments required to control the
"effective" dijdt also increases [7.11]. Simulations have demonstrated that
111
APPLICATION SPECIFIC OUTPUT DRIVERS
more than three driver segments in the final stage is useful only when the
output current drive is greater than 32 rnA (D.C. sink for Vo/=OA v), and
driving a load capacitance of 25 pF or greater [7.11].
~--------~----------~----~~Ouj
Daja
Enable
Vss
Driver #1
Driver #2
Driver #3
Figure 7.8 Tri-statable, Controlled Slew Rate (CSR) output driver.
A final output driver stages using there driver segments (as shown in
Figure 7.8) was used in PLIO, PLI03, and PLI05 CSR output driver designs.
The weighted ratio of 1:2:3 was selected for driver segment (1, 2 and 3) device
sizes respectively. For example, for a conventional PLI05 driver Wp=624 /lm
and WN=414 /lm , the following device sizes were selected for the CSR PLI05
driver stages; 1) Wpl=104 /lm, WN1=69 /lm, 2) Wp2=208 /lm, WN2=138
/lm, and 3) Wp3=312 /lm, WN3=207 /lm. Similar weighting scheme (1:2:3)
SSN OF CMOS DEVICES AND SYSTEMS
112
was used to calculate the device sizes of final stage output driver segments of
the PLI03 and the PLIO output drivers. Notice that the increase in driver
device sizes increase the input capacitance, and this act increases the delay
time between each driver segment's switching time D..T. For example, if N
or P-channel transistor in driver stage number one switches at To (arbitrary
time) time, then second driver switches at To + D..Tl time, and the final (or
third) driver switches at To + D..T2 time. Note that all the P-channel and
N-channel transistors in each driver segments are designed to minimize the
through current on all driver segments. The input capacitance (CJ) of each
stage is proportional to,
CJ = k Wtotal Cunit
(7.10)
where Wtotal=total channel width, k=fringing factor, and Cunit=per-unitlength capacitance for a given CMOS technology (Lell fixed). With the
switching point centered around V~D volts, and using RC tree, delays between
segments can be calculated [7.12].
(7.11)
N
D..T2
~
Rl
= 2'1
(Cr + Cr) +
"T P2
L.),
N3
R4 CJ
~
R3
= 2'1 R 3 CP3
J
(7.12)
,
cr ,
and
(7.13)
(7.14)
where the supercripts on D..T and CJ denotes the P or N-channel transistor.
Note that the appropriate D..T value can be realized by adjusting the
driver segments device sizes (vary CJ), and/or changing the resistor (RJ)
values. The selection criteria depend on the trade-offs between the driver
delay and the simultaneous switching noise for a specific application. In this
work, a standard 1 KD resistance was used for all four resistors. Even though,
poly resistors (sheet) have little variation with process and temperature (~
60 ± 20D), diffusion resistors (sheet) (~ 130 ± 35D) were used to save silicon
APPLICATION SPECIFIC OUTPUT DRIVERS
113
area. Note that to control the slew rate by adjusting the !J.T, the ratio between
resistors are important, and not the absolute value.
5
4
2
°OL-----2L-----4L-----6L-----L8-----llO--~~IL2----~IL4-----+
Time (ns)
Figure 7.9 CSR output driver voltage switching characteristics.
4'
S
102
---------------
Conventional
I
I
I
1
1
--r"
1
~I~H~
I
a
____ T--->-l
.t--------- T + LIt
""I
CSR
•1
Time (ns)
Figure 7.10 CSR output driver current switching characteristics.
SSN OF CMOS DEVICES AND SYSTEMS
114
In Figures 7.9 and 7.10 a typical CSR output driver voltage and current
switching characteristics ate compared with the conventional output drivers.
As expected, including the additional resistors (R 1 , R 2 , R3 and R 4 ) n the output driver design increases the driver delay for a given load capacitance. However these delays are very small compared to the "effective" switching noise
pulse width reduction. A typical lumped PGA package parasitics (Lv ss=5
nH, Cvss=l pF, and Rvss=l mn), and CLoad=100 pF were selected for
the SPICE simulations. These CSR output driver's performance-noise values are compared with the conventional output drivers, and the results are
given in Table 7.3. Note that even though there is not much reduction in the
maximum switching noise amplitude, more than 50 % reduction in the noise
pulse width was realized using CSR output drivers. From the noise immunity
curves shown in Chapter 6, it is clear that larger number of simultaneously
switching CSR outputs can be integrated safely compared to the conventional
output drivers for a noise limited system design.
Table 7.3
Performance-SSN comparison of conventional and CSR output
drivers.
Driver TY12e
PLIO
"
"
"
PLI03
Performance-Noise
Delay [lh+hlJ/2 (ns)
Conventional Driver
9.6
CSR Driver
10.3
3.5
3.4
Noise Pulse Amp. (mV)
430
424
Noise Pulse Width (ns)
1.3
0.7
Delay [lh+hlJ/2 (ns)
7.5
7.8
Sink/Source (rnA)
9.2
8.3
Sink/Source (rnA)
"
"
Noise Pulse Amp. (mV)
655
637
"
Noise Pulse Width (ns)
1.6
0.9
Delay [lh+hlJ/2 (ns)
4.9
5.1
Sink/Source (rnA)
12.5
12.1
Noise Pulse Amp. (mV)
800
741
Noise Pulse Width (ns)
2.0
0.8
PLI05
"
"
"
APPLICATION SPECIFIC OUTPUT DRIVERS
115
7.5 SUMMARY
Detailed investigations on the CMOS output switching current components, and their impact on the simultaneous switching noise were performed. Current controlled output driver circuit design technique and its
capabilities and limitations are explained. Controlled slew rate output driver
design technique, and methods of realizing skewing times between driver segments are given. The advantage in using controlled slew rate output drivers
over the conventional output drivers to minimize the "effective" simultaneous
switching noise was demonstrated.
CHAPTER 8
SSN SIMULATOR ARCHITECTURE
8.1 INTRODUCTION
In previous Chapters, methods of calculating Simultaneous Switchmg Noise (SSN) for CMOS based systems, and some techniques to reduce
SSN were discussed. Note that these techniques require some trade-offs in the
maximum clock frequency or in the silicon area to reduce SSN. As we scale
down CMOS devices (Lejj
<
111m) with the reduced-supply-voltage (3.3 or
2.0 volts), and increase the maximum operating frequency (Ie) together with
increase in data/address bus width (> 32-b switching), SSN to signal ratio
increases rapidly. Increase in noise to signal ratio can be a limitation in high
level integration Multi-Chip Modules (MCMs) [8.1)[8.2]. For high level integration CMOS systems, it is essential to minimize SSN by using several
techniques, such that SSN is minimized and within the acceptable limits. For
a given number of bond-pad and package-pin VDD /Vss connections, SSN can
be reduced with proper placement of bond-pad and package-pin connections.
An optimal placement minimizes the effective inductance "Lv ss" by minimizing the mutual inductive elements in the inductance network. In addition,
SSN can also be minimized by using application specific output drivers instead of conventional output drivers [8.3]. Measurements and simulations
have demonstrated that the use of internal (plane-to-plane) and/or external
118
SSN OF CMOS DEVICES AND SYSTEMS
decoupling capacitors also reduce the overall SSN [8.4] [8.5]. To implement
any of these techniques to reduce SSN, system designers need to incorporate
these techniques at the early stages ofthe system design. This is because these
implementations may alter other performance metrics (mechanical, thermal,
reliability and cost), and may require formal reliability and quality assurance
verifications [8.6]. A Simultaneous Switching Noise Simulator (SSNS) based
on a trial architecture was designed to calculate SSN and to minimize SSN by
using several techniques explained in the previous Chapters. A software tool
(C program) was developed to verify the functionality of each modules in the
architecture, and to assure the overall flow through this architecture. Note
that this tool is intented for early system simultaneous switching noise analysis, and/or to guide system designers in the selection of appropriate detailed
(computationally expensive) simulations for final verifications.
8.2
SIMULTANEOUS SWITCHING NOISE SIMULATOR
(SSNS) ARCHITECTURE
In Figure 8.1, a trial architecture to calculate SSN for a CMOS based
system is given. Note that, this SSNS architecture requires an "effective"
chip-package inductance (Lv ss) as seen by the output driver's in their Vss
path. In Chapter 5, a method to reduce the chip-package Vss connection
inductance network to an equivalent "effective" inductance for a single chip
package was explained. A method of modeling "Lv ss" using similar techniques (as explained in Chapter 4.0) for MCMs is explained in the following
section. Knowing the chip-package interface "Lvss", and the output driver
device and switching characteristics, SSN can be calculated using the methodology explained in Chapter 3. Note that these models include the output
driver negative feedback effects which are important in calculating the SSN.
Using the above methodology, SSN can be calculated on the on-chip VDD /Vss
buses, or at the package VDD /Vss planes. As explained in Chapter 3, the internal gates switching current, and the D.C. "ON" sink/source current also
contribute to the overall SSN. In SSNS architecture, the D.C. "ON" driver
SSN SIMULATOR ARCHITECTURE
r---------~
119
Negative Feedback Equations
Iterative Noise Solver
D.C. ·ON· Driver Perturbation
Internal Switching Current
Power & Ground
Pads/Pins Calculator
YES
Figure 8.1 Simultaneous switching noise simulator (SSNS) trial architecture.
120
SSN OF CMOS DEVICES AND SYSTEMS
perturbations are included. This offset voltage is calculated using the D.C.
sink/source current and the switching current. For p number of D.C. "ON"
N-channel drivers with each sinking D.C. current I j in their Vss path, the
D.C. offset voltage is,
p
Voj jset
L
Ij(sink) Rvss
+
Irms(max) Rvss
(8.1)
j=l
where Irms(max) is the maximumroot-mean-square current, and
Irms(max)
=
IT(max)
V2
.
(8.2)
Note that it is very hard to calculate the internal switching current at any
given time exactly, and need an estimation of this current for a given system
design. There are empirical formulas relating the number of gates, design architecture, and device feature size to the internal switching current. However,
these empirical formulas are very specific for each CMOS chip design house's,
and in SSNS it is defined as a user specified information. In SSNS, knowing
the number of Vss connections, SSN can be calculated or vice versa.
For example, knowing the worst case outputs switching activity, and
the maximum tolerable noise, the minimum required number of pad-pin connections is calculated. If the calculated minimum number of pad-pin connections exceed the practical implementation limit, methods of reducing SSN by
skewing and/or damping switching noise waveform can be explored. Methods
of calculating SSN and trade-off in using these techniques are explained in
Chapter 6. In addition to these techniques, use of Current Controlled (CC)
or Controlled Slew Rate (CSR) output drivers also reduce SSN. The negative
feedback effects of CC and CSR drivers are very much application specific
(to broad to generalize), therefore not included in this version (1.0) of the
SSNS architecture. Knowing the minimum required number of Vss pad-pin
connections, one can further decrease SSN or the number of Vss pad-pin
connections needed for a given maximum tolerable noise level by utilizing an
optimal bond-pad/package-pin placements. Note that proper pad-pin placement can distribute SSN evenly on the VDD /Vss buses and the planes, and
121
SSN SIMULATOR ARCHITECTURE
also reduce SSN by reducing the mutual inductive elements in the "Lv ss"
inductance network ..
8.3 "Lvss" MODELING FOR MCM Vss CONNECTIONS
A typical MCM Vss connection system is shown in Figure 8.2.
,/
-
Vi;
Ch'IP- Pac kage Interface Level
ql =Number of Vias Abov
V
PI =q2= NumberofVias Between Vss#1 and Vss # 2
P2
'-'
Figure 8.2 Multi-chip module chip-package V ss connections.
A chip-package level with two Vss planes is selected for simplicity. Note that,
in all these Vss planes, there are qi number of source points (current into the
plane) and Pi number of sink points (current leaving the plane). In general
q, p, and their placements can be arbitrary, however there could be many
122
SSN OF CMOS DEVICES AND SYSTEMS
symmetries in their placements. The frequency-independent package plane
parasitic calculator UALGRL [8.7] was used to model the Vss planes. A
method of calculating the inductance network using a superposition method
for a single chip package with one Vss plane is explained in Chapter 4.0 [8.8].
A similar technique can be used here.
The inductance model for Figure 8.2 chip-package Vss connections is
shown in Figure 8.3.
o
CD
@
• ••
1
•••
I
I
2
•••
L~'one (K,. K2)
•••
1
Chip-Plane
(K 2-1)
Plane#1
1
K2 Vias
L~'one (K 2 • P)
Plane#2
I
2
•••
• ••
(P-I)
1
~
P
Pins
~
Figure 8.3 Multi-chip module "Lv ss" inductance network model.
There are
J{l
number of chip-package connections (including wire bonding,
TAB, or C4) to the first Vss plane. First Vss plane is connected to the second Vss plane with J{2 number of vias. Note that these J{2 number of vias
123
SSN SIMULATOR ARCHITECTURE
are source points and p number of pins coming out of this plane are the sink
points for the second Vss plane. In this first order model, it is assumed that
each source point on the Vss plane is at an equipotential, and each sink point
is also at a (different) equipotential. Also mutual inductance between neighboring Vss chip-plane connections, vias, and package-pins connections are
negligible. These assumptions are fulfilled if the sink points on the planes are
symmetrical around the source points, and each Vss connections are isolated
with VDD connections. This is because, current flow through VDD and Vss
chip-package connections are in opposite direction and this reduces or even
cancels out mutual inductance. Consider a MCM with N number of chips each
having qi number of chip-package Vss connections. H0re qi is a percentage
of the total number of I/O's. In addition, there are m number of Vss planes,
with adjacent Vss planes strapped together by means of l{i number of via
connections between plane i and i+1, and p number of pins connected to the
bottom most Vss plane. Using Figure 8.3, the effective inductance "Lvss"
as seen by the output driver is,
Lvss ~
L
~-p
Li=l qi
m-1
+
m-1
L j ,j+1
L: L~lane(l{i) + L: ~ +
i=l
j=l
J\.j
L
L;iane(P) +
pin
P
(8.3)
Here L c - p is the chip-package inductance for a single connection, Ltlane is
the inductance of the ith Vss plane inductance, L~'/a+1 is the inductance for
a single via connection between planes j and j+1, and Lpin is the packagepin inductance for a single connection. In this model, mutual inductance
between planes is not included. However, for unevenly distributed via or pin
connections on an MCM Vss planes, mutual inductance between planes need
to be incorporated in the Lvss model. Note that N=1 with m=l in equation
(8.3) corresponds to a single chip with one Vss plane connection.
8.4 SIMULTANEOUS SWITCHING NOISE CALCULATION
FOR CMOS MCM
Consider N number of "equivalent" CMOS chips in a MCM. Decrease
124
SSN OF CMOS DEVICES AND SYSTEMS
in channel length, and increases in data/address bus width from each chip
increases the SSN at the local chip site VDD/VSS buses. With increase in
number of chips and similar probability of outputs switching on other chip
sites, SSN increases on all global VDD /Vss connections. Uncontrolled SSN
may degrade or even limit the system performance. From CMOS SSN calculator given in Chapter 3, the maximum peak ground noise Vn for n number
of outputs switching simultaneously is,
Vn = Vk
1
1
+ -L-",n
Ki
VSS L...i=l Ti
[ 1-
n
1+2 Vk Lvss
L
i=l
I{-
T~
(8.4)
I
Here J{i = J-ln Cox (W/ L) for ith N-channel output driver device, T; is the
time taken for the ith current spike to travel from zero to its maximum peak
value, and Vk=Vin - Vt. Lvss is given by equation (8.3). Using equation
(8.1), the maximum peak simultaneous switching noise voltage at the on-chip
Vss bus is ,
VssN(max)
=
Vojjset
+
Vn .
(8.5)
To calculate workstation application MCM SSN, the following number of simultaneously switching outputs (n) was used.
n
= ~
(# of logic chips) (data/address bus width)
(8.6)
Note that this is not a worst case. It represents a typical case where either
the data or the address bus in 50% of the logic chips are switching from
low-to-high or high-to-Iow at a given arbitrary time T.
Rent's rule with appropriate constants (k and j3) for CMOS based
MCMs was used to calculate the total number of chip-plane connections N p ,
(8.7)
No is the number of chips in an MCM, and N 1 / O is the number of I/O's for
each chip. Note that only a certain percentage ofthese I/O's are Vss, and the
remaining I/O's are VDD and input/output signals. In practice, only a part
of these chip-package Vss connections are package Vss pins (i.e., there is no
SSN SIMULATOR ARCHITECTURE
125
one-to-one correspondence). In this work, it is assumed that the number of
Vss package pins are 50 % of the chip-plane Vss connections. Output driver
and package connection parameters used in these calculations are given in
Tables 8.1 and 8.2.
Table 8.1 MCM CMOS Chip Integration Parameters.
Parameter
Year 2000
1.0
0.5
0.25
3.3
2.0
(v)
±0.9
±0.6
±0.4
of I/O's
168
400
608
40
100
250
VDD
Vt
(v)
!chip (MRz)
foot print (cm)
# of logic chips
# of memory chips
memory /logic
#
Year 1995
5.0
Lefj (pm)
#
Year 1991
1. 75x1. 75
2.0x2.0
2.35x2.35
[4,8,12J
[4,8,12,16,20J
[4,8,12,16,20J
[16,32,48J
[16,32,48,64,80J
[16,32,48,64,80J
1
"6
of equivalent chips [6.6,13.3,20J
1
1
"6
[6.6,13.3,20,26.6,33.3J [6.6,13.3,20,26.6,33.3J
6
Table 8.2 MCM Integration: Driver and package parameters.
Parameter
#
Year 1991
of drivers switching [32,64,96J
data/address bus width 32/32
driver J{ (A/V2)
T (ns)
4.9x10- 3
Year 1995
[64,128,192,256,320J
Year 2000
[128,256,384,527,640J
64/64
128/128
9.8x10- 3
19.6x10- 3
1.0
0.7
0.5
1.0
0.7
0.5
Lplane (nR)
0.1
0.1
0.1
Lvia (nR)
0.1
0.1
0.1
Lpin (nR)
1.5
1.2
1.0
Lchip-plane (nR)
126
SSN OF CMOS DEVICES AND SYSTEMS
These parameters are extracted from many industry forecasts [8.1]. In this
work, the number of equivalent chips (N) is determined to be,
N = (# of logic chips)
+ ~
(# of memory chips) .
(8.8)
In Figure 8.4, ground noise is plotted as a function of integration level.
Note that, with increase in integration level in MCM, the total number of
chip-plane connections (Np ) and thereby the total number of Vss connections
increase. As expected, SSN increases with integration level together with the
increase in current drive capability. In Figure 8.4, 10 % (from N p ) chip-plane
and 5 % package-pin Vss connections were used for SSN simulations.
Number of "Effective Logic" CMOS Chips
o
10
5
15
20
25
30
35
o.-----~------~-----,-------.------.------.-------.--~
-5
Year 2000 Technology
_ _ _6:
co
-10
b:.
____ b:.----b:.
x
~x
oJ -/2 - - - - - - - - - - - - - - - en
~
Yearl~x
___
"0
"0
b:.
-15
~
x
______
X
~o
o~
<.!)
-20
----------------------
Year 1991 0
____
Vss Connections
10% Chip Package
5% Package-Pin
-25
Figure 8.4 SSN vs. MCM integration level (10-5 % Vss connections).
To explain the effects of number of Vss connections on SSN, in Figure 8.5,
SSN SIMULATOR ARCHITECTURE
127
SSN for 20 % chip-plane and 10 % package-pin
V55
connections are plotted.
Number of "Effective Logic" CMOS Chips
10
15
20
25
30
35
o
5
O.------r------.------,-------r------.-----~------~--~
____ 6-----
-5
~-IO
.~
-/2
~
-15
e
_____
6
Yearl995
~
------~------x~~~-~---- ~~-
x
~
Year 1991
____0
~o
(9
-20
Year 2000 Technology
6 _ _ _6
/"
°
x
---
Vss Connections
20% Chip-Package
10% Package-Pin
-25
Figure 8.5 SSN vs. MCM integration level (20-10 % V 55 connections).
In these Figures, -12 dB noise (SSN) to signal (clean VDD) ratio is denoted
by dash lines. Note that, pushing the noise to signal ratio beyond -12 dB can
lead to many unreliable operations.
From these results, it is clear that higher levels of integration increase noise to signal ratio. As expected, this ratio increases with reduced
supply voltage. Reduction in threshold voltage [8.9], and false triggering even
at narrower switching noise pulse in scaled CMOS devices can create many
challenges for system designers to reduce noise to signal ratio.
128
SSN OF CMOS DEVICES AND SYSTEMS
8.5 SUMMARY
A trial architecture to calculate simultaneous switching noise for
CMOS based systems, including SSN calculations for MCMs was presented.
Applications and limitations in using the SSNS were explained. A method
of calculating "Lv ss" for MCM chip-package Vss connections was modeled.
Trends in simultaneous switching noise to signal ratio were predicted for future
CMOS MCMs.
CHAPTER 9
SIGNAL CONDUCTORS OVER A NOISY
REFERENCE PLANE
9.1 INTRODUCTION AND MOTIVATION
To obtain a high system operating frequency, both integrated circuit and multi-chip module integration levels have increased. Higher levels
of integration puts stronger requirements on overall noise level for reliable
operation of devices that are integrated within a system. Often in practice
the worst case Simultaneous Switching Noise (SSN), and Coupled Noise (CN)
are calculated independently, and these values are added to the overall noise
budget calculations. With increase in device/chip integration, simple addition of worst case coupled and switching noise over-estimates their effect, and
may demand a decrease in the system operating speed for reliable operation
of these devices. It is essential to model the overall noise level with actual
driver/receiver circuits, and using a detailed chip-package interface model.
This is because the dynamic noise immunity of the input receiver not only
depends on the amplitude of the noise spike but also on its pulse width [9.1].
In this chapter, a method of modeling and simulation of coupled transmission line interconnects over a noisy reference plane is presented. Limitations
in using conventional coupled transmission line simulators to model signal
propagation over a noisy reference plane are explained. A distributed lumped
130
SSN OF CMOS DEVICES AND SYSTEMS
element circuit model including reference plane parasitics and associated coupling (to signal conductors) parasitics is developed, and verified using SPICE
simulations. Inductance and capacitance per-unit-Iength [p.u.l.] matrix elements are calculated using detailed two-dimensional parasitic extractors, and
the partial inductance concept. Results using this model were compared with
conventional "isolated" (switching noise isolated) coupled transmission line
simulations. Significant differences were found. Package-pin placement on
the reference plane, and its impact on overall noise characteristics are analyzed. Some work on modeling signal conductor noise from a reference plane
was reported by C. R. Paul [9.2]. This last work accounts for a constant
voltage drop along the plane and does not account for time varying switching
noise coupling through reference planes and also through D.C. "ON" (quiet)
drivers.
In this study, output driver VD D/Vss terminals are connected to the
package VDD /Vss planes. When these output drivers switch simultaneously,
switching noise is created on VDD/VSS planes. Because of this switching noise
on reference planes, these planes are no longer at zero or constant D.C. voltage, and are noisy. Due to the symmetry in power and ground connections,
here only signal propagation over a noisy Vss plane is analyzed. It is worth
mentioning here that in the case of packages with multiple Vss planes, often these Vss planes are connected together with vias (strapped together),
and thus de-coupling of switching noise is not assured. The basic modeling
approach followed in this work is to include the effects of switching noise
on reference planes and thereby analyze the signal propagation over a noisy
reference plane. Notice that all the conventional, TEM-mode transmission
line simulators require a clean (not time varying voltage) reference plane. To
surpass this limitation, a distributed lumped element circuit model was developed to model signal transients over a noisy reference plane. Typical 1 pm
technology CMOS driver/receiver circuits were used for this study [9.3].
Because of noisy reference planes, it is essential to include in the
electrical analysis both Vss plane parasitics and coupling parasitics to signal
lines. To calculate the self and coupling parasitics, the plane is modeled as
a very wide conductor beneath signal conductors as shown in Figure 9.1.
131
SIGNAL OVER A NOISY REFERENCE PLANE
Package Vss pins are assumed to connect this noisy Vss plane to a perfect
ground. Modeling techniques based on rigorous inductance and capacitance
calculators are explained in Section 9.3.
Vss Plane
I
1~~r---------------W2--------------~·~1
Figure 9.1 Interconnect cross-section geometry.
Simulation results using these models were compared with conventional "isolated" (switching noise isolated) simulation results, and differences are explained. Effects of Vss pin distribution on noise on the the Vss plane are
analyzed for various pin placements.
9.2 EQUIVALENT ELECTRICAL CIRCUIT MODEL FORMULATION
A. LIMITATIONS IN USING CONVENTIONAL COUPLED
TRANSMISSION LINE MODELS
Consider a coupled transmission line structure as shown in Figure
SSN OF CMOS DEVICES AND SYSTEMS
132
9.2. Often the transient response of coupled lines is calculated using a set of
coupled wave equations with appropriate boundary conditions, and Fourier
analysis.
Figure 9.2 A coupled transmission line interconnect model.
For example, coupled, lossless transmission line equations for the structure
shown in Figure 9.2 can be written in the sinusoidal steady state as
dV1
= -jw (Ll1ft
dz
+
dl1
dz
dV2
dz
-jw (Cl1 V1
+ C12 V2)
(9.2)
-jw (L22h
+
(9.3)
L 12 h) ,
L21 ft) ,
(9.1)
SIGNAL OVER A NOISY REFERENCE PLANE
133
dh
(9.4)
dz
Here h, h are current through and Vi, V2 are voltage on conductor one
and two respectively. Self and mutual/coupling inductance, capacitance are
denoted by
C;j. It can be shown that,
Lii, C ii ,
and
and
are capacitance and inductance matrix coefficients re-
Lij,
Similarly
where
C ij
Lij
spectively. For symmetrical interconnect structures as shown in Figure 9.2,
Lll=L22 and C ll =C22 . In addition, from reciprocity it is always true that
C ij
= Cj i
and
Lij
= Lj i.
Notice that in the above equations Vi and
V2
are position-dependent voltages measured with respect to a perfect reference
plane. Consequently, the use of this coupled transmission line model for signal propagation over a noisy reference plane becomes cumbersome, especially
when one is interested in analyzing the effects of Vss pin distribution on noise.
B. PROPOSED MODEL FOR SIGNAL CONDUCTORS OVER
NOISY REFERENCE PLANE
Consider the Vss plane as a very wide Vss conductor
Wsignal)
(Wpl ane
>>
with the current return point at the near end. In Figure 9.3, only
a single conductor over a noisy reference plane is shown for mathematical
simplicity. Here conductor number 1 is a signal conductor, and number 2 is a
reference plane treated as a ground conductor. It can be shown that, in the
sinusoidal steady state
(9.7)
dh
dz
-jw (C ll ) V12
.
(9.8)
134
SSN OF CMOS DEVICES AND SYSTEMS
Here L1P, Ll are partial self inductances, and L 12 P is a partial mutual inductance as shown in Figure 9.3.
Signal Conductor
Conductor I
\
r
hu--_____-:-:-___-:-:-______---'
+t
VI2 (Z) VI2 (Z+.6Z)
1_
_I
Conductor 2
/
Reference Plane
Figure 9.3 A signal conductor over a very wide Vss conductor.
Cl l is the self capacitance. For a single, lossless transmission line with the
Vss plane as reference, the equations for the voltage and current along the
line are,
dV
dz
-jw (Ls) I,
:~ = - jw (Cs ) V
and
.
(9.9)
(9.10)
Here Ls and C s are the p.u.I. inductance and capacitance ofthe line. Comparing equation (9.7) with (9.9), the dependence of Ls on the Vss plane inductive
SIGNAL OVER A NOISY REFERENCE PLANE
135
parasitics becomes clear. A distributed lumped element circuit model, including coupling parasitics to the Vss conductor is developed and shown in Figure
9.4, where L 1P, Ll, L/ are the partial self inductances of conductors, one,
two, and the ground conductor, respectively.
Figure 9.4 Lumped circuit model including plane parasitic.
L 12 P, L 21 P , L 1 / , and L 2 /
are partial mutual inductances. Similarly, C 1g , C2g
are the self capacitances of conductors one and two, and C12 is the mutual
capacitance between signal conductors. After several SPICE simulations, it
SSN OF CMOS DEVICES AND SYSTEMS
136
was found that 10 lumps/cm was more than adequate to provide good convergence for up to 200 ps rise/fall times. Because of this, we have used 10
lumps/cm distributed lumped model to simulate signal propagation over a
noisy reference plane.
9.3 CALCULATION OF LUMPED CIRCUIT ELEMENTS
A. METHODOLOGY
An interconnect structure as shown in Figure 9.1 was selected for this
analysis. Typical thin film and thick film interconnect geometries were used
in these simulations. Note that all dimensions for the thin film structures are
in microns, and for the thick film in mils. The following values were used for
thick film technology; Erl = 1.0, Er2 = 3.9, W=3, S=3, 6, 9, 15, t=l, and
h=10. The following values were used for thin film technology, Erl = 1.0,
fr2
= 3.9, W=5.0, S=5, 10, 20, 30, t=2, and h=10. Ground conductor width
of 100 mils and 200 /Lm, and thickness of 1 mil and 2 /Lm (same as conductor
thickness) was selected for thick and thin film technologies, respectively. The
two-dimensional capacitance calculator UAC [9.4] was used to calculate the
p.u.I. capacitance matrix for the interconnect geometry. Using the noisy
ground conductor as a reference (V=O) UAC calculates actually the electric
induction coefficients J{ij defined by means of the relations
(9.11)
where Qi is the total charge per-unit-Iength on conductor i, and Vj is the
voltage of the lh conductor with respect to the reference. On the other hand
the capacitances used in our distributed lumped circuit model are consistent
with the expressions
GIg VI
+
G 12 (V2 -
G 12 (VI
VI)
+
V2)
(9.12a)
G 2g V 2
(9.12b)
-
A direct comparison of (9.11) and (9.12) reveals that
J{2g - G 12 ,
and
G 12
=
-J{12.
GIg
=
J{lg - G 12 , G 2g
=
SIGNAL OVER A NOISY REFERENCE PLANE
137
A detailed two-dimensional inductance calculator UA2DL [9.5] was
used to extract the p.u.l. inductance matrix. The p.u.l. inductance matrix
corresponding to the interconnect structure of Figure 9.1 is,
[L](l, 2; g)
= (~~~
nH/cm.
(9.13)
Here [L](1, 2; g) denotes the p.u.l. interconnect matrix for the transmission
line consisting of two signal conductors 1, 2 and a finite ground conductor.
From Section 9.2-B, it is clear that Lll and L22 can be written as,
Lll
(9.14)
(9.15)
Partial self inductances are calculated using A. E. Ruehli's equations [9.6],
and results are given in the following section.
#1
GND
1
t
T
~I~~-w---~~I~~---S---~~I
Figure 9.5 Two conductor model for UA2DL inductance calculation.
138
SSN OF CMOS DEVICES AND SYSTEMS
Since this method requires a finite conductor length for inductance calculations, a 10 cm long line was used, and the results are converted to per-unitlength values. From the partial self inductances L/, Ll, L/, equations
(9.14) and (9.15) can be used to calculate the partial mutual inductance between signal and ground conductors (Llg and L~g), since Ll1 and L22 are
already known.
In order to calculate the partial mutual inductance between the two
signal conductors (Ll 2 ), the configuration of the two signal conductors with
one of them grounded is used as shown in Figure 9.5. Using UA2DL, the total
(or loop) inductance L l1 (1,2 g) is calculated. From Section 9.2-B,
(9.16)
Knowing L1P, L2 P, and L 11 (1,2 g), Ll2 is calculated using equation (9.16).
Notice, all these capacitance and inductance matrix coefficients are per-unitlength parameters. This technique can be extended to three or more coupled
transmission line interconnects over a noisy reference plane.
To verify the validity of our proposed model at very high, mid-range
and at low frequency, the following per-unit-length [pull delay values were
compared for thin film and thick film interconnect structures: 1) UAC calculated capacitance and inductance matrix, 2) UAC calculated capacitance
matrix, UA2DL ( at 1 GHz ) and Ruehli's algorithm for inductance matrix
element extraction (extraction method explained earlier), and 3) UAC calculated capacitance matrix, UA2DL (at low frequency) and Ruehli's algorithm
for inductance matrix element extraction. The maximum worst case [pUll delay of 4.2 % was obtained between model (1) and (3), while the worst case
errors on the [pull delays between model (2) and (3) are within 1.3 %. These
delay values have demonstrated that it is appropriate (to within engineering
accuracy) to use UA2DL (at 1 GHz) and Ruehli's algorithm (valid at low frequency) in conjunction to extract the inductive elements (both interconnect
and reference plane) used in our proposed model.
B. LUMPED ELEMENT VALUES
To explain the above methodology, a two conductor thin film case
139
SIGNAL OVER A NOISY REFERENCE PLANE
with conductor spacing 5 pm and other parameters given in Section 9.3-A
was selected. As explained in the previous section, UAC was used to calculate
the capacitance matrix. The following UAC [K] and [L] matrix are calculated,
[F] = (0.647
i
-0.180
-0.180)
0.647
pF/cm,
1.892)
[L]UAC(l , 2', g ) = (5.241
1.892 5.241
nH/cm.
(9.17)
(9.18)
Note that UAC assumes that all conductors are perfect and thus their internal inductance is zero. Now for the same structure, the inductance matrix
calculated using UA2DL is,
5.697 2.071)
[L](l, 2; g) = ( 2.071 5.696
nH/cm.
(9.19)
Since UA2DL simulations require a single frequency to calculate the inductance matrix, 1GHz operating frequency was selected. The discrepancy between (9.19) and (9.18) is due to the fact that UA2DL accounts for the finite
conductivity of the conductors and thus includes their internal inductance due
to the field penetration inside them. For 1 GHz and copper conductors, the
skin depth is 2.09 pm. Notice that this amount of skin depth only perturbs
the current distribution significantly on thick film interconnects (t=25.4 pm)
and not on thin film interconnects (t=2.0 pm).
Again, UA2DL was executed to calculate the inductance for the structure shown in Figure 9.5. The following inductance is calculated
Partial self inductance for these structures are calculated using [9.6]:
Lf
= L~ = 21.620 nH/cm , and
L~
= 12.5 nH/cm .
Using Lf, L~, Lij{l, 2, g) in equations (9.14) and (9.15), Lfg and L~g are found
to be
Lfg = 14.212 nH/cm ,
SSN OF CMOS DEVICES AND SYSTEMS
140
H29
=
14.212 nH /crn .
Similarly using Lf, L~, and L11 (1, 2g) in equation (9.16), Lf2 is found to be,
Li2 = 17.835 nH/crn .
Capacitance values are calculated from the UAC-computed electric induction
coefficient matrix given by equation (9.17). Lumped circuit element values
for thick and thin film interconnect structures, using technology parameters
contained in Section 9.3-A with a range of conductor spacings were calculated
using the above methodology, and results are given in Table 9.1 and 9.2,
respectively. All the capacitance and inductance values are in pF / cm and
nH/cm, respectively.
Table 9.1. Thick film interconnect lumped element values.
Lum)2ed Elements
S=3 (mils)
S=6 (mils)
S=9 (mils)
S=15 (mils)
C1g=C2g
C12=C21
0.359
0.394
0.419
0.449
0.209
0.121
0.079
0.038
Li=L~
16.070
16.070
16.070
16.070
LP9
9.577
9.577
9.577
9.577
Lig=L~g
9.776
9.755
9.669
9.519
Lf2
12.648
11.755
11.155
10.321
Table 9.2. Thin film interconnect lumped element values.
Lum)2ed Elements
S=5 (gm)
S=10 (gm)
S=20 (gm)
S=30 (gm)
C1g =C2g
0.472
0.519
0.564
C12 = C21
0.178
0.089
0.029
0.013
Li=L~
21.620
21.620
21.620
21.620
LP
12.501
12.501
12.501
12.501
9
0.579
Lig=L~g
14.212
14.247
14.312
14.315
Lf2
17.835
17.001
15.965
15.271
141
SIGNAL OVER A NOISY REFERENCE PLANE
9.4 TRANSIENT RESPONSE SIMULATIONS
A. CHIP-PACKAGE
V55
CONNECTION MODELS
In packaged CMOS systems all the output driver VDD/VSS buses are
connected to the global external (or noisy) VDD/VSS buses. These external
buses are connected to the package VDD /Vss planes using any of the following
connection technologies: 1) wire bonding, 2) tape-automated-bonding (TAB),
and 3) C4 (controlled collapse connection) flip-chip technology. A coupled
transmission line interconnect model including the driver/receiver circuits and
chip-package connections is shown in Figure 9.6.
LI
Vg
"I"
0
~
I
L2
I
\
Lm,C c
/
Vie
•
~
Figure 9.6 Chip-package Vss connection: "Complete Isolation" (CIS) model.
SSN OF CMOS DEVICES AND SYSTEMS
142
There are N number of simultaneously switching (including the active driver)
CMOS output drivers (Dl' D 2 ,
•••
DN) sharing the same Vss connections,
and a quiet driver (Dq) with its Vss connection isolated (has its own Vss).
Also, the transmission line Vss reference plane and the receiver circuit (Rl
and R 2 ) Vss connections are isolated. This Vss connection model is an ideal
case, and from here on this model is referenced as "Complete Isolation" (CIS).
More realistic Vss connection models ("Isolation" (IS) and "Plane Connected"
(PC)) are shown in Figures 9.7 and 9.S .
•
•
•
•
LI
1
Vne
"1"
L2
Vg
1
Figure 9.7 Chip-package Vss connection: "Isolation" (IS) model.
Because of the symmetry, only Vss chip-package connections are
shown in Figure 9.6, 9.7 and 9.S; however
VDD
chip-package connections
SIGNAL OVER A NOISY REFERENCE PLANE
143
are similar. It has been shown in the past using simulations and experiments
that CMOS outputs simultaneous switching noise exhibits a sub-linear behavior with the number of outputs switching simultaneously. This sub-linear
behavior was explained with negative feedback equations for CMOS outputs
switching noise [9.7]. The indirect interactions due to the negative feedback
effects reduce the drive strength of the active driver D 1 , and thereby switching
and coupled noise are perturbed.
•
•
•
•
LI
'----+--- ••• - - - • •• - -
L2
Figure 9.8 Chip-package Vss connection: "Plane Connected" (PC) model.
In this work, output driver negative feedback effects are not of interest, and
unless they happen to be essential to explain a transient waveform, they are
not included. In the CIS model, there are no direct interactions between
144
SSN OF CMOS DEVICES AND SYSTEMS
switching noise and coupled noise. Note that in the models shown in Figures
9.6, 9.7, and 9.8, Vss pins are intended to be lumped into a single R,L,C
lumped element model, and placed very close to the chip-package interface
(i.e. front of the Vss plane). Methods of lumping into a single "effective"
lumped inductance (Lejj), including the effects of package-pin placements
are given in [9.8]. The impact of package-pin placement on the Vss plane
and signal propagation over this Vss plane is discussed in Section 9.5.
In Figure 9.7, all the active drivers and the quiet driver share the
same Vss connection. The transmission line Vss plane and the receiver circuit Vss connections are isolated. In this (IS) model, SSN can feed through
the N-channel transistor of the quiet driver Dq to the quiet transmission line
interconnect. This injection of switching noise through Dq can disturb the
near-end and the far-end crosstalk (noise) values. In the (PC) model case
of Figure 9.8, all the active drivers, the quiet driver, and the transmission
line Vss plane share the same Vss connections, and the receiver circuit Vss
connections are isolated. The dotted line on the Vss plane in Figure 9.8
corresponds to the model where the Vss plane is modeled as a distributed
Vss conductor.
As explained in Section 9.2, the simulation of the "plane
connected" model is rather cumbersome if conventional transmission line simulators are used, whereas "complete isolation" and "isolation" models can be
simulated in a straightforward manner using conventional transmission line
simulator, such as UANTL [9.9].
B. RESULTS
In the following examples, output driver device sizes of Wp=306 J-Lm
and WN=200 J-Lm, and line interconnect length of 10 cm was selected. In this
work, package pin parasitics are modeled into a single RLC lumped parameter.
Package-pin lumped parasitics (LVDD=Lvss=3 nH, RVDD=Rvss=1 mn,
and Cv DD = Cv ss= 1 pF) were used in conjunction with typical level-2
SPICE MOSFET circuit models (Lei 1 (channellength)= 1.0 J-Lm) for transient
simulation. For the SPICE simulations, 1.0 ns output driver risetime was
selected. The transmission line interconnects are terminated with a typical
SIGNAL OVER A NOISY REFERENCE PLANE
145
CMOS receiver (Wp=25 pm, WN=15 pm) as shown in Figures 9,6, 9,7, and
9,8,
In Figures 9,9 and 9,10, ground noise (Vg) is plotted as a function of
signal conductor pitch, and the number of simultaneously switching outputs
(N) for thin and thick film interconnect technologies, respectively,
3,0
-
--
N =16 (IS 8 PC)
(j)
o
2:
20
(l)
if)
N=4 (IS)
'0
z
:;::::::::::==N =4
CJl
c
(PC)
.r:
!:!
3
1.0
(J)
>0,
N=I (IS)
00
1---I'---"-----'----'----.1..------'-----.J...--~
10
15
20
Spacing (fLm)
25
30
N= 1 (PC)
-1.0
Figure 9,9 SSN vs conductor spacing (thin film technology),
Vg is the simultaneous switching ground noise measured at the source end
of the output driver N-channel transistor(s), Near-end and far-end crosstalk
probe points are denoted by
V ne
and
Vje
in Figures 9,6, 9,7 and 9,8, SSN
waveforms on Vss plane are shown in Section 9,5, Ground path "effective"
SSN OF CMOS DEVICES AND SYSTEMS
146
lumped package parasitics (Rvss, Lvss, and Cvss) are not shown in these
figures for clarity. To explain the impact of noisy ground plane on the signal
propagation characteristics, only "isolated" (IS), and "plane connected" (PC)
models are plotted in these figures.
3.0
N=16 (ISBPC)
~
g 2.0
~
Q)
IJ)
'0
N=4 (IS)
Z
--~------
0>
.~
~(PC)
.c.
..g
3
1.0
(j)
>0.
9
12
Spacing (mils)
N=I (PC)
~
15
_ _- -
-1.0
Figure 9.10 SSN vs conductor spacing (thick film technology).
Input transients to the output drivers (D 1 , D 2 , ... D N ) are low-to-high, and
the output transients are high-to-low. With the above simulation conditions,
primary simultaneous switching ground noise pulse is positive, and the nearend crosstalk is negative. The negative polarity of the near-end crosstalk
can be explained using closed-form equations derived by Feller et. al. [9.10]'
SIGNAL OVER A NOISY REFERENCE PLANE
147
and a primary positive switching noise is because of the initial rising edge of
the current spike when the simultaneously switching N-Channel transistors
are turned ON. when the number of simultaneously switching outputs (N) is
equal to 16, both the (IS) and the (PC) models generate larger ground noise
compared to the near-end crosstalk, thus Vg is not affected by Vne . However,
for N =4, ground noise (Vg) is perturbed by the near-end crosstalk for closely
coupled (S::;10 /-Lm, or S::;9 mils) interconnect structures. This trend is more
prominent in the "PC" model compared to the "IS" model. As expected,
deviations on the ground noise as a function of signal conductor pitch are
significant for the N=l case. Note that for the "IS" model, the only coupling
between Vg and Vne is through the D.C. "ON" N-channel transistor, while
for the "PC" model an additional coupling exists through the non-ideal Vss
plane. Impact of this additional coupling is clear by comparing the (IS) and
(PC) models for the N=l case curves shown in Figures 9.9 and 9.10.
4.0
~ 3.0
~
~
~ 2.0
Vl
Vl
o....
U
'0
c:
W
1.0
-----
~--
....
I
o
~ 0.0 I---~--:::;o"""':::"':---~--"""""---='=---~--+
-1.0
-2.0
Figure 9.11 Near-end crosstalk vs conductor spacing (thin film technology).
SSN OF CMOS DEVICES AND SYSTEMS
148
In Figures 9.11 and 9.12, the near-end crosstalk (Vne ) is plotted as a
function of conductor pitch for thin and thick film interconnect technologies.
3.0
N= 16 (PC)
7
~
~16(IS)
~
~2..0
-'"
:Een
en
e
N=4 (PC)
u
'0
c
~
oQ)
1.0
~4(IS)
:
Z
N=UIS)
0.0
f-------'------,:~---'---'-----'----'-_ _
3
15
18
-1.0
Figure 9.12 Near-end crosstalk vs conductor spacing (thick film technology).
As the number of simultaneous switching outputs increases, Vg increases, and
this dominates in the overall near-end crosstalk (Vne). However, for a large
number of simultaneously switching outputs (N216), Vne is not exactly equal
to Vg for closely coupled lines. Note that, for N=l case, the (IS) model overestimates Vne , and for N24, the (IS) model under-estimates Vne compared
to the (PL) model. This is because, for the N=1 case, Vne is dominated
by coupled noise; however for large Vg (N24), the impact of switching noise
coupling to an adjacent signal conductor through the D.C. "ON" transistor
and the Vss plane is dominant. These trends are similar for thin and thick film
SIGNAL OVER A NOISY REFERENCE PLANE
149
transmission line interconnects over a noisy reference plane. Often in practice,
for the worst case noise budget calculations, SSN and coupled noise (CN) are
simply added. These results have demonstrated that simple addition of SSN
and CN at a given arbitrary time represent an over-estimated system budget.
To calculate the overall noise budget for MCMs, it is not only important to
understand in detail each isolated noise (SSN, CN) sources, but also how these
noise sources interact globally in a system.
In Figures 9.13 and 9.14, the far-end crosstalk (Vje) is plotted as a
function of conductor pitch for thin and thick film interconnect technologies.
3.0
'2
~
N=16(PC)
----~----__________~N~=~16~(~IS~)__
..>::
.E
rJ)
~
....
2.0
~-_ _N=_4....;..(P_C....;..)_
U
"0
C
~------~N~=~I(~PC~)--
W
I
"---
~
----------_
1.0
00
N=4(IS)
'----'------'----.J--~---'---__'_:_----i~
o
5
10
15
20
Spacing (.um)
25
30
Figure 9.13 Far-end crosstalk vs conductor spacing (thin film technology).
As expected, when a large number of outputs switch simultaneously the
crosstalk is dominated by SSN even for closely coupled (S:S5 /Lm for thin
150
SSN OF CMOS DEVICES AND SYSTEMS
film or S::;6 mils for thick film) interconnects. Note that, for all of the interconnect structures analyzed in this work, SSN and the far-end coupled noise
are positive, and both contribute to the overall far-end noise value. This effect
is demonstrated in Figures 9.13 and 9.14 for N=l case.
2.0.
~
N=16(PC)
~
N=16(IS)
~::::=====
"
~
~
N=4(IS)
05
0.0 OL----!3--...I.6--9.l-..-....J12'---...I.IS--I.LS----.
Spacing (mils)
Figure 9.14 Far-end crosstalk vs conductor spacing (thick film technology).
In all these cases, the (IS) model does not include SSN coupling through the
Vss plane. The results from this study demonstrate that switching noise,
near-end noise and far-end noise characteristics are different for conventional
isolated (IS) and noisy reference plane (PC) models. This is because in the
(PC) model, in addition to SSN fed through the quiet line and the conventional
coupled noise at far-end, SSN also propagates through the Vss plane and
contributes to the overall far-end noise characteristics. In reality, there are
SIGNAL OVER A NOISY REFERENCE PLANE
151
localized Vss pins (or Vss via connections) beneath these signal conductors
which are connected to the Vss plane. These Vss pins suppress the noise on
the Vss plane. Consequently, the actual noise levels depend on package-pin
placement.
9.5
IMPACT OF Vss PACKAGE-PIN PLACEMENT ON
NOISE MODELING
In Figure 9.15, coupled transmission line interconnects over a noisy
reference plane with package-pin connections are shown, where A, B, and C
are the Vss package-pin connections.
"1"0-----1
L2
Figure 9.15 Effects of package-pins placement ("Plane Connected").
SSN OF CMOS DEVICES AND SYSTEMS
152
Note that these are localized Vss pins connected to the Vss plane beneath (or
in the vicinity of) the signal conductors. As explained, these Vss packagepins are modeled using R,L,C lumped elements (values given in Section 9.4).
Driver-receiver device sizes, lumped circuit package parasitics, and the simulation conditions are given in Section 9.4. The "ON" or "OFF" state of A, B,
and C switches in Figure 9.15 denotes the "existence" or the "non-existence"
of that Vss pin at that particular location on the Vss plane. For example,
(110) state represents Vss pin placement of A and B only (i.e. there is no
Vss pin on the Vss plane at the location C). The case of sixteen outputs simultaneously switching (N=16) and the thin film interconnect structure was
selected for this analysis. To show the effects of Vss package-pin placement
on the overall noise modeling, noise levels are calculated at the near-end,
center, and far-end on the Vss plane for various pin placements.
(110 Package - Pin Placement)
3.00
"~ at the far end of the plane
~
~
(J)
c:
2.50
x.----'':---at the near end of the plane
o
a::
U)
~
c:
2.00
Thin Film Interconnect Structure
N=16, S=5fLm
o
(J)
en
~ 1.50
CI
c:
:.c
E 1.00
~
at the middle
of the plane
~
I
S
~
0.50
"
-<j,,---
_----t-",
" ...
0,00 r==-=-...,::..:..:. ." '. . J~.'- ._ _--'-_ _---'--:--_ _
'.L-_---:::---_-_'L'_''':';..,·~o!Q-....---+
0.50
1.00
1.50
2.00 ".
Time (ns)
-0.50
2.50.,' -
3.00\
.....
Figure 9.16 SSN on the Vss plane (110 package-pin placement).
In Figure 9.16, SSN on the Vss plane was plotted for the (110) Vss
153
SIGNAL OVER A NOISY REFERENCE PLANE
package-pin placement. As expected, SSN generated at the near-end of the
Vss plane is suppressed by the center (B) Vss pin as it propagates. Since
Vss plane at the far-end is open (no Vss pin and only coupling to signal
conductors exists), SSN at the far-end increases. This is demonstrated in
Figure 9.16 with the reduction in SSN at the center, and bouncing back to a
higher value at the far-end. In Figure 9.17, SSN on the Vss plane was plotted
for the (101) Vss package-pin placement.
(101 Package-Pin Placement)
'?
!
250
Q)
C
.E 2.00
Q..
U)
.y
C
0
1.50
Q)
U)
'0
I
z
c>
.!:
..:
.l:!
1.00
.~
(f)
~
I
0.50
Q)
C
I
E
3
~
0.00
I
I
/
/
/
I
/--- ..... ,
Thin Film Interconnect Structure
N=16, S= 5fLm
\
\~._ _--'-o.---- at the middle of the plane
at the for end \
of the plane \
1/
I
t··..
\ ...... _. .
-~
/ '
\
'\
\
,
.... \
,.
I'-'-'-'"""""''---'---''----'---'.--......,...---l'---'"''.,''F-~~~
0.50
1.00
1.50 ".
2.00
Time (ns) ........... :
2.50
3.00 ..
\
-0.50
Figure 9.17 SSN on the Vss plane (101 package-pin placement).
Note that the amplitude of SSN at the center is lower than the near end. This
is because, for the (101) configuration, at any given angular-frequency w, the
maximum peak noise at the center and far-end can be estimated using simple
voltage driven arguments
Lp;n + Lplane/2)
Vcenter ~ ( L. + L
Vnear-end ,
p,n
plane
(9.20)
154
SSN OF CMOS DEVICES AND SYSTEMS
Vjar-end ~
)
( L. LpinL
pm
plane
+
Vnear-end
.
(9.21)
Here Lpl ane is the total plane inductance, and L pin is the package-pin inductance. In equations (9.20) and (9.21), coupling to signal lines and the
influence of other (other than pins A, B, and C) pins placement are neglected
for analytical simplicity. SSN on the
shown in Figure 9.18.
plane for the (111) pin placement is
Vss
(III Package-Pin Placement)
?
2.50
~
-
QJ
at the near end of the plane
c:
c 2.00
0::
<I)
>(1)
§
Thin Film Interconnect Structure
N=16, S=5fLm
1.50
QJ
<I)
'0
z
1
at the middle of the plane
C'I
~~
j
1.00
~
0.50
::J
E
(j) 0.00
at the for end
...... / ........OffhjPIOne
,.
_--::--------"':""-!.
,.... .
.
.
.....
_...,..'-."""-- .... ~.,....
I=-==-~....:.:..~.:.:.~.:.l.-=-.' - ' - '_ - L_ _---l--;.. ~-'---L.,.:.....----L-'-:....~:¥c,.-£-_
0.50
1.00
1.50'·.
2.00
Time (ns)'· .. ....
2.50
..... 3.00\
...
-0.50
Figure 9.18 SSN on the
Vss
plane (111 package-pin placement).
Propagated SSN is reduced all the way from the near-end to the far-end, and
reduced significantly at the far-end.
The noise characteristics on the
Vss
plane have an impact on the
far-end crosstalk values. This is because of the additional coupling between
the quiet line and the noisy
Vss
plane. Proper package-pin placement can
SIGNAL OVER A NOISY REFERENCE PLANE
155
improve the overall noise performance. To demonstrate this effect, thin film
interconnect structure (spacing S=5 /Jm), and N=16 case was selected. In
Figure 9.19, the far-end crosstalk was plotted for (IS) and (PL) models. As
expected, the (IS) model predicts the worst-case far-end noise.
Thin Film Interconnect Structure
N=16,S=5fLm
2.00
". '"
-
en
~
1.50
'\+-------'-:-Plane Connected
Model (110)
.>0:
.E
III
Isolation Model
1.00
e
III
u
: Plane Connected
i Model (101)
"0
c
w
L 0.50
~
J
,~.\ Plane Connected
/ / \\\ M~odel (III)
/ : \~,
/:'
0.00
-
'.:--..... -::::-.~\
,
,,:
~
',\
. ,,'/
f - - _............""'--_ _ _...I...-_ _.;:.-'---_ _ _...I...-_.....:,.....-..."'~-~
1.00
2.00
3.00
.... 4 Oo:.·-... ~ 500
· ()':TIme
ns ,~, ,,/" ".
......-:.
~
-0.50
Figure 9.19 Far-end crosstalk for the "Isolation" and "Plane Connected"
model.
This is because in the (IS) model, noise on the Vss plane was not suppressed
since no Vss pins exist beneath the signal conductors. In the (110) pin placement model, since there is no Vss pin at location C, far-end noise is larger
compared to the (101) and (111) pin placement models. It is clear from this
study that Vss package-pins beneath (or in the vicinity of) the signal conductors suppress the fed-through SSN from the quiet transistor and the Vss
156
SSN OF CMOS DEVICES AND SYSTEMS
plane, and this reduces the coupled noise.
9.6 SUMMARY
A method of modeling and simulation of coupled transmission line interconnects over a noisy reference plane was presented. Various chip-package
Vss connection models have been reviewed, and their impact on overall noise
modeling and simulations are explained. A lumped circuit element "Plane
Connected" model was proposed, and implemented for the simulation of signal propagation over a noisy reference plane. The impact of Vss package-pins
placement on the noisy reference plane on the overall noise level was examined. It was found that package-pin placement on the Vss plane has significant
influence on the overall noise performance.
CHAPTER 10
CONCLUSIONS
An investigation into the behavior of delays and SSN of CMOS devices
with constant-voltage scaling was presented in Chapter 2. It appears that
interconnects playa major role in the delay calculations for small geometry
devices. As a result, accurate modeling of interconnect parasitics is essential
for future VLSI chips. Thus detailed modeling of device and also package
interconnect parasitics are required to predict the performance of the packaged
small geometry CMOS devices/systems.
In Chapter 3, calculation of simultaneous switching noise (SSN) for
CMOS based systems was presented. It was found that SSN exhibits a sublinear behavior with the number of outputs switching simultaneously. As
a result, when calculating the switching noise, negative feedback influence
must be incorporated in the equations. This effect must also be carried out
in the power and ground bond-pad and package-pin connections calculations.
The trends in output driver switching noise with constant-voltage [CV] device
scaling were explained. A method of calculating the "effective" VDD /Vss chippackage interface inductance "Lej j" was presented in Chapter 4. It was found
that package-pin placement has a strong influence in the plane inductance
values (especially for a small number of package Vss pins). Perforations on
the Vss plane perturb the current distribution on the reference plane, and
this perturbations increase the plane inductance. Results have shown that
158
SSN OF CMOS DEVICES AND SYSTEMS
having symmetrical placement in the sink points greatly reduce the package
plane inductance. The impact of
Lpl ane
on the SSN was explained, and the
errors associated with the neglection of plane mutual inductive elements in
the inductance network were discussed.
In Chapter 5, a method for constructing equivalent circuit representations for signal propagation over non-continuous reference planes was described. This method can employ a number of very different tools, including
partial-element and full-wave tools, and arrive at the same equivalent circuit.
Through comparisons with measured data, confidence in the ability of this approach to provide acceptable accuracy has been shown. Appropriate ranges
of applicability have been established to aid in selecting the best combination
of modeling tools. For example, it was shown that when the perforation
area becomes small (relative to the reference plane total area), detailed 3-D
inductance modeling is essential for accuracy. Design guidelines were also presented to help estimate when perforation discontinuities can be safely ignored.
In high-speed applications where they are important, the method described
here can be used to predict time-domain waveforms accurately prior to hardware prototyping.
In Chapter 6, an investigation of the maximum tolerable ground noise
was presented using noise immunity curves. Rules-of-thumb were derived to
minimize the switching noise by skewing the outputs. Use of an additional
damping resistor in the output driver circuit to reduce the switching noise
was demonstrated. Trade-offs in using an additional damping resistor to reduce SSN were analyzed. Investigation on the CMOS output driver switching current components and their impact on SSN were analyzed in Chapter
7. Current controlled output driver circuit design techniques, and its limitations are explained. Controlled slew rate output driver design techniques, and
methods of realizing skewing times between final driver segments are given.
The advantage in using controlled slew rate output drivers over conventional
output drivers to reduce the "effective" simultaneous switching noise were
demonstrated.
A trial architecture to calculate SSN for CMOS based systems was
presented in Chapter 8. Applications and limitations in using SSNS (Simul-
CONCL USIONS
159
taneous Switching Noise Simulator) were explained. A method of calculating
"Lv ss" for MCMs, and thereby a method to calculate SSN using the SSNS
architecture for CMOS based MCMs are given. Using SSNS architecture,
device-interconnect scaling rules, and first-order MCMs "Lv ss" model, SSN
for future CMOS based MCMs are predicted. In Chapter 9, a method of
modeling and simulation of coupled transmission line interconnects over a
noisy reference plane was presented. Various chip-package Vss connection
models have been reviewed, and their impact on overall noise modeling and
simulations were demonstrated. A lumped circuit element "Plane Connected"
model was proposed, and implemented for the simulation of signal propagation over a noisy reference plane. The impact of Vss package-pins placement
on the noisy reference plane on the overall noise level was examined. It was
found that package-pin placement on the Vss plane has significant influence
on the overall noise performance. In Chapter 11, future work on reducing and
modeling SSN were discussed.
CHAPTER 11
DISCUSSION AND FUTURE WORK
11.1
BiCMOS OUTPUTS SIMULTANEOUS SWITCHING
NOISE
Even though Bipolar Junction Transistor (BJT) output driver current
drive capabilities are better than its counterpart CMOS output drivers, they
dissipate more power. For high level integration Multi-Chip Modules (MCMs),
power-delay product is an important performance metric in system performance evaluation. With advancement in CMOS process technology in the last
decade, high level of integration can be achieved by using CMOS technology
compared to BJT technology. However, one of the trade-off is between speed
and integration. With the advancements in scaled (Leff < O.75I'lm) CMOS
technology, preliminary trade-off studies have shown that possible technology
map for high performance computers will move from BJT to BiCMOS and
eventually to CMOS technology [11.1).
In Figure 11.1, a typical BiCMOS output driver circuit is shown
[11.2)[11.3). Note that, BiCMOS output drivers have best characteristics from
both technologies. From BJT devices (Q1 and Q2), a low output impedance
and large current drive capability, and from CMOS devices (M1, M2, M3, and
M4), a high input impedance and transient drive with no D.C. power consumption. Owing to the base-emitter voltage of BJT devices, the output swing in
162
SSN OF CMOS DEVICES AND SYSTEMS
=
=
BiCMOS output drivers is limited to Vol VBE and Voh
VDD - VBE. Note
that, for the typical BiCMOS output driver circuit shown in Figure 11.1,
transistors M1 and M3 provide base current for the BJT transistors Q1 and
Q2.
Voo
I n - -..
~-----~-----~---~
Out
Figure 11.1 A typical BiCMOS output driver circuit.
Transistors M2 and
BJT transistors Q1
MOS output driver
parasitics [11.4].
M4 provide a current discharge path for turning-off the
and Q2 respectively. Switching characteristics of BiCdepends on several second-order device and associated
Because of this second-order effects, negative feedback
switching mechanics are complex, and need more fundamental studies to generalize Simultaneous Switching Noise (SSN) for BiCMOS outputs. Note that,
DISCUSSION AND FUTURE WORK
163
in BiCMOS output drivers, not only the final stage BJT outputs, but also the
MOS pre-drivers, and the internal circuits contribute to the overall SSN.
11.2 USE OF SUBSTRATE-TAPS TO REDUCE SSN
As explained in Chapter 4, the effective inductance "Lv ss" include
bonding, package plane, and pin inductance. For a typical 168-256 pins PinGrid-Array (PGA) package, bonding, plane, and pin inductance are about
50 %, 10 %, and 40 % of the total "Lvss" respectively [11.5J. One method
to reduce "Lv ss" is to reduce the chip- Vss plane connection inductance. In
addition to other advantages, controlled collapse connection (C4) technology
provides a low chip-plane inductance. Another method to reduce the chipplane inductance is to provide an alternate current conduction path from the
on-chip Vss buses to the package Vss plane through the substrate (known as
"substrate-taps").
= Conductivity
T= Thickness
0'
Figure 11.2 Substrate-Taps current spreading.
164
SSN OF CMOS DEVICES AND SYSTEMS
Consider a twin-tub, p-type epitaxial CMOS process on a P+ substrate. For
this CMOS process, there exist a conduction path (if tapped) from the onchip Vss bus to the bottom ground plane through the substrate as shown in
Figure 11.2. With limited measurements on a single product, it was found
that SSN can be reduced with the use of substrate-taps. Measurements have
demonstrated that with proper implementation of substrate-taps, even with
the removal of all Vss bond connections, the packaged CMOS device was fully
functional with reduced switching noise on the on-chip Vss bus [11.5]. This
confirm the existence and the usefulness of the substrate conduction path from
the on-chip Vss bus to the package Vss plane through the substrate.
The major limitation in evaluating the performance of this technique
is the calculation of the parasitics associated with all the conduction path
through the substrate. First attempts in modeling these parasitics have
demonstrated that it is essential to account for the current spreading in the
substrate, and requires rigorous modeling tools [11.6].
~Substrar-Taps~
Ls
:L
Ls
Ls
Lb
Lb
Rs
Rs
Rs
Rb
Rb
Rp
Lpin
Rpin
Lp
Rp
Lb. Rb•Cb Bonding
Ls. Rs' Substrate-Taps
Lpin • Rpin ' Package-Pin
Lp
_
L pin
Rpin
Figure 11.3 Chip-Package interface parasitics with substrate-taps.
r
VssPlane
DISCUSSION AND FUTURE WORK
165
A typical chip-package interface parasitics including substrate-taps are shown
in Figure 11.3. In Figure 11.3, both the conventional bonding and the substrate tap connections are shown. Note that, even if the substrate-tap connection parasitics are comparable to the bonding parasitics (Ls :=::: Lb and
Rs
:=:::
Rb), a large number of substrate-taps can be placed on most part of
the Vss buses. In addition to reducing SSN, substrate-taps also improves
latch-up suppression [11.7]. Note that, for electromigration limited Vss bus
widths (minimum size is determined by the electromigration requirements),
use of substrate-taps may demand to increase the Vss bus widths to fulfill
electromigration requirements [11.5]. This is because of the additional taps
that are placed in the on-chip Vss buses.
11.3 SSNS ARCHITECTURE IMPROVEMENT
The SSNS architecture explained in Chapter 8 calculates SSN for a
given number of Vss connections, and vice versa. Even though, some methods
ofreducing SSN and effects of package-pin placements are included, results do
not include simultaneous switching noise waveform. In future SSNS development, one can include switching noise waveform modeling. This development
can help system designers to evaluate switching noise waveform on the Vss
buses, and the package plane as a function of time. As explained in Chapter 8,
in reality there are additional mutual coupling exist from signal lines to the reference planes, and these mutual inductance elements need to be incorporated
in the Lvss inductance network. However, with more and more detailed calculations, SSNS will lose its charm as a fast SSN calculator, and may become
computationally comparable to the detailed SPICE simulations.
Knowing
the negative feedback effects in BiCMOS output driver's, SSN calculation for
BiCMOS outputs can also be incorporated. After the development of a detailed substrate-conduction path parasitic extractor, substrate-taps method
can be included in future SSNS. This can be realized by developing a separate inductance network calculator module for substrate-taps, and using it in
conjunction with the present inductance network calculator.
APPENDIX A
TEM PARAMETER CALCULATORS [A.I]
In order to analyze the electrical performance of integrated circuit
packages in the TEM approximation, one has to characterize the interconnect
by the per unit length [PULl capacitance [C], inductance [L], conductance [G]
and resistance [R] matrices. In the event that only lossless transmission lines
are to be investigated, the problem is reduced to determining capacitance [C]
and inductance [L] matrices only. To find the [PULl per unit length electrical
parameters, time dependent Maxwell's equation in three dimension must be
solved for arbitrarily complex packaging geometries. In the TEM approximation, Maxwell's equation reduce to solving Poisson's/Laplace's equation in
the zero frequency limit (i.e. all charges and currents are on the surface of
infinite conductivity
(J'
conductors) with the appropriate boundary conditions.
However, in the two dimensional approximation only those structures which
posses symmetry such that they may be represented as being infinitely long
in one of the three dimension are considered.
Although simple configurations may be solved analytically in two dimension by techniques such as conformal mapping, serious technical problems
develop due to the presense of dielectric interfaces. Numerical techniques need
to be developed. Several numerical techniques exist which are widely utilized
to solve this type of elliptic partial differential equations, such as the finite
difference method [FDM], the finite element method [FEM], the variational
method [VM], the spectral domain method [SDM] , the method of moments
[MOM]' and the semi-analytic Green's function method [GFM]. In this work,
168
SSN OF CMOS DEVICES AND SYSTEMS
we have used both the semi-analytic Green's function method (UAC), and the
method of moments (UAMOM) method to extract two dimensional TEM [C]
and [L] matrices.
A.I SEMI-ANALYTIC GREEN'S FUNCTION METHOD [GFMl
This particular method of determining the short circuit capacitances
for a system of conductors is based on Week's method [A.2]. Presently, due to
the availability of applicable Green's functions, this method has been developed for three special cases. These are: case (1) N-conductors between two
infinite ground planes with one dielectric present, case (2) N-conductors, one
finite ground plane and one dielectric interface, and case (3) N-conductors,
one finite ground conductor, and one dielectric interface. The semi-analytic
Green's function approach to systems comprised of more than two dielectric
layers, involves extremely complicated Green's functions.
For N dielectric
layers the Green's function contains N 2 expressions and N-I infinite terms.
Therefore, an algorithm based on this technique will become computationally expensive. The charge density on the
ith
conductor is denoted by W;(r')
where 1'" is the vector specifying the coordinate on the conductor surface, The
charge on any conductor is the integral around boundary of the conductor.
(A.I)
The total charge must fulfill the electroneutrality condition,
m
m
L
f
;=1 Jboundary
W;(r') dr'
=
0
(A.2)
where m is the total number of conductors present. The potential cP(r) due to
the charges on all conductors can be written in the form of an integral,
cP(r)
=
cPo
+
f
f
;=1 Jboundary
G;(r,r') W;(r') dr' ,
(A.3)
169
APPENDIX A
where Gi(r,r') is the Green's function for the appropriate case, r represents
some position vector in the two-dimensional sub-space, r' is the position vector
along the charge density surface and rf;o is the reference potential. Note, rf;(r)
should satisfy the appropriate boundary conditions for the problem. The three
pertinent Green's functions may be found in reference [A.2].
Once the charge density on the surface of the conductors has been
determined by suitably discretizing the equation (A.3) and solving the resulting set of linear equation (A.3), the short circuit capacitance matrix [C] may
be evaluated by determining the charge per unit length Qi on conductor i,
m
Qi =
L
Cij Vj
(A.4)
i=l
due to the potential of 1 volt on conductor j. Thus to determine C 12 , we
calculate the charge per unit length on conductor i=1 due to a potential on
conductor j=2 of Vj=1 volt with all other lines set to zero volts.
Using the properties of duality, we can determine the inductance matrix [L] by calculating the capacitances in the presence of no dielectrics [Co]
(with the assumption that we are not considering magnetic materials, l.e.,
J.lr=1). The inductance matrix is related to the matrix [Co] as
[L]
=
:2
[Co]-l
(A.5)
where V is the propagation velocity in vacuum and [CO]-l denotes matrix
mverslOn.
A.2 METHOD OF MOMENTS [MOM I
An alternative approach is to use the free space Green's function in
conjunction with total charge on the conductor-dielectric interfaces. This formulation has the distinct advantage that an arbitrary number of conductors
together with arbitrary number of dielectric interfaces can be handled, limited only by the storage of the computer resulting from discretization of the
conductor and dielectric interfaces.
170
SSN OF CMOS DEVICES AND SYSTEMS
For any position r in the plane, the potential is due to the total charge
on all conductors and dielectric interfaces and the image charges is due to a
finite ground plane. The potential may be written as:
(A.6)
where the sum extends over all Nl conductors and N2 dielectric interfaces
where N = Nl
+ N 2, (J'T
is the surface charge at
r', r' is the position along
the conductor surfaces and dielectric interfaces and r' is the position along
the image of (J'T. If no ground plane is present, the numerator in the log term
becomes 1. The electric field can now be determined as the negative gradient
of the electric potential E( r) = -V <p( r).
Two sets of boundary conditions are needed to generate the necessary number of equations. The potential along each conductor i must be
equal to
Vi
for each discretized boundary element, and the displacement vec-
tor D( r) = c E( r) must be continuos across each dielectric interface. Since
the boundary elements lie on either the dielectric or conductor boundaries,
these conditions supply the necessary number of linear integral equations to
determine all
(J'Ti.
The method of moments solution is generated by looking
for solutions of the form,
(A.7)
where
Pn(r)
are unit impulse functions.
Now the coefficients
(J'Tn
can be
determined. The dielectric interfaces will be truncated at finite width (for numerical reasons) and all conductor and interface boundaries will be discretized
into straight line segments. Once the geometry has been discretized, N linear
equations in
N((J'Tn)
unknowns result, where the coefficients in the equations
are integrals of Green's function over the discretized boundary elements. The
coefficients can now easily be determined.
Once the
(J'T j
has been determined, where the superscript j now refers
to that charge distribution resulting from exciting the
/h
conductor to 1 volt
171
APPENDIX A
and keeping other conductors grounded, the short circuit capacitance may be
determined using the following equation:
Gij ==
1
conductor i
c(1').
-co
(J"T J
d li
(A.8)
c( r) is the relative dielectric just outside of the conductor i's surface and dli is
the differential boundary element along the
ith
conductor. In similar fashion,
the inductance matrix may be found by determining the [Gal matrix.
APPENDIX B
TRANSIENT RESPONSE USING MATRIX METHOD [A.I]
To simulate the transient response of the transmission line, the natural procedure seem to be a SPICE implementation of a lumped element line,
but this may not be the most time efficient procedure to follow. The only
advantage to using SPICE is the ability to implement non-linear drivers and
receivers. Often engineers want to simulate the transient response of coupled
transmission line interconnects using their desktop personnel computer. Matrix method is very useful for this purpose, and given below. Note that this
method is not intended for detailed coupled transmission line interconnects
transient response simulations. For high-density, high-performance systems,
one needs to use a detailed transient response simulator for signal integrity
analysis.
Consider N coupled loss less transmission lines with N linear time
dependent near end voltage sources and termination resistors, and N linear
time dependent far end voltage sources and termination resistors as shown in
Figure B.l. Matrix method relies on a transformation to effectively decouple
the lines and determine an equivalent resistance matrix for the transmission
lines. Since we can write the capacitance matrix [C] as,
[Co] = [N] diag[a n ] [Nf
(B.1)
where [N] is the matrix ofthe eigenvectors ofthe eigenvalues an and diag[a n ] is
the diagonal matrix of the eigenvalues of [Co], where T signifies the transpose,
174
SSN OF CMOS DEVICES AND SYSTEMS
then
[CO]-05
=
[N] diag_1_ [Nf .
(B.2)
va;;
This is due to the fact that [C] is a symmetric matrix. Then we can write the
matrix product
.
1
[W]dzag- [Wf
(B.3)
Vk C
Rbt
LINE 1
LINE 2
LINE 3
Rb n
eb n
LINE n
FAR END
Figure B.1 General N-Coupled Transmission Lines.
Again, due to the symmetry, it can always be diagonalized and VkC
(c = speed of light) is the wave propagation velocity, and [Wl is once again the
matrix of eigenvectors of the Vk eigenvalues. Now define the transformation
matrix [Xl,
[Xl = [C otO. 5 [W] diag( Vk VG;)
(B.4)
where Ck are the eigenvalues found by diagonalizing [C]. The equivalent resistance matrix for the decoupled N-ports becomes
1
r'ii =
N
and
I:j=l [R-l]ij
APPENDIX B
175
r'ij
-1
--[R-l]ij
(B.5)
Here,
(B.6)
Once the resistance N-port for the transmission line has been determined, we
need only to solve Kirchoff's laws for the resistive N-port at the termination
resistors. However, only lossless lines and linear terminations are allowed.
APPENDIX C
LOSSY TRANSMISSION LINE INTERCONNECTS
Motivated by desire for high density, technologists are constantly reducing conductor crossections to increase the interconnect density. Reduced
conductor crossection together with faster rise/fall times will force these interconnects to be treated as lossy instead of lossless. In addition dielectric
losses become more important at high frequencies. For system designers, it
is important to know the regions where the interconnects may be considered
lossless, and the regions they are lossy. False switching may occur due to SSN
feeding through the D.C. "ON" drivers. If the interconnects are lengthy and
lossy, some of the unwanted feed-through noise may be damped out when it
arrives at the input of the receiver due to attenuation caused by losses. Of
course, signals also experience attenuation which can reduce noise margins on
the active lines.
In Chapter 9, signal conductors over a noisy reference plane were analyzed in detail. The signal conductors and reference plane models used in this
analysis were lossless. Losses and distortion in high-speed interconnect systems can degrade the driven signal as mentioned above, and thereby they can
degrade or even limit the system frequency of operation. Although physically
losses are waste of energy, they do help to damp out all the unwanted noise
in signal conductors, and VDD /Vss buses, planes, and etc. Consider a signal
conductor over a reference plane as shown in FigureC.l. If the transmission
line crossection geometry is much less than the wavelength (>.) of the maximum frequency of interest and if R is not more than 10
W max
L where
W max
178
is
SSN OF CMOS DEVICES AND SYSTEMS
/r
(Tr is the pulse risetime), a quasi-TEM model can be used to analyze
the transmission line interconnects. For this case, it can be shown that
d2 V
dz 2
= _ 12
V
(C.1)
where
=
1
J(R + jwL)(G + jwC)
(C.2)
and R, L, G, and Care per-unit-length resistance, inductance, conductance,
and capacitance of the interconnect geometry, respectively. The propagation
constant 1 can be written as,
(l'
+
Signal Conductor
h
\
jf3
(C.3)
.
I,(Z)
I,(Z+6Z)
~
~
+t
t+
V'2(Z) V'2(Z+6Z)
b
J
/
-+-
I,(Z)
Reference Plane
1-
..-
I,(Z+6Z)
Figure C.l. Signal conductor over a reference plane.
With the assumption that losses are small, but not negligible (R < <
wmaxL , and G
« wmaxC),
a
it can be shown [C.I]
~ 2~
+ ;
I¥
and
(C.4)
APPENDIX C
179
RG
4wVLC
G
4wC
(C.5)
Since the characteristic impedance of a loss less line is Zo = ~,
the frequency components of the pulse are uniformly attenuated (for the case
G=O) according to
-Rl)
A exp ( - Z
2Zo
IVI
which gives
V(l) I
IV(O)
=
exp
(-Rl)
(C.6)
2Zo
where Rl is the total resistance of the line of length l.
The exponent in
equation (C.6) can be rearranged so that
V(l) I
IV(O)
where
Td
= exp
(1
- '2
R
wmaxL
Td)
Tr
is the propagation time on a lossless line,
cally "long" line,
I.i.
Tr
>
1 ,
-2
Td
= lVLC.
For electri-
so that considerable attenuation is possible even if
~L«
W max
l.
From equation (C.5) it is clear that different frequency components of
the pulse propagation with different velocities, even if G=O. This "dispersive"
propagation results in distortion of the pulse, particularly on the leading and
trailing edges. Note that transmission line interconnects can be distortionless
in spite of being lossy. These conditions are met if the delay is frequency
independent, or equivalently if f3 is directly proportional to frequency, and a
is frequency independent [C.4]. It was shown that a transmission line interconnect is distortionless when
R
G
which gives
a
=
f3
Note that the phase constant
the lossless case, v
= k.
L
(C.7)
C
VRG,
=
wVLC
and
(C.S)
(C.9)
f3 then gives the same propagation velocity as
180
SSN OF CMOS DEVICES AND SYSTEMS
For further aspects of lossy lines the reader is referred to detailed
analyses of signal propagation on lossy transmission lines interconnects given
in references [C.2] and [C.3].
APPENDIX D
DISTRIBUTED, LUMPED TRANSMISSION LINE SPICE
MODELS AND ASSOCIATED FILTERING EFFECTS
In order to incorporate both the non-linear driver and receiver circuits, often transmission line interconnects are modeled using distributed,
lumped element models in digital systems. Since SPICE (or compatible)
circuit simulator is the most used transistor-level circuit simulator, system
designers utilize SPICE simulator to analyze signal integrity. One of the
problems in using SPICE to model transmission line interconnects in digital
systems is to choose the proper number oflumps/cm. Obviously, the trade-off
is between accuracy and CPU time. Note that the number of lumps/em will
perform a filtering effect on the waveforms [A.I].
Consider a single, loss less transmission line interconnect structure
described by the per-unit-Iength [PULl inductance (Lo), and capacitance (Co).
From the dispersion relation [C.4],
Sin(~l)
Here I is the lump length,
w
= w
7
(D.I)
is the angular frequency, and k is the wave-vector.
The group wave velocity (Vg) is given by,
Vg
=
dw
I
(kl)
dk = ...;r;;c; Cos "2
(D.2)
from equation (D.I),
k
(D.3)
182
SSN OF CMOS DEVICES AND SYSTEMS
It is clear from the dispersion relation that both the group velocity
and the wave-vector are complex functions of the lump length I, as evidenced
in equation (D.2) and (D.3), and the dispersion curve in Figure D.l.
w
7r
'2
Figure D.1 Dispersion relation.
Thus different number of lumps/ cm will have different filtering effects
on the simulation. When using SPICE, the user must be familiar with the
filtering effect in order to see which spikes are due to the transmission line
mismatches, and which are due to the model's filtering effect.
APPENDIX E
CMOS INVERTER ANALYSIS
In Figure E.I a simple CMOS inverter circuit is shown. The operation
of this circuit is discussed in detail in references [E.I] and [E.2]. Some aspects
of the operation will be summarized here for the convenience of the reader.
Vout(V)
Figure E.I Simple CMOS inverter circuit.
In order to have an equal low-to-high (tplh) and high-to-low (tphl)
184
SSN OF CMOS DEVICES AND SYSTEMS
delay, the following conditions are sufficient:
and
(E.1)
(E.2)
where
K
=
P Cox
(~)
(E.3)
and K, p, W, and L are subscripted either p or n. Here 1ft is the threshold
voltage, p is the carrier mobility (a measure of the ease of motion of the
electrons and holes within the semiconductor at the surface), Wand L are
"effective" channel width and length respectively, and Cox is the gate oxide
capacitance per unit area. Because of the difference in the effective mass of
electrons and holes, the mobilities are different (i.e. Pn ::/= pp). Silicon bulk
mobilities for lightly doped material are Pn=1350 ~r:.:.: and pp=480 ~r:.:.:,
whereas surface mobilities are in the range from 300-700 tr:.:.'., and 100-300
~r:.:.: for electrons and holes, respectively [E.3]. The electron to hole mobility
ratio is approximately 2 to 3 [E.4].
It is clear from equation (E.3) that to obtain Kn=Kp, one must have
larger channel width PMOS devices (Wp ) compared to the NMOS channel
width (Wn ) for a given channel length (Lejj). Generally, design engineers
have design rules from process/technology development groups describing the
appropriate ~ ratio required to obtain Kp=Kn for various choice of Wp (or
W n ). Note that it is necessary to have a symmetrical switching characteristics
to minimize clock skew problems. In addition, not only the D.C. switching
point, but also the dynamic noise immunity (both power and ground) depends
on the ~ ratio of the input receiver. The proper selection of ~ to achieve
symmetrical switching is even more important for reduced supply voltage
(VDD=3.3
In
is shown.
shown. In
V or 2.0 V) CMOS circuits to minimize clock skew.
Figure E.2a a typical CMOS inverter voltage transfer characteristic
In Figure E.2b the associated current switching characteristic is
Figure E.2b, it is assumed that the sub-threshold current is very
small compared to the saturation current, and it is neglected.
APPENDIX E
185
With the rail-to-railoutput swing (VOL=O and VO H =VDD), the D.C.
noise margin is given as
NML =
IVIL(max) -
N MH =
VOL(max)l,
lVoH(min) -
and
VIH(min) I
(E.4)
(E.5)
~=-1
VOL
= 0
(a)
(b)
Figure E.2 a) CMOS inverter voltage switching characteristics.
inverter current switching characteristics.
b) CMOS
186
SSN OF CMOS DEVICES AND SYSTEMS
Here VIH(min) = minimum high input voltage, VIL(max) = maximum low input voltage, VOH (min)=minimum high output voltage, and VOL (max) = maxIt can be shown for the general case, where
imum low output voltage.
Kp =F Kn and
IVtpl =F Vtn
2Vout
[E.1] that
+
Vtn
+ (~)
1
VIL =
(VDD -
IVtpl)
+ (~)
,and
2Vout
(E.7)
+ (~)
1
(E.6)
With the assumption Kp=Kn, it can be shown [E.2] that
NMH
=
N ML
For example, if
IVtpl
3VDD
=
+ 51Vtpl 8
3VDD -
3Vtn
31Vtpl +
8
,and
5Vtn
(E.8)
(E.g)
= Vtn = v VDD (where v <1.0), then
NMH
=
NML
=
(3
+
2v) VDD
8
(E.I0)
It is clear from equation (E.I0) that as we scale down the power supply voltage,
the noise margin will be reduced. With reduced noise margin, input receivers
may be more susceptible to simultaneous switching noise, and/or coupled
nOIse.
REFERENCES
CHAPTER 1
[1.1] M. A. Plonus, "Applied Electromagnetics," McGraw-Hill, Inc., New
York, 1978.
[1.2] S. Ramo, J. R. Whinnery, and T. V. Duzer, "Fields and Waves in
Communication Electronics," John Wiely fj Sons, Inc., New York,
1984.
[1.3] G. A. Katopis, "Delta-I Noise Specification for a High-Performance
Computing Machine," IEEE Proceedings, vol. 73, no. 9, p. 1405,
September 1985.
[1.4] A. J. Rainal, "Computing Inductive Noise of Chip Packages," ATfjT
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1984.
[1.5] E. E. Davidson, "Electrical Design of a High Speed Computer Package," IBM Journal of Research fj Development, vol. 26, no. 3, p.
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[1.6] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground
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Solid-State Circuits, vol. SC-26, no. 11, p. 1724, November 1991.
[1.7] M. Pasik, A. C. Cangellaris, and J. L. Prince,
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Power/Ground Plane Inductance and Resistance Calculator; Users's
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SSN OF CMOS DEVICES AND SYSTEMS
188
[1.8] R. Senthinathan, W. E. Pence, and N. Raver, "Signal Propagation
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CHAPTER 2
[2.1] G. Baccarani, M. R. Wordeman and R. H. Dennard, "Generalized
Scaling Theory and its Application to a 1/4 micrometer MOSFET
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[2.2] P. K. Chatterjee, W. R. Hunter, T. C. Holloway and Y. T. Lin, "The
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[2.3] Y. El-Mansy, "MOS Device and Technology constraints in VLSI,"
IEEE Trans. on Electron Devices, vol. ED-29, no. 4, p. 567, April
1982.
[2.4] J. D. Meindl, "Opportunities for Gigascale Integration," Solid State
Technology, vol. 30, no. 12, p. 85, December 1987.
[2.5] K. C. Saraswat and F. Mohammadi, "Effect of Scaling of Interconnects on the Time Delay of VLSI Circuits," IEEE Trans. on Electron
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[2.7] M. R. Scheinfein and J. L. Prince, "Electrical Performance of Integrated Circuit Packages: Three Dimensional Structures," Proc. of the
37th IEEE Electronic Components Conference, p. 377, May 1987.
[2.8] A. C. Cangellaris, J. L. Prince, and O. A. Palusinski, "Real Inductance Calculation for High Speed Interconnect Systems," Proc. of the
8th International Electronics Packaging Conference, p. 596, November 1988.
[2.9] R. Senthinathan, J. L. Prince and M. R. Scheinfein, "Characteristics of Coupled Buried Microstrip Lines by Modeling and Simulation.", IEEE Trans. on Components, Hybrids, Manuf. Technol., vol.
CHMT-12, no. 4, p. 604, December 1987.
[2.10] H. G. Parks and J. L. Prince, "The Influence of Loss Mechanisms
on VLSI/WSI Trends," 1990 Government Microcircuits Applications
Conference Digest of Papers, p. 555, Nov. 1990.
[2.11] J. M. Ford, "AI/Poly Si Specific Contact Resistivity," IEEE Trans.
on Electron Device Letters, vol. EDL-4, no. 7, p. 255, July 1983.
[2.12] H. Nozawa, S. Nishimura, Y, Horiike, K. Okumura, H. Iizuka, and
S. Kohyama, "High Density CMOS Processing for a 16K-Bit RAM,"
IDEM Tech. Digest., p. 366, December 1983.
CHAPTER 3
[3.1] A. J. Rainal, "Computing Inductive Noise of Chip Packages," ATCJT
Bell Laboratories Technical Journal, vol. 63, no. 1, p. 177, January
1984.
[3.2] G. A. Katopis, "Delta-I Noise Specification for a High-Performance
Computing Machine," IEEE Proceedings, vol. 73, no. 9, p. 1405,
September 1985.
[3.3] E. E. Davidson, "Electrical Design of a High Speed Computer Package," IBM Journal of Research CJ Development, vol. 26, no. 3, p.
349, May 1982.
SSN OF CMOS DEVICES AND SYSTEMS
190
[3.4] J. L. Prince and R. Senthinathan, "Methods of Calculating Simultaneous Switching Noise," Proc. of the 1991 NSF Multi-Chip Modules
workshop, p. 130, March 1991.
[3.5] R. Senthinathan, G. Tubbs and M. Schuelein, "Negative Feedback
Influence on Simultaneously Switching CMOS Outputs," Proc. of
the 1988 IEEE Custom Integrated Circuits Conference, p. 5.4.1, May
1988.
[3.6] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground
Noise Calculation for Packaged CMOS Devices," IEEE Journal of
Solid-State Circuits, vol. SC-26, no. 11, p. 1724, November 1991.
[3.7] R. Senthinathan and R. Yach, "High-speed 1 Jlm Output Driver Design Methodology," Intel Corporation: Technical Report, Arizona,
September 1988.
[3.8] J. C. Liao, O. A. Palusinski, and J. L. Prince, "Computation of Transients in Lossy VLSI Packaging Interconnects," IEEE Trans. on Components, Hybrids, and Manufacturing Technology, vol. 13, no. 4., p.
833, December 1990.
[3.9] R. Senthinathan, J. L. Prince, and S. Nimmagadda, "Effects of Skewing CMOS Output Driver Switching on the Simultaneous Switching
Noise," Proc. of the 1991 IEEE/CHMT International Electronics
Manufacturing Technology Symposium, p. 342, September 1991.
[3.10] A. C. Cangellaris, J. L. Prince, and O. A. Palusinski, "Real Inductance Calculation for High Speed Interconnect Systems," Proc. of the
8 th International Electronics Packaging Conference, p. 596, November 1988.
[3.11] R. Senthinathan and J. L. Prince, "Effect of Device and Interconnect
Scaling on the Performance and Noise of Packaged CMOS Devices,"
Proc.
of the 1990 IEEE Custom Integrated Circuit Conference, p.
11.3.1, May 1990.
REFERENCES
191
CHAPTER 4
A. C. Cangellaris, and J. 1. Prince,
"UALGRL,
Power/Ground Plane Inductance and Resistance Calculator; Users's
Guide," Center for Electronic Packaging Research (CEPR), Department of Electrical and Computer Engineering, University of Arizona,
Tucson, Arizona 8572l.
[4.1] M. Pasik,
[4.2] A. C. Cangellaris, J. L. Prince, and R. Senthinathan, "Modeling of
Power /Ground Plane Parasitics and Investigation of their Contribution to the Effective Inductance of VDD /Vss Chip-Package Interface,"
Proc. of the IEEE VLSI & GaAs Chip Packaging Workshop, p. 32,
October 1991.
[4.3] R. Senthinathan and R. Yach, "High-speed 1 J-lm Output Driver De-
sign Methodology," Intel Corporation: Technical Report, Arizona,
September 1988.
[4.4] M. A. Schmitt, K. Lam, L. E. Mosley, G. Choksi, and B. K. Bhattacharyya, "Current Distribution in Power and Ground Planes of a
Multilayered Pin Grid Array Package," Proc. of the 8th International
Electronics Packaging Conference, p. 467, November 1988.
[4.5] L. Vakanas, "Report on UALGRL Program," Technical Report: Motorola Corporation, Motorola: PEPL/Phoenix, Arizona, September
1990.
[4.6] M. Pasik and M. Gribbons, Private Communication.
[4.7] S. L. March, "Simple Equations Characterize Bond Equations," Journal of Microwaves & RF, p. 105, November 1991.
[4.8] A. J. Rainal, "Computing Inductive Noise of Chip Packages," AT&T
Bell Laboratories Technical Journal, vol. 63, no. 1, p. 177, January
1984.
[4.9] Y. Hiruta, K. Katoh, M. Masuda, K. Kobayashi, M. Segawa, H.
Shinya, and T. Katagiri, "Effects of Simultaneous Switching Noise
on the Performance of a High-Speed Static RAM and its Improved
Lead Frames," Proc. of the 1990 International Electronics Packaging
Conference, p. 787, November 1990.
SSN OF CMOS DEVICES AND SYSTEMS
192
CHAPTER 5
[5.1] W. E. Pence, "Simulated and Measured Characteristics of Triplate
Structures with Non-Continuous Ground Plane," Proc. 1991 Progress
in Electro. Res. Sym., p.721, July 1991.
[5.2] A. A. Oliner, "Equivalent Circuits for Discontinuities in Balanced
Strip Transmission Line," IRE Trans. Microwave Tech., vol. MTT3, p. 134, March, 1955.
[5.3] W. J. Hoefer, "Equivalent Series Inductivity of a Narrow Transverse
Slit in Microstrip," IEEE Trans. Microwave Theory Tech., vol. MTT25, p. 822, Oct. 1977.
[5.4] K. C. Gupta, R. Garg, and R. Chadha, "Computer-Aided Design of
Microwave Circuits," Artech House Inc., Massachussetts, 1981.
[5.5] Advanced Statistical Analysis Program (ASTAP), Program Reference
Manual, Pub. No. SH20-1118-0, IBM Corporation, Data Processing
Division, White Plains, N.Y. 10604.
[5.6] R. Senthinathan, J. L. Prince, and M. R. Scheinfein, "Characteristics
of Coupled Buried Microstrip Lines by Modeling and Simulation,"
IEEE Trans. Components, Hybrids, Manu/. Tech., vol. CHMT-12,
p. 604, Dec. 1987.
[5.7] J. L. Prince, R. Senthinathan, O. A. Palusinski, and M. R. Scheinfein,
"Electrical Characteristics of Single Buried Microstrip Lines in the
TEM Approximation," IEEE Trans. Components, Hybrids, Manu/.
Tech., vol. CHMT-11, p. 279, Sept. 1988.
[5.8] G. Arjavalingam, Y. Pastol, J.-M. Halbout, and G. V. Kopcsay,
"Broad-Band Microwave Measurements with
Transient Radiation
from Optoelectronically Pulsed Antennas," IEEE Trans. Microwave
Theory Tech., vol. 38, p. 615, May 1990.
[5.9] W. T. Weeks, "Calculation of Coefficients of Capacitance of Multiconductor Transmission Lines in the Presence of a Dielectric Interface,"
IEEE Trans. Microwave Theory Tech.,vol. MTT-18, p. 35, 1970.
[5.10] Touchstone Software, EEsof, Inc., Westlake Village, CA 91362.
[5.11] P. Brennan, N. Raver, and A. Ruehli, "Three-Dimensional Induc-
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tance Computations with Partial Element Equivalent Circuits," IBM
Journal of Research and Development, vol. 23, no. 6, 1979.
"An Electromagnetic Approach for Modeling High[5.12] B. J. Rubin,
Performance Computer Packages," IBM Journal of Research and Development, vol. 34, July 1990.
CHAPTER 6
[6.1] R. Senthinathan, G. Tubbs and M. Schuelein, "Negative Feedback
Influence on Simultaneously Switching CMOS Outputs," Proc. of
the 1988 IEEE Custom Integrated Circuits Conference, p. 5.4.1, May
1988.
[6.2] R. Senthinathan and J. L. Prince, "Effect of Device and Interconnect
Scaling on the Performance and Noise of Packaged CMOS Devices,"
Proc. of the 1990 IEEE Custom Integrated Circuit Conference, p.
11.3.1, May 1990.
[6.3] R. Senthinathan and R. Yach, "High-speed 1 J.lm Output Driver Design Methodology," Intel Corporation: Technical Report, Arizona,
September 1988.
[6.4] J. L. Prince and R. Senthinathan, "Methods of Calculating Simultaneous Switching Noise," Proc. of the 1991 NSF Multi-Chip Modules
Workshop, p. 130, March 1991.
[6.5] W. H. Hayt, and J. E. Kemmerly, "Engineering Circuit Analysis,"
McGraw-Hill, Inc., New York, 1978.
CHAPTER 7
[7.1] R. Senthinathan and R. Yach, "High-speed 1 J.lm Output Driver Design Methodology," Intel Corporation: Technical Report, Arizona,
September 1988.
[7.2] I. Tomioka, M. Hyozo, M. Okabe, S. Kishida, T. Arakawa, and Y. Kuramitsu, "Current Control Buffer for Multi Switching CMOS SOG,"
SSN OF CMOS DEVICES AND SYSTEMS
194
Proc.
of the 1990 IEEE Custom Integrated Circuit Conference, p.
11.7.1, May 1990.
[7.3] K. Leung, "Controlled Slew Rate Output Buffer," Proc. of the 1988
IEEE Custom Integrated Circuit Conference, p. 5.3.3, May 1988.
[7.4] N. Raver,
"Open-Loop Gain Limitations for Push-Pull Off-Chip
Drivers," IEEE Journal of Solid-State Circuits, vol. SC-22, no. 2, p.
145, April 1987.
[7.5] M. Hashimoto, and O. Kwon, "Low di/dt Noise and Reflection Free
CMOS Signal Driver," Proc. of the 1989 IEEE Custom Integrated
Circuit Conference, p. 14.4.1, May 1989.
[7.6] Y. Itoh, K. Nakagawa, K. Sakui, F. Horiguchi, and M. Ogura, "NoiseGeneration Analysis and Noise-Suppression Design Techniques in
Megabit DRAMs," IEEE Journal of Solid-State Circuits, vol. 22,
no. 4, p. 619, August 1987.
[7.7] T. Wada, M. Eino, and K. Anami, "Simple Noise Model and LowNoise Data-Output Buffer for Ultra high-Speed Memories," IEEE
Journal of Solid-State Circuits, vol. 25, no. 6, p. 1586, December
1990.
[7.8] D. A. Hodges and H. G. Jackson, "Analysis and Design of Digital
Integrated Circuits," McGraw-Hill, Inc., New York, 1983.
[7.9] M. Shoji, "CMOS Digital Circuit Technology," Prentice-Hall, Inc.,
New Jersy, 1988.
[7.10] P. R. Gray and R. G. Meyer, "Analysis and Design of Analog Integrated Circuits," John Wiley fj Sons, Inc., New York, 1984.
[7.11] R. Senthinathan and J. L. Prince,
"Application Specific CMOS
Output Driver Design Techniques to Reduce Simultaneous Switching Noise," (accepted for pUblication), IEEE Journal of Solid-State
Circuits.
[7.12] J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, "Signal Delay in
RC Tree Networks," IEEE Trans. on Computer-Aided Design, vol.
CAD-2, p. 202, July 1983.
REFERENCES
195
CHAPTER 8
[8.1] R. Senthinathan, J. L. Prince, and A. C. Cangellaris,
"Module Frequency Estimation and Noise Budget Limitations/Tradeoffs in MultiChip Modules as a Function of CMOS Chips Integration," (accepted
for publication) IEEE Trans. Components, Hybrids, Manuf. Tech.
[8.2] R. Senthinathan and J. L. Prince, "Electrical Performance Analy-
sis of Packaged CMOS ASIC Devices and Systems," Proc. of the
1992 IEEE Application Specific Integrated Circuit Conference, p. 222,
September 1992.
[8.3] R. Senthinathan and J. L. Prince, "Design of Controlled Slew Rate
CMOS Output Driver and Optimum Package-Pin Placement to Minimize the "Effective" Power/Ground Switching Noise," Proc. of the
1992 IEEE Topical Meeting on Electrical Performance of Electronic
Packaging, p. 15, April 1992.
[8.4] B. Downing, P. Gebler, and G. Katopis, "Decoupling Capacitor Effects on Switching Noise," Proc. of the 1992 IEEE Tropical M eeting on Electrical Performance of Electronic Packaging, p. 148, April
1992.
[8.5] P. A. Sandborn, H. Hashemi, and B. Weigler, "Switching Noise in
Medium Film Copper/Polymide Multi-Chip Module," Proc. of 1990
SPIE, International Conference on Advances in Interconnection and
Packaging, vol. 1389, p. 177, 1990.
[8.6] P. Hsu, R. Senthinathan, J. W. Rozenblit, and J. L. Prince, "A
knowledge-Based Simulation Environment for Early Design of MultiChip Modules," (accepted for publication) Microelectronics Journal,
July 1993.
[8.7] M. Pasik,
A. C. Cangellaris,
and J. L. Prince,
"UALGRL,
Power/Ground Plane Inductance and Resistance Calculator; Users's
Guide," Center for Electronic Packaging Research (CEPR), Department of Electrical and Computer Engineering, University of Arizona,
Tucson, Arizona 8572l.
[8.8] A. C. Cangellaris, J. L. Prince, and R. Senthinathan, "Modeling of
SSN OF CMOS DEVICES AND SYSTEMS
196
Power/Ground Plane Parasitics and Investigation of their Contribution to the Effective Inductance of VDD /Vss Chip-Package Interface,"
Proc. of the IEEE VLSI8 GaAs Chip Packaging Workshop, p. 32,
Oct. 1991.
[8.9] M. Nagata, "Limitations, Innovations, and Challenges of Circuits and
Devices into a Half Micrometer and Beyond," IEEE Journal of SolidState Circuits, vol. SC-27, No.4, p. 465, April 1992.
CHAPTER
9
[9.1] R. Senthinathan, J. L. Prince, and S. Nimmagadda,
"Noise Im-
munity Characteristics of CMOS Receivers and Effects of Skewing/Damping CMOS Output
Driver Switching Waveform on the
Simultaneous Switching Noise," Microeledronics Journal, vol. 23,
no. 1, p. 29, March 1992.
[9.2] C. R. Paul, "Modeling Electromagnetic Interference Properties of
Printed Circuit Boards," IBM Journal Research 8 Development, vol.
33, no. 1, P. 33, Jan. 1989.
[9.3] R. Senthinathan and R. Yach, " High-speed 1 f.1m Output Driver Design Methodology.", Intel Corporation: Technical Report, Chandler,
Arizona, Sept. 1988.
[9.4] J. C. Liao, O. A. Palusinski, J. L. Prince, P. E. Teshan, and F. Quintero, "University of Arizona Capacitance Calculator, Users Manual,"
Center for Electronic Packaging Research, Dept. ECE: University of
Arizona, June 1986.
[9.5] L. P. Vakanas, A. C. Cangellaris, and J. L. Prince, "University of
Arizona Two- Dimensional Frequency- Dependent Inductance and Resistance Calculator, Users Manual," Center for Electronic Packaging
Research, Dept. ECE: University of Arizona, Sept. 1989.
[9.6] A. E. Ruehli, "Inductance Calculation in a Complex Integrated Circuit Environment," IBM Journal Research 8 Development, vol. 16,
no. 5, p. 470, Sept. 1972.
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197
[9.7] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground
Noise Calculation for Packaged CMOS Devices," IEEE Journal of
Solid-State Circuits, vol. SC-26, no. 11, p. 1724, Nov. 1991.
[9.8] A. C. Cangellaris, J. L. Prince, and R. Senthinathan, "Modeling of
Power/Ground Plane Parasitics and Investigation of their Contribution to the Effective Inductance of VDD /Vss Chip-Package Interface,"
Proc. of the IEEE VLSI fj GaAs Chip Packaging Workshop, p. 32,
Oct. 1991.
[9.9] J. C. Liao, O. A. Palusinski, and J. L. Prince, "Computation of Transients in Lossy VLSI Packaging Interconnects," IEEE Trans. on Components, Hybrids, and Manufacturing Technology, vol. 13, no. 4., p.
833, Dec. 1990.
[9.10] A. Feller, H. R. Kaupp, and J. J. Digiacomo, "Crosstalk and Reflections in High-Speed Digital Systems," Proc. of the 1965 Fall Joint
Computer Conference, p. 511, 1965.
CHAPTER 11
[11.1] G. A. Katopis and E. Davidson, "Private Communication," IBM:
East Fishkill Semiconductor Labs, East Fishkill, NY 12533.
[11.2] W. Fang, A. Brunnschweiler, and P. Ashburn, "An Accurate Analytical BiCMOS Delay Expression and its Application to Optimizing
High-Speed BiCMOS Circuits," IEEE Journal of Solid-State Circuits,
p. 191, vol. 27, no. 2, February 1992.
[11.3] E. W. Grenneich and K. 1. McLaughlin, "Analysis and Characterization of BiCMOS for High-Speed Digital Logics," IEEE Journal of
Solid-State Circuits, p. 558, vol. 23, no. 1, February 1989.
[11.4] G. P. Rosseel and R. W. Dutton, "Influence of Device Parameter on
the Switching Speed of BiCMOS Buffers," IEEE Journal of SolidState Circuits, p. 90, vol. 24, no. 1, February 1989.
[11.5] R. Senthinathan, R. Yach, G. Tubbs, and B. Bhattacharyya, "Investigation of Substrate-Taps for CMOS Twin-Tub Process Technology,"
SSN OF CMOS DEVICES AND SYSTEMS
198
Internal Memo, Intel Corporation, Chandler, Arizona 87226.
[11.6] A. Mehra, "Private Communication," CEPR, Dept. of ECE: University of Arizona, Tucson, Arizona 85721.
[11.7] T. Gabara, "Reduced Ground Bounce and Improved Latch-Up Suppression Through Substrate Conduction," IEEE Journal of SolidState Circuits,p. 1224, vol. 23, no. 5, October 1988.
APPENDIX
[A.1] R. Senthinathan,
"Electrical Characteristics of Integrated Cir-
cuit Packages," M. S. Thesis, Department of Electrical & Computer
Engineering, The University of Arizona, Tucson, 1987.
[A.2] W. T. Weeks, "Calculation of Coefficients of Capacitance of Multiconduct or Transmission Lines in the Presence of a Dielectric Interface,"
IEEE Trans. Microwave Theory Tech.,vol. MTT-18, p. 35, 1970.
[C.1] R. E. Matick, "Transmission Lines for Digital and Communications
Networks," McGraw-Hill Inc., New York, 1969.
[C.2] A. Deutsch et. aI., "High-Speed Signal Propagation on Lossy Transmission Lines," IBM Journal of Research
fj
Development, p. 601, vol.
34, no. 4, July, 1990.
[C.3] A. Voranantukul, J. L. Prince, and P. Hsu, "Crosstalk Analysis for
High Speed Pulse Propagation in Lossy Electrical Interconnects,"
IEEE Trans.
Components, Hybrids, Manuf.
Tech., p.127, vol. 16,
no. 1, February 1993.
[C.4] S. Ramo, J. R. Whinnery, and T. V. Duzer, "Fields and Waves in
Communication Electronics," John Wiely
fj
Sons, Inc., New York,
1984.
[E.1] D. A. Hodges and H. G. Jackson, "Analysis and Design of Digital
Integrated Circuits," McGraw-Hill, Inc., New York, 1988.
[E.2] N. Weste and K. Eshraghian, "Principles of CMOS VLSI Design: A
Systems Perspective," Addison- Wesley, Inc., Massachusetts, 1985.
[E.3] R. S. Muller and T. 1. Kamins, "Device Electronics for Integrated
Circuits," John Wiely
fj
Sons, Inc., New York, 1986.
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[E.4] D. K. Ferry, L. A. Akers, and E. W. Greeneich, "Ultra Large Scale
Integrated Microelectronics," Prentice-Hall, Inc., New Jersy, 1988.
Index
A
Address bus 32,87,117,124,125
Architecture 3,6,117-122,128,165
ASIC 100
ASTAP 6,57,60-63,73
B
BiCMOS drivers 161-165
BITs 161-165
BNC T-junction 74
Board parasitics 1,4
Bond wire inductance
-(L bond) 37,38,40
Buried microstrip line 57,58
C
Capacitive loading 100,102
Ceramic DIP (CDIP) 33
Ceramic Quad Flat Pack (CQFP) 33
Channel doping 9
Charge accumulation 36
Charging current 100,102
Clock drivers 17
Clock frequency 117
Clock wait cycle 87,91
Complementary switch 104
Complete isolation 141,142
Constant field [CE] 3,9
Constant voltage [CV] 3,9
Contact resistance 9,12,13,17
Contact windows 13
Continuity equation 36
Controlled collapse
-connection (C4) 5,122,141
Controlled Slew
-Rate (CSR) 102,105-115,120
Critical height (h c) 57
Current controlled
-(CC) 102,103-105,120
Current density 10,36
Current distribution 5,34,42,48,51
Current mirror 103
Current spreading 163,164
Current unregulated 100,103-105
D
Damping coefficient 87,91
Damping resistor 87,93-97
Data bus 117,124,125
De coupling 6
Delta-II
Die area 12
Diffusion+contact resistance 13
Diffusion resistance 13,17
Discharging current 24,102,103
Discretization distance 37
Doping 9,10
INDEX
202
Double clocking 99
DRAM 12
Lniverpe~bationsl19
Lnive capability 1,4,19,126
Lniver segments 111
Dual in line package (DIP) 5,33
E
Equipotential 40
Electric field 35
Electric induction 136,140
Electric potential 35
External buses 4,20,107,141
External power 2,85
F
Faraday's law 2
Far-end crosstalk 144-155
Finite element solution 36
Flux linkage 2
FR-4 5
Frequency dependent power 10
Fringing factor 112
Full-wave solver 57,80,83
G
Gap perforations 72
Gate oxide 10
Global minimum 92
Green's function 36,168,169
Ground bounce 1,20
H
Hardware prototype 84
Hot electrons 9
I
Input receivers 27,86
Interconnect scaling 3,10,13
Interline capacitance 13
Internal buses 4,86,106
Internal gates 35,107,118
Internal inductance 139
Internal logic 19,23,90
Inversion layer 9
Isolated ground 130,131
J
Junction depth 9
K
Kirchoffs law 173
L
L3D inductance extractor 67,83
Laplace's equation 36
Lead frame 40
Line capacitance 12,13
Line resistance 12,13
Line voltage drop 13
Local minimum 92
Loop inductance 68,71
M
Magnetic diffusion 35,36
Magnetic flux 2
Magnetic vector potential 37
Mathematical induction theorem 46
Matrix method 171-173
Maximum interconnect length 12
Maxwell's equation 167
Methods Of Moments (MOM) 169
Microstripline 11
INDEX
Missing clock pulse 99
Multi-Chip Modules
-(MCMs) 85,87,91,121-129
Multilayer package 20,33
203
N
Poly interconnect 11
Poly resistor 112
Power-delay product 10
Power dissipation 10
Power dissipation density 10
Pre-driver's 106-108
N+/AI contacts 13
Q
Near-end crosstalk 145-155
Network analyzer 61
Noise immunity 6,27,85-97,114
Noisy plane 129-159
o
Offset voltage 120
Ohm's law 9,36
Overlap current 24,100
p
P +/ AI contacts 13
P + - substrate 164
Partial inductance 130,134-140
Perforated plane 5,37
Perforation width (Wp) 80
Pin grid array (PGA) 5,21,46,114
Pin inductance
-(L pin) 27,40,123,154
Pin to pin timings 17
Plane connected ground 142-151
Plane inductance
-(L plane) 34-51,123,154
Plated through hole 81
Plexiglass 58
Poisson's equation 167
Quad flat package (QFP) 5,33
Quasi-constant voltage [QCV] 10
Quasi-Newton optimization 62
Quasi-period 91,92
Quiet drivers 144
R
Radian frequency 36
RC tree 112
Rent's rule 124
Return current path 81
RMS current 120
Ruehli's algorithm 137,138
s
Scaled-up model 5,54-80
Scaling factor 10-14
Si-Si0 2 interface 11
Sink/source points 38-51
Skewing 6,86,87,91-97
Skin depth 35,139
SMA connector 81
Sockets 53
Source/drain resistance 9
S-parameter 5,57,60-64
Specific contact resistivity 13
SRAM40
SSNS architecture 6,117-121,128
Stored energy 45
INDEX
204
Substrate taps 163-165
Superposition theory 5,41,45,122
T
Tape Automated Bonding
-(TAB) 34,122
TDR 6,54,63,72-83
1EM-mode 167-171
Thick film interconnects 136-156
Thin film interconnects 136-156
Through
-current 100-102,105,108-112
Time constant 13
Time-domain waveform 53,83
Tri-statable 100,106-115
TIL-compatible 20,27,86-89
Twin-tub process 164
Two-port calibration 61
u
UA2DL 137-140
UAC 136-140
UALGRL 5,35-38,122
UAMOM 169-171
UANTL 24,114
UASSNS 6,117-121,165
Underdamped
-oscillation 87,94,95
v
Velocity saturation 9
Vias 33,123,130
w
Week's method 168
Weighting scheme 112
x
x-v wiring pairs 60
y
z
Zero-frequency limit 167
ABOUT THE AUTHORS
Ramesh Senthinathan
Ramesh Senthinathan is working as a senior engineer at the Advanced Packaging
Development Center, Motorola, Inc. From 1992-93 he worked as a staff engineer at
the IBM Fishkill Semiconductor Packaging Labs. From 1987-89, he worked as a
design engineer at ASIC & microcontroller divisions, Intel corporation. He worked
as a summer intern at IBM, Hestia, GTE, and Honeywell corporations. He received
his B.S. degree in computer engineering from the State University of New York at
Buffalo in 1984. He received his M.S. & Ph.D. degrees in electrical engineering
from the University of Arizona in 1987 and 1992, respectively.
John L. Prince
John L. Prince is Professor of Electrical & Computer Engineering at the University
of Arizona (UA), Tucson, Arizona. He leads a group of faculty and student
researchers involved in developing methods for analysis and prediction of electrical,
thermal and mechanical performance of packaging structures for high speed
ULSI/VLSI circuits. In addition, from 1991 to 1992, he served as Distinguished
Visiting Scientist and Director (Acting) of Packaging Sciences at Semiconductor
Research Corporation. He is a fellow of the IEEE. He received his Ph.D. in
Electrical Engineering from North Carolina State University (Raleigh, NC) in
1969, after receiving a B.S.E.E. degree from Southern Methodist University
(Dallas, TX) in 1965. He has been at UA for ten years. Earlier in his career he was
at the Research Triangle Institute (1968-70), Texas Instruments, Inc. (1970-75),
Clemson University (1975-80), and Intermedics, Inc (1980-83).