DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING
EEE 2408: Integrated Circuits
Week 1
Instructor: Mr. Peter Karanja
Email: peterkaranja@jkuat.ac.ke
LECTURE 2A:
FROM SAND TO SILICON
EEC 2408 – Integrated Circuits
September 2023
PERSPECTIVE
The deserts of Arizona are home to Intel’s Fab 32, a $3 billion factory that’s performing one of the
most complicated electrical engineering feats of our time. It’s here that processors with components
measuring just 45 millionths of a millimeter across are manufactured, ready to be shipped out to
motherboard manufacturers all over the world. Creating these complicated miniature systems is
impressive enough, but it’s not the processors’ diminutive size that’s the most startling or impressive
part of the process.
It may seem an impossible transformation, but these fiendishly complex components are made from
nothing more glamorous than sand. Such a transformative feat isn’t simple. The production process
requires more than 300 individual steps.
Fig 1. IC Fabrication Process
In the lecture series that shall follow, we shall take an in-depth look at the manufacturing method
and distill the whole process into the individual component stages. So, to find out how sandcastles
become Core i7 & AMD processors, read on – and prepare to be amazed.
Lecture Objectives
In this first lecture in a 2-part series we delve into the process of production of semiconductor wafers.
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TABLE OF CONTENTS
1.0
INTRODUCTION: Silicon Wafers.............................................................................................................4
1.1
PART 1: WAFER FABRICATION PROCESS ............................................................................................5
1.1.1
STEP ONE: Converting sand to silicon ........................................................................................ 5
1.1.2
STEP TWO: Ingot Growth............................................................................................................ 6
1.1.3
STEP THREE: Slicing ................................................................................................................... 7
1.1.4
STEP FOUR Cleaning .................................................................................................................. 8
1.1.5
STEP FIVE: Polishing................................................................................................................... 9
1.1.6
STEP SIX: Packaging ................................................................................................................... 9
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EEC 2408 – Integrated Circuits
1.0
September 2023
INTRODUCTION: Silicon Wafers
Silicon is the material that forms the bedrock of modern-day semiconductors.
Silicon is a gray, brittle, tetravalent, chemical element. It is the 7th most abundant element in the
universe and makes up 27.8% of the earth’s crust and next to oxygen, it is the most abundant element
in nature. Some of the most common materials that contain silicon are quartz, agate, flint, and
common beach sand, among others. It is the main component in building materials like cement, brick
and glass. Silicon is also the most common material used to build semiconductors and microchips.
Ironically, silicon by itself does not conduct electricity very well; however, it can take on dopants
precisely in order to control resistivity to an exact specification.
A wafer is a fairly thin disc of a semiconductor material such as silicon. It is used as a support for the
manufacture of microstructures. These micro-structures are a major component in the manufacture
of integrated circuits, transistors, power semiconductors. The wafers can be of different sizes from 1
inch (25.4 mm) up to 300 mm for a thickness of the order of 0.7 mm. The trend is to use the largest
wafers possible to be able to burn more chips simultaneously and limit losses on the edge of the
plate, resulting in increased production at a lower cost. We print integrated circuits, transistors, and
power semiconductors on these tight grid wafers to put as much as possible on a single silicon or
semiconductor wafer.
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September 2023
1.1
PART 1: WAFER FABRICATION PROCESS
1.1.1
STEP ONE: Converting sand to silicon
Before a semiconductor can be built, silicon must turn into a wafer. This begins with the growth of a
silicon ingot. A single silicon crystal consists of atoms arranged in a three-dimensional periodic
pattern that extends throughout the material. A polysilicon crystal is formed by many small single
crystals with different orientations, which alone, cannot be used for semiconductor devices.
Sand is composed of silica (also known as silicon dioxide SiO2) and is the starting point for making
a processor.
Sand used in the building industry is often yellow, orange or red due to impurities, but the type
chosen in the manufacture of silicon is a purer form known as silica sand, which is usually recovered
by quarrying.
The starting material for Si manufacture is quartzite (SiO2) or sand. The ore is reduced to Si by mixing
with coke and heating in a submerged electrode arc furnace. The SiO2 reacts with excess C to first
form SiC. At high temperature (2,000°C), the SiC reduces SiO2 to form Si. The overall reaction is given
By
SiC (s) + SiO2 (s) → Si (l) + SiO (g) + CO (g)………………………..(1)
The Si(l) formed is removed from the bottom of the furnace. This is the Metallurgical grade Silicon
(MGS) and is around 98% pure.
This is not nearly pure enough for semiconductor manufacture. The next task is to refine the
Metallurgical grade Silicon (MGS) further to Electronic Grade Silicon (EGS). One of the techniques for
converting MGS to EGS is called the Seimens process. In this process the Si is reacted with HCl gas
to form tricholorosilane, which is in gaseous form.
Si (s) + 3HCl (g) → SiHCl3 (g) + H2 (g) ………………………..(2)
The reaction is performed in a fluidized-bed reactor at temperatures around 300oC (550oF).
Trichlorosilane (SiHCl3), although shown as a gas in Eq. 2, is a liquid at room temperature. Its low
boiling point of 32oC (90oF) permits it to be separated from the leftover impurities of MGS by
fractional distillation.
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The final step in the process is reduction of the purified Trichlorosilane by means of hydrogen gas.
The process is carried out at temperatures up to 1000oC (1800oF), and a simplified equation of the
reaction can be written as follows:
2SiHCl3 (g) + 2H2 (g) → 2Si (s) + 6HCl (g) ………………………..(3)
The product of this reaction is electronic grade silicon—nearly 100% pure Si.
1.1.2 STEP TWO: Ingot Growth
Although pure to a very high degree, raw electronic-grade silicon has a polycrystalline structure. In
other words, it’s made up of lots of small silicon crystals, with defects called grain boundaries
between them. Because these anomalies affect local electronic behaviour, polycrystalline silicon is
unsuitable for semiconductor manufacturing.
To turn it into a usable material, the silicon must be turned into single crystals that have a regular
atomic structure. This transformation is achieved through the Czochralski Process and the Float
zone technique.
Fig 1.
Czochralski Process
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To grow an ingot, the first step is to heat the silicon to 1500°C, which is above the melting point of
silicon (1412°C). Once the polycrystalline and dopant combination has been liquified, a single silicon
crystal, the seed, is positioned on top of the melt, barely touching the surface. The seed has the same
crystal orientation required in the finished ingot.
To achieve doping uniformity, the seed crystal and the crucible of molten silicon rotate in opposite
directions. Once the system reaches proper conditions for crystal growth, the seed crystal slowly lifts
out of the melt. Growth begins with a rapid pulling of the seed crystal. This minimizes the number
of crystal defects within the seed at the beginning of the growing process.
After this, the pull speed reduces to allow the diameter of the crystal to increase. When the desired
diameter is obtained, the growth conditions are stabilized to maintain the diameter. As the seed is
slowly lifts above the melt, the surface tension between the seed and the melt causes a thin film of
the silicon to adhere to the seed and then to cool. While cooling, the atoms in the melted silicon
orient themselves to the crystal structure of the seed.
The final solidified Si obtained is the single crystal ingot. A 450 mm wafer ingot can be as heavy as
800 kg. A picture of a such an ingot is show in figure 2.
1.1.3 STEP THREE: Slicing
Integrated circuits are approximately linear, which is to say that they’re formed on the surface of the
silicon. To maximize the surface area of silicon available for making chips, the boule is sliced up into
discs called wafers.
Fig 2.
Slicing of Ingot into wafers
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After passing a number of inspections, the ingot proceeds to slicing. Because of the silicon’s hardness,
a diamond edge saw carefully slices the silicon wafers so they are slightly thicker than the target
specification. The diamond edge saw also helps to minimize damage to the wafers, thickness
variation, and bow and warp defects.
After the wafers have been sliced, the lapping process begins. Lapping the wafer removes saw marks
and surface defects from the front and backside of the wafer. It also thins the wafer and helps to
relieve stress accumulated in the wafer from the slicing process. After lapping the silicon wafers,
they go through an etching and cleaning process. Sodium hydroxide or acetic and nitric acids
alleviate any microscopic cracks and/or surface damage that may have come about during lapping.
The nitric acid oxides the surfaces to give a thin layer of silicon dioxide which the hydrofluoric acid
immediately dissolves away to leave a clean silicon surface – and the acetic acid controls the reaction
rate.
A critical edge grinding procedure takes place to round the edges, drastically reducing the probability
of breakage in the remaining steps of manufacturing and later when device manufacturers use the
wafers.
After rounding the edges, depending on the end user’s specification, oftentimes the edges will go
through an extra polishing step, improving overall cleanliness and further reducing breakage up to
400%.
1.1.4 STEP FOUR Cleaning
The final and most crucial step in the manufacturing process is polishing the wafer. This process
takes place in a clean room. Clean rooms have a rating system that ranges from Class 1 to Class
10,000. The rating corresponds to the number of impurity particles per cubic foot. These particles are
not visible to the naked eye and in an uncontrolled atmosphere, such as a living room or office, the
particle count would likely be 5 million per cubic foot. To help maintain this level of cleanliness, the
workers must wear clean room suits that cover their body from head to toe and do not collect or
carry any particles. They also stand under a fan that blows away any small particles that might have
accumulated before entering the room.
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1.1.5 STEP FIVE: Polishing
Most prime grade silicon wafers go through 2-3 stages of polishing, using progressively finer slurries
or polishing compounds. The majority of the time, wafers are polished on the front side only,
excluding 300mm wafers which are double side polished. Polishing produces a mirror finish. The
polish also distinguishes which side to use for device fabrication. This surface must be free of
topography, micro-cracks, scratches, and residual work damage.
The polishing process occurs in two steps, which are stock removal and final chemical mechanical
polish (CMP). Both processes use polishing pads and polishing slurry. The stock removal process
removes a very thin layer of silicon and is necessary to produce a wafer surface that is damage-free.
On the other hand, the final polish does not remove any material. During the stock removal process,
a haze forms on the surface of the wafer, so an extra polishing step gives the wafer a mirror finish.
After polishing, the silicon wafers proceed to a final cleaning stage that uses a long series of clean
baths. This process removes surface particles, trace metals, and residues. Oftentimes a backside
scrub is done to remove even the smallest particle.
1.1.6 STEP SIX: Packaging
Once the wafers complete the final cleaning step, engineers sort them by specification and inspect
them under high intensity lights or laser-scanning systems. This detects unwanted particles or other
defects that may have occurred during fabrication. All wafers that meet the proper specifications are
packaged in cassettes and sealed with tape. The wafers ship in a vacuum-sealed plastic bag with an
airtight foil outer bag. This ensures that no particles or moisture enters the cassette upon leaving the
clean room.
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