Fundamentals of Signal and Power Integrity Christian Schuster Distinguished Lecturer for the IEEE EMC Society 2012-13 Institute of Electromagnetic Theory Hamburg University of Technology (TUHH) Acknowledgements Renato Rimolo-Donadio, Xiaomin Duan, Sebastian Müller, Miroslav Kotzev, Heinz-Dietrich Brüns Young Kwark, Xiaoxiong Gu, Mark Ritter, Bruce Archambeault, Dale Becker, Thomas-Michael Winkel, Hubert Harrer … and many others! Christian Schuster – 2 Abstract This presentation will give an introduction to the fundamentals of signal and power integrity engineering for high-speed digital systems with a focus on packaging aspects. The presentation is intended for an audience that has little or no formal training in electromagnetic theory and microwave engineering. Topics that will be addressed include lumped discontinuities, transmission line effects, crosstalk, bypassing and decoupling, via and power plane effects, return current issues, and measurement techniques for Gbps links. More information on current research projects at the Institute of Electromagnetic Theory can be found at: http://www.tet.tuhh.de/ Christian Schuster – 3 A Bird‘s Eye View on SI, PI & EMC Driver Via PCB Power Plane Ground Plane DC Power Supply Receiver Christian Schuster – 4 A Bird‘s Eye View on SI, PI & EMC Signal Transmission Issues: Attenuation, Reflection, Dispersion, Interference, Crosstalk Christian Schuster – 5 A Bird‘s Eye View on SI, PI & EMC Signal Transmission Issues: Attenuation, Reflection, Dispersion, Interference, Crosstalk Christian Schuster – 6 A Bird‘s Eye View on SI, PI & EMC Power Delivery Issues: Voltage Drop, Switching Noise, Crosstalk Christian Schuster – 7 A Bird‘s Eye View on SI, PI & EMC Power Delivery Issues: Voltage Drop, Switching Noise, Crosstalk Christian Schuster – 8 A Bird‘s Eye View on SI, PI & EMC Electromagnetic Compatibility Issues: Near Field Coupling, Radiated Emissions Christian Schuster – 9 A Bird‘s Eye View on SI, PI & EMC Electromagnetic Compatibility Issues: Near Field Coupling, Radiated Emissions Christian Schuster – 10 SI + PI + EMC = “Electrical Integrity“ Christian Schuster – 11 Outline (1) Hamburg and TUHH (2) Signal Integrity (3) Power Integrity (4) Vias and Return Currents (5) Measurement Techniques (6) Wrapping Up Christian Schuster – 12 (1) Hamburg and TUHH Christian Schuster – 13 Christian Schuster – 14 Hamburg University of Technology © TUHH Downtown Founded 1978 Approx. 6000 Students Approx. 100 Faculty Members Christian Schuster – 15 Hamburg University of Technology © TUHH Christian Schuster – 16 What We Do at TUHH D B 0 B E t D H J t Maxwell‘s Equations Printed circuit board layout Christian Schuster – 17 (2) Signal Integrity Christian Schuster – 18 Electrical Integrity of Digital Systems Christian Schuster – 19 Packaging of Digital Systems Cable Daughtercard Housing / Chassis IC (Transmitter) IC (Receiver) Package / Module Socket Connector Connector Backplane / Motherboard Christian Schuster – 20 Packaging of Digital Systems Interconnect (Link) Connector Christian Schuster – 21 Effect of Interconnects The ideal interconnect will simply delay the signal: Tx Rx t Any real interconnect will additionally change timing and amplitude: Rx Tx t Christian Schuster – 22 Effect of Interconnects The deviations in timing and amplitude are in general called: t Timing jitter or simply: Amplitude noise or simply: NOISE Christian Schuster – 23 JITTER Signal Bandwidth f max s(t ) ŝ 1 0.3 .. 0.5 TR rise time Maximum Frequency ŝ / 2 TB t TR 1 0.5 f0 2TB bit period Fundamental Frequency Christian Schuster – 24 Maintaining Signal Integrity 1. Match terminations 2. Manage discontinuities 3. Reduce Coupling 4. Limit attenuation 5. Equalize signals Christian Schuster – 25 Effect of Terminations Let‘s use the following interconnect (link) model: Z 0, , l ZS u0 Transmitter ZL u1 u2 Interconnect Christian Schuster – 26 Receiver ?? Transmission Lines in Digital Systems Microstrip Line Z0 87 5.98 h ln r 1.41 0.8 w t (h = height of dielectric, w = conductor width, t = conductor thickness) Stripline (symmetric) Z0 60 1.9 h ln r 0.8 w t (h = height of dielectric, w = conductor width, t = conductor thickness) Metal Christian Schuster – 27 Dielectric Transmission Lines in Digital Systems Typical trace length ≈ 5 – 75 cm Velocity of propagation ≈ 150 000 km/s Operating frequency ≈ 5 GHz Corrsponding wavelength ≈ 3 cm Delay ≈ 5 ns … up to 25 wavelengths on a trace! Printed circuit board layout Christian Schuster – 28 Effect of Terminations Let‘s use the following interconnect (link) model: Z 0, , l ZS u0 ZL u1 u2 u2 const. and max. ! u0 Christian Schuster – 29 ?? Effect of Terminations Z0 a ZS Z0 Z 0, , l ZS ZL input acceptance Christian Schuster – 30 Effect of Terminations H exp( l ) Z 0, , l ZS ZL input acceptance TL transfer function Christian Schuster – 31 Effect of Terminations ZL Z0 rL ZL Z0 Z 0, , l ZS t L 1 r L ZL input acceptance TL transfer function load transmission load reflection Christian Schuster – 32 Effect of Terminations ZS Z0 rS ZS Z0 tS 1 rS Z 0, , l ZS ZL input acceptance TL transfer function source transmission load transmission source reflection load reflection Christian Schuster – 33 Effect of Terminations Z 0, , l ZS ZL u2 a H tL ?? 2 u0 1 H r L rS Christian Schuster – 34 Effect of Terminations Z 0, , l ZL Z0 ZS u2 aH u0 ZL ZS Z L Z0 Christian Schuster – 35 u2 1 H u0 2 Effect of Terminations Matched interconnect: Voltage lossless transmisson line lossy transmisson line Time TD Mismatched Interconnect: Voltage low source impedance high source impedance Time 2 TD Christian Schuster – 36 Effect of Terminations 1 Z S 10 Ω, Z 0 50 Ω, Z L 1kΩ zero losses 2 Z S 50 Ω, Z 0 50 Ω, Z L 100 Ω zero losses 1 3 Z S 50 Ω, Z 0 50 Ω, Z L 50 Ω zero losses 2 4 Z S 100 Ω, Z 0 50 Ω, Z L 100 Ω 3 6 5 4 zero losses 5 Z S 10 Ω, Z 0 50 Ω, Z L 1kΩ non-zero losses 6 Z S 50 Ω, Z 0 50 Ω, Z L 50 Ω non-zero losses (all lines have a delay of 0.1 ns) Christian Schuster – 37 Matching Terminations (2 TD TR ) Check your interconnect length Check your interconnect impedance! Match receiver input impedance! Match transmitter output impedance! ! Christian Schuster – 38 ! Real World Interconnect (Link) Data Equalizer + Slicer . . . Data . . . Equalizer Serializer Tx CDR Deserializer Clock & Data Recovery Clock Rx The technology is typically CMOS with the links being voltage mode, unidirectional, serial, point-to-point, and sourcesynchronous. For improved bandwidth equalization is typically used in the Tx, Rx, or both. Christian Schuster – 39 Packaging of Digital Systems Interconnect (Link) Connector Christian Schuster – 40 Effect of Lumped Discontinuities Signal Out Signal In Source Voltage u1 50 Tx-Output 2.5 nH Bond Wire Christian Schuster – 41 50 Rx-Input u2 Received Voltage Effect of Lumped Discontinuities Signal In Signal Out Source Voltage u1 50 Tx-Output 50 1 pF Via Christian Schuster – 42 Rx-Input u2 Received Voltage Effect of Lumped Discontinuities Attenuation of high frequency signal components „Slowing down" of the edges of a digital signal Step Response u2(t) / u1(t) Magnitude of u2 / u1 Frequency Response t 1/w0 = 25 ps f0 ≈ 6.37 GHz Frequency [GHz] Time [ps] Christian Schuster – 43 Effect of Distributed Discontinuities Z0 Z, ,l Z0 1 inch, 45 Ohm mismatched transmission line at c0 /2 c f 2.952GHz 4l Frequency Response (Scattering Parameters) Christian Schuster – 44 Overall Effect of Discontinuities Port1 Port2 2nH 2nH 2nH P=1cm P=15cm P=5cm P=1cm 0 0 Christian Schuster – 45 0 300fF Z=48 300fF Z=52 300fF Z=48 300fF Z=49 0 Managing Discontinuities Avoid them! Check their impact! Minimize them (± 10 Ohm around 50 Ohm)! Compensate them (difficult)! Concentrate on the “bottleneck! ! Christian Schuster – 46 Packaging of Digital Systems Interconnect (Link) Connector Christian Schuster – 47 Effect of Coupling Consider two transmission lines in close proximity: (1) Input (3) Near End Aggressor Line (Active Line) Victim Line (Quiet Line) Christian Schuster – 48 (2) Output (4) Far End Effect of Coupling Consider two transmission lines in close proximity: (1) Input (2) Output IC UL (3) Near End (4) Far End NEXT = Near End Crosstalk FEXT = Far End Crosstalk (sum of ind. and cap. crosstalk) (difference of ind. and cap. crosstalk) Christian Schuster – 49 Effect of Coupling For weak coupling (kL,C ≤ 0.25) it is found approximatively: (1) Input (2) Output Effect of crosstalk is usually small. INPUT U max TR TD (3) Near End (4) Far End Polarity is equal to input polarity. TR 2 TD TR Christian Schuster – 50 Polarity also depends on coupling coefficients. TD TD TR Effect of Coupling For weak coupling (kL,C ≤ 0.25) it is found approximatively: NEXT U max U FEXT max kC k L TD INPUT U max 2 T R INPUT kC k L U max 4 (TD 0.5 TR ) (TD 0.5 TR ) kC kL TD INPUT U max 2 TR It should be noted that these formulas do not take into account losses on the lines or reflections from load mismatches. Christian Schuster – 51 Example for Coupling Coefficients For two thin wires above infinite ground one can find: a diameter = d h 0 C12 ln(1 (2h / a) 2 ) kC C12 C11 2 ln( 4h / d ) Christian Schuster – 52 Reducing Coupling Increase line separation! Decrease distance to ground! Balance capacitive and inductive coupling! Increase rise time! Reduce coupling length! Use differential signaling! Christian Schuster – 53 ! Differential Signaling In a SINGLE-ENDED link there is a common (global) reference against which the signal is measured ("ground"). In a DIFFERENTIAL link the reference is the negative of the signal itself (which has to be transmitted as well). Christian Schuster – 54 (3) Power Integrity Christian Schuster – 55 Electrical Integrity of Digital Systems Christian Schuster – 56 Effect of Common Power Delivery IC #1 ZPDN IC #2 U0 PDN = Power Delivery Network Christian Schuster – 57 Effect of Common Power Delivery R U0 L uIC iGate1, iGate2, … Du uIC = U0 - Du d Du (t ) R iGate1 (t ) iGate1 (t ) ... L iGate1 (t ) iGate1 (t ) ... dt "DC-drop or IR-drop" Christian Schuster – 58 "DI-drop or DI-noise" Maintaining Power Integrity 1. Decrease PDN impedance 2. Add decoupling 3. Add even more decoupling 4. Use several power supplies 5. Use on-chip VRMs Christian Schuster – 59 PDN Elements High Power DC Supply Discrete Decoupling Capacitors (various sizes) IC incl. Power/Ground Grid & Integrated Decaps Voltage Regulator Module Printed Circuit Board incl. Power/Ground Planes Christian Schuster – 60 Package incl. Power/Ground Planes PDN Impedance In frequency domain the standard PDN model looks like this: ZPDN ( f ) u0 ~ Du( f ) Dumax Du( f ) ZIC ( f ) f " operating frequency range" Z PDN ( f ) Z Target Christian Schuster – 61 PDN Impedance A typical maximum ripple for ditigal systems is: Dumax maximum ripple 5% to 10% u0 With a 10% value the following numbers can be obtained for applications … of the early 1990'ies: … of 2000 and on: u0 1.2 V u0 5.0 V iavg 120 A iavg 1 A u0 / iavg 0.01 Ω u0 / iavg 5.0 Ω Pavg 144 W Pavg 5 W Z Target 0.001 Ω = 1 m ! Z Target 0.5 Ω Christian Schuster – 62 PDN Impedance Is 1 m hard to achieve? How about 10 m? Let's see … Example: The PDN consists of a simple copper wire of 2 mm radius in theform of a flat rectangle with side lengths of 5 cm and 1 cm, respectively. with Z PDN R 2 (wL) 2 R 0.7 m L 40 nH It turns out that 10 m cannot be maintained beyond 40 kHz! Christian Schuster – 63 Decreasing PDN Impedance Use adequate copper cross sections! Avoid big current loops! Use power/ground planes! Provide enough power/ground pins! Decouple! ! Christian Schuster – 64 Decoupling Based on the simple example from before: R U0 L ~ ZIC ( f ) Z PDN R jwL jwL (R = 0.7 m, L = 40 nH) (for large w ) Christian Schuster – 65 Decoupling … we ask what a so called "decoupling" or "bypass" capacitor does: R U0 Z PDN L ~ C R jwL 1 jwRC w 2 LC 1 (for large w ) jwC ZIC ( f ) R = 0.7 m L = 40 nH C = 1 mF Christian Schuster – 66 Decoupling Heuristic explanation: R U0 L ~ C ZIC ( f ) Frequency domain: Beyond the resonance frequency the capacitor decouples the part of the PDN that lies "left" of him, i.e. the IC sees only the impedance of the capacitor. Time domain: The capacitor stores charges close to the IC that can become currents needed for fast switching. It is like a "small battery". Christian Schuster – 67 Decoupling While being beneficial at higher frequencies decoupling increases the PDN impedance in the vicinity of the resonance frequency: 1 L w0 R2 L C Z PDN (w0 ) R = 0.7 m L = 40 nH C = 1 mF Z PDN (w0 ) 57m ( L / C R 2 )* 1 L R R C Hence, increasing the "damping" (by increasing R and/or reducing L/C) can be helpful: (with Q 1 / R L / C the condition becomes Q 1)* Christian Schuster – 68 R = 10 m L = 40 nH C = 1 mF Real Word Decoupling Capacitors Unfortunately, there is no ideal capacitor available in the real world! Ideal world: … and real world: R C L C R is also is called the EQUIVALENT SERIES RESISTANCE (ESR) and L the EQUIVALENT SERIES INDUCTANCE (ESL). As a consequence any real world capacitor behaves approximately like an inductor beyond its resonance frequency: w0 1 / LC Christian Schuster – 69 More Decoupling ~ board-level package-level Amount of charge, size of decoupling capacitance chip-level Speed of charge delivery, effective frequency Christian Schuster – 70 Power/Ground Planes Power/ground planes serve multiple purposes at the same time: easy access to power and ground domains for mounted components a "natural" decoupling capacitor for PDN improvement return current paths, i.e. they serve as reference conductors shielding between different signal layers, i.e. they reduce crosstalk containment for internal EM fields, i.e. reduce EM emission … HOWEVER … Christian Schuster – 71 Power/Ground Planes … they do show a resonant behavior: Dielectric Filling (r = 4) Cpp 0 r 10 mil Port Power Ground A 11 nF d 11 inch Christian Schuster – 72 11 inch (1 inch = 2.54 cm, 1 mil = 0.001 inch) Power/Ground Planes The resonance frequencies are given by: f mn c0 r r 2 m n 2a 2b 2 (m, n 0,1, 2, ...) Examples of standing wave patterns on a rectangular power/ground plane pair. Christian Schuster – 73 Adding Decoupling Determine your target impedance! Determine your operating frequency range! Provide decoupling at all levels/frequencies! Use parallel decoupling to reduce ESR/ESL! Be wary of resonances! ! Christian Schuster – 74 (4) Vias and Return Currents Christian Schuster – 75 The Problem With Vias Signal Current SignalVia Load Return Current Ground Via Load Christian Schuster – 76 A “Physcis-Based” Model for Vias Current Plane viu Cp vi vil Cp Plane Via Via Cross Section i'iu Zp viu 1 Z pp vil i i 0 1 il iu Zpp iil Christian Schuster – 77 vil 1 i 1 / Z pl il Zp v'il 0 viu 1 iiu iiu Zpp: (Parallel Plate Impedance) v'iu 1 i ' 1 / Z pu iu i'il 0 v'il 1 i'il Where Do We Zpp Get From? Port i (xi,yi) Port j (xj,yj) (a,b,d) Current Open Plane Edges (a,b,0) Voltage z Filling with and (0,0,0) jwd Z ij (w ) ab m0 n 0 (a,0,0) y x 2 2 cos(k xm xi ) cos(k yn yi ) cos(k xm x j ) cos(k yn y j ) CmCn 2 2 2 k k k xm yn m n k yn a b Cm , Cn 1 for m, n 0 and k xm Christian Schuster – 78 k w 2 otherwise Including Striplines Trace between planes: 2 Modes: Stripline + Parallel Plate Stripline Mode Parallel Plate Mode (pp) Modal decomposition: find suitable transformation matrices to diagonalize MTL equations Christian Schuster – 79 Including Striplines h2 h1 k h1 h1 h2 I ps1 V ps1 2 V I ps2 k 2 Y stripline Y pp (k k )Y stripline Y pp ps2 I 2 2 Vgs1 gs1 ( k k ) Y Y ( k 2 k 1 ) Y Y stripline pp stripline pp I V gs2 gs2 R. Rimolo-Donadio, H. D. Brüns, C. Schuster, “Including Stripline Connections into Network Parameter Based Via Models for Fast Simulation of Interconnects,” International Zurich Symposium on Electromagnetic Compatibility, Switzerland, Jan. 12-15, 2009 Christian Schuster – 80 Stacking the Deck Decap Linterc. Decoupling capacitor model Port 1 Zpp Port n Cavity representation Ztl S-Parameter Matrix Zpp Ztl Cavity representation Cavities joined by segmentation techniques R. Rimolo-Donadio et al., “Physics-based via and trace models for efficient link simulation on multilayer structures up to 40 GHz", IEEE Trans. Microw. Theory and Techn., vol. 57, no. 8, p.p. 2072-2083, August 2009. Christian Schuster – 81 Comparison with Full-Wave Results Full-wave model 6 Vias, 4 traces case Magnitude [dB] of SS12 Magnitude of 14 [dB] Centered striplines at two levels, and thru vias in a 6 cavity stackup Full-wave model Frequency Frequency [GHz] [GHz] Christian Schuster – 82 Model Model FEM simulation simulation FEM FIT simulation simulation FIT Comparison with Measurements • 119 vias (76 signal, 43 ground) Assumption of infinite plates • 14 differential striplines (2D) • 6 cavities • Terminations Comp. time: < 3 min Christian Schuster – 83 Comparison with Measurements |S13| [dB] - FEXT |S12| [dB] - IL Link 10 S3 Stripline Link 17 S5 Stripline Link 10 S3 Stripline Link 17 S5 Stripline Measurement Link 10 Models capture the salient features of the hardware response despite the drastic model simplification Christian Schuster – 84 Measurement Link 17 Model Link 10 Model Link 17 Investigation of Via Return Currents Effect of number of ground vias: GND via 1 GND via 2 GND vias 4 GND vias 6 GND vias Christian Schuster – 85 Investigation of Via Return Currents Magnitude of S12 [dB] Effect of number of ground vias: 1 GND vias 2 GND vias 4 GND vias 6 GND vias Frequency [GHz] Christian Schuster – 86 (5) Measurement Techniques Christian Schuster – 87 Multiport Vector Network Analysis Agilent Vector Network Analyzer 8364C with 12-port extension at Institute of Electromagnetic Theory (TUHH) 12 ports Bandwidth 10 MHz – 50 GHz Electronic calibration module Advanced calibration software Christian Schuster – 88 Common Surface Launches Surface Connectors Access Vias MICRO-PROBE 5 mm 5 mm STRUCTURE UNDER TEST STRUCTURE UNDER TEST ... but vias are usually a high frequency bottleneck ! Christian Schuster – 89 The Recessed Probe Launch (RPL) MICROPROBE MICROPROBE STRUCTURE UNDER TEST Ground Vias Signal trace No access vias → less distortion → probes closer to the structure under test Christian Schuster – 90 Ground pads with “U” strap RPL Error Box Extraction Error boxes of RPLs from TRL calibration (thru = 90 mil long, line = 220 mil long) Christian Schuster – 91 Problems with Via Arrays 13 mm 45° Via array Via array … many vias at tight pitch! 92 Christian Schuster – 92 The Interposer Concept SMA or SMP Connectors ~ 1 cm ~ 1 cm ~ 1 mm Signal pitch conversion from ~1 cm to ~1 mm & easy multiport access 93 Christian Schuster – 93 Typical Measurement Set-up Multiport VNA Interposer 1 Interposer 2 High speed serial links 94 Christian Schuster – 94 Interposer Prototype SMP adapters SMP connectors Interposer LGA Test board Hardware courtesy of IBM YKT (Y. Kwark) Clamping and pressure plates 95 Christian Schuster – 95 Application to Link Measurement Stripline connecting vias from both via arrays Hardware courtesy of IBM YKT (Y. Kwark) 1st interposer connected to the via array 2nd interposer connected to the via array 96 Christian Schuster – 96 (6) Wrapping Up Christian Schuster – 97 Electrical Integrity of Digital Systems Christian Schuster – 98 Electrical Integrity of Digital Systems The basic goals of EMC, SI, and PI for an electrical system are complementary to each other. SIGNAL INTEGRITY: insure acceptable quality of signals within SNR System Target Frequency POWER INTEGRITY: insure acceptable quality of power delivery within EMC: insure acceptable level of interference with the outside PDN Impedance Target System Frequency EMI Target System Frequency Christian Schuster – 99 Contact Information Prof. Dr. sc. techn. Christian Schuster Institut für Theoretische Elektrotechnik Technische Universität Hamburg-Harburg Harburger Schloss Str. 20 21079 Hamburg, Germany Tel: +49 40 42878 3116 WWW: http://www.tet.tuhh.de/ E-Mail: schuster@tuhh.de Christian Schuster – 100
