Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Contents lists available at ScienceDirect
Memories - Materials, Devices, Circuits and Systems
journal homepage: www.elsevier.com/locate/memori
An efficient read approach for memristive crossbar array
Pravanjan Samanta a ,∗, Dev Narayan Yadav b , Partha Pratim Das b , Indranil Sengupta b
a
b
Rajendra Mishra School of Engineering Entrepreneurship, Indian Institute of Technology Kharagpur, India
Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, India
ARTICLE
Keywords:
Logic design
Memristor
Read operation
ReRAM
Sneak-path
INFO
ABSTRACT
Resistive random access memories (ReRAM) have drawn attention of researchers due to their unique properties
with applications in in-memory computing, which allows storage and computation in the same unit. This
mitigates one of the major limitations in current computing architectures, where for each computation we
require to move data from memory to processor or vice versa, which incurs immense amount of energy
overheads. Among the various technologies for implementing ReRAM, memristor is considered to be one of
the most desirable candidates due to its small size, low power consumption, and high data retention. Such
ReRAM systems are often fabricated in the form of crossbar for compact layout. However, they suffer from
various challenges, one of the major ones being the sneak-path problem during reading of cell values. The
read operation is mostly disturbed by sneak-path currents that can result in incorrect reading of the cell.
This paper presents a new approach for reading the cell values in memristive crossbars, which is capable
of avoiding erroneous read operations caused by sneak-paths. It also supports parallel operations whereby
multiple memristor states can be read in a single cycle. A straightforward approach for reading all the cells
in an 𝑛 × 𝑛 crossbar, where the read operation is performed sequentially, requires 𝑂(𝑛2 ) cycles, whereas the
proposed approach requires 𝑂(𝑛) cycles.
1. Introduction
The CPU-memory bottleneck in current memory architectures limits
the maximum processing capabilities in computing systems, which has
led researchers to look for alternate memory technologies to address
this problem. Resistive random access memory (ReRAM) systems provide
mechanism to reduce this bottleneck. Although a number of technologies exist to realize ReRAM systems, memristor is considered to be
one of the most suitable candidates due to its non-volatile nature, inmemory computing capability, low power consumption, dense layout,
and higher write endurance [1].
Subsequent to the introduction of memristor as the fourth fundamental passive circuit element by Leon Chua in 1971 [2], the first
TiO2 -based memristor device was fabricated by HP Lab in 2008 [3].
Memristors are typically fabricated in a compact crossbar structure
where the devices are placed at the junctions between two sets of
perpendicular nanoscale wires. A memristor cell can act as storage as
well as computing device, which allows a new computing paradigm
known as in-memory computing [4,5].
In its simplest form, a memristor crossbar can be classified as 0𝑇 1𝑅,
where each storage cell comprises of a single memristor. This provides
the highest storage density but suffers from the sneak-path problem.
The presence of sneak-paths can cause errors while reading a high resistance memristor cell that is parallel to other low resistance memristor
cells in the crossbar [6]. To avoid this problem, the 1𝑇 1𝑅 crossbar has
been proposed, where each storage cell consists of an access transistor
in series with a memristor. By switching off the transistors in the
remaining rows and columns, a particular cell can be read correctly
avoiding the sneak-path problem [7].
As mentioned, the conventional approach for reading the cells in
a crossbar suffers from sneak-path issue and also does not support
parallel read operations, thereby causing latency and energy overheads.
This paper proposes a new read approach for reading the cells of a
memristor crossbar. The approach is based on the principle of binary
search, where the crossbar is progressively divided into smaller crossbar
segments, and read voltages are applied to the corresponding rows
and columns in an iterative fashion. To detect the memristor states,
the currents generated in column/row are analyzed. The approach also
supports parallel operation, i.e. all the rows and columns of the selected
crossbar segment can be analyzed in a single cycle thereby reducing the
overall latency.
The rest of the paper is organized as follows. Section 2 describes
the background and related works. Section 3 discusses the proposed
read approach. Section 4 presents the experimental evaluation of the
∗ Corresponding author.
E-mail addresses: pravanjan.samanta@iitkgp.ac.in (P. Samanta), dev.narayan@iitkgp.ac.in (D.N. Yadav), ppd@cse.iitkgp.ac.in (P.P. Das), isg@iitkgp.ac.in
(I. Sengupta).
https://doi.org/10.1016/j.memori.2023.100047
Received 16 December 2022; Received in revised form 10 April 2023; Accepted 10 April 2023
2773-0646/© 2023 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Fig. 1. (a) Physical structure of memristor; (b) Equivalent circuit.
Fig. 3. Schematic diagram of a memristor crossbar.
Fig. 2. Typical V-I hysteresis loop of the memristor.
2.2. Memristor crossbar and read–write operation
2.2.1. Memristor crossbar
A crossbar is fabricated using a set of perpendicular nanoscale wires
in two layers [10], with a memristor placed at each junction as shown
in Fig. 3. Due to the non-volatile nature of memristor, the crossbar can
be used as a storage unit, where information is stored in the cells as
resistance values. For this purpose, this architecture is often referred to
as resistive random-access memory (ReRAM).
In addition to being used as resistive memory, the crossbar can
also be used to carry out logic operations. This requires us to apply
suitable voltages to the rows and the columns of the crossbar in proper
sequence. Essentially, this introduces a new architecture where storage
and computation can be carried out in the same hardware. This is often
referred as in-memory (in-situ) computing architecture [4,5].
approach, the results of which are presented in Section 5 concludes the
paper with a brief discussion of future research.
2. Background
2.1. Memristor
Memristor is a passive circuit element whose resistance value depends on the amount of charge that has previously passed through it.
The existence of memristor was predicted by Leon Chua in 1971 [2] as
a missing link between electric charge (𝑞) and flux (𝜙). Subsequently,
Strukov et al. demonstrated a memristor device using a Pt-TiO2 -Pt
structure in 2008 [3] as shown in Fig. 1.
The device consists of two regions, doped and undoped. The undoped
region consists of pure TiO2 , whereas the doped region contains an
oxide material with extra oxygen vacancies (e.g. Ti4 O7 ). The resistance
of the doped region is much lower as compared to that of the undoped
region. The overall resistance of the device can be expressed as:
(
)
𝑥
𝑥
(1)
𝑀(𝑥) = 𝑅𝑜𝑛 . + 𝑅𝑜𝑓 𝑓 . 1 −
𝐷
𝐷
where 𝑥 is the length of the doped region, 𝐷 is the total length of the
device, and 𝑅𝑜𝑛 and 𝑅𝑜𝑓 𝑓 represents the two stable resistance state of
device when 𝑥 = 𝐷 and 𝑥 = 0 respectively.
The boundary between the two regions (i.e. doped and undoped)
can be moved by applying a suitable voltage across the device, thereby
changing the overall resistance. The resistive state remains unchanged
even if the power supply is withdrawn, which leads to non-volatile
behavior of the device. The 𝑉 − 𝐼 characteristics of the device depicts a
pinched hysteresis loop as shown in Fig. 2. Depending on the polarity of
the applied voltage, the device switches between two distinct resistive
states, high resistance state (HRS) and low resistance state (LRS), which
are typically treated as logic 0 and logic 1 respectively for logic design
applications [8,9].
2.2.2. Read and write operations in crossbar
In general, to change the state of a cell (i.e. a write operation), a
write voltage 𝑉𝑤𝑟𝑖𝑡𝑒 of proper polarity, magnitude and pulse width is
applied across it. For a write-1 (set memristor state to 𝑅𝑜𝑛 ) operation,
a positive voltage is applied to the terminal attached to the doped
side of the selected memristor, whereas for a write-0 (set memristor
state to 𝑅𝑜𝑓 𝑓 ) operation a negative voltage is used. The other terminal
of the device is connected to ground. To prevent unnecessary state
changes in other memristors a limiting voltage (𝑉𝑤𝑟𝑖𝑡𝑒 ∕2) is applied to
all unselected memristors of the crossbar [11,12].
For reading a cell, usually a voltage 𝑉𝑟𝑒𝑎𝑑 of smaller magnitude is
applied such that it does not modify the memristor states. For reading
multiple cells, the read operation is carried out one cell at a time,
where at every step the read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to the selected
row and the current is measured along the selected column to identify
the state as shown in Fig. 4. If the memristor is in 𝑅𝑜𝑛 (𝑅𝑜𝑓 𝑓 ) state
then the measured current will be high (low). However, the reading
process suffers from the sneak-path problem, which typically occurs in
the 0T1R crossbars [13]. In addition to this, if the read voltage is not
2
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Fig. 4. Read operation in memristor crossbar.
Fig. 5. Sneak path in memristor crossbar circuit. (For interpretation of the references
to color in this figure legend, the reader is referred to the web version of this article.)
selected properly, then the read operation itself can disturb the stored
data.
The read operation of memristor crossbar is mostly affected by
sneak-path current. The author in [14] introduced a read approach that
requires two consecutive read operations for a single memristive cell of
the crossbar. To avoid the effect of sneak-path current, the background
sneak currents is measured in the first read operation, which is factored
out of the current measurement in the second read operation.
In [12] the authors discuss the major difficulties in constructing
a crossbar and present solutions to improve the read accuracy and
latency. It has been observed that the background sneak current measured for any cell can be reused in the subsequent reads for other cells
of the same column, which introduces open-column semantics for the
crossbar. This implies that instead of two consecutive read operations,
the read can be performed in a single cycle if the background current
is available for reuse, for which the authors use a sample-and-hold
circuit. The proposed approach improves the power consumption and
latency by 26% and 20% respectively as compared to the approaches
that require two read cycles.
The authors in [15]propose a row grounding approach to read the
memristor states. The work also discuss several techniques and constraints for read operation in the crossbar. In the method, the number of
rows in the crossbar is increased while applying row grounding method
that basically reduces read energy and latency.
A read technique in selector-less memristive crossbar is presented
in [16]. The sneak-path problem is overcome with the row readout
technique. A single cycle is required to read an entire row of the
crossbar. The paper also derives approximate expression for the power
consumption in the crossbar and shows some advantages over existing
read approaches.
A read–write technique is proposed for a memristor crossbar in [17],
which presents some advantages in read latency, delay latency and low
area layout. Moreover, it has been shown that the design is able to
maintain the store data even for large number of successive reading
cycles. Many others read/write circuits for memristor-based ReRAM
systems are also available in the literature [18–21].
current path. The parallel path is created due to the memristors shown
in green color that are in the 𝑅𝑜𝑛 state. This causes the current to flow
through memristors 𝑀𝑅1 𝐶2 → 𝑀𝑅2 𝐶2 → 𝑀𝑅2 𝐶1 and cause the current
sensor to infer incorrectly.
3. The proposed read approach
To read the content of a cell in the crossbar using conventional
approach, a read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to a row of the crossbar and
the current is sensed along the corresponding column. If the current is
high then it indicates that memristor is in its 𝑅𝑜𝑛 state, and if it is low
then it indicates that the memristor is in its 𝑅𝑜𝑓 𝑓 state. This process
does not allow parallel operation, and hence requires 𝑂(𝑛𝑚) cycles to
read all the cells in an 𝑛 × 𝑚 crossbar.
However, a parallel read approach can reduce the number of read
cycles. In this paper, we have proposed an approach that allows parallel
read operations in the crossbar, whereby multiple cells can be read in a
single cycle. The proposed approach progressively divides the crossbar
into smaller crossbar segments and analyzes the currents in every step.
The overall flow of the proposed approach is depicted in Fig. 6. In
the framework, reading steps are shown for a memristor in the 𝑅𝑜𝑓 𝑓
state and the size of the crossbar is assumed as 𝑛 × 𝑚. For the sake
of simplicity, we assume the crossbar to be symmetrical (i.e., 𝑛 = 𝑚).
First the crossbar is divided into two parts (upper-half and lower-half ),
and the read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to all the rows 𝑅1 , 𝑅2 , … , 𝑅𝑛∕2
(𝑅𝑛∕2+1 , 𝑅𝑛∕2+2 , … , 𝑅𝑛 ) of the upper-half (lower-half) crossbar keeping
the lower-half (upper-half) memristors inactive. This process requires
two cycles. However, it can be done in a single cycle as well, for which
the read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to all the rows (𝑅1 , 𝑅2 , … , 𝑅𝑛 ) in a
single cycle and the column currents are analyzed using two threshold
detector circuits (TDC) [26].
By analyzing the currents generated by TDCs, we can easily identify
in which portion of the crossbar a higher number of memristors are in
𝑅𝑜𝑛 (or 𝑅𝑜𝑓 𝑓 ) states. The portion from where we get higher (lower)
current will indicate that the portion consists of more number of 𝑅𝑜𝑛
(𝑅𝑜𝑓 𝑓 ) memristors as compared to the other portion. In the next step,
the crossbar is again divided into two parts, right-half and left-half, and
the currents generated in the rows (columns) are analyzed. This process
is repeated until the size of the partitioned crossbar reaches 1 × 1 or
the current generated by the smaller crossbar is negligible (≈ 0).
The overall approach is depicted in Algorithm 1. The steps are
explained as follows.
2.2.3. Sneak-path issue
The bidirectional nature of memristors allows sneak-path currents
to flow in the crossbar. The presence of sneak-paths can cause an error
while reading the state of a memristor in HRS that is parallel to other
memristors of the crossbar in LRS state [6,13,22–25].
Fig. 5 shows how sneak-path can affect the reading of a memristor
in the crossbar. Assume that the desired memristor for which the read
operation needs to be performed is 𝑀𝑅1 𝐶1 (shown in yellow). To read
the content, we apply voltage 𝑉𝑟𝑒𝑎𝑑 to the row 𝑅1 and expect the
resulting current to follow the green line that is sensed at 𝐶1 . However,
there is a sneak-path indicated by the red line parallel to the desired
(a) First the crossbar is divided into two segments, upper-half and
lower-half.
(b) A read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to all the rows (𝑅1 , 𝑅2 , … , 𝑅𝑛∕2 )
available in upper-half of the crossbar keeping the lower-half
memristors inactive.
3
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Fig. 6. Flowchart of proposed reading approach.
(e) By comparing the currents generated in these two steps, we can
identify which segment of the crossbar has higher number of
memristors in the 𝑅𝑜𝑛 (𝑅𝑜𝑓 𝑓 ) states. The segment from where
we get higher (lower) current will indicate that it consists of
more number of 𝑅𝑜𝑛 (𝑅𝑜𝑓 𝑓 ) memristors as compared to the other
segment.
(f) Previously we divided the crossbar horizontally, but now the
crossbar will be divided vertically into two parts, left-half and
right-half.
(g) The process will be repeated as done for upper-half and lowerhalf of the crossbar. Previously we divided the crossbar horizontally, and applied 𝑉𝑟𝑒𝑎𝑑 into rows of the crossbar. But now the
read voltage will be applied into columns and the current will
be sensed through rows.
(h) Again the generated current will be analyzed to decide which
segment of the crossbar has higher number of 𝑅𝑜𝑛 (𝑅𝑜𝑓 𝑓 ) memristors.
(i) The above steps will be repeated alternately (left-half & righthalf, and upper-half & lower-half) until the size of the residual crossbar segment reaches 1 × 1, or the currents generated
becomes negligible (≈ 0).
Algorithm 1 Proposed read algorithm
1:
2:
3:
4:
5:
6:
7:
8:
INPUT: 𝑛 × 𝑛 crossbar (NN-chip)
OUTPUT: State of memristors of NN-chip
Initialize: 𝑘 = log2 𝑛, 𝑖 = 1
for each 𝑖 in 𝑘 do
Row partition: Partition Crossbar horizontally
if Current[upper crossbar]= 0 then
upper[crossbar]← 0
else if current[lower crossbar]= 0 then
lower[crossbar]← 0
Column partition: Partition Crossbar vertically
else if Current[right crossbar]= 0 then
right[crossbar]← 0
else if Current[left crossbar]= 0 then
left[crossbar]← 0
9:
10:
11:
12:
13:
end if
14: end for
15: RETURN:
state of memristors
(c) A read voltage 𝑉𝑟𝑒𝑎𝑑 is applied to all the rows (𝑅𝑛∕2+1 , 𝑅𝑛∕2+2 , … ,
𝑅𝑛 ) available in lower-half of the crossbar keeping the upper-half
memristors inactive.
(d) An alternative approach is now followed. In this approach 𝑉𝑟𝑒𝑎𝑑
is applied to all the rows (𝑅1 , 𝑅2 , … , 𝑅𝑛 ) only one time rather
than two times as was done earlier. We use two TDCs for
measuring the total currents of upper-half and lower-half. Each
iteration requires two cycles. In the first cycle we partition the
rows of the crossbar, and in the second cycle we partition the
columns.
The function of the TDC circuit that is used to analyze the currents
generated by the crossbar is defined as follows:
𝑇 𝐷𝐶𝑜𝑢𝑡
⎧
∑𝑛 ∑𝑛 𝑉𝑟𝑒𝑎𝑑
⎪1, if
𝑖=1
𝑗=1 𝑀𝑖𝑗 ≥ 𝐼𝑇 ℎ
=⎨
⎪0, otherwise
⎩
(2)
Assuming the crossbar size to be 𝑛 × 𝑛, where 𝑀𝑖𝑗 is the resistance of
the memristor located at row 𝑖 and column 𝑗, 𝑉𝑟𝑒𝑎𝑑 is the read voltage,
and 𝐼𝑇 ℎ is a predefined threshold current. The output of TDC will be
4
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Fig. 7. Proposed read operation in the crossbar.
Table 1
VTEAM model [27] parameters used for simulation.
high if the weighted sum of the currents is greater than 𝐼𝑇 ℎ , otherwise
it will be low.
The schematic of the proposed read approach is shown in Fig. 7.
In the proposed approach the inputs to the TDC that are used to
analyze the upper and lower halves of the crossbar are as follows:
𝑇 𝐷𝐶𝑢𝑝 =
𝑛∕2 𝑛
∑ 1
∑
𝑀𝑖𝑗
𝑖=1 𝑗=1
𝑇 𝐷𝐶𝑙𝑜𝑤 =
𝑛
𝑛
∑
∑
1
𝑀𝑖𝑗
𝑖=𝑛∕2+1 𝑗=1
𝑇 𝐷𝐶𝑟𝑖𝑔ℎ𝑡 =
𝑖=1 𝑗=𝑛∕2+1
Parameter
Value
Parameter
Value
1 kΩ
−2
1𝑒8
4
8𝑒−13
𝑅𝑜𝑓 𝑓
D
𝑝𝑐𝑜𝑒𝑓 𝑓
𝑤𝑖𝑛𝑑𝑜𝑤𝑡𝑦𝑝𝑒
𝛼𝑜𝑛
300 kΩ
3𝑒− 9
2
2
3
𝑉𝑠𝑒𝑡
𝜇𝑣
j
𝑘𝑜𝑛
𝛼𝑜𝑓 𝑓
2 V
1𝑒−15
1
−8𝑒−13
3
The proposed framework has been implemented in Python and run
on an Intel i7 based desktop with 2.6 GHz clock and 8 GB RAM running
Ubuntu. We have used the VTEAM memristor model [27] to simulate
the crossbar, which has been carried out under the Cadence Spectre environment. For simulation, maximum and minimum resistance values
are set to 𝑅𝑜𝑓 𝑓 = 300 kΩ and 𝑅𝑜𝑛 = 1 kΩ respectively.
The voltage sources of 0.3 V and 2.0 V and −2.0 V are used for reading, preset (write-1) and reset (write-0) of the memristors respectively.
We have used the VTEAM memristor model [27] for analysis, where
the model parameters used for simulation are presented in Table 1.
In the conventional read approach, reading of a single cell requires
0.72 f J and 1.71 ns energy and delay respectively. And reading of
each cell requires one cycle. To see the effectiveness of the proposed
approach two different crossbars are used for analysis, viz. 2 × 2 (𝐶1 )
and 4 × 4 (𝐶2 ). The energy, delay and total current generated by the
two crossbars are reported in Tables 2 and 3 respectively.
The total current plays an important role in our proposed approach.
We observe that 1 μA and 4 μA currents respectively represent that
all memristors of 𝐶1 and 𝐶2 are in HRS. We can also identify that all
memristors of 𝐶1 is in LRS if the total current generated is 300 μA.
However, for all other combinations, the current generated cannot be
used to make any such decision. For such cases we have to carry on our
iterative procedure of partitioning the crossbar until the termination
condition is reached.
From Tables 2 and 3 we observe that it is possible to easily identify
that all the memristors of 𝐶1 and 𝐶2 are in HRS in a single cycle.
Whereas in the conventional approach, 4 and 16 read cycles will be
required for 𝐶1 and 𝐶2 respectively. Also, the energy consumption and
delay for 𝐶1 , 𝐶2 are (2.88 f J, 6.84 ns) and (11.52 f J, 27.36 ns) respectively.
The analysis has been carried out for a symmetrical crossbar (𝑛 × 𝑛);
however, the proposed approach requires less number of cycles for
𝑛∕2 𝑛∕2
∑
∑ 1
𝑀𝑖𝑗
𝑖=1 𝑗=1
𝑛∕2
𝑛
∑
∑
Value
𝑅𝑜𝑛
𝑉𝑟𝑒𝑠𝑒𝑡
𝑤𝑚𝑢𝑙𝑡𝑖𝑝𝑙𝑖𝑒𝑑
real model
𝑘𝑜𝑓 𝑓
4. Experimental evaluation
The TDC used for analyzing the upper and lower halves can be used
again to analyze the left-half and right-half of the crossbar. However,
the inputs to the TDC will be changed as:
𝑇 𝐷𝐶𝑙𝑒𝑓 𝑡 =
Parameter
1
𝑀𝑖𝑗
Fig. 8 shows how the crossbar is divided into smaller segments
for an example crossbar of size 32 × 32. In the first iteration, during
the first cycle the crossbar will be divided into two segments of size
16 × 32, upper-half and lower-half. During the second cycle there are
again two phases. In the first phase, the 16 × 32 upper-half is divided
into 16 × 16 right-half and left-half, where the 16 × 32 lower-half is
inactive. In the second phase, we will get another two crossbars of size
16 × 16, right-half and left-half from the 16 × 32 lower-half, where the
16 × 32 upper-half is inactive. So effectively after analysis the crossbar
is divided into four smaller crossbars of size 16 × 16 each. Similarly,
these will be divided into 8 × 8 crossbars, and so on. The process will
continue till the termination condition is reached.
To measure the total current values in the two crossbar segments
simultaneously, two TDC circuits are used, one for upper-half and the
other for lower-half. The same TDC circuits can be reused for right-half
and left-half also. This allows us to apply the read voltage to all the cells
in the crossbar in a single cycle. A total of 𝑛 TDCs will be required for a
𝑛×𝑛 crossbar. However, the number of TDCs required can be reduced if
the analysis is done only for one crossbar segment at a time; however,
this will increase the number of cycles required.
5
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Fig. 8. Illustration of crossbar partitioning.
Table 2
Current measurement for (2 × 2) crossbar.
Memristor state
Current (μA)
Energy (fJ)
Delay (ns)
All mem in HRS
All mem in LRS
𝑅11 , 𝑅12 = 0
𝑅21 , 𝑅22 = 0
𝑅11 , 𝑅13 = 0
𝑅21 , 𝑅22 = 0
1.00
300.00
150.50
150.50
1.93
1.93
0.745
224.82
113.23
110.61
1.435
1.435
1.243
1.249
1.254
1.225
1.232
1.240
the crossbar horizontally into upper and lower segments. The two
segments are then partitioned vertically in the second and third cycles
respectively.
In the worst case, the process of recursive partitioning will continue
till we reach a 1 × 1 crossbar. Thus the total number of cycles required
in the worst case will be (3 × 2⌈log2 𝑛⌉ − 1) ∼ 𝑂(𝑛). The last column
of Table 4 shows the efficiency, defined as the ratio of total cycles in
conventional method to the proposed method for read operation.
However, we know that the 1T-1R or 1S-1R structure is capable
of avoiding sneak path issues in memristor crossbars. But, the 1T-1R
and 1S-1R structures incur an eminent amount of energy and area
overhead. This is because the power consumption and area required by
a transistor used as a selector are high. Moreover, it has been observed
that memristors operate at very low power, so the leakage current of
transistors can also affect the reading process. We have shown that the
energy and delay for 𝐶1 and 𝐶2 are 3.46 f J, 8.89 ns and 16.12 f J, 38.3 ns
respectively, for the 1T-1R approach. The results show that the 1T-1R
structure is less efficient than the conventional 1R structure, as well as
our proposed approach in terms of speed and area overhead.
It may be noted that the sneak-path problem can occur during read
operations in a crossbar, the probability of which increases rapidly with
the number of memristors in LRS state in the crossbar. However, in
the proposed scheme if most of the memristors in the crossbar are in
HRS state, the probability of sneak-paths disrupting the read operations
will be very less. Moreover, the crossbar is logically split into four
smaller crossbars in every iteration. We first detect the memristors that
are in HRS in a step-by-step fashion, and then identify the memristors
Table 3
Current measurement for (4 × 4) crossbar.
Memristor state
Current
Energy
Delay (ns)
All mem in HRS
All mem in LRS
𝑅1𝑚 = 𝑅2𝑚 = 0, 𝑚 = 1 → 4
𝑅3𝑚 = 𝑅4𝑚 = 0, 𝑚 = 1 → 4
𝑅𝑚1 = 𝑅𝑚2 = 0, 𝑚 = 1 → 4
𝑅𝑚3 = 𝑅𝑚4 = 0, 𝑚 = 1 → 4
4.00
1.20
1.20
1.20
1.20
1.20
4.77
1.42
1.43
1.43
1.36
1.42
1.989
1.980
1.994
1.9
1.981
1.981
μA
mA
mA
mA
mA
mA
fJ
pJ
pJ
pJ
pJ
pJ
non-symmetrical crossbar 𝑛 × 𝑚 (where 𝑛 > 𝑚) as well. Table 4 shows
the total number of cycles required for reading all the memristors
for different sizes of the crossbar. In each iteration the crossbar is
divided into 4 smaller segments. Also for each iteration, we apply
several voltage signals for row partition as well as column partition.
Each iteration requires three cycles, where in the first cycle we divide
6
P. Samanta, D.N. Yadav, P.P. Das et al.
Memories - Materials, Devices, Circuits and Systems 4 (2023) 100047
Table 4
Read cycles for an 𝑛 × 𝑛 crossbar.
Crossbar
(𝑛 × 𝑛)
# Iteration
(𝑘 = ⌈log2 𝑛⌉)
Row partition
(𝑅 = 2𝑘 − 1)
Column partition
(𝐶 = 2(2𝑘 − 1))
Total Cycles
(𝑇 = 3(2𝑘 − 1))
# Threshold detectors
𝑛
Efficiency
2
(𝜂 = 3×(2𝑛𝑘 −1) )
(8 × 8)
(16 × 16)
(32 × 32)
(64 × 64)
(128 × 128)
(256 × 256)
(512 × 512)
(1024 × 1024)
3
4
5
6
7
8
9
10
7
15
31
63
127
255
511
1023
14
30
62
126
254
510
1022
2046
21
45
93
189
381
765
1533
3069
8
16
32
64
128
256
512
1024
3.05
5.67
11.01
21.67
43.00
85.67
171.00
341.67
that are in LRS. If the memristor has short defects, they need to be
identified first, and then the threshold value can be modified accordingly. For example, if a block has a defective cell that is stuck in a
high conductance state, it will always generate a high current, so to
eliminate the erroneous read operation, the current value generated
by that block needs to be calibrated by threshold logic. However cell
resistance variation can also effect the overall reading process.
[7] L. Sun, N. Zheng, T. Zhang, P. Mazumder, Fault modeling and parallel testing
for 1T1M memory array, IEEE Trans. Nanotechnol. 17 (3) (2018) 437–451,
http://dx.doi.org/10.1109/TNANO.2018.2806938.
[8] J. Borghetti, G.S. Snider, J.P. Kuekes, J.J. Yang, D.R. Stewart, R. Williams,
‘Memristive’switches enable ‘stateful’logic operations via material implication,
Nat. Publ. Group 464 (7290) (2010) 873–876.
[9] S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E.G. Friedman, A.
Kolodny, U.C. Weiser, (MAGIC) - memristor-aided logic, IEEE Trans. Circuits
Syst. II 61 (11) (2014) 895–899.
[10] K. Akarvardar, H.S.P. Wong, Ultralow voltage crossbar nonvolatile memory based
on energy-reversible NEM switches, IEEE Electron Device Lett. 30 (6) (2009)
626–628.
[11] I. Vourkas, D. Stathis, G.C. Sirakoulis, Improved read voltage margins with
alternative topologies for memristor-based crossbar memories, in: 2013 IFIP/IEEE
21st International Conference on Very Large Scale Integration, VLSI-SoC, IEEE,
2013, pp. 336–339.
[12] M. Shevgoor, N. Muralimanohar, R. Balasubramonian, Y. Jeon, Improving
memristor memory with sneak current sharing, in: 2015 33rd IEEE International
Conference on Computer Design, ICCD, IEEE, 2015, pp. 549–556.
[13] W. Fei, H. Yu, W. Zhang, K.S. Yeo, Design exploration of hybrid cmos and
memristor circuit by new modified nodal analysis, IEEE Trans. Very Large Scale
Integr. (VLSI) Syst. 20 (6) (2011) 1012–1025.
[14] C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, Y. Xie,
Overcoming the challenges of crossbar resistive memory architectures, in: 2015
IEEE 21st International Symposium on High Performance Computer Architecture,
HPCA, IEEE, 2015, pp. 476–488.
[15] A. Dozortsev, I. Goldshtein, S. Kvatinsky, Analysis of the row grounding technique in a memristor-based crossbar array, Int. J. Circuit Theory Appl. 46 (1)
(2018) 122–137.
[16] M.E. Fouda, A.M. Eltawil, F. Kurdahi, On resistive memories: One step row
readout technique and sensing circuitry, 2019, arXiv preprint arXiv:1903.01512.
[17] M. Elshamy, H. Mostafa, M.S. Said, New non-destructive Read/Write circuit for
Memristor-based memories, in: 2014 International Conference on Engineering
and Technology, ICET, IEEE, 2014, pp. 1–5.
[18] H. Kim, M.P. Sah, C. Yang, L.O. Chua, Memristor-based multilevel memory,
in: 2010 12th International Workshop on Cellular Nanoscale Networks and
their Applications, CNNA 2010, 2010, pp. 1–6, http://dx.doi.org/10.1109/CNNA.
2010.5430320.
[19] M.S. Qureshi, M. Pickett, F. Miao, J.P. Strachan, CMOS interface circuits for
reading and writing memristor crossbar array, in: 2011 IEEE International
Symposium of Circuits and Systems, ISCAS, 2011, pp. 2954–2957, http://dx.
doi.org/10.1109/ISCAS.2011.5938211.
[20] M. Elshamy, H. Mostafa, Y.H. Ghallab, M.S. Said, A novel nondestructive
read/write circuit for memristor-based memory arrays, IEEE Trans. Very Large
Scale Integr. (VLSI) Syst. 23 (11) (2014) 2648–2656.
[21] C. Yakopcic, T.M. Taha, R. Hasan, Hybrid crossbar architecture for a memristor
based memory, in: NAECON 2014-IEEE National Aerospace and Electronics
Conference, IEEE, 2014, pp. 237–242.
[22] M.B. Majumder, M. Uddin, G.S. Rose, J. Rajendran, Sneak path enabled authentication for memristive crossbar memories, in: 2016 IEEE Asian Hardware-Oriented
Security and Trust, AsianHOST, IEEE, 2016, pp. 1–6.
[23] R. Joshi, J.M. Acken, Sneak path characterization in memristor crossbar circuits,
Int. J. Electron. 108 (8) (2021) 1255–1272.
[24] Y. Cassuto, S. Kvatinsky, E. Yaakobi, Information-theoretic sneak-path mitigation in memristor crossbar arrays, IEEE Trans. Inform. Theory 62 (9) (2016)
4801–4813.
[25] R. Naous, M.A. Zidan, A. Sultan-Salem, K.N. Salama, Memristor based crossbar
memory array sneak path estimation, in: 2014 14th International Workshop
on Cellular Nanoscale Networks and their Applications, CNNA, IEEE, 2014, pp.
1–2.
[26] Y.K.Y. Danaboina, P. Samanta, K. Datta, I. Chakrabarti, I. Sengupta, Design and
implementation of threshold logic functions using memristors, in: 2019 32nd
International Conference on VLSI Design and 2019 18th International Conference
on Embedded Systems, VLSID, IEEE, 2019, pp. 518–519.
[27] S. Kvatinsky, M. Ramadan, E.G. Friedman, A. Kolodny, VTEAM: A general model
for voltage-controlled memristors, IEEE Trans. Circuits Syst. II 62 (8) (2015)
786–790.
5. Conclusion
The proposed search algorithm for partitioning the crossbar is influenced by the binary search algorithm where the crossbar is divided
into smaller segments. In the proposed approach, the currents in the
divided crossbar segments are analyzed, which can read state of all
the memristors available in rows/columns (in the divided crossbar
segment) in parallel. Thus reduces the overall read time. For a crossbar
if most of the memristors are in 𝑅𝑜𝑓 𝑓 state, then the proposed approach
can report the states of the memristors in few cycles. For an 𝑛 × 𝑛
crossbar, the conventional read approach requires O(𝑛2 ) read cycles.
Whereas the proposed approach can read state of all memristors in 𝑂(𝑛)
cycles.
In the proposed work, we have only discussed the read circuit for
2D crossbars. However, the work can be extended to read the data
from 3D crossbar arrays as well. In general, if we directly apply the
proposed circuit to each layer of the 3D crossbar, we can achieve higher
parallelism at the cost of more number of TDC units. However, if we
read the crossbar data layer by layer, the same TDC units can be reused
in each level. However, this needs more detailed investigation that can
be taken up as a future work.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to
influence the work reported in this paper.
Data availability
No data was used for the research described in the article.
References
[1] O. Kavehei, Memristive Devices and Circuits for Computing, Memory, and
Neuromorphic Applications (Ph.D. thesis), 2012.
[2] L.O. Chua, Memristor-the missing circuit element, IEEE Trans. Circuit Theory 18
(5) (1971) 507–519.
[3] D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor
found, Nature 453 (2008) 80–83.
[4] J.J. Yang, D.B. Strukov, D.R. Stewart, Memristive devices for computing, Nature
Nanotechnol. 8 (1) (2013) 13.
[5] R.B. Hur, S. Kvatinsky, Memory processing unit for in-memory processing, in:
Intl. Symp. on Nanoscale Architectures, NANOARCH, 2016, pp. 171–172.
[6] M.A. Zidan, H.A.H. Fahmy, M.M. Hussain, K.N. Salama, Memristor-based memory: The sneak paths problem and solutions, Microelectron. J. 44 (2) (2013)
176–183.
7