2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE) | 978-1-6654-4837-6/22/$31.00 ©2022 IEEE | DOI: 10.1109/PESGRE52268.2022.9715907
Droop controlled voltage source converter with
different classical controllers in voltage control loop
Vikash Gurugubelli, Student Member, IEEE
Department of Electrical Engineering
National Institute of Technology
Rourkela, India
vikas0225@gmail.com
Arnab Ghosh, Senior Member, IEEE
Department of Electrical Engineering
National Institute of Technology
Rourkela, India
aghosh.ee@gmail.com
Abstract— The contribution of renewable energy sources
(RESs) in the conventional power system is increasing day by
day due to its availability, advancement in control methods,
and eco-friendly nature. This work is mainly focused on the
control of voltage source converter (VSC) in islanding mode.
The main contribution of this work is to apply different
classical control methods in the voltage control loop of a droopcontrolled VSC. In general, a PI controller is used in the
voltage control loop of a VSC. In this work, PI, PID, Lead, Lag,
Lead-Lead, Lead-Lag, PI-Lead, PI-Lag compensators are
applied in the voltage control loop. The dynamic response of
the VSC system with the above-mentioned controllers is
analyzed by using time domain and frequency domain analysis.
The simulation results of the droop-controlled inverter
corroborate the proposed work.
Keywords— Voltage Source Converter, Droop control,
Renewable energy source, Lead Compensator, Lead-Lead
Compensator.
I. INTRODUCTION
The RESs like PV, Fuel cells generate DC power. So,
the inverter is the inevitable solution for converting the DC
power AC. In this paper, the detailed implementation of
VSC with different classical control methods in the voltage
control loop and droop control is the most outer loop in the
system. The droop controller generates the voltage and
frequency set points of the VSC according to the load
variations.
The modeling, design, and analysis of a droop-controlled
inverter is presented in many works of literature [1-3]. The
small-signal stability of the droop-controlled inverter system
is presented in [4]. The demerit in the droop control is the
high rate of change frequency (RoCF), the virtual
synchronous machine concept introduced in [5-12], to
mitigate the high RoCF problem. In [13], the authors
introduce a concept for parallel inverters control in islanding
microgrids. In literature, all are focusing on the droop,
virtual synchronous machine, and some other advanced
control strategies to improve the system performance. In this
work, we are focusing on the inner voltage control loop with
different classical control strategies.
This paper makes the following contributions: (a)
different classical control methods (PI, PID, Lead, Lag,
Lead-Lead, Lead-Lag, PI-Lead, PI-Lag) are introduced in
the voltage control loop of the droop controlled VSC; (b) the
dynamic performance of the system is analysed with all the
conventional control methods, and (c) conclusions are drawn
on all controllers based on the system's stability analysis and
simulation results.
There are five portions to this work. The first portion
contains the introduction; the second section has the system
description; and section three contains the inner voltage and
current loops of the VSC, the classical controller's transfer
functions, and the droop control. The fourth part contains
the results and discussions. Section 5 concludes with
remarks on all traditional control approaches.
Anup Kumar Panda, Senior Member, IEEE
Department of Electrical Engineering
National Institute of Technology
Rourkela, India
akpanda@nitrkl.ac.in
II. SYSTEM DESCRIPTION
As illustrated in Fig. 1, the system in this paper is a
simple VSC working in islanded mode. Vdc is the input dc
supply. The DC-link capacitor (C) regulates the voltage on
the dc bus. The filter resistance, inductance, and capacitor
are represented as Rf, Lf, and Cf, respectively. The IGBT
switch's on-resistance is rsw. The voltages of the inverter
before and after the filter in the abc frame are Va1, Vb1, Vc1,
Va2, Vb2, and Vc2, respectively. Vd2, Vq2, are voltages of the
inverter after the filter in the dq frame. Similarly, the
inverter currents flowing through the filter capacitor and
load in both the frames are shown in Fig. 1. The inverter is
regulated in this paper so that it can provide the required
voltage and frequency. In the following sections, we'll go
through the VSC control system's internal voltage and
current control loops.
III. CONTROL STRUCTURES
A. Inner voltage and current control loops of VSC
The VSC control system has voltage and current control
loops [14-15]. In grid-connected VSC voltage control loop
is not required. In this study, standalone VSC is considered.
So, both voltage and current control loops are required to get
the desired performance of the system. The main
mathematical equations are presented below.
From Fig. 1, apply KVL across the filter inductor
dI (t )
(1)
L f a1 + ( R f + rsw ) I a1 (t ) = Va1 (t ) − Va 2 (t )
dt
dI (t )
(2)
L f b1 + ( R f + rsw ) Ib1 (t ) = Vb1 (t ) − Vb 2 (t )
dt
dI (t )
(3)
L f c1 + ( R f + rsw ) I c1 (t ) = Vc1 (t ) − Vc 2 (t )
dt
Transform the equations (1-3), from abc–dq, then the apply
Laplace transform, one can get the following equations [14]
[ sL f + ( R f + rsw )]I d 1 ( s ) = Vd 1 ( s ) − Vd 2 ( s ) + ω L f I q1 ( s ) (4)
[ sL f + ( R f + rsw )]I q1 ( s ) = Vq1 ( s ) − Vq 2 ( s ) − ω L f I d 1 ( s )
(5)
The coupling between the state variables may be seen in
equations (4-5). The decoupling of the state variables is
included in [15]. Finally, the present control's closed-loop
transfer function (CLTF) is shown in (6).
 I ( s)   I q1 ( s )   V (s ) 
1
1
 d1  = 
=
=
 I d ( s )   I q ( s )   1 + V1 ( s) 
 Lf
 r
  r

1+ 
 KP
 c
Where

KI

s+ c
 K Pc  
K Pc
V1 ( s ) = 

 sL f  

 s +  R f + rsw

 Lf




,






s


=
1
1+τi s
(6)
and K Pc , K Ic are simple
proportional-integral (PI) compensators.
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2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
Ia3
+
−
C
Vdc
I b3
I c3
I dr
θ
θ
ω
θ
θ
Vd 2
Vq 2
I qr
Fig. 1. Schematic diagram of a 3-phase inverter unit in islanding mode.
From Fig. 1, apply KCL at the AC filter capacitor
dVa 2 (t )
= I a1 (t ) − I a 2 (t )
(7)
I a 3 (t ) = C f
dt
dVb 2 (t )
= Ib1 (t ) − Ib 2 (t )
(8)
I b 3 (t ) = C f
dt
dVc 2 (t )
= I c1 (t ) − I c 2 (t )
(9)
I c3 (t ) = C f
dt
Transform the above equations from abc–dq, the subsequent
equations are found
dVd 2 (t )
= I d 1 (t ) − I d 2 (t ) + ωC f Vq 2 (t )
(10)
Cf
dt
dVq 2 (t )
= I q1 (t ) − I q 2 (t ) + ω C f Vd 2 (t )
(11)
Cf
dt
Apply Laplace transform on (10-11), the subsequent
equations are found
(12)
sC f Vd 2 ( s ) = I d1 ( s ) − I d 2 ( s ) + ωC f Vq 2 ( s )
sC f Vq 2 ( s ) = I q1 ( s ) − I q 2 ( s ) + ωC f Vd 2 ( s )
(13)
The coupling between the state variables may be seen in
equations (12-13). The decoupling of the state variables is
included in [15]. Finally, the present control's closed-loop
transfer function (CLTF) is shown in (14).
 V ( s)   Vq 2 ( s)   V

K
2
 d2  = 
=
=
 Vd ( s)   Vq ( s)   1 + V2 ( s)  C τ s 2 + C s + K
f i
f
 r
  r

(14)
 1  1 
Where V2 = K 
 , and K is simple

 1 + sτ i   sC f 
proportional compensator.
The primary contribution of this research is to examine
the performance of the VSC system with several classical
control schemes (PI, PID, Lead, Lag, Lead-Lead, Lead-Lag,
PI-Lead, and PI-Lag) in place of simple proportional
control.
B. Classical control strategies
This section goes through all of the traditional
compensators. This section also includes the transfer
functions (TF) and bode diagrams for all of the
compensators.
1) PI compensator: The PI compensator's TF is shown
in (15)
k s + k I 0.4 s + 240
GPI ( s ) = P
=
(15)
s
s
The proportional and integral gains of the PI compensator
are kP and kI, respectively. Fig. 2(a) depicts the PI
compensator's bode plot.
2) PID compensator: The PID compensator's TF is
shown below.
k s + kI + kD s2 0.8781s + 601.4 + 5.05 ×10−5 s2
GPID (s) = P
=
(16)
s
s
Where kP, kI, and kD are the gains of the PID compensator.
Fig. 2(b) depicts the PID compensator's bode plot.
3) Lead compensator: The Lead compensator's TF is
shown in (17)
s + 5000
(s + α )
GLead ( s ) = k Lead
= 0.98 ×
(17)
s + 9091
(s + β )
Where α and β are the lead compensator's parameters,
and α should be smaller than β . Fig 2(c) depicts the Lead
compensator's bode plot.
4) Lag compensator: The Lag compensator's TF is
shown in (18)
s + 5882
(s + α )
GLag ( s ) = k Lag
= 1.3 ×
(18)
s + 4545
(s + β )
Where α and β are the lead compensator's parameters,
and α should be greater than β . Fig 2(d) depicts the Lead
compensator's bode plot.
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Magnitude (dB)
Phase (deg)
Magnitude (dB)
Phase (deg)
Phase (deg)
Magnitude (dB)
Phase (deg)
Magnitude (dB)
2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
Fig. 2. Bode plot of the compensators (a) PI; (b) PID; (c) Lead; (d) Lag
5) Lead-Lead
compensator:
The
compensator's TF is shown below.
( s + α1 ) ( s + α 2 )
GLead − Lead ( s ) = k Lead − Lead ×
×
( s + β1 ) ( s + β 2 )
(s + α )
 k s + kI 
GPI − Lead ( s ) =  P
 × k Lead × ( s + β )
s


(21)
(s + 1493)
 0.4 s + 240 
=
 × 0.97 × (s + 1852)
s


Where kP and kI are the proportional and integral gains of
the PI compensator and α , β are the parameters of the lead
compensator and α should be less than β . Fig 3(c) depicts
the PI-Lead compensator's bode plot.
8) PI-Lag compensator: The PI-Lag compensator's TF is
shown in (22)
(s + α )
 k s + kI 
GPI − Lag ( s ) =  P
× k Lag ×

s
(s + β )


(22)
(s + 4762)
 0.4 s + 240 
=
 ×1.71× (s + 2778)
s


Where kP and kI are the proportional and integral gains of
the PI compensator and α , β are the parameters of the lag
compensator and α should be greater than β . Fig 3(d)
depicts the PI-Lead compensator's bode plot.
Lead-Lead
(19)
s + 2222 s + 5556
×
s + 4167 s + 6667
Where α1 , α 2 , β1 , and β 2 are the parameters of this
compensator and α1 < β1 , α 2 < β 2 . Fig 3(a) depicts the
Lead-Lead compensator's bode plot.
6) Lead-Lag compensator: The Lead-Lag compensator's
TF is shown below.
( s + α1 ) ( s + α 2 )
GLead − Lag ( s ) = k Lead − Lag ×
×
( s + β1 ) ( s + β 2 )
(20)
s + 2273 s + 5882
= 0.8 ×
×
s + 3704 s + 4545
Where α1 , α 2 , β1 , and β 2 are the parameters of the lead-lag
compensator and α1 < β1 , α 2 > β 2 . Fig 3(b) depicts the
Lead-Lag compensator's bode plot.
7) PI-Lead compensator: The PI-Lead compensator's TF
is shown in (21)
Magnitude (dB)
Phase (deg)
Magnitude (dB)
Phase (deg)
Phase (deg)
Magnitude (dB)
Phase (deg)
Magnitude (dB)
= 0.67 ×
Fig. 3. Bode plot of the compensators (a) Lead-Lead; (b) Lead-Lag; (c) PI-Lead; (d) PI-Lag
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2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
C. Droop control
The droop control implementation is shown in Fig. 4. In
which, the VSC generates power to the load. The power
flow from the VSC to load is
V V
V2
S = P e jθ − P S e j (θ +δ )
(23)
Z
Z
From (23), the active and reactive power flow from the
VSC to load is shown in (24)
V
P = 2 P 2 [R(VP − VS cos δ ) + X VS sin δ ]
R +X
(24)
VP
Q= 2
[X(VP − VS cos δ ) − RVS sin δ ]
R + X2
In this work, the resistance of the line is less compared to
the reactance of the line. Therefore, it can be approximated
that sin δ ≈ δ and cos δ ≈ 1 , and (24) can be revised as
V
XP
P ≈ P VS sin δ  δ ≈
(25)
X
VPVS
Q≈
VP
XQ
(VP − VS cos δ )  (VP − VS ) ≈
X
VP
(26)
f = f * − m( Pm − P* )
(27)
V = V * − n(Qm − Q* )
The droop laws are shown in (27), where f, V denote the
new operating frequency and voltage, respectively; Pm, Qm
denote the measured active and reactive power at the new
operating point. The reference frequency and voltage are f*
and V*, respectively. The setpoints for real and reactive
power are P* and Q*, respectively.
The dynamic analysis of the system using the abovementioned classical controllers is described in this part. The
VSC closed-loop transfer function with a proportional
controller may be understood from (14). The transfer
functions of all classical control techniques are provided in
the previous sections. Figures 5(a) and 5(b) demonstrate the
bode plots and step response of the system with all
conventional control schemes. Table I shows the VSC's
performance indices in the time and frequency domain for
all traditional control approaches.
Gate driver
Vdc
P
W
M
L
Inverter
iabc
Vabc
C
θ
id
iabc
Vd
2
Vdc
ud
+
+
PI
−
uq
−
+
ωL
+
+
+
PI
id
+
id*
iq*
−
iq
ωL
2π
PI
−
−
+
ωC
+
+
+
PI
+
−
ωC
I Lq
Current control loop
−
+
m
−
Pm
P*
f*
+
+
Vq
f
+
I Ld
−
RL
ω*
s
Vd
abc
abc
abc
i
dq i Labc
dq i Vabc
dq
q
Lq
Vq
θ
abc
dq
1
iLd
iLabc
Voltage control loop
Vd
−
V
+
n
+
−
V*
Vq*
VVqq
Qm
Q*
Vabc
iLabc
Power
calculation
Pm
Qm
Droop control
Fig. 4. Droop control implementation.
IV. RESULTS AND DISCUSSIONS
The goal in islanded mode is to keep the output voltage at
the specified magnitude and frequency. The two best
compensators (Lead and Lead-Lead) have been evaluated,
and the load is resistive. The load voltage is 415 V (rms), the
frequency is 50 Hz, the input dc voltage is 800 V, the Lf is
3.5 mH, the Rf is 14 mΩ, the Cf is 4.5 µF, and the current
control parameters are kp is 35 and ki is 140. The voltage
control parameters are discussed in detail in the third section.
A. Lead compensator
The load is simply resistive in this case study and the
compensator is Lead. Fig. 6 (a), (b), (c), and (d) show the
output voltage, current, frequency, and active power,
respectively. At 0.4 seconds, the load changes from 1 kW to
1.5 kW (a 50 percent increase in the load), and at 0.6
seconds, the load changes from 1.5 kW to 1 kW. Fig. 7(a)
shows the active power tracking of the inverter with all
traditional control techniques mentioned above, and Fig. 7(b)
is a magnified view of Fig. 7(a). Figs. 8 (a), (b), (c), and (d)
illustrate the output voltage, current, frequency, and active
power tracking with a lead compensator when the load is
reduced by 50%.
B. Lead-Lead compensator
The load is simply resistive, and the compensator is
Lead-Lead. Figs. 9 (a), (b), (c), and (d) show the output
voltage, current, frequency, and active power, respectively.
At 0.4 seconds, the load changes from 1kW to 0.5 kW, and at
0.6 seconds, the load changes from 0.5 kW to 1 kW.
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Phase (deg)
Amplitude
Magnitude (dB)
2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
Fig. 5. (a) Bode plot of the system with all classical controllers; (b) Step response of the system with all classical controllers.
TABLE I
PERFORMANCE INDICES OF VSC WITH ALL CLASSICAL CONTROLLERS
Controller
Peak
Rise Time
Settling
Phase
Gain Crossover
Gain Margin
Phase Crossover
Overshoot (%)
Time (ms)
Margin (0)
Frequency (rad/s)
Frequency (rad/s)
(ms)
(dB)
PI
18.9
0.68
4.69
62.8
1820
inf
0
PID
13.1
0.39
3.41
75.1
3740
inf
0
Lead
0.61
0.17
0.68
68.1
9250
inf
Inf
Lag
4.98
0.37
1.13
64.9
3950
inf
Inf
Lead-Lead
1.61
0.15
1.09
71.3
5210
inf
Inf
Lead-Lag
0.31
0.28
1.21
61.2
9970
inf
Inf
PI-Lead
13.1
0.49
4.92
69.1
2510
inf
0
PI-Lag
28.4
0.64
4.11
51.3
1670
inf
0
(d)
Fig. 6. The load voltage, current, frequency, and active power tracking in the
Lead compensator for R-load (50% sudden increment in the load).
(a)
(b)
Active power (W)
(a)
(c)
Voltage (V)
(b)
Fig. 7. Active power tracking with all compensators for R-load.
(a)
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Current (A)
2022 IEEE International Conference on Power Electronics, Smart Grid, and Renewable Energy (PESGRE)
(b)
V. CONCLUSION
In this work, droop-controlled VSC is presented with
different classical methods in the voltage loop of the system.
After observing the step response and bode plot analysis, the
Lead and Lead-Lead compensators showed little better
performance compared to other methods. The simulation
results with Lead and Lead-lead compensators are presented
to validate the proposed work.
Frequency (Hz)
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[2]
(c)
Active power (W)
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[4]
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Fig. 8. The load voltage, current, frequency, and active power tracking in
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[5]
Voltage (V)
[6]
[7]
Current (A)
(a)
[8]
[9]
[10]
(b)
Frequency (Hz)
[11]
[12]
Active power (W)
(c)
[13]
[14]
[15]
(d)
Fig. 9. The load voltage, current, frequency, and active power tracking in
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