ICC II o cial tutorial notes 3 start design setup from create_
ndm
tags: DC ASIC Synopsys linux
NDM cell libraries
MW library used in ICC
The NDM new data model is used in ICC II; the new data model
Introduce the relevant content of the NDM library and the settings before PR;
NDM library
The standard units and macro units used by ICC are in NDM format and are called CLIBs
Does not use .db Milkway GDS LEF files;
The entire NDM library also contains four parts, which are used to replace the above file functions;
Each CLIB contains the definition of physical and logic timing power consumption required for
complete placement and routing optimization;
Logic timing power consumption information is stored in timing view; originates from multiple .db files
The physical information is stored in the frame view; originates from GDS or LEF is not the information of
the MW library
CLIB can optionally include design and layout view information;
CLIB is related to a specific process; from the .tf file;
Library and process information source
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It can be seen from the above figure that the NDM library is still generated from various files given
by the foundry;
2Library Compiler (library synthesizer) creates:
Convert .lib files to .db
Convert GDS or LEF files to .frame
Library Manager (library management tool) Create CLIBs
Convert .db .frame tech-file to ndm
ICC II uses CLIBs to directly call Library Manager in ICC II;
Standard unit de ned in .lib
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Process documents
For each process, the process file is unique;
It defines all process layer parameters; including:
layer name
GDSIIlayer num
The color and patterns used to display the layout
Design rules (width pitch area pitch)
The definition of via contact;
The rules of the default via array
site definition
layout vs frame view
The frame view is dedicated to layout and routing, which contains the minimum information
required for layout and routing;
Representation of cell library information
CLIB contains logical and physical models;
Each .db file matching PVT Corner is represented as a pane
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After CLIB is created, the source .db and .frame are not needed;
library queries can still use the original .db name
instruction:
get_libs get_lib_cells get_lib_pins get_lib_timing_arcs
Both accept the name of the .db library and the name of the NDM library as parameters;
When the name of the .db library is used, the name of the NDM library needs to be returned
Directly read the contents of the .db and .frame libraries
In addition to using the pre-assembled unit library, it also supports direct reading of the contents in
the .db and .frame libraries;
Library Manager can be called by ICC II. Create cell library (CLBS)
The generated CLIBs will automatically link with the design;
It is submitted as the configuration of the library;
It is similar to DC by setting search_path and link_library variables;
The generated CLIBs will be automatically regenerated when their logical or physical source files are
changed;
library con guration example (automatic CLIB creation)
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# set searchpath
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lappend search_path lib_data/DB lib_data/FRAME
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# specify the link lib
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set_app_var link_library "ABC14_ff_1p16v_n40c.db ..."
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#Specify .frame view when create_lib
create_lib ORCA.dlib \
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-technology ABC4_9m.tf
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-ref_libs {ABC4_svt.frame ...}
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The assembled CLIBs will be stored in ./CLIBs by default for future use;
Con gure (Auto-Assembled) automatically assembled CLIBs (library
cache)
The configuration of the library allows a central and a local library cache (library cache)
Specify the variable value of link_library. Frames also has a central cell library location;
If FC finds the corresponding cell library in the central location, it will not create a new library
If it is not found, FC will form a new celllibrary in the local location and automatically put in the remaining
cell library of the central library;
Example of library con guration
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set_app_var search_path ". lib_data/DB lib_data/FRAME"
# Run the creation of CLIBs and use the multi-core acceleration on the machine;
set_app_options -name lib.configuration.cdpl_host -value "-hosts : 4"
# Specify the path to store CLIBs (default is ./CLIBs) to configure the central cache;
set_app_options -list {
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lib.configuration.local_output_dir "./MY_CLIBs"
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lib.configuration.central_output_dir "./.../TEAM/CLIBs"
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}
#Add process lable
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set_app_options -name lib.configuration.process_lable_mapping \
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{{p_slow {BB.db AA.db FF.db}}{p_type {DD.db EE.db}} {p_fast CC.db}}
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13
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## Specify the library file .dbs
set_app_var link_library "xx_ff_1p16v_n40c.db ..."
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# .frame will be specified when create_lib;
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# Will call Library Manager to create new clibs
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create_lib ORCA.dlib \
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-technology ABC4.tf
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-ref_libs {xx_abc14_hvt.frame ...}
The combination of pre-assembled and newly generated;
In addition to generating all CLIBs (.db + .frame), it is feasible to use pre_assembled CLIBs to
generate new CLIBs;
For example .ndm for standard cell and .db + .frame for macro & IP
Compared with .db, .ndm has priority, and those in the specified .db file that are used by .ndm will
be ignored;
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If the pre-built CLIBs library is used from the beginning and the .db file core .frame library has
updates available, then CLIBs can be easily regenerated for the updated information;
This requires specifying the .db .frame file for clibs at the beginning;
Use updated db le
1
# At the beginning, set up the CLIbs using pre_assembled
2
lappend search_path /x/y/clibs
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create_lib ORCA.dlib -technology ABC4_9m.tf \
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-ref_libs {ABC4_std.ndm ABC4_ls.ndm ABC4_sram.ndm}
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# The reference libraries used by create_lib here are all CLIBs
analyze ...
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##Configure to use the updated .db file SRAM.db
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lappend search_path /x/y/sram_db /x/y/sram_frame
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#Specify a new db file
set link_library "ABC4_sram_12c.db ABC4_sram_20c.db ABC4_sram_m40c.db"
#Replace the original frame reference of the ndm library
set_ref_libs {ABC4_std.ndm ABC4_ls.ndm sram.fram}
# The tool will perform the operation of creating the library again
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16
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report_ref_libs
# Check whether the reference library has been modified;
It is necessary to replace the frame library for the existing pre-built CLIBs (.ndm has priority over
.db)
Library Manager (icc2_lm_shell) ow
create a workspace (create a workspace to create the NDM library and read the process file);
read input data from the LEF GDS frame db file (read the physical and timing guilty conscience
under the required PVT conditions into the do workspace)
check the workspace (validate the entered data, identify and automatically correct errors, create a
frame view)
commit the workshop (write the combined data to the hard disk in the way of the NDM reference
library) and remove the workspace
exploration ow: automatic cell library creation
Exploration flow is an automated process for creating unit libraries;
Use commands to load the logic (.db) and physical libraries (LEFGDS.frame) of all units, including
the library information of standard unit IP cores in all available PVTs and voltage domains;
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Select the PVT parameters you wish to design work;
Then let the library manager do the remaining work:
Combine the correct logical and physical library information;
Check the consistency of the library;
Create a frame view for all loaded cells
Create NDM unit library;
PVT con guration
When you read into the library but don't know which PVT is available, you can use filter
Process/voltage/temperature;
Before reading into the library, if you already know which PVT is available, use configure Process
/voltage/temperature in the set up exploration workshop
Using the PVT configuration allows ICC II to find the correct timing library from all imported DBs
according to the PVT you specify
Exploration ow -example output
1
create_workspace EXPLORE -flow exploration-technology tech.tf
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set_pvt_configuration -voltage {0.95 1.16} -temperatures {125 -40}
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read_db [glob ./libs/DB/*.db]
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foreach frame [glob ./libs/frames/*.frame]
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6
group_libs
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write_workspace -file lib_template.tcl
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9
process_workspace
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# group 1
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create_workspace "LIB_hvt_ff_c" \
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-tech
./LIB_nm_1p9m_ft.tf
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read_db ff0p95v125c
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read_db ff0p95v40c
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read_db ff1p16v40c
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read_db ff1p16v40c
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read_ndm hvt_1p9m.frame
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check_workspace
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commite_workspace -output hvt_ff_c.ndm
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#group 2
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create_workspace "LIB_lvt_ff_c" \
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-tech 1p9m_ft.tf
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read_db ff0p95v125c
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read_db ff0p95v40c
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read_db ff1p16v40c
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read_db ff1p16v40c
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read_ndm lvt_1p9m.frame
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check_workspace
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commite_workspace -output lvt_ff_c.ndm
retrieving version information retrieving version information;
Retrieve the version information of the library manager used when generating the cell library:
separate reference library
Each reference library is independent and needs to be specified and opened independently. You
need to know which unit is in which library;
The search order of the reference library is defined when the design library is created;
aggregate reference library
An aggregated reference library is a combination of independent NDM reference libraries;
It allows simple distribution of multiple related reference libraries;
ICC II will prefer to read in an aggregated reference library rather than multiple independent
reference libraries;
An aggregated reference library has:
Any unit in the aggregation library has only one name;
Top a search order in the reference library;
Reference script of the aggregation library:
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#Create workspace in aggregation mode
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create_workspace std_lib -flow aggregate
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#Open the existing library and add it to the aggregate reference library;
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4
read_ndm ./LIBRARIES/ndms/hvt_lib.ndm
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read_ndm lvt_lib.ndm
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read_ndm rvt_lib.ndm
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## Report all open libraries
get_libs
report_workspace
# Check the eclipse issues of the aggregate workspace report unit
check_workspace
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## Define the search order of the aggregate reference library
set_lib _order {hvt rvt lvt}
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## Delivery workspace
commit_workspace [-output new_std_lib.ndm]
19
design setup
What are the inputs?
reference library
tech only library
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Create a container: the design library
Create a design library
Specify tech and cell libraries
The default is only created in memory and not stored in the hard disk;
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lappend search_path /x/y/libs
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create_lib ORCA.dlib -use_technology_lib abc14_9m_tech.ndm \
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-ref_libs { abc14_9m_tech.ndm
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hvt_std.ndm
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svt_std.ndm
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lvt_std.ndm
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sram.ndm
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ip.ndm
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}
10
## If you use the -use_technology_lib option to specify the tech library, Nan Wu also nee
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## If lib.set.on_disk_operation is set to true create_lib will be written to the hard dis
Process information
If you use a tech library, you need to make sure it contains all the information needed by the NDM
database;
If you are using tech file, you need to apply TLU+ site and routing track information in ICC II
1
create_lib ORCA.dlib \
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-technology abc14_9m_tech.tf \
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-ref_libs ...
4
5
read_parasitics_tech -tlup Cmax.tlup -name maxTLU
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read_parasitics_tech -tlup Cmin.tlup -name minTLU
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## Set site routing track information
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set_attribute [get_site_defs unit] symmetry (symmetric) Y
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set_attribute [get_site_defs unit] is_default true
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set_attribute [get_layers {M1 M2}] track_offset 0.03
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set_attribute [get_layers {M1 M3 M5}] routing_direction horizontal
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set_attribute [get_layers {M2 M4 M6}] routing_direction vertical
compression of block
Block can be compressed to save the volume on the hard disk;
If you want to compress the storage, you need to do the following settings when creating the
design library;
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1
#All blocks will be compressed:
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set_app_var
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-name lib.setting.compress_design_lib -value true
# You can choose to compress the block when saving it
4
save_block -compress
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save_lib -compress
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Reference library path
There are two ways to specify the reference library when creating the design library;
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# One is to store reflib's path in search_path
2
#One is to specify the path of the complete ref lib relative to the current session;
3
# This textbook is playful; I don’t want to play anymore;
Mobile design library or reference library or design library and
reference library;
1
#Corresponding to the above two ways to specify the reference library path When the locati
2
#Use a relative (absolute) reference library path; the first
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#If the design library is moved, there is no need to make any changes;
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#If the path of the reference library changes, update the content of search_path
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#Use the relative reference library path;
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#Reference library needs to be changed along with design_library
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#If you did not update, you need to update the path of the reference library
rebind a design library
1
open_lib $DESIGN_LIBRARY
2
set_search_path
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set_ref_libs
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report_ref_libs
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save_lib
Restricting cells (restricting the use of cells) in speci ed modules or
regions
Use a sub-setting of all available reference library units to restrict the use of units in a specific
module or region;
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Only use units with double site height
Only use high/low speed units
The use of ultra_LVth units is not allowed;
Use set_target_library_subset
example
The sub-design sub1/suba is timing_critical. Set it to use HVT and SVT cells as well as LVT cells.
The rest of the design uses SVT/HVT cells.
1
set_target_library_subset -top {lib_HVT LIB_SVT}
2
set_target_library_subset -object Sub1/suba {lib_HVT LIB_LVT LIB_SVT}
Perform automatic design settings;
If you use DC synthesis, consider using write_icc2_files to create all the necessary input files of
ICC II to achieve seamless switching;
1
write_icc2_files -output ORCA_DC_icc2 \
2
-golden_floorplan ORCA_TOP.fp/floorplan.tcl
3
#### golden floorplan is the DC created by icc II write_floorplan that will only write in
4
Read into the netlist to create a design;
1
# At the beginning, pay attention to adding the path of the netlist to search_path;
2
read_verilog -top ORCA ORCA.v
3
link_block
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# Block level layout and routing;
5
#Design view will be generated when the netlist is read;
linking
The success of the link mainly lies in whether there are missing references;
1
# Use the following command report link problem
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report_design_mismatch -verbose
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get_cells -hierarchical -filter is_unbound
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Load the parasitic parameter model of nxtgrd or TLUplus
1
read_parasitics_tech -tlup $TLUPLUS_MAX_FILE -name MAXTLU
2
read_parasitics_tech -tlup $TLUPLUS_MIN_FILE -name MINTLU
3
4
5
6
7
get_parasitic_techs
# You can view the tlu+ read by the current session;
report_lib -parasitic_tech orca.dlib
# question: What is dlib?
8
In many advanced nodes, the ntxgrd file is used instead of the tlu+ file, the nxtgrd file contains the
information of the TLUplus file, and the same option (-tlup) is used to read the nxtgrd file;
Tlup or nxtgrd files smaller than 20M will be copied to the design library, otherwise it will only store
the pointer of the file to the design library;
Layout site and symmetry (symmetry mirror ip)
The process file will not contain the following information:
The flip layout requirements of the unit layout;
Initialize the default location of the floorplan
Set the site attribute
1
set_attribute [get_site_defs unit_st] symmetry {Y}
2
set_attribute [get_site_defs unit_st] is_default true
3
#
Routing direction
There is no preferential layout direction of the metal line in the process file;
Need to manually execute the wiring direction of the metal layer through the attribute;
See the example above for the tcl statement;
Load power intent (power intent)
Mainly through loading UPF file to load description power intent;
UPF: unified power format is an international file format; it defines a power intent and structure for
a multi-voltage domain design;
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The netlist read by Plex DC already has multi-voltage design components like level shifter isolation
cells retention registers
Load and deliver the UPF le;
1
load_upf TOP.upf
2
load_upf -scope I_B B.upf
3
4
5
### After loading UPF
commit_upf
Refers to all UPF objects, perform the main power ground check
Connect instantiated power management cells with strategies;
It is recommended to run the following command after loading UPF to ensure that everything is
executed;
commit_upf will run automatically in check_mv_design or place_opt;
Golden UPF UPF’ UPF" ow support
Load the DEF layout le;
If the floorplan is saved using write_def; you can use the following command to load the saved
DEF file;
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1
read_def -add_def_only_objects all ORCA.def
2
# By default, those units that exist in the DEF file but not in the netlist (such as tap
3
#Use 5.8 and later version score files as much as possible;
4
caution: (Caution) Content not supported in DEF;
In the 5.8 version of the def file, the following content is not supported:
1. group bound (no fixed coordinates) create_bounds -dimensions
2. partial blockage for category / register / allow_buffer_only create_placement_blockage -type register
-blocked_percentage 10 …
3. voltage areas create_voltage_area -power_domains
4. layer assignments set_routing_rule -min_routing_layer "M6" -max_routing_layer "M7"
If the above tcl commands are executed in the floorplan stage, then these instructions need to be
reapplied after reading the DEF;
Load oorplan
If you use write_floorplan to save the floorplan of ICC II;
1
source ORCA_TOP.fp /floorplan.tcl
2
#floorplan.tcl will source fp.tcl
3
#And fp.tcl will read the saved score file and all the unsupported content in def reapply
Load DC's spg information
If you use spg flow in DC, you need to import the following information into ICC;
Your layout of standard units;
soft constraints of the layer;
The write_icc2_files in DC will create all necessary ICC II inputs, including your layout of standard
cells and soft constraints of layers;
1
write_icc2_files -output ORCA_DC_icc2 \
2
-golden_floorplan ORCA_TOP.fp/floorplan.tcl
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3
### jiazai placement and layer constrains
4
5
sourceORCA_DC_icc2/ORCA.floorplan/floorplan.tcl
Specify unused wiring layers;
By default, ICC II will use all metal layers defined in the process file for wiring;
If you use fewer metal layers, it will lead to:
Congestion analysis before a more optimistic route;
Calculation of inaccurate delay due to inaccurate calculation of RC parasitic parameters
In order to get a more accurate analysis of congestion and timing before routing, specify the
inapplicable amount or the neglected metal layer before routing,
1
set_ignored_layers -max_routing_layer M7
2
report_ignored_layers
Load the information de ned by the scan chain
Load scan-def to help ICCII identify the information and reorder of the scan chain;
Reorder scanchain will be used during placement to reduce congestion;
1
read_def ORCA_scam.def
2
#scan chain will re_order during layout
3
The function of # scan_def is mainly to identify those units in the circuit that are part
Connect PG pin with supply net;
The synthesized netlist does not have the supply net and connection of power/ground; it is not
allowed to connect the P/G PIN with the supply net.
This is a logical link, not a physical metal wiring;
The name of P/G net will be defined in the UPF file;
In a design without UPF, use the -net option of port_pin_list to view the name of the net;
Here will also connect the tie_high /low pin with the P/G PIN;
1
2
connect_pg_net #
check_mv_design # Check the violation of multivoltage
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Turn on the option to use tie_high / low cell
The tie_high / low unit will be inserted into the design during placement optimization;
1
2
set_dont_touch [get_lib_cells */TIE*] false # Remove the dont touch attribute of tie high
set_lib_cell_purpose -include optimization [get_lib_cells */TIE*] # Point the unit intent
The name of the reference library depends on the name of the library file using the ndm suffix. For
example: std_cell.ndm prefix std_cell: get_lib_cells std_cell/AND3*
TIP
： design library package
The purpose is to save the information of each stage before tapout;
You can pack a library at any stage of the design process
1
2
3
4
write_lib_package
# Design data and reference library information are stored in a single file, including ap
read_lib_package
# Restore the design exactly the same as the state before packaging
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Pack /unpack usage details
1
#pack
2
open_lib TOP.dlib
3
open_block abc
4
...
5
write_lib_package TOP.packed
6
#unpack
7
read_lib_package TOP.packed
8
ls TOP.dlib
9
lib.ndm reflibs abc
summary : design setup
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