Chapter 2
Algebraic Methods for the Analysis and
Synthesis of Logic Circuits
Chapter 2
1
Fundamentals of Boolean Algebra (1)
•
•
•
•
•
•
•
•
Basic Postulates
Postulate 1 (Definition): A Boolean algebra is a closed algebraic system
containing a set K of two or more elements and the two operators  and +.
Postulate 2 (Existence of 1 and 0 element):
(a) a + 0 = a (identity for +),
(b) a 1 = a (identity for )
Postulate 3 (Commutativity):
(a) a + b = b + a,
(b) a b = b a
Postulate 4 (Associativity):
(a) a + (b + c) = (a + b) + c
(b) a (bc) = (ab) c
Postulate 5 (Distributivity):
(a) a + (bc) = (a + b) (a + c)
(b) a (b + c) = ab + ac
Postulate 6 (Existence of complement):
(a) a  a  1
(b) a  a  0
Normally is omitted.
Chapter 2
2
Fundamentals of Boolean Algebra (2)
•
Fundamental Theorems of Boolean Algebra
•
•
Theorem 1 (Idempotency):
(a) a + a = a
Theorem 2 (Null element):
(a) a + 1 = 1
Theorem 3 (Involution)
•
a a
Properties of 0 and 1 elements (Table 2.1):
•
OR
a+0=0
a+1=1
Chapter 2
AND
a0 = 0
a1 = a
(b) aa = a
(b) a0 = 0
Complement
0' = 1
1' = 0
3
Fundamentals of Boolean Algebra (3)
•
•
•
•
Theorem 4 (Absorption)
(a) a + ab = a
(b) a(a + b) = a
Examples:
– (X + Y) + (X + Y)Z = X + Y
– AB'(AB' + B'C) = AB'
[T4(a)]
[T4(b)]
Theorem 5
(a) a + a'b = a + b
(b) a(a' + b) = ab
Examples:
– B + AB'C'D = B + AC'D
– (X + Y)((X + Y)' + Z) = (X + Y)Z
Chapter 2
[T5(a)]
[T5(b)]
4
Fundamentals of Boolean Algebra (4)
•
•
Theorem 6
(a) ab + ab' = a
(b) (a + b)(a + b') = a
Examples:
– ABC + AB'C = AC
[T6(a)]
– (W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z)
= (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z)
[T6(b)]
= (W' + X' + Y')(W' + X' + Y)
[T6(b)]
= (W' + X')
[T6(b)]
Chapter 2
5
Fundamentals of Boolean Algebra (5)
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•
Theorem 7
(a) ab + ab'c = ab + ac
Examples:
– wy' + wx'y + wxyz + wxz'
(b) (a + b)(a + b' + c) = (a + b)(a + c)
= wy' + wx'y + wxy + wxz'
= wy' + wy + wxz'
= w + wxz'
=w
– (x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y')
Chapter 2
[T7(a)]
[T7(a)]
[T7(a)]
[T7(a)]
[T7(b)]
6
Fundamentals of Boolean Algebra (6)
•
Theorem 8 (DeMorgan's Theorem)
(a) (a + b)' = a'b'
(b) (ab)' = a' + b'
•
Generalized DeMorgan's Theorem
(a) (a + b + … z)' = a'b' … z'
(b) (ab … z)' = a' + b' + … z'
•
Examples:
– (a + bc)'
= (a + (bc))'
= a'(bc)'
= a'(b' + c')
= a'b' + a'c'
– Note: (a + bc)' a'b' + c'
Chapter 2
[T8(a)]
[T8(b)]
[P5(b)]
7
Fundamentals of Boolean Algebra (7)
•
More Examples for DeMorgan's Theorem
– (a(b + z(x + a')))'
= a' + (b + z(x + a'))'
= a' + b' (z(x + a'))'
= a' + b' (z' + (x + a')')
= a' + b' (z' + x'(a')')
= a' + b' (z' + x'a)
= a' + b' (z' + x')
– (a(b + c) + a'b)'
Chapter 2
= (ab + ac + a'b)'
= (b + ac)'
= b'(ac)'
= b'(a' + c')
[T8(b)]
[T8(a)]
[T8(b)]
[T8(a)]
[T3]
[T5(a)]
[P5(b)]
[T6(a)]
[T8(a)]
[T8(b)]
8
Fundamentals of Boolean Algebra (8)
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•
Theorem 9 (Consensus)
(a) ab + a'c + bc = ab + a'c
(b) (a + b)(a' + c)(b + c) = (a + b)(a' + c)
Examples:
– AB + A'CD + BCD = AB + A'CD
– (a + b')(a' + c)(b' + c) = (a + b')(a' + c)
– ABC + A'D + B'D + CD
= ABC + (A' + B')D + CD
= ABC + (AB)'D + CD
= ABC + (AB)'D
= ABC + (A' + B')D
= ABC + A'D + B'D
Chapter 2
[T9(a)]
[T9(b)]
[P5(b)]
[T8(b)]
[T9(a)]
[T8(b)]
[P5(b)]
9
Switching Functions
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Switching algebra: Boolean algebra with the set of elements K = {0, 1}
If there are n variables, we can define 22 switching functions.
Sixteen functions of two variables (Table 2.3):
n
AB f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
00
01
10
11
•
•
•
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
1
A switching function can be represented by a table as above, or by a switching
expression as follows:
f0(A,B)= 0, f6(A,B) = AB' + A'B, f11(A,B) = AB + A'B + A'B' = A' + B, ...
Value of a function can be obtained by plugging in the values of all variables:
The value of f6 when A = 1 and B = 0 is: 1 0'1'0 = 0 + 1 = 1.
Chapter 2
10
Truth Tables (1)
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•
Shows the value of a function for all possible input combinations.
Truth tables for OR, AND, and NOT (Table 2.4):
ab
f(a,b)=a+b
ab
f(a,b)=ab
a
f(a)=a'
00
0
00
0
0
1
01
1
01
0
1
0
10
1
10
0
11
1
11
1
Chapter 2
11
Truth Tables (2)
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Truth tables for f(A,B,C) = AB + A'C + AC' (Table 2.5)
Chapter 2
ABC
f(A,B,C)
ABC
f(A,B,C)
000
0
FFF
F
001
1
FFT
T
010
0
FTF
F
011
1
FTT
T
100
1
TFF
T
101
0
TFT
F
110
1
TTF
T
111
1
TTT
T
12
Algebraic Forms of Switching Functions (1)
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•
Literal: A variable, complemented or uncomplemented.
Product term: A literal or literals ANDed together.
Sum term: A literal or literals ORed together.
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•
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SOP (Sum of Products):
ORing product terms
f(A, B, C) = ABC + A'C + B'C
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POS (Product of Sums)
ANDing sum terms
f (A, B, C) = (A' + B' + C')(A + C')(B + C')
Chapter 2
13
Algebraic Forms of Switching Functions (2)
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A minterm is a product term in which all the variables appear exactly
once either complemented or uncomplemented.
Canonical Sum of Products (canonical SOP):
– Represented as a sum of minterms only.
– Example: f1(A,B,C) = A'BC' + ABC' + A'BC + ABC
(2.1)
Minterms of three variables:
Minterm
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
Chapter 2
Minterm Code
000
001
010
011
100
101
110
111
Minterm Number
m0
m1
m2
m3
m4
m5
m6
m7
14
Algebraic Forms of Switching Functions (3)
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Compact form of canonical SOP form:
f1(A,B,C) = m2 + m3 + m6 + m7
A further simplified form:
f1(A,B,C) = S m (2,3,6,7) (minterm list form)
The order of variables in the functional notation is important.
Deriving truth table of f1(A,B,C) from minterm list:
Row No. Inputs
(i)
ABC
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Chapter 2
Outputs
f1(A,B,C)=Sm(2,3,6,7)
0
0
1
m2
1
m3
0
0
1
m6
1
m7
(2.2)
(2.3)
Complement
f1'(A,B,C)=Sm(0,1,4,5)
1
m0
1
m1
0
0
1
m4
1
m5
0
0
15
Algebraic Forms of Switching Functions (4)
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Example: Given f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ, express
f(A,B,Q,Z) and f '(A,B,Q,Z) in minterm list form.
f(A,B,Q,Z)
= A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ
= m0 + m1 + m6 + m7
= S m(0, 1, 6, 7)
f '(A,B,Q,Z)
= m2 + m3 + m4 + m5 + m8 + m9 + m10 + m11 + m12
+ m13 + m14 + m15
= S m(2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15)
2 n 1
m
i 0
i
1
(2.6)
AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B'  1.
Chapter 2
16
Algebraic Forms of Switching Functions (5)
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•
A maxterm is a sum term in which all the variables appear exactly once
either complemented or uncomplemented.
Canonical Product of Sums (canonical POS):
– Represented as a product of maxterms only.
– Example: f2(A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C')
(2.7)
Maxterms of three variables:
Maxterm
A+B+C
A+B+C'
A+B'+C
A+B'+C'
A'+B+C
A'+B+C'
A'+B'+C
A'+B'+C'
Chapter 2
Maxterm Code
000
001
010
011
100
101
110
111
Maxterm Number
M0
M1
M2
M3
M4
M5
M6
M7
17
Algebraic Forms of Switching Functions (6)
•
f2(A,B,C) = M0M1M4M5
= PM(0,1,4,5) (maxterm list form)
•
The truth table for f2(A,B,C):
(2.8)
(2.9)
Rwo No. Inputs
M0
M1
M4
M5
Outputs
(i)
ABC A+B+C A+B+C' A'+B+C A'+B+C' f2(A,B,C)
0
000
0
1
1
1
0
1
001
1
0
1
1
0
2
010
1
1
1
1
1
3
011
1
1
1
1
1
4
100
1
1
0
1
0
5
101
1
1
1
0
0
6
110
1
1
1
1
1
7
111
1
1
1
1
1
Chapter 2
18
Algebraic Forms of Switching Functions (7)
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•
•
Truth tables of f1(A,B,C) of Eq. (2.3) and f2(A,B,C) of Eq. (2.7) are identical.
Hence, f1(A,B,C) = S m (2,3,6,7)
= f2(A,B,C)
= PM(0,1,4,5)
(2.10)
Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'),
construct the truth table and express in both maxterm and minterm form.
– f(A,B,C) = M1M3M5M7 = PM(1,3,5,7) = S m (0,2,4,6)
Chapter 2
Row No.
(i)
0
1
2
3
4
5
6
7
Inputs
ABC
000
001
010
011
100
101
110
111
Outputs
f(A,B,C)= PM(1,3,5,7) = Sm(0,2,4,6)
1
m0
0
M1
1
m2
0
M3
1
m4
0
M5
1
m6
0
M7
19
Algebraic Forms of Switching Functions (8)
•
Relationship between minterm mi and maxterm Mi:
– For f(A,B,C), (m1)' = (A'B'C)' = A + B + C' = M1
– In general, (mi)' = Mi
(Mi)' = ((mi)')' = mi
Chapter 2
(2.11)
(2.12)
20
Algebraic Forms of Switching Functions (9)
•
Example: Relationship between the maxterms for a function and its
complement.
– For f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C')
– The truth table is:
Row No. Inputs
(i)
ABC
0
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
Chapter 2
Outputs
f (A,B,C)
1
0
1
0
1
0
1
0
Outputs
f '(A,B,C)= PM(0,2,4,6)
0
M0
1
0
M2
1
0
M4
1
0
M6
1
21
Algebraic Forms of Switching Functions (10)
– From the truth table
f '(A,B,C) = PM(0,2,4,6) and f(A,B,C) = PM(1,3,5,7)
– Since f(A,B,C)  f '(A,B,C) = 0,
(M0M2M4M6)(M1M3M5M7) = 0 or  M  0
– In general,  M  0
– Another observation from the truth table:
f(A,B,C) = S m (0,2,4,6) = PM(1,3,5,7)
f '(A,B,C) = S m (1,3,5,7) = PM(0,2,4,6)
2 3 1
i 0
2 n 1
i 0
Chapter 2
i
i
(2.13)
22
Derivation of Canonical Forms (1)
•
•
Derive canonical POS or SOP using switching algebra.
Theorem 10. Shannon's expansion theorem
(a). f(x1, x2, …, xn) = x1 f(1, x2, …, xn) + (x1)' f(0, x2, …, xn)
(b). f(x1, x2, …, xn) = [x1 + f(0, x2, …, xn)] [(x1)' + f(1, x2, …, xn)]
•
Example: f(A,B,C) = AB + AC' + A'C
– f(A,B,C) = AB + AC' + A'C = A f(1,B,C) + A' f(0,B,C)
= A(1 B + 1 C' + 1' C) + A'(0 B + 0 C' + 0' C) = A(B + C') + A'C
– f(A,B,C) = A(B + C') + A'C = B[A(1+C') + A'C] + B'[A(0 + C') + A'C]
= B[A + A'C] + B'[AC' + A'C] = AB + A'BC + AB'C' + A'B'C
– f(A,B,C) = AB + A'BC + AB'C' + A'B'C
= C[AB + A'B 1 + AB' 1' + A'B' 1] + C'[AB + A'B 0 + AB' 0' + A'B' 0]
= ABC + A'BC + A'B'C + ABC' + AB'C'
Chapter 2
23
Derivation of Canonical Forms (2)
•
•
Alternative: Use Theorem 6 to add missing literals.
Example: f(A,B,C) = AB + AC' + A'C to canonical SOP form.
– AB = ABC' + ABC = m6 + m7
– AC' = AB'C' + ABC' = m4 + m6
– A'C = A'B'C + A'BC = m1 + m3
– Therefore,
f(A,B,C) = (m6 + m7) + (m4 + m6) + (m1 + m3) = Sm(1, 3, 4, 6, 7)
•
Example: f(A,B,C) = A(A + C') to canonical POS form.
– A = (A+B')(A+B) = (A+B'+C')(A+B'+C)(A+B+C')(A+B+C)
= M3M2M1M0
– (A+C')= (A+B'+C')(A+B+C') = M3M1
– Therefore,
f(A,B,C) = (M3M2M1M0)(M3M1) = PM(0, 1, 2, 3)
Chapter 2
24
Incompletely Specified Functions
•
•
•
•
•
A switching function may be incompletely specified.
Some minterms are omitted, which are called don't-care minterms.
Don't cares arise in two ways:
– Certain input combinations never occur.
– Output is required to be 1 or 0 only for certain combinations.
Don't care minterms: di
Don't care maxterms: Di
Example: f(A,B,C) has minterms m0, m3, and m7 and don't-cares d4 and d5.
– Minterm list is: f(A,B,C) = Sm(0,3,7) + d(4,5)
– Maxterm list is: f(A,B,C) = PM(1,2,6)·D(4,5)
– f '(A,B,C) = Sm(1,2,6) + d(4,5) = PM(0,3,7)·D(4,5)
– f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C)
= B'C' + BC (use d4 and omit d5)
Chapter 2
25
Electronic Logic Gates (1)
•
Electrical Signals and Logic Values
Electric Signal
High Voltage (H)
Low Voltage (L)
Logic Value
Positive Logic
Negative Logic
1
0
0
1
– A signal that is set to logic 1 is said to be asserted, active, or true.
– An active-high signal is asserted when it is high (positive logic).
– An active-low signal is asserted when it is low (negative logic).
Chapter 2
26
Electronic Logic Gates (2)
AND
OR
a
b
a
b
NOT a
NAND
NOR
a
b
a
b
a
EXCLUSIVE
OR
b
f(a, b) =ab
f(a, b) =a + b
f(a) =a
f(a, b) =ab
f(a, b) =a + b
f(a, b) =a  b
Symbol set 1
Chapter 2
AND
OR
NOT
NAND
NOR
a
b
a
&
f(a, b) =ab
³
1
f(a, b) =a + b
1
f(a) =a
&
f(a, b) =ab
³
1
f(a, b) =a + b
b
a
b
a
b
a
b
a
EXCLUSIVE
OR
b
=1
f(a, b) =a  b
Symbol set 2
(ANSI/IEEE Standard 91-1984)
27
Electronic Logic Gates (3)
Vcc
14
4B
13
4A
12
4Y
11
3B
10
3A
9
3Y
8
Vcc
14
4Y
13
4B
12
4A
11
3Y
10
3B
9
3A
8
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
1
1Y
2
1A
3
1B
4
2Y
5
2A
6
2B
7
GND
7400:
Y =AB
Quadruple two-input NAND gates
Vcc
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
8
Vcc
14
4B
13
4A
12
4Y
11
3B
10
3A
9
3Y
8
1
1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
7
GND
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
7404:
Y =A
Hex inverters
Chapter 2
7402:
Y =A + B
Quadruple two-input NOR gates
7408:
Y =AB
Quadruple two-input AND gates
28
Electronic Logic Gates (4)
Vcc
1C
1Y
3C
3B
3A
3Y
Vcc
2D
2C
NC
2B
2A
2Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1A
1B
2A
2B
2C
2Y
GND
1A
1B
NC
1C
1D
1Y
GND
7410:
Y =ABC
Triple three-input NAND gates
Chapter 2
7420:
Y =ABCD
Dual four-input NAND gates
29
Electronic Logic Gates (5)
Vcc
NC
H
G
NC
NC
Y
Vcc
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
F
GND
1A
1B
1Y
2A
2B
2Y
GND
7430:
Y =ABCDEFGH
8-input NAND gate
7432:
Y =A + B
Quadruple two-input OR gates
Vcc
4B
4A
4Y
3B
3A
3Y
14
13
12
11
10
9
8
1
2
3
4
5
6
7
1A
1B
1Y
2A
2B
2Y
GND
7486:
Y =A Å B
Quadruple two-input exclusive-OR gates
Chapter 2
30
Basic Functional Components (1)
•
AND
a b
0
0
1
1
0
1
0
1
fAND(a, b) =ab
0
0
0
1
(a)
A B Y
L
L
H
H
L
H
L
H
(b)
L
L
L
H
A
B
Y
(c)
A
B
&
Y
(d)
(a) AND logic function.
(b) Electronic AND gate.
(c) Standard symbol.
(d) IEEE block symbol.
Chapter 2
31
Basic Functional Components (2)
•
OR
a b fOR(a, b) =a + b
A B Y
0
0
1
1
L L
L H
HL
HH
0
1
0
1
0
1
1
1
(a)
(b)
L
H
H
H
A
B
Y
(c)
A
B

Y
(d)
(a) OR logic function.
(b) Electronic OR gate.
(c) Standard symbol.
(d) IEEE block symbol.
Chapter 2
32
Basic Functional Components (3)
•
Meaning of the designation  1 in IEEE symbol:
ab
00
01
10
11
Chapter 2
sum(a, b)
0
1
1
2
sum(a, b)  1
False
True
True
True
fOR(a, b) = a + b
0
1
1
1
33
Basic Functional Components (4)
•
NOT
A
a
0
1
fNOT(a) =a
1
0
(a)
(c)
A Y
L H
H L
(b)
Y
A
1
Y
(d)
(a) NOT logic function.
(b) Electronic NOT gate.
(c) Standard symbol.
(d) IEEE block symbol.
Chapter 2
34
Basic Functional Components (5)
•
Positive Versus Negative Logic
1 is represented by
0 is represented by
Chapter 2
Positive Logic
High Voltage
Low Voltage
Negative Logic
Low Voltage
High Voltage
35
Basic Functional Components (6)
•
AND Gate Usage in Negative Logic
A B Y
1
1
0
0
1
0
1
0
(a)
1
1
1
0
a
b
A
B
Y
(b)
y =a +b
(c)
a
b
y = ab
(d)
–
–
–
–
–
–
Chapter 2
(a) AND gate truth table (L = 1, H = 0)
(b) Alternate AND gate symbol (in negative logic)
(c) Preferred usage
(d) Improper usage
y = a·b =
a  b  a  b  fOR(a , b )
y  (a )  (b )  a  b  fOR(a, b)
(2.14)
(2.15)
36
Basic Functional Components (7)
•
OR Gate Usage in Negative Logic
A B Y
1
1
0
0
1
0
1
0
(a)
1
0
0
0
a
b
A
B
Y
(b)
y = ab
(c)
a
b
y =a +b
(d)
–
–
–
–
–
–
Chapter 2
(a) OR gate truth table(L = 1, H = 0)
(b) Alternate OR gate symbol (in negative logic)
(c) Preferred usage
(d) Improper usage
y  a  b  a  b  a  b  fAND(a , b )
y  (a )  (b )  a  b  fAND(a, b)
(2.16)
(2.17)
37
Basic Functional Components (8)
•
Example 2.32: Building smoke alarm system
– Components: two smoke detectors, a sprinkler, and an automatic
telephone dialer
– Behavior:
• Sprinkler is activated if either smoke detector detects smoke.
• When both smoke detector detect smoke, fire department is called.
– Signals:
• D1, D 2 : Active-low outputs from two smoke detectors.
•
: Active-low input to the sprinkler
SPK
• DIAL : Active-low input to the telephone dialer.
– Logic equations
• SPK  D1  D2
(2.18)
•
(2.19)
DIAL  D1 D 2
Chapter 2
38
Basic Functional Components (9)
•
Logic diagram of the smoke alarm system
Smoke
detectors
D1
D2
G1
D1 + D2
Sprinkler
SPK
G2
D1 D2
Telephone
dialer
DIAL
Chapter 2
39
Basic Functional Components (10)
•
NAND
a b
0
0
1
1
fNAND(a, b) =ab
0
1
0
1
A B Y
1
1
1
0
L L H
L H H
HL H
HH L
(b)
(a)
A
B
Y
(c)
–
–
–
–
Chapter 2
A
B
Y
(d)
A
B
&
Y
(e)
(a) NAND logic function
(b) Electronic NAND gate
(c) Standard symbol
(d) IEEE block symbol
40
Basic Functional Components (10)
•
Matching signal polarity to NAND gate inputs/outputs
–
(a) Preferred usage
(b) Improper usage
a
b
y
a
b
y
a
b
y
a
b
y
(a)
•
(b)
Additional properties of NAND gate:
fNAND (a, a)  a  a  a  fNOT (a)
fNAND (a, b)  a  b  a  b  fAND(a, b)
•
fNAND (a , b )  a  b  a  b  fOR(a, b)
Hence, NAND gate may be used to implement all three elementary operators.
Chapter 2
41
Basic Functional Components (11)
•
AND, OR, and NOT gates constructed exclusively from NAND gates
a
b
ab
f(a, b) =ab= ab
AND gate
a
a
f(a, a) = aa = a
NOT gate
a
f(a, b) =a + b = a + b
b
b
OR gate
Chapter 2
42
Basic Functional Components (12)
•
NOR
a b
0
0
1
1
fNOR(a, b) =a + b
0
1
0
1
A B Y
1
0
0
0
L
L
H
H
(a)
A
B
Y
(c)
–
–
–
–
Chapter 2
A
B
Y
(d)
A
B
L H
H L
L L
H L
(b)
³1
Y
(e)
(a) NAND logic function
(b) Electronic NAND gate
(c) Standard symbol
(d) IEEE block symbol
43
Basic Functional Components (13)
•
Matching signal polarity to NOR gate inputs/outputs
–
(a) Preferred usage
(b) Improper usage
a
b
y
a
b
y
a
b
y
a
b
y
(a)
•
(b)
Additional properties of NAND gate:
fNOR (a, a)  a  a  a  fNOT (a)
fNOR (a, b)  a  b  a  b  fOR(a, b)
•
fNOR (a , b )  a  b  a  b  fAND(a, b)
Hence, NAND gate may be used to implement all three elementary operators.
Chapter 2
44
Basic Functional Components (14)
•
AND, OR, and NOT gates constructed exclusively from NOR gates.
a
b
a +b
f(a, b) =a + b a
OR gate
a
f(a, a) =a + a = a
NOT gate
a
f(a, b) =ab= ab
b
b
AND gate
Chapter 2
45
Basic Functional Components (15)
•
Exclusive-OR (XOR)
– fXOR(a, b) = a  b = a b  ab
ab
00
01
10
11
fXOR(a, b) = a  b
0
1
1
0
(2.24)
AB
LL
LH
HL
HH
Y
L
H
H
L
(a) XOR logic function (b) Electronic XOR gate
A
B
Y
(c) Standard symbol
Chapter 2
A
B
=1
Y
(d) IEEE block symbol
46
Basic Functional Components (16)
•
POS of XOR
a  b  a b  ab
 a a  a b  ab  bb
 a ( a  b)  b ( a  b)
 (a  b )(a  b)
•
Some other useful relationships
– aa=0
– a a =1
– a0=a
– a1= a
– a b  a b
– ab=ba
– a  (b  c) = (a  b)  c
Chapter 2
[P2(a), P6(b)]
[P5(b)]
[P5(b)]
(2.25)
(2.26)
(2.27)
(2.28)
(2.29)
(2.30)
(2.31)
47
Basic Functional Components (17)
•
Output of XOR gate is asserted when the mathematical sum of inputs is one:
ab
00
01
10
11
•
sum(a, b)
0
1
1
2
sum(a, b) = 1?
False
True
True
False
f(a, b) = a  b
0
1
1
0
The output of XOR is the modulo-2 sum of its inputs.
Chapter 2
48
Basic Functional Components (18)
•
Exclusive-NOR (XNOR)
– fXNOR(a, b) = a  b  a
a b fXNOR(a, b) =a b
AB Y
0
0
1
1
LL H
LH L
HL L
HH H
(b)
0
1
0
1
1
0
0
1
(a)
–
–
–
–
Chapter 2
b
(2.32)
A
B
Y
(c)
A
B
=1
Y
(d)
(a) XNOR logic function
(b) Electronic XNOR gate
(c) Standard symbol
(d) IEEE block symbol
49
Basic Functional Components (19)
•
SOP and POS of XNOR
a b  ab
 a b  ab
 a b  ab
 ( a  b )(a  b)
 aa  ab  a b  b b
 ab  a b
•
a b = a
Chapter 2
[P2]
[T8(a)]
[T8(b)]
[P5(b)]
[P6(b), P2(a)]
b
50
Analysis of Combinational Circuits (1)
•
Digital Circuit Design:
– Word description of a function
 a set of switching equations
 hardware realization (gates, programmable logic devices, etc.)
•
Digital Circuit Analysis:
– Hardware realization
 switching expressions, truth tables, timing diagrams, etc.
•
Analysis is used
– To determine the behavior of the circuit
– To verify the correctness of the circuit
– To assist in converting the circuit to a different form.
Chapter 2
51
Analysis of Combinational Circuits (2)
•
Algebraic Method: Use switching algebra to derive a desired form.
•
Example 2.33: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.21a).
a
b
a
c
b
c
P1
P4
f (a, b, c)
P2
P3
(a)
Chapter 2
52
Analysis of Combinational Circuits (3)
•
•
•
Write switching expression for each gate output:
– P  ab, P  a  c, P3  b  c , P4  P1  P2  ab  (a  c)
1
2
The output is: f (a, b, c)  P  P  (b  c )  ab  (a  c)
3
4
Simplify the output function using switching algebra:
f (a, b, c)  (b  c )  ab  a  c
[Eq. 2.24]
 bc  b c  ab  a  c
[T8]
 bc  b c  (a  b )ac
[T5(b)]
 bc  b c  ab c
[T4(a)]
 bc  b c
[Eq. 2.32]
f (a, b, c) = b c
Therefore, f (a,b,c) = (b c)' = b  c
b
c
Chapter 2
f (a, b, c)
53
Analysis of Combinational Circuits (4)
•
Example 2.34: Find a simplified switching expressions and logic network for
the following logic circuit (Fig. 2.22).
a
b
b
c
a
b
a
c
a
b
(a
b
b)(b
c)
c
f (a, b, c)
a +b
a +b +a +c
a +c
Given circuit
Chapter 2
54
Analysis of Combinational Circuits (5)
•
Derive the output expression:
f(a,b,c)
= (a  b)(b  c)  (a  b  a  c)
= (a  b)(b  c)  a  b  a  c)
= (a  b)(b  c)  (a  b )(a  c)
= (ab  a b)(bc  b c)  (a  b )(a  c)
= ab bc  ab b c  a bbc  a bb c  a a  a c  ab  b c
= ab c  a bc  a c  ab  b c
= a bc  a c  ab  b c
= a bc  a c  ab
a
= a b  a c  ab
c
f (a, b, c)
= ac  a  b
a
b
[T8(b)]
[T8(a)]
[Eq. 2.24]
[P5(b)]
[P6(b), T4(a)]
[T4(a)]
[T9(a)]
[T7(a)]
[Eq. 2.24]
Simplified circuit
Chapter 2
55
Analysis of Combinational Circuits (6)
•
Truth Table Method: Derive the truth table one gate at a time.
•
The truth table for Example 2.34:
abc
000
001
010
011
100
101
110
111
Chapter 2
ac
0
1
0
1
0
0
0
0
a b
0
0
1
1
1
1
0
0
f(a,b,c)
0
1
1
1
1
1
0
0
56
Analysis of Combinational Circuits (7)
•
Analysis of Timing Diagrams
– Timing diagram is a graphical representation of input and output signal
relationships over the time dimension.
– Timing diagrams may show intermediate signals and propagation delays.
Chapter 2
57
Analysis of Combinational Circuits (8)
•
Example 2.35: Derivation of truth table from a timing diagram
A
A
B
B
Y = fa (A, B, C)
C
Inputs
Outputs
Z = fb (A, B, C) Y = fa (A, B, C)
Z = fb (A, B, C)
C
t0
(a)
t2
t3
t4
t5
t6
t7
(b)
Inputs
Time
Chapter 2
t1
ABC
Outputs
fa(A, B, C)
fb(A, B, C)
t0
000
0
0
t1
001
1
1
t2
010
1
0
t3
011
0
1
t4
100
0
0
t5
101
0
1
t6
110
1
1
t7
111
1
0
(c)
58
Analysis of Combinational Circuits (9)
•
Propagation Delay
– Physical characteristics of a logic circuit to be considered:
• Propagation delays
• Gate fan-in and fan-out restrictions
• Power consumption
• Size and weight
– Propagation delay: The delay between the time of an input change and the
corresponding output change.
– Typical two propagation delay parameters:
• tPLH = propagation delay time, low-to-high-level output
• tPHL = propagation delay time, high-to-low-level output
– Approximation:
• t  t PLH  t PHL
PD
Chapter 2
2
59
Analysis of Combinational Circuits (10)
•
Propagation delay through a logic gate
a
b
a
b
c
c
(a) Two-input AND gate
a
a
b
b
c
c
tPD
tPD
(c)tPD = tPLH= tPHL
Chapter 2
(b) Ideal (zero) delay
tPLH
tPHL
(d)tPLH<tPHL
60
Analysis of Combinational Circuits (11)
•
Power dissipation and propagation delays for several logic families (Table 2.7)
Logic
Family
7400
74H00
74L00
74LS00
74S00
74ALS00
Propagation Delay
tPD(ns)
10
6
33
9.5
3
3.5
Power Dissipation
Per Gate (mW)
10
22
1
2
19
1.3
74AS00
74HC00
3
8
8
0.17
Chapter 2
Technology
Standard TTL
High-speed TTL
Low-power TTL
Low-power Schottky TTL
Schottky TTL
Advanced low-power
Schottky TTL
Advanced Schottky TTL
High-speed CMOS
61
Analysis of Combinational Circuits (12)
•
Propagation delays of primitive 74LS series gates (Table 2.8)
Chip
74LS04
74LS00
74LS02
74LS08
74LS32
Function
NOT
NAND
NOR
AND
OR
tPLH
Typical
Maximum
9
15
9
15
10
15
8
15
14
22
tPHL
Typical Maximum
10
15
10
15
10
15
10
20
14
22
22
Chapter 2
62
Analysis of Combinational Circuits (13)
•
Example 2.36: Given a circuit diagram and the timing diagram, find the truth
table and minimum switching expression.
D
C
A
F
ABC f (A, B, C)
0
0
0
0
1
1
1
1
Y = f (A, B, C)
E
B
G
A
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
B
C
f ( A, B, C)
D
E
  m(1,4,5,6)
F
 A B C  AB C  AB C  AB C
G
f (A, B, C)
t0
t1
t3
t1 + 2t2 t2 + 2
t1 + 1
Chapter 2
t2 + 1
t4
t5
t4 + 3
t4 + 2
t4 + 1
t6
t7
 AC  B C
t7 + 3
t7 + 2
t7 + 1
63
Synthesis of Combinational Logic Circuits (1)
•
AND-OR and NAND Networks
– Switching expression must be in SOP form.
– Example: f ( p, q, r, s)  pr  qrs  ps
Bubbles
Òcancel
Ó
p
r
q
r
s
p
r
fd (p, q, r, s)
p
s
p
s
(a) AND-OR network
–
Chapter 2
q
r
s
p
r
x1
fd (p, q, r, s)
x2
x3
(b) NAND network
f ( p, q, r , s )  pr  qrs  ps
 pr  qrs  ps
 x1  x2  x3
where x  pr , x  qrs, and x  ps
1
2
3
q
r
s
x1
x2
fd (p, q, r, s)
p
x3
s
(c) NAND network (preferred form)
[T3]
[T8(a)]
64
Synthesis of Combinational Logic Circuits (2)
•
OR-AND and NOR Networks
– Switching expression must be in POS form.
– Example: f ( A, B, C , D)  ( A  B  C )( B  C  D)( A  D)
A
B
C
B
C
D
A
B
C
fe (A, B, C, D) B
C
D
A
D
A
D
(a) OR-AND network
y1
fe (A, B, C, D)
y2
y3
(b) NOR network
A
B
C
B
C
D
y1
fe (A, B, C, D)
y2
A
D
y3
(c) NOR network (preferred form)
– f ( A, B, C, D)  ( A  B  C )( B  C  D)( A  D)
 A  BC  BC  D A  D
[T3]
[T8(b)]
 y1  y2  y3
where y  A  B  C,
1
Chapter 2
y2  B  C  D, and y3  A  D
65
Synthesis of Combinational Logic Circuits (3)
•
Two-level Circuits
– Input signals pass through two levels of gates before reaching the output.
p
r
q
r
s
p
s
p
r
x1
fd (p, q, r, s)
x2
x3
Level 2 Level 1
(a) Two-level network
q
r
s
p
s
x1
fd (p, q, r, s)
x2
x3
Level 3Level 2 Level 1
(b) Three-level network
– Implementation procedure for NAND (NOR) logic:
• Step 1. Express the function in minterm (maxterm) list form.
• Step 2. Write out the minterms (maxterms) in algebraic form.
• Step 3. Simplify the function in SOP (POS) form.
• Step 4. Transform the expression into the NAND (NOR) form.
• Step 5. Draw the NAND (NOR) logic diagram.
Chapter 2
66
Synthesis of Combinational Logic Circuits (4)
•
Circuits with more than two levels are often needed due to fan-in constraints.
a
b
c
f = abcde
d
e
(a) A single five-input AND gate
a
b
a
b
c
c
d
f = abcde
e
d
e
(b) Three-level network of two-input gates
Chapter 2
f = abcde
(c) Four-level network of two-input gates.
67
Synthesis of Combinational Logic Circuits (5)
•
Example 2.37: NAND implementation of f (X,Y,Z) = Sm(0,3,4,5,7)
1. f (X,Y,Z) = Sm(0,3,4,5,7)
2. f (X,Y,Z) = m0 + m3 + m4 + m5 + m7
 XYZ  XYZ  XYZ  XYZ  XYZ
3. f ( X , Y , Z )  YZ  YZ  XZ
[T6(a)]
4a. f ( X , Y , Z )  YZ  YZ  XZ

or
4b. f ( X , Y , Z )  YZ  YZ  XZ
 Y Z  YZ  XZ
[T4]
[T3]
[T8(a)]
Y
Z
Y
Z
X
Z
Chapter 2
f (X, Y, Z)
(a) NAND implementation
68
Synthesis of Combinational Logic Circuits (6)
•
AND-OR-invert Circuits
– A set of AND gates followed by a NOR gate.
– Used to readily realize two-level SOP circuits.
– 7454 circuit: F  AB  CD  EF  GH
Make no external
connection
Vcc
14
B
13
12
11
H
10
G
9
Y
8
Y1
A
B
Y2
C
D
Y
1
A
Chapter 2
2
C
3
D
4
E
5
F
6
NC
7
GND
(a) 7454 circuit package (top view)
Y3
E
F
Y4
G
H
Output
Enable lines
(b) 7454 used as a 4-to-1 multiplexer
69
Synthesis of Combinational Logic Circuits (7)
•
•
Factoring
– A technique to obtain higher-level forms of switching functions.
– Higher-level forms:
• May need less hardware
• May be used when there are fan-in constraints
• More difficult to design
• Slower
Example 2.39:
f ( A, B, C, D)  AB  AD  AC  A( B  D  C )  A( BCD)
A
B
A
D
A
C
Chapter 2
A
f (A, B, C, D)
f (A, B, C, D)
B
C
D
(a) Original form
(b) After factoring
70
Synthesis of Combinational Logic Circuits (8)
•
Example 2.40: f (a,b,c,d) = Sm(8,13) with only two-input AND and OR gates.
– Write the canonical SOP form:
f (a,b,c,d) = Sm(8,13) = ab c d  abc d
(2.34)
Two four-input AND gates and one two-input OR gate are needed.
– Apply factoring:
(2.35)
f (a, b, c, d )  ab c d  abc d  (ac )(bd  b d )
b
d
f = (a, b, c, d)
c
a
Chapter 2
71
Synthesis of Combinational Logic Circuits (9)
•
Example 2.41: A burglar alarm with four control switches, each of which
produces logic 1 when:
Switch A: Secret switch is closed
Switch B: Safe is in its normal position in the closet
Switch C: Clock is between 1000 and 1400 hours
Switch D: Closet door is closed.
Write the equations of the control logic that produces logic 1 when
the safe is moved AND the secret switch is closed,
OR
the closet is opened after banking hours,
OR
the closet is opened with the control switch open.
f ( A, B, C , D)  AB  C D  A D
Chapter 2
72
Synthesis of Combinational Logic Circuits (10)
•
Example 2.42: The Doe family voter:
– Vote for either hamburgers (0) or chicken (1).
– Majority wins.
– If Mom and Dad agree, they win.
– John (Dad): A, Jane (Mom):B, Joe: C, Sue: D.
– The logic function is:
f ( A, B, C , D)  A BCD  AB CD  AB C D  AB C D  ABC D  ABCD
 A BCD  AB CD  AB
 AB  ACD  A BCD
 AB  ACD  BCD
A
B
C
D
Chapter 2
f (A, B, C, D)
73
Synthesis of Combinational Logic Circuits (11)
•
Example 2.43: Logic equations for a circuit that adds two 2-bit binary
numbers (A1A0)2 and (B1B0)2, and produces sum bits (S1S0)2 and carry bit C1;
A1A0
+ B1B0
C1S1S0
Chapter 2
74
Synthesis of Combinational Logic Circuits (12)
•
Truth Table:
A1 A0 B1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Chapter 2
•
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C1
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
S1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
S0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Logic equations:
S0 = A A B B  A A B B  A A B B
1 0 1 0
1 0 1 0
1 0 1 0
 A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
 A1 A0 B1B0  A1 A0 B1B0
S1 = A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
 A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
 A1 A0 B1B0  A1 A0 B1B0
C1 = A A B B  A A B B  A A B B
1 0 1 0
1 0 1 0
1 0 1 0
 A1 A0 B1B0  A1 A0 B1B0  A1 A0 B1B0
75
Synthesis of Combinational Logic Circuits (13)
•
Reduced equations:
S0 = A0 B0  A0  B0
S1 = A A B  A B B  A A B B
1 0 1
1 1 0
1 0 1 0
 A1 A0 B1B0  A1B1B0  A1 A0 B1
C1 = A0 B1B0  A1 A0 B0  A1B1
Chapter 2
76
Computer-aided Design (1)
•
Design Cycle
Concept
Modeling
and
design capture
Synthesis
Design
optimization
Design
database
Test
vectors
Logic
simulation
Analysis
Fail
Results
?
Pass
Realization
Implementation
Physical
design
Testing
Test
Finished circuit
Chapter 2
77
Computer-aided Design (2)
•
Digital Circuit Modeling
– Purpose of modeling:
• Helps the designer formalize a solution.
• To check errors, verify correctness, and predict timing characteristics.
– CAD tools are available for design optimization and transformation of
design from abstract form to a physical realization.
– Model can represent different levels of design abstraction.
Level
Behavioral
Register
Transfer
Gate
Transistor
Layout
Chapter 2
Abstraction
Algorithms to be realized
 Structure of modules
 Data flow among modules and control algorithm
Structure of primitive logic gates
Structure of transistors and low-level components
Geometric patterns of materials for IC layout
78
Computer-aided Design (3)
•
High-level abstract model (behavioral model)
– Describes only desired behavior.
– Usually represented using a hardware description language (HDL), e.g.,
VHDL or Verilog.
– Other representation mechanisms: logic equations, truth tables, and
minterm or maxterm lists.
Chapter 2
79
Computer-aided Design (4)
•
Behavioral models of a full-adder circuit:
(a) block diagram, (b) truth table, (c) logic equations.
a
b
cin
Full_adder
s
cout
(a)
Chapter 2
a b
cin
cout
s
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
0
1
1
s =a
b
cin
cout = ab+ acin + bcin
(c)
(b)
80
Computer-aided Design (5)
•
VHDL behavioral model of a full adder circuit (Figure 2.38)
– Entity defines the interface between the circuit and the outside world.
– Architecture defines the function implemented within the circuit.
– Multiple architectures may be defined for a given entity.
•
Structural model
– Interconnection of components.
– Behavior is deduced from the behavioral models of individual components
and their interconnection.
– Represented by:
• Logic or schematic diagram
• Netlist (textual representation of schematic diagram)
• HDL description of circuit structures.
Chapter 2
81
Computer-aided Design (6)
•
Structural models of a full-adder circuit:
(a) schematic diagram, (b) netlist
I1
I2
I3
a
b
X1
x1
X2
cin
A1
A2
A3
s
O1
a1
a2
a3
(a)
R1
cout
O2
I1
I2
I3
X1
X2
A1
A2
A3
R1
O1
O2
IN
a
IN
b
IN
cin
XOR2 x1
XOR2
s
AND2 a1
AND2 a2
AND2 a3
OR3 cout
OUT
s
OUT cout
a
x1
a
a
b
a1
b
cin
b
cin
cin
a2
a3
(b)
– In a netlist, each circuit element is defined as follows:
gate_name, gate_type, output, input1, input2, …, inputN
– VHDL structural model of a full-adder circuit: Figure 2.40.
Chapter 2
82
Computer-aided Design (7)
•
Mixed-mode model
– Contains both behavioral and structural components.
– Mixed-mode model of the full-adder circuit: (a) full-adder block diagram,
(b) circuit for sum function, (c) truth table for carry function.
a b
a
b
cin
Sum
module
s
Carry
module
cout
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
cin
cout
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
(c)
(a)
a
b
s
cin
(b)
Chapter 2
83
Computer-aided Design (8)
•
Design synthesis process
Behavioral models
Function
library
HDL model
Truth tableLogic equations
Automatic
synthesis
Automatic
synthesis
Structural models
Schematic
Logic
equations
Constraints
Component
library
Netlist
Design
optimization
Minimize
Schematic
Optimized
logic
equations
Back
annotation
Component
library
Netlist
generation
Map design
onto circuit
elements
Circuit
netlist
Chapter 2
84
Computer-aided Design (9)
•
Capture tools
– Each circuit model in the design process must be captured in a format that
can be stored and processed by a digital computer.
– Schematic capture: an interactive graphics tool with which a designer
draws a logic diagram.
Chapter 2
85
Computer-aided Design (10)
•
Schematic capture process
MENU
DRAWING AREA
MENU
DRAWING AREA
Parts Library
ZOOM ZOOM
IN
OUT
and2
and3
or2
or3
nand2
nand3
nor2
nor3
xor2
not
in
out
SELECT
DELETE
COPY MOVE
PLACE DRAW
COMP NET
NAMEPARAM
OPEN SAVE
SHEET SHEET
(a)
MENU
DRAWING AREA
ZOOM ZOOM
IN
OUT
MENU
ZOOM ZOOM
IN
OUT
SELECT
DELETE
SELECT
DELETE
COPY MOVE
COPY MOVE
PLACE DRAW
COMP NET
PLACE DRAW
COMP NET
NAMEPARAM
NAMEPARAM
OPEN SAVE
SHEET SHEET
OPEN SAVE
SHEET SHEET
(c)
Chapter 2
(b)
DRAWING AREA
11
12
13
a
b
X1
x1
X2
s
O1
cin
A1
A2
A3
a1
a2
R1
cout
O2
a3
(d)
86
Computer-aided Design (11)
•
Logic Simulation
– Three primary purposes:
1. Logic verification: only logical correctness is checked.
2. Performance analysis: propagation delays and potential timing
problems are analyzed.
3. Test development (fault simulation): helps develop optimal test set.
– Simulation environment
Design
Netlist
Component
models
Simulator
Logic
verification
data
Chapter 2
Test
vectors
Timing
analysis
data
87
Computer-aided Design (12)
•
Simulation Test Inputs
– Test set: a carefully designed set of test inputs.
– For logic verification, a list of input vectors is used (time is ignored).
– For timing analysis, the time of each input change is also specified.
functional
test set for
input
tabular
waveform
full-adder
waveform
format
format
a b cin
0
0
0
0
1
1
1
1
Chapter 2
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Time a b cin
a
0
5
10
15
b
c
0
5
10
0
0
1
1
0
1
1
0
0
0
0
0
a = 0:0, 10
:1;
b = 0:0, 5:1,15:0;
cin = 0:0;
15
88
Computer-aided Design (13)
•
Event-Driven Simulation
– Event: a change in the value of a signal at a given time.
– Event-driven simulation example for an AND gate:
a
b
a
b
c
c
T0
(a)
Chapter 2
T1 T1 + t
T2
(b)
89
Computer-aided Design (14)
•
Event-driven simulation procedure
– Input test set is converted into a set of events.
– The set of events are entered into an event queue (or event list).
– In each simulation step, the first event is retrieved and is made to occur.
– Output of each affected gate is recomputed, and new event is created.
– Record of all events along with output results are maintained.
– Simulation continues until the event queue is empty or time limit expires.
a
b
cin
cout
s
0
Chapter 2
5 7
10 12
15 17
20
Time a
0 0
0
2 0
4 0
6 0
8 1
10 1
12 1
14
16 1
18 1
20 1
b
0
0
0
1
1
1
1
1
0
0
0
cincout
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
1
1
1
0
0
s
X
0
0
0
1
1
0
0
0
1
1
Time a b
0
2
5
7
10
12
15
17
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
cincout
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
0
s
X
0
0
1
1
0
0
1
90
Computer-aided Design (15)
•
Debugging a full-adder using simulation
erroneous
full-adder
circuit
a
b
simulation output:
error in s at time 3
n1
n2
n3
cin
n4
Chapter 2
Time a
s
0
3
5
10
13
15
18
0
0
0
1
1
1
1
b
0
0
1
1
1
0
0
cin
s
0
0
0
0
0
0
0
X
1
1
1
0
0
1
expanded simulation:
isolates error to n3
Time a b cin n1 n2 n3 n4 s
0 0 0 0 X X X X X
1 0 0 0 1 1 X 1 X
2 0 0 0 1 1 0 1 X
3 0 0 0 1 1 0 1 1
5 0 1 0 1 1 0 1 1
10 1 1 0 1 1 0 1 1
12 1 1 0 1 1 1 1 1
13 1 1 0 1 1 1 1 0
15 1 0 0 1 1 1 1 0
17 1 0 0 1 0 1 1 0
18 1 0 0 1 0 1 1 1
91
Computer-aided Design (16)
•
Detection of static hazard via simulation
– A glitch in g at time t3 can be detected from the output waveforms.
– This occurs because both e and f become 0 momentarily between t2 and t3.
a
b
c
d
e
f
a
b
e
g
g
d
c
f
(a)
Chapter 2
Time
t1
t
t2
t
t3
t
t4
(b)
92
Computer-aided Design (17)
•
Symbolic Logic Signal Values
– Designers sometimes need signal values other than just 0 or 1.
– Logic signal values are represented by a state and a strength.
– A third state X represents an unknown state or a potential problem.
– Truth tables for three-valued logic (with X added)
AND 0 1 X
0
1
X
0 0 0
0 1 X
0 X X
OR 0 1 X
0
1
X
0 1 X
1 1 1
X 1 X
NOT 0
0
1
X
1
0
X
– Signal strength values:
• Forcing (F): signal line is strongly forced to a given state.
• Resistive (R): signal line is weakly forced to a given state.
• Floating (Z): signal line is not forced forced at all.
• Unknown (U): signal strength cannot be determined.
Chapter 2
93
Computer-aided Design (18)
•
Signal strengths are used to resolve conflicting gate outputs:
output resolved in favor of
stronger signal.
output value
unable to be resolved
VCC
F0
I1
F1
Ux
F0
I1
F1
R1
F0
F1
I2
I2
F0
(b)
F0
Chapter 2
94
Computer-aided Design (19)
•
Primitive Device Delay Models
– Every primitive logic gate has an intrinsic delay.
– A gate can be modeled as an ideal (zero-delay) gate and a transport delay
element.
a
b
c*
Ideal
gate
t
c
Time
delay
– Different models of transport delays:
• Unit/Nominal Delay
• Rise Fall Delay
• Ambiguous or Min/Max Delay
Chapter 2
95
Computer-aided Design (20)
•
Unit/Nominal Delay
– Unit delay: assign to each gate in a circuit the same unit delay.
– Nominal delay: delays are determined separately for each type of gate
(e.g., on time unit for NOR and two time units for XOR).
a
b
c
t
Chapter 2
t
96
Computer-aided Design (21)
•
Rise/Fall Delay
– Different delays for 0 to 1 transition and 1 to 0 transition.
– tPLH (rise time): propagation delay from low to high.
– tPHL (fall time): propagation delay from high to low.
a
b
c
tPLH
(rise time)
Chapter 2
tPHL
(fall time)
97
Computer-aided Design (22)
•
Ambiguous or Min/Max Delay
– Sometimes it is impossible to predict exact rise or fall time of a signal.
– For worst-case performance analysis, {tmin, tmax} is specified for each
timing parameter.
a
b
c
tmin
tmax
Chapter 2
98
Computer-aided Design (23)
•
A problem with min/max delay: the results tend to be pessimistic.
circuit model
a
b
c
d
worst-case delays:
ambiguity region gets larger
at each successive level
f
h
e
g
d
e
g
h
15
10 1214 16
Chapter 2
20
25
99
Computer-aided Design (24)
•
Inertial Delay
– An input value must persist for some minimum duration of time to provide
the output with the needed inertia to change.
– The minimum duration is called inertial delay.
– Effect of inertial delay:
a
a
b
b
c
c
(a) Transport delay model
(b) Inertial delay model
– Gate model with both inertial delay and transport delay:
a
t
a*
c*
b
Chapter 2
t
Inertial
delay
t
c
b*
Ideal
gate
Transport
delay
100