VLSI Design
Chapter 4
Circuit Characterization and
Performance Estimation
Jin-Fu Li
Chapter 4 Circuit Characterization
and Performance Estimation
• Resistance & Capacitance Estimation
• Switching Characteristics
• Transistor Sizing
• Power Analysis
• Other Issues
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Resistance Estimation
• Resistance
− R = ( ρ / t )( L / W ), where ( ρ , t , L, W ) is (resistivity,
thickness, conductor length, conductor width)
− Sheet resistance Rs = Ω/
− R = Rs ( L / W )
W
W
1 rectangular block
R = Rs (L / W )
L
W
t
L
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t
L
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4 rectangular block
R = Rs ( 2 L / 2W ) = Rs ( L / W )
3
Resistor – None rectangular (1)
L
R=L/W
L
W
W1
R=4L/(L+4W 1)
R=L/W
W
W1
L
L
W2
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R=2L/(L+2W 1)
W2
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Resistor – None rectangular (2)
W1
W1
W2
W2
L
W
W2
Ratio=L/W
W1
W2
W1
Ratio=W 1/W 2
Ratio=W 1/W 2
W2
W1
W1
W2
W1
W2
W1
Ratio=W 2/W 1
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Ratio=W 2/W 1
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Capacitor
• Load capacitance on the output of a CMOS
gate is the sum of
− Gate capacitance
− Diffusion capacitance
− Routing capacitance
• Capacitance can be calculated by
− C =
ε 0ε x
A
d
− ε x : dielectric constant
− ε 0 : permitivity of free space
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Gate Capacitor (1)
Accumulation
gate
gate
Depletion
Vg<0
gate
tox
Co
Co
gate
Vg>0
tox
Depletion layer
Cdep
P-substrate
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P-substrate
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Gate Capacitor (2)
Inversion
gate
gate
Capacitance variation
Vg>0
Accumulation Depletion Inversion
1.0
Co
Cdep
tox
Channel
Depletion layer
Low freq.
C/Co
High freq.
P-substrate
0
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Vt
Vgs
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Gate Capacitor (3)
gate
Cgs Cgb
Cgd
source
Csb
drain
depletion layer
Cdb
substrate
Cg=C gb+C gs+Cgd
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Gate Capacitor (4)
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Diffusion Capacitor
Substrate
b
a
Source
Diffusion
Area
Drain
Diffusion
Area
a
b
Cjp
Xc
C d = C ja × (ab) + C jp × (2a + 2b)
Cja
Cja=junction capacitance per micron square
Cjp=periphery capacitance per micron
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Wire Capacitor (1)
Fringing fields
W
L
T
H
Insulator (Oxide)
substrate
Layer 3
Multi-layer
conductor
C22
C23
C21
Layer 2
Layer 1
C2=C21+C23+C22
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Wire Capacitor (2)
A
B
C
D
m2
m2
C
C
poly
E
F
G
m2
m2
m1
C
m1
C
C
poly
C
m2
m2
m1
C
C
Thin-oxide/diffusion
Substrate
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Inductor
• For bond wire inductance
− L=
µ
4h
ln( )
2π
d
• For on-chip metal wires
L=
µ
8h w
ln( + )
2π
w 4h
• The inductance produces Ldi/dt noise especially
for ground bouncing noise. Note that when
CMOS circuit are clocked, the current flow
changes greatly.
di
V = L
dt
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Wire RC Effects (1)
Ij-1
R
R
C
CdV = Idt ⇒ C
Vj-1 R Vj
C
dV j
dt
Ij
R V
j+1
C
= ( I j −1 − I j ) =
R
C
(V j −1 − V j )
R
C
−
(V j − V j +1 )
R
dV d 2V
rc
= 2 ⇒ t x = kx 2
dt
dx
r : resistance per unit length
c : capacitance per unit length
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Wire RC Effects (2)
1mm
1mm
buffer
input
output
tbuf
−15 2
Assume that t x = 4 ×10 x
With buffer
t p = 4 × 10−15 × 10002 + tbuf + 4 × 10−15 × 10002
= 4ns + tbuf + 4ns = 8ns + tbuf
Without buffer
t p = 4 × 10−15 × 20002 = 16ns
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Delay Analysis (1)
Vin(t)
Vout (t)
Vds=Vgs-Vt
CL
VDD
Ids
Vin(t)
VDD
tpf
t
tdr
90%
Vout (t)
Vout (t)
50%
10%
tf
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tr
VDD
t
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Delay Analysis (2)
P-device
P-device
Vout (t)
N-device Idsn
CL
Saturated Vout>=VDD-Vtn
P-device Idsp
Vout (t)
N-device
Vout (t)
CL
Saturated Vout<=|Vtp|
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CL
Nonsaturated 0<Vout<=VDD-Vtn
P-device
N-device
Rcn
Rcp
Vout (t)
N-device
CL
Nonsaturated |Vtp|<Vout<VDD
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Delay Analysis (3)
• The fall time consists of two intervals:
− tf1=period during which the capacitor voltage, Vout,
drops from 0.9VDD to (VDD-Vtn)
− tf2=period during which the capacitor voltage, Vout,
drops from (VDD-Vtn) to 0.1VDD
dVout β n
CL
+
(VDD − Vtn ) 2 = 0 (In saturation)
dt
2
CL
CL
tf ≈ k ×
tr ≈ k ×
β nVDD
β pVDD
CL 1
1
tp ≈ k ×
( + )
VDD β n β p
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Design Challenges
• Reduce CL
− Careful layout can help to reduce the diffusion
and interconnect capacitance
• Increase β
n
and β p
− Increase the transistor sizes also increases the
diffusion capacitance as well as the gate
capacitance. The latter will increase the fan-out
factor of the driving gate and adversely affect its
speed.
• Increase VDD
− The designer does not have too much control
over this factor, as the supply voltage is
determined by system and technology
considerations.
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Gate Delays
P3
P2
β neff
P1
out
IN-3
N3
IN-2
N2
IN-1
N1
1
=
(1 / β n1 ) + (1 / β n 2 ) + (1 / β n3 )
β n1 = β n 2 = β n3 ⇒ β neff =
βn
3
L
L
3L
L
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Delay Analysis – Switch Level RC Model
P4
P3
P2
P1
Rp
out
A
N4
Cab
B
Cout
N3
Cout
Cbc
C
N2
Rn
Ccd
D
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Switch Level RC Model
• Simple RC model
t df = ∑ R pulldown × ∑ C pulldown− path
= ( RN 1 + RN 2 + RN 3 + RN 4 ) × (Cout + Cab + Cbc + Ccd )
t dr = R p 4 × Cout
• Elmore delay model
t d = ∑ Ri Ci
i
tdf = ( RN 1 × Ccd ) + [( RN 1 + RN 2 ) × Cbc ] + [( RN 1 + R N 2 + RN 3 ) × C ab ]
+ [( RN1 + RN 2 + RN 3 + RN 4 ) × Cout ]
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Transistor Sizing
tinv-pair
4/1
2/1
Icharge
R
R
3Ceq
Idischarge
3Ceq
W p=2W n
tinv − pair = t fall + trise
R
= R3Ceq + 2 3Ceq
2
= 3RCeq + 3RCeq
= 6 RCeq
Ceq is the capacitance of a unit (2/1) NMOS transistor
R is the equivalent channel resistance of a unit NMOS
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Transistor Sizing
tinv-pair
2/1
2/1
Icharge
R
2R
2Ceq
Idischarge
2Ceq
W p=W n
tinv − pair = t fall + t rise = R2C eq + 2 R2C eq
= 6 RCeq
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Transistor Sizing
2/3
2/1
Icharge
3Rp
R
Ceq
Idischarge
Ceq
tinv − pair = trise + t fall = 6 R(C g + 2C d ) + R(C g + Cd )
= 7 RC eq
Ceq = Cg + 2Cd
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Transistor Sizing
1
a
a2
a3
CL
n(4) stages
10
9
8
7
6
a/ln(a)e 5
4
3
2
1
2
4
10
Stage ratio -- a
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Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
Vsupply t +T
1 t +T
Pave = ∫
p (t )dt =
isupply (t )dt
∫
t
T t
T
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Power Analysis
• Power consumption of a CMOS circuit
− Static power caused by the leakage current and
other static current
− Dynamic power caused by the total output
capacitance
− Dynamic power caused by the short-circuit
current
• Total power consumption of a CMOS circuit is
given by
− Pt = Ps + Pd + Psc
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Power Analysis – Static Power
Vin
Gnd
VDD
Vout
p+
n+
n+
p+
p+
n+
n-well
p-substrate
PN junction reverse bias leakage current
i0 = is ( e qV / KT − 1)
n
Ps = ∑ I leakage × Vsup ply
1
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Power Analysis – Dynamic Power
• Let the inverter is operated at a switching
frequency f=1/T
VDD
ip
Vin
io
V out
CL
in
1 T
Pd = ∫ io (t )vo (t )dt
T 0
dvo
i p = io = C L
dt
dvo
in = −io = −C L
dt
0
1 VDD
Pd = [∫ C L vo dvo − ∫ C L vo dvo ]
VDD
T 0
2
C LVDD
2
Pd =
= fC LVDD
T
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Energy vs. Power
• Energy consumption of an inverter (from 0 → V
DD
)
− The energy drawn from the power supply is
∗ E = QV = C LV DD2
− The energy stored in the load capacitance is
V
1
2
∗ E cap = ∫0 C vo dv o = C LV DD
2
− The output from VDD → 0
∗ The Ecap is consumed by the pull-down NMOS
DD
• Low-energy design is more important than lowpower design
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Power Analysis – Short-Circuit Power
T
VDD
VDD-|Vtp|
Vin
isc
Vout
tr
tf
Vtn
CL
Imax
Imean
t1 t2 t3
Psc = I mean V DD
I mean
I mean
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1 t2
= 2 × [ ∫ i ( t ) dt +
T t1
4 t2
=
[ ∫ i ( t ) dt ]
T t1
∫
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t3
t2
i ( t ) dt ]
33
Power Analysis – Short-Circuit Power
4 t2 β
I mean = [ ∫
(V in ( t ) − V T ) 2 dt ]
T t1 2
V DD
V in ( t ) =
t
tr
VT
t1 =
tr
V DD
tr
t2 =
2
β
Psc =
(V DD − 2V T ) 3 τ f , where τ = tr = t f
12
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Power Analysis – Switching Activity
• The dynamic power for a complex gate cannot be
estimated by the simple expression C LVDDf
• Dynamic power dissipation in a complex gate
− Internal cell power
VDD
− Capacitive load power
• Capacitive load power
− PL = α C L V
2
DD
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∑
i =1
C
C1
A
f
out
• Internal celln power
− P =
int
B
A
α i C iV iV DD f
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C
B
C2
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Power Analysis – Glitching power
• In a static logic gate, the output or internal nodes
can switch before the correct logic value is being
stable. This phenomenon results in spurious
transitions called glitches.
ABC
A
B
C
100
111
D
D
Z
Z
Unit delay
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Spurious transition
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Rules for avoiding Glitching power
• Balance delay paths; particularly on highly loaded
nodes
• Insert, if possible, buffers to equalize the fast path
• Avoid if possible the cascaded implementation
• Redesign the logic when the power due to the
glitches is an important component
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Principles for Power Reduction
• Prime choice: reduce voltage
− Recent years have seen an acceleration in supply
voltage reduction
− Design at very low voltage still open question
(0.6V… 0.9V by 2010)
• Reduce switching activity
• Reduce physical capacitance
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Low -Power Design – Layout Guidelines
• Identify, in your circuit, the high switching nodes
• Use for these high activity nodes low-capacitance
layers such as metal2, metal3, etc.
• Keep the wires of high activity nodes short
• Use low-capacitance layers for high capacitive
nodes and busses
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Low -Power Design Guidelines
• Avoid, if possible, the use of dynamic logic design
style
• For any logic design, reduce the switching activity,
by logic reordering and balanced delays through
gate tree to avoid glitching problem
• In non-critical paths, use minimum size devices
whenever it is possible without degrading the
overall performance requirements
• If pass-transistor logic style is used, careful design
should be considered
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Charge Sharing
• Charge Q=CV
• A bus can be modeled as a capacitor Cb
− If the voltage on the bus is sampled to determine
the state of a given signal
Bus
Vb
Cb
( Qb = CbVb )
QT = CbVb + C sVs
CT = Cb + Cs
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VR =
Vs
Cs
( Qs = CsVs )
QT
= (CbVb + CsVs ) /(Cb + C s )
CT
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Contact Replication
• Current tends to concentrate around the perimeter
in a contact hole
− This effect, called current crowding, puts a practical
upper limit on the size of the contact
− When a contact or a via between different layers is
necessary, make sure to maximize the contact
perimeter (not area)
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Ground Bounce
Voltage
Vin
L
Vout
Time
Current
I
Time
VDD Pad
Vout
Vin
I
VSS Pad
VL
L
VL =L(di/dt)
Time
Ground bounce
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Approaches for Coping with L(di/dt)
• Multiple power and ground pins
− Restrict the number of I/O drivers connected to a
single supply pins (reduce the di/dt per supply pin)
• Careful selection of the position of the power and
ground pins on the package
− Avoid locating the power and ground pins at the
corners of the package (reduce the L)
• Increase the rise and fall times
− Reduce the di/dt
• Adding decoupling capacitances on the board
− Separate the bonding-wire inductance from the
inductance of the board interconnect
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Package Issues
• Packaging requirements
− Electrical: low parasitics
− Mechanical: reliable and robust
− Thermal: efficient heat removal
− Economical: cheap
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Bounding Techniques
Wire Bonding
Substrate
Die
Pad
Lead Frame
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Die Cost
Single die
Wafer
Going up to 12” (30cm)
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Yield Estimation
No. of good chips per wafer
Y=
× 100%
Total number of chips per wafer
Wafer cost
Die cost =
Dies per wafer × Die yield
π × (wafer diameter/2 )2 π × wafer diameter
Dies per wafer =
−
die area
2 × die area
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