VPI®
Vital Processor
Interlocking Control
System
Copyright © 2001, 2006, 2013 Alstom Signaling Inc.
Installation, Operation, and Maintenance Manual
P2086B, Volume 1
VPI®
Vital Processor
Interlocking Control
System
Copyright © 2001, 2006, 2013 Alstom Signaling Inc.
Installation, Operation, and Maintenance Manual
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, November 2013, Printed in U.S.A.
LIST OF EFFECTIVE PAGES
P2086B, Volume 1, VPI® Vital Processor Interlocking Control System Installation,
Operation, and Maintenance Manual
ORIGINAL ISSUE DATE:
January 2001
CURRENT REVISION AND DATE:
Rev D, November 2013
PAGE
CHANGE OR REVISION LEVEL
Cover
Nov/13
Title page
Nov/13
Preface
Nov/13
i through xxii
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1–1 through 1-4
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2–1 through 2-10
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3–1 through 3-2
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4–1 through 4-24
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5–1 through 5-92
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6–1 through 6-60
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7–1 through 7-22
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8–1 through 8-128
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9–1 through 9–68
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A–1 through A–4
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B–1 through B–4
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C–1 through C–4
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D–1 through D–8
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E–1 through E–4
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F–1 through F–4
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G–1 through G–4
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H–1 through H–8
Nov/13
P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
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P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
ABOUT THE MANUAL
This manual is intended to describe a set of the Alstom Vital Processor Interlocking
Control System boards.
The information in this manual is arranged into sections. The title and a brief description
of each section follow:
Section 1 – INTRODUCTION: This section provides a general description of the Alstom
VPI® Vital Processor Interlocking Control System.
Section 2 – INSTALLATION AND SETUP: This section describes installation and
configuration of the software of the VPI system for regular service.
Section 3 – OPERATION: This section describes VPI in-service operating instructions.
Section 4 – THEORY OF OPERATION: This section provides an overview of VPI
system level functionality.
Section 5 – VITAL PRINTED CIRCUIT BOARDS: This section describes the Printed
Circuit Boards used to provide Vital functionality in the VPI System.
Section 6 – NON-VITAL PRINTED CIRCUIT BOARDS: This section describes the
Printed Circuit Boards used to provide non-Vital functionality in the VPI System.
Section 7 – VPI CHASSIS: This section serves as an overview of chassis related
options including part numbers and a brief explanation of their application.
Section 8 – MAINTENANCE: This section describes the process of making changes to
an existing application, especially as it applies to Vital applications.
Section 9 – BOARD REFERENCE DATA: This section provides board drawings and
details.
Appendix A – GLOSSARY: This section lists the acronyms used throughout this
manual.
Appendix B – MODULE WIRING AND SPECIAL TOOLS: This section provides
information on module wiring and special tools needed.
Appendix C – Alstom VPI APPLICATION DESIGN AND TEST POLICY: This section
is provided as a reference guide to the validation process.
Appendix D – SIMULATOR REFERENCE: This section gives detailed information on
some simulator file formats.
P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
Appendix E – CIRCUIT BOARD KEYING: This section describes the various circuit
board keying information.
Appendix F – SIGNATURE HEADERS AND PROMS: This section describes how to
use the Graphical Simulator tool.
Appendix G – ALLOWABLE VSC/CSEX BOARD COMBINATIONS: This section
provides the allowable VSC/CSEX board combinations for the VPI system.
Appendix H – CRG APPLICATION GUIDELINES: This section gives detailed
information on the CRG application guidelines.
P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
MANUAL SPECIAL NOTATIONS
In the Alstom manuals, three methods are used to convey special informational
notations. These notations are warnings, cautions, and notes. Both warnings and
cautions are readily noticeable by boldface type and a box around the entire
informational statement.
Warning
A warning is the most important notation to heed. A warning is used to tell the reader
that special attention needs to be paid to the message because if the instructions or
advice is not followed when working on the equipment then the result could be either
serious harm or death. The sudden, unexpected operation of a switch machine, for
example, or the technician contacting the third rail could lead to personal injury or death.
An example of a typical warning notice follows:
WARNING
Disconnect motor energy whenever working on switch layout or switch
machine. Unexpected operation of machine could cause injury from open
gears, electrical shock, or moving switch points.
Caution
A caution statement is used when an operating or maintenance procedure, practice,
condition, or statement, which if not strictly adhered to, could result in damage to or
destruction of equipment. A typical caution found in a manual is as follows:
CAUTION
Turn power off before attempting to remove or insert circuit boards into a
module. Boards can be damaged if power is not turned off.
Note
A note is normally used to provide minor additional information to the reader to explain
the reason for a given step in a test procedure or to just provide a background detail. An
example of the use of a note follows:
Note: This step should be done first to validate the correct information
is used.
P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
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P2086B, Volume 1, Rev. D, Nov/13
Alstom Signaling Inc.
PREFACE
NOTICE OF CONFIDENTIAL INFORMATION
Information contained herein is confidential and is the
property of Alstom Signaling Inc. Where furnished with a
proposal, the recipient shall use it solely to evaluate the
proposal. Where furnished to customer, it shall be used
solely for the purposes of inspection, installation, or
maintenance. Where furnished to a supplier, it shall be used
solely in the performance of the contract. The information
shall not be used or disclosed by the recipient for any other
purposes whatsoever.
VPI®, WEE-Z®, and Microchron® are registered trademarks of Alstom Signaling Inc.
GM4000A™, iVPI™, microWIU™, and VCS™ are trademarks of Alstom Signaling Inc.
All other trademarks referenced herein are trademarks of their respective owners.
FOR QUESTIONS AND INQUIRIES, CONTACT CUSTOMER SERVICE AT
1–800–717–4477
OR
WWW.ALSTOMSIGNALINGSOLUTIONS.COM
ALSTOM SIGNALING INC.
1025 JOHN STREET
WEST HENRIETTA, NY 14586
REVISION LOG
Revision
Date
0(A)
June 1996
1(B)
2(C)
D
Description
Checked
Approved
SM
NI
November 1999
VE
NI
June 2003
VE
NI
November 2013
P2086B, Volume 1, Rev. D, Nov/13
Original issue
By
Updated with new part
numbers, new
illustrations, new
warnings
SG
KW
MS
Alstom Signaling Inc.
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Alstom Signaling Inc.
TABLE OF CONTENTS
Topic
Page
SECTION 1 – INTRODUCTION ................................................................................... 1-1
1.1
SCOPE OF MANUAL ................................................................................. 1-1
1.2
TERMS, ABBREVIATIONS AND TRADE NAMES ..................................... 1-1
1.3
VPI SYSTEM FEATURES .......................................................................... 1-1
1.4
RELATED PUBLICATIONS ........................................................................ 1-3
1.5
SPECIFICATIONS ...................................................................................... 1-4
1.6
DIAGNOSTICS ........................................................................................... 1-4
SECTION 2 – INSTALLATION AND SETUP ............................................................... 2-1
2.1
INTRODUCTION ........................................................................................ 2-1
2.2
UNPACKING AND INSPECTION ............................................................... 2-1
2.3
MOUNTING PROCEDURES ...................................................................... 2-2
2.4
PRE-POWER-UP CHECKS........................................................................ 2-2
2.5
SOFTWARE CONFIGURATION ................................................................ 2-5
2.6
RECORDING OF SYSTEM CONFIGURATION DATA ............................... 2-6
2.6.1
Handheld Terminal ........................................................................... 2-6
2.6.2
General Diagnostics ......................................................................... 2-6
2.6.3
Vital Diagnostic Protocol (VDP)........................................................ 2-7
2.6.4
Tracker Remote Diagnostic Analyzer Software ................................ 2-7
SECTION 3 – OPERATION ......................................................................................... 3-1
3.1
INTRODUCTION ........................................................................................ 3-1
3.2
START-UP PROCEDURE .......................................................................... 3-1
3.3
OPERATING INSTRUCTIONS ................................................................... 3-1
3.4
OPERATING UNDER UNUSUAL CONDITIONS ....................................... 3-1
3.5
OPERATIONAL CHANGES........................................................................ 3-2
3.6
SHUTDOWN PROCEDURE ....................................................................... 3-2
SECTION 4 – THEORY OF OPERATION .................................................................... 4-1
4.1
INTRODUCTION ........................................................................................ 4-1
4.2
VITAL SYSTEM OPERATION .................................................................... 4-3
4.2.1
Vital Input Check Circuit ................................................................... 4-4
4.2.2
Other Inputs ..................................................................................... 4-5
4.2.3
Vital Expression Evaluation .............................................................. 4-5
4.2.4
Vital Checkwords ............................................................................. 4-7
4.2.5
System Timing ................................................................................. 4-8
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TABLE OF CONTENTS
Topic
Page
4.2.6
System Output Update ..................................................................... 4-8
4.2.7
Electrical Isolation ............................................................................ 4-8
4.2.8
Absence-Of-Current Detector .......................................................... 4-8
4.2.9
Output Loads.................................................................................... 4-9
4.3
NON-VITAL SYSTEM OPERATION ......................................................... 4-10
4.3.1
Non-Vital Processing...................................................................... 4-10
4.3.2
Non-Vital TWC Communications.................................................... 4-10
4.3.3
Non-Vital I/O................................................................................... 4-11
4.3.4
Diagnostics for Non-Vital VPI ......................................................... 4-12
4.4
VPI MODULE............................................................................................ 4-13
4.4.1
System Expansion ......................................................................... 4-16
4.4.2
System Bus .................................................................................... 4-16
4.4.3
I/O Bus Motherboard (Vital I/O Bus and Non-Vital I/O Bus) ........... 4-18
4.4.4
Expansion Bus ............................................................................... 4-20
4.4.5
Board Placement............................................................................ 4-21
4.4.6
Signature Header Assignments ..................................................... 4-22
4.4.7
Output Board Signature PROMs .................................................... 4-22
4.4.8
Board Address Assignments .......................................................... 4-23
4.4.9
Field-Settable Vital Timers ............................................................. 4-23
4.4.10
Power Supply Consideration .......................................................... 4-24
4.4.11
Backplane Interface Card ............................................................... 4-24
SECTION 5 – VITAL PRINTED CIRCUIT BOARDS .................................................... 5-1
5.1
INTRODUCTION ........................................................................................ 5-1
5.1.1
Vital and Non-Vital Subsystems ....................................................... 5-1
5.2
CPU (CENTRAL PROCESSING UNIT) BOARD, P/N 59473-742 .............. 5-5
5.2.1
General ............................................................................................ 5-5
5.2.2
Memory Address Decoding .............................................................. 5-6
5.2.3
Control Bus Buffering ....................................................................... 5-7
5.2.4
Reference Timer and I/O Decoding.................................................. 5-7
5.2.5
Microprocessor Control Circuitry ...................................................... 5-8
5.2.6
Automatic Hardware Reset .............................................................. 5-9
5.2.7
Interrupt Handling............................................................................. 5-9
5.2.8
Integrated Diagnostics ..................................................................... 5-9
5.2.9
Software Revision Signature .......................................................... 5-10
5.2.10
Maintenance Indicators .................................................................. 5-10
5.2.11
Test Points ..................................................................................... 5-10
5.2.12
Interface Connections .................................................................... 5-10
5.2.13
Specifications ................................................................................. 5-11
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TABLE OF CONTENTS
Topic
Page
5.2.14
Assembly Differences .................................................................... 5-11
5.3
PD (POLYNOMIAL DIVIDER) BOARD, P/N 59473-737 ........................... 5-12
5.3.1
General .......................................................................................... 5-12
5.3.2
Interface Connections .................................................................... 5-14
5.3.3
Specifications ................................................................................. 5-14
5.4
CPU/PD (CENTRAL PROCESSING UNIT/POLYNOMIAL
DIVIDER) BOARD, P/N 31166-029 .......................................................... 5-15
5.4.1
General .......................................................................................... 5-15
5.4.2
Memory Address Decoding ............................................................ 5-17
5.4.3
Reference Timer and I/O Decoding................................................ 5-17
5.4.4
Hardware Reset and Watchdog Timer ........................................... 5-17
5.4.5
Integrated Diagnostics ................................................................... 5-18
5.4.6
Software Revision Signature .......................................................... 5-18
5.4.7
Indicators ....................................................................................... 5-19
5.4.8
Polynomial Divider ASIC ................................................................ 5-19
5.4.9
High Integration Embedded Microprocessor .................................. 5-20
5.4.10
Interface Connections .................................................................... 5-20
5.4.11
CPU/PD Board Jumpers ................................................................ 5-21
5.4.12
Specifications ................................................................................. 5-22
5.4.13
Assembly Differences .................................................................... 5-22
5.5
VRD (VITAL RELAY DRIVER) BOARD, P/N 59473-740 .......................... 5-24
5.5.1
General .......................................................................................... 5-24
5.5.2
Physical Characteristics ................................................................. 5-24
5.5.3
Operating Characteristics ............................................................... 5-25
5.5.4
Interface Connections .................................................................... 5-27
5.5.5
Specifications ................................................................................. 5-27
5.6
VSC (VITAL SERIAL CONTROLLER) BOARD, P/N 59473-939 .............. 5-28
5.6.1
General .......................................................................................... 5-28
5.6.2
Communication Process ................................................................ 5-30
5.6.3
Memory Types ............................................................................... 5-31
5.6.4
Indicators ....................................................................................... 5-31
5.6.5
Communication Interfaces ............................................................. 5-31
5.6.6
Direct Wire Interface ...................................................................... 5-32
5.6.7
Data Communications Interface ..................................................... 5-35
5.6.8
Interface Connections .................................................................... 5-36
5.6.9
Assembly Differences for 59473-939 ............................................. 5-42
5.6.10
Allowable VSC/CSEX Board Combinations ................................... 5-48
5.7
CODE RATE GENERATOR (CRG) BOARD, P/N 31166-261 .................. 5-51
5.7.1
General .......................................................................................... 5-51
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TABLE OF CONTENTS
Topic
Page
5.7.2
Physical.......................................................................................... 5-52
5.7.3
Electrical Ratings ........................................................................... 5-52
5.7.4
Outputs .......................................................................................... 5-53
5.7.5
Communications ............................................................................ 5-55
5.7.6
Environmental ................................................................................ 5-56
5.7.7
Assembly Differences for 31166-261 ............................................. 5-56
5.8
IOB (I/O BUS INTERFACE) BOARD, P/N 59473-827 .............................. 5-57
5.8.1
General .......................................................................................... 5-57
5.8.2
Vital Continuous Output Verification (50 ms Recheck Cycle)......... 5-59
5.8.3
Interface Connections .................................................................... 5-60
5.8.4
Specifications ................................................................................. 5-60
5.9
DI (DIRECT INPUT) BOARDS, P/N 59473-867........................................ 5-61
5.9.1
General .......................................................................................... 5-61
5.9.2
Operating Example ........................................................................ 5-63
5.9.3
Interface Connections .................................................................... 5-63
5.9.4
Specifications / Assembly Differences ........................................... 5-64
5.10
VITAL DC OUTPUT BOARDS, P/N 59473-739, -747, -977, -749 ............ 5-65
5.10.1
General .......................................................................................... 5-65
5.10.2
Interface Connections .................................................................... 5-69
5.10.3
SBO Board ..................................................................................... 5-70
5.10.3.1
SBO Specifications ................................................................ 5-70
5.10.3.2
Assemblies ............................................................................. 5-71
5.10.3.3
Test Points ............................................................................. 5-71
5.10.4
DBO and DBO-50V Board ............................................................. 5-72
5.10.4.1
DBO and DBO-50V Specifications ......................................... 5-73
5.10.4.2
Assemblies ............................................................................. 5-74
5.10.4.3
DBO and DBO-50V Board Test Points................................... 5-74
5.10.5
LDO Board ..................................................................................... 5-75
5.10.5.1
LDO Specifications................................................................. 5-76
5.10.5.2
Assemblies ............................................................................. 5-77
5.10.5.3
Test Points ............................................................................. 5-77
5.10.6
LDO2 Board ................................................................................... 5-78
5.10.6.1
LDO2 Specifications............................................................... 5-79
5.10.6.2
Assemblies ............................................................................. 5-80
5.10.6.3
LDO2 Board Test Points ........................................................ 5-80
5.11
ACO (VITAL AC OUTPUT) BOARD, P/N 59473-937 ............................... 5-81
5.11.1
General .......................................................................................... 5-81
5.11.2
Jumper Configurations ................................................................... 5-83
5.11.3
Transient Protection ....................................................................... 5-83
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TABLE OF CONTENTS
Topic
Page
5.11.4
Specifications ................................................................................. 5-84
5.11.5
Assembly ....................................................................................... 5-86
5.11.6
Test Points ..................................................................................... 5-86
5.12
(FSVT) FIELD-SETTABLE VITAL TIMER BOARDS, P/N 59473748, -894................................................................................................... 5-87
5.12.1
General .......................................................................................... 5-87
5.12.2
Interface Connections .................................................................... 5-89
5.12.3
Specifications ................................................................................. 5-90
SECTION 6 – NON-VITAL PRINTED CIRCUIT BOARDS ........................................... 6-1
6.1
CSE (CODE SYSTEM EMULATOR) BOARD, P/N 59473-741 .................. 6-4
6.1.1
General ............................................................................................ 6-4
6.1.2
Interface Connections ...................................................................... 6-7
6.1.3
Specifications ................................................................................... 6-7
6.1.4
Assembly Differences ...................................................................... 6-7
6.2
CSEX1 (CODE SYSTEM EMULATOR EXTENDED) BOARD, P/N
59473-938................................................................................................... 6-8
6.2.1
General ............................................................................................ 6-8
6.2.2
Communications Types.................................................................. 6-10
6.2.3
Interface Connections .................................................................... 6-11
6.2.4
CSEX1 Board Jumpers .................................................................. 6-13
6.2.5
Specifications ................................................................................. 6-14
6.3
CSEX3 (CODE SYSTEM EMULATOR EXTENDED 3) BOARD,
P/N 31166-175.......................................................................................... 6-15
6.3.1
General .......................................................................................... 6-15
6.3.2
Features ......................................................................................... 6-15
6.3.3
Test Points ..................................................................................... 6-17
6.3.4
Jumpers ......................................................................................... 6-17
6.3.5
LEDs .............................................................................................. 6-19
6.3.6
Serial Ports .................................................................................... 6-20
6.3.7
Diagnostic Display and Switch ....................................................... 6-26
6.3.8
Troubleshooting Guide ................................................................... 6-28
6.3.9
Specifications ................................................................................. 6-29
6.3.10
Assembly Differences .................................................................... 6-29
6.4
NVI (NON-VITAL INPUT) BOARD, P/N 59473-757 .................................. 6-30
6.4.1
General .......................................................................................... 6-30
6.4.2
Isolated Inputs ................................................................................ 6-30
6.4.3
Diagnostic Aids .............................................................................. 6-30
6.4.4
Interface Connections .................................................................... 6-31
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TABLE OF CONTENTS
Topic
Page
6.4.5
Specifications/Assembly Differences ............................................. 6-31
6.5
NVID (NON-VITAL INPUT DIFFERENTIAL) BOARD, P/N 31166106 ............................................................................................................ 6-32
6.5.1
General .......................................................................................... 6-32
6.5.2
Jumper Selection ........................................................................... 6-33
6.5.3
Specifications ................................................................................. 6-34
6.6
NVIDSW (NON-VITAL INPUT DIFFERENTIAL SWITCH) BOARD,
P/N 31166-276.......................................................................................... 6-35
6.6.1
General .......................................................................................... 6-35
6.6.2
Jumper Selection ........................................................................... 6-36
6.6.3
Specifications ................................................................................. 6-36
6.7
NVO (NON-VITAL OUTPUT) BOARDS, P/N 59473-785-, 59473936 ............................................................................................................ 6-37
6.7.1
General .......................................................................................... 6-37
6.7.2
Isolated Outputs ............................................................................. 6-37
6.7.3
Diagnostic Aids .............................................................................. 6-38
6.7.4
Specifications/Assembly Differences ............................................. 6-39
6.8
NVO-SNK (NON-VITAL OUTPUT SINK) BOARD, P/N 31166-123 .......... 6-41
6.8.1
General .......................................................................................... 6-41
6.8.2
Diagnostic Aids .............................................................................. 6-42
6.8.3
Specifications ................................................................................. 6-42
6.9
NVRELAY (NON-VITAL RELAY OUTPUT) BOARD, P/N 31166238 ............................................................................................................ 6-43
6.9.1
General .......................................................................................... 6-43
6.9.2
Isolated Outputs ............................................................................. 6-44
6.9.3
Diagnostic Aids .............................................................................. 6-49
6.9.4
Specifications ................................................................................. 6-50
6.9.5
Assembly Differences .................................................................... 6-50
6.10
TWCMAIN (TRAIN-TO-WAYSIDE COMMUNICATIONS MAIN)
MODEM BOARD, P/N 59473-996 ............................................................ 6-51
6.10.1
General .......................................................................................... 6-51
6.10.2
System Limitations ......................................................................... 6-52
6.10.3
Assembly Differences .................................................................... 6-52
6.11
TWCAUX (TRAIN-TO-WAYSIDE COMMUNICATIONS
AUXILIARY) BOARD, P/N 59473-995 ...................................................... 6-53
6.11.1
General .......................................................................................... 6-53
6.11.2
Assembly Differences .................................................................... 6-53
6.12
TWCATT (TRAIN-TO-WAYSIDE COMMUNICATIONS
ATTENUATOR) BOARD, P/N 31166-021................................................. 6-54
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TABLE OF CONTENTS
Topic
Page
6.12.1
General .......................................................................................... 6-54
6.12.2
Assembly Differences .................................................................... 6-54
6.13
NVTWC-MOD (NON-VITAL TWC MODEM) BOARD, P/N 31166099 ............................................................................................................ 6-55
6.13.1
General .......................................................................................... 6-55
6.13.2
Specifications/Assembly Differences ............................................. 6-56
6.14
NVTWC-MUX (NON-VITAL TWC MULTIPLEXER) BOARD, P/N
31166-100................................................................................................. 6-57
6.14.1
General .......................................................................................... 6-57
6.14.2
Specifications ................................................................................. 6-58
6.15
NVTWC-FSK (NON-VITAL TWC FSK) BOARD, P/N 31166-119 ............. 6-59
6.15.1
General .......................................................................................... 6-59
6.15.2
Specifications/Assembly Differences ............................................. 6-60
SECTION 7 – VPI CHASSIS ........................................................................................ 7-1
7.1
GENERAL................................................................................................... 7-1
7.2
SYSTEM MODULES (31038-249-00, 31038-274)...................................... 7-1
7.2.1
Plug Coupler Chassis....................................................................... 7-1
7.2.2
Edge Wired Chassis......................................................................... 7-2
7.2.3
Back Plane Interface Card (BPIC).................................................... 7-3
7.3
INTERCONNECTIONS............................................................................... 7-4
7.4
CABLE AND BACK PLANE CONNECTORS.............................................. 7-6
7.5
POWER SUPPLY ....................................................................................... 7-9
7.6
MISCELLANEOUS ................................................................................... 7-10
7.6.1
VRD Relay ..................................................................................... 7-11
7.7
BACK PLANE INTERFACE CARDS (BPIC) ............................................. 7-12
SECTION 8 – MAINTENANCE .................................................................................. 8-23
8.1
GENERAL................................................................................................. 8-23
8.1.1
Service Log .................................................................................... 8-23
8.1.2
Spare Parts .................................................................................... 8-24
8.1.3
Test Equipment .............................................................................. 8-25
8.1.4
Preventive Maintenance ................................................................. 8-26
8.2
BASIC DIAGNOSTIC FLOWCHART ........................................................ 8-28
8.3
VITAL SYSTEM DIAGNOSTICS AVAILABLE ON THE CPU/PD
BOARD ..................................................................................................... 8-31
8.3.1
Use of Handheld Terminal (HHT), Diagnostics Terminal and
the CSEX VDP ............................................................................... 8-31
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TABLE OF CONTENTS
Topic
Page
8.3.2
Top Level Vital Status Messages ................................................... 8-33
8.3.3
HHT Keyboard Command Summary.............................................. 8-34
8.3.4
Vital Diagnostic Charts ................................................................... 8-36
8.4
TROUBLESHOOTING WITH LEDS ......................................................... 8-45
8.5
NON-VITAL SYSTEM DIAGNOSTICS AVAILABLE ON THE CSEX
BOARD ..................................................................................................... 8-50
8.5.1
Operational Overview..................................................................... 8-50
8.5.2
Using Menus .................................................................................. 8-52
8.5.3
Menu Structure............................................................................... 8-53
8.5.4
CSEX Main Menu........................................................................... 8-55
8.5.5
Emulation Menu ............................................................................. 8-58
8.5.5.1
Emulation Menu Choice: Port ................................................ 8-60
8.5.5.2
Emulation Menu Choice: Next or Last .................................... 8-61
8.5.5.3
Emulation Menu Choice: Optns ............................................. 8-63
8.5.5.4
Emulation Menu Choice: Msg ................................................ 8-64
8.5.5.5
Emulation/Message Sub-Menu Choice: Post ......................... 8-65
8.5.5.6
Emulation/Message Sub-Menu Choice: Disp ......................... 8-66
8.5.5.7
Emulation/Message Sub-Menu Choice: Spcl ......................... 8-67
8.5.5.8
Emulation/Message Sub-Menu Choice: Mode ....................... 8-68
8.5.6
Emulation Diagnostics Menu .......................................................... 8-71
8.5.7
Monitor Menu ................................................................................. 8-73
8.5.8
System Configuration Information .................................................. 8-77
8.5.9
System Diagnostics Menu .............................................................. 8-78
8.6
EMBEDDED DATALOGGER (DL) ............................................................ 8-86
8.6.1
General Information ....................................................................... 8-86
8.6.2
Real-Time Clock............................................................................. 8-86
8.6.3
Memory Usage ............................................................................... 8-87
8.6.4
Directory Frames............................................................................ 8-88
8.6.5
Log Frames .................................................................................... 8-88
8.6.6
Logging Capacity ........................................................................... 8-89
8.6.7
Data Protection .............................................................................. 8-89
8.6.8
Log Area Reclamation.................................................................... 8-90
8.6.9
System Overloading ....................................................................... 8-90
8.7
TRACKER ANALYZER ............................................................................. 8-91
8.7.1
General Information ....................................................................... 8-91
8.7.2
System Overview ........................................................................... 8-91
8.8
BOARD REPLACEMENT ......................................................................... 8-93
8.8.1
Signature PROM ............................................................................ 8-93
8.8.2
Signature Headers ......................................................................... 8-94
P2086B, Volume 1, Rev. D, Nov/13
viii
Alstom Signaling Inc.
TABLE OF CONTENTS
Topic
Page
8.8.3
Field-Settable Vital Timer ............................................................... 8-94
8.8.4
Board Replacement Procedures .................................................... 8-94
8.8.5
Vital Boards .................................................................................... 8-95
8.8.5.1
CPU Board, P/N 59473-742-00 .............................................. 8-95
8.8.5.2
PD Board P/N 59473-737-00 ................................................. 8-97
8.8.5.3
CPU/PD Board P/N 31166-029-00 ......................................... 8-98
8.8.5.4
Vital Relay Driver Board, P/N 59473-740-00.......................... 8-99
8.8.5.5
Vital Serial Controller Board, P/N 59473-939-00 .................. 8-100
8.8.5.6
Code Rate Generator Board, P/N 31166-261-00 ................. 8-101
8.8.5.7
I/O Bus Interface Board, P/N 59473-827-00 ........................ 8-102
8.8.5.8
Vital Input Board, P/N 59473-867-00 ................................... 8-103
8.8.5.9
Vital Output Boards,
P/N 59473-739, -747, -749, -937, -977-00 ........................... 8-104
8.8.5.10
Field-Settable Vital Timer Board, P/N 59473-894-00 ........... 8-105
8.8.6
Non-Vital Boards .......................................................................... 8-106
8.8.6.1
Code System Emulator – CSE Board, P/N 59473-74100 ......................................................................................... 8-106
8.8.6.2
Code System Emulator Extended – CSEX1 Board, P/N
59473-938-00 ....................................................................... 8-107
8.8.6.3
Code System Emulator Extended 3 – CSEX3 Board,
P/N 31166-175-00 ................................................................ 8-108
8.8.6.4
Non-Vital Input Board, P/N 59473-757-00............................ 8-116
8.8.6.5
Non-Vital Input Differential Board, P/N 31166-106-00.......... 8-117
8.8.6.6
Non-Vital Input Differential Switch Board, P/N 31166276-00 .................................................................................. 8-118
8.8.6.7
Non-Vital Output Boards, P/N 59473-785, -936-00 and
31166-123-00 ....................................................................... 8-119
8.8.6.8
Non-Vital Output Relay Board, P/N 31166-238-00 ............... 8-120
8.8.6.9
Non-Vital TWC Main Board, P/N 59473-996-00 ................... 8-121
8.8.6.10
Non-Vital TWC Auxiliary Board, P/N 59473-995-00 ............. 8-122
8.8.6.11
Non-Vital TWC Attenuator Board, P/N 31166-021-00 .......... 8-123
8.8.6.12
Non-Vital TWC Modem Board, P/N 31166-099-00 .............. 8-124
8.8.6.13
Non-Vital TWC Multiplexer Board, P/N 31166-100-00 ......... 8-125
8.8.6.14
Non-Vital TWC FSK Board, P/N 31166-119-00 ................... 8-126
8.9
PROCEDURE TO VERIFY VPI BOARD FUNCTIONALITY ................... 8-127
8.9.1
I/O Interface Board ....................................................................... 8-127
8.9.2
Vital Input Boards ......................................................................... 8-127
8.9.3
Vital Output Boards ...................................................................... 8-128
8.9.4
Field-Settable Vital Timer Board .................................................. 8-128
P2086B, Volume 1, Rev. D, Nov/13
ix
Alstom Signaling Inc.
TABLE OF CONTENTS
Topic
Page
SECTION 9 – BOARD REFERENCE DATA............................................................... 9–1
9.1
GENERAL.................................................................................................. 9–1
9.2
LED LOCATION AND DEFINITION ........................................................... 9–1
9.2.1
CPU Board LED Indications, P/N 59473-742 .................................. 9–1
9.2.2
PD Board LED Indications, P/N 59473-737 .................................... 9–2
9.2.3
CPU/PD Board LED Indications, P/N 31166-029 ............................ 9–3
9.2.4
VRD Board LED Indications, P/N 59473-740 .................................. 9–4
9.2.5
VSC Board LED Indications, P/N 59473-939 .................................. 9–5
9.2.6
I/OB Board LED Indications, P/N 59473-827 .................................. 9–6
9.2.7
CRG Board LED Indications, P/N 31166-261 ................................. 9–7
9.2.8
DI Board LED Indications, P/N 59473-738, 59473-867 ................... 9–8
9.2.9
SBO, DBO, DBO-50V, LDO, ACO Board LED Indications,
P/N 59473-739, 59473-747, 59473-977, 59473-749, 59473937 .................................................................................................. 9–9
9.2.10
FSVT Board LED Indications, P/N 59473-894 .............................. 9–10
9.2.11
CSE Board LED Indications, P/N 59473-741 ................................ 9–11
9.2.12
CSEX1 Board LED Indications, P/N 59473-938 ............................ 9–12
9.2.13
CSEX3 Board LED Indications, P/N 31166-175 ............................ 9–13
9.2.14
NVI Board LED Indications, P/N 59473-757 ................................. 9–14
9.2.15
NVID and NVIDSW Board LED Indications, P/N 31166-106
and 31166-276 .............................................................................. 9–15
9.2.16
NVO, NVOAC and NVO-SNK Board LED Indications
P/N 59473-785, 59473-936, 31166-123 ........................................ 9–16
9.2.17
NVORELAY Board LED Indications, P/N 31166-238 .................... 9–17
9.2.18
NVTWC-MOD Board LED Indications, P/N 31166-099 ................. 9–18
9.2.19
NVTWC-FSK Board LED Indications, P/N 31166-119 .................. 9–19
9.2.20
NVTWC-MUX Board LED Indications, P/N 31166-100 ................. 9–20
9.3
BOARD LAYOUT ..................................................................................... 9–21
9.3.1
CPU Board, P/N 59473-742-00 ..................................................... 9–21
9.3.2
PD Board, P/N 59473-737-00 ....................................................... 9–23
9.3.3
CPU/PD Board, P/N 31166-029-00 ............................................... 9–24
9.3.4
VRD Board, P/N 59473-740-00 ..................................................... 9–27
9.3.5
VSC Board, P/N 59473 939-00 ..................................................... 9–29
9.3.6
VSC Board, P/N 59473-939-00 with T1 Adapter Board
Layout ........................................................................................... 9–30
9.3.7
CRG Board, P/N 31166-261-00 .................................................... 9–36
9.3.8
I/OB Board, P/N 59473-827-00 ..................................................... 9–37
9.3.9
DI Board, P/N 59473-867-00 ......................................................... 9–38
9.3.10
SBO Board, P/N 59473-739-00 ..................................................... 9–39
P2086B, Volume 1, Rev. D, Nov/13
x
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TABLE OF CONTENTS
Topic
Page
9.3.11
9.3.12
9.3.13
9.3.14
9.3.15
9.3.16
9.3.17
9.3.18
9.3.19
9.3.20
9.3.21
9.3.22
9.3.23
9.3.24
9.3.25
9.3.26
9.3.27
9.3.28
9.3.29
9.3.30
9.3.31
9.3.32
9.3.33
9.3.34
9.3.35
9.3.36
9.3.37
9.3.38
DBO Board, P/N 59473-747-00..................................................... 9–40
DBO-50V Board, P/N 59473-977-00 ............................................. 9–41
LDO Board, P/N 59473-749-00 ..................................................... 9–42
ACO Board, P/N 59473-937-00..................................................... 9–43
FSVT Board, P/N 59473-894-00 ................................................... 9–44
CSE Board, P/N 59473-741-00 ..................................................... 9–46
CSEX1 Board, P/N 59473-938-00................................................. 9–47
CSEX3 Board, P/N 31166-175-00................................................. 9–48
NVI Board, P/N 59473-757-00 ...................................................... 9–49
NVID Board, P/N 31166-106-00 .................................................... 9–50
NVIDSW Board, P/N 31166-276-00 .............................................. 9–51
NVO Board, P/N 59473-785-00..................................................... 9–52
NVOAC Board, P/N 59473-936-00................................................ 9–53
NVO-SNK Board, P/N 31166-123-00 ............................................ 9–54
NVORELAY Board, P/N 31166-238-00 ......................................... 9–55
TWCMAIN Board, P/N 59473-996-00 ........................................... 9–56
TWCAUX Board, P/N 59473-995-00 ............................................. 9–57
TWCATT Board, P/N 31166-021-00 ............................................. 9–58
NVTWC-MOD Board, P/N 31166-099-00 ...................................... 9–59
NVTWC-MUX Board, P/N 31166-100-00 ...................................... 9–60
NVTWC-FSK Board, P/N 31166-119-00 ....................................... 9–61
BPIC CPU/PD Board, P/N 31166-336-00 ..................................... 9–62
BPIC Vital Output Board, P/N 31166-194-00 ................................ 9–63
BPIC Vital Input Board, P/N 31166-195-00 ................................... 9–64
BPIC Non-Vital I/O Board, P/N 31166-196-00 .............................. 9–65
BPIC Vital Relay / Power Board, P/N 31166-197-00 ..................... 9–66
BPIC Vital Serial Controller Board, P/N 31166-198-00 ................. 9–67
BPIC Communications Board, P/N 31166-199-00 ........................ 9–68
APPENDIX A – GLOSSARY ...................................................................................... A–1
A.1
COMMON ABBREVIATIONS ................................................................... A–1
APPENDIX B – VPI CAPACITY GUIDELINES .......................................................... B–1
B.1
CAPACITY OVERVIEW............................................................................ B–1
B.2
HARDWARE CRITERIA ........................................................................... B–1
B.2.1
Vital Boards .................................................................................... B–1
B.2.2
Non-Vital Boards ............................................................................ B–2
B.2.3
Application Criteria ......................................................................... B–3
APPENDIX C – MODULE WIRING AND SPECIAL TOOLS ..................................... C–1
P2086B, Volume 1, Rev. D, Nov/13
xi
Alstom Signaling Inc.
TABLE OF CONTENTS
Topic
Page
APPENDIX D – ALSTOM VPI APPLICATION DESIGN AND TEST POLICY ........... D–1
APPENDIX E – CIRCUIT BOARD KEYING ............................................................... E–1
APPENDIX F – SIGNATURE HEADERS AND PROMS ............................................. F–1
APPENDIX G – ALLOWABLE VSC/CSEX BOARD COMBINATIONS..................... G–1
APPENDIX H – CRG APPLICATION GUIDELINES .................................................. H–1
H.1
GENERAL OVERVIEW ............................................................................ H–1
H.2
APPLICATION PARAMETERS ................................................................ H–1
H.3
CPU/PD TO CRG PARAMETERS ............................................................ H–2
H.4
INSTALLATION AND OPERATION .......................................................... H–3
H.5
CPU/PD REQUIREMENTS ...................................................................... H–3
H.6
TERMINAL BLOCK CONFIGURATION.................................................... H–3
H.7
DISPLAYS AND DIAGNOSTICS .............................................................. H–4
P2086B, Volume 1, Rev. D, Nov/13
xii
Alstom Signaling Inc.
LIST OF FIGURES
Figure No.
Title
Figure 1-1.
Typical Wayside Devices Under VPI Control ................................... 1-2
Figure 2-1.
Figure 2-2.
Figure 2-3.
Typical Rack Mount Installation........................................................ 2-3
Typical Module Rear Panel Wiring with Plug Coupled
Chassis ............................................................................................ 2-4
Alstom Handheld Terminal ............................................................. 2-10
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Typical VPI System Configuration .................................................... 4-2
Functional Logic Flow....................................................................... 4-3
Vital Input Check Circuit ................................................................... 4-4
Boolean Expression Example (Switch Lock) .................................... 4-6
Absence-Of-Current Detector Circuit ............................................... 4-9
CSEX Diagnostic Connection......................................................... 4-12
VPI Boards Grouped by Vital and Non-Vital Functions .................. 4-14
Typical Board Placement for Single Chassis VPI System .............. 4-15
Typical VPI Module Chassis........................................................... 4-16
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
Figure 5-15.
Figure 5-16.
Figure 5-17.
Figure 5-18.
Figure 5-19.
Figure 5-20.
Figure 5-21.
Figure 5-22.
Figure 5-23.
Figure 5-24.
Vital and Non-Vital Subsystems ....................................................... 5-1
CPU Board Block Diagram ............................................................... 5-6
PD (Polynomial Divider) Board Block Diagram .............................. 5-13
CPU/PD Board Block Diagram ....................................................... 5-16
CPU/PD Board Jumper Locations .................................................. 5-23
VRD Board Block Diagram ............................................................. 5-26
The Effect of Manchester Encoding on NRZ Data ......................... 5-32
VSC Link Cable and Shield Connections ....................................... 5-34
VSC board DIP Switch S1 .............................................................. 5-38
VSC Board DIP Switch S2 ............................................................. 5-39
VSC Board DIP Switch S4 ............................................................. 5-40
Daughterboard Current vs Voltage ................................................. 5-43
VSC Board LED Indications ........................................................... 5-44
VSC Board Layout ......................................................................... 5-45
VSC Board with Daughter Board Installed ..................................... 5-46
31166-058-01 VSC Daughterboard ................................................ 5-47
VPI CRG Block Diagram ................................................................ 5-51
Output Circuit Solid State Relay Driver .......................................... 5-53
Output Circuit B-Relay Driver ......................................................... 5-54
I/OB (I/O Bus Interface) Board Block Diagram ............................... 5-58
DI (Direct Input) Board Block Diagram ........................................... 5-62
Vital Output Board Block Diagram .................................................. 5-69
SBO Block Diagram ....................................................................... 5-70
DBO Block Diagram ....................................................................... 5-72
P2086B, Volume 1, Rev. D, Nov/13
Page
xiii
Alstom Signaling Inc.
LIST OF FIGURES
Figure No.
Title
Figure 5-25.
Figure 5-26.
Figure 5-27.
Figure 5-28.
Figure 5-29.
Figure 5-30.
LDO Block Diagram ....................................................................... 5-75
LDO2 Port Interface ....................................................................... 5-78
ACO (Vital AC Output) Board Block Diagram................................. 5-82
ACO Block Diagram ....................................................................... 5-84
FSVT Timer Setting Examples ....................................................... 5-88
FSVT (Field-Settable Vital Timer) Board Block Diagram ................ 5-91
Figure 6-1.
Figure 6-2.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 6-10.
Figure 6-11.
CSE (Code System Emulator) Block Diagram ................................. 6-4
CSEX1 (Code System Emulator eXtended) Board Block
Diagram.......................................................................................... 6-10
CSEX3 (Code System Emulator eXtended 3) Board Block
Diagram.......................................................................................... 6-16
CSEX3 Board Indicators, Test Point Connectors and
Switches (Card Edge View)............................................................ 6-24
NVI (Non-Vital Input) Board Block Diagram ................................... 6-31
NVO (Non-Vital Output) Board Block Diagram ............................... 6-38
NVRELAY (Non-Vital Relay Output) Board Block Diagram ............ 6-45
TWC Main Modem Board Block Diagram....................................... 6-51
NVTWC-MOD Subsystem Block Diagram...................................... 6-55
NVTWC-MUX Subsystem Block Diagram ...................................... 6-57
NVTWC-FSK Subsystem Block Diagram ....................................... 6-59
Figure 8-1.
Figure 8-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-3.
Figure 8-3.
Figure 8-3.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-8.
Figure 8-9.
Figure 8-10.
Figure 8-11.
Figure 8-12.
General Diagnostic Flowchart (Sheet 1 of 3).................................. 8-28
General Diagnostic Flowchart (Sheet 2 of 3).................................. 8-29
General Diagnostic Flowchart (Sheet 3 of 3).................................. 8-30
Diagnosis With Handheld Terminal ................................................ 8-31
LED Troubleshooting Sequence (Sheet 1 of 5) .............................. 8-45
LED Troubleshooting Sequence (Sheet 2 of 5) .............................. 8-46
LED Troubleshooting Sequence (Sheet 3 of 5) .............................. 8-47
LED Troubleshooting Sequence (Sheet 4 of 5) .............................. 8-48
LED Troubleshooting Sequence (Sheet 5 of 5) .............................. 8-49
Connection to the CSEX MAC Port ................................................ 8-50
Menu Tree ...................................................................................... 8-54
CSEX Main Menu ........................................................................... 8-55
Emulation Menu ............................................................................. 8-58
Emulation Menu – Select the Serial Port ........................................ 8-60
Emulation Menu – View a Station’s Messages............................... 8-61
Emulation Menu – View Port Setup ................................................ 8-63
Emulation Menu – Message Sub-Menu ......................................... 8-64
Post a Control Message ................................................................. 8-65
Figure 6-3.
Figure 6-4.
P2086B, Volume 1, Rev. D, Nov/13
Page
xiv
Alstom Signaling Inc.
LIST OF FIGURES
Figure No.
Title
Figure 8-13.
Figure 8-14.
Figure 8-15.
Figure 8-16.
Figure 8-17.
Figure 8-18.
Figure 8-19.
Figure 8-20.
Figure 8-21.
Figure 8-22.
Figure 8-23.
Figure 8-24.
Display Messages in Real-Time ..................................................... 8-66
Post a Special Message ................................................................. 8-67
Select the Message Display Mode ................................................. 8-68
Display Messages – New Hex Display Option ............................... 8-70
Display Messages – Binary Display Option .................................... 8-70
DataTrain VIII Diagnostics Menu.................................................... 8-71
DataTrain VIII Counts Screen ........................................................ 8-72
Data Monitor Screen ...................................................................... 8-73
CenTraCode II System Configuration Screen ................................ 8-77
CenTraCode II System Diagnostics Menu ..................................... 8-78
DataLogger Memory Usage ........................................................... 8-87
Typical System Using Tracker Software......................................... 8-91
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 9-7.
Figure 9-8.
Figure 9-9.
CPU Board LED Indications, P/N 59473-742 .................................. 9–1
PD Board LED Indications, P/N 59473-737..................................... 9–2
CPU/PD Board LED Indications, P/N 31166-029 ............................ 9–3
VRD Board LED Indications, P/N 59473-740 .................................. 9–4
VSC Board LED Indications, P/N 59473-939 .................................. 9–5
I/OB Board LED Indications, P/N 59473-827 .................................. 9–6
CRG Board LED Indications, P/N 31166-261.................................. 9–7
DI Board LED Indications, P/N 59473-738, 59473-867 ................... 9–8
SBO, DBO, DBO-50V, LDO, ACO Board LED Indications
P/N 59473-739, 59473-747, 59473-977, 59473-749, 59473937 .................................................................................................. 9–9
FSVT Board LED Indications, P/N 59473-894 .............................. 9–10
CSE Board LED Indications, P/N 59473-741 ................................ 9–11
CSEX1 Board LED Indications, P/N 59473-938 ............................ 9–12
CSEX3 Board LED Indications, P/N 31166-175 ............................ 9–13
NVI Board LED Indications, P/N 59473-757.................................. 9–14
NVID and NVIDSW Board LED Indications P/N 31166-106
and 31166-276 .............................................................................. 9–15
NVO, NVOAC and NVO-SNK Board LED Indications P/N
59473-785, 59473-936, 31166-123 ............................................... 9–16
NVORELAY Board LED Indications, P/N 31166-238 .................... 9–17
NVTWC-MOD Board LED Indications, P/N 31166-099 ................. 9–18
NVTWC-FSK Board LED Indications, P/N 31166-119 .................. 9–19
NVTWC-MUX Board LED Indications, P/N 31166-100 ................. 9–20
CPU Board, P/N 59473-742-00 ..................................................... 9–21
CPU Board DIP Switch Settings.................................................... 9–22
PD Board, P/N 59473-737-00 ....................................................... 9–23
Figure 9-10.
Figure 9-11.
Figure 9-12.
Figure 9-13.
Figure 9-14.
Figure 9-15.
Figure 9-16.
Figure 9-17.
Figure 9-18.
Figure 9-19.
Figure 9-20.
Figure 9-21.
Figure 9-22.
Figure 9-23.
P2086B, Volume 1, Rev. D, Nov/13
Page
xv
Alstom Signaling Inc.
LIST OF FIGURES
Figure No.
Title
Figure 9-24.
Figure 9-25.
Figure 9-26.
Figure 9-27.
Figure 9-28.
Figure 9-29.
CPU/PD Board, P/N 31166-029-00 ............................................... 9–24
CPU/PD Board DIP Switch S2 Settings ........................................ 9–25
VRD Board, P/N 59473-740-00 ..................................................... 9–27
VRD Board SW1 Switch Setting.................................................... 9–28
VSC Board, P/N 59473 939-00 ..................................................... 9–29
VSC Board, P/N 59473-939-00 with T1 Adapter Board
Layout ........................................................................................... 9–30
VSC Board DIP Switch S1 Settings .............................................. 9–31
VSC Board DIP Switch S2 Settings .............................................. 9–32
VSC Board DIP Switch S4 Settings .............................................. 9–33
31166-058-01 Daughterboard ....................................................... 9–35
CRG Board, P/N 31166-261-00 .................................................... 9–36
I/OB Board, P/N 59473-827-00 ..................................................... 9–37
DI Board, P/N 59473-867-00 ......................................................... 9–38
SBO Board, P/N 59473-739-00 ..................................................... 9–39
DBO Board, P/N 59473-747-00..................................................... 9–40
DBO-50V Board, P/N 59473-977-00 ............................................. 9–41
LDO Board, P/N 59473-749-00 ..................................................... 9–42
ACO Board, P/N 59473-937-00..................................................... 9–43
FSVT Board, P/N 59473-894-00 ................................................... 9–44
Timer Setting Example .................................................................. 9–45
CSE Board, P/N 59473-741-00 ..................................................... 9–46
CSEX1 Board, P/N 59473-938-00................................................. 9–47
CSEX3 Board, P/N 31166-175-00................................................. 9–48
NVI Board, P/N 59473-757-00 ...................................................... 9–49
NVID Board, P/N 31166-106-00 .................................................... 9–50
NVIDSW Board, P/N 31166-276-00 .............................................. 9–51
NVO Board, P/N 59473-785-00..................................................... 9–52
NVOAC Board, P/N 59473-936-00................................................ 9–53
NVO-SNK Board, P/N 31166-123-00 ............................................ 9–54
NVORELAY Board, P/N 31166-238-00 ......................................... 9–55
TWCMAIN Board, P/N 59473-996-00 ........................................... 9–56
TWCAUX Board, P/N 59473-995-00 ............................................. 9–57
TWCATT Board, P/N 31166-021-00 ............................................. 9–58
NVTWC-MOD Board, P/N 31166-099-00 ...................................... 9–59
NVTWC-MUX Board, P/N 31166-100-00 ...................................... 9–60
NVTWC-FSK Board, P/N 31166-119-00 ....................................... 9–61
BPIC CPU/PD Board, P/N 31166-336-00...................................... 9–62
BPIC Vital Output Board, P/N 31166-194-00 ................................ 9–63
BPIC Vital Input Board, P/N 31166-195-00 ................................... 9–64
Figure 9-30.
Figure 9-31.
Figure 9-32.
Figure 9-33.
Figure 9-34.
Figure 9-35.
Figure 9-36.
Figure 9-37.
Figure 9-38.
Figure 9-39.
Figure 9-40.
Figure 9-41.
Figure 9-42.
Figure 9-43.
Figure 9-44.
Figure 9-45.
Figure 9-46.
Figure 9-47.
Figure 9-48.
Figure 9-49.
Figure 9-50.
Figure 9-51.
Figure 9-52.
Figure 9-53.
Figure 9-54.
Figure 9-55.
Figure 9-56.
Figure 9-57.
Figure 9-58.
Figure 9-59.
Figure 9-60.
Figure 9-61.
Figure 9-62.
P2086B, Volume 1, Rev. D, Nov/13
Page
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Alstom Signaling Inc.
LIST OF FIGURES
Figure No.
Title
Figure 9-63.
Figure 9-64.
Figure 9-65.
Figure 9-66.
BPIC Non-Vital I/O Board, P/N 31166-196-00............................... 9–65
BPIC Vital Relay / Power Board, P/N 31166-197-00 ..................... 9–66
BPIC Vital Serial Controller Board, P/N 31166-198-00 ................. 9–67
BPIC Communications Board, P/N 31166-199-00. ....................... 9–68
Figure C–1.
Figure C–2.
Figure C–3.
Figure C–4.
Direct Wiring Option on Rear Plane of VPI Module ........................ C–1
Terminal Crimp Tool ....................................................................... C–2
Terminal Extraction Tools............................................................... C–2
Pin and Socket Extraction Tool ...................................................... C–3
Figure E-1.
Figure E-2.
Figure F–5.
Registration Keying of Circuit Board ............................................... E–1
Registration Keying Numbering....................................................... E–2
Selectable Signature PROM Assembly ........................................... F–3
P2086B, Volume 1, Rev. D, Nov/13
Page
xvii
Alstom Signaling Inc.
LIST OF TABLES
Table No.
Title
Table 1–1.
Table 1–2.
Related Publications List .................................................................. 1-3
VPI Specifications ............................................................................ 1-4
Table 2–1.
Logic Configuration Log Sheet for CPU Board Assembly
59473-742-xx ................................................................................... 2-8
Logic Configuration Log Sheet for CPU/PD Board Assembly,
31166-029-xx ................................................................................... 2-9
Table 2–2.
Page
Table 4–1.
Table 4–2.
System Bus Interface Connections ................................................ 4-17
Motherboard Interface Connections (Vital and Non-Vital) .............. 4-18
Table 5–1.
Table 5–2.
Table 5–3.
Table 5–4.
Table 5–5.
Table 5–6.
Table 5–7.
Table 5–8.
Table 5–9.
Table 5–10.
Table 5–11.
Table 5–12.
Table 5–13.
Table 5–14.
Table 5–15.
Table 5–16.
Table 5–17.
Table 5–18.
Table 5–19.
Table 5–20.
Table 5–21.
Table 5–22.
Table 5–23.
Table 5–24.
Table 5–25.
Table 5–26.
Table 5–27.
Table 5–28.
Table 5–29.
Table 5–30.
Vital PC Boards Index ...................................................................... 5-2
CPU Board Bus Command Signals.................................................. 5-8
Central Processing Unit (CPU) Specifications................................ 5-11
CPU Assembly Differences ............................................................ 5-11
Polynomial Divider (PD) Specifications .......................................... 5-14
CPU/PD Board Jumpers ................................................................ 5-21
CPU/PD Specifications................................................................... 5-22
CPU/PD Assembly Differences ...................................................... 5-22
Vital Relay Driver Specifications .................................................... 5-27
VSC Connector Assignments ......................................................... 5-36
VSC Board DIP Switch S1 Functions ............................................. 5-38
VSC Board DIP Switch S2 Functions ............................................. 5-39
VSC S4 Miscellaneous Functions .................................................. 5-40
Line Termination Jumpers for Copper Pair Interface ...................... 5-41
VSC Assembly Differences ............................................................ 5-42
Allowable VSC & CSEX Board Combinations ................................ 5-48
Allowable VSC Board Quantities by Type ...................................... 5-50
CRG Communications Specifications ............................................ 5-55
CRG Assembly Differences............................................................ 5-56
I/O Bus Interface Specifications ..................................................... 5-60
Direct Input Specifications/Assembly Differences .......................... 5-64
Single Break Output Specifications ................................................ 5-70
Single Break Output Board Assembly Differences ......................... 5-71
SBO Board Test Points .................................................................. 5-71
DBO/DBO-50 Board Specifications ................................................ 5-73
DBO Board Assemblies.................................................................. 5-74
DBO Board Test Points .................................................................. 5-74
DBO-50V Board Test Points .......................................................... 5-74
LDO Board Specifications .............................................................. 5-76
LDO Board Assemblies .................................................................. 5-77
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
LIST OF TABLES
Table No.
Title
Table 5–31.
Table 5–32.
Table 5–33.
Table 5–34.
Table 5–35.
Table 5–36.
Table 5–37.
Table 5–38.
LDO Board Test Points .................................................................. 5-77
LDO2 Board Specifications ............................................................ 5-79
LDO2 Board Assemblies ................................................................ 5-80
LDO2 Board Test Points ................................................................ 5-80
AC Outputs Specifications/Assembly Differences .......................... 5-84
ACO Board Assembly .................................................................... 5-86
ACO Board Test Points .................................................................. 5-86
Field-Settable Vital Timer Specifications/Assembly
Differences ..................................................................................... 5-90
Table 6–1.
Table 6–2.
Table 6–3.
Table 6–4.
Table 6–5.
Table 6–6.
Table 6–7.
Table 6–8.
Table 6–9.
Table 6–10.
Table 6–11.
Table 6–12.
Non-Vital Printed Circuit Boards Index ............................................. 6-1
Code System Emulator Specifications ............................................. 6-7
CSE Assembly Differences .............................................................. 6-7
CSEX1 External I/O Connector Assignments................................. 6-11
Extended Code System Emulator Specifications ........................... 6-14
CSEX3 Test Points ........................................................................ 6-17
CSEX3 Battery Selection Jumper .................................................. 6-17
CSEX3 Watchdog Selection Jumper .............................................. 6-17
CSEX3 MAC Port Power Selection Jumper ................................... 6-18
CSEX3 Jumper Assignments Reserved for Future Use ................. 6-18
CSEX3 LED Descriptions ............................................................... 6-19
CSEX3 Channel 1 Communication Standard Selection
Switch Setting ................................................................................ 6-20
CSEX3 Channel 2 Communication Standard Selection
Switch Setting ................................................................................ 6-20
CSEX3 Port 2 DC Code Line Communication Selection
Switch Setting ................................................................................ 6-20
CSEX3 MAC Port Connector Pin Assignments .............................. 6-21
CSEX3 MAC Port RXD Source Selection Switch Setting ............... 6-21
CSEX3 36-pin P3 Connections (with P/N 31166-058) ................... 6-22
CSEX3 36-pin P3 Auxiliary Board Communication Selection
Switch (SW1) ................................................................................. 6-25
CSEX3 36-pin P3 Auxiliary Board CSEX1 vs. ..... CSEX3 Switch (SW2)
Use the CSEX3 Diagnostic Display and Switch ............................. 6-27
CSEX3 Troubleshooting Guide ...................................................... 6-28
CSEX3 Assembly Differences ........................................................ 6-29
Non-Vital Inputs Specifications....................................................... 6-31
Non-Vital Input Differential Jumper Selection ................................. 6-33
Non-Vital Input Differential Specifications ...................................... 6-34
Non-Vital Input Differential Jumper Selection ................................. 6-36
Table 6–13.
Table 6–14.
Table 6–15.
Table 6–16.
Table 6–17.
Table 6–18.
Table 6–19.
Table 6–20.
Table 6–21.
Table 6–22.
Table 6–23.
Table 6–24.
Table 6–25.
Table 6–26.
P2086B, Volume 1, Rev. D, Nov/13
Page
xix
Alstom Signaling Inc.
LIST OF TABLES
Table No.
Title
Table 6–27.
Table 6–28.
Table 6–29.
Table 6–30.
Table 6–31.
Table 6–32.
Table 6–33.
Table 6–34.
Table 6–35.
Table 6–36.
Table 6–37.
Table 6–38.
Table 6–39.
Table 6–40.
Table 6–41.
Non-Vital Input Differential Switch Specifications ........................... 6-36
Non-Vital DC Outputs (NVO) Specifications................................... 6-39
Non-Vital AC Outputs (NVOAC) Specifications .............................. 6-40
Non-Vital Output Sink (NVO-SNK) Specifications .......................... 6-42
NVRELAY P1 Connections ............................................................ 6-46
NVRELAY P3 Connections ............................................................ 6-48
NVRELAY Test Points.................................................................... 6-49
Non-Vital Relay Output (NVR) Specifications................................. 6-50
NVR Assembly Differences ............................................................ 6-50
TWCMAIN Assembly Differences .................................................. 6-52
TWCAUX Assembly Differences .................................................... 6-53
TWCATT Assembly Differences..................................................... 6-54
Non-Vital TWC Modem (NVTWC-MOD) Specifications ................. 6-56
Non-Vital TWC Multiplexer (NVTWC-MUX) Specifications ............ 6-58
Non-Vital TWC Multiplexer (NVTWC-FSK) Specifications ............. 6-60
Table 7–1.
Table 7–2.
Table 7–3.
Table 7–4.
Table 7–5.
Table 7–6.
Table 7–7.
Table 7–8.
Table 7–9.
Table 7–10.
Table 7–11.
Table 7–12.
Table 7–13.
Table 7–14.
Table 7–15.
Table 7–16.
Table 7–17.
Table 7–18.
Table 7–19.
Table 7–20.
Table 7–21.
Table 7–22.
Table 7–23.
Ribbon Cables.................................................................................. 7-5
38216-392 Cable Complete ............................................................. 7-6
38216-393 Cable Complete ............................................................. 7-7
38216-394 Cable Complete ............................................................. 7-7
38216-497 Cable Complete ............................................................. 7-7
Plug coupler mating connectors (AMP Type ‘M’) ............................. 7-8
Ribbon Cable Part Numbers ............................................................ 7-8
Melcher DC-DC Converters ............................................................. 7-9
Miscellaneous Components ........................................................... 7-10
Vital Output (31166-194-01) I/O Pin Map ....................................... 7-12
Vital Input (31166-195-01) I/O Pin Map .......................................... 7-13
Non-Vital Input (31166-196-01) I/O Pin Map .................................. 7-14
VRD/5VDC Power (31166-197-01) Pin Interface ........................... 7-16
VSC Modular Jack (31166-198-01) Pin Map .................................. 7-16
VSC EIA422 (31166-198-01) Pin Map ........................................... 7-17
Terminal Block Setting (31166-198-01) .......................................... 7-17
VSC EIA232 (31166-198-01) Pin Map ........................................... 7-17
VSC Isolated Power (31166-198-01) Pin Map ............................... 7-17
4 Track Genrakode Interface (31166-198-01) Pin Map .................. 7-18
Communications (31166-199-01) Connector Types....................... 7-18
Serial Port 1 (31166-199-01) Pin Map ............................................ 7-19
Serial Port 2 (31166-199-01) Pin Map ............................................ 7-20
Port 2 DC Code Line (31166-199-01) Pin Map .............................. 7-20
P2086B, Volume 1, Rev. D, Nov/13
Page
xx
Alstom Signaling Inc.
LIST OF TABLES
Table No.
Title
Table 7–24.
Serial Port 3, 4, 5 and 6 (31166-199-01) Pin Map .......................... 7-21
Table 8–1.
Table 8–2.
Table 8–3.
CPU/PD HHT Port Cable ............................................................... 8-32
Troubleshooting Chart: Start-up Diagnostics.................................. 8-37
Troubleshooting Chart: Diagnostics During System
Operation ....................................................................................... 8-40
CSEX1 Current Loop...................................................................... 8-51
CSEX3 EIA232............................................................................... 8-51
CenTraCode II Main Menu Choices ............................................... 8-56
Emulation Menu Choices ............................................................... 8-59
Hexadecimal to Binary Conversion ................................................ 8-62
Message Display Modes ................................................................ 8-69
Monitor Menu Choices ................................................................... 8-74
Data Monitor Status Indicators ....................................................... 8-75
Message Descriptors...................................................................... 8-76
System Diagnostic Menu Choices.................................................. 8-79
Secondary Diagnostics Menu Choices ........................................... 8-81
System Errors ................................................................................ 8-83
CPU Board Replacement ............................................................... 8-95
PD Board Replacement.................................................................. 8-97
CPU/PD Board Replacement ......................................................... 8-98
Vital Relay Driver Board Replacement ........................................... 8-99
Vital Serial Controller Board Replacement ................................... 8-100
Code Rate Generator Board Replacement .................................. 8-101
I/O Bus Interface Board Replacement .......................................... 8-102
Vital Input Board Replacement..................................................... 8-103
Vital Output Board Replacement .................................................. 8-104
Field-Settable Vital Timer Board Replacement ............................ 8-105
Code System Emulator Board Replacement ................................ 8-106
CSEE 1 Board Replacement ........................................................ 8-107
CSEX3 Board Replacement Procedure ....................................... 8-108
CSEX3 Board Configuration Jumpers .......................................... 8-114
CSEX3 Board Configuration Switches ......................................... 8-115
Non-Vital Input Board Replacement ............................................. 8-116
Non-Vital Input Differential Board Replacement ........................... 8-117
Non-Vital Input Differential Switch Board Replacement ............... 8-118
Non-Vital Output Board Replacement .......................................... 8-119
Non-Vital Output Board Replacement .......................................... 8-120
Non-Vital TWC Main Board Replacement .................................... 8-121
Non-Vital TWC Auxiliary Board Replacement .............................. 8-122
Table 8–4.
Table 8–5.
Table 8–6.
Table 8–7.
Table 8–8.
Table 8–9.
Table 8–10.
Table 8–11.
Table 8–12.
Table 8–13.
Table 8–14.
Table 8–15.
Table 8–16.
Table 8–17.
Table 8–18.
Table 8–19.
Table 8–20.
Table 8–21.
Table 8–22.
Table 8–23.
Table 8–24.
Table 8–25.
Table 8–26.
Table 8–27.
Table 8–28.
Table 8–29.
Table 8–30.
Table 8–31.
Table 8–32.
Table 8–33.
Table 8–34.
Table 8–35.
Table 8–36.
Table 8–37.
P2086B, Volume 1, Rev. D, Nov/13
Page
xxi
Alstom Signaling Inc.
LIST OF TABLES
Table No.
Title
Table 8–38.
Table 8–39.
Table 8–40.
Table 8–41.
Table 8–42.
Table 8–43.
Table 8–44.
Table 8–45.
Non-Vital TWC Attenuator Board Replacement ........................... 8-123
Non-Vital TWC Modem Board Replacement ................................ 8-124
Non-Vital TWC Multiplexer Board Replacement .......................... 8-125
Non-Vital TWC FSK Board Replacement ..................................... 8-126
I/O Interface Board Functionality Verification ............................... 8-127
Vital Input Board Functionality Verification ................................... 8-127
Vital Output Board Functionality Verification ................................ 8-128
Field-Settable Vital Timer Board Functionality Verification ........... 8-128
Table 9–1.
Table 9–2.
Table 9–3.
Table 9–4.
Table 9–5.
Table 9–6.
Table 9–7.
CPU Board Switch 2 (SW2) Normal Functions ............................. 9–22
SW2 DIP Switch Settings .............................................................. 9–25
MAC Port Rear and Front Wiring .................................................. 9–26
VSC Board DIP Switch S1 Settings .............................................. 9–31
VSC Board DIP Switch S2 Settings .............................................. 9–32
Line Termination Jumpers for Copper Pair Interface ..................... 9–33
VSC S4 Miscellaneous Function Settings ..................................... 9–34
Table A–1.
Table B–1.
Table B–2.
Table B–3.
Glossary .......................................................................................... A–1
VPI Vital Board Limitations .............................................................. B–1
VPI Non-Vital Board Limitations ...................................................... B–2
VPI Application Criteria ................................................................... B–3
Table E–1.
Vital and Non-Vital PC Board Keying Information ........................... E–3
Table F–1.
Table F–2.
Address Signature Headers ............................................................ F–1
Signature PROMs ........................................................................... F–2
Table G–1.
Board Placement Rules.................................................................. G–1
Table H–1.
Table H–2.
Table H–3.
CPU/PD to CRG Parameters ......................................................... H–2
CRG to CPU/PD Parameters ......................................................... H–2
CRG Board Display and Diagnostics ............................................. H–4
P2086B, Volume 1, Rev. D, Nov/13
Page
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Alstom Signaling Inc.
Introduction
SECTION 1 – INTRODUCTION
1.1
SCOPE OF MANUAL
This document contains a general description of the Alstom VPI® Vital Processor
Interlocking Control System. It contains basic system level information, technical
hardware descriptions, maintenance, and troubleshooting instructions.
The technical material in this manual assumes the reader has a basic knowledge of
railroad signaling terminology, digital electronics, and basic computer software
principles. Courses are available for the user that requires additional training. Contact
an Alstom representative for details.
1.2
TERMS, ABBREVIATIONS AND TRADE NAMES
Terms and abbreviations used throughout this manual are defined in Appendix A. Refer
to Appendix A anytime a term or abbreviation in the text is unfamiliar.
CenTraCode®, cTc®, Safety Assurance Logic™, Tracker™ and VPI® are registered trade
names of Alstom Signaling Inc.
1.3
VPI SYSTEM FEATURES
The VPI module is a Vital fail-safe, microprocessor-based control system designed to
meet the needs of interlocking control for mainline railroads and mass transit
applications.
Versatility is the hallmark of the VPI system. Designed as a modular control system, it
contains a set of plug-in Printed Circuit Boards (PCB) that are applied in varying
quantities to meet the needs of a specific location. Although one VPI system is sufficient
for many installations, additional systems in distributed arrangements can be added for
more complex sites (and/or to provide redundant operation).
The VPI system is fully compatible with the majority of equipment found at interlockings.
Figure 1-1 shows how a control center, through the DC code line/communications
system, interfaces with more than one Vital interlocking and shows the ancillary features
that can be added to the basic VPI system. In addition, other viable ways of
communication from the Central Control are via microwave, radio, and fiber optic links.
Note that in Figure 1-1 as well as in the rest of this manual, references to the CPU/PD
circuit board also apply to the CPU circuit board unless otherwise noted. In a similar
manner, references to the CSEX circuit board refer to CSEX1 and CSEX3 circuit boards
unless otherwise noted.
P2086B, Volume 1, Rev. D, Nov/13
1-1
Alstom Signaling Inc.
Introduction
Figure 1-1 shows some examples of equipment commonly operated under VPI control.
Figure 1-1. Typical Wayside Devices Under VPI Control
The VPI system can be mounted in a small wayside equipment shelter. No special
heating or cooling equipment is required for operation in AAR-specified temperature
environments (-40 to +70ºC). Built-in secondary transient protection is provided for all
I/O lines to prevent disruption of service from EMI or other local interference. If required,
additional primary protection devices can be added to the external lines to protect
against higher level EMI such as pulses from nearby electrical storms.
Inputs to the VPI system are identical to older, Vital relay-based systems. No relays are
used in the solid state module, thereby eliminating the need for periodic maintenance or
adjustments. With VPI, complex relay logic is reduced to a closed set of Boolean
mathematical expressions or expressed as Relay Logic Diagrams that represent
standard relay contact closures. Then, through Alstom’s Computer-Aided Application
Programming Environment (CAAPE) software package, these Boolean expressions are
converted into operating instructions for the VPI microprocessor.
P2086B, Volume 1, Rev. D, Nov/13
1-2
Alstom Signaling Inc.
Introduction
1.4
RELATED PUBLICATIONS
Several publications comprise the present collection of manuals covering the VPI
system as shown below. Other code/communication system publications shall be added
to this list as they become available.
Table 1–1. Related Publications List
Publication Number
P2086B:
Title
Vol. 1
VPI Installation, Operation, and Maintenance
Vol. 2
Vital Printed Circuit Board and Schematics
Vol. 3
Non-Vital Printed Circuit Boards and Schematics
Vol. 4
Modules, Cables and Other
P2086G
VPI Product Overview
P2307
Tracker™ Diagnostic Analyzer Software User Guide
P2326D
DataLogger, An Event Recorder Utility for CenTraCode
Systems
P2346
Series: Code/Communication System Publications:
P2346A
LCE Protocol Emulation
P2346B
S2 Protocol Emulation
P2346C
K/K2 Protocol Emulation
P2346D
DataTrain IV Protocol Emulation
P2346E
DataTrain VIII Protocol Emulation
P2346F
Genisys Protocol Emulation
P2346G
US&S 504/506/514 Emulation
P2346H
Safetran SCS-128 Protocol Emulation
P2346M
Modicon Modbus Protocol Emulation
P2346N
DataTrain II Protocol Emulation
P2346P
Rockwell ARES Protocol Emulation
P2346Q
CN2000 Protocol Emulation
P2346R
MCS1 Protocol Emulation
P2346S
J Code Protocol Emulation
P2346T
WMATA RTU Protocol Emulation
P2346U
ATCS Protocol Emulation
P2346V
WMATA NVTWC Hardware, Software, Diagnostics
P2346W
Vital Diagnostic Protocol (VDP)
P2086B, Volume 1, Rev. D, Nov/13
1-3
Alstom Signaling Inc.
Introduction
1.5
SPECIFICATIONS
Table 1–2 lists nominal specifications for the VPI module. Additional module information
is found in Section 7.
Table 1–2. VPI Specifications
Characteristic
Specification
Logic Input Power
5 ±0.25 VDC at 8 amperes
maximum per module
High Voltage Isolation Rating
Meets AAR requirements
Operating Temperature
-40 to +160ºF
(-40 to +70ºC)
Humidity
0 to 95% Non-Condensing
Typical Weight per Module with some boards
15 lbs. (6.80 kg)
Dimensions
14H × 19W × 23D inches
(35.56H × 48.26W × 35.56D cm)
1.6
DIAGNOSTICS
Four levels of diagnostic support exist for troubleshooting a VPI system. These levels
are as follows for remote and local testing.
1. LEDs on circuit boards for visual operating checks.
2. Handheld Terminal for Vital System diagnostics.
3. Properly equipped terminal for Non-Vital System diagnostics.
4. Tracker™ Remote Diagnostic Analyzer software for Non-Vital diagnostics from field
and/or office to any number of remote locations, or useful at a field location.
P2086B, Volume 1, Rev. D, Nov/13
1-4
Alstom Signaling Inc.
Installation and Setup
SECTION 2 – INSTALLATION AND SETUP
2.1
INTRODUCTION
Use the information in this section to install and configure the software of the VPI
system for regular service. Initial checkout procedures are given at the end of the
section to verify proper system performance.
The VPI system is supplied as part of a packaged, pre-assembled, control system that
is mounted in a rack frame. The installation instructions for a stand-alone device, in the
event the VPI module is added to an existing system or is used to replace a damaged
unit, are included in this section.
WARNING
Disruption of Vital controller service poses a potential threat to rail safety.
Before shutting down a facility for any reason, notify the railroad dispatcher in
charge of the affected route(s). Take all steps necessary to ensure the safe
passage of traffic is maintained.
2.2
UNPACKING AND INSPECTION
Carefully open the shipping carton and check the contents against the packing list
secured to the outside of the container. Accessories and spare parts kits are wrapped
separately. Take careful note of all small hardware shipped with the units. Inspect all
items for signs of damage. Save all packing material for possible re-shipment.
P2086B, Volume 1, Rev. D, Nov/13
2-1
Alstom Signaling Inc.
Installation and Setup
2.3
MOUNTING PROCEDURES
Each VPI installation differs slightly depending on the type of rack enclosure used and
the types of equipment to be controlled. While it is impossible to anticipate all mounting
configurations, the general procedures given below serve as a guide for typical
systems. Refer to the rack mount illustration shown in Figure 2-1 for these procedures.
Step
Procedure
1
Install (if required) clip-on nuts at the rack holes to be used for VPI module
mounting.
2
Position the VPI module in the rack, lining up the front panel holes on the VPI
module with the mounting holes/nuts in the rack frame. Secure the module to
the rack with screws as shown.
3
Connect the VPI ground wire.
4
Connect all rear panel cables (if applicable) as required by the system plans
(see Figure 2-2 for an example). Tighten the retaining screws or clips (if so
equipped) on the cable plugs to secure them to the VPI rear panel. Dress all
cabling in accordance with the system plans.
5
Note that some VPI racks may have either 18 or 32 VAC heavy-duty surge
protectors mounted on a panel to handle unwanted line surges.
2.4
PRE-POWER-UP CHECKS
Once the equipment is mounted, and before application of power, perform the following
checks:
Step
Procedure
1
Check power supplies, batteries or chargers used in conjunction with the VPI
system for adherence to operating specifications.
The VPI logic power supply, if other than provided by Alstom, should be 5
VDC (± 0.25V, 1% ripple) and must meet AAR isolation requirements, as
found in AAR Specification Section 11.5.1.
2
Verify VRD relay and repeaters are securely fastened to the relay plugboards.
The system will not operate if this is not done.
3
Check all output wiring for shorts to avoid possible damage to the system
outputs. Check all power connections for the correct voltage and polarity.
4
Lower the VPI front cover plate and verify that all plug-in Printed Circuit
Boards are firmly seated in the correct slots.
5
Verify that Signature PROM and Signature Headers are in place and in proper
order per module arrangement plan.
P2086B, Volume 1, Rev. D, Nov/13
2-2
Alstom Signaling Inc.
Installation and Setup
19" RACK
5V
LOGIC
POWER
SUPPLY
VRD
RELAY
VPI®
MAIN
MODULE
ALSTOM
VPI
EIA
MOUNTING
ALSTOM
VPI
VPI®
EXTENSION
MODULE
(If Required)
MODEM
Figure 2-1. Typical Rack Mount Installation
P2086B, Volume 1, Rev. D, Nov/13
2-3
Alstom Signaling Inc.
Installation and Setup
60 Way
Extender
Cable
VPI Module
Power
Coupler
I/O Bus
Motherboard
- Plug CouplersVital and Non- Vital
Connects with
Relays, Relay Contact,
etc.
Printed
Circuit
Board
Cable
Ribbon Cable
(System Bus or Expansion
Bus)
Figure 2-2. Typical Module Rear Panel Wiring with Plug Coupled Chassis
P2086B, Volume 1, Rev. D, Nov/13
2-4
Alstom Signaling Inc.
Installation and Setup
2.5
SOFTWARE CONFIGURATION
Before the VPI module can be activated, the interlocking logic must be configured to
meet the needs of the particular installation. This is accomplished using an IBM or
compatible PC with Alstom’s Computer-Aided Applications Programming Environment
(CAAPE) software. The CAAPE software is used to program the VPI's plug-in EPROM
chips. For instructions on using the CAAPE package, refer to the CAAPE’s on-line help.
While the VPI Vital system software is common to all installations, the application data
software, which describes the logical operation of a specific interlocking, needs to be
customized for each location. These Boolean equations or Relay Logic Diagrams are
written by the Application or Signal Engineer using the CAAPE software in conjunction
with traditional tools such as a track plan and aspect charts. These equations may also
be written as a direct interpretation of existing relay logic circuits. After the equations
have been written, the logic can then be tested and loaded into EPROM.
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Alstom Signaling Inc.
Installation and Setup
2.6
RECORDING OF SYSTEM CONFIGURATION DATA
Whenever a new or modified VPI system is put into service, the system configuration
data should be recorded using the “.CFG” report generated by the CAAPE. This
provides a means to verify that the CAAPE instructions exactly match the EPROM
contents residing on the Vital system boards. Although not strictly required, it is
recommended that during other (non-VPI) periodic maintenance programs that the VPI
logic configuration be re-recorded and verified against the installed/in service
configuration data. This ensures that the on-site documentation reflects current
configuration and has been kept up to date. EPROM contents are accessed by using a
Handheld Terminal (HHT) or the Alstom Tracker Remote Diagnostic Analyzer software
as described later in this document. Use Table 2–1 / Table 2–2 (shown in this section)
to log configuration data. The table may be locally reproduced as needed.
2.6.1
Handheld Terminal
A Handheld Terminal (HHT) is typically used for field diagnostic analysis of Vital
systems. It connects directly to the VPI CPU or CPU/PD board via a short cable and
plug assembly. The Handheld Terminal is packaged in a 1-inch high Lexan® case. HHT
diagnostic commands and VPI responses are presented to the user on an LCD display
as shown in Figure 2-3. Handheld Terminals are available for use with either a current
loop interface for CPU boards or an RS-232 interface for a CPU/PD board (see Section
8, Maintenance, for a complete reference of the use of the HHT). To view Logic
Configuration Data, the HHT can access the EPROM contents using the REPORT (R)
feature. Open the VPI module front cover and connect the HHT to the CPU or CPU/PD
HHT connector. Next, press “R” and then “CR”. Memory signatures can be accessed
using the QUERY (Q) command.
2.6.2
General Diagnostics
With the Handheld Terminal connected to the CPU or CPU/PD board, apply VPI system
power and observe the display on the HHT or the Tracker Analyzer screen. If operation
is correct, “SYSTEM OK” is displayed and the VRD relay energizes after several
seconds. If connections to system inputs or outputs are open or intermittent, the “SYS
WARNING” message may be observed. This type of failure may still allow the VRD
relay to energize. Should a major fault be detected, the display will read “ERROR
ALERT”. The VRD relay remains de-energized in such cases. If the VRD relay remains
de-energized and no display message is shown, verify that the application memory has
been properly configured and installed on the CPU or CPU/PD and that the Handheld
Terminal is properly connected. If the failure persists, replace the CPU or CPU/PD
board. If an “ERROR ALERT” or “SYS WARNING” display is shown, refer to Section 8,
Maintenance, for in-depth troubleshooting procedures.
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Alstom Signaling Inc.
Installation and Setup
2.6.3
Vital Diagnostic Protocol (VDP)
Through the use of Alstom’s optional Vital Diagnostic Protocol (VDP), a user may view
CPU/PD board status and perform CPU/PD diagnostic commands when connected to
the non-vital CSEX board’s Maintenance Access (MAC) port. Refer to Alstom
publication P2346W and Section 8, Maintenance, for more detail on the VDP.
2.6.4
Tracker Remote Diagnostic Analyzer Software
The Alstom Tracker Remote Diagnostic Analyzer software utility may also be used to
view configuration information in a manner very similar to the Handheld Terminal.
Besides local connection, the Tracker software can also be operated remotely using a
data modem. A brief explanation of the Tracker Analyzer Software is provided in
Section 8, Maintenance. For more detailed information refer to Alstom Publication
P2307.
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Alstom Signaling Inc.
Installation and Setup
SOFTWARE CONFIGURATION DATA LOG
Name of Person Performing System Query:
Location of System
System Description ( e.g. SYSTEM 1 or
MAIN SYSTEM or application name ):
IN SERVICE Date:
Current Date:
Following “R” Command
INPUT FILE #:
CAAPE FILE #:
VRS FILE #:
INPUT FILE NUMBER
RUNTIME/DATE
VSC.VB1
VSC.VB2
VSC.VB3
VSC.VB4
Following "Q" Command
System Software Signature (@ADDR 174)
(base application EPROM) (@ADDR 178)
(shadow application EPROM) (@ADDR 17C)
Table 2–1. Logic Configuration Log Sheet for CPU Board Assembly 59473-742-xx
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Installation and Setup
SOFTWARE CONFIGURATION DATA LOG
Name of Person Performing System Query:
Location of System:
System Description ( e.g. SYSTEM 1 or
MAIN SYSTEM or application name ):
IN SERVICE Date:
Current Date:
Following “R” Command:
INPUT FILE #:
CAAPE FILE #:
VRS FILE #:
INPUT FILE NUMBER
RUNTIME/DATE
VRS FILE NUMBER
REVISION
VSC.VB1
VSC.VB2
VSC.VB3
VSC.VB4
VSC.VB5
VSC.VB6
VSC.VB7
VSC.VB8
VSC.VB9
VSC.VBA
CRG 1
CRG 2
CRG 3
Following "Q" Command:
System Software 1 Signature @ ADDR 174
System Software 2 Signature @ ADDR 23E
System Software 3 Signature @ ADDR 242
System Software 4 Signature @ ADDR 246
(Base application EPROM) (@ADDR 178)
(Shadow Application 1 EPROM) (@ADDR 17C))
(Shadow Application 2 EPROM) (@ADDR 24 A
(Shadow Application 3 EPROM) (@ADDR 24E)
Table 2–2. Logic Configuration Log Sheet for CPU/PD Board Assembly, 31166-029-xx
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Installation and Setup
SYSTEM WARNING
XPR RSLT ERR
ERROR ALERT
RCHK CWD ERR
F1
A
`
ESC
E
B TAB
BKSP
{
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/
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}
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]
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9
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#
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CR
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6
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4
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F3
BRK
1
*
LK
F2
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LF
Figure 2-3. Alstom Handheld Terminal
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Operation
SECTION 3 – OPERATION
3.1
INTRODUCTION
This section gives VPI in-service operating instructions for units that have been installed
and configured as described in Section 2.
3.2
START-UP PROCEDURE
The VPI system requires no warm-up period; it may be used immediately after being
turned on. Simply apply system power to the module to begin Vital controller operation.
The power switch is typically located on or near the rack cabinet.
3.3
OPERATING INSTRUCTIONS
The VPI system is designed for automatic, unattended field operation. Once power is
applied, operator actions are limited to infrequent, periodic observation to ensure that
proper interlocking operation is maintained. Included with many installations is an
indicator and control panel that can be used to observe and activate basic interlocking
functions. Also, the Alstom Tracker™ Remote Diagnostic Analyzer system can be used
to remotely (and continuously) monitor one or several VPI installations (refer to Alstom
publication P2307 for complete detail). When a problem is detected, an alarm sounds
and an on-screen description of the failure is presented.
3.4
OPERATING UNDER UNUSUAL CONDITIONS
The fail-safe design of the VPI system allows continued operation in the presence of
certain non-safety related faults. For instance, when a VPI module appears in the
WARNING box of the Tracker Analyzer main window (or “SYS WARNING” appears on
the Handheld Terminal display), it indicates an abnormal or out-of-tolerance condition
that has not caused a system shutdown. While continued operation may still be
possible, the problem should be checked and corrected to avoid a possible complete
system shutdown. Refer to Section 8, Maintenance, for troubleshooting details.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Operation
3.5
OPERATIONAL CHANGES
If it becomes necessary to make changes to the VPI control logic, authorized personnel
should refer to the Software Configuration procedures in Section 2, “Board
Replacement and Verification” in Section 8 and the Alstom VPI Application and Design
test policy in Appendix D.
3.6
SHUTDOWN PROCEDURE
WARNING
Disruption of Vital controller service poses a potential threat to rail safety.
Before shutting down a facility for any reason, notify the railroad dispatcher in
charge of the affected route(s). Take all steps necessary to ensure the safe
passage of traffic is maintained.
To shut down the VPI system, set the system power supply switches to the OFF
position. Power switches are typically located on or near the rack cabinet.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
SECTION 4 – THEORY OF OPERATION
4.1
INTRODUCTION
This section provides an overview of VPI system level functionality. All VPI boards (both
Vital and Non-Vital) reside in a VPI module. While the configuration of these modules
can take many forms, a common interconnection system is used. All VPI modules have
the following interconnection structure:
1. System Bus: P1 board connector (bottom connector)
2. I/O Bus Motherboard: P2 board connector (middle connector):
A. Vital I/O Bus
B. Non-Vital I/O Bus
3. Expansion Bus: P3 board connector (top connector)
Figure 4-1 illustrates a typical VPI system that contains both Vital and Non-Vital
elements and shows how they are interrelated (all four bus types are referenced in the
figure).
Section 4.2 discusses Vital System Operation (a complete reference to Vital Circuit
boards is provided in Section 5). Section 4.3 discusses Non-Vital System Operation (a
complete reference to Non-Vital Circuit boards is provided in Section 6). Finally Section
4.4 discusses the VPI Module including typical board placement (more details on
various Chassis configurations is available in Section 7) and bus interface pinouts.
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Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
4-2
(VSC)
CODE/COMM
LINE
INTERFACE
CODE/COMM LINE
VITAL
SERIAL
CONTROLLERS
(VSC)
SYSTEM &
APPLICATION
EPROMS
CODE SYSTEM
EMULATOR
(CSEX3)
SYSTEM &
APPLICATION
EPROMS
INTERLOCKING
LOGIC
EXPRESSION
EVALUATOR
POLYNOMIAL
DIVIDER
(CPU/PD)
**
*
***
VITAL
POWER
ENABLE
TWC
ANTENNA
TWC MUX
OR MODEM
BOARD
Non-vital
I/O Bus
(Motherboard)
NON-VITAL
COMMUNICATIONS LINK
TO OTHER CSEX BOARDS
TO FIELD
32 OUTPUTS /
BOARD
NON-VITAL
OUTPUTS
SUPPLY
VRDFRONT
FROM FIELD
32 INPUTS /
BOARD
NON-VITAL
INPUTS
VRD
'B' RELAY
RACK MOUNTED
(I/OB)
I/O
INTERFACE
P1
P2
P3
Vital I/0 Bus
(Motherboard)
OTHER
VITAL SERIAL
CONTROLLERS
(MVSC,GVSC)
MULTIDROP
VITAL SERIAL
CONTROLLERS
CODE
RATE
GENERATORS
(CRG)
SAFETY
SYSTEM
MONITOR
(VITAL RELAY
DRIVER)
Main CPU Bus
(Ribbon Cable)
System Bus
Expansion Bus
up to Three VPI Modules
VITAL
OUTPUT
BOARD
VITAL
INPUT
BOARD
VITAL
INPUT
BOARD
****
FRONT VIEW LEGEND
8 OUTPUTS / BOARD
SBO, DBO, LDO, ACO
VITAL
VITAL
OUTPUT
OUTPUT
BOARD
BOARD
***
VITAL
INPUT
BOARD
16 INPUTS / BOARD
8 TIMERS/BOARD
VITAL FIELD
SETTABLE
TIMER INPUTS
VITAL
OUTPUT
BOARD
VITAL
INPUT
BOARD
**
**
* ** Motherboard Address Wirewrap
*** Requires Signature Header
**** Requires Signature PROM
VITAL
APPARATUS
VITAL
APPARATUS
Theory of Operation
Figure 4-1. Typical VPI System Configuration
Alstom Signaling Inc.
Theory of Operation
4.2
VITAL SYSTEM OPERATION
To achieve fail-safe microprocessor-based interlockings, the VPI processing system
vitally determines that the inputs to the system are read correctly, that the equations are
evaluated correctly and that non-permissive outputs do not become permissive (Figure
4-2). Vital logic equations are written in Boolean form and are stored in the VPI EPROM
using Alstom’s Computer-Aided Applications Programming Environment (CAAPE)
software package. For details, refer to Alstom Publication P2512D or on-line manuals
provided with the CAAPE package.
Vital input and output hardware is used in conjunction with a processing system
controlled by safety software. Safety software is based on the principles of Safety
Assurance Logic, an Alstom design philosophy applied to all products using
microprocessors for Vital control. Additional techniques using Numerically Integrated
Safety Assurance Logic (NISAL) are used to provide Vital processing logic that is
compatible with the application-dependent logic required by the interlocking design.
VPI primary logic performs the task of logically controlling the interlocking. The NISAL is
integrated into the primary logic to prove that the intended tasks are performed correctly
and to prove that no output can wrongly assert (for any reason) a permissive state.
INPUT VITAL &
NON-VITAL DATA
OUTPUT VITAL &
NON-VITAL DATA
TRACK CIRCUIT OCCUPANCY
EVALUATE
SWITCH MACHINE CONTACTS
LOGIC
SIGNAL RELAY OR MECHANISM
EXPRESSIONS
CONTACTS
AND
TRAFFIC CIRCUIT STATUS
PERFORM
H-D LINE CIRCUITS
SAFETY
LOCAL CONTROL PANEL
CHECKS
INPUTS
SIGNAL MECHANISM DRIVE
SIGNAL FILAMENT DRIVE
SWITCH CONTROL
TRAFFIC CIRCUIT CONTROL
H-D LINE CIRCUIT
EMERGENCY PANEL
INDICATIONS
CODE SYSTEM INDICATIONS
CODE SYSTEM CONTROLS
HIGHWAY CROSSING CONTROL
FILAMENT CHECKS
WHEEL COUNTING
WHEEL COUNT INPUT
Figure 4-2. Functional Logic Flow
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Alstom Signaling Inc.
Theory of Operation
4.2.1
Vital Input Check Circuit
VPI operation is based on a 1-second input-evaluate-output cycle. That is, all inputs are
read, all equations are solved (using the read input values) and all outputs are updated
on the basis of the current evaluation.
Figure 4-3 shows a simplified diagram of the Vital input check circuit. Each input is
assigned a unique numerical value, or test word. During the input read process, this
word is transported to the input. The input circuit passes the word from the “data in” to
“data out” terminals if, and only if, there is energy applied to the field terminals. The
word returned to the CPU for an “on” (true) or permissive input is the inverse of the
serial word sent to the “data in” input. Any other word results in the input being
interpreted as “off” (false) or non-permissive. The read operation ensures that high
levels of induced AC on the field conductors will not be interpreted as a permissive
input.
B10
DATA
OUT
N10
DATA
IN
FIELD
Figure 4-3. Vital Input Check Circuit
The data returned to the CPU from each input is used in the expression (equation)
evaluation. The input is read a second time using a different data and the result of this
process is used to solve a diverse set of expressions.
Because the field terminals for each Vital input circuit are electrically isolated from each
other, each input is equivalent to a separate, isolated Vital relay coil. Where a bipolar
input function is required, two inputs may be interconnected in a “cross-coupled”
arrangement. There are board assembly variations to handle different physical interface
requirements.
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Alstom Signaling Inc.
Theory of Operation
4.2.2
Other Inputs
Vital serial input data (via the Vital Serial Controller board) as well as non-vital input and
code or communication system data via the Code System Emulator (CSE/CSEX) board
are obtained by the main processor once each second, and assigned true or false
values in both channels.
4.2.3
Vital Expression Evaluation
Each Boolean expression is processed twice using diverse data in two separate
processing channels. Each channel's result is unique. For example, in a switch lock
circuit (Figure 4-4) the Vital output corresponding to the 1LR expression becomes true
(energized) only if both channels’ results combine to form a true value. This requires
each of the three parameters to be true in both channels.
Expressions are evaluated by combining parameters mathematically using an algorithm
based on polynomial division. The data result produced by this process is such that the
correct values are only a small subset of possible values. They are different from other
results in many bits (hamming distance) and exhibit a particular bit weight by the
number of ones. This method produces a higher degree of security than does a simple
logic scheme (AND, OR, ADD, etc.). All equations are executed diversely once per
second and Vital precautions are taken to prevent skipping of expressions or evaluating
out-of-order equations. In the same equations below, a plus (+) sign means an OR
operation whereas a star (*) means an AND operation.
Using NISAL, VPI uses a single microprocessor and a single set of software in
combination with the system’s primary function, a configured control system operates in
a Vital manner without the need for redundant hardware or software. These concepts
make extensive use of diversity and cycle checking to implement a safe function.
Uniquely encoded checkwords are generated as a result of executing Vital processes
and permissive outputs are allowed only if the full complement of generated checkwords
are correct.
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Alstom Signaling Inc.
Theory of Operation
1
LSR
1
LR
1
NWCR
1
RWCR
BOOL 1LSR = [(1LR + 1LSR) * .N.1NWCR * .N.1RWCR]
OR
BOOL 1LSR = (1LR * .N.1NWCR * .N.1RWCR +1LSR * .N1NWCR * .N.1.RWCR)
1
LR
1
TPR
BOOL 1LR
1
WSR
1
ESR
= (1TPR * 1WSR * 1ESR)
Figure 4-4. Boolean Expression Example (Switch Lock)
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Alstom Signaling Inc.
Theory of Operation
4.2.4
Vital Checkwords
The VPI system has two classifications of Vital checkwords. The recheck checkword set
verifies the results from the state of all Vital outputs. The main checkword set verifies
system operation with respect to processing equations, reading Vital inputs, timing and
other internal operations.
The recheck checkword operates as follows. Every 50 ms, the state of each output is
checked by creating a checkword which should correspond to its evaluated result. If an
output is energized as a result of expression evaluation, then the true two-channel
expression value is included in the formation of a checkword. If the output expression
result is false, then a value returned from the Vital output check circuitry is used to
prove that the output is off. This returned value is a unique result formed in two
channels by circulating and compressing data continuously through the output check
circuit. This data is then used to form a recheck checkword.
The main checkwords are used to Vitally prove that the processes carried out by the
Vital main cycle software are executed properly. These checkwords are created once
per second.
Examples of Vital software processes follow:
Verification that all data used resulting in permissive outputs is current to that particular
cycle; all old data must be Vitally erased.
Verification that routines and application information reside in memory as designed and
are unaltered (signature analysis).
Verification that all functions requiring strict timing (one-second processing cycle, 50 ms
output recheck, Vital input timing, etc.) can be validated.
Memory buffers, which store system parameters, are erased each cycle by known
benign data constants. A combination of these data constants, along with buffer
address information, results in several of the main checkwords.
Signature analysis of routine and application memory proves the integrity of stored
PROM data. Signature analysis results in higher error detection than does a simple
checksum routine. The method of combining memory contents is similar to expression
evaluation where an algorithm of polynomial division is used. The system memory is
divided into blocks upon which a signature is found and used to create a main
checkword.
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Alstom Signaling Inc.
Theory of Operation
4.2.5
System Timing
An independently clocked reference timer performs most system timing and is separate
from the processor clock. The reference timer is read “on the fly” to determine system
timing. In addition, it is used to cause processor interrupts at pre-defined intervals (for
example, output check every 50 ms). Some checkwords are created based on timer
contents. All checkwords are provided to a Vital Relay Driver (VRD) board for
processing. Checkwords are only accepted once during a precise window that occurs in
50 ms intervals. If, and only if, all main and recheck checkwords are correct, delivered
on time and are correct for the proper cycle will Vital energy be supplied to the VPI Vital
outputs.
4.2.6
System Output Update
Results of the Vital expression evaluations set the Vital outputs to the evaluated states.
Once per second, all system outputs are updated. A set of independent checks is then
run to ensure that only those outputs that evaluated true are in the permissive state.
Output data for the Non-Vital outputs and the code/communication system indications
are sent to the CSE/CSEX board once every second. Vital serial output messages are
passed from the CPU/PD to the VSC boards at the end of expression processing in
each one-second cycle.
4.2.7
Electrical Isolation
The Vital output circuitry achieves the same isolation and safety obtained from a Vital
relay contact by maintaining physical separation between PC board traces and between
connector pins, and by using optoisolators, magnetic devices and other components
that meet and/or exceed AAR isolation requirements (see Section 5 for details on
specific Vital boards).
4.2.8
Absence-Of-Current Detector
A simplified version of an output circuit is shown in Figure 4-5. This circuitry proves the
output status using an Absence of Current Detector (AOCD). The AOCD senses the
current being delivered to the output load and if it is above a preset level (3 mA and 50
mA are typical depending on output type), the passage of a test word is blocked.
Therefore, the only time that the correct data can pass from the Test Word Data In to
the Test Word Data Out of the AOCD is if the current flow in the output is below the
preset level. This provides a fail-safe means of verifying that an “off” output is indeed in
the off state.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
VITAL OUTPUT
POWER SOURCE
ABSENCE- OF- CURRENT
DETECTOR
VITAL OUTPUT
TO WAYSIDE
TEST WORD
DATA IN
TEST WORD
DATA OUT
Figure 4-5. Absence-Of-Current Detector Circuit
The status of an output is positively known only when it is being checked. A unique
serial data stream (word) is repeatedly applied to each AOCD for greater than 95% of
each 50 ms recheck cycle. The resulting data from the AOCD is compressed in a shift
register. The purpose of this operation is to obtain a numerical value for each output
that is the mathematical equivalent of dividing the serial data stream by a primitive
polynomial. The correct result for an “off” (false) occurs if, and only if, the current in that
output is below the safe level for the entire check period. A unique numerical value is
produced by each output.
The processor uses these values to create checkwords and to maintain energy to the
outputs. Using this method, the VPI system can detect any output failure and Vitally
remove its power within a maximum of 140 ms (typically 100 ms).
4.2.9
Output Loads
There are many different types of output loads that the VPI system can drive. Different
circuitry, therefore, is used to suit each application. The VPI system can produce
outputs that are equivalent to a single-break relay circuit, a double-break relay circuit, a
lamp drive output and an AC output. The lamp drive output also includes circuitry for hot
and cold filament tests. If a bipolar output function is required, double break output
circuits may be interconnected in a cross-coupled arrangement.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
4.3
NON-VITAL SYSTEM OPERATION
The Non-Vital VPI contains a number of circuit board types. A brief description of the
boards used in the Non-Vital system is useful in understanding the integration of the
Non-Vital VPI into the overall ATC system. A detailed description of each of the boards
is found in section 6, Non-Vital Printed Boards Section.
4.3.1
Non-Vital Processing
The VPI boards designated as CSEX1 and CSEX3 provide multi-port serial
communications, along with Non-Vital logic capabilities. CSEX stands for Code System
Emulator eXtended, with each version of the CSEX board being an upgrade of the
previous board. The first board of this type, CSE (Code System Emulator) provided
communication only without the capability of non-vital logic processing. References to
the CSEX circuit board refer to CSEX1 and CSEX3 circuit boards unless otherwise
noted.
The CSEX board is the equivalent of the Central Processor Board of the Vital VPI
system and has its own separate processor to serve the non-vital system. The CSEX
board has serial data ports that allow it to directly interface with multiple communication
environments and it controls non-vital I/O boards. The Non-Vital VPI system can use
multiple CSEX boards in one system. This allows division of some of the functions
between boards, increasing system speed and capacity, while allowing a type of
redundancy to be available. Furthermore, the CSEX board can simultaneously support
multiple communication/code system protocols while performing non-vital application
logic functions.
4.3.2
Non-Vital TWC Communications
The NVTWC (Non-Vital Train-to-Wayside Communication) boards enable train-towayside and wayside-to-train messages as typically found in Automatic Transit
applications. These messages pass from Central through the VPI CSEX board, and
then on to the train through the NVTWC Modem board and external antennae.
Messages from the train to a Central Control can flow in the reverse direction. Also, the
transmission of messages to the train for loading train ID, dispatching, and door control
performance level are included. Various board assemblies exist for different physical
interfaces.
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Alstom Signaling Inc.
Theory of Operation
4.3.3
Non-Vital I/O
The Non-Vital Input (NVI) board is used to detect discrete Non-Vital inputs. Discrete
Non-Vital inputs are typically comprised of panel functions such as signal request,
switch request, as well as miscellaneous inputs such as power off, ground detection and
dwell timer program jumpers. For each of 32 inputs on a NVI board, an LED mounted
near the board edge is used to represent the input state from the field equipment.
Various board assemblies exist for different physical interfaces.
The Non-Vital Input Differential Switch (NVIDSW) board provides 32 isolated Non-Vital
inputs to a VPI system. Interface to the system is accomplished through the system
motherboard. Input states are latched and then read every 25 ms. The NVIDSW board
provides the ability to physically set the state of the inputs through 32 switches located
on the front of the board. The inputs can be forced ON, OFF or to the actual state of the
physical input.
The Non-Vital Output (NVO) boards in a VPI system are of two types, AC and DC. The
AC NVO boards typically provide the panel lighting functions. The DC output boards are
typically used to control panel lighting functions, to control other discrete Non-Vital
outputs, and to drive any Non-Vital relays that are required. Various board assemblies
exist for different physical interfaces.
The Non-Vital Relay Output (NVRELAY) board provides 32 Form A non-vital relays
interfaced through the system backplane to the connectors on the back of the module.
The NVRELAY board is functionally equivalent to its NVO predecessors, except for
power requirements, and the existence of the Field Programmable Gate Array (FPGA).
The outputs are grouped in four groups with eight outputs each, as on the NVO board,
but the outputs on the P1 and P3 connectors are assigned two pins each, an even and
an odd. If the output is currently active, these two pins will be connected through the
associated relay contact, allowing current flow.
P2086B, Volume 1, Rev. D, Nov/13
4-11
Alstom Signaling Inc.
Theory of Operation
4.3.4
Diagnostics for Non-Vital VPI
Several types of diagnostics are available for the Non-Vital VPI. As with Vital VPI
Printed Circuit Boards, edge mounted LEDs on each board give visual indications of
board status. Also available for use as a diagnostic tool is a menu-driven series of
diagnostic screens resident in the system software of the CSEX board and the NVTWC
Modem board. These screens are displayed on a VT100 video terminal connected to a
9-pin MAC (Maintenance ACcess) port on the boards. An alternative means of viewing
the diagnostics is through a PC with appropriate communications software capable of
emulating a terminal on a PC, see Figure 4-6. More information on Non-Vital board
LEDs and Non-Vital Diagnostics via the MAC port is provided in Section 8
VT100
or PC
RS-232 (CSEX2/CSEX3) or
current loop (CSEX1/CSEX2)
connection
MAC
port
CSEX
board
Figure 4-6. CSEX Diagnostic Connection
P2086B, Volume 1, Rev. D, Nov/13
4-12
Alstom Signaling Inc.
Theory of Operation
4.4
VPI MODULE
Figure 4-7 shows the types of PC boards typically found in the VPI module case. Slots
are provided to hold up to 21 boards. At least a Central Processor Unit/Polynomial
Divider (CPU/PD) (or CPU and PD boards), Vital Relay Driver (VRD) and Interface Bus
(I/O Bus) boards are required in each Vital system. These boards all operate on the
System bus. A single VPI system can be for one to four modules.
Some combination of Vital boards may be used in the VPI module in quantities of one or
more. These are the Direct Input (DI), Single Break Output (SBO), Double Break Output
(DBO), Lamp Driver Output (LDO), AC Output (ACO), Vital Serial Communication
(VSC), Multidrop Vital Serial Communication (MVSC), Genrakode Vital Serial
Communication (GVSC), Field-Settable Vital Timer (FSVT) and Code Rate Generator
(CRG) boards.
In addition, some combination of Non-Vital boards may be used in the module in
quantities of one or more. These are the Non-Vital Input (NVI), Non-Vital Input
Differential (NVID), Non-Vital Input Differential Switch (NVIDSW), Non-Vital Output
(NVO), Non-Vital Output Relay (NVRELAY), Non-Vital AC Output (NVOAC), Non-Vital
Output Sink (NVO-SNK), TWC MAIN (TWCMAIN), TWC Attenuator (TWCATT), NonVital TWC Modem (NVTWCMOD), Non-Vital TWC Multiplexer (NVTWCMUX) and NonVital TWC Frequency-Shift-Keying (NVTWCFSK). Also, up to four CSEX boards,
depending on system design requirements, may be used. These additional
communication emulation boards can be used in expansion modules.
P2086B, Volume 1, Rev. D, Nov/13
4-13
Alstom Signaling Inc.
Theory of Operation
VITAL PRINTED
CIRCUIT BOARDS
VITAL SYSTEM INTERFACE
AND COMMUNICATION BOARDS
CPU
PD
CPU/PD
Central Processor
Unit
CRG
I/OBUS
VSC
MVSC
GVSC
TIMER
Code Rate Generator
Interface Board
Polynomial Divider
Vital Serial
Communication
Multidrop VSC
Central Processor
Unit/Polynomial Divider
Genrakode VSC
VRD
Vital Relay Driver
Field Settable
Vital Timer
VITAL INPUT BOARD
DI
Direct Input
VITAL OUTPUT BOARDS
SBO
DBO
DBO-50V
LDO
ACO
Single Break Output
Double Break Output
Double Break
Output 50V
NON-VITAL PRINTED
CIRCUIT BOARDS
Lamp Driver Output
Code System
Emulator
CSE
CSEX1
CSEX2
CSEX3
AC Output
Code System
Emulator eXtended
Code System
Emulator eXtended 2
Code System
Emulator eXtended 3
NON-VITAL TWC BOARDS
NVTWCMOD
TWC Modem
NVTWCMUX
NON-VITAL I/O BOARDS
NVI
NVID
NVIDSW
NVO
NVOAC
NVO-SNK
NVRELAY
TWC Multiplexer
Non–Vital Input
NVTWCFSK
Non–Vital Input
Differential
TWC Freq. Shift Keying
TWC
Non–Vital Input
Differential Switch
Non–Vital Output
Train-to Wayside
Communicatons
TWCATT
Non–Vital
AC Output
TWC Attenuator
Non–Vital
Output Sink
Non–Vital
Relay Output
Figure 4-7. VPI Boards Grouped by Vital and Non-Vital Functions
P2086B, Volume 1, Rev. D, Nov/13
4-14
Alstom Signaling Inc.
Theory of Operation
Figure 4-8 shows typical board placement in the VPI module for most of the above
mentioned boards. Individual board locations in a VPI configuration depend on the total
complement of boards used.
CENTRAL
PROCESSOR UNIT/
POLYNOMIAL
DIVIDER
CODE SYSTEM
EMULATOR
EXTENDED
1
NON-VITAL
INPUT
2
3
4
5
NON-VITAL
OUTPUT
6
7
8
VITAL RELAY
DRIVER
9
I/O
INTERFACE
10
11
12
TIMER
13
DIRECT
INPUT
DOUBLE BREAK
OUTPUT
14 15 16 17 18 19 20 21
LAMP DRIVER
OUTPUT
NON-VITAL
TWC MODEM
Figure 4-8. Typical Board Placement for Single Chassis VPI System
Note: Currently produced systems use one CPU/PD board whereas
earlier produced systems used separate CPU and PD boards.
All boards may be located in slot locations other than shown in
this figure.
P2086B, Volume 1, Rev. D, Nov/13
4-15
Alstom Signaling Inc.
Theory of Operation
Figure 4-9 shows typical VPI module chassis bus interfaces. This chassis implements
three different interface connector locations: P1, P2, P3 (P1 at bottom, P3 at top).
POWER INPUTS
&
MOTHERBOARD
I/0 BUS BREAK
1
2
I/O BUS
MOTHERBOARD
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
TS 1
TS 2
MODULE
POWER
&
I/O BUS
TRACES
TS 3
TS 4
Figure 4-9. Typical VPI Module Chassis
4.4.1
System Expansion
More than one module can be combined depending on the complexity of an application.
The number of expansion modules that one system can handle depends on the quantity
of Vital and Non-Vital I/O that is required and the number of equations Vital and NonVital that must be solved (the maximum number of expansion modules is three). For
VPI capacity application guidelines, see Appendix B for system capacities.
4.4.2
System Bus
The main CPU is connected between the appropriate boards with a 60-way system bus
ribbon cable (38216-395). This cable interconnects the lower connector (P1) of each
board with a system bus connection. The length of cable, number of connectors and
location in the module is determined by the board layout for each application. Table 4-1
shows the interface connections to the Main System Bus.
A 7-position System Bus Motherboard (31166-201) also exists for VPI. It is a doublesided board which utilizes 60-way press-fit edge connectors and is designed to
duplicate the functionality of the system bus ribbon cable (38216-395) mentioned
above. This System Bus Motherboard is also located in connector row P1 and supports
all the current system PC boards utilized on VPI. It also replaces the discrete 58920252-00 connector used to secure the Field Settable Vital Timer PC board to the CPIB
(31038-274) chassis.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
Table 4–1. System Bus Interface Connections
Pin
Description
Pin
Description
1
DB0
31
DT/R
2
5V COM
32
5V COM
3
DB1
33
ENIORD
4
DB2
34
5V COM
5
5V COM
35
ENIOWR
6
DB3
36
5V COM
7
DB4
37
AB18
8
5V COM
38
AB17
9
DB5
39
AB16
10
DB6
40
5V COM
11
5V COM
41
AB15
12
DB7
42
AB14
13
DB8
43
AB13
14
5V COM
44
5V COM
15
DB9
45
AB12
16
DBA
46
AB11
17
5V COM
47
AB10
18
DBB
48
5V COM
19
DBC
49
AB9
20
5V COM
50
AB8
21
DBD
51
AB7
22
DBE
52
5V COM
23
DBF
53
AB6
24
5V COM
54
AB5
25
MRD
55
AB4
26
5V COM
56
5V COM
27
MWT
57
AB3
28
5V COM
58
AB2
29
DEN
59
5V COM
30
5V COM
60
AB1
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
4.4.3
I/O Bus Motherboard (Vital I/O Bus and Non-Vital I/O Bus)
The Motherboard provides operating logic power and signal distribution to all boards in
the module. This Motherboard can contain an all Vital I/O Bus, an all Non-Vital I/O Bus
or a combination of both (with a split between slots 5 and 6). The I/O Bus Motherboard
is connected to the P2 connector. Table 4–2 lists the I/O Bus Motherboard interface
connections.
Table 4–2. Motherboard Interface Connections (Vital and Non-Vital) (Cont.)
Pin
Description (Vital I/O)
Description (Non-Vital I/O)
1
+5V
+5V
2
+5V
+5V
3
5V COM
5V COM
4
IODB0
NVDB0
5
IODB1
NVDB1
6
IODB2
NVDB2
7
IODB3
NVDB3
8
IODB4
NVDB4
9
IODB5
NVDB5
10
5V COM
5V COM
11
IODB6
NVDB6
12
IODB7
NVDB7
13
IODB8
EMSEL/
14
IODB9
NVA0
15
5V COM
5V COM
16
IODBA
NVA1
17
IODBB
NVA2
18
IODBC
NVA3
19
IODBD
NVA4
20
IODBE
NVA5
21
IODBF
NVA6
22
5V COM
5V COM
23
ENIORD/
NVIORD/
24
ENIOWR/
CLR.IREQ/
25
T-OUTC3
NVA7
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
Table 4–2. Motherboard Interface Connections (Vital and Non-Vital) (Cont.)
Pin
Description (Vital I/O)
Description (Non-Vital I/O)
26
TIMC4
NVA8
27
IOAB1
NVA9
28
IOAB2
NVA10
29
IOAB3
NVA11
30
IOAB4
NVA12
31
5V COM
5V COM
32
CLR/
NVA13
33
125 KHZ CLK
NVIOWR/
34
OUTC1/
POLL/
35
SEL DISABLE ON-OFF/ (See Note 1)
5V COM
36
DISABLE ON-OFF/
NVMRD/
37
IODT-R/
NVMWR/
38
5V COM
5V COM
39
RCHK CLK
INT/REQ/
40
SEL 1 (See Note 1,3)
NOT USED
41
OUTC2/
PROG
42
SEL 2 (See Note 1,3)
MISC SEL 2
43
SEL 3 (See Note 1)
MISC SEL 3
44
ADD SEL 0 (See Note 2)
ADD SEL 0 (See Note 2)
45
ADD SEL 1 (See Note 2)
(See Note 2)
46
ADD SEL 2 (See Note 2)
(See Note 2)
47
ADD SEL 3 (See Note 2)
(See Note 2)
48
5V COM
5V COM
49
+5V
+5V
50
+5V
+5V
Note 1: SEL 1 is wire-wrapped to SEL 2 to select the lower data bus and to SEL 3 to
select the upper data bus, for use with Vital output boards. SEL DISABLE ONOFF/ is wire-wrapped to pin 36 when a Vital output board requires special
output checking. This function is used with the lamp drive outputs to permit hot
and cold filament tests.
Note 2 Pins are wire-wrapped to 5V COM as required for the board address.
Note 3 For split motherboard, if slot 5/6 used for I/O, pins must be isolated.
P2086B, Volume 1, Rev. D, Nov/13
4-19
Alstom Signaling Inc.
Theory of Operation
4.4.4
Expansion Bus
The expansion bus is connected to the top connector (P3) of the System module's I/O
Bus interface board and runs to a 60-way ribbon cable connector on the System
module's rear panel. A 60-way ribbon cable (38216-404) connects from the rear panel
of the System module to the rear panel of the Extender module(s). An internal 60-way
ribbon cable then runs from the rear panel of the Extender module(s) to the lower
connector (P1) of the I/O Bus interface board and/or CSE or CSEX boards in the
Extender module(s).
If two or more Extender modules are used, the Expansion bus can be connected to any
of the three remaining 60-way connector locations on the module's rear panel and then
run to the other modules with additional 60-way ribbon cables. Connectors on the rear
panel of the Extender module(s) are used to implement this interconnection and to
minimize the ribbon cable length.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Theory of Operation
4.4.5
Board Placement
The following rules apply to all Vital VPI applications:
•
Modules containing Vital I/O must have an I/O Bus interface board
•
Modules containing a CPU or CPU/PD board must have an I/O Bus interface board
and a VRD board
•
Module containing a CPU board must have a PD board
•
Modules containing Non-Vital I/O must have a CSE or CSEX board
As a minimum, each Vital system module must have a Central Processing Unit (CPU
and PD boards or CPU/PD board), Vital Relay Driver (VRD) board, an I/O Bus interface
(I/OB) board and at least one Vital output (i.e., SBO, DBO, ACO, DBO-50 VDC) and
Vital input board (i.e., DI for VRD front contact).
In the System module, the Split Backplane Motherboard (59473-743-01) is typically
used. This Motherboard has a split between slots 5 and 6 in order to create two
independent I/O busses. Using this backplane, Vital and Non-Vital I/O boards may be
housed in the same module. The I/O Bus Interface board controls the Vital I/O section
of the Bus, while a CSE or CSEX board controls the Non-Vital I/O section of the bus. If
the slots 1-5 are designated for Vital I/O, then slots 6-21 may be designated for NonVital I/O. Alternatively, if slots 1-5 are designated for Non-Vital I/O, slots 6-21 may be
designated for Vital I/O. It is also possible to use the Split Backplane Motherboard to
drive two separate Vital or two separate Non-Vital I/O sections.
If the system configuration requires more Vital or Non-Vital I/O than can be placed in a
single module, additional Extender modules can be used. These Extender modules can
use either the split backplane Motherboard (59473-743-01) as described above or a
continuous backplane Motherboard (31166-166-01). However, when using a full
complement of either all Vital or all Non-Vital boards in a System or Extender module,
the continuous backplane Motherboard which allows either an all Vital module or an all
Non-Vital module must be used. The split backplane Motherboard allows mixing of Vital
and Non-Vital I/O in the Extended module.
The CPU, PD, CPU/PD, and VRD boards do not use the I/O bus and may be placed
anywhere. The CPU/PD, VRD, and I/O Bus interface boards are usually adjacent to
each other to provide easy interconnection via the System Bus that interconnects their
P1 connectors.
P2086B, Volume 1, Rev. D, Nov/13
4-21
Alstom Signaling Inc.
Theory of Operation
4.4.6
Signature Header Assignments
All DI boards and their associated I/O Bus interface boards are assigned a Signature
Header by the VPI CAAPE package or manually assigned by the Engineer. A Signature
Header is a 36-pin header that is installed on DI and IOB boards. Its purpose is to
electrically key a specific PCB to a specific slot in the module. DI boards connected to
different I/O Bus interface boards may have the same signatures. The signature is tied
to the addressing for the I/O Bus interface and direct input boards and is used to
prevent address failures from compromising system safety. There are 16 different
signatures available for use by a system (59473-871). Each of the 16 types is unique
and plugs into sockets on each DI or IOB board. See Appendix F for a list of Signature
Headers and the associated Alstom part numbers.
4.4.7
Output Board Signature PROMs
Each Vital output board has an assigned Signature PROM (39780-003) that contains
the output check information for that board. Each PROM used in a system is unique.
The PROM code required for each output board is assigned by the CAAPE package.
This data is tied to a specific board address to prevent failures from compromising
system safety. This 16-pin signature PROM plugs into a socket on each Vital output
board to key the output board to a specific module slot. See Appendix F for a list of
Signature PROMs and the associated Alstom part numbers.
P2086B, Volume 1, Rev. D, Nov/13
4-22
Alstom Signaling Inc.
Theory of Operation
4.4.8
Board Address Assignments
Each board requires an address (except the CPU/PD board, which requires a revision
signature on pins 42-47, see CPU/PD board sections) that is encoded on the
Motherboard. Motherboard pins 44, 45, 46, and 47 are used for this function. On the PC
boards, these lines are connected to +5V through resistors, placing them in a high or “1”
state. To set a particular line to a “0” state, the appropriate pin is wire wrapped or
jumpered to 5-volt common on the Motherboard.
Motherboard pins are used to implement the desired address by wire wrapping or
jumpering them to represent the binary equivalent of the address. Pin 44 represents the
Least Significant Bit (LSB) of the address and pin 47 represents the most significant bit
(MSB). For instance, board address "A" which is 1010 in binary, is implemented by wire
wrapping pins 46 and 44 to 5-volt common. Board addresses are assigned by the
CAAPE package. The CAAPE creates a list of the pins to be connected to 5-volt
common by board slot as well as a module wire table.
For Vital output boards, additional connections are made. A wire wrap or jumper is
installed to select the appropriate half of the Vital I/O bus allocated to a particular board
(Motherboard pins 40, 42 and 43). Because there are eight outputs on a board and the
I/O bus is 16 data lines wide, the CPU controls any two output boards that have the
same address. In this case, one is dedicated to the lower eight data bus lines and the
other to the upper eight data bus lines. If special on/off checking of an output (such as
for hot or cold filament check) is required, another wire wrap or jumper is installed
(Motherboard pins 35 and 36). The VPI CAAPE package defines the pins that are
connected to create these functions.
4.4.9
Field-Settable Vital Timers
When using additional modules, all Field-Settable Vital Timer boards must be placed
within the same module (always a system module) as well as the I/O Bus interface
board (59473-827) using signature A.
P2086B, Volume 1, Rev. D, Nov/13
4-23
Alstom Signaling Inc.
Theory of Operation
4.4.10
Power Supply Consideration
The logic circuitry portion of the VPI module requires 5 VDC power. The common side
of this supply is connected to the chassis, internal to the VPI module. The chassis is
electrically connected to the rack when it is properly mounted and the rack is connected
to earth ground. When the normal signal battery is used with a DC/DC converter to
create this supply, the converter must have 3000 VAC RMS isolation between input and
output. Since the Non-Vital input and output boards do not maintain this isolation
between the supply used for the Non-Vital I/O and the 5V power supply, supplies used
for Vital circuits cannot be applied to the Non-Vital boards. When multiple VPI modules
are used and connected together via the expansion bus, they may either have a
common 5-volt power supply or have separate power supplies with their commons tied
together. When separated power supplies are used, the output of each supply should
be adjusted so that the modules are within 0.1 volt of each other.
The 5-volt supply must maintain an output between 4.75 and 5.25 volts as measured at
the Motherboard or at the input power test points on the VPI boards. Note that the
number of boards installed in a VPI module affects the total current drawn by the
module. Maximum load specifications for each circuit board used in the VPI module are
given at the end of the board descriptions.
4.4.11
Backplane Interface Card
The Backplane Interface Card (BPIC) version VPI System Module (BPIC VPI) is
intended to replace the current 31038-015-03 Case Complete chassis in low end,
single-module mainline railroad applications (Control Point In a Box). The main feature
of the BPIC VPI is the replacement of the chassis-mounted 36-position I/O connectors
and associated bifurcated crimp terminals with a series of distinct versions of the BPIC
(Appendix G). This is accomplished by extending the depth of the module by two (2)
inches and mounting twenty-one (21) four-inch nylon card guide sets in the rear plane of
the chassis to accommodate each BPIC. The BPIC VPI module product structure
combines the required material for a case complete (sideplates, card guide sets, main
motherboard, etc.) with the minimum number of VPI System Boards and corresponding
BPICs in order to create a base module which is suitable for all CPIB applications.
P2086B, Volume 1, Rev. D, Nov/13
4-24
Alstom Signaling Inc.
Vital Printed Circuit Boards
SECTION 5 – VITAL PRINTED CIRCUIT BOARDS
5.1
INTRODUCTION
This manual describes a set of the Vital and non-vital printed circuit boards used to
provide functionality in the VPI System. It is a subset of all available VPI system boards.
It includes a brief description of the differences between board variations and the keying
information for all variations of each board type.
5.1.1
Vital and Non-Vital Subsystems
Figure 5-1 is a block diagram of the boards in the Vital and non-vital subsystems.
Vital Subsystem
Vital I/O Bus
IOB
CPU/PD
Vital Inputs
Vital Outputs
VRD
Non-Vital Subsystem
Non-Vital I/O Bus
VSC
CSEX
Non-Vital
Inputs
Non-Vital
Outputs
Figure 5-1. Vital and Non-Vital Subsystems
P2086B, Volume 1, Rev. D, Nov/13
5-1
Alstom Signaling Inc.
Vital Printed Circuit Boards
Table 5–1 describes the Printed Circuit Boards used to provide Vital functionality in the
VPI System. It then gives a brief description of differences between board variations
along with the keying information for all variations of each board type 1. The remainder of
Section 5 then provides a technical description of each board type. See P2086B
Volume 2 for Vital board schematics.
Table 5–1. Vital PC Boards Index (Cont.)
Board Type
Drawing
Number
Comments
CPU
59473-742-01
Basic Board, No VPI System Software
CPU
59473-742-02
59473-742-01 w/40026-027-00 VPI System
Software
CPU
59473-742-03
59473-742-01 w/40026-054-00 VPI System
Software
CPU
59473-742-05
59473-742-01 w/40026-067-00 VPI System
Software
CPU
59473-742-06
59473-742-01 w/40026-084-00 VPI System
Software
CPU
59473-742-07
59473-742-01 w/40026-094-00 VPI System
Software
CPU
59473-742-08
59473-742-01 w/40026-138-00 VPI System
Software
CPU
59473-742-09
59473-742-01 w/40026-159-00 VPI System
Software
PD
59473-737-01
PD board must be used with CPU (59473-742)
board
CPU/PD
31166-029-01
Basic Board, No VPI System Software
CPU/PD
31166-029-10
31166-029-01 w/40026-180-00 VPI System
Software
CPU/PD
31166-029-11
31166-029-01 w/40026-191-00 VPI System
Software
CPU/PD
31166-029-25
31166-029-01 w/40025-304-00 VPI System
Software
CPU/PD
31166-029-27
31166-029-01 w/40025-321-00 VPI System
Software
CPU/PD
31166-029-28
31166-029-01 w/40025-328-00 VPI System
Software
1
See Appendix E for keying instructions.
P2086B, Volume 1, Rev. D, Nov/13
5-2
Alstom Signaling Inc.
Vital Printed Circuit Boards
Table 5–1. Vital PC Boards Index (Cont.)
Board Type
Drawing
Number
Comments
CPU/PD
31166-029-29
31166-029-01 w/40025-329-00 VPI System
Software
CPU/PD
31166-029-30
31166-029-01 w/40025-347-00 VPI System
Software
CPU/PD
31166-029-31
31166-029-01 w/40025-356-00 VPI System
Software
CPU/PD
31166-029-32
31166-029-01 w/40025-366-00 VPI System
Software
CPU/PD
31166-029-33
31166-029-01 w/40025-404-00 VPI System
Software
VRD
59473-740-02
Fast Drop Circuit removed
VSC
59473-939-01
Pt.-Pt. w/40026-081-00 VSC software
VSC
59473-939-04
Pt.-Pt. w/40026-192-00 VSC software
VSC
59473-939-05
Multidrop w/40026-193-00 MVSC software
VSC
59473-939-06
Pt.-Pt. w/T1 Adapter w/40026-192-00 VSC software
VSC
59473-939-07
Multidrop, half duplex w/40025-290-00 GVSC
software
VSC
59473-939-10
Pt.-Pt. w/40025-322-00 VSC software
VSC
59473-939-11
Pt.-Pt. w/T1 Adapter w/40025-322-00 VSC software
VSC
59473-939-12
Multidrop w/40025-323-00 MVSC software
VSC
59473-939-13
Multidrop, half duplex w/40025-324-00 GVSC
software
VSC
59473-939-14
Multidrop, half duplex w/40025-348-00 GVSCE
software
CRG
31166-261-03
Solid State Relay Driver w/40025-235,218,219-00
software
CRG
31166-261-04
B-Relay Driver w/40025-325,326,327-00 software
IOB
59473-827-01
Vital I/O Bus Interface board
DI
59473-867-01
(16) 9-15 VDC, low-pass filter
DI
59473-867-02
(16) 9-15 VDC, no low-pass filter
DI
59473-867-03
(16) 9-15 VDC, momentary input hold
DI
59473-867-04
(16) 45-55 VDC, low-pass filter
DI
59473-867-05
(16) 9-22 VDC, low-pass filter
P2086B, Volume 1, Rev. D, Nov/13
5-3
Alstom Signaling Inc.
Vital Printed Circuit Boards
Table 5–1. Vital PC Boards Index (Cont.)
Board Type
Drawing
Number
Comments
DI
59473-867-07
(16) 24-34 VDC, low-pass filter
SBO
59473-739-01
(8) 9-30 VDC, 0.5 A
SBO
59473-739-02
(8) 9-30 VDC, 0.5 A
DBO
59473-747-01
(8) 9-15 VDC, 0.6 A, Vout=Vin - 5*Iout,
(nominal 12 VDC source/12 VDC out)
DBO
59473-747-02
(8) 9-15 VDC, 0.3 A, Vout=2.3*Vin - 10 *Iout
(nominal 12 VDC source/24 VDC out)
DBO
59473-747-03
59473-747-01 with different Keying
DBO-50V
59473-977-01
(8) 50 VDC @ 0.14 A out, 30-40 VDC in
DBO-50V
59473-977-02
(8) 50 VDC @ 0.14 A out, 45-55 VDC in
LDO
59473-749-02
(8) 9-18 VDC, 2.9 A, 100 mA Hot/Cold check
LDO
59473-749-03
(8) 15-30 VDC, 2.9 A, 200 mA Hot/Cold check
LDO
59473-749-04
(8) 9-18 VDC, 2.9 A, 100 mA Cold check
ACO
59473-937-02
(8) 90-130 VAC, 0.8 A, 40-150 HZ (higher EMI
protection)
ACO
59473-937-03
(8) 90-130 VAC, 0.8 A, 40-150 HZ (EMI
suppression)
FSVT
59473-894-01
(8) Field-Settable Vital Timers #1-8, Jumper
Selection
FSVT
59473-894-02
(8) Field-Settable Vital Timers #9-16, Jumper
Selection
P2086B, Volume 1, Rev. D, Nov/13
5-4
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2
CPU (CENTRAL PROCESSING UNIT) BOARD, P/N 59473-742
5.2.1
General
All control and monitoring functions for the VPI module go through the Central
Processing Unit board. Once each second inputs are read, outputs are updated, and all
expressions are evaluated. In addition, Vital output status is verified every 50 ms.
Information is also passed to and from local or office code systems via the CSEX and
Non-Vital I/O boards. The CPU board controls the main system bus over which the
CPU, PD, VRD, CSE, CSEX, VSC, and I/O bus interface boards communicate.
Eighteen address, sixteen data, and five control signals are buffered and used for
driving the 60-way System bus cable.
Figure 5-2 shows a block diagram of the CPU board. Each CPU board contains a 16-bit
microprocessor, related program and data memory, logic to allow use of dual CPU
boards in cases of increased interlocking complexity, and logic necessary to carry out
VPI timing and data handling functions. With a Handheld Terminal, the VPI memory can
be viewed while it is installed on the board and system diagnostics can be performed.
The CPU board has the following functional areas:
•
Memory address decoding
•
Control bus buffering
•
Reference timer and I/O decoding
•
Microprocessor control circuitry
•
Automatic hardware reset
•
Interrupt handling
•
Integrated diagnostics
•
Software revision signature
•
Maintenance indicators
•
Test Points
P2086B, Volume 1, Rev. D, Nov/13
5-5
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.2
Memory Address Decoding
Program memory is divided into two parts: CPU task and Application Data. Memory is
allocated on this board in two separate segments corresponding to program and data
memory address space. This address space may be selected by placing an on-board
DIP switch in the required position. Two EPROM memory chips are used for system
Vital routines (PMGR 1, and 2) and six EPROMs are reserved for application data
memory (APMGR 1-6). To provide for more than 64K application memory, two
additional sockets are available for 32K of “shadow” memory (APMGR5 and 6), which is
selectable under system software control.
Each EPROM used on this board has 16K × 8 bytes (27128). Address lines A15-A19
are input to a 32 × 8-bit PROM that decodes whether CPU program or application data
are being accessed. In a similar manner, the address space for data memory (RAM) is
decoded by a bipolar PROM. An output from the PROM decoder indicates that RAM is
being accessed. This output, besides lines A14 and A15, selects one of four 8K × 8
static RAM chips. Because the 8086 chip performs data manipulations in 16-bit word
operations, two RAM chips are accessed at a time. Inputs to the bipolar PROM are for
processor outputs A0 and BHE. These lines dictate whether 8- or 16-bit operations are
being performed.
SYSTEM RAM
20 BIT
ADDRESS
8K
LATCHED
APPLICATION
C
SOFTWARE
P
CPU
U
B
U
80C86
S
16K
L
O
RESET
C
A
WATCHDOG
SYSTEM
SOFTWARE
P1
L
MAIN BUS
CIRCUIT
60 PINS
16K
MOTHERBOARD
CONNECTOR P2
HANDHELD
TERMINAL
SOFTWARE REVISION
PORT
SIGNATURE PORT
(CURRENT LOOP)
(WIRE WRAP)
Figure 5-2. CPU Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
5-6
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.3
Control Bus Buffering
The control bus for the VPI system is generated by the CPU board. The control bus flow
is vectored to different parts of the system by buffers that determine the implementation
of the processor's local control bus. In applications where only one processor controls
the system, the local control bus is enabled continuously. The control bus is used to
access memory, access I/O, latch the address bus and drive other peripherals
connected to the same system bus. If a second CPU (named CPU B) is needed
because of interlocking complexity, the control bus is enabled to provide handshaking
between CPU A and CPU B.
5.2.4
Reference Timer and I/O Decoding
The 8086 chip has a separate memory and I/O address space and all external circuit
boards located on the system bus are memory-mapped. The input and output ports,
reference timer, a USART and shadow PROM located on the CPU board are accessible
through the use of IN and OUT instructions.
The reference timer, an 82C54 programmable interval timer, has three separate
timer/counters. In this application, one counter provides a signal to interrupt the CPU
every 50 ms. The remaining two are configured as a 32-bit counter. This counter can be
initialized at a particular value in the initial segment of the program and can be read
while it counts. Since this counter runs at a 1 MHz rate, the exact state of the counter
(32-bit value) is easily predicted. This counter is used as an external clock reference
with respect to the CPU.
To ensure the processor is executing the program instructions with correct timing,
various segments of the program may be timed and compared to the reference timer to
verify the integrity of the bus cycle timing. Loading, gating and reading of each timer is
done by I/O addressing. Loading of the control word and reading of the counter value
are performed using address lines A1 and A0.
Output port 08H provides similar signals to the coprocessor: completion of its program
cycle, signals involving a hold sequence, a hardware reset output, an output indicating a
one-second interval has elapsed, an output to clear interrupt circuitry and control signals
used by the programmable timer.
The software revision signature is read at port 18H and operations concerning the
USART are performed at port 10H. The shadow ADS PROM is selected by performing
an IOREAD from address A0H.
Each of the ports and timer is located at a particular address in the I/O address space.
A 3-to-8 line decoder using address lines A3, A4 and A5 provides the outputs to select
the desired function.
P2086B, Volume 1, Rev. D, Nov/13
5-7
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.5
Microprocessor Control Circuitry
Support chips for the microprocessor include a clock generator, address latches, and
control signal decoding gates. The clock generator chip provides the 8086 chip with a
crystal-controlled clock input that in turn determines the bus cycle timing. The control
signal gates take status lines from the 8086 chip and derive the appropriate bus
command signals as shown in Table 5–2.
Table 5–2. CPU Board Bus Command Signals
IO/M/
WR/
RD/
Processor State
Bus Command Signal
1
1
0
Read I/O port
IOREAD/
1
0
1
Write I/O port
IOWRT/
0
0
1
Write memory
MWRT/
0
1
0
Read memory
MREAD/
Besides the command outputs provided by the control decoder, the following control
outputs needed by the CPU system are generated:
ALE: This is the Address Latch Enable that supplies a strobe that is active when a valid
address is present on the multiplexed address/data bus.
DT-R/: This is a two-state signal. When high, it indicates data is being transmitted to a
peripheral device and, when low, it indicates data is being received. This signal provides
data direction information to the data bus transceivers.
DEN/: This is an active low signal that is used to enable data transceivers’ outputs onto
the local and system busses.
INTA/: This is an active low signal that indicates an interrupt has been acknowledged by
the 8086.
A set of three octal latch buffers store the address of the hardware segment being
accessed. The ALE output from the control decode serves as an input strobe to latch
the valid addresses on its positive transition. The latched address accesses local
program and data memory, as well as addresses other circuit boards within the VPI
system.
P2086B, Volume 1, Rev. D, Nov/13
5-8
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.6
Automatic Hardware Reset
If a program failure results in a lockup of instruction execution, a signal is needed to
force the 8086 microprocessor to restart its program. This prevents a transient error
from causing a complete VPI system shutdown. A correctly operating program causes a
reset holdoff signal to be generated every 50 ms in correspondence with an interrupt
sequence. A program failure does not allow this signal to be output, and the reset circuit
begins to oscillate. On the negative transition of this oscillating output, the clock
generator is forced to reset, which in turn causes the RESET output to activate, thus
restarting the program.
When a RESET signal is received, the 8086 chip executes a fetch instruction from
address location 0FFF0H that contains an address vector, signaling the starting address
of the program. A bipolar PROM, using address lines A16-A19 as chip selects and
address lines A0-A3 as its address input, provides the vector address to the data bus.
Also stored in these PROMs is the address vector for processing interrupts.
5.2.7
Interrupt Handling
As stated earlier, a programmable reference timer is used to interrupt the 8086
microprocessor. Internal to the 8086, two interrupt acknowledge cycles are executed.
On the second cycle, a fetch to memory is performed to obtain an address vector that
diverts the program flow to an appropriate interrupt service routine. Using a flip-flop, this
second bus cycle is detected and, with control signals INTA and DEN, a strobe is
provided that places the address vector on the data bus. The address vector is stored in
a bipolar PROM, which uses address lines A0 to A4 as its inputs. Since the PROM used
has 32 bytes of memory space, it is used for both interrupt and reset address vectors.
The A4 input is used to differentiate between them. The use of a Handheld Terminal
also provides a system interrupt PROM, which directs the program to the Handheld
Terminal service routine.
5.2.8
Integrated Diagnostics
Incorporated in the hardware is a system diagnostic program that tests the operation of
the CPU board and, in addition, the functional operation of most other peripheral boards
by choosing different diagnostic routines. Diagnostic software is run on-line. Most
parameters generated during the controlling of an application are accessible in real
time. Also, an external Handheld Terminal (HHT) or the Alstom Tracker software can be
used to display error information to the user. A separate counter with a baud rate of
1200 bps generates the transmit/receive clock for the USART.
P2086B, Volume 1, Rev. D, Nov/13
5-9
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.9
Software Revision Signature
On the Motherboard connector for the CPU board, six programmed binary inputs are
provided. These inputs can be programmed to 5V COM to yield a binary representation
of a decimal number from 0 to 64. This number corresponds to the revision number of
the current application software in the CPU EPROM. When the software is changed, the
CAAPE changes this number in EPROM. The hardware must be reprogrammed to tie a
particular CPU board to a specific application. Programming is completed by wire
wrapping the appropriate pins on the CPU Motherboard connector. A wire table is
generated as a report from the CAAPE for Motherboard pins P2 42-48. These pins
define the CPU board slot.
5.2.10
Maintenance Indicators
LED indicators are located on the CPU board's front edge to indicate board functions.
Each LED number and its associated function are shown in Section 8 Maintenance.
5.2.11
Test Points
Connector PC3 contains many of the CPU board test points. Also, individual points such
as reset holdoff, mode selection, and others are accessible. PC1, which is the program
monitor bus, contains the address, data, memory controls, and read and write
commands. Also available is 5V and 5V COM on separate terminals.
Refer to Volume 2 of this manual series for detailed pin information.
5.2.12
Interface Connections
Connector P1 with 60 contacts is wired to the system bus. Connector P2 contains 6
wires that are used to determine the software (PROM) revision of the CPU board.
Connector P3 is normally unused. For specific pinout details and locations of PROM
chips, refer to Volume 2 of this manual series.
P2086B, Volume 1, Rev. D, Nov/13
5-10
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.2.13
Specifications
Table 5–3. Central Processing Unit (CPU) Specifications
Characteristic
Specification
Maximum Number of Boards per VPI System
1
Board slots required
1
Maximum Board Logic Current Supply
500 mA
Maximum Board Logic Current Supply with HHT
600 mA
Support 27128 EPROM, 200ns
Yes
Supports 27H010 EPROM, 70ns
No
5.2.14
Assembly Differences
Table 5–4. CPU Assembly Differences
Specification
Alstom Part Number
Basic Board, No VPI System Software
59473-742-01
59473-742-01 with 40026-027-00 VPI System Software
59473-742-02
59473-742-01 with 40026-055-00 VPI System Software
59473-742-04
59473-742-01 with 40026-067-00 VPI System Software
59473-742-05
59473-742-01 with 40026-084-00 VPI System Software
59473-742-06
59473-742-01 with 40026-094-00 VPI System Software
59473-742-07
59473-742-01 with 40026-138-00 VPI System Software
59473-742-08
59473-742-01 with 40026-159-00 VPI System Software
59473-742-09
P2086B, Volume 1, Rev. D, Nov/13
5-11
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.3
5.3.1
PD (POLYNOMIAL DIVIDER) BOARD, P/N 59473-737
General
The Polynomial Divider board consists mainly of a 32-bit shift register that uses
feedback taps for data compression testing and parameter testing during the Vital
program execution (only used in conjunction with the CPU board). This board performs
three essential functions:
1. Boolean logic expressions through the combination of system parameters.
2. Aids in the creation of system checkwords.
3. Tests system parameters for unique properties.
All PD functions are performed by loading the shift register with 32-bit values and
executing one of the three functions mentioned. The mode of operation is determined
by memory-mapped hardware dedicated for each specific function.
There are four shift register feedback configurations; two modes with two channels
each. When PD modes 1, 1 and 1, 2 are selected, code words are verified to ensure
that the expression result or input port test data is valid. Most VPI system parameters
are represented by code words, which are a subset of 32-bit values that possess unique
properties. The shift register is arranged with the lower 14 bits being the information
field and the upper 18 being the check field. Feedback taps are arranged in an 18th
order polynomial. An information field for the code word is loaded into the lower 14 bits
of the shift register and the remaining 18 bits are zeroed. Fourteen shifts are performed
and the upper 18 bits should return the value of the tested code word's check field.
Feedback arrangements 3, 1 and 3, 2 are used to combine data, such as memory
check sums or expression evaluations. In this mode, the full 32 bits are loaded and
shifted nine times. Successive parameters are added into the register and shifted. Here,
the 32nd order feedback tap arrangement is used. The 32-bit result contains unique
code word properties.
Figure 5-3 shows a block diagram of the PD board. Operation of the PD is controlled by
memory-mapped addressing. Each function — loading of data, adding of parameters,
selecting the feedback configuration, clocking of the shift register and reading of the 32bit result — is controlled by performing a read or write operation to a specific address.
The address and data provided to the board are decoded by two 32 × 8 bipolar PROMs.
The output of the PROMs gated with the read or write commands creates several
control signals as described below.
P2086B, Volume 1, Rev. D, Nov/13
5-12
Alstom Signaling Inc.
Vital Printed Circuit Boards
32 BIT PARALLEL LOAD/SERIAL SHIFT REGISTER
FEEDBACK TAPS - 1 OF 4
CONFIGURATIONS
DB0-7
8
DB8-15
8
DB0-7
8
DB8-15
8
P1
BUS
DRIVERS
PD LOCAL BUS
MAIN BUS
60 PINS
FEEDBACK
CONTROL
SIGNALS
MEMORY MAPPED CONTROL
LOGIC
Figure 5-3. PD (Polynomial Divider) Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
5-13
Alstom Signaling Inc.
Vital Printed Circuit Boards
A binary counter is loaded with the desired number of shift operations. Its output is used
to gate a 6-MHz, crystal-controlled clock that results in that number of clock pulses. The
6-MHz clock allows the cycling action to occur faster than it takes the CPU to fetch and
execute the next instruction. In this way, the shifting places no time burden on the
system. The 32-bit shift register is arranged in two 16-bit sections, SRLO and SRHI,
which are loaded alternately from the 16-bit system bus. Four 8-bit latches function as
the 32-bit register.
All operations perform a parallel load or adding of data to the registers. Clocking
(shifting) of the latches causes an XORing of latch outputs with ADDED data and/or
data presented from feedback taps and is input into the next higher register stage.
Inverting buffers are used to present the correct logic sense when data is processed by
the registers.
Test points are provided for board troubleshooting. Both 50- and 60-way headers are
located at the front of the PD board. Wired to them are major control signals, shift
register inputs and outputs, and a signal to trigger a logic analyzer. Indicators are also
provided to aid in troubleshooting. LEDs on the board front edge show feedback
arrangements and register output controls used during normal system processing.
5.3.2
Interface Connections
The PD board has three connections to the VPI system. P1 connects to the System
bus, P2 connects to the Motherboard for system power and also carries interface
communications. P3 is normally unused. For specific pinout details, refer to Volume 2 of
this manual.
5.3.3
Specifications
Table 5–5. Polynomial Divider (PD) Specifications
Characteristic
Specification
Maximum number of Boards per VPI System
1
Board slots required
1
Maximum Board Logic Current Supply
300 mA
P2086B, Volume 1, Rev. D, Nov/13
5-14
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4
CPU/PD (CENTRAL PROCESSING UNIT/POLYNOMIAL DIVIDER) BOARD,
P/N 31166-029
5.4.1
General
All control and monitoring functions for the VPI module go through the CPU/PD (Central
Processing Unit/Polynomial Divider) board. The CPU/PD board also contains an
integrated polynomial divider that consists of a 32-bit shift register that uses feedback
taps for data compression testing and parameter testing during the Vital program
execution.
Once each second, inputs are read, outputs are updated, and all expressions are
evaluated. In addition, Vital output status is verified every 50 ms. Information is also
passed to and from local or office code systems via the CSEX and Non-Vital I/O boards.
The CPU/PD board controls the System bus over which the CPU/PD, VRD, CSEX, VSC
and I/O Bus interface boards communicate. Eighteen address, sixteen data and five
control signals are buffered and used to drive the 60-way System bus cable.
The block diagram in Figure 5-4 shows the key functional blocks of the CPU/PD Board
and the busses that interconnect them. The CPU/PD board can control up to four 21slot chassis depending on an application’s complexity.
Each board contains a 16-bit microprocessor, related program, data and RAM memory
and logic to carry out VPI timing and data handling functions. Provision is made for two
serial data channels that can be individually configured for EIA232, EIA422, EIA423 or
EIA485. One of these data channels is brought out to the front of the board for use with
the EIA232 Handheld Terminal for diagnostic purposes. The CPU/PD board has the
following functions:
•
Memory address decoding
•
Control bus buffering
•
Reference timer and I/O decoder
•
Hardware reset and watchdog timer
•
Interrupt handling
•
Polynomial Divider
•
Integrated diagnostics
•
Software and Installation signature
•
Maintenance indicators
•
Test points
P2086B, Volume 1, Rev. D, Nov/13
5-15
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
32 MHz
Osc.
Y3
5-16
WDT & Pwr
On Reset
U4
CPU
80C186EB
U13
Communications
Interface
U20, 21, 22, 23, 24, 25
PD ASIC
U2
Address
Latch
U10, 11, 12 Bus
Data Bus
Interrupt
Control Bus
Port 0
Port 1
SYS MEM
EPROM
or FLASH
U16, 17
J1 & P3
P3
RAM
U14, 15
ADS MEM
EPROM
or FLASH
U18, 19
Bus Interface
U30, 31, 32, 33, 34, 35
TIMER
U1, 7
To/From
P1
Output
Port
U9
Input Port
U26, 27
From
P2 & P3
Vital Printed Circuit Boards
Figure 5-4. CPU/PD Board Block Diagram
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.2
Memory Address Decoding
Program memory is divided into two parts: VPI system software and VPI application
data. Two EPROM memory chips (27C010, 70 nanoseconds) are provided for each
part. U16 and U17 are for VPI system software while U18 and U19 are for VPI
application data. Thus each part has 256K bytes of memory for a total of 512K of
program memory. One chip in each part is used for the low order bytes; the other chip is
used for the high order bytes. Address decoding is performed by the microprocessor
and two 22V10 programmable logic chips. These programmable logic chips also
perform address decoding for two RAM chips that provide 64K bytes of memory.
Programmable logic chips simplify the logic on the board and reduce the number of
necessary logic chips.
5.4.3
Reference Timer and I/O Decoding
An 82C54 programmable interval timer and a 1 MHz crystal oscillator perform the
interval timer function. In this application, one counter provides a time-based signal to
interrupt the CPU. The remaining two are configured as a 32-bit counter. This counter
can be initialized at a particular value in the initial segment of the program and can be
read while it counts. Since this counter runs at a 1 MHz rate, the exact state of the
counter (32-bit value) is easily predicted. This counter is used as an external clock
reference independent of the processor clock.
To insure the processor is executing the program instructions with correct timing,
various segments of the program may be timed and checked against the reference
timer to verify the integrity of the bus cycle timing. Loading, gating and reading of each
of the timers is done by I/O addressing performed by a programmable logic device.
5.4.4
Hardware Reset and Watchdog Timer
U4, a CPU supervisory integrated circuit, resets the CPU upon power up, provides a
manual reset through push-button S1 and contains a watchdog circuit. The watchdog
circuit must be regularly activated by the CPU or the circuit will assume the CPU is in a
“lock up” condition. Under these conditions, the circuit produces a reset pulse at regular
intervals until the CPU appears to have cleared itself of the lock up condition. U4 also
monitors 5V power on the board.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.5
Integrated Diagnostics
Within the program memory is a system diagnostic program that tests the operation of
the CPU/PD board and, in addition, the functional operation of most other peripheral
boards by choosing different diagnostic routines. Diagnostic software is run on-line.
Most parameters generated during the controlling of an application are accessible in
real time. In addition, an external Handheld Terminal (HHT), a dumb terminal, Alstom
Tracker software or the Vital Diagnostic Protocol (VDP) in a CSEX board can be used to
display error information to the user.
5.4.6
Software Revision Signature
On the Motherboard connector for the CPU/PD board, six programmed binary inputs
are provided. These inputs can be programmed to 5V or common to provide a binary
representation of a decimal number from 0 to 63. This number corresponds to the
revision number of the current application software in the CPU EPROMs. When the
software is changed, the CAA changes this number in the EPROM memory.
The hardware must be reprogrammed to associate a particular CPU/PD board to a
specific application. Programming is completed by wire wrapping the appropriate pins
on the CPU Motherboard connector P2. A wire table is generated as a report from the
CAA for Motherboard pins 42 - 48. In a similar manner, a Site ID jumper can be placed
on connector P3 (odd pins 1-19) to provide an additional 10 input bits, for 1024 decimal
combinations.
Note: The user can utilize these 10 input bits for configuration control
or in any manner desired.
Starting with the 31166-029-30 CPU/PD board and any other CPU/PD board assembly
built using the 31165-575-00 copper, the six revision ID pins are also routed to the P3
connector. This allows for a system ID to be configured completely through the P3
connector.
P2086B, Volume 1, Rev. D, Nov/13
5-18
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.7
Indicators
LED indicators are provided on the front of the CPU/PD board (see Figure 9-3). The
functions indicated by these LEDs are as follows:
•
Reset
•
One second "OK" indicator
•
5 Volts DC
5.4.8
Polynomial Divider ASIC
All of the functions of the polynomial divider (PD) are in U2 on the CPU/PD board and
are performed by loading the ASIC with 32-bit values and executing one of the three
following functions. The mode of operation is determined by memory-mapped hardware
dedicated for each specific function.
The ASIC:
•
Provides Boolean logic expressions through the combination of system parameters
•
Aids in the creation of system checkwords
•
Tests system parameters for unique properties
There are four polynomial division configurations; two modes with two channels each.
When modes 1,1 and 1,2 are selected, code words are verified to ensure that the
expression result or input port test data is valid. Most VPI system parameters are
represented by code words, which are a subset of 32-bit values that possess unique
properties. The 32-bit value is arranged with the lower 14 bits being the information field
and the upper 18 being the check field. A 14-bit information field for the code word is
loaded into a register and is operated on by an 18th order polynomial division. The upper
18 bits contain the result and should return the value of the tested code word's check
field.
Polynomial division modes 3,1 and 3,2 are used to combine data, such as memory
checksums or expression evaluations. In this mode, the full 32 bits are loaded and
operated on by a 32nd order polynomial division. The 32-bit result contains unique code
word properties.
Operation of the PD is controlled by memory-mapped addressing. Each function
(loading data, selecting the operation and reading the 32-bit result) is controlled by
performing a read or write operation to a specific address.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.9
High Integration Embedded Microprocessor
Microprocessor U2 (80C186EB-16) on this board has many integrated features:
•
Two independent UARTs, each with an integral baud rate generator
•
Two 8-bit multiplexed I/O ports
•
Three programmable 16-bit timer/counter circuits
•
Ten programmable chip selects with integral wait state generators
•
An operating clock speed of 16 MHz
All of these features are used on the CPU/PD board to provide a compact, high-speed
board set. The increased speed and memory capacity of the board provide increased
Vital I/O and Vital expression capacities.
5.4.10
Interface Connections
Connector P1 with 60 contacts is wired to the system bus. Connector P2 contains 6
input pins that are used to determine the software (PROM) revision of the CPU/PD
board. Connector P3 contains 10 input pins that are used to determine the site
identification, or can be used for a system identification as previously explained. P3 is
also used to connect to either Serial Data channel 0 or Data channel 1. J1 on the front
of the board is connected to data channel 0 and is normally used for connection to
access diagnostic information.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.11
CPU/PD Board Jumpers
All terminal strips (W1-W10) use 01196-012-ON jumpers (see Figure 5-5). These
jumpers should only be changed during board test or system design. The listing in
Table 5–6 is for verification purposes when a board has been returned after repair.
Table 5–6. CPU/PD Board Jumpers
Terminal Block
In Place for Normal
Operation
5 volt power to HHT plug
W1 1-2
YES
1 MHz Crystal to CPU
W2 1-2
YES (See Note)
1 MHz Oscillator to CPU
W3 1-2
YES
Watch Dog Timer Enable
W4 1-2
YES
Internal Pulse Times 2
W5 1-2
YES
Internal Pulse Times 3
W6 1-2
YES
CPU Ready to Reset
W7 2-3
NO
CPU Ready to 5 VOLTS
W7 1-2
YES
32 MHz Oscillator to CPU
W8 1-2
YES
Future Use
W9 1-2
YES
CPU Timer Inhibit
W10 2-3
YES
CPU Timer Enable
W10 1-2
NO
Function
Note: Jumper W2 placement is not required for normal operation if component
Y4 is installed rather than component Y1. However, leaving it installed in
this case keeps a full set of jumpers on the board. W2 must be removed if
Y4 and Y1 are both installed.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.4.12
Specifications
Table 5–7. CPU/PD Specifications
Characteristic
Specification
Maximum number of Boards per VPI System
1
Board slots required
1
Maximum Board Logic Current Supply
500 mA
Maximum Board Logic Current Supply with HHT
600 mA
Support 27128 EPROM,200ns
No
Supports 27H010 EPROM,70ns
Yes
5.4.13
Assembly Differences
Table 5–8. CPU/PD Assembly Differences
Specification
Alstom Part Number
Basic Board, No VPI System Software
31166-029-01
31166-029-01 with 40026-180-00 VPI System Software
31166-029-10
31166-029-01 with 40026-191-00 VPI System Software
31166-029-11
31166-029-01 with 40025-304-00 VPI System Software
31166-029-25
31166-029-01 with 40025-321-00 VPI System Software
31166-029-27
31166-029-01 with 40025-328-00 VPI System Software
31166-029-28
31166-029-01 with 40025-329-00 VPI System Software
31166-029-29
31166-029-01 with 40025-347-00 VPI System Software
31166-029-30
31166-029-01 with 40025-356-00 VPI System Software
31166-029-31
31166-029-01 with 40025-366-00 VPI System Software
31166-029-32
31166-029-01 with 40025-404-00 VPI System Software
31166-029-33
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Alstom Signaling Inc.
Vital Printed Circuit Boards
W1
DIP
Switch
HHT
Connector
W2
W3
W9
SYS-LO
W4
W5
SYS-HI
W6
W7
W8
ADS-HI
RESET
ADS-LO
W10
Figure 5-5. CPU/PD Board Jumper Locations
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.5
5.5.1
VRD (VITAL RELAY DRIVER) BOARD, P/N 59473-740
General
Figure 5-6 shows a block diagram of the Vital Relay Driver (VRD) board. This board
produces an output voltage capable of operating a 100Ω Alstom Type B relay (56001787-05) if, and only if, the data sent to it by the main processing system is exactly
correct. The main processing system creates a set of data called “main checkwords”
once every second. These checkwords are used by the VRD board and allow it to
continue operation for another 1-second period. In addition, the main processing system
generates a set of recheck checkwords every 50 ms based on the status of all the
systems outputs. These checkwords are sent to the VRD board every 50 ms where they
are used to produce 50 ms worth of output. If any of these checkwords are not precisely
correct, the VRD output is shut off and the external relay de-energizes.
5.5.2
Physical Characteristics
The processing portion of the VRD board is based on an 8085 microprocessor chip with
4K of EPROM program memory and 4K of RAM. The RAM is shared with the main
processing system and is the means by which the checkwords are transferred.
This board has three indicators for use as troubleshooting aids. The top indicator
illuminates whenever the signal produced by the processing portion of this board
passes through the 10 kHz tuned circuit. The remaining two indicators illuminate during
the exchange of handshaking controls between the VRD board and the main processing
system. These controls are REQ/ and RDY/. During normal operation, each of these
indicators turns on or off each time their respective control line changes state.
Depending upon system timing, one of these indicators may appear to be on all the time
while the other appears to be off most of the time or these indicators may appear to
alternately flash. If neither indicator flashes, it means the main processing system and
the VRD are not communicating with each other, hence no control handshaking occurs.
There is a 16-position switch located along the front edge of this board. This switch
must be set to position F to allow the system to attempt to restart if the VRD relay deenergizes. If the switch is in any other position, the system makes no attempt to restart.
See Section 8, Maintenance, for a complete list of troubleshooting indicators and switch
settings.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.5.3
Operating Characteristics
Once every second the main processing system delivers a new set of data called main
checkwords to the VRD board. The VRD board processes these main checkwords and
converts them to “tokens.” The VRD requires 20 tokens to operate for the next onesecond period. Every 50 ms the main processing system delivers a set of data called
“recheck checkwords” to the VRD. The VRD uses one token and the set of recheck
checkwords to create an output signal for 50 ms. If any of the checkwords is incorrect or
if the new checkwords are not delivered on time, the VRD output is lost.
The output of the processing portion of the VRD board (when all checkwords are
correct) is a 10 kHz square wave modulated at 500-Hz. This signal passes through a 10
kHz tuned circuit and then a 500-Hz tuned circuit. The output of the 500-Hz tuned circuit
is rectified and filtered to produce an isolated DC voltage to energize an Alstom Type B
100Ω relay.
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Alstom Signaling Inc.
CLOCK
5 MHZ
RESET
CIRCUITRY
RST CLKOUT
8085
CPU
RST
HOLDOFF
P2086B, Volume 1, Rev. D, Nov/13
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TIMER 2
TIMER 1
HALT ADD.
OUT OF
RANGE
INPUT
PORT
OUTPUT
PORT
PROG
CONTROL
LOGIC
REF
CLOCK
5 MHZ
DIAG.
SW.
DECODER TEST
DECODER DRIVE
CIR REQ / RDY
SET REQ
RAM
2 FREQ DECODER
RELAY DRIVER
REQ FF
RDY FF
RAM
CONTROL
LOGIC
N12
B12
ISOLATED RELAY
DRIVER OUTPUT
MAIN CPU
BUS
BUFFERS
MAIN CPU
Vital Printed Circuit Boards
Figure 5-6. VRD Board Block Diagram
Alstom Signaling Inc.
Vital Printed Circuit Boards
The VRD board gives the main processing system three chances to deliver the new
checkwords before shutting down the outputs. This is to allow for clock variations and
variations in system timing. As part of the recheck checkword set, three dummy
checkwords are sent to the VRD. These three checkwords cause the VRD to look for a
new set of checkwords. The VRD creates a 46 ms output if the set of recheck
checkwords it received is correct. It then creates an additional 2 ms output, using the
first of the dummy checkwords. However, during a portion of this period, the VRD allows
the main processing system to deliver a new set of checkwords. If the main processing
system does not deliver the new checkwords, then the VRD uses the second dummy
checkword and tries again 2 ms later. If it still does not receive the new set of
checkwords by the third try, it has run out of checkwords and no longer produces the
proper output. Consequently, the VRD begins a new cycle using the new checkwords to
create another 46 ms of output.
The VRD program uses Safety Assurance Logic that does not change from system to
system and cannot produce the correct output without the checkwords being absolutely
correct. The VRD requires that the checkwords received from the main processing
system be different on each cycle.
The VRD automatically tries to restart if its control switch is in the F position. As part of
the restart procedure, it runs a 7-second delay before it accepts any checkwords from
the main processing system. If the processor halts or tries to operate in memory
locations outside the allocated memory space, it is automatically reset. The system
removes power from the outputs immediately in the event of a failure.
5.5.4
Interface Connections
The VRD board has three connections to the VPI system. P1 connects to the system
bus, P2 carries board power and address selection signals and P3 connects to +12
VDC and an external relay. Refer to Volume 2 of this manual for detailed pinout
information.
5.5.5
Specifications
Table 5–9. Vital Relay Driver Specifications
Characteristic
Specification
Maximum number of Boards per VPI System
1
Board slots required
2
Maximum Board Logic Current Supply
300 mA
VRD Drive Output Isolation
>3000 Vrms
Minimum VRD Supply Voltage
9.00 VDC
Maximum VRD Supply Voltage
15.00 VDC
Typical VRD Drive Current draw @ 12.00 V
40 mA
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6
5.6.1
VSC (VITAL SERIAL CONTROLLER) BOARD, P/N 59473-939
General
The Vital Serial Controller board is a microprocessor-based board that provides a
means for exchanging the states of up to 200 Vital interlocking functions (in each
direction) between interlocking systems in a Vital manner. This communication is used
between Vital systems within the train control room and from room to room for limited
distances.
One version of the VSC board is used to provide Vital serial communication from VPIto-VPI via a transformer coupled, proprietary communications protocol (59473-939-04, 10) over two twisted pairs. When using appropriate cable, it is possible to reliably
communicate over distances of four miles.
To communicate from one train control room to another over the fiber optic system, a
different assembly version of VSC board is used. This VSC board (59473-939-06, -11)
contains a special interface board (31166-058-01), referred to as a “daughter board”,
mounted on the VSC board itself. This daughter board contains an EIA232 converter
that allows the VSC board to directly interface with compatible line cards in T1
multiplexers and other standard communications equipment that may be part of an
existing copper or fiber optic data transmission system.
Another version of the VSC was created to provide a means of communicating to and
from AF Track Circuit modules. This Multi-Drop Vital Serial Controller (MVSC) board is
capable of communicating by using Vitally addressable destinations. Up to 15 AFTC
modules may be multi-dropped on one serial line. The MVSC board (59473-939-05, 12) hardware and operation are almost identical to the VSC.
A different multi-drop version of the VSC is the Genrakode Vital Serial Controller
(GVSC) board. This is often used in Alstom’s Control Point in a Box (CPIB) rack system.
It is capable of communicating with up to two Programmable Genrakode (PGK) boards
on a two-wire half-duplex line. This application allows for the communication of up to 15
parameters for each track. The GVSC board (59473-939-07, -13) hardware and
operation are almost identical to MVSC.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
Another multi-drop version of the VSC is the Genrakode Vital Serial Controller Extended
(GVSCE) board. This is also used in Alstom’s Control Point in a Box (CPIB) rack
system. It is capable of communicating with up to two Programmable Genrakode (PGK)
boards on a two-wire half-duplex line. This version allows for the communication of up
to 25 parameters for each track. The GVSCE board (59473-939-14) hardware and
operation are almost identical to GVSC and is required when a full implementation of
Code T™ is needed.
Each type of board, MVSC, GVSC, GVSCE or VSC, has its own unique Vital system
software which is not interchangeable and must be matched with specific versions of
the CPU and CPU/PD system software. The basic difference in the system software is
the message structure used by each board. The MVSC, GVSC or GVSCE transmits a
message containing 450 Vital parameters that is sent simultaneously to the various
addressable AF modules or PGK boards on the serial line. It then listens for responses
from the modules, with 30 (50 for GVSCE) Vital parameters returning from each
module. The VSC, used for VPI-to-VPI communications, sends and receives up to 200
Vital parameters of information in its message.
In the following descriptions, the term VSC is used generically to describe a Vital serial
communication board of any of the above types.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.2
Communication Process
The VSC is a system board that must reside on the VPI System bus. Link information in
the form of system parameter values and checkwords is provided from the VPI CPU
system RAM over the system bus to Dual Ported RAM (DPRAM) memory located on
the VSC. The block of data (or message packet) is then moved, under VSC control, to
its transmit processing RAM area.
The transmit process converts message packet contents into two serial message
components: an “image field” and a “check field.” The image field represents the
TRUE/FALSE (or PERMISSIVE/NON-PERMISSIVE) state of each system parameter in
the provided message block. The check field incorporates a combination of all link
processing checkwords created up to this point in the link transfer. These fields, plus
transmit/receive protocol flags, are formed into a message and transmitted.
The receive process uses the image field to reconstruct a receive message packet with
parameter values resembling those passed from the CPU board to the VSC board at
the transmit end. This reconstructed block of data, along with a receive link checkword,
are passed to the CPU upon request. The receive link checkword includes all link
checkwords created along the data path to this point.
The CPU then retrieves the input message packet from the VSC DPRAM and places it
in its input matrix. Processing is performed to combine the receive end CPU link
checkwords with those provided from the VSC board. If all checkwords are correct and
the path of the data is correct (e.g. origin in SYSTEM 1 CPU to destination in CPU of
SYSTEM 3), parameters directed to be in a TRUE state by the transmit end are allowed
to assume the correct TRUE parameter value within the receive end CPU memory.
Otherwise, failures along the link path have occurred and all link parameters are forced
into a FALSE (restrictive) state. These parameters are subsequently used as required
during expression evaluation at the receiving end.
A maximum of four VSC boards may be used in a VPI system supported by CAA
31746-007 to 31746-023. These may reside in either the SYSTEM MODULE or an
EXTENDER MODULE.
A maximum of ten VSC boards may be used in a VPI system supported by CAA 31746025 and later. These may reside in both the SYSTEM MODULE and EXTENDER
MODULE. The maximum number is dependent on the number of CRG and CSEX
boards being used. Refer to Table 5–16 and Table 5–17 to determine configuration
requirements when using multiple VSC boards with CSEX and CRG boards.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.3
Memory Types
The VSC program and application memory is designed to be one of two types; 16K or
32K × 8 bits, which is DIP switch selectable (SW4). Board functions allocated to SW4
are shown in Figure 5-11.
Note: Only the 16K x 8 bit memory size is currently supported.
5.6.4
Indicators
Eleven indicators are provided on the VSC. Eight are multipurpose indicators for use
with diagnostic software. Another indicator is assigned as a power supply voltage level
monitor. An output of the watchdog timer IC drives the LED when the VSC board supply
is below 4.6 VDC. Another indicator illuminates when the VSC is in a reset condition. A
final indicator driven by the SCC is used to display serial link activity. Refer to Figure
5-13 for a list of the indicators and their use.
5.6.5
Communication Interfaces
There are two different physical communications interfaces available in this board
series. A direct wire interface that requires two copper pairs and an industry standard
EIA232 signal level interface for use with data communications equipment. The choice
of interface is primarily an economic one, the Vital operation of the VSC link is not
altered by the choice of physical interface. However, reliability of the communication link
may be affected depending upon the choice made and the electrical environment.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.6
Direct Wire Interface
Serial Communication Controller – Manchester Encoder-Decoder
The VPI-VPI link is controlled by one channel of a serial communications controller
(SCC) IC (82530 or 85C30). Data is provided to and from the SCC under interrupt
control. Its output and input data is converted between non-return-to-zero (NRZ) and
Manchester format by a Manchester encoder/decoder (MED) device (6409). Data is
provided in synchronous mode. Synchronous data link control (SDLC) format is used for
this link interface.
Serial Link Interface
The VSC contains a full duplex interface for linking VPI-to-VPI. Baud rate is 19.2 K for
standard applications. The serial data stream is converted from NRZ to a Manchester
coding format. This format is such that each data bit cell contains a logic transition.
Therefore, a continual stream of logic ‘0’ data bits is not a constant signal level but
rather a series of cycles each with a low to high transition in the center of the data bit.
Similarly, a continual stream of logic ‘1’ data bits will have a high to low transition in the
center of the data bit interval. Refer to Figure 5-7 for a comparison between NRZ and
Manchester encoding. This signal is twice the frequency of the data bit stream provided
by the USART. The advantage of this data format is that due to its continuous
transitions, the signal can be used to power a transformer; i.e. no DC component. The
Manchester Encoder/Decoder also provides the benefit of message synchronization,
clock recovery and noise immunity.
Bit Boundaries
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
1
0
0
1
1
1
0
0
0
0
1
0
0
0
1
1
0
NRZ Encoding
Data Values
Manchester Encoding
Figure 5-7. The Effect of Manchester Encoding on NRZ Data
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Alstom Signaling Inc.
Vital Printed Circuit Boards
Data Transmission
The signal supplied by the MED is provided to an EIA422 driver. The EIA422 driver
drives a transformer in differential mode. The voltage swing of the driver is 4 Vp-p
(typical).
The transformer interfaces with twisted pair communication links having a characteristic
impedance of about 100Ω at a signal frequency of 19.2 kHz. It provides isolation of the
system 5V supply from external references. The transformer has a center-tapped
secondary that allows for a 1:1 or a 1:2 turns ratio. For the transmit direction the 1:1
configuration is used. The VPI-VPI link uses two transformers for full duplex operation.
The receiver transformer uses the 1:2 transformer configuration to step up the incoming
signal.
Jumpers in the transformer secondary can be used to modify the turns ratio at a later
time if necessary. The secondary of the transformer interfaces with the twisted pair link
via a line termination, transient suppression, and low-pass filter network. A 100Ω
resistor terminates the twisted pair link in its characteristic impedance to minimize line
reflections. Back-to-back transient suppressors clamp the link at 12V in either polarity.
The L-C low-pass filter in each leg of the link has a cutoff frequency of 100 kHz. This
filter arrangement provides common mode and differential mode filtering. Also, 68 uH
inductors serve as series resistive elements with the transient suppressor to limit current
surges.
Data Reception
The VPI-VPI link receiver section uses the same transformer as the transmitter but
converts the 4Vp-p signal to an 8 Vp-p on the secondary side that feeds the EIA422
differential receiver. The EIA422 receiver output provides a 5V logic representation of
the differential signal to the MED. In the receive circuit, resistors provide hysteresis to
minimize the effect of interference on the message data. The receiver responds to
receive signals > ± 800 mV.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
Application Wiring
The VSC uses a transformer-coupled twisted pair link as the medium of data exchange.
Serial link transmission distances of up to four miles are possible given a suitable
variety of twisted shielded cable is used and cable runs are separated from high power
transmission cables. The recommended minimum conductor size to achieve the four
mile distance is 16 AWG. Primary lightning protection is necessary for link runs that are
accessible to lightning strikes, e.g., aerial runs, above ground duct banks, etc. The
protection should be located as close to where the cable enters the house as practical.
The recommended cabling scheme for the VSC link is shown in Figure 5-8. Shielded
cable is not required for all installations. However, if shielded cable is used, the shield
must be connected to earth ground at only one point. This point need not be at the
same location as one of the two VPI systems. If a better ground is available at some
other point on the cable run, e.g., a junction box, the shield may be grounded at that
point.
Interlocking
A
Ground at one end only
Cable Shield
Interlocking
B
A
Transmit
B
A
Receive
B
A
Receive
B
A
Transmit
B
Figure 5-8. VSC Link Cable and Shield Connections
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.7
Data Communications Interface
The data communications interface is provided through the addition of a daughterboard.
The daughterboard, 31166-058-01, provides a galvanically isolated interface (optical) to
the data communication equipment. This reduces the likelihood that circulating currents
in possible ground loops with other equipment would have an effect on the operation of
the VPI electronics. See Figure 5-16 for an outline of the daughterboard.
Data Transmission and Reception
When the daughterboard is installed on the VSC board it establishes connections to the
SCC serial data lines and the connections that the SCC had to the Manchester
encoder-decoder are severed. The message format is changed from synchronous to
asynchronous. The asynchronous message format is one start bit, eight data bits, no
parity bit and two stop bits. The data transmission rate may be at either 9600 or 19200
bits per second. The data communication equipment used with this interface must be
able to support this format.
WARNING
The features and capabilities of the data communication equipment must be
carefully reviewed to insure that any message buffering or error correcting
protocols do not insert significant delays in the message. The VSC receiver
must receive the complete message within 400 milliseconds from the point at
which it recognizes the beginning of a message. If the message is not
completely received within this 400 millisecond interval the message
parameters are forced to FALSE. While this is a safe-side failure, it may
create operational issues in the movement of trains.
External Power
To provide the isolated interface a power source must be provided to power the isolated
electronics of the daughterboard. An on-board power supply regulates the applied
voltage to five volts for the interface electronics. This power supply does not provide
isolation between the external source and the daughterboard electronics. When
selecting a source of this external power application engineer should be aware that the
typical data communications equipment will tie the serial data signal common to earth
ground. Therefore, an energy source which cannot be grounded for any reason should
not be used for this power connection. Often, the data communications equipment
power supply has sufficient power available to provide power to the daughterboard.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.8
Interface Connections
The VSC board has three on-board connectors as follows:
1. P1: This 60-pin connector is wired to the system bus; contains addresses A1 to
A18, data bus 0 to 15, six controls, and numerous grounds (5V COM).
2. P2: This 50-pin connector is wired to the VPI Motherboard that contains 5V power
and system address programming.
3. P3: This 36-pin connector is wired to the isolated serial I/O for both VPI-VPI and
VPI-OTHER links.
When applied with a plug-coupled VPI chassis, connector P3, a 36-pin discrete wire PC
edge connector, is wired to a 50-way connector on the back panel of a VPI module to
permit use of a VSC standard cable. VSC edge connector, name, standard cable
coordinate, and function are shown in Table 5–10.
WARNING
Although the VSC board assembly is equipped with a 9-pin connector that is
similar to that used by other processors for diagnostic information and
access to internal status, there are no diagnostics available with this board
assembly. Attempts to access diagnostics on this assembly may result in
interruption to the operation of the VSC functions and VSC parameters. This
in turn may affect the operation of the interlockings that depend upon the
VSC parameters.
Table 5–10. VSC Connector Assignments (Cont.)
P3 Pin
Name
50-Way
Signal Function
1
VPITXA
C1
VPI to VPI link transmit wire A
2
VPITXB
B5
VPI to VPI link transmit wire B
3
UNUSED
C3
4
UNUSED
D1
5
VPIRCVA
C5
VPI To VPI link receive wire A
6
VPIRCVB
D3
VPI To VPI link receive wire B
7
UNUSED
D2
8
UNUSED
D5
9
UNUSED
E5
10
UNUSED
E2
11
UNUSED
E1
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Alstom Signaling Inc.
Vital Printed Circuit Boards
Table 5–10. VSC Connector Assignments (Cont.)
P3 Pin
2
Name
50-Way
Signal Function
12
UNUSED
E3
13
UNUSED
A1
14
UNUSED
E4
15
UNUSED
D4
16
UNUSED
F1
17
UNUSED
C2
18
UNUSED
F2
19
UNUSED
A4
20
UNUSED
F3
21
UNUSED
B2
22
UNUSED
F4
23
UNUSED
C4
24
UNUSED
F5
25
INTERFACE OPT 1
A2
TXD 2
26
INTERFACE OPT 2
G1
RTS2
27
INTERFACE OPT 3
A3
DTR2
28
INTERFACE OPT 4
G2
RXD2
29
INTERFACE OPT 5
A5
CTS2
30
INTERFACE OPT 6
G3
CD2
31
INTERFACE OPT 7
B1
DSR2
32
UNUSED
G4
33
UNUSED
B3
34
UNUSED
G5
35
INTERFACE OPT 8
B4
IVCC (9-35VDC)2
36
INTERFACE OPT 9
H1
ISOCOM (Isolated Signal Common)2
Indicates EIA232 signals from daughter board interface assemblies -06 and -11 VSC boards. Note:
RTS, DTR, CTS, CD and DSR signals are not supported by the VSC system software. These signals
should not be wired to any external equipment.
P2086B, Volume 1, Rev. D, Nov/13
5-37
Alstom Signaling Inc.
Vital Printed Circuit Boards
On-Board Switches
The following tables list VSC on-board switches and give the function associated with
each setting. An asterisk (*) denotes default settings.
Note: If a 31166-058-01 daughter board is installed, the switches SW1
and SW2 must be set for -06 or -11 VSC boards. If an attempt is
made to operate the board through the copper wire pair
interface with a daughter board installed, the board will not
operate properly.
SW1: DIP switch to configure handshake signals to the SCC. An asterisk (*) denotes
default settings for assemblies -04, -10 VSC boards. Note that SW1 settings default to
all ON for assemblies -05, -07, -12, -13, -14 VSC boards, and to all OFF for -06, -11
VSC boards.
Switch Position
1
Indicates Side of
Switch that is Down
ON
1
2
3
OFF
4
5
6
7
8
OPEN
Figure 5-9. VSC board DIP Switch S1
Table 5–11. VSC Board DIP Switch S1 Functions
Switch
Position
OFF
ON
1
*Transmit Data Out Disabled
Transmit Data Out Enabled
2
*MED Transmit Sync Disabled
MED Transmit Sync Enabled
3
*Non-Valid Manchester Code To
SCC-CTS\ Disabled
Non-Valid Manchester Code To
SCC-CTS\ Enabled
4
*Not Used
5
*Receive Data From MED Disabled
Receive Data From MED Enabled
6
*Transmit Clock From MED Disabled
Transmit Clock From MED Enabled
7
*Receive Clock From MED Disabled
Receive Clock From MED Enabled
8
*Not Used
* = default switch position when not using the 31166-058-01 daughter board
P2086B, Volume 1, Rev. D, Nov/13
5-38
Alstom Signaling Inc.
Vital Printed Circuit Boards
SW2: 8-position DIP switch used to select between private copper pair interface or
EIA232 interface.
•
The private copper pair interface uses Sync Data and baud rate is fixed at 19200.
Switch positions 7 and 8 are not used.
•
The EIA232 interface with T1 Adapter (daughter board P/N 31166-058-01) installed
uses Async Data. The EIA232 interface baud rate can be selected between 9600 or
19200 with switch positions 7 and 8.
Switch Section
1
Indicates Side of
Switch that is Down
ON
OFF
1
2
3
4
5
6
7
8
OPEN
Figure 5-10. VSC Board DIP Switch S2
Table 5–12. VSC Board DIP Switch S2 Functions
Switch
Section
OFF
ON
1
* Async data 1 enabled
** Sync data 1 enabled
2
* Async data 2 enabled
** Sync data 2 enabled
3
*Not used
4
*Not used
5
*Not used
6
*Not used
7
9600 Baud select 1
** 19.2 Baud select 1
8
9600 Baud select 2
** 19.2 Baud select 2
* = default for VSC with 31166-058-01 daughter board
** = default for VSC without 31166-058-01 daughter board
Note: When operating in asynchronous mode, the message format is
one start bit, eight data bits, no parity bit and two stop bits. The
communication equipment selected must be able to support this
format.
P2086B, Volume 1, Rev. D, Nov/13
5-39
Alstom Signaling Inc.
Vital Printed Circuit Boards
SW3: VSC reset switch.
SW4: Memory select, reset inhibit, etc.
Switch Section
1
Indicates Depressed
Side of Switch
1
2
3
4
OFF
ON
Figure 5-11. VSC Board DIP Switch S4
Table 5–13. VSC S4 Miscellaneous Functions
Switch
Section
OFF
ON
1
*Enable Auto Watchdog
Reset
Disable Reset
2
*Memory Select 16K X 8
EPROM (System, U16)
Memory Select 32K X 8 EPROM
(System, U16)
3
*Memory Select 16K X 8
EPROM (Application, U18)
Memory Select 32K X 8 EPROM
(Application, U18)
4
Select Alternate Reset Vector
*Select Normal Reset Vector
* = default Switch Position
P2086B, Volume 1, Rev. D, Nov/13
5-40
Alstom Signaling Inc.
Vital Printed Circuit Boards
The following jumpers affect the operation of the direct wire interface only. When using
the 31166-058-01 daughter board they have no effect on the board operation. Refer to
Figure 9-28 for the location of the following jumpers.
Table 5–14. Line Termination Jumpers for Copper Pair Interface
Jumper
Installed
Function/Explanation
JU10
yes
Connects the back-to-back junction of suppressors CR6 & CR7
to the logic common. This provides transient protection for the
direct wire transmitter.
JU11
yes
Connects the back-to-back junction of suppressors CR4 & CR5
to the logic common. This provides transient protection for the
direct wire receiver.
JU12
no
Transmitter output level 1:2 (JU13 not installed)
JU13
yes
Transmitter output level 1:1 (JU12 not installed)
P2086B, Volume 1, Rev. D, Nov/13
5-41
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.9
Assembly Differences for 59473-939
Table 5–15. VSC Assembly Differences
Maximum
Maximum
Number of
Board
Boards
Board
Logic
per VPI
slots
Current
System required Supply
VPI CAA
31746-
Assy
Number
Type
-01
Pt - Pt
4
(Note 1)
1
500 mA
19200
40025-081-00 VSC
(Sync.)
007 –
010
-04
Pt - Pt
4
(Note 1)
1
500 mA
19200
40025-192-00 VSC
(Sync.)
011 –
025
-05
Multi-drop full
duplex 4-wire
2
(Note 2)
1
500 mA
19200
(Sync.)
011 –
025
Baud
Rate
System Software
40025-193-00
MVSC (Note 3)
-06
Pt.-Pt. with
4
daughter board (Note 1)
2
9600 or
19200
500 mA* (Async. 40025-192-00 VSC
or
Sync.)
-07
Multi-drop, half
duplex 2-wire
2
(Note 2)
1
500 mA
19200
(Sync.)
-10
Pt - Pt
4
(Note 1)
1
500 mA
027 and
19200
40025-322-00 VSC
later
(Sync.)
2
9600 or
19200
027 and
500 mA* (Async. 40025-322-00 VSC
later
or
Sync.)
-11
Pt.-Pt. with
4
daughter board (Note 1)
40025-290-00
GVSC (Note 3)
011 –
025
023 –
025
-12
Multi-drop full
duplex 4-wire
2
(Note 2)
1
500 mA
19200
(Sync.)
40025-323-00
MVSC (Note 3)
027 and
later
-13
Multi-drop, half
duplex 2-wire
2
(Note 2)
1
500 mA
19200
(Sync.)
40025-324-00
GVSC (Note 3)
027 and
later
-14
Multi-drop, half
duplex 2-wire
2
(Note 2)
1
500 mA
19200
(Sync.)
40025-348-00
GVSCE (Note 4)
030 and
later
* See Figure 5-12 for daughterboard current requirements
Note 1: Starting with CAA 31746-025, this limit is increased to 10 minus the sum of
(#VSC + #MVSC + #GVSC + #GVSCE + #CRG + #CSEX), where # indicates
the total number of a particular VPI board type.
Note 2: The total number of GVSCE + GVSC + MVSC combinations must be less
than or equal to 2.
Note 3: Supports 15 parameters per track.
Note 4: Supports 25 parameters per track.
P2086B, Volume 1, Rev. D, Nov/13
5-42
Alstom Signaling Inc.
Vital Printed Circuit Boards
WARNING
When using assembly versions that include the daughter board, an external
power source must be provided. This energy source must not be a Vital
energy or a non-vital energy that cannot be connected to earth ground. This
is because the communication equipment that the daughter board will
connect to usually connects signal common, i.e., ISOCOM, P3-36 (plug
coupler H1), to earth ground.
Required Current (amperes)
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.000
9
14
19
24
29
34
39
Supply Voltage (volts)
Figure 5-12. Daughterboard Current vs Voltage
P2086B, Volume 1, Rev. D, Nov/13
5-43
Alstom Signaling Inc.
Vital Printed Circuit Boards
VITAL SERIAL
CONTROLLER
(VSC)
NORMAL CONDITION:
INDICATION LIGHTS WHEN:
Flashing Once Per Second
1
Serial Message Transmitted
Off
2
5VDC Power Low
Flashing Once Per Second
3
VSC Cycles
Off
4
Unused
Flashing Once Per Second
5
Transmit Data Recieved from CPU or CPU/PD
Flashing Once Per Second
6
Transmit Messages are Formed
Flashing*
7
Serial Message Recieved
Flashing Once Per Second
8
Data is Being Sent to CPU or CPU/PD Board
Flashing*
9
Recieved Message Data Processed
On After Initialization of Application Data 10
Off 11
*
Rate of flashing will depend on the
number of line drop points.
VSC = 1 per second
MVSC = up to 15 per second
GVSC = up to 2 per second
GVSCE = up to 2 per second
Power Up Application Data Received from CPU or CPU/PD Board
Reset is Activated
Reset Switch
Figure 5-13. VSC Board LED Indications
P2086B, Volume 1, Rev. D, Nov/13
5-44
Alstom Signaling Inc.
Vital Printed Circuit Boards
POS
P3
JU10
8
HHT
PORT
OFF
1
S1*
JU11
JU13
JU12
ON
LEDs
8
1
P2
S2*
SYSTEM
EPROM
LEDs
APPLICATION
EPROM
S3
RESET
P1
4
S4*
DUAL PORT RAM
IC29
1
OFF
5V COM
TP10
VITAL SERIAL CONTROLLER
59473-939-KN
Figure 5-14. VSC Board Layout
P2086B, Volume 1, Rev. D, Nov/13
5-45
Alstom Signaling Inc.
Vital Printed Circuit Boards
TB5
TB5
S1 1
A
TB1
POS
T1 ADAPTER
4
B
OFF
TB4
PORT
TB3
TB2
HHT
P3
S1*
ON
LEDs
8
1
P2
S2*
SYSTEM
EPROM
LEDs
APPLICATION
EPROM
S3
RESET
P1
4
S4*
DUAL PORT RAM
IC29
1
OFF
5V COM
TP10
VITAL SERIAL CONTROLLER
59473-939-KN
Figure 5-15. VSC Board with Daughter Board Installed
P2086B, Volume 1, Rev. D, Nov/13
5-46
Alstom Signaling Inc.
Vital Printed Circuit Boards
1
Pin 1 End
TB5
Terminal
Block ID
Shorting Jumper
Switch Section
Indicates Side of
Switch that is Down
TB5
T1 ADAPTER
S1 1
A
4
TB1
B
TB4
TB3
TB2
Figure 5-16. 31166-058-01 VSC Daughterboard
For normal operation of the daughterboard, all sections of S1 should be set in the “A”
position. There are five (5) terminal blocks on the daughterboard. These terminal blocks
support special manufacturing and development functions and should not be altered in
applying this assembly. For the operating positions of them refer to the table below.
Terminal Block
Jumper Position
TB1
1-2
TB2
2-3
TB3
2-3
TB4
1-2
TB5
1-2
P2086B, Volume 1, Rev. D, Nov/13
5-47
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.6.10
Allowable VSC/CSEX Board Combinations
The following board placement rules are applicable for the VPI CAA 31746-026 and
later.
Table 5–16. Allowable VSC & CSEX Board Combinations (Cont.)
Total Number
of VSC Type
Boards
Allowable
CSEX Boards:
System
Module
Allowable
CSEX Boards:
Extender
Module
0
4
4
-
-
1
4
4
4
4
1
0
0
1
2
4
4
4
4
4
4
2
1
0
0
1
2
3
4
4
4
4
4
4
4
4
3
2
1
0
0
1
2
3
4
4
4
4
4
4
4
4
4
4
4
4
3
2
1
0
0
1
2
3
4
5
3
4
4
4
4
4
4
4
4
4
4
3
5
4
3
2
1
0
0
1
2
3
4
5
6
2
3
4
4
4
4
4
4
4
4
4
4
3
2
6
5
4
3
2
1
0
0
1
2
3
4
5
6
P2086B, Volume 1, Rev. D, Nov/13
5-48
Allowable VSC Allowable VSC
type Boards:
type Boards:
System
Extender
Module
Module
Alstom Signaling Inc.
Vital Printed Circuit Boards
Table 5–16. Allowable VSC & CSEX Board Combinations (Cont.)
Total Number
of VSC Type
Boards
Allowable
CSEX Boards:
System
Module
Allowable
CSEX Boards:
Extender
Module
7
1
2
3
4
4
4
4
4
4
4
4
4
4
3
2
1
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
4
4
4
4
4
4
4
4
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
4
4
4
4
4
4
4
3
2
1
0
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
10
0
1
2
3
4
4
4
4
4
4
3
2
1
0
8
7
6
5
4
3
2
2
3
4
5
6
7
8
P2086B, Volume 1, Rev. D, Nov/13
5-49
Allowable VSC Allowable VSC
type Boards:
type Boards:
System
Extender
Module
Module
Alstom Signaling Inc.
Vital Printed Circuit Boards
In the following table, # represents the total number of a particular board type.
Table 5–17. Allowable VSC Board Quantities by Type
VSC Type Board
Maximum Allowable VSC Type Boards
Total VSC type boards
10
Vital Serial Communications (VSC)
10 – (#MVSC + #GVSC + #CRG)
Multidrop Vital Serial Communications
(MVSC)
2 – #GVSC
Genrakode Vital Serial Communications
(GVSC)
2 – #MVSC
Code Rate Generator (CRG)
3
P2086B, Volume 1, Rev. D, Nov/13
5-50
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.7
CODE RATE GENERATOR (CRG) BOARD, P/N 31166-261
5.7.1
General
The Code Rate Generator Board is a Vital VPI board that receives code rate commands
from the VPI CPU/PD board. The received code rate commands are decoded and used
to non-vitally generate eight coded outputs. The frequency and duty-cycle of the coded
outputs are Vitally verified by using an absence of current detector (AOCD). Data is
circulated through the AOCD. Data returned from the AOCD coupled with other NISAL
processing verifications are used to generate a message that the CRG board sends to
the VPI CPU/PD board. The message received by the CPU/PD board from the CRG is
used as part of the generation of the VRD checkwords. All outputs are generated using
a Double Break Output (DBO) DC-DC converter and as such, are isolated from each
other by >2000Vrms and protected from undetected single-fault failures. A system block
diagram is shown below:
RS-232
SRAM
SRAM
MASTER
PROCESSOR
FLASH
RS-422
VPI
7-SEGMENT
DISPLAYS
SLAVE COPROCESSOR
MASTER LOCAL BUS
ROCKER
SWITCH
FLASH
MASTER
CO-PROCESSOR
SUPPORT_PLD
SLAVE_A_PLD
SLAVE COPROCESSOR
MASTER_PLD
SLAVE_B_PLD
WIRE
WRAP
BUFFERS
SRAM
VITAL
POWER
SWITCHES
SLAVE B LOCAL BUS
MASTER
CO-PROCESSOR
WIRE
WRAP
A
WIRE
WRAP
B
SLAVE A LOCAL BUS
Serial
Terminal
SLAVE
A
PROCESSOR
SLAVE
B
PROCESSOR
FLASH
Serial AOCD Data (2) & Code Rate Control (1)
Rocker Switch Up/Down (2)
Wire Wrap and 7-Segment Data (8)
Master: Address[19:8] - Address/Data[7:0] - Bus Control
Slave: Address[15:0] - Address/Data[7:0] - Bus Control
Communications Data: VPI (4) - Serial Terminal (3)
Vital Power Control Switch Bits (8)
Interrupts[3:0]
Interrupt Line
Wire Wrap Return Data (8)
Code Rate Output (2)
AOCDDBO A
PORT
1
AOCDDBO B
PORT
2
AOCDDBO C
PORT
3
AOCDDBO D
PORT
4
AOCDDBO A
PORT
5
AOCDDBO B
PORT
6
AOCDDBO C
PORT
7
AOCDDBO D
PORT
8
Latched Address[7:0]
Figure 5-17. VPI CRG Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
5-51
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.7.2
Physical
Mounts in 31038-249 type system modules (VPI) or equivalent
Dimensions: 12.0” x 9.3125” x 0.67”
Weight: 2.125 lbs.
Minimum mounting center = 0.75”
Card edge connectors:
P1 (lower connector) is a 36-pin connector
P2 (middle connector) is a 50-pin connector
P3 (upper connector) is a 36-pin connector
Keying on connector P2: 2-4-7-10 per Alstom drawing AD47-11
5.7.3
Electrical Ratings
+5V Power Supply: Voltage Range: 4.75V to 5.25
Typical Operating Current: 1.15A
+12V Power Supply (VRD Energy): Voltage Range: 8V to 16V
Typical Operating Current: 0.5A
P2086B, Volume 1, Rev. D, Nov/13
5-52
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.7.4
Outputs
Solid State Relay Driver
Nominal Operating Conditions (load 1500Ω):
Output Voltage: ~4.64V
Output Current: ~3.1mA
Vital Pwr+
390
1500pf
3000V
Vital Pwr Control In
AOCD
Data In
DBO & AOCD
Module
31166-117-01
Vital Pwr -
243
Ohms,
2W
1500 ohm
SSR
AOCD
Data Out
Figure 5-18. Output Circuit Solid State Relay Driver
The values listed below are calculated considering worst case conditions. Component
values and power supply voltages are chosen to yield a result at the extreme of the
condition in question.
Load Short-Circuit:
•
Max Current (16V into DBO-AOCD): ~50mA
•
Min Current (8V into DBO-AOCD): ~24mA
Load Open-Circuit:
•
Max Voltage (16V into DBO-AOCD): ~7.38V
•
Min Voltage (8V into DBO-AOCD): ~3.29V
P2086B, Volume 1, Rev. D, Nov/13
5-53
Alstom Signaling Inc.
Vital Printed Circuit Boards
B-Relay Driver:
•
Nominal Operating Conditions (VS = Vital Power Supply Voltage; RL = Coil
Impedance):
•
Output Voltage: VOUT = VS*(1.2) - (~0.7)
•
Output Current: IOUT = VOUT/RL
Vital Pwr+
1500pf
3000V
Vital Pwr Control In
AOCD
Data In
DBO & AOCD
Module
31166-117-01
Vital Pwr -
CF
Relay
AOCD
Data Out
Figure 5-19. Output Circuit B-Relay Driver
P2086B, Volume 1, Rev. D, Nov/13
5-54
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.7.5
Communications
Table 5–18. CRG Communications Specifications
Characteristic
Specification
Serial Port 1
Serial Port 0
(EIA232)
(EIA422)
Mode of Operation
Single-ended
Differential
Total number of drivers and receivers
on 1 line
1 Driver
1 Receiver
1 Driver
10 Receivers
Maximum cable length
50 ft.
4000 ft.
Maximum data rate
20kb/s
10Mb/s
Maximum driver output voltage
± 25V
-0.25V to +6V
Driver output signal level (loaded
minimum)
5V to 15V
± 2V
Driver output signal level (unloaded
maximum)
± 25V
± 6V
Driver load impedance
3kΩ to 7kΩ
100Ω
Maximum driver current in high Z state
(power off)
± 6mA @ ± 2V
± 100цA
Maximum slew rate
30.0V/цs
N/A
Receiver input voltage range
± 15V
-10V to +10V
Receiver input sensitivity
± 3V
± 200mV
Receiver input impedance
3kΩ to 7kΩ
4kΩ min.
P2086B, Volume 1, Rev. D, Nov/13
5-55
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.7.6
Environmental
Operating Temperature Range: −40°C to +70°C
Storage Temperature Range: −55°C to +85°C
Humidity: 0% to 95% non-condensing
5.7.7
Assembly Differences for 31166-261
Table 5–19. CRG Assembly Differences
Assy
Number
Maximum
Number of
Board
Boards per
slots
Output Driver VPI System required
Program Numbers
Code Rates Supported
(Pulses Per Minute)
03
Solid State
3
1
40025-235
40025-218
40025-219
0, 50, 75, 120, 180
04
B-Relay
3
1
40025-325
40025-326
40025-327
0, 50, 75, 120, 180,
270, 420, Steady On
P2086B, Volume 1, Rev. D, Nov/13
5-56
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.8
5.8.1
IOB (I/O BUS INTERFACE) BOARD, P/N 59473-827
General
The I/O Bus Interface board serves as a buffer between the system processing boards
and Vital I/O. It provides a storage medium for test data obtained during Vital input and
output port checks. The board includes logic to control the continuous verification of
Vital output port states.
Figure 5-20 shows the I/O bus interface block diagram. Address, control, and data
signals are buffered for use within the IOBUS logic. While address and control buffers
are always enabled, the data buffers are only active when the IOBUS is specifically
addressed. A 7-bit address decoder compares a system bus address with that
programmed for the slot in which the interface board resides (slot address inputs are
labeled ADD SEL 0, 1, 2, 3). A particular bus interface board and its associated I/O are
referred to as a supergroup. If bus and slot address agree, the SUPERGROUP
SELECTED signal enables the data buffers. If the bus address for Vital I/O is greater
than that programmed for the system module interface board, then the EN EXP DBUS
control signal is generated to allow data to be obtained from expansion I/O modules in
multi-module configurations.
The IOBUS logic provides buffering for links between the main system module and all
expansion modules via five octal buffers and a 60-way cable. Actual data transfers
occur only when the external data bus is enabled from the main system module, by
jumpering P2-35 to P2-48 on the IOBUS board. The EN EXP DBUS signal is
permanently disabled for interface boards in expansion modules by inserting a jumper
between the proper pins on the Motherboard. The system module expansion bus can
drive several expansion I/O modules.
Expansion bus buffer logic supports usage of redundant systems; that is, two sets of
system electronics in a system module and Vital I/O in expansion modules. An opticallyisolated input (SEL EXP BUS), derived from redundancy transfer logic, activates either
of the two sets of redundant system electronics, with each having an I/O bus interface
board. A 24V signal at SEL EXP BUS allows one of the two sets of system redundant
electronics to communicate with the expansion I/O bus via the buffered expansion bus.
When the SEL EXP BUS signal is removed, signaling a system failure, the SEL EXP
BUS input is energized on the spare interface board to allow the backup set of system
electronics to communicate to the Vital I/O. Vital input and output functions are
controlled through memory-mapped address operations. An input/output control
decoder employs three address bits to perform four tasks. The first control (YIN)
represents a signal that is later gated with a read or write control when operations
involving Vital inputs are performed.
The second control (YADR-YSR) when gated with a write control sets the I/O group
address latch. It is also gated with a read control to enable the reading of the bank of 16
shift registers.
P2086B, Volume 1, Rev. D, Nov/13
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Vital Printed Circuit Boards
Signal YOF signifies a write operation to Vital output boards (output state control
latches), while the third control (YSM) is used to clock the mode latch used in output
state verification.
The Vital I/O group address latch is buffered and is used to address each Vital I/O slot
on the Motherboard (I/O bus) bus.
P3 Expansion
Bus
P1 System
Bus
Expansion Bus
Buffers
Redundancy
Transfer Logic
Select
Expansion
Bus
Address, Control &
Data Buffers
Supergroup
Address Decoding
Read Shift Reg.
Controls
16 x 18 Bit Serial
to Parallel Shift
Register
Input/Output Control
Decoder
2 MHz
XTAL
Supergroup
Signature Header
Vital I/O Bus Buffers
(Motherboard)
Add (4), Data (16)
Control (11)
Crystal Controlled
Output Verification
Logic
P2
Motherboad
I/O Bus
Figure 5-20. I/OB (I/O Bus Interface) Board Block Diagram
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.8.2
Vital Continuous Output Verification (50 ms Recheck Cycle)
The operation of output state verification is accomplished by a crystal controlled logic
sequence and a mode latch. Data representing a desired function are loaded into the
mode latch with the YSM signal. The mode latch performs one of five functions:
1. Selects mode of output verification (recheck)
2. Initiates selected mode
3. Clears logic for subsequent operations
4. Enables the highest 8 sequence/counter stages
5. Selects between an even or an odd recheck cycle
The board contains a 2-MHz crystal that drives a 14-stage counter. Function timing is
controlled using specific counter stages. One output, a 125 kHz signal, is used for data
modulation and another is used for the output recheck clock. Outputs of the mode latch,
gated with different counter outputs, perform these functions:
Read mode 1: the data in output board RAM is read into the shift registers (SR LOAD)
as 8 serial bits, 16 bits wide and processed four times to obtain the 32-bit check data
word for each output.
Write mode 2: fills all RAM on the output boards with logic ones as an initialization
process. Control signal CLR CNTR is generated in this mode while the recheck clock is
disabled.
Circulate mode 3: the circulate mode occurs 45 out of every 50 ms. The recheck clock
is provided during this time to all output boards causing output port check data to be
circulated and stored. Control signals C1 and C2 control this operation for even and odd
recheck cycles.
Circulate mode 4: this is the same as circulate mode 3 except that the circulation
process is interrupted after 1 ms. At this time the output state may be changed to
enforce special output checks, for example, hot and cold filament checks.
The 16-bit I/O data bus forwards data derived from input port tests, output port tests and
Vital timer operation to a serial input of each register, which is shifted in 8-bit blocks.
The registers are then accessed by the main CPU where the data is retrieved in parallel
format.
Each register’s serial input is dedicated to an I/O data bus line. This allows the system
to access 16 Vital inputs or Vital outputs. Data is loaded into the register either by a
read operation (INTMRD) with YIN active or by the output verification logic. The
registers are accessed by a memory read operation with YADR-YSR active. A three-toeight decoder provides a register pair output enable signal based on the state of three
address bits, when registers are read by the CPU.
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Vital Printed Circuit Boards
Data derived from outputs is connected directly to the register shift left input. Input test
data, however, is obtained from the I/O bus and routed through a SIGNATURE header.
This header possesses 16 input-to-output path assignments, the output of which is
connected to each of the 16 register shift right inputs. Each header takes as an input a
certain data bus line and swaps it with another. For example, header input is data bus 1
and output is routed to data bus 9, which is tied to shift register 9. This scrambling of the
data bus when reading Vital input data is used to verify correct Vital input addressing.
IOBUS logic controls the Vital I/O bus that communicates over the system Motherboard.
It provides buffered outputs for board addressing (IOAB1-4), data passage via bidirectional data bus (IODB0-F), read and write data controls, output recheck controls,
and memory mapped controls for communicating with a Vital timer (T-OUTC3, TIMC4).
T-OUTC3 also accesses the low current output check circuitry on a lamp drive output
board.
5.8.3
Interface Connections
The I/O Bus board has three connections to the VPI system. P1 connects to the System
bus, P2 carries board power and address selection signals and P3 provides connection
to the Expansion bus (when an Extended system is used). Refer to Volume 2 of this
manual for detailed pinout information.
5.8.4
Specifications
Table 5–20. I/O Bus Interface Specifications
Characteristic
Specification
Maximum number of boards per VPI System
4
Board slots required
1
Maximum Board Logic Current Supply
300 mA
Signature Header 59473-871-01
Board 1
Signature Header 59473-871-02
Board 2
Signature Header 59473-871-03
Board 3
Signature Header 59473-871-04
Board 4
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.9
5.9.1
DI (DIRECT INPUT) BOARDS, P/N 59473-867
General
Direct Input boards contain 16 isolated Vital inputs, each requiring two connections to
the field (-IN and +IN). The inputs are DC current sensing and require a minimum of
12.8 mA. The maximum input current is 33 mA. Two inputs may be connected in
parallel with opposite polarity (i.e. input A+ connected to input B-, and input Aconnected to input B+) to form a bipolar input (except for board 59473-867-03).
Each input has an LED indicator that is on when the input is on (i.e. current flow from
+IN to -IN terminals). Input circuit indicators are recessed from the edge of the board
and are placed in sequence from 1 to 16 corresponding to inputs 1 to 16 (counting from
the top of the board down). The board has two other indicators: the first one (the top
one of the two located in the middle of the board near the board edge) is on for about
100 ms when data is read from the board. The second one (the lower of the two in the
middle of the board) is on for about 100 ms when data is written to the board. These
indicators flash once each second when the system is operating normally.
Each input board interfaces with the data bus through a signature header. This
signature header is created on the boards by a programming plug inserted in the socket
labeled IC35. When a system is configured, a specific signature is assigned to each
input slot. If an input board is changed, the correct signature must be inserted in the
new board for that slot. The correct signature for that slot is listed on the module cover.
The Alstom drawing number for the signature header is 59473-871 (see Appendix F for
more information). Figure 5-21 shows a block diagram for the Direct Input boards. The
input circuitry provides a means of safely reading the presence of a DC voltage at the
field terminals of the input and converting it to a form usable by the main processing
system. In the same way that a Vital relay makes its front contacts if, and only if, power
is applied to its coil, this input circuitry allows its true, or on, status to be indicated to the
main processor (via a digital word) if, and only if, power is applied to its input terminals.
In this scheme, all circuit failures result in the input being interpreted as off or false,
which is the more restrictive condition.
All 16 inputs on a direct input board are read at once by sending a serial bit stream to
each input, one bit at a time, and then reading the results. The system outputs the first
bit of the serial bit stream to each of the 16 inputs. It then reads the result of these bits
at the output of each of the 16 inputs. Then the system outputs the second bit until the
entire bit stream has been sent to the inputs and the results read back. The resultant bit
pattern, called a word, represents the status of that input. The serial bit streams sent to
the inputs are unique for each input and, therefore, the word that results (when an input
is on) is unique for that input. For an input that is off, the returned word contains all
zeroes.
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Vital Printed Circuit Boards
Since this is a serial process, the resultant data is presented to the main processor in a
serial form. The main processor cannot efficiently use the data in this form. Therefore,
the resultant data is stored in shift registers on the I/O bus interface board and then is
read by the main processor in a parallel process. This process is done in 8-bit segments
because the shift registers are 8 bits long. Thus, the first 8 bits of the serial-bit stream
are transmitted to the inputs one bit at a time and the resultant bits are stored in the shift
registers.
Special attention is given to the reading of input checkwords to prevent induced AC
from causing incorrect input sensing. This AC noise immunity is obtained by Vitally
spacing the reading of adjacent 8-bit segments of the 32-bit checkwords. Early
generations of VPI (CAA 31746-001 through -004) used Vital time delays of 7, 7 and 7
ms between 8-bit segments 1-2, 2-3 and 3-4 (respectively). More recent VPI
implementations (CAA 31746-005 and later) use spacing of 7, 12 and 7 ms between 8bit segments 1-2, 2-3 and 3-4 (respectively).
Each input is read twice using two different 32-bit words (one word for each of the two
processing channels). At the completion of this operation, only those inputs that are
sensing current will produce the correct on 32-bit word in both channels for the CPU to
use in evaluating the expressions.
ADDRESS
+IN
ADDRESS
DECODER
ADDRESS
SELECT
A
WRITE
LOGIC
B
I/O
BUS
-IN
READ
LOGIC
16 ISOLATED INPUTS
1 OF 16 TYPICAL
SIGNATURE
Figure 5-21. DI (Direct Input) Board Block Diagram
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Vital Printed Circuit Boards
5.9.2
Operating Example
The presence of a ‘0’, or low, on the write logic output line(s) causes optoisolator A to
turn on. When this isolator turns on, its output transistor effectively diverts the current
away from the input of optoisolator B, causing its output to turn off. This in turn places a
‘1’, or high, on the input to the read logic. Similarly, if the write logic output is a ‘1’, the
resultant input to the read logic is ‘0’. If there is no current flow (from the field) between
the +IN and -IN terminals, then there is no current at the input of optoisolator B to be
diverted to the output transistor of isolator A. Thus, the output of isolator B remains in a
high ‘1’ state all the time. Because the circuit has additional transistor stages, the
returned data for an “off” input contains all zeros. The field input for each of these inputs
contains a low-pass filter comprised of a 22 mFd capacitor and a 267Ω resistor. The
purpose of this filter is to attenuate induced AC signals.
5.9.3
Interface Connections
The Direct Input board has three connections to the VPI system. P1 connects inputs 9
through 16 via a 36-way I/O interface connector. P2 carries power, address, and Vital
I/O signals. P3 connects inputs 1 through 8 via a 36-way interface connector. Refer to
Volume 2 of this manual for detailed pinout information.
Address Signature Header
Appendix F lists the address signature headers' drawing number and signature letter
used for board address definition with the VPI system.
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Vital Printed Circuit Boards
5.9.4
Specifications / Assembly Differences
Table 5–21. Direct Input Specifications/Assembly Differences
Characteristic
Specification
59473
Assembly
Variations
-867-01
-867-02
-867-03
-867-04
Maximum number of
Boards per VPI
System
10 (with CPU)
20 (with CPU/PD)
Board slots required
1
Maximum Board Logic
Current Supply
-867-05
-867-07
300 mA
Minimum Input
Voltage/Port
9.0 VDC
9.0 VDC
9.0 VDC
45.0 VDC
9.0 VDC
24.0 VDC
Maximum Input
Voltage/Port
15.0 VDC
15.0 VDC
15.0 VDC
55.0 VDC
22.0 VDC
34.0 VDC
Input Transient
Protection Voltage
(Max Voltage)
1700 Vrms
Input Transient
Protection Energy
(Max Energy)
3.6 Joules
Isolation Between
Inputs
> 3000 Vrms
Address Signature
Header Required
Yes
Equipped with LowPass Filter
Yes
No
No
Yes
Yes
Yes
Momentary Input Hold
No
No
Yes
(see
Warning)
No
No
No
WARNING
The 59473-867-03 assembly input circuit possesses the ability to rectify AC
signals and is intended for special situations only. Consult Alstom on its use.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10
5.10.1
VITAL DC OUTPUT BOARDS, P/N 59473-739, -747, -977, -749
General
There are four types of Vital DC Output boards: single break (SBO) 59473-739, double
break (DBO) 59473-747, double break 50 V (DBO-50V) 59473-977 and lamp driver
(LDO) 59473-749. All are configured with eight Vital outputs per board. The single break
output is analogous to a single relay contact placed in the positive or feed side of the
circuit. The equivalent to the relay contact in the solid state circuit is the FET switch.
The double break output is analogous to a relay circuit with the contacts in both the feed
and return sides of the circuit. With the solid-state equivalent, however, each output is
completely isolated from all other outputs and/or power supplies.
Ten LED indicators are on each output board. The top indicator lights for about 50 ms
every time data is read from the board. Under normal conditions this indicator appears
to be “on” all the time because the main processing system reads the output check data
from the output boards every 50 ms. The second indicator lights for 50 ms every time
data is written to this board. Since the system does this once per second (twice for
flashing outputs), this indicator flashes once or twice per second under normal
conditions. The remaining 8 indicators represent the status of the 8 outputs. Each
indicator lights only when the system requests the associated output to turn on. The
third indicator from the top of the board is for output number 1 and the last indicator on
the board is for output number 8.
Eight outputs on each board are divided into two groups of four. Outputs 1-4 are
connected to one power supply input, while outputs 5-8 are connected to a second
power supply input. These power supply inputs may be connected to different power
supplies or they may be tied together external to the VPI module. If the outputs are
being used in a Vital application, the power supply must come from a source that can be
Vitally turned off (usually a contact of the VPI Vital relay or one of its repeaters).
Each output board is assigned a Signature PROM (see Appendix F for more
information) that contains a unique set of data for each of the outputs on that board.
These data are tied into the board addressing and are used to prove that there are no
addressing failures. They are also used by the output check circuitry to prove the status
of the output. When an output board is changed, this PROM must be changed to the
new board. If an output board is missing its PROM or contains a wrong PROM, the
system will not operate.
Figure 5-22 shows a block diagram of the SBO, DBO, DBO-50V and LDO boards. For
these boards, the outputs are turned “on” by writing a ‘1’ to the output and turned “off”
by writing a ‘0’. The main processing system controls the status of the outputs by setting
the data bus lines to the data pattern corresponding to the desired output on/off status
and writing that data to the output board. Since the system has a 16-bit wide data bus,
16 outputs can be updated at once.
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Vital Printed Circuit Boards
To accomplish this, two output boards are given the same address and one board is
connected to the lower half of the data bus and the other is connected to the upper half.
For the board on the lower half of the bus, output 1 corresponds to data bus line 0 and
output 8 to data bus line 7. For the board on the upper half, output 1 corresponds to
data line 8 and output 8 will be data line F.
Besides turning the outputs on and off, the VPI system checks each output to ensure it
is in the correct state. To do this, each output circuit monitors its output current flow.
This circuitry, called an Absence Of Current Detector (AOCD), passes a digital signal if,
and only if, the current in its output winding is less than a specified level.
Each output board contains the necessary logic to circulate a digital word through the
AOCD, read the resultant word at the output of the AOCD, divide it by a preset
polynomial, and store the result. Every 50 ms the main processor reads the result of this
process. If the output is in the off state, the result indicates that there was no current
flow for the entire 50 ms period.
WARNING
VPI users must confirm that output device current requirements are
consistent with AOCD current threshold characteristics.
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Vital Printed Circuit Boards
A step-by-step breakdown of this circuit's operation follows:
•
Each output board has a unique signature header that is a 32 × 8 PROM (39780-3).
The PROM contains eight 32-bit words arranged vertically. These words are
clocked serially through the AOCD associated with each output at a rate of 1 bit
every 128 µs.
•
The 32-bit word is cycled through the output's AOCD 11 consecutive times. This
requires 11 × 32 × 128 µs = 45,056 µs.
•
All serial data streams circulated through each of the eight AOCDs are compressed
into eight 32-bit words in RAM (which is made up from two 256 × 4 RAMs). The
compressed data appear vertically in the RAM.
•
The data are compressed via eight individual polynomial dividers that operate
simultaneously. One of two polynomials of the 32nd degree is configured for either
an even or odd recheck cycle.
•
At the end of a verification cycle, the value of a particular 32-bit vertical result in
RAM is the correct value if, and only if both of the following two statements are true:
•
•
–
there were no failures in the AOCD circuitry
–
the current in the AOCD output winding was below the specified threshold for
the entire verification period
For a given output, the unique 32-bit result depends on the polynomial used during
the verification cycle:
–
the polynomial used is pe(x) for even 50 ms recheck cycles and po(x) for odd
recheck cycles
–
by using different polynomials on adjacent recheck cycles, it proves that the 32bit result was calculated during the current 50 ms and not left over from a
previous recheck period
The data compression in RAM is accomplished by manipulating the RAM to
simulate a 32-bit feedback shift register that represents the desired polynomial.
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Vital Printed Circuit Boards
The RAM address PROM is 512 × 8 and it is divided into four 128 × 8 sections. Two of
the sections contain the address sequences that represent the two diverse primitive
polynomials. The remaining two sections contain the address sequences needed to
read the collected compressed data from the RAM and the sequence needed to
initialize the RAM to all “ones”. The RAM is initialized at the beginning of each recheck
cycle.
Control logic for synchronizing and clocking this circuitry is contained on the I/O bus
interface board.
Operation of this circuitry is divided into four modes:
1. READ MODE: In the read mode, the data from the RAM is read. Since the read
data is stored vertically in RAM, each group of 8 bits represents one bit of each of
the eight words. This data is serially clocked into shift registers on the I/O bus
interface board. Each shift register receives one bit for each read operation. After
eight read operations, a particular shift register contains eight of the 32 bits of a
particular output's checkword. The shift register data is then stored in the CPU
memory. This process continues until the entire 32-bit word is read and stored for all
the outputs.
2. WRITE MODE: In this mode, the RAM is filled with all “ones”.
3. CIRCULATE MODE (11): In this mode, the even or odd polynomial is selected
depending on which recheck cycle is in process and the 32-bit words are cycled
through the AOCD circuitry 11 times.
4. CIRCULATE MODE (1): This mode circulates the first eight bits of the 32-bit word
through the AOCD circuitry and then stops. This allows the state of the output to be
changed, after which circulate mode 11 is invoked to complete the recheck cycle.
Special tests can be run on selected outputs, such as a hot or cold lamp filament
check. The returned 32-bit word obtained by this mode of operation is unique and
indicates that the desired test was performed correctly.
Note: When this test is required for current and filament checking, a
wire wrap jumper is installed between pins 35 and 36 on the
Motherboard in the slot for that output board.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.2
Interface Connections
Each of the Vital Output Boards has three connections to the system: P1, P2, and P3.
Refer to the appropriate board drawings in Volume 2 of this manual for detailed pinout
information.
ADDRESS
8 OUTPUTS
ADDRESS
DECODER
+V
+5
AOCD
ADDRESS
SELECT
A
WRITE
LOGIC
OUT
I/O
BUS
RECHECK
DRIVE LOGIC
READ
LOGIC
TYPICAL SINGLE BREAK
HI/LOW
BUS SELECT
RECHECK
LOGIC (PD)
AOCD
SEL
+V
+5
+
DC/DC
CONVERTER
OUT
-
TYPICAL DOUBLE BREAK
A
AOCD
OUT
+5
+5
- BATT.
FILAMENT CHECK
(1st RCK Cycle, 1mS)
TYPICAL LIGHT DRIVE
Figure 5-22. Vital Output Board Block Diagram
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Vital Printed Circuit Boards
5.10.3
5.10.3.1
SBO Board
SBO Specifications
The single break output is analogous to a single relay contact placed in the positive or
feed side of the circuit. The equivalent of the relay contact in the solid-state circuit is the
FET switch.
Iout
Vin
SBO
LOAD
Figure 5-23. SBO Block Diagram
Table 5–22. Single Break Output Specifications
59473-739
Specification
-01
-02
Maximum Number of Boards Per VPI II System
40
Board Slots Required
1
Number of Ports per Board
8
Maximum Board Logic Current Supply
500 mA
Minimum Switched Output Supply Voltage (Vin)
9.0 VDC
Maximum Switched Output Supply Voltage (Vin)
30.0 VDC
Typical Output Voltage Drop
1.0 VDC
Maximum Switched Power
15 watts
AOCD Current Threshold
3 mA max
Maximum Output Current Per Port (Iout)
500 mA
Isolation Between Outputs and 5 Volt Logic
> 3000 Vrms
Address Signature PROM Required
Yes
Code Energy Switching
No
Yes
Group Energy Filtered
Yes
No
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Vital Printed Circuit Boards
WARNING
The SBO board may fail with up to 3 milliamperes of output leakage current
with the system requesting the output to be in the de-energized state. To
prevent a potential unsafe condition, any load device attached to a low
current Vital output circuit board must not operate and must de-activate
above 3 milliamperes. This includes all environmental operating conditions
and all operating values of the load device over its service life. Failure to
follow this requirement may lead to unexpected operation of the load device.
5.10.3.2
Assemblies
Table 5–23. Single Break Output Board Assembly Differences
Description
Part Number
SBO Board Assembly, 8 outputs (9 - 15 VDC)
Group energy is filtered
59473-739-01
SBO Board Assembly, 8 outputs (9 - 15 VDC)
Group energy is not filtered, supports use of coded energy
59473-739-02
Signature PROM
(one for each output board in a system, determined by CAA)
39780-003-01
through
39780-003-40
5.10.3.3
Test Points
Table 5–24 lists the SBO board test points.
Table 5–24. SBO Board Test Points
Test Points
TP1
+5V, power
TP2
COM, common
TP3, TP4, TP5 TP6, TP7, TP8, TP9
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Vital Printed Circuit Boards
5.10.4
DBO and DBO-50V Board
The double break output is analogous to a relay circuit with the contacts in both the feed
and return sides of the circuit. With the solid-state equivalent, however, each output is
completely isolated from all other outputs and/or power supplies. Each output is isolated
by using individual DC/DC converters that meet or exceed AAR isolation requirement.
Iout
Vin
DBO
Vout
LOAD
Figure 5-24. DBO Block Diagram
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Vital Printed Circuit Boards
5.10.4.1
DBO and DBO-50V Specifications
Table 5–25. DBO/DBO-50 Board Specifications
59473Description
747-01
747-02
747-03
Maximum number of Output
Boards per VPI II System
40
Board slots required
1
Number of ports per board
8
Maximum Board Logic
Current Supply
977-01
977-02
500 mA
Minimum Input Voltage (Vin)
9 VDC
9 VDC
9 VDC
30 VDC
45 VDC
Maximum Input Voltage (Vin)
15 VDC
15 VDC
15 VDC
40 VDC
55 VDC
Minimum Output Voltage
(Vout)
6 VDC
17.7
VDC
6 VDC
45 VDC
45 VDC
Maximum Output Voltage
(Vout)
15 VDC
34.5
VDC
15 VDC
55 VDC
55 VDC
Maximum Output Current
per Port (Iout)
600 mA
300 mA
600 mA
140 mA
140 mA
Maximum Output Power per
Port
9W
9W
9W
7.7 W
7.7 W
Typical AOCD operating
threshold
3 mA
3 mA
3 mA
3 mA
3 mA
Isolation Between Outputs
> 3000
Vrms
> 3000
Vrms
> 3000
Vrms
> 3000
Vrms
> 3000
Vrms
Signature PROM Required
Yes
Yes
Yes
Yes
Yes
WARNING
The DBO board may fail with up to 3 milliamperes of output leakage current
with the system requesting the output to be in the de-energized state. To
prevent a potential unsafe condition, any load device attached to a low
current Vital output circuit board must not operate and must de-activate
above 3 milliamperes. This includes all environmental operating conditions
and all operating values of the load device over its service life. Failure to
follow this requirement may lead to unexpected operation of the load device.
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Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.4.2
Assemblies
Table 5–26. DBO Board Assemblies
Description
Part Number
DBO Board Assembly, 8 outputs
(9 - 15 VDC operation)
Note: Not for new designs since board keying is the same as
that for 747-02 assembly
DBO Board Assembly, 8 outputs with doubled output voltage
(9 - 15 VDC in with 18 - 30 VDC output)
59473-747-01
59473-747-02
DBO Board Assembly, 8 outputs
(9 - 15 VDC operation)
Note
Preferred for new designs since board keying is
different than that for 747-02 assembly
59473-747-03
DBO Board Assembly, 8 outputs
(30 - 40 VDC operation)
59473-977-01
DBO Board Assembly, 8 outputs
(45 - 55 VDC operation)
59473-977-02
Signature PROM
(one for each output board in a system, determined by CAA)
39780-003-01
through
39780-003-40
5.10.4.3
DBO and DBO-50V Board Test Points
Table 5–27. DBO Board Test Points
Test Points
TP1, TP2, TP3, TP4, TP5
used for factory test
TP7
+5V, power
TP8
COM, common
Table 5–28. DBO-50V Board Test Points
Test Points
E1
+5V, power
E2
COM, common
P2086B, Volume 1, Rev. D, Nov/13
5-74
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.5
LDO Board
The lamp drive output circuit handles high current to light signal lamps. Each output
circuit can accommodate hot and cold filament checks. This output uses a FET switch in
the common or return line of the circuit. Therefore, it is necessary to supply the positive
side of the battery or signal lighting supply to the signal lamps.
LOAD
Iout
VIN
LDO
Figure 5-25. LDO Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
5-75
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.5.1
LDO Specifications
Table 5–29. LDO Board Specifications
59473Description
749-02
749-03
Maximum number of Output Boards per
VPI II System
40
Board slots required
1
Number of ports per board
8
Maximum Board Logic Current Supply
749-04
500 mA
Minimum Switched Output Supply
Voltage (Vin)
9 VDC
15 VDC
9 VDC
Maximum Switched Output Supply
Voltage (Vin)
18 VDC
30 VDC
18 VDC
2.0 A
2.9 A
2.9 A
Maximum Output Current per Port (Iout)
Typical Output Voltage Drop
1.7 VDC
Typical AOCD operating threshold
50 mA
Isolation Between Outputs and 5 Volt
Logic
Hot/Cold Filament Check
> 3000 Vrms
Yes, 100 mA Yes, 200 mA
Signature PROM Required
Hot 100 mA,
no Cold
Yes
WARNING
The LDO board may fail with up to 50 milliamperes of output leakage current
with the system requesting the output to be in the de-energized state. To
prevent a potential unsafe condition, any load device attached to a high
current Vital output circuit board must not operate and must de-activate
above 50 milliamperes. This includes all environmental operating conditions
and all operating values of the load device over its service life. Failure to
follow this requirement may lead to unexpected operation of the load device.
P2086B, Volume 1, Rev. D, Nov/13
5-76
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.5.2
Assemblies
Table 5–30. LDO Board Assemblies
Description
Part Number
LDO Board Assembly, 8 outputs
(9 - 18 VDC, 2.9 Amp. operation)
59473-749-02
LDO Board Assembly, 8 outputs
(15 - 30 VDC, 2.9 Amp. operation)
59473-749-03
LDO Board Assembly, 8 outputs
(9 - 18 VDC, 2.9 Amp. operation)
59473-749-04
Signature PROM
(one for each output board in a system, determined by CAA)
39780-003-01
through
39780-003-40
5.10.5.3
Test Points
Table 5–31 lists the LDO board test points.
Table 5–31. LDO Board Test Points
Test Points
TP1
+5V, power
TP2
COM, common
TP3, TP4, TP5, TP6, TP7, TP8, TP9
P2086B, Volume 1, Rev. D, Nov/13
used for factory test
5-77
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.6
LDO2 Board
The LDO2 is a Vital VPI Output board that interfaces with signal lamps. It provides
essentially similar functions as the LDO described above. However, this assembly offers
the following additional features for each of the eight outputs on each board assembly:
•
Sourcing Current Drive (positive side switch)
•
Non-Vital Current Monitor with Over Current Protection and Low Current Detection
•
Non-Vital Cable Integrity Check (CIC)
•
Switch Selectable AOCD Signature PROM
The board assembly together with improved Vital system software offers enhanced
CPU-PD diagnostic capability. A diagnostic interface on the board edge is provided to
permit maintenance personnel to examine the operation of the board without connecting
any other equipment.
Iout
+
VIN
LDO2
LOAD
-
Figure 5-26. LDO2 Port Interface
P2086B, Volume 1, Rev. D, Nov/13
5-78
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.6.1
LDO2 Specifications
Table 5–32. LDO2 Board Specifications
31166Description
340-01
340-02
Maximum number of Output Boards per VPI II System
40
40
Board slots required
1
1
Number of ports per board
8
8
Maximum Board Logic Current Supply
350mA
250mA
Minimum Switched Output Supply Voltage (Vin)
8 VDC
8 VDC
Maximum Switched Output Supply Voltage (Vin)
18 VDC
18 VDC
Maximum Output Current per Port (Iout)
3.3 A
3.3 A
Maximum Output Current per 4-port group
7.5 A
7.5 A
1V
1V
2.0 ±0.3 V
2.0 ±0.3 V
4.0 A
none
0.55 to 3.25
in 7 steps
none
100 mA
100 mA
Isolation Between Outputs and 5 Volt Logic
> 3000 Vrms
> 3000 Vrms
Hot/Cold Filament Check
Yes, 100 mA
Yes, 100 mA
No
No
Typical Output Voltage Drop on board
Cable Integrity Check Detection Voltage
Over Current Shutdown Threshold (t = 200 to 400 mS)
Low level current detection threshold range
AOCD operating threshold
Signature PROM Required
WARNING
The LDO2 board may fail with up to 50 milliamperes of output leakage
current with the system requesting the output to be in the de-energized state.
To prevent a potential unsafe condition, any load device attached to a high
current vital output circuit board must not operate and must de-activate
above 50 milliamperes. This includes all environmental operating conditions
and all operating values of the load device over its service life. Failure to
follow this requirement may lead to unexpected operation of the load device.
P2086B, Volume 1, Rev. D, Nov/13
5-79
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.10.6.2
Assemblies
Table 5–33. LDO2 Board Assemblies
Description
Part Number
LDO2 Board Assembly, 8 outputs
(8 - 18 VDC, 3.3 Amp. operation)
31166-340-01
LDO2 Board Assembly, 8 outputs w/o current monitor
(8 - 18 VDC, 3.3 Amp. operation)
31166-340-02
5.10.6.3
LDO2 Board Test Points
Table 5–34. LDO2 Board Test Points
Test Points
TP3, TP39
+5V, power
TP5, TP36
-V1
TP7, TP13, TP27, TP40
COM, common
TP17
+V1
TP29
+V2
TP1, TP2, TP4, TP6,
TP8 - TP12, TP14 - TP16, TP18 - TP26,
TP28,
TP30 - TP35, TP37, TP38, TP40 - TP78
P2086B, Volume 1, Rev. D, Nov/13
used in factory test
5-80
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.11
5.11.1
ACO (VITAL AC OUTPUT) BOARD, P/N 59473-937
General
The Vital AC Output board operates in a manner similar to Vital Output boards. It is
used for lighting signal lamps or for operating other AC loads requiring less than 0.8
ampere. The board has eight outputs divided into two groups of four. Outputs 1 through
4 are connected to one power supply input while outputs 5 through 8 are connected to a
second power supply input. In Vital applications, these power supply inputs are
connected to a source that can be Vitally turned off (usually a contact of a Vital relay or
one of its repeaters).
There are three main modes of operation: READ, WRITE, and CIRCULATE as
described below.
1. READ MODE: In the read mode the data from the RAM is read. Since data is
stored vertically in the RAM, each group of 8-bits represents one bit of each of the
eight words. This data is serially clocked into shift registers on the I/O interface
board. Each shift register receives one bit for each read operation. After eight read
operations a particular shift register will contain eight of the 32-bits of a particular
output checkword. The shift register data is then stored in CPU memory. This
process continues until the entire 32-bit word is read and stored for all of the
outputs.
2. WRITE MODE: In the write mode the RAM is filled with all “ones”.
3. CIRCULATE MODE: In the circulate mode, the even or odd polynomial is selected
depending on which recheck cycle is in process and the 32-bit words are cycled
through the AOCD circuitry 11 times.
Figure 5-27 shows a block diagram of the Vital AC Output Board. The outputs of this
board are turned on by writing a ‘1’ to the output and turned off by writing a ‘0’. The
main processing system controls the status of the outputs by setting the data bus lines
to the data pattern corresponding to the desired output on/off status and writing that
data to the output board. Because the system has a 16-bit wide data bus, 16 outputs
can be updated at once. To do this, two output boards are given the same address, one
board is connected to the lower half of the data bus, and the other is connected to the
upper half. For the board on the lower half of the bus, output 1 will correspond to data
bus line 0 and output 8 will be data line 7. For the board on the upper half, output 1 will
be data line 8 and output 8 will be data line F.
P2086B, Volume 1, Rev. D, Nov/13
5-81
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
I/O
BUS
ADDRESS
SELECT
ADDRESS
SEL
ADDRESS
DECODER
5-82
HI/LOW
BUS SELECT
READ
LOGIC
WRITE
LOGIC
RECHECK
LOGIC (PD)
RECHECK
DRIVE LOGIC
+5V
AC1 COM
TYPICAL VITAL AC OUTPUT
8 OUTPUTS
AC1
Note: AC Current
flows only when FET
is turned on
+AC
OUT 1
Vital Printed Circuit Boards
Figure 5-27. ACO (Vital AC Output) Board Block Diagram
Alstom Signaling Inc.
Vital Printed Circuit Boards
Besides turning the outputs on and off, the circuit must verify each output is in the
correct state. To check the outputs, each individual output contains PROM-defined
AOCD circuitry that monitors its output current flow. The AOCD PROM chip (see
Appendix F for more information) is designated U12. The AOCD passes a digital signal
if, and only if, the current in its output winding is less than a specified level. Each output
board contains the necessary logic to circulate a digital word through the AOCD, read
the resultant word at the output of the AOCD, divide it by a preset polynomial and store
the result. Every 50 ms the main processing system reads the result of this process. If
the output was supposed to be in its off state, the result indicates there was current flow
less than 50 mA for the entire 50 ms period.
WARNING
VPI users must confirm that output device current requirements are
consistent with AOCD current threshold characteristics.
5.11.2
Jumper Configurations
In the system module, this board's address is established by wire wrapping selected
terminals P2-44, 45, 46, and/or 47 to 5V common.
When a wire wrap jumper is installed between PC2-40 and 42, the board in that slot is
connected to the lower data bus. When the jumper is installed between PC2-40 and 43,
the board is connected to the upper data bus.
5.11.3
Transient Protection
To prevent interference from transients and other local noise, this board contains EMI
and MOV filters on the outputs and capacitive filters in the power supply circuitry. These
filters are very effective in combating interference when combined with good earth
grounding of the VPI system.
P2086B, Volume 1, Rev. D, Nov/13
5-83
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.11.4
Specifications
LAMP
`
VIN
(AC)
Iout
ACO
Figure 5-28. ACO Block Diagram
Table 5–35. AC Outputs Specifications/Assembly Differences
59473-937
Specification
-02
-03
Maximum Number of Boards Per VPI
System
40
Board Slots Required
1
Number of Ports Per Board
8
Maximum Board Logic Current Supply
500mA
Minimum Switched Output Supply Voltage
90 VAC
90 VAC
Maximum Switched Output Supply
Voltage
130 VAC
130 VAC
Frequency Range
40 - 150 Hz
40 - 150 Hz
AOCD Operating Threshold
50 mA max
3 mA max
0.8 A rms
0.5 A rms
104 W
104 W
Isolation Between Outputs
> 3000 Vrms
> 3000 Vrms
Special EMI Suppression
No
Yes
Address Signature PROM Required
Yes
Yes
Maximum Output Current Per Port
Switched Power (max resistive)
P2086B, Volume 1, Rev. D, Nov/13
5-84
Alstom Signaling Inc.
Vital Printed Circuit Boards
WARNING
Low current Vital AC output boards may fail with up to 3 milliamperes of
output leakage current with the system requesting the output to be in the deenergized state. To prevent a potential unsafe condition, any load device
attached to a low current vital output circuit board must not operate and must
de-activate above 3 milliamperes. This includes all environmental operating
conditions and all operating values of the load device over its service life.
Failure to follow this requirement may lead to unexpected operation of the
load device.
WARNING
High current Vital AC output boards may fail with up to 50 milliamperes of
output leakage current with the system requesting the output to be in the deenergized state. To prevent a potential unsafe condition, any load device
attached to a high current vital output circuit board must not operate and
must de-activate above 50 milliamperes. This includes all environmental
operating conditions and all operating values of the load device over its
service life. Failure to follow this requirement may lead to unexpected
operation of the load device.
P2086B, Volume 1, Rev. D, Nov/13
5-85
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.11.5
Assembly
Table 5–36. ACO Board Assembly
Description
Part Number
ACO Board Assembly, 8 channels with enhanced EMI protection
59473-937-02
ACO Board Assembly, 8 channels with EMI suppression
59473-937-03
Signature PROM
(one for each output board in a system, determined by CAA)
39780-003-01
through
39780-003-40
5.11.6
Test Points
Table 5–37. ACO Board Test Points
Test Points
E1
+5V, power
E2
COM, common
P2086B, Volume 1, Rev. D, Nov/13
5-86
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.12
5.12.1
(FSVT) FIELD-SETTABLE VITAL TIMER BOARDS, P/N 59473-748, -894
General
The Vital Timer board contains provisions for the use of eight (8) field settable Vital
timing functions. Time setting selection is accomplished through the programming of the
time selection headers. Jumpers, i.e., shorting straps, are applied to pin headers to set
timer values for each of eight Vital timers. Eight groups of four (4) headers each are
used to specify tens of minutes, units of minutes, tens of seconds and units of seconds.
Failure to install all four jumpers for a timer or installing more than one on a header will
result in an infinite timing cycle, i.e., the timer will never time out. Figure 5-29 shows two
examples of Vital timer settings.
After the proper time settings for a particular application are selected by applying the
jumpers, a sealable cover is installed to enclose the headers. A tag, indicating the
timing function names, time setting selected, date of setting, and initials of the person
programming the time, is located on the front of the board.
On the board front edge are indicators showing which of the eight (8) timing functions
are active. In addition, test points useful in troubleshooting internal operation are
available at the board front edge.
The Vital Timer board is located on the Vital I/O bus. Normal operation is to detect the
switch setting and then perform a Vital algorithm to verify the setting of that timer's
switch.Figure 5-30 shows a block diagram of the timer board operation.
To determine the switch setting, a write operation is performed to set the base address
of switch wafer “name” PROMs. This places a logic ‘0’ on the wiper of the desired
switch while the switch decade lines are floated. The switch decade lines are connected
to the internal data bus lines 0 to 9. Upon performing the above write operation, a ‘0’ is
outputted from the name PROM and it returns to the I/O data bus and a time-setting pin
position shorts the wiper to a particular switch decade. The result is the internal data
bus consists of all ones except for the bit that funnels the name PROM position (0) to a
data bus line through the shorting strap and pin headers. This shunt position image is
then read by the CPU via the I/O bus interface board.
Once the switch position is determined (a non-vital process), verification of that switch
setting is performed. Unique data representing each of all possible switch settings are
stored in onboard EPROM. The “name” PROMs store switch wafer data while data
relating to the switch decades are stored within “label” PROMs. A name PROM output
corresponding to the setting determined by the above process is enabled, thus driving a
specific switch wafer. Next, all label PROM outputs are enabled except the one that
drives the data bus line corresponding to the switch setting. A PROM address unique
for a particular switch setting is established by storing address data into an 8-bit latch.
The latched data forms the upper eight significant PROM address bits. A binary counter
supplying the three least significant address bits is cleared.
P2086B, Volume 1, Rev. D, Nov/13
5-87
Alstom Signaling Inc.
Vital Printed Circuit Boards
The switch combination/position-select latches select one of four wiper positions on one
of eight switches for providing wiper NAME information. They also provide decoding for
the passing of decade (label) information through the 10 decade lines of all switches.
Once the PROM outputs and address have been set, verification of the switch setting is
next. A series of eight read operations takes place. Following each read, the PROM
address is incremented. Unique data, representing the switch position previously
determined, are obtained from the PROMs. Data corresponding to the wafer selected
are taken from the name PROMs and passed through the switch wiper and are returned
on a particular data bus line. Switch decade data is output from label PROMs and
placed on the data bus.
Controls for the Vital Timer board are decoded using a dual 2- to 4-bit decoder.
SET FOR
12 MINUTES, 45 SECONDS
ONE JUMPER MUST BE INSTALLED IN EACH COLUMN
JUMPER ORIENTATION:
TB1
TB2
TB3
9
TB4
9
8
8
7
7
6
6
50
5
50
5
40
4
40
4
30
3
30
20
3
2
10
0
0
20
2
10
1
0
0
T.MIN
U.MIN
1
T.SEC
U.SEC
(0 to 59 Min. & 59 Sec.)
SET FOR
4 MINUTES, 10 SECONDS
TB1
TB2
TB3
9
8
8
7
7
6
50
40
30
TB4
9
6
5
4
50
5
40
4
3
30
20
2
20
3
2
10
1
0
0
10
0
0
T.MIN
U.MIN
T.SEC
1
U.SEC
(0 to 59 Min. & 59 Sec.)
Figure 5-29. FSVT Timer Setting Examples
P2086B, Volume 1, Rev. D, Nov/13
5-88
Alstom Signaling Inc.
Vital Printed Circuit Boards
Clocking of timer data is done with a binary counter that is incremented once each time
a read operation is performed from the Vital Timer board. It must be initialized for each
switch read operation. Coincident with each read operation, data provided by the Vital
Timer board return a serial bit to each of 16 shift registers on the I/O bus interface
board. The information can be stored in the registers (for example, switch 1 position
unit's seconds with time setting of 4 seconds) as follows:
IOBUS SREG
#1 —label position #1 data (8 bits)
#2 —label position #2 data
#3 —label position #3 data
#4 —name SW#1 position #4 data
#5-16 —label position #5-16
Shift register data determines timing constants that are unique for, in this case, a 4second switch setting on switch 1. Any failure could cause reading of the wrong switch
or improper setting place wrong information in the shift registers. Timer constants,
created by shift register contents, aid in solving of Vital timer expressions within the
main VPI program.
The timer matrix is secured with standard wire lead seals run through the hole in each
threaded screw. Leads are kept short. The seal is oriented so that it does not make
contact with adjacent boards.
5.12.2
Interface Connections
The Field-Settable Vital Timer boards have three on-board connectors. Connectors P1
and P3 are normally unused; connector P2 is wired to the I/O bus. Refer to Volume 2 of
this manual for detailed pinout information.
P2086B, Volume 1, Rev. D, Nov/13
5-89
Alstom Signaling Inc.
Vital Printed Circuit Boards
5.12.3
Specifications
Table 5–38. Field-Settable Vital Timer Specifications/Assembly Differences
Characteristic
Specification
59473748-01
59473748-02
59473894-01
Maximum number of Boards per
VPI System
2
Board slots required
1
Logic Voltage Range
4.75 to 5.25 Volts
Logic Current Load (Maximum)
500 mA
Number of Discrete Timers per
board
8
Used for Vital Timers Number
1 through
8
9 through
16
1 through
8
Minimum Run Time
(minutes/seconds)
0:00
Maximum Run Time
(minutes/seconds)
59:59
Assign to I/O Bus With Signature
Header
Drawing Number (ID letter)
00/09 seconds
Jumper TB3 Timer Settings
(min/max)
0/50 seconds
Jumper TB2 Timer Settings
(min/max)
00/09 minutes
Jumper TB1 Timer Settings
(min/max)
0/50 minutes
P2086B, Volume 1, Rev. D, Nov/13
9 through
16
59473-871-01 (A)
Jumper TB4 Timer Settings
(min/max)
Time Setting Method
59473894-02
Pin Grid
Array
5-90
Pin Grid
Array
Jumper
Selection
Jumper
Selection
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
C
A
C
5-91
1 of 8
Decoder
1 of 8
Decoder
1 of 8
Decoder
1 of 8
Decoder
A
A
D
8 Bit
latch
8 Bit
Latch
Label
Prom
Label
Prom
E
8 Bit
Latch
Name
Prom
Name
Prom
A
8 Bit
Latch
Counter
E
E
D0
Through
D15
Gates
Tens
&
Units
Gates
D15
D0
D0
D9
To Matrix 1
C
C
D
1 of 8
Switch
Matricies
E
D
C
A
Enable
Data
Control Signal (3)
Address
Bus Control
and Direction
Logic
C
Bus
Trans
Bus
Trans
Vital
I/O Bus
C
to
IODB15
IODB8
IODB0
to
IODB7
Vital Printed Circuit Boards
Figure 5-30. FSVT (Field-Settable Vital Timer) Board Block Diagram
Alstom Signaling Inc.
Vital Printed Circuit Boards
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
5-92
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
SECTION 6 – NON-VITAL PRINTED CIRCUIT BOARDS
The following index describes the Printed Circuit Boards used to provide non-vital
functionality in the VPI System. This section gives a brief description of differences
between board assembly variations along with the keying information for each
assembly. The remainder of Section 6 then gives a technical description of each board
type. See Publication P2086B, Volume 3 for Non-Vital board schematics.
Table 6–1. Non-Vital Printed Circuit Boards Index (Cont.)
Board Type
Drawing
Number
Comments
CSE
59473-741-01
Basic Board, No EPROM
CSE
59473-741-02
59473-741-01 w/40026-049-00 CSE software
CSE
59473-741-03
59473-741-01 w/40026-035-00 CSE software
CSE
59473-741-04
59473-741-01 w/40026-047-00 CSE software
CSE
59473-741-06
59473-741-01 w/40026-056-00 CSE software
CSE
59473-741-07
59473-741-01 w/40026-059-00 CSE software
CSE
59473-741-08
59473-741-01 w/40026-062-00 CSE software
CSE
59473-741-09
59473-741-01 w/40026-070-00 CSE software
CSE
59473-741-10
59473-741-01 w/40026-069-00 CSE software
CSEX1
59473-938-01
Basic Board, No EPROM, jumpers for EIA423
CSEX3
31166-175-02
6 Serial Ports
CSEX3
31166-175-03
DC Code Line + 5 Serial Ports
NVI
59473-757-02
32 inputs, 18-33 VDC Source Inputs
NVI
59473-757-03
32 inputs, 9-18 VDC Source Inputs
NVID
31166-106-01
32 inputs, 4.5 - 14.5 VDC Differential, Source, Sink
NVID
31166-106-02
32 inputs, 18 - 33 VDC Differential, Source, Sink
NVID
31166-106-03
32 inputs, 9 - 16 VDC Differential, Source, Sink
NVID
31166-106-04
32 inputs, 9 - 16 VDC Differential, Source, Sink
NVID
31166-106-05
32 inputs, 18 - 33 VDC Differential, Source, Sink
NVIDSW
31166-276-01
32 inputs w/Force Input Switch, 9-18 VDC Source
NVIDSW
31166-276-02
32 inputs, 9-18 VDC Source Inputs
NVIDSW
31166-276-03
32 inputs w/Force Input Switch, 18-33 VDC Source
NVIDSW
31166-276-04
32 inputs, 18-33 VDC Source Inputs
P2086B, Volume 1, Rev. D, Nov/13
6-1
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–1. Non-Vital Printed Circuit Boards Index (Cont.)
Board Type
Drawing
Number
Comments
NVO
59473-785-01
32 outputs, 18-33 VDC, 0.25 A, Source Outputs
NVO
59473-785-02
32 outputs, 9-18 VDC, 0.25 A, Source Outputs
NVO
59473-785-03
32 outputs, 18-33 VDC, 0.25 A Source Outputs,
Power On Reset
NVO
59473-785-04
32 outputs, 9-18 VDC, 0.25 A, Source Outputs,
Power On Reset
NVO
59473-785-05
32 outputs, 4.5 – 14.5 VDC, 0.25 A, Source, Power
On Reset
NVOAC
59473-936-01
32 outputs, 5-250 VAC, 0.25 A, 47-70 HZ
NVOAC
59473-936-02
32 outputs, 5-250 VAC, 0.25 A, 47-70 HZ, Power On
Reset
NVO-SNK
31166-123-01
32 outputs, 4.5 – 14.5 VDC, 0.25 A, Sink Outputs,
Power On Reset
NVRELAY
31166-238-01
32 outputs, Relay Output Board, requiring 9–18 V
relay power
NVRELAY
31166-238-02
32 outputs, Relay Output Board, requiring 18–35 V
relay power
TWCMAIN
59473-996-01
2 Channel Transmit/Receive (Inc. -995-01, 02) with
DC/DC converter (+5 VDC in)
TWCMAIN
59473-996-02
2 Channel Transmit/Receive (Inc. -995-01, 02)
requires ± 15 VDC in
TWCAUX
59473-995-01
Manchester Encode (daughter board to –996-01,02)
TWCAUX
59473-995-02
No Manchester Encode(daughter board to –996-01,
02)
TWCATT
31166-021-01
TWC (Train-to-Wayside Communications)
Attenuator - 4 Channel
TWCATT
31166-021-02
TWC Attenuator - 2 Channel
NVTWC-MOD
31166-099-01
Basic Board w/o programmed parts, processor
based
NVTWC-MOD
31166-099-02
2 Channel TWC Transmit/Receive (Analog)
w/40026-237-00 TWC software, processor based
NVTWC-MUX
31166-100-02
4 Channel TWC Transmit/Receive (Digital)
Multiplexer w/40026-236-00 TWC software,
processor based TWC
P2086B, Volume 1, Rev. D, Nov/13
6-2
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–1. Non-Vital Printed Circuit Boards Index (Cont.)
Board Type
Drawing
Number
Comments
NVTWC-FSK
31166-119-01
Basic Board w/o programmed parts, processor
based TWC
NVTWC-FSK
31166-119-02
4 Channel Receive Only (analog) w/40025-238-00
TWC software, processor based TWC
NVTWC-FSK
31166-119-03
4 Channel Transmit/Receive (analog) w/40025-24200 TWC software, processor based TWC
NVTWC-FSK
31166-119-04
4 Channel Transmit/Receive (analog) w/40025-28400 TWC software, processor based TWC
NVTWC-FSK
31166-119-05
4 Channel Transmit/Receive (analog) w/40025-28900 TWC software, processor based TWC
NVTWC-FSK
31166-119-06
4 Channel Transmit/Receive (analog) w/40025-29500 TWC software, processor based TWC
P2086B, Volume 1, Rev. D, Nov/13
6-3
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.1
CSE (CODE SYSTEM EMULATOR) BOARD, P/N 59473-741
6.1.1
General
The Code System Emulator board, a general-purpose, single-board computer, emulates
serial code/communications systems and DC code line interfaces. It directs non-vital
information between a central control office and a remote interlocking, plus provides for
local control of an interlocking through the use of non-vital inputs and outputs.
A typical code system application consists of standard software and hardware
configured through the assignment of programmable peripherals. Peripheral
assignments are made with a wire wrapped wire harness that interconnects specific
programming pins located near the front edge of the board.
Figure 6-1 shows a block diagram of the CSE board. The CSE board uses an 8085
microprocessor. The hardware consists of fixed and programmable peripheral circuitry,
dual-ported memory, control logic, and buffering for the Non-Vital I/O bus.
>
FROM CPU
>
DUAL PORT RAM
(2K x 8)
BOARD SELECT
& DPRAM CONTROL
8085 UP
&
SUPPORT LOGIC
LOCAL 8085 BUS
ADDRESS
DECODING
MEMORY & I/O
LOCAL MEMORY
16K x 8 EPROM
8K x 8 SRAM
DEDICATED
PERIPHERALS:
0
0
1. AUTO RESET
2. TIMER GATES
PROGRAMMABLE
PERIPHERALS
120
WW
PINS
3. BAUD RATES
0
1. USART
2. ISOLATED INS
3. ISOLATED OUTS
4. TIMERS
5. INTERRUPTS
6. RS232 INTERFACE
7. LOGIC GATES
NONVITAL I/O
BUS BUFFERS &
DRIVERS
(14 ADDRESS, 8
DATA, 5 CONTROL)
TO MOTHER BOARD
NONVITAL BUS
Figure 6-1. CSE (Code System Emulator) Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-4
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Once each second all code system and Non-Vital I/O data processed by the VPI system
passes through a shared dual port memory interface. The CSE board is accessed by
the CPU board over the 60-way main system bus on the P1 connector. The module slot
where the CSE resides is programmed for a certain address by wire wrapping the
address pins. The CPU accesses the CSE dual-ported memory by placing this address
on the bus and setting in succession, two flip-flops. The first initiates an interrupt to the
CSE to flag an impending data transfer. The second produces a MAIN GRANT signal
that allows direct access to the 2K × 8 RAM. Following the retrieval from or placing of
data in RAM, the memory is released to the CSE. The CPU addresses the CSE and
resets the two arbitration flip-flops.
A 6-bit comparator produces a BOARD SELECT signal if the slot and bus addresses
are equal. The two flip-flops are controlled by addressing the CSE and setting or
resetting the least significant data bus bit. All address, data, and control lines are
buffered so as to isolate the main CPU from the local CSE bus.
Associated with the 8085 microprocessor is program memory (16K × 8) and data
memory (8K × 8). A 32 × 8 bit PROM provides the address decoding (chip selects) for
local program and data memory, external memory addresses (Non-Vital I/O), and dual
ported memory. Decoded control signals (read and write) are also provided for memory
and I/O operations. A separate 3-to-8 decoder governs chip selection for peripheral
devices in the I/O address range.
An automatic hardware reset circuit allows for a maximum of system availability. Normal
operation of the CSE provides a “holdoff” signal to the reset circuit, typically every 50
ms to disable an oscillator. Should a program fault occur to cease normal emulation, the
oscillator portion of the watchdog circuit forces a reset condition and a program restart.
Repeated resets occur until the fault has cleared.
Some peripheral logic on the CSE is dedicated for particular tasks in the emulation of
code system protocols. A Programmable Peripheral Interface (PPI) contains three ports
that can be configured as inputs or outputs. Port A drives the GATE signals for
Programmable Interval Timers (PIT). One output of Port C drives the watchdog reset
circuit. The remainder of Port C and Port B is connected to some of the 120 program
pins. Port C is an output port; Port B is an input port.
Two PITs, yielding six 16-bit timer/counters, implement time measurement, baud-rate
generation and system clocks. A crystal-controlled 1.8432 MHz clock sets the time base
that goes to three of the six timer clock inputs. Two of these timers create the baud
rates for both a dedicated and programmable communication link via Universal
Synchronous/Asynchronous Receiver/Transmitter (USARTs) peripherals. Two of the
timer outputs go to a Programmable Interrupt Controller (PIC) for CSE interrupts. The
remaining two timers are unused.
The PIC provides the CSE with an additional eight programmable interrupts. Three of
the eight interrupt inputs are fixed; two from the PIT and one generated by Non-Vital I/O
obtained from the Non-Vital bus.
P2086B, Volume 1, Rev. D, Nov/13
6-5
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
The one dedicated USART drives a current loop interface to a Handheld Terminal
(HHT) or equivalent device. This terminal interface is normally used as an interactive
troubleshooting port. Other USART inputs and outputs are connected to the
programming pins.
Other hardware whose inputs and outputs are brought to programming pins consists of
isolated inputs/outputs, EIA232 transmitters and receivers and logic gates. The isolated
inputs designed for 24V (12 mA) operation are arranged in two groups of four. One
group shares a common return while the other allows for bipolar connection of field
inputs.
Four optically isolated outputs operate from an externally connected power source. The
outputs are current sinking FET transistors capable of driving loads of 12 to 33 VDC at
250 mA maximum. Included are suppressors to protect the transistor from transients
normally produced when driving inductive loads.
To drive an EIA232 communications interface, four line drivers and receivers are
included. These drivers/receivers are also hardware-programmable and optically
isolated. The line driver operates with a ±12 VDC output swing. The undedicated
USART is normally hardwired to the line driver interface for implementing most carrierbased serial communication protocols.
Similarly, the line receivers convert a ±12 V line signal to an optically isolated 5 V logic
signal. This, too, is normally connected to the undedicated USART. Most modem
interface signals can then be implemented using the drivers and receivers (CTS, RTS,
DSR, DTR, etc.).
Eight logic gates are included with all inputs' and outputs' programmable hardware.
NAND gates are used so that a majority of logic functions (NAND, AND, OR, NOR) can
be implemented.
The CSE serves as a Non-Vital I/O controller in most applications. Its 8085 address,
data, and control signals are buffered and used to drive the Motherboard's Non-Vital I/O
bus. Peripheral boards (e.g., Non-Vital inputs and outputs) reside within a CSE
memory-mapped address range and are accessed via this bus.
P2086B, Volume 1, Rev. D, Nov/13
6-6
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.1.2
Interface Connections
The CSE board has three connections to the VPI system. P1 connects to the System
bus, P2 carries power and addressing signals, and P3 connects to the system interface
cable or field wiring. Refer to Volume 3 of this manual for detailed pinout information.
6.1.3
Specifications
Table 6–2. Code System Emulator Specifications
Charactersitic
Specification
Maximum number of Boards per VPI System
2
Board slots required
1
Maximum Board Logic Current Supply
750 mA
Supports 27128 EPROM, 200ns
Yes
Supports 27256 EPROM
No
Supports 27512 EPROM,120ns
No
Supports 27H010 EPROM,150ns
No
6.1.4
Assembly Differences
Table 6–3. CSE Assembly Differences
Specification
Alstom Part Number
Basic Board, No software
59473-741-01
59473-741-01 with 40026-049-00 software
59473-741-02
59473-741-01 with 40026-035-00 software
59473-741-03
59473-741-01 with 40026-047-00 software
59473-741-04
59473-741-01 with 40026-056-00 software
59473-741-06
59473-741-01 with 40026-059-00 software
59473-741-07
59473-741-01 with 40026-062-00 software
59473-741-08
59473-741-01 with 40026-070-00 software
59473-741-09
59473-741-01 with 40026-069-00 software
59473-741-10
P2086B, Volume 1, Rev. D, Nov/13
6-7
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.2
6.2.1
CSEX1 (CODE SYSTEM EMULATOR EXTENDED) BOARD, P/N 59473-938
General
The Code System Emulator Extended board is based on an Intel 80C186 chip and
comprises a single-board computer. This board is designed as a system board for VPI
as well as a stand-alone Non-Vital logic processor. The CSEX1 board has six serial
ports for communications to external devices, such as modems, other CSEX boards,
data loggers, etc. A DC code line interface is available, as well as EIA422 or EIA423 full
modem control interfaces.
The CSEX1 board provides interface to Non-Vital inputs and outputs and Non-Vital logic
computation for local control of interlockings. Figure 6-2 shows a block diagram of the
CSEX1 board.
The main processing element of the CSEX1 board is an 80C186 8MHz processor. The
processor has many internal functions such as timers, chip select logic and an interrupt
controller. All memory and peripheral devices are selected with the internal select logic.
Eight 28-pin IC sockets are on the CSEX1 board. Two sockets are dedicated to system
program memory (PROM), two are for application program memory (PROM) and the
remaining four are designed for static RAM chips. Jumpers are available to select the
memory size of the EPROMs.
An 82C59A Programmable Interrupt Controller (PIC) provides four external interrupt
sources, three serial controller chips, and one dual-ported memory chip.
Three Dual Asynchronous Receiver Transmitters (DUARTs) are for serial
communications. Two 88C681s and one 82530 chip comprise the hardware for six
serial channels. One channel is dedicated to a current loop converting circuit for
diagnostics. Two channels have full modem controls and the remaining three channels
have transmit and receive only.
For diagnostics, either a Maintenance ACcess Terminal (MAC) or a Handheld Terminal
(HHT) can be used. While a MAC terminal is the preferred method (see Non Vital
Diagnostics in Section 8), an HHT can be used for memory Query in the same manner
in which it is used for Vital Diagnostics.
Optoisolators and suppression Zener diodes are provided on all external communication
lines to prevent damage from power surges.
P2086B, Volume 1, Rev. D, Nov/13
6-8
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Address and data bus demultiplexing allows an external processor (CPU board) to
access a 2K × 8 dual ported memory device. This device acts as a message buffer to
pass data between the CSEX1 board and the VPI CPU board.
Address and data bus interfaces through an I/O mapped data area to the Non-Vital
input and output boards.
Light emitting diodes indicate various parameters and are discussed in Section 8,
Maintenance.
A MAX691 chip sends a reset pulse to the processor if an input bit is not toggled in a
preset time period.
P2086B, Volume 1, Rev. D, Nov/13
6-9
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.2.2
Communications Types
The CSEX1 board can be configured for either EIA422 or EIA423 communications.
WATCHDOG
TIMER
ADDRESS
CONTROL
LATCH
80C186 CPU
INTERRUPT
CONTROLLER
TIMERS
SELECT LOGIC
RESET
BUSHBUTTON
(BOARDEDGE)
82C59A
PIC
MEMORY
ARRAY
PROM/RAM
DUART 1
DUART 0
1
0
2
3
1
2
3
DUART 2
4
5
6
A
D
D
R
E
S
S
PROTECTED, ISOLATED
EXTERNAL INTERFACE
MAINTENANCE
ACCESS
TERMINAL (MAC)
DC CODE
LINE
B
U
S
D
A
T
A
B
U
S
C
O
N
T
R
O
L
L
I
N
E
S
ADDRESS
DECODER
DIAGNOSTIC
LEDs
(BOARDEDGE)
TO VPI
L
A
T
C
H
E
D
NON-VITAL
I/O
DPRAM
DECODE
( VPI )
DPRAM
PIC-IR3
Figure 6-2. CSEX1 (Code System Emulator eXtended) Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-10
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.2.3
Interface Connections
The following on-board connectors are used on the CSEX1 board:
J2
This is the serial connector for the Maintenance ACcess Terminal (MAC).
Refer to Section 8, Maintenance, for more information on connection to the MAC.
P1
This 60-pin connector carries the System bus: addresses A1 to A18, data
bus lines 0 to 15, six control lines and numerous 5V system grounds.
P2
This 50-pin connector interfaces with the VPI Motherboard which contains
5V power, system address programming and (where used) a Non-Vital I/O
interface bus.
P3
This 36-pin connector interfaces the communication lines with the CSEX1
board. All serial and DC communications are accessed through this connector.
See Table 6–4 for pin signal functions.
Table 6–4. CSEX1 External I/O Connector Assignments (Cont.)
P3
50-Way
Name
1
C1
+5V
EIA422/423 isolated power supply
2
B5
Com
EIA422/423 isolated return
3
C3
-5V
EIA423 isolated power supply
4
Dl
TDA-1
Channel 1 transmit (+)
5
C5
TDB-1
Channel 1 transmit (-)
6
D3
RTSA-1
Channel 1 request to send (+)
7
D2
RTSB-1
Channel 1 request to send
8
D5
RDA-1
Channel 1 receive (+)
9
E5
RDB-1
Channel 1 receive (-)
10
E2
CTSA-1
Channel 1 clear to send (+)
11
El
CTSB-1
Channel 1 clear to send (-)
12
E3
DCDA-1
Channel 1 data carrier detect
13
Al
DCDB-1
Channel 1 data carrier detect
14
E4
TDA-2
ISOL
Channel 2 transmit (+)
V+ DC interface power supply
15
D4
TDB-2
ISOL V-
16
Fl
RTSA-2
OUT1-DC
P2086B, Volume 1, Rev. D, Nov/13
Signal Function
Channel 2 transmit
DC interface power supply
Channel 2 request to send (+)
DC output 1
6-11
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–4. CSEX1 External I/O Connector Assignments (Cont.)
P3
50-Way
Name
17
C2
RTSB-2
OUT2-DC
18
F2
RDA-2
IN1+
Channel 2 receive (+)
DC input 1 (+)
19
A4
RDB-2
IN1-
Channel 2 receive
DC input 1
20
F3
CTSA-2
IN2+
Channel 2 clear to send (+)
DC input 2 (+)
21
B2
CTSB-2
IN2-
Channel 2 clear to send
DC input 2 (-)
22
F4
DCDA-2
Channel 2 data carrier detect
23
C4
DCDB-2
Channel 2 data carrier detect
24
F5
CLKS
Ch. 1, 2 sync. clocks (EIA423 only)
25
A2
RDA-3
Channel 3 receive (+)
26
Gl
RDB-3
Channel 3 receive (-)
27
A3
TDA-3
Channel 3 transmit (+)
28
G2
TDB-3
Channel 3 transmit (-)
29
A5
RDA-4
Channel 4 receive (+)
30
G3
RDB-4
Channel 4 receive (-)
31
Bl
TDA-4
Channel 4 transmit (+)
32
G4
TDB-4
Channel 4 transmit (-)
33
B3
RDA-5
Channel 5 receive (+)
34
G5
RDB-5
Channel 5 receive (-)
35
B4
TDA-5
Channel 5 transmit (+)
36
H1
TDB-5
Channel 5 transmit (-)
P2086B, Volume 1, Rev. D, Nov/13
Signal Function
Channel 2 request to send
DC output 2
6-12
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.2.4
CSEX1 Board Jumpers
EPROM Device Selection Jumpers (JU1 and JU2):
Device
System EPROM Jumper (JU1)
Application EPROM Jumper
(JU2)
2764
3-4, 7-8, 11-12
3-4, 7-8, 11-12
27128
1-2, 7-8, 11-12
1-2, 7-8, 11-12
27256
1-2, 5-6, 11-12
1-2, 5-6, 11-12
27512
1-2, 5-6, 9-10
1-2, 5-6, 9-10
Communication Section Jumper (JU3, JU4, JU5) applies to Ports 1 and 2 only:
Port 1 and 2 Comm.
Jumper
Jumpers IN
EIA423
JU3
JU4
JU5
1-2, 5-6
1-2, 3-4, 5-6, 7-8
1-2, 3-4, 5-6, 7-8
EIA422
JU3
JU4
JU5
2-3, 4-5
No Jumpers
No Jumpers
Watchdog Timer Jumper:
Jumper
Watchdog Selection
JU6
Active
P2086B, Volume 1, Rev. D, Nov/13
6-13
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.2.5
Specifications
Table 6–5. Extended Code System Emulator Specifications
Characteristic
Specification
Maximum number of Boards per VPI
System
4
Board slots required
1
Maximum Board Logic Current Supply
Draw
1000 mA
Supports 27128 EPROM
Yes
Supports 27256 EPROM
Yes
Supports 27512 EPROM
Yes
Port 1 Communications
EIA423, Modem Control
Port 2 Communications
EIA423, Modem Control
Port 3 Communications
EIA422
Port 4 Communications
EIA422
Port 5 Communications
EIA422
Additional Assembly Information
Basic Board No EPROM
P2086B, Volume 1, Rev. D, Nov/13
6-14
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3
6.3.1
CSEX3 (CODE SYSTEM EMULATOR EXTENDED 3) BOARD, P/N 31166-175
General
The CSEX3 (Code System Emulator eXtended) board is an upgrade for the CSEX1
(59473-938) board. It is designed as a system board for VPI as well as a stand-alone
non-vital logic processor. The CSEX3 board has six serial ports for communications to
external devices, such as modems, other CSEX boards, etc. A DC code line interface is
available as well as EIA232, EIA422 and EIA485 interfaces. The CSEX3 board provides
an interface to non-vital inputs and outputs for local control of an interlocking. Batterybacked RAM and a Real Time Clock are included for data logging. The CSEX3 board is
designed using primarily SMT (Surface Mount Technology) parts.
6.3.2
Features
Serial Ports: 6 ports total. Up to a 56K baud rate is available on all serial ports. All serial
ports are optically isolated. Serial ports 1-5 also contain suppression diodes to protect
the CSEX3 board from power surges on the communication lines. The 36-pin P3
connector is used to access serial ports 1-5. Serial ports 1 and 2 support synchronous
and asynchronous EIA232, EIA422 and EIA485. Serial port 2 also supports a DC code
line. Serial ports 3-5 support asynchronous EIA422 and EIA485. Serial Port 6 supports
asynchronous EIA232, available at the front DB-9 connector or from the backplane.
Serial port 6 is the MAC (Maintenance Access) port used for connecting to a diagnostic
terminal or personal computer for on-line diagnostic purposes.
Pin-for-pin compatible with the CSEX1 board.
Future upgrade: different versions of the P3 auxiliary board may be designed for
expanded communications capability. The address/data bus from the CPU is available
for use on the auxiliary board.
Diagnostic port for connection to a logic analyzer.
RAM: 2 Mbytes (1 Mbyte system RAM and 1 Mbyte BBRAM).
ROM: 1 Mbyte Flash ROM or 256 Kbytes EPROM.
CPU: Intel 80C186EB running at 20 MHz.
Watchdog: resets the CPU if system power fails, if the software doesn’t periodically
strobe the watchdog, or if the reset button (SW8) is pressed.
Real-Time Clock (RTC): used to keep system time. The RTC is battery-backed to keep
time when power is removed. The accuracy of the RTC is dependent on the accuracy of
the crystal. At 25°C, the worst-case deviation is approximately 1 minute/month.
DC-DC converter: provides complete isolation for the serial ports.
P2086B, Volume 1, Rev. D, Nov/13
6-15
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Dual-Ported RAM: 2 Kbytes used for a message buffer for communications with VPI’s
CPU/PD board.
Board-Edge Diagnostics: status LEDs to indicate various parameters and two 7segment displays (controlled by a three-position switch).
Non-Vital I/O: the CSEX3 board is designed to control non-vital I/O boards, including
non-vital TWC (Train-to-Wayside Communications) boards.
Battery: easily changeable button battery, with a minimum life of 48 hours for
maintaining the RTC and battery-backed RAM contents when external power is
removed.
Figure 6-3 shows the general block diagram of the CSEX3 board.
CSEX3
base
board
CSEX3
block
diagram
CSEX3
interface
board
P4
connector
suppression
circuitry
P3
connector
address/data bus
CPU
serial ports
data bus
pushbutton
reset
ports 1-5
address bus
watchdog
timer
J4
connector
address
latch
port 6
MAC port
interface via P2 or
J2 connector
(switch selectable)
RTC
power
monitor
and battery
DPRAM
P1 connector
(VPI system
bus)
non-vital
bus
interface
P2 connector
(NV I/O and
TWC bus)
batterybacked
RAM
RAM
display
drivers
LEDs and
7-segment
displays
ROM
display
switch
Figure 6-3. CSEX3 (Code System Emulator eXtended 3) Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-16
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.3
Test Points
Table 6–6 describes the test points on the CSEX3 board. Oscilloscope and clip leads
may be temporarily attached to the board using the test points. TP3, TP4, and TP5 are
always accessible, even when the board is in a system.
Table 6–6. CSEX3 Test Points
6.3.4
Test Point
Label
Connection
TP1
ISO5V
TP2
ISOCOM
TP3, TP7, TP9
+5V
+5V power
TP4, TP6, TP8
COM
common
TP5
FL WR EN/
isolated +5V power
isolated common
reserved for future use
Jumpers
Table 6–7, Table 6–8, Table 6–9, and Table 6–10 show the jumper assignments. All
possible functions have a jumper installed even though the jumper may not make an
electrical connection. This is done to ensure that there is the correct number of jumpers
(six) on the board at all times.
Table 6–7. CSEX3 Battery Selection Jumper
JP3
Function
6-8
battery disconnected (use this position for shipping and storage, or if no
battery is installed during operation)
7-8
battery connected (do not use this position if no battery is installed)
Table 6–8. CSEX3 Watchdog Selection Jumper
JP2
Function
3-5
normal operation
1-3
disable watchdog reset (for emulator use only)
P2086B, Volume 1, Rev. D, Nov/13
6-17
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–9. CSEX3 MAC Port Power Selection Jumper
JP1
Function
3-4
MAC port power disconnected
1-2
MAC port power connected (for HHT use only)
Table 6–10. CSEX3 Jumper Assignments Reserved for Future Use
JP1
JP2
JP3
5-6
6-8
1-3
Note: All three jumpers must be installed
P2086B, Volume 1, Rev. D, Nov/13
6-18
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.5
LEDs
The CSEX3 board has twenty LEDs to indicate the status of the board, the software,
and the communication ports. Table 6–11 shows the function of the LEDs. The
information in this table assumes that the LEDs are not being used by the operator for
diagnostics accessible using diagnostic switch SW11 (see “Diagnostic Display and
Switch” later in this section).
Table 6–11. CSEX3 LED Descriptions (Cont.)
LED
Label on Board
Function
DS1
ISO5V
isolated 5V is present
DS2
PWR
board power is present
DS3
RUN
CPU is running; flashes when a CPU reset occurs
DS4
APPL EXEC
non-vital application (NVA) logic is running
DS5
5TX
serial port 5 transmitting data
DS6
5RX
serial port 5 receiving data
DS7
4TX
serial port 4 transmitting data
DS8
4RX
serial port 4 receiving data
DS9
3TX
serial port 3 transmitting data
DS10
3RX
serial port 3 receiving data
DS11
2NORMAL
not used (reserved for future use)
DS12
2RX ERROR
serial port 2 error in received message
DS13
2INVAL ADDR
serial port 2 invalid (unknown) address in received
message
DS14
2RESPONSE
serial port 2 transmitting data
DS15
2ADDR OK
serial port 2 valid addressed message received
DS16
1NORMAL
not used (reserved for future use)
DS17
1RX ERROR
serial port 1 error in received message
DS18
1INVAL ADDR
serial port 1 invalid (unknown) address in received
message
DS19
1RESPONSE
serial port 1 transmitting data
DS20
1ADDR OK
serial port 1 valid addressed message received
P2086B, Volume 1, Rev. D, Nov/13
6-19
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.6
Serial Ports
All serial ports are powered by an on-board isolated 5V-5V DC-DC converter. Both the
5V and ground outputs of the DC-DC converter are completely isolated from the rest of
the circuit. When replacing a CSEX1 board, the off-board power supply used to power
CSEX1 communications may either be left connected (the incoming power pin is not
connected on CSEX3), or it may be removed (if no other boards are relying on the
power supply).
Serial ports 1 and 2 can receive and transmit the EIA232, EIA422, and EIA485
standards. Serial port 2 can also be configured as a DC code line interface. Both ports
can be configured independently, as shown in Table 6–12, Table 6–13, and Table 6–14.
Serial ports 3 through 5 can receive and transmit the EIA422 and EIA485 standards.
Table 6–12. CSEX3 Channel 1 Communication Standard Selection Switch Setting
Standard
SW7 Position
EIA422/485
all off
EIA232
all on
Table 6–13. CSEX3 Channel 2 Communication Standard Selection Switch Setting
Standard
SW4 Position
EIA422/485
all off
EIA232
all on
Table 6–14. CSEX3 Port 2 DC Code Line Communication Selection Switch Setting
Communication Mode
SW2, SW3, SW5 and SW6 Position
EIA232/422/485
all switch actuators towards front of board
DC code line
all switch actuators towards back of board,
indicated on board by DC
P2086B, Volume 1, Rev. D, Nov/13
6-20
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Serial port 6 (the MAC port) receives and transmits the EIA232 standard, and is used to
connect diagnostic equipment, such as a laptop computer, to the CSEX3 board. Switch
SW1 determines whether the MAC port’s RXD signal (an input to the CSEX3 board) is
accessible through the DB-9 connector at the front of the board, or through the
backplane (for a permanent diagnostic connection). The MAC port’s TXD signal always
transmits data to both the front and the back of the board. Table 6–15 describes the
MAC port connections through the DB-9 connector, and Table 6–16 describes the
switch settings to select between front and back MAC port access.
Table 6–15. CSEX3 MAC Port Connector Pin Assignments
Pin
Function
J3-1
–
J3-2
RXD: receive data
J3-3
TXD: transmit data
J3-4
–
J3-5
ISOCOM: isolated common
J3-6
–
J3-7
–
J3-8
–
J3-9
ISO5V: isolated +5V (only when the proper jumper is installed)
Table 6–16. CSEX3 MAC Port RXD Source Selection Switch Setting
Source
SW1 Setting
front of board (DB-9 connector)
"F"
backplane connection
"B"
P2086B, Volume 1, Rev. D, Nov/13
6-21
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
The P3 connector is used to access serial ports 1 through 5, as shown in Table 6–17.
Table 6–17. CSEX3 36-pin P3 Connections (with P/N 31166-058) (Cont.)
P3-
Name
Dir.
EIA232
EIA422 /
EIA485
1
NC
2
ISOCOM
3
NC/ISOC
OM
4
1TXD-A
O
5
1TXD-B
O
6
1RTS-A
O
7
1RTS-B
O
8
1RXD-A
I
9
1RXD-B
I
10
1CTS-A
I
11
1CTS-B
I
12
1DCD-A
I
13
1DCD-B
I
14
2TXD-A
O
15
2TXD-B
O
16
2RTS-A
O
17
2RTS-B
O
18
2RXD-A
I
19
2RXD-B
I
20
2CTS-A
I
21
2CTS-B
I
22
2DCD-A
I
23
2DCD-B
I

24
NC/ISOC
OM
25
3RXD-A
I

26
3RXD-B
I

27
3TXD-A
O

P2086B, Volume 1, Rev. D, Nov/13

DC
code
line

ARES
ATCS
(EIA232)
(EIA422)







1TXCLK-A

1TXCLK-B

















1TXCLK
1RXCLK-A

1RXCLK

1RXCLK-B


TX_V+

TX_V–

TX1

TX2

RX1+

RX1–

RX2+

(RX2–)

6-22
(RX2–)


2TXCLK-A

2TXCLK-B



2TXCLK
2RXCLK-A
2RXCLK
2RXCLK-B
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–17. CSEX3 36-pin P3 Connections (with P/N 31166-058) (Cont.)
P3-
Name
Dir.
EIA232
EIA422 /
EIA485
28
3TXD-B
O

29
4RXD-A
I

30
4RXD-B
I

31
4TXD-A
O

32
4TXD-B
O

33
5RXD-A
I

34
5XRD-B
I

35
5TXD-A
O

36
5TXD-B
O

DC
code
line
ARES
ATCS
(EIA232)
(EIA422)
 Indicates that the “Name” column identifies the signal for this protocol.
Note:
For DC code line operation on the 36-pin P3 connector, the RX2– input may
come from either of two pins (P3-21 or P3-23), which allows backwardcompatibility with CSEX1.
P2086B, Volume 1, Rev. D, Nov/13
6-23
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
NORMAL
INDICATION
ON
PCB
NOTATION
DS1
(LABEL)
FUNCTION
(ISO5V) Isolated +5V
F
SW1
B
TP3
J3
TP4
ON
ON
ON
DS2
DS3
DS4
SW8
ON, OFF
ON, OFF
ON, OFF
ON, OFF
ON, OFF
ON, OFF
DS5
DS6
DS7
DS8
DS9
DS10
TP5
(MAC F/B) Maintenance Port Selection
(Front or Back of Board)
(+5V) +5 Volts
MAC Port
(COM) Common
(PWR) System +5V Logic
(RUN) CPU Is Running
(APPL EXEC) Application Is Running
(RESET) Reset Switch
(5TX)
(5RX)
(4TX)
(4RX)
(3TX)
(3RX)
Channel 5 Transmitting Data
Channel 5 Receiving Data
Channel 4 Transmitting Data
Channel 4 Receiving Data
Channel 3 Transmitting Data
Channel 3 Receiving Data
(FL WR EN/)
Flash Write Enable
OFF
OFF
OFF
ON, OFF
ON, OFF
DS11
DS12
DS13
DS14
DS15
(2NORMAL) Channel 2 Normal, Future Use
(2RX ERROR) Channel 2 Error In Received Message
(2INVAL ADDR) Channel 2 Invalid Address In Received Message
(2RESPONSE) Channel 2 Transmitting Data
(2ADDR OK) Channel 2 Valid Address Message Received
OFF
OFF
OFF
ON, OFF
ON, OFF
DS16
DS17
DS18
DS19
DS20
(1NORMAL) Channel 1 Normal, Future Use
(1RX ERROR) Channel 1 Error In Received Message
(1INVAL ADDR) Channel 1 Invalid Address In Received Message
(1RESPONSE) Channel 1 Transmitting Data
(1ADDR OK) Channel 1 Valid Address Message Received
DS21
DS22
SW11
Diagnostic
Display
(ENTER)
(SELECT)
Test Point
LED
Figure 6-4. CSEX3 Board Indicators, Test Point Connectors and Switches
(Card Edge View)
P2086B, Volume 1, Rev. D, Nov/13
6-24
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Switch SW1 on the 36-pin auxiliary board routes the incoming receive clock signal
needed for some synchronous communication protocols, such as ARES. See
Table 6–18 for a description of the switch usage.
Table 6–18. CSEX3 36-pin P3 Auxiliary Board Communication Selection Switch (SW1)
Switch Position
Function
actuator towards P4 connector
(indicated by DCD-B on silkscreen)
normal operation mode
(maps the P3-13 input to the DCD-B
signal)
actuator towards P3 connector
(indicated by RXCLK on silkscreen)
provides external receive synchronous
clock signal
(maps the P3-13 input to the RXCLK
signal)
Pins P3-3 and P3-24 use switch SW2 on the 36-pin auxiliary board to select between
NC (no connect) and ISOCOM, used for CSEX1 vs. CSEX3 compatibility. See Table 6–
19 for a description of the switch usage.
Table 6–19. CSEX3 36-pin P3 Auxiliary Board CSEX1 vs. CSEX3 Switch (SW2)
Switch Position
Function
actuator towards P4 connector
(indicated by CSEX3 on silkscreen)
CSEX3 compatibility mode
(connects P3-3 and P3-24 to ISOCOM)
actuator towards P3 connector
(indicated by CSEX1 on silkscreen)
CSEX1 compatibility mode
(disconnects P3-3 and P3-24 from
ISOCOM)
P2086B, Volume 1, Rev. D, Nov/13
6-25
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.7
Diagnostic Display and Switch
The CSEX3 board offers a 2-digit diagnostic display used in conjunction with a 3position diagnostic input switch through which various diagnostic functions may be
accessed.
When the CSEX3 board is turned on, the diagnostic display (labeled DS21 and DS22)
normally displays “8.8.” for a moment followed by “0 0”. Other displayed codes indicate
an operational problem that resulted in a system reset.
To operate the display, use switch SW11, shown in Figure 6-4. The ENTER (up)
position is used to enter or exit a diagnostic function. The SELECT (down) position is
used to advance to the next diagnostic function and to make selections.
The diagnostic display can be used in conjunction with two sets of CSEX3 board edge
LEDs, labeled DS12 through DS15 and DS17 through DS20, to view the status of nonvital I/O ports and represent an I/O group of eight ports. When not being used for
diagnostic purposes, these LEDs are used to show communication activity on ports 1
and 2 (see Table 6–11).
Each non-vital I/O board is comprised of 32 ports consisting of four groups of eight ports
per board. To access, use the SELECT function to advance to the appropriate I/O board
and group. The output board and group numbers start with 0.0 (as shown on the
diagnostic display), whereas the input board and group numbers are offset by one and
therefore start at 1.0 (i.e. input board #1, group 0). Depress SELECT repeatedly to
advancing through output groups: 0.0 through 0.3 for the first board, 0.4 through 0.7 for
second board, 0.8 through 1.1 for third and so on. When each I/O board and group is
selected, the eight LEDs display the status of that group’s I/O ports in real time. The
LEDs are read from bottom to top, which is the reverse order with respect to the layout
of ports on the I/O boards themselves.
P2086B, Volume 1, Rev. D, Nov/13
6-26
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–20. Use the CSEX3 Diagnostic Display and Switch
Diag.
Function
Description
00
No diagnostic function is currently selected. LEDs DS12-DS15 and DS17DS20 will show communication port activity, as is the normal operational
use of these LEDs (refer to Table 6–11).
01
Show the total number of system resets since power-up, displayed in the
form “02.” (for example).
02
Test LEDs DS12-DS15 and DS17-DS20 by incrementally lighting each in
a binary pattern upon each press of SELECT.
03
Display the current state of the DC codeline relay, and test LEDs as in
diagnostic function 02.
04
Use LEDs DS12-DS15 and DS17-DS20 to show the current state of a
group of eight non-vital inputs; advance to the next input group or board
by pressing SELECT.
05
Use LEDs DS12-DS15 and DS17-DS20 to show the current state of a
group of eight non-vital outputs; advance to the next output group or
board by pressing SELECT.
06
Perform a system reset; displays “rE” (i.e. reset) when this function is
entered. To reset the CSEX3 board press SELECT, else press ENTER to
abort. After a reset thus induced, the diagnostic display will read “1d”.
P2086B, Volume 1, Rev. D, Nov/13
6-27
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.8
Troubleshooting Guide
Table 6–21. CSEX3 Troubleshooting Guide
Observation
Possible Trouble
All LEDs are off
No +5V (±0.25V) system power.
Status of LEDs does not change
Communication port interface problem.
The “Application Is Running” LED does not The non-vital application code is not
light
operational.
The “CPU Is Running” LED flashes on and
off
The operating software is not running
correctly – verify proper programming of
EPROMs.
Controls or displays do not function as
expected
CAA application logic programming or
wiring error.
Maintenance (MAC) port does not operate
properly
Check the error code shown on the 2-digit
diagnostic display.
Check the MAC port for communication
activity.
Verify wiring of the MAC port cable.
See Section 8, Maintenance, for a complete list of troubleshooting indicators and
diagnostic display error codes for CSEX3.
P2086B, Volume 1, Rev. D, Nov/13
6-28
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.3.9
Specifications
+5V power supply:
Voltage range: 4.75V to 5.25V
Typical operating current (logic and communications): 0.75A
Environmental:
Operating temperature range: −40°C to +70°C
Storage temperature range: −55°C to +85°C
Humidity: 0% to 95% non-condensing
VPI System:
Maximum number of CSEX3 boards per system: 4
Board slots required: 1
6.3.10
Assembly Differences
Table 6–22. CSEX3 Assembly Differences
Complete Board
Assembly
Function
Sub-Assemblies
Base Board
Auxiliary Board
31166-175-02
6 Serial Ports
31166-175-01
31166-187-01
31166-175-03
DC Code Line
+ 5 Serial Ports
31166-175-01
31166-187-02
P2086B, Volume 1, Rev. D, Nov/13
6-29
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.4
6.4.1
NVI (NON-VITAL INPUT) BOARD, P/N 59473-757
General
The Non-Vital Input (NVI) board provides 32 isolated, Non-Vital inputs interface through
the Motherboard to the VPI module. A CSE or CSEX board, employing Non-Vital I/O
control software, communicates over the Motherboard bus to the NVI board. Input
states are latched and read every 25 ms.
Five of the available address bus lines can access one of 20 Non-Vital I/O boards in a
VPI module. A logic comparator compares the address on the bus with the slotprogrammed address, which, if they agree, results in a BOARD SELECT signal.
Another address line latches the state of all system Non-Vital inputs.
Figure 6-5 shows a block diagram of this board. Inputs are arranged into four groups of
eight. Two additional address lines select each of the groups. These inputs as well as
BOARD SELECT go to a control PROM.
A 32 × 8 bit PROM decodes address and control line information for the execution of the
latching and subsequent input read operations. Besides the above signals, memory
read and Non-Vital address signals provide individual READ INPUT GROUP signals at
the PROM output.
As stated, inputs are latched and read on an 8-bit basis. A LATCH address signal goes
to the clock input of each of four octal latches. The READ INPUT GROUP signals
enable the latch output, allowing the status of the inputs to be presented to the NonVital data bus.
6.4.2
Isolated Inputs
Optical isolators separate the power supplies of the 5V logic system and field circuitry.
Each of the four groups of eight inputs has a separate signal return, allowing inputs
derived from four isolated supplies to share one input board.
Inputs typically draw 10 mA. Secondary transient protection is provided by a
resistor/metal oxide varistor pair in series with each input, thus giving protection against
a transient having 3.5 joules of energy or less. In locations where inputs are subject to
frequent lightning, some form of primary protection should also be used.
6.4.3
Diagnostic Aids
An indicator for each input, representing the input state from the field side is found at
the board’s front edge. In addition, outputs of the control PROM feed indicators so that
failures within address or control logic can be readily observed. Test points are also
included at critical points within the circuit to assist in troubleshooting.
P2086B, Volume 1, Rev. D, Nov/13
6-30
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.4.4
Interface Connections
NVI boards have three connections to the VPI system. P1 and P3, 36-pin connectors,
contain wiring for inputs 1-32. P2, a 50-pin connector, carries 5 volt power and
addressing signals. P2 interfaces with the Motherboard. For detailed pinout information
on these connectors, refer to Volume 3 of this manual.
DATA BUS (8)
NON-VITAL
ADDRES
S
BU
S
ADDRESS
DECODE
FOR
BOARD
SEL
( 5 ADDRESS
)
NVI INPUT
LATCHES
ISOLATED
INPUTS
IN
+
4 X 8 INPUTS
NONVITAL I/O
CONTROL PROM
(2
ADDRESS,
2 CONTROL)
POR
T
INDICATIO
N
LED
COM 1
UPDATE
OUTPUTS
DIAGNOSTIC LED'S
Figure 6-5. NVI (Non-Vital Input) Board Block Diagram
6.4.5
Specifications/Assembly Differences
Table 6–23. Non-Vital Inputs Specifications
Characteristic
Specification
P/N 59473-757-02
P/N 59473-757-03
Maximum number of Boards per CSEX
Subsystem
20
20
Board slots required
1
1
Number of ports per board
32
32
200 mA
200 mA
Minimum Input Voltage Per Port
18.0 VDC
9.0 VDC
Maximum Input Voltage Per Port
33.0 VDC
18.0 VDC
10 mA (Source)
7 mA (Source)
Maximum Board Logic Current Supply
Draw
Minimum Activation Current Per Port
P2086B, Volume 1, Rev. D, Nov/13
6-31
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.5
NVID (NON-VITAL INPUT DIFFERENTIAL) BOARD, P/N 31166-106
6.5.1
General
The Non-Vital Input Differential board provides 32 isolated Non-Vital Inputs to a VPI
system. Interface to the system is accomplished through the system Motherboard. A
Code System Emulator employing Non-Vital I/O control software communicates over
the Motherboard bus to the NVI board. Input states are latched, then read, every 25 ms.
Five of the available address bus lines are used to access one of 20 I/O boards. A logic
comparator compares the address on the bus with the slot programmed address
resulting in a BOARD SELECT if they agree. Another address line is used to latch the
state of all system Non-Vital inputs.
The inputs are arranged in four groups of eight. Two additional address lines are used
to select each of the groups. These inputs as well as BOARD SELECT are provided to
a control PROM.
A 32 × 8 bit PROM is used to decode address and control line information for the
execution of the latching and subsequent input read operations. In addition to the above
signals, memory read and Non-Vital address signals are used to provide individual
READ INPUT GROUP signals at the PROM output. The PROM combines the address
and control line inputs to provide board control signals:
READ GRP1/
- read input group #1 (8 inputs)
READ GRP2/
- read input group #2 (8 inputs)
READ GRP3/
- read input group #3 (8 inputs)
READ GRP4/
- read input group #4 (8 inputs)
BD SEL/
- slot address is addressed
I/O SEL/
- Non-Vital input address space is accessed
LATCH INPUT/
- latch states of all inputs in module
P2086B, Volume 1, Rev. D, Nov/13
6-32
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
As stated, inputs are latched and read on an 8-bit basis. A LATCH address signal is
connected to the clock input of each of four octal latches. The READ INPUT GROUP
signals enable the latch output, allowing the status of the inputs to be presented to the
Non-Vital data bus.
Optical isolators are used to separate the power supplies of the 5V logic system and the
field circuitry. Each channel has the flexibility of being set up as a double break input or
signal break input. The single break input can either source or sink current. Jumpers are
provided on the board to set the inputs to the desired configuration.
Note: Although isolation is provided to allow versatility in system
application and a degree of noise elimination, the isolation is
NOT Vital. Any field supply that is used for Vital functions
cannot be used in conjunction with this board.
Secondary transient protection in the form of a resistor/MOV pair exists in series with
each input providing protection against a transient possessing 3.5 Joules of energy or
less. In locations where inputs are subject to lightning, some form of primary protection
would be necessary.
6.5.2
Jumper Selection
There are eight sets of 8 terminal strips for a total of 64 jumpers selections related to
input mode type. For Differential mode, no jumpers are inserted. For Source and Sink
inputs, jumpers are inserted. Each channel can be independently configured as
Differential, Source, or Sink. Table 6–24 defines the terminal strips associated with each
input group (4 groups). For example, if input group 3 is to be all Sink inputs, all 8
jumpers should be inserted on TB10. If however inputs 1-4 in group 3 should be Sink,
and inputs 5-8 in group 3 should be Source then jumpers 1-4 on TB10 should be in (5-8
on TB10 out) and jumpers 5-8 on TB11 should be in (1-4 on TB11 out).
Table 6–24. Non-Vital Input Differential Jumper Selection
Input Group
Source
Sink
1
TB7
TB6
2
TB9
TB8
3
TB11
TB10
4
TB13
TB12
P2086B, Volume 1, Rev. D, Nov/13
6-33
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.5.3
Specifications
Table 6–25. Non-Vital Input Differential Specifications
Characteristic
Specification
P/N 31166-106
Assembly Variant
-01
-02
-03
-04
-05
Maximum number of Boards per CSEX
Subsystem
20
20
20
20
20
Board slots required
1
1
1
1
1
Number of ports per board
32
32
32
32
32
Maximum Board Logic Current Supply
Draw
200
mA
200
mA
200
mA
200
mA
200
mA
Minimum Input Voltage Per Port
4.5
VDC
18
VDC
9 VDC
9 VDC
18
VDC
Maximum Input Voltage Per Port
14.5
VDC
33
VDC
16
VDC
16
VDC
33
VDC
Nominal Wetting Current at Rated Input 5 ma
6 ma
3.6 ma
3.6 ma
6 ma
Input Sensitivity (min. input voltage to
be read as “1”)
0.7
2
0.9
3
13
P2086B, Volume 1, Rev. D, Nov/13
6-34
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.6
6.6.1
NVIDSW (NON-VITAL INPUT DIFFERENTIAL SWITCH) BOARD, P/N 31166276
General
The Non-Vital Input Differential Switch (NVIDSW) board provides 32 isolated Non-Vital
inputs to a VPI system. Interface to the system is accomplished through the system
motherboard. Input states are latched and then accessed every 25 ms. A CSEX board
equipped with the appropriate application logic can communicate with the NVIDSW
board through the Non-Vital Data Bus. Certain NVIDSW boards provide the ability to
physically set the state of the inputs through 32 switches located on the front of the
board. The inputs can be forced ON, OFF or to the state of the physical input.
Assemblies one and three of the NVIDSW board (31166-276-01 and 03) provide the
ability to physically set the state of the inputs through 32 switches located on the front of
the board. Assemblies two and four (31166-276-02 and 04) function identically to the
original NVID board (31166-106), and have no switches. Assemblies one and two are
rated for a 9 to 18 input voltage range. Assemblies three and four are rated for an 18 to
33 input voltage range.
Five of the available address bus lines access one of 20 Non-Vital I/O boards. The
inputs on the NVIDSW board are arranged in four groups of eight. Two additional
address lines select each of the groups. The slot address, along with these seven
address lines and two control signals are routed to an FPGA (Field Programmable Gate
Array) on the board. The FPGA processes these signals to determine if the address on
the bus matches the slot address of the board. If the two match, the appropriate 8 bits
from one of the groups is loaded to the Non-Vital Data Bus. The FPGA also outputs
signals to onboard diagnostic indicators so that failures within the address and control
logic can be readily observed.
In the case of the switched input boards (31166-276-01/03), the actual value of the
switch overrides the value that would normally be read by the FPGA off of the board
edge. The switches are three-position toggles, with a position assigned to allow the
actual value to go through, to pull the value low, or to pull the value high. The -02
assembly and -04 assembly versions of the board do not contain these switches, and
the normal value will pass through unchanged in all cases.
P2086B, Volume 1, Rev. D, Nov/13
6-35
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.6.2
Jumper Selection
The NVIDSW board is equipped with 8 jumper blocks, which allow the user to make the
board non-differential. Using these jumper blocks, the user can either source or sink
current for the inputs. The following provides a description of these blocks.
Table 6–26. Non-Vital Input Differential Jumper Selection
Jumper Blocks
TB1
Input Group 1 (i.e., inputs 1-8) Tie-up block
TB2
Input Group 1 (i.e., inputs 1-8) Tie-down block
TB3
Input Group 2 (i.e., inputs 9-16) Tie-up block
TB4
Input Group 2 (i.e., inputs 9-16) Tie-down block
TB5
Input Group 3 (i.e., inputs 17-24) Tie-up block
TB6
Input Group 3 (i.e. inputs 17-24) Tie-down block
TB7
Input Group 4 (i.e. inputs 25-32) Tie-up block
TB8
Input Group 4 (i.e. inputs 25-32) Tie-down block
6.6.3
Specifications
Table 6–27. Non-Vital Input Differential Switch Specifications
Characteristic
Specification
31166-276
Assembly Variant
-01
-02
-03
-04
Maximum Number of Boards per
CSEX Subsystem
20
20
20
20
Board Slots Required
1
1
1
1
Number of Ports per Board
32
32
32
32
Maximum Board Logic Current Supply
Draw
200
mA
200
mA
200
mA
200 mA
Minimum Input Voltage Per Port
9V
9V
18V
18V
Maximum Input Voltage Per Port
18V
18V
33V
33V
Minimum Input Current Per Port to
activate
8.6
ma
8.6
ma
8.6
ma
8.6 ma
Switches to force each input on/off
Yes
No
Yes
No
P2086B, Volume 1, Rev. D, Nov/13
6-36
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.7
6.7.1
NVO (NON-VITAL OUTPUT) BOARDS, P/N 59473-785-, 59473-936
General
The Non-Vital Output (NVO) board (59473-785) and Non-Vital Output AC (NVOAC)
board (59473-936) provide 32 isolated Non-Vital outputs interfaced through the system
Motherboard to the couplers on the back of the module or Back Plane Interface Cards
(BPIC). A CSE or CSEX board, employing Non-Vital I/O control software,
communicates over the Motherboard bus to the NVO board. Output states are latched
and updated once a second; twice a second if a flashing indication is required.
Five of the available address bus lines access one of 20 Non-Vital I/O boards. A logic
comparator compares the address on the bus with the slot programmed address; the
result is a BOARD SELECT output if they agree.
Figure 6-6 shows a block diagram of the NVO boards. Operation of the NVO and
NVOAC boards are identical except as noted in this discussion.
NVO outputs are arranged in four groups of eight. Two additional address lines select
each of the groups. These outputs, as well as BOARD SELECT, go to a control PROM.
A 32 × 8 bit PROM decodes address and control line information for the latching of the
output state. In addition to the above signals, OUTPUT WRITE and address signals
provide individual LATCH OUTPUT GROUP signals for each of four output group
latches at the PROM output. Other outputs are directed to onboard diagnostic indicators
so that failures within the address and control logic can be readily observed.
As stated, outputs are latched on an 8-bit basis. A LATCH OUTPUT GROUP signal
goes to the clock input of each of four octal latches. An OUTPUT WRITE operation puts
the desired 8-bit output port image to the group latch addressed. The latched output
states are buffered to drive optical isolators.
6.7.2
Isolated Outputs
Optical isolators separate the power supplies of the 5V logic system and field circuitry.
Each of the four groups of eight outputs possesses a separate power feed and signal
return, allowing interface with four distinctly different supplies.
Various board groups have different output voltage (see specifications). Outputs can
source up to 250 mA. Secondary transient protection in the form of a suppressor is
placed across the output-to-supply common. These suppressors afford protection
against induced transients. A series output diode protects and isolates each output as
well. Note that these outputs do not have Vital isolation.
P2086B, Volume 1, Rev. D, Nov/13
6-37
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.7.3
Diagnostic Aids
Each output contains an indicator representing its state. The LED is connected on the
field supply side. These indicators along with the output board logic control indicators
are presented on the front edge of the board. Test points for troubleshooting logic
problems are included for several onboard control signals. Refer to Volume 3 of this
manual for board layout drawings and detailed circuit views.
DATA BUS (8)
NON-VITAL
ADDRESS
BUS
1
ADDRESS DECODE
FOR BOARD
SELECT
(5 ADDRESS)
ISOLATED
OUTPUTS
32
NVO OUTPUT
LATCHES &
BUFFERS
1
SOLID
STATE
RELAY
AC
OUT 1
32
SOLID
STATE
RELAY
AC
OUT 32
4 x 8 OUTPUTS
NON-VITAL I/O
CONTROL PROM
(2 ADDRESS,
2 CONTROL)
DIAGNOSTIC
LEDS
UPDATE
OUTPUTS
Figure 6-6. NVO (Non-Vital Output) Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-38
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.7.4
Specifications/Assembly Differences
Table 6–28. Non-Vital DC Outputs (NVO) Specifications
Characteristic
Specification
P/N 59473-785
Assembly Variant
-01
-02
-03
Maximum number of Boards per
CSEX Subsystem
20
Board slots required
1
Number of ports per Board
32
Maximum Board logic Current Supply
Draw
-04
-05
500 mA
Minimum Switched Output Supply
Voltage
18.0
VDC
9.0
VDC
18.0
VDC
9.0
VDC
4.5
VDC
Maximum Switched Output Supply
Voltage
33.0
VDC
18.0
VDC
33.0
VDC
18.0
VDC
14.5
VDC
Maximum Output Current per Port
(Source)
0.25 A
0.25 A
0.25 A
0.25 A
0.25 A
Power On Reset
No
No
Yes
Yes
Yes
P2086B, Volume 1, Rev. D, Nov/13
6-39
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–29. Non-Vital AC Outputs (NVOAC) Specifications
Characteristic
Specification
59473-936-01
59473-936-02
Maximum number of Boards per CSEX
Subsystem
20
Board slots required
1
Number of ports per Board
32
Maximum Board logic Current Supply Draw
500 mA
Minimum Switched Output Supply Voltage
5.0 VAC
5.0 VAC
Maximum Switched Output Supply Voltage
250 VAC
250 VAC
0.25 A
0.25 A
Frequency Range
47 - 70 Hz
47 - 70 Hz
Power On Reset
No
Yes
Maximum Output Current per Port
P2086B, Volume 1, Rev. D, Nov/13
6-40
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.8
6.8.1
NVO-SNK (NON-VITAL OUTPUT SINK) BOARD, P/N 31166-123
General
The Non-Vital Sink Output board provides a VPI system with 32 Non-Vital, latched,
isolated, open drain, current sinking outputs, each capable of driving TTL or CMOS
logic inputs. (Note: logic inputs must be provided with an appropriate pull-up resistor.)
The outputs are divided into four groups of eight. The outputs are controlled, via the
system bus on the system Motherboard, by a Code System Emulator board (CSE or
CSEX) running Non-Vital I/O control software.
When the Code System Emulator board (CSE or CSEX) performs an input or output
operation, it places an address on certain lines of the system bus. A digital comparator,
U43, on the output board compares the states of six of the bus address lines with the
states of the slot programming inputs, jumpers on the mother board, of the card slot
where the board is located. If the states agree, the operation is intended for this board
and a BOARD SELECT signal is generated.
The BOARD SELECT signal is input to a 32 word by 8 bit PROM, U6. The other inputs
to the PROM are the write, output select and the two least significant address signals
from the system bus. The PROM combines these signals to generate an enable
(EN.DATA/) that turns on the line receivers in U41 and applies the data from the bus to
the data inputs of the four output storage registers: U27, U28, U29 and U30.
Each of the eight outputs of each output register is connected to the input of a
photoisolator so that there are 32 isolators, one for each output. When the register
contains a 0 (zero) in the location represented by the register output, the isolator is
turned on. The output transistor of each isolator is configured as an emitter follower
which, when turned on, applies the output group positive voltage to the gate of an Nchannel MOSFET transistor. The MOSFET is the board output device, which, when the
positive voltage is applied to its gate, turns on and connects the corresponding board
output to its output group return. The status of each board output is shown by an LED
indicator connected between the MOSFET drain and its group positive voltage. The
LED is lit when the corresponding board output is ON.
The MOSFET output devices are protected from reverse voltages by a Schottky diode
in series with the output. They are also protected from overvoltage transients by a
Transorb type suppressor between the output and its group return.
P2086B, Volume 1, Rev. D, Nov/13
6-41
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Previously, reference was made to a group positive voltage and a group return, plus the
arrangement of board outputs into four groups of eight. Each group of eight outputs is
provided with a separate positive supply voltage and corresponding return. The positive
voltage supplies the ON bias for the output MOSFETs and the current for the indicator
LEDs for the outputs of the group. Output load current is sinked to the return by the
output MOSFETs. Each of the four groups is electrically separated from the other three
groups and all are isolated from the board logic supply.
Note: The isolation is provided to allow versatility in system application
and a degree of noise elimination. The isolation is NOT VITAL.
Any field supply which is used for Vital functions CANNOT be
used with this board.
The board outputs can sink up to 500 mA. Output voltages are typically less than 0.6
volts at a load current of 250 mA over the temperature range from -40 to +70ºC. At a
load current of 10 mA over the same temperature range the output voltage is typically
less than 0.4 volts.
6.8.2
Diagnostic Aids
Each output is provided with an LED indicator on the edge of the circuit board to
indicate the status of that output. Seven other LED indicators on the edge of the board
show the status of various logic control signals. The status of these signals is latched
into a display register each time the Code System Emulator (CSE or CSEX) board
issues a system bus write signal.
6.8.3
Specifications
Table 6–30. Non-Vital Output Sink (NVO-SNK) Specifications
Characteristic
Specification
P/N 31166-123-01
Maximum number of Boards per CSEX Subsystem
20
Board slots required
1
Number of ports per Board
32
Minimum Switched Output Supply Voltage
4.5 VDC
Maximum Switched Output Supply Voltage
14.5 VDC
Maximum Output Current per Port
0.25 A (sink)
Power On Reset
P2086B, Volume 1, Rev. D, Nov/13
Yes
6-42
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.9
NVRELAY (NON-VITAL RELAY OUTPUT) BOARD, P/N 31166-238
6.9.1
General
The Non-Vital Relay Output (NVRELAY) board (31166-238) provides 32 Form A nonVital relay contacts interfaced through the system backplane to the couplers on the back
of the module. A CSEX board, employing non-vital I/O control software, communicates
over the motherboard bus to the NVRELAY board. Output states are latched and
updated once a second; twice a second if a flashing indication is required. Internal
circuitry on the NVRELAY board disables outputs at power-up until a CSEX board
writes to this board to initialize the outputs.
Five of the available address bus lines access one of twenty non-vital input/output
boards in a system. The NVRELAY board relays are arranged in four groups of eight.
Two address lines allow for selection of the groups (0-3). The slot address, along with
seven address lines and two control signals go to an FPGA (Field Programmable Gate
Array) on the board. The FPGA processes these signals to determine if the address on
the bus matches the slot address of the board. If the two match, the eight bits on the
data bus are stored in the selected register internal to the FPGA. The FPGA also
outputs signals to onboard diagnostic indicators so that failures within the address and
control logic can be readily observed.
Outputs are latched on an 8-bit basis. An output write operation puts the desired 8-bit
output port image to the group register addressed. The latched output states are
buffered to drive FETs (Field Effect Transistors) which in turn drive the relay coils,
enabling the appropriate LED.
When removing or inserting a NVRELAY Board for test or maintenance purposes be
sure to follow these important instructions:
•
The 5V power for this board and for the non-vital CPU board (i.e., CSEX) must be
off.
•
The external power supplies for relays and outputs to this board must also be off.
This is important because:
•
It will help to avoid damage to both the NVRELAY and other boards.
•
It will assure an orderly power-up sequence that avoids unwanted output states.
The following block diagram portrays a brief look at the interaction between the FPGA
and the various hardware registers (outputs) on the NVRELAY board.
P2086B, Volume 1, Rev. D, Nov/13
6-43
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.9.2
Isolated Outputs
Two isolating power supplies for the relay coil drive separate the power supplies of the
5V logic system and field circuitry. There are two separate power feeds, with two groups
of 8 relays running off of one power feed and signal return pair, allowing interface with
two distinctly different supplies. The power supplies are truly isolating between the input
and output sides.
The NVRELAY board is functionally equivalent to its NVO (non-vital output)
predecessors, except for power requirements and the existence of the Field
Programmable Gate Array. The outputs are grouped in four groups with eight outputs
each, as they are in the NVO board, but the outputs on the P1 and P3 connectors are
assigned two pins each, an even and an odd. If the output is currently active, these two
pins will be connected through the associated relay, allowing current flow. Table 6–31
shows the P1 connections and Table 6–32 shows the P3 connections.
Two board assembly variations have different voltage ranges for the relay power feeds
(see specifications). Secondary transient protection in the form of a suppressor is
placed across the relay contacts. These suppressors afford protection against induced
transients. Note that these relay outputs are not vitally isolated.
P2086B, Volume 1, Rev. D, Nov/13
6-44
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Figure 6-7. NVRELAY (Non-Vital Relay Output) Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-45
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–31. NVRELAY P1 Connections (Cont.)
P1-
Name
Function
Deactivated (Low)
Activated (High)
1
Group 4, Bit 7
NC (Not Connected)
connected to P1-2
2
Group 4, Bit 7
NC
connected to P1-1
3
Group 4, Bit 6
NC
connected to P1-4
4
Group 4, Bit 6
NC
connected to P1-3
5
Group 4, Bit 5
NC
connected to P1-6
6
Group 4, Bit 5
NC
connected to P1-5
7
Group 4, Bit 4
NC
connected to P1-8
8
Group 4, Bit 4
NC
connected to P1-7
9
Group 4, Bit 3
NC
connected to P1-10
10
Group 4, Bit 3
NC
connected to P1-9
11
Group 4, Bit 2
NC
connected to P1-12
12
Group 4, Bit 2
NC
connected to P1-11
13
Group 4, Bit 1
NC
connected to P1-14
14
Group 4, Bit 1
NC
connected to P1-13
15
Group 4, Bit 0
NC
connected to P1-16
16
Group 4, Bit 0
NC
connected to P1-15
17
+12V / + 24V
12V power supply (31166-238-01)
24V power supply (31166-238-02)
18
COM
Ground
19
Group 3, Bit 7
NC
connected to P1-20
20
Group 3, Bit 7
NC
connected to P1-19
21
Group 3, Bit 6
NC
connected to P1-22
22
Group 3, Bit 6
NC
connected to P1-21
23
Group 3, Bit 5
NC
connected to P1-24
24
Group 3, Bit 5
NC
connected to P1-23
25
Group 3, Bit 4
NC
connected to P1-26
26
Group 3, Bit 4
NC
connected to P1-25
27
Group 3, Bit 3
NC
connected to P1-28
28
Group 3, Bit 3
NC
connected to P1-27
29
Group 3, Bit 2
NC
connected to P1-30
P2086B, Volume 1, Rev. D, Nov/13
6-46
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–31. NVRELAY P1 Connections (Cont.)
P1-
Name
Function
Deactivated (Low)
Activated (High)
30
Group 3, Bit 2
NC
connected to P1-29
31
Group 3, Bit 1
NC
connected to P1-32
32
Group 3, Bit 1
NC
connected to P1-31
33
Group 3, Bit 0
NC
connected to P1-34
34
Group 3, Bit 0
NC
connected to P1-33
35
+12V / + 24V
12V power supply (31166-238-01)
24V power supply (31166-238-02)
36
COM
P2086B, Volume 1, Rev. D, Nov/13
Ground
6-47
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–32. NVRELAY P3 Connections (Cont.)
P3-
Name
Function
Deactivated (Low)
Activated (High)
1
Group 2, Bit 7
NC
connected to P3-2
2
Group 2, Bit 7
NC
connected to P3-1
3
Group 2, Bit 6
NC
connected to P3-4
4
Group 2, Bit 6
NC
connected to P3-3
5
Group 2, Bit 5
NC
connected to P3-6
6
Group 2, Bit 5
NC
connected to P3-5
7
Group 2, Bit 4
NC
connected to P3-8
8
Group 2, Bit 4
NC
connected to P3-7
9
Group 2, Bit 3
NC
connected to P3-10
10
Group 2, Bit 3
NC
connected to P3-9
11
Group 2, Bit 2
NC
connected to P3-12
12
Group 2, Bit 2
NC
connected to P3-11
13
Group 2, Bit 1
NC
connected to P3-14
14
Group 2, Bit 1
NC
connected to P3-13
15
Group 2, Bit 0
NC
connected to P3-16
16
Group 2, Bit 0
NC
connected to P3-15
17
+12V / + 24V
12V power supply (31166-238-01)
24V power supply (31166-238-02)
18
COM
Ground
19
Group 1, Bit 7
NC
connected to P3-20
20
Group 1, Bit 7
NC
connected to P3-19
21
Group 1, Bit 6
NC
connected to P3-22
22
Group 1, Bit 6
NC
connected to P3-21
23
Group 1, Bit 5
NC
connected to P3-24
24
Group 1, Bit 5
NC
connected to P3-23
25
Group 1, Bit 4
NC
connected to P3-26
26
Group 1, Bit 4
NC
connected to P3-25
27
Group 1, Bit 3
NC
connected to P3-28
28
Group 1, Bit 3
NC
connected to P3-27
29
Group 1, Bit 2
NC
connected to P3-30
P2086B, Volume 1, Rev. D, Nov/13
6-48
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
Table 6–32. NVRELAY P3 Connections (Cont.)
P3-
Name
Function
Deactivated (Low)
Activated (High)
30
Group 1, Bit 2
NC
connected to P3-29
31
Group 1, Bit 1
NC
connected to P3-32
32
Group 1, Bit 1
NC
connected to P3-31
33
Group 1, Bit 0
NC
connected to P3-34
34
Group 1, Bit 0
NC
connected to P3-33
35
+12V / + 24V
12V power supply (31166-238-01)
24V power supply (31166-238-02)
36
COM
6.9.3
Ground
Diagnostic Aids
Each output contains an LED (Light Emitting Diode) indicator representing its state. The
LED is controlled by a contact on the relay, and turns on when the relay is closed (which
corresponds to an active or true output). These indicators, along with the output board
control logic indicators, are presented on the front edge of the board. Test points for
troubleshooting signal problems are included. Table 6–33 describes the test points and
their locations.
Table 6–33. NVRELAY Test Points
Test Point
Function
TP1
+5V for relay power group A (near PS1)
TP2
+5V logic power (near PS1)
TP3
GND (near PS2)
TP4
+5V for relay power group B (near PS2)
TP5
GND (near FPGA)
TP6
+5V logic power (near FPGA)
P2086B, Volume 1, Rev. D, Nov/13
6-49
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.9.4
Specifications
Table 6–34. Non-Vital Relay Output (NVR) Specifications
Characteristic
Specification
31166-238-01
31166-238-02
Maximum Number of Boards per CSEX
Subsystem
20
20
Board Slots Required
1
1
Number of Ports per Board
32
32
Maximum Board Logic Current Supply Draw
500 mA
500 mA
Minimum Switched Coil Energy Supply Voltage
9.0 VDC
18.0 VDC
Maximum Switched Coil Energy Supply Voltage
18.0 VDC
35.0 VDC
1A
1A
Maximum Current per Relay Contact Port
Maximum Contact Power Rating
30 W / 62.5 VA
Maximum Contact Voltage
34.8 VDC
Power On Reset
6.9.5
3
Yes
30 W / 62.5 VA
34.8 VDC
Yes
Assembly Differences
Table 6–35. NVR Assembly Differences
Specifications
Alstom Part Number
For use with 9V to 18V power supply for relays
31166-238-01
For use with 18V to 35V power supply for relays
31166-238-02
3
This is a limit imposed by the 1.5KE43CA bi-directional suppressor. Actual contact rating is 100 VDC or 125 VAC
P2086B, Volume 1, Rev. D, Nov/13
6-50
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.10
6.10.1
TWCMAIN (TRAIN-TO-WAYSIDE COMMUNICATIONS MAIN) MODEM
BOARD, P/N 59473-996
General
The Train-to-Wayside Communications Main Modem board is part of the Train to
Wayside Communications (TWC) system. TWC is a two-way communication link
consisting of a transmitter/receiver set (Transceiver) aboard the train and a similar set in
wayside systems. The system provides a communication medium between the carcarried equipment and the wayside equipment for the transfer of routing, dispatch
information and for monitoring by Central Control.
Figure 6-8 shows a system level representation of how the TWCMAIN board interfaces
with the TWCAUX (59479-995) and TWCATT (31166-021) boards in a typical TWC
system. Two TWC Channels are housed on a single TWCMAIN board. Channel 1
interfaces to the ATP and Bond through connector P3 while channel 2 interfaces
through connector P1. All interfaces between the TWC channels and the controlling
processor (CSEX) are provided through the Non-Vital Bus, P2. As many as eight TWC
boards allow up to 16 TWC channels to be controlled by a single processor. Note that
the TWCMAIN board requires two slots in the VPI chassis.
TWCMAIN
#1
TWCAUX
#1
Wayside
Interface
Train
Wayside
Interface
Train
Wayside
Interface
Train
Wayside
Interface
Train
TWCATT
CSEX
TWCMAIN
#1
TWCAUX
#1
Figure 6-8. TWC Main Modem Board Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-51
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.10.2
System Limitations
•
Four CSEX boards per VPI system (maximum)
•
Eight TWC boards per CSEX board
•
32 TWC boards per VPI system (maximum)
•
Four TWC boards per TWC Attenuator board
•
Eight TWC Attenuator boards per system
6.10.3
Assembly Differences
Table 6–36. TWCMAIN Assembly Differences
Specification
Alstom Part Number
2-Channel Transmit/Receive, with DC/DC converter
(+5 VDC in)
59473-996-01
2-Channel Transmit/Receive, requires ± 15 VDC in
59473-996-02
P2086B, Volume 1, Rev. D, Nov/13
6-52
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.11
6.11.1
TWCAUX (TRAIN-TO-WAYSIDE COMMUNICATIONS AUXILIARY) BOARD,
P/N 59473-995
General
The Train-to-Wayside Communications Auxiliary board is part of the Train-to-Wayside
Communications (TWC) system. TWC is a two-way communication link consisting of a
transmitter/receiver set (Transceiver) aboard the train and a similar set in wayside
systems. The system provides a communication medium between the car-carried
equipment and the wayside equipment for the transfer of routing, dispatch information
and for monitoring by Central Control
This board is always used in conjunction with the TWCMAIN board (59473-996). This
board connects to the TWCMAIN board via a DIN connector (with the TWCAUX board
being a daughter board to the TWCMAIN board). The TWCAUX board contains the
timers, Manchester Encoder-Decoder (59473-995-01 only) and USART.
6.11.2
Assembly Differences
Table 6–37. TWCAUX Assembly Differences
Specification
Alstom Part Number
Uses Manchester Encoding
59473-995-01
No Manchester Encoding
59473-995-02
P2086B, Volume 1, Rev. D, Nov/13
6-53
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.12
6.12.1
TWCATT (TRAIN-TO-WAYSIDE COMMUNICATIONS ATTENUATOR)
BOARD, P/N 31166-021
General
The Train-to-Wayside Communications Attenuator board is part of the Train to Wayside
Communications (TWC) system. TWC is a two-way communication link consisting of a
transmitter/receiver set (Transceiver) aboard the train and a similar set in wayside
systems. The system provides a communication medium between the car-carried
equipment and the wayside equipment for the transfer of routing, dispatch information
and for monitoring by Central Control
The purpose of this board is to protect the Vital Filter associated with each of two
receive channels on a TWCMAIN board (59473-996). It is used during transmit to
attenuate the transmit signal level before it gets to the Vital Filter. Note that the
TWCATT board requires two slots in the VPI chassis.
Note: User must maintain Vital 1/4 inch spacing from the entrance rack all the way to
the board edge connector. Do not insert extra pins in any connectors used for this
interface.
6.12.2
Assembly Differences
Table 6–38. TWCATT Assembly Differences
Specification
Alstom Part Number
4-Channel Attenuator (handles 2 TWCMAIN boards)
31166-021-01
2-Channel Attenuator (handles 1 TWCMAIN board)
31166-021-02
P2086B, Volume 1, Rev. D, Nov/13
6-54
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.13
6.13.1
NVTWC-MOD (NON-VITAL TWC MODEM) BOARD, P/N 31166-099
General
This board is used to extract Analog Frequency information into a Digital form and pass
it on to a CSEX board as illustrated in Figure 6-9. In general TWC use, there are two
different frequencies representing a logical 1 and a logical 0 for a given communication
link. These two frequencies must both be below 10 kHz. There are a total of four
channels on the board, each one capable of recognizing one distinct frequency via a
very selective bandpass filter. In some applications, it may be desirable to use two
channels for each communications link (one to detect the logical 1 frequency and one to
detect the logic 0 frequency). In other applications it may be acceptable to simply detect
the logical 1 frequency and assume logical 0 otherwise. This board can be configured
(by Alstom) to meet a variety of applications. An onboard microprocessor and FPGAs
(programmable hardware) allow a considerable degree of flexibility.
Menu driven board diagnostics can be accessed with a VT100 terminal or equivalent.
The diagnostics will allow the user to view incoming receive messages, transmit
messages and to view commands to and from the CSEX board. In addition, a complete
self-test of the board is available via a diagnostic loop back cable. Additional information
for a specific application can be found in Alstom specific system manuals.
Digital Equivalent
1
0 1
1/Baud rate
External
Environment
Analog Frequencies
< 10 KHz
NVTWC Modem Board
(31166-099)
1
0
1
Analog Frequecy
example: 0 = 8880 Hz
1 = 5920 Hz
CSEX Board
Non-Vital
I/O Bus
Figure 6-9. NVTWC-MOD Subsystem Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-55
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.13.2
Specifications/Assembly Differences
Table 6–39. Non-Vital TWC Modem (NVTWC-MOD) Specifications
Characteristic
Maximum number of Boards per CSEX
Board slots required
Maximum Board Logic Current Supply
Number of channels
Maximum Baud Rate
Maximum detection frequency
Software
P2086B, Volume 1, Rev. D, Nov/13
Specification
P/N 31166-099-01
P/N 31166-099-02
8
1
350 mA
4
50
10 kHz
Basic board without
8
1
350 mA
4
50
10 kHz
2 Channel TWC
6-56
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.14
6.14.1
NVTWC-MUX (NON-VITAL TWC MULTIPLEXER) BOARD, P/N 31166-100
General
The purpose of this board is to process bit streams of TWC information as received
from other field equipment. These bit streams are then reformatted so that they can
then be sent to the CSEX board. The digital portion of this board is very similar to the
Non-Vital TWC Modem board. However instead of the four analog bandpass filters, this
board contains 24 Non-Vital optically isolated inputs and 8 Non-Vital optically isolated
outputs. In this manner, the Non-Vital TWC Multiplexer board can be thought of as a
“smart” Non-Vital I/O interface. This board can be configured (by Alstom) to meet a
variety of applications. An on-board microprocessor and FPGAs (programmable
hardware) allow a considerable degree of flexibility.
Menu driven board diagnostics can be accessed with a VT100 terminal or equivalent.
The diagnostics will allow the user to view incoming receive messages, transmit
messages and to view commands to and from the CSEX board. Additional information
for a specific application can be found in Alstom specific system manuals.
24 Non-Vital
Inputs
NVTWC Multiplexer
Board
(31166-100)
Digital Signals to/from
field TWC equipment
Non-Vital
I/O Bus
CSEX Board
8 Non-Vital
Outputs
Figure 6-10. NVTWC-MUX Subsystem Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-57
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.14.2
Specifications
Table 6–40. Non-Vital TWC Multiplexer (NVTWC-MUX) Specifications
Characteristic
Specification
P/N 31166-100-02
Maximum number of Boards per CSEX Subsystem
8
Board slots required
1
Maximum Board Logic Current Supply Draw
External Power Supply Requirements
6-12 VDC, 8A
Number of Inputs
24
Voltage range of Inputs
6-20 VDC
Frequency range of inputs
0 – 1000 Hz
Number of Outputs
8
Maximum Output Current per port
1A (source/sink)
Maximum Output Steady State Power per port
Frequency range of outputs
P2086B, Volume 1, Rev. D, Nov/13
350 mA
5 Watts
0 - 1000 Hz
6-58
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.15
6.15.1
NVTWC-FSK (NON-VITAL TWC FSK) BOARD, P/N 31166-119
General
The Non-Vital TWC FSK board is similar to the NVTWC-MOD board except it provides
true Frequency Shift Keying TWC. The incoming TWC messages are keyed such that
the logic 1 and logic 0 frequencies are based symmetrically around some base
frequency (example: 9650 ± 150 Hz). This board uses 4 Phase Lock Loops (1 per
channel) to decode the incoming signals. The output of the phase lock loops are then
reformatted so that they can then be sent to the CSEX board
Menu-driven board diagnostics can be accessed with a VT100 terminal or equivalent.
The diagnostics will allow the user to view incoming receive messages, transmit
messages and to view commands to and from the CSEX board. In addition, a complete
self-test of the board is available via a diagnostic loop back cable. Additional information
for a specific application can be found in Alstom specific system manuals.
Digital Equivalent
0
1 0
1/Baud rate
External
Environment
Analog FSK signals
NVTWC FSKBoard
(31166-119)
0
1
0
Non-Vital
I/O Bus
CSEX Board
Analog FSK Signals
Example: Base Frequency = 9650 Hz
Logic 1 = 9800
Logic 0 = 9500
Figure 6-11. NVTWC-FSK Subsystem Block Diagram
P2086B, Volume 1, Rev. D, Nov/13
6-59
Alstom Signaling Inc.
Non-Vital Printed Circuit Boards
6.15.2
Specifications/Assembly Differences
Table 6–41. Non-Vital TWC Multiplexer (NVTWC-FSK) Specifications
Characteristic
Specification
31166-119-02
31166-119-03
31166-119-04
31166-119-05
31166-119-06
Maximum
number of
Boards per
CSEX
8
8
8
8
8
Board slots
required
1
1
1
1
1
350 mA
350 mA
350 mA
350 mA
350 mA
4
4
4
4
4
110
110
100
4800
100
Maximum
detection
frequency
10 kHz
10 kHz
10 kHz
65 kHz
10 kHz
Software
4 Channel
TWC
Receive
only
(40025238)
4 Channel
TWC
Transmit/
Receive
(40025242)
4 Channel
TWC
Transmit/
Receive
(40025284)
4 Channel
TWC
Transmit/
Receive
(40025289)
4 Channel
TWC
Transmit/
Receive
(40025295)
Maximum Board
Logic Current
Supply Draw
Number of
detection
channels
Maximum Baud
Rate
P2086B, Volume 1, Rev. D, Nov/13
6-60
Alstom Signaling Inc.
VPI Chassis
SECTION 7 – VPI CHASSIS
7.1
GENERAL
This section serves as an overview of chassis related options including part numbers
and a brief explanation of their application. See P2086B Volume 4 for a complete
reference to chassis configuration options. Note that all part numbers are Alstom
numbers unless otherwise noted.
The Alstom Control Point In a Box (CPIB) interface chassis uses printed circuit cards
with WAGO style (spring clip) wire termination blocks and PCB edge connectors to map
the I/O termination points on the VPI PCBs to discrete wire connectors. The chassis is
designed to allow these interface PCBs to be inserted and removed from the rear of the
chassis. This provides a wire termination method that can be quickly disconnected (by
removing the PCBs).
7.2
SYSTEM MODULES (31038-249-00, 31038-274)
7.2.1
Plug Coupler Chassis
Case Complete (31506-015-01):
Connection Method: Plug Coupling
P2 Motherboard: Split Backplane (59473-743-01)
Case Complete (31506-015-11):
Connection Method: Plug Coupling
P2 Motherboard: Continuous Backplane (31166-166-01)
P2086B, Volume 1, Rev. D, Nov/13
7-1
Alstom Signaling Inc.
VPI Chassis
7.2.2
Edge Wired Chassis
Case Complete (31506-015-02):
Connection Method: Card Edge Wired
P2 Motherboard: Split Backplane (59473-743-01)
Used in Multi-Module system
Case Complete (31506-015-03):
Connection Method: Card Edge Wired
P2 Motherboard: Split Backplane (59473-743-01)
Used as stand-alone system
Case Complete (31506-015-12):
Connection Method: Card Edge Wired
P2 Motherboard: Continuous Backplane (31166-166-01)
Used in Multi-Module system
Case Complete (31506-015-13):
Connection Method: Card Edge Wired
P2 Motherboard: Continuous Backplane (31166-166-01)
Used as stand-alone system
Case Complete (31506-015-14):
Connection Method: Card Edge Wired
P2 Motherboard: Split Backplane (59473-743-01)
Used as stand-alone system
Case Complete (31506-015-15):
Connection Method: Plug Coupling
P2 Motherboard: Split Backplane (2” deeper chassis) (59473-743-01)
Used as stand-alone system
Case Complete (31506-015-16):
Connection Method: Plug Coupling
P2 Motherboard: Continuous Backplane (2” deeper chassis) (31166-166-01)
Used as stand-alone system
P2086B, Volume 1, Rev. D, Nov/13
7-2
Alstom Signaling Inc.
VPI Chassis
7.2.3
Back Plane Interface Card (BPIC)
Case Complete (31038-274-01):
Connection Method: BPIC Interface
P2 Motherboard: Split Backplane (59473-743-01)
System Boards: VRD, IOB, CPU/PD, DI and DBO
P2086B, Volume 1, Rev. D, Nov/13
7-3
Alstom Signaling Inc.
VPI Chassis
7.3
INTERCONNECTIONS
P1 Interconnection
System Bus (connects CPU, CPU/PD, VRD, VSC, IOB, CSE, CSEX)
Uses one of the following Ribbon Cables:
Location
Alstom Part Number
6 slot
38216-395-01
5 slot
38216-395-02
2 slot (2 inch)
38216-395-03
2 slot (18 inch)
38216-395-04
7 slot
38216-395-05
8 slot
38216-395-06
9 slot
38216-395-07
10 slot
38216-395-08
11 slot
38216-395-09
12 slot
38216-395-10
System Bus PC Board (31166-201-07) duplicates the functionality of ribbon cable
58216-395-01.
P2 Interconnection
Split Backplane - 59473-743-01:
Has bus split between slots 5 and 6
For use with a mixed chassis having both Vital and non-vital boards or two
subsystems of non-vital boards
Do not use Motherboard Jumper Cable part number38216-402-01 to create a
backplane for all Vital and non-vital chassis; instead use the continuous
backplane (31166-166-01)
Continuous backplane - 31166-166-01:
Has no bus split
For use with either an all Vital I/O chassis or an all non-vital I/O chassis
P2086B, Volume 1, Rev. D, Nov/13
7-4
Alstom Signaling Inc.
VPI Chassis
P3 Interconnection
For interfacing between System Bus and Extender Modules (I/O Bus board only).
Table 7–1. Ribbon Cables
Main Module Connector
Ext Mod Edge Connector
Alstom Drawing Number
1 connector
1 connector
38216-404-01
1 connector
2 connector
38216-404-02
2 connector
1 connector
38216-404-03
2 connector
2 connector
38216-404-04
2 connector
3 connector
38216-404-05
1 connector
3 connector
38216-404-06
2 connector
6 connector
38216-404-07
1 connector
6 connector
38216-404-08
P2086B, Volume 1, Rev. D, Nov/13
7-5
Alstom Signaling Inc.
VPI Chassis
7.4
CABLE AND BACK PLANE CONNECTORS
Cable from board edge to rear plug couplers (Amp type ‘M’).
Table 7–2. 38216-392 Cable Complete
Board
Board Edge
Connector
Back Plane
Connector
Coupler Row
Alstom
Drawing
Number
Vital Relay
Driver
(1) 36-pin
board edge
(1) 28-way plug
coupler
bottom
38216-392-01
CSE,
CSEX,VSC
(1) 36-pin
board edge
(1) 50-way plug
coupler
top
38216-392-02
Vital Relay
Driver
(1) 36-pin
board edge
(1) 28-way plug
coupler
middle
38216-392-03
CSE, CSEX,
VSC
(1) 36-pin
board edge
(1) 50-way plug
coupler
middle
38216-392-04
Vital Relay
Driver
(1) 36-pin
board edge
(1) 28-way plug
coupler
top
38216-392-05
CSE, CSEX,
VSC
(1) 36-pin
board edge
(1) 50-way plug
coupler
bottom
38216-392-06
CRG
(1) 20-pin
board edge
(1) 28-way plug
coupler
bottom
38216-536-01
CRG
(1) 20-pin
board edge
(1) 28-way plug
coupler
middle
38216-536-02
CRG
(1) 20-pin
board edge
(1) 28-way plug
coupler
top
38216-536-03
Note: 38216-392-01, -03, -05 are 4-conductor cables; 38216-392-02, 04, -06 are 36-conductor cables.
P2086B, Volume 1, Rev. D, Nov/13
7-6
Alstom Signaling Inc.
VPI Chassis
Table 7–3. 38216-393 Cable Complete
Board
Board Edge
Connector
Back Plane
Connector
Alstom Drawing
Number
Non-Vital I/O
(2) 36-pin board
edge
(1) 50-pin plug
coupler, 10.5"
38216-393-01
Non-Vital I/O
(2) 36-pin board
edge
(1) 50-pin plug
coupler, 6.875"
38216-393-02
Non-Vital I/O
(2) 36-pin board
edge
(1) 50-pin plug
coupler, 2.5"
38216-393-03
Table 7–4. 38216-394 Cable Complete
Board
Board Edge
Connector
Back Plane
Connector
Alstom Drawing
Number
Vital Output
(2 × 3) 36-pin board
edge
(3) 28-way plug
coupler
38216-394-01
Vital Input
(2 × 2) 36-pin board
edge
(3) 28-way plug
coupler
38216-394-02
Vital Output
(2 × 2) 36-pin board
edge
(3) 28-way plug
coupler
38216-394-03
Table 7–5. 38216-497 Cable Complete
Board
Board Edge
Connector
Back Plane
Connector
Coupler Row
Alstom
Drawing
Number
Non-Vital I/O
(2) 36-pin
board edge
(1) 75-way plug
coupler
bottom
38216-497-01
Non-Vital I/O
(2) 36-pin
board edge
1) 75-way plug
coupler
middle
38216-497-02
Non-Vital I/O
(2) 36-pin
board edge
(1) 75-way plug
coupler
top
38216-497-03
P2086B, Volume 1, Rev. D, Nov/13
7-7
Alstom Signaling Inc.
VPI Chassis
Table 7–6. Plug coupler mating connectors (AMP Type ‘M’)
Mating Connector
Alstom Drawing Number
AMP Number
28-way plug coupling
58920-124
205689-2
50-way plug coupling
58920-112
203622-2
75-way plug coupling
58920-116
201331-1
Note: When any of these connectors are used with Cable Assemblies
38216-392-01, -03, -05, only four pins should be placed in the
mating connector (do not insert extra pins). This is necessary to
maintain Vital spacing.
The following 60-conductor ribbon cables support connection of CPU/PD or CPU II
header and rear panel bulkhead mount to support connection to CPU II/CPU/PD
assembly via 38216-589-00 cable.
The following 10-conductor ribbon cables support the connection of CRG Boards to the
CPU/PD or CPU II Boards.
Table 7–7. Ribbon Cable Part Numbers
Board Connect Between
Description
Part Number
CPU/PD or CPU II
Board Header
Rear Panel VPI case
60 Conductor Ribbon
Cable, 18 inches
38216-625-01
CPU/PD or CPU II
Board Header
Rear Panel VPI case
60 Conductor Ribbon
Cable, 27 inches
38216-625-02
CRG Board 31166544-01 (P1
Interconnect)
CGR Board 31166544-01 (P1
Interconnect)
10 Conductor Ribbon
Cable, 6 inches
38216-629-00
CPU/PD or CPU II
Board 31166-543-01
(P3 Interconnect)
CRG Board 31166544-01 (P1
Interconnect)
10 Conductor Ribbon
Cable, 18 inches
38216-630-00
P2086B, Volume 1, Rev. D, Nov/13
7-8
Alstom Signaling Inc.
VPI Chassis
7.5
POWER SUPPLY
Complete assembly comes on ‘B2’ mounting plate.
Table 7–8. Melcher DC-DC Converters
Power Supply
Input Voltage
Output
Voltage/Current
Alstom Drawing
Number
(1) Single IN/Single OUT
8-35 VDC
5.1 VDC/8A
42560-273-01
(2) Single IN/Single OUT
8-35 VDC each
5.1 VDC/8A
42560-273-02
(1) Single IN/Single OUT
20-100 VDC
5.1 VDC/25A
42560-273-03
(1) Single IN/Dual OUT
8-35 VDC
15 VDC/1.7A,
15 VDC/1.7A
42560-273-04
(2) Single IN/Single OUT
8-35 VDC each
12 VDC/4A
42560-273-05
(1) Single IN/Single OUT
8-35 VDC
12 VDC/4A
42560-273-06
(1) Single IN/Dual OUT
8-30 VDC
12VDC/4A,
5VDC/8A
42560-273-07
Single IN/Dual OUT
8-30 VDC
5.1VDC/8A
42560-287-01
(1) Single IN/Dual OUT
8-30 VDC
5.1VDC/25A
42560-287-02
(1) Single IN/Single OUT,
CageClamp Terminals, PSConnector M4 Screw
8-35 VDC
5.1VDC/20A
42560-287-03
(1) Single IN/Single OUT,
CageClamp Terminals, PSConnector 0.250 Faston
8-35 VDC
5.1VDC/8A
42560-287-05
(1) Single IN/Single OUT,
CageClamp Terminals, PSConnector 0.250 Faston
8-35 VDC
12 VDC/4A
42560-287-09
(1) Single IN/Single OUT,
CageClamp Terminals, PSConnector M4 Screw
8-35 VDC
12 VDC/10A
42560-287-10
P2086B, Volume 1, Rev. D, Nov/13
7-9
Alstom Signaling Inc.
VPI Chassis
7.6
MISCELLANEOUS
Table 7–9. Miscellaneous Components
Description
Alstom
Drawing
Number
Extender Board for IOB, CPU, PD, CPU/PD
59473-744-01
Extender Board for DI, SBO, DBO, ACO, LDO, NVI,NVID,NVIDSW,
NVO, NVOAC,NVRELAY, TWCMAIN, TWCATT, NVTWC-MOD,
NVTWC-MUX, NVTWC-FSK, CRG
59473-745-01
Extender Board for boards VRD, CSE, CSEX, VSC, FSVT
59473-746-01
Diagnostic Control Cable
38216-452-00
Diagnostic Control Panel
42560-285-01
5 Volt Filter Board
59473-819-01
100 Ohm Type B Relay for VRD (See Section 7.6.1 below)
56001-787-05
14-way connector
58920-113-00
Amp Terminal Crimp Tool (AMP Number 90285-1)
24745-149-00
Amp Terminal Extraction Tool (AMP Number 91073-1)
59688-048-00
Vital Output BPIC Assembly
31166-194-01
Vital Input BPIC Assembly
31166-195-01
Non-Vital BPIC Assembly
31166-196-01
VRD & 5VDC Power BPIC Assembly
31166-197-01
VSC BPIC Assembly
31166-198-01
Communications BPIC Assembly
31166-199-01
CPU/PD BPIC Assembly
31166-336-01
P2086B, Volume 1, Rev. D, Nov/13
7-10
Alstom Signaling Inc.
VPI Chassis
7.6.1
VRD Relay
WARNING
iVPI contains special safety circuit components which must only be replaced
by components specified by the Alstom part number.
These original-design replacement parts are manufactured to the same
standards as the original parts; their performance being verified. The use of
replacement parts that are not of the same Alstom part number could
potentially impair the safe performance of the system.
The railroad or transit system authority and the manufacturer of an
aftermarket (i.e., non-Alstom designated) part assume the responsibility that
the part will not adversely affect the safe performance of the system. The
authority and the manufacturer of the aftermarket part must analyze and
certify in writing that use of the part will not result in a failure of the system to
comply with safety regulations and safety performance. Completion of such
an analysis and certification is considered due diligence and standard
practice, will not be reviewed or approved by Alstom, and neither absolves
the authority and aftermarket part manufacturer of responsibility nor implies
approval by Alstom to use such an aftermarket part. The responsibility of any
consequences resulting from using such a part remains with the authority
and part manufacturer.
WARNING
Only Alstom VRD relay (P/N 56001-787-05) is to be used with the Alstom
iVPI system. Alstom products are designed to function within all-Alstom
systems. The introduction of non-Alstom products into an Alstom iVPI system
could have unintended and unforeseeable safety consequences
A front contact from the VRD Relay must be fed back into the iVPI system as a Vital
input for use in the application, for example, to prevent vital timers from starting when
the VRD is de-energized. The name of this Vital input may be VRDFRNT-DI.
Note: The front contact used as the Vital input is also available to
supply energy to Vital outputs.
P2086B, Volume 1, Rev. D, Nov/13
7-11
Alstom Signaling Inc.
VPI Chassis
7.7
BACK PLANE INTERFACE CARDS (BPIC)
Table 7–10. Vital Output (31166-194-01) I/O Pin Map
VPI CARD-EDGE
PIN
BPIC INTERFACE
WAGO PIN
BPIC BUS
JUMPER WAGO
PIN
VITAL OUTPUT
FUNCTION
P1-1
P1B-10
P1A-10
PORT 8 (-)
P1-2
P1B-9
P1A-9
PORT 8 (+)
P1-9
P1B-8
P1A-8
PORT 7 (-)
P1-10
P1B-7
P1A-7
PORT 7 (+)
P1-21
P1B-6
P1A-6
PORT 6 (-)
P1-22
P1B-5
P1A-5
PORT 6 (+)
P1-25
P1B-4
P1A-4
PORT 5 (-)
P1-26
P1B-3
P1A-3
PORT 5 (+)
P1-33
P1B-2
P1A-2
VN (-)
P1-34
P1B-1
P1A-1
VB (+)
P3-1
P3B-10
P3A-10
PORT 4 (-)
P3-2
P3B-9
P3A-9
PORT 4 (+)
P3-9
P3B-8
P3A-8
PORT 3 (-)
P3-10
P3B-7
P3A-7
PORT 3 (+)
P3-21
P3B-6
P3A-6
PORT 2 (-)
P3-22
P3B-5
P3A-5
PORT 2 (+)
P3-25
P3B-4
P3A-4
PORT 1 (-)
P3-26
P3B-3
P3A-3
PORT 1 (+)
P3-33
P3B-2
P3A-2
VB (-)
P3-34
P3B-1
P3A-1
VN (+)
P2086B, Volume 1, Rev. D, Nov/13
7-12
Alstom Signaling Inc.
VPI Chassis
Table 7–11. Vital Input (31166-195-01) I/O Pin Map (Cont.)
VPI CARD-EDGE
PIN
BPIC INTERFACE
WAGO PIN
BPIC BUS
JUMPER WAGO
PIN
DIRECT INPUT
FUNCTION
P1-1
P1B-16
P1A-16
PORT 16 (-)
P1-2
P1B-15
P1A-15
PORT 16 (+)
P1-5
P1B-14
P1A-14
PORT 15 (-)
P1-6
P1B-13
P1A-13
PORT 15 (+)
P1-9
P1B-12
P1A-12
PORT 14 (-)
P1-10
P1B-11
P1A-11
PORT 14 (+)
P1-13
P1B-10
P1A-10
PORT 13 (-)
P1-14
P1B-9
P1A-9
PORT 13 (+)
P1-17
P1B-8
P1A-8
PORT 12 (-)
P1-18
P1B-7
P1A-7
PORT 12 (+)
P1-21
P1B-6
P1A-6
PORT 11 (-)
P1-22
P1B-5
P1A-5
PORT 11 (+)
P1-25
P1B-4
P1A-4
PORT 10 (-)
P1-26
P1B-3
P1A-3
PORT 10 (+)
P1-29
P1B-2
P1A-2
PORT 9 (-)
P1-30
P1B-1
P1A-1
PORT 9 (+)
P3-1
P3B-16
P3A-16
PORT 8 (-)
P3-2
P3B-15
P3A-15
PORT 8 (+)
P3-5
P3B-14
P3A-14
PORT 7 (-)
P3-6
P3B-13
P3A-13
PORT 7 (+)
P3-9
P3B-12
P3A-12
PORT 6 (-)
P3-10
P3B-11
P3A-11
PORT 6 (+)
P3-13
P3B-10
P3A-10
PORT 5 (-)
P3-14
P3B-9
P3A-9
PORT 5 (+)
P3-17
P3B-8
P3A-8
PORT 4 (-)
P3-18
P3B-7
P3A-7
PORT 4 (+)
P3-21
P3B-6
P3A-6
PORT 3 (-)
P3-22
P3B-5
P3A-5
PORT 3 (+)
P3-25
P3B-4
P3A-4
PORT 2 (-)
P3-26
P3B-3
P3A-3
PORT 2 (+)
P2086B, Volume 1, Rev. D, Nov/13
7-13
Alstom Signaling Inc.
VPI Chassis
Table 7–11. Vital Input (31166-195-01) I/O Pin Map (Cont.)
VPI CARD-EDGE
PIN
BPIC INTERFACE
WAGO PIN
BPIC BUS
JUMPER WAGO
PIN
DIRECT INPUT
FUNCTION
P3-29
P3B-2
P3A-2
PORT 1 (-)
P3-30
P3B-1
P3A-1
PORT 1 (+)
Table 7–12. Non-Vital Input (31166-196-01) I/O Pin Map (Cont.)
VPI CARD-EDGE
PIN
BPIC INTERFACE
WAGO PIN
NONVITAL INPUT
FUNCTION
NONVITAL
OUTPUT
FUNCTION
P1-5
P1A-20
PORT 32 (+)
PORT 32 (+)
P1-6
P1A-19
PORT 31 (+)
PORT 31 (+)
P1-9
P1A-18
PORT 30 (+)
PORT 30 (+)
P1-10
P1A-17
PORT 29 (+)
PORT 29 (+)
P1-13
P1A-16
PORT 28 (+)
PORT 28 (+)
P1-14
P1A-15
PORT 27 (+)
PORT 27 (+)
P1-17
P1A-14
PORT 26 (+)
PORT 26 (+)
P1-18
P1A-13
PORT 25 (+)
PORT 25 (+)
P1-19
P1A-12
UNUSED
VB (+)
P1-20
P1A-11
VN (-)
VN (-)
P1-21
P1A-10
PORT 24 (+)
PORT 24 (+)
P1-22
P1A-9
PORT 23 (+)
PORT 23 (+)
P1-25
P1A-8
PORT 22 (+)
PORT 22 (+)
P1-26
P1A-7
PORT 21 (+)
PORT 21 (+)
P1-29
P1A-6
PORT 20 (+)
PORT 20 (+)
P1-30
P1A-5
PORT 19 (+)
PORT 19 (+)
P1-32
P1A-4
PORT 18 (+)
PORT 18 (+)
P1-34
P1A-3
PORT 17 (+)
PORT 17 (+)
P1-35
P1A-2
UNUSED
VB (+)
P1-36
P1A-1
VN (-)
VN (-)
P2086B, Volume 1, Rev. D, Nov/13
7-14
Alstom Signaling Inc.
VPI Chassis
Table 7–12. Non-Vital Input (31166-196-01) I/O Pin Map (Cont.)
VPI CARD-EDGE
PIN
BPIC INTERFACE
WAGO PIN
NONVITAL INPUT
FUNCTION
NONVITAL
OUTPUT
FUNCTION
P3-5
P3A-20
PORT 16 (+)
PORT 16 (+)
P3-6
P3A-19
PORT 15 (+)
PORT 15 (+)
P3-9
P3A-18
PORT 14 (+)
PORT 14 (+)
P3-10
P3A-17
PORT 13 (+)
PORT 13 (+)
P3-13
P3A-16
PORT 12 (+)
PORT 12 (+)
P3-14
P3A-15
PORT 11 (+)
PORT 11 (+)
P3-17
P3A-14
PORT 10 (+)
PORT 10 (+)
P3-18
P3A-13
PORT 9 (+)
PORT 9 (+)
P3-19
P3A-12
UNUSED
VB (+)
P3-20
P3A-11
VN (-)
VN (-)
P3-21
P3A-10
PORT 8 (+)
PORT 8 (+)
P3-22
P3A-9
PORT 7 (+)
PORT 7 (+)
P3-25
P3A-8
PORT 6 (+)
PORT 6 (+)
P3-26
P3A-7
PORT 5 (+)
PORT 5 (+)
P3-29
P3A-6
PORT 4 (+)
PORT 4 (+)
P3-30
P3A-5
PORT 3 (+)
PORT 3 (+)
P3-32
P3A-4
PORT 2 (+)
PORT 2 (+)
P3-34
P3A-3
PORT 1 (+)
PORT 1 (+)
P3-35
P3A-2
UNUSED
VB (+)
P3-36
P3A-1
VN (-)
VN (-)
P2086B, Volume 1, Rev. D, Nov/13
7-15
Alstom Signaling Inc.
VPI Chassis
Table 7–13. VRD/5VDC Power (31166-197-01) Pin Interface
VPI TERMINATION
WAGO TERMINAL
FUNCTION
P3-2
J1-1
RELAY-
P3-6
J1-2
RELAY+
P3-32
J1-3
12V COMMON
P3-36
J1-4
+12V INPUT
NONE
J2-1
MELCHER +5VDC INPUT
NONE
J2-2
MELCHER +5VDC INPUT
NONE
J2-3
MELCHER 5V COMMON INPUT
NONE
J2-4
MELCHER 5V COMMON INPUT
GROUND POST
J2-5
5V COMMON
GROUND POST
J2-6
5V COMMON
P2-TS1
J3-1
FILTERED +5VDC
P2-TS3
J3-2
FILTERED +5VDC
P2-TS2
J3-3
5V COMMON
P2-TS4
J3-4
5V COMMON
Table 7–14. VSC Modular Jack (31166-198-01) Pin Map
VSC PIN
RJ-45 JACK PIN
P3-5
J1-1
VPIRCVA
P3-6
J1-2
VPIRCVB
P3-2
J1-7
VPITXB
P3-1
J1-8
VPITXB
P3-25
J2-3
TXD
P3-26
J2-1
RTS
P3-28
J2-6
RXD
P3-29
J2-8
CTS
P3-30
J2-2
RLSD
P3-36
J2-4
J2-5
ISOLATED COMMON
P2086B, Volume 1, Rev. D, Nov/13
7-16
FUNCTION
Alstom Signaling Inc.
VPI Chassis
Table 7–15. VSC EIA422 (31166-198-01) Pin Map
VSC PIN
DB-25 PIN
FUNCTION
P3-1
J6-2
VPITXA
P3-2
J6-14
VPITXB-
P3-5
J6-3
VPIRCVA
P3-6
J6-16
VPIRCVB
VSCIC J3-4
J6-1
SHIELD
Table 7–16. Terminal Block Setting (31166-198-01)
INTERFACE MODE
JUMPER PINS
4 TRACK GENRAKODE
TB1-1 TO TB1-2
TB2-1 TO TB2-2
VSC TO VSC
TB1-2 TO TB1-3
TB2-2 TO TB2-3
Table 7–17. VSC EIA232 (31166-198-01) Pin Map
VSC PIN
DB-25 PIN
FUNCTION
P3-25
J5-2
TXD
P3-26
J5-4
RTS
P3-28
J5-3
RXD
P3-29
J5-5
CTS
P3-30
J5-8
RLSD
VSCIC J3-4
J5-1
SHIELD
Table 7–18. VSC Isolated Power (31166-198-01) Pin Map
VSC PIN
WAGO TERMINAL
P3-35
J3-1
+VCC
P3-36
J3-2
ISOLATED COMMON
P3-36
J3-3
ISOLATED COMMON
CHASSIS GROUND
J3-4
SHIELD
P2086B, Volume 1, Rev. D, Nov/13
7-17
FUNCTION
Alstom Signaling Inc.
VPI Chassis
Table 7–19. 4 Track Genrakode Interface (31166-198-01) Pin Map
VSC PIN
WAGO TERMINAL
FUNCTION
P3-1
J4-1
VPITXA
P3-2
J4-2
VPITXB
P3-5
J4-3
VPIRCVA
P3-6
J4-4
VPIRCVB
Table 7–20. Communications (31166-199-01) Connector Types
FUNCTION
CONNECTOR
NAME
ISOLATED 9-35VDC /
PORT2 (DC CODE LINE)
14-WAY WAGO
(0.200-inch centers)
J5
PORT1 (EIA530)
DB-25 CONNECTOR
J7
PORT2 (EIA530)
DB-25 CONNECTOR
J6
PORT3 (EIA422)
RJ-45 MODULAR BLOCK
J3
PORT4 (EIA422)
RJ-45 MODULAR BLOCK
J2
PORT5 (EIA422)
RJ-45 MODULAR BLOCK
J1
PORT6 (HHT CURRENT LOOP)
RJ-45 MODULAR BLOCK
J4
P2086B, Volume 1, Rev. D, Nov/13
7-18
Alstom Signaling Inc.
VPI Chassis
Table 7–21. Serial Port 1 (31166-199-01) Pin Map
CSEX3 PIN
DB-25 PIN(S)
COMIC J5-14
J7-1
SHIELD
P3-2
J7-7
ISOLATED COMMON
(SIGNAL GROUND)
P3-4
J7-2
TDA-1
P3-5
J7-14
TDB-1
P3-6
J7-4
RTSA-1
P3-7
J7-19
RTSB-1
P3-8
J7-3
RDA-1
P3-9
J7-16
RDB-1
P3-10
J7-5
CTSA-1
P3-11
J7-13
CTSB-1
P3-12
J7-8
J7-15
DCDA-1
(CSEX3) 1TXCLK
P3-13
J7-10
J7-17
DCDB-1
(CSEX3) 1RXCLK
P2086B, Volume 1, Rev. D, Nov/13
7-19
FUNCTION(S)
Alstom Signaling Inc.
VPI Chassis
Table 7–22. Serial Port 2 (31166-199-01) Pin Map
CSEX3 PIN
DB-25 PIN
FUNCTION
COMIC J5-14
J6-1
SHIELD
P3-2
J6-7
ISOLATED COMMON
(SIGNAL GROUND)
P3-14
J6-2
TDA-2
P3-15
J6-14
TDB-2
P3-16
J6-4
RTSA-2
P3-17
J6-19
RTSB-2
P3-18
J6-3
RDA-2
P3-19
J6-16
RDB-2
P3-20
J6-5
CTSA-2
P3-21
J6-13
CTSB-2
P3-22
J6-8
J6-15
DCDA-2
(CSEX3) 2TXCLK
P3-23
J6-10
J6-17
J7-17
DCDB-2
(CSEX3) 2RXCLK
Table 7–23. Port 2 DC Code Line (31166-199-01) Pin Map
CSEX3 PIN
WAGO TERMINAL
P3-14
J5-8
ISOLATED V+
P3-15
J5-7
ISOLATED V-
P3-16
J5-6
OUT1-DC
P3-17
J5-5
OUT2-DC
P3-18
J5-4
IN1+
P3-19
J5-3
IN1-
P3-20
J5-2
IN2+
P3-21 (CSEX3)
J5-1
IN2-
P2086B, Volume 1, Rev. D, Nov/13
7-20
FUNCTION
Alstom Signaling Inc.
VPI Chassis
Table 7–24. Serial Port 3, 4, 5 and 6 (31166-199-01) Pin Map
CSEX3 PIN
RJ-45 JACK PIN
FUNCTION
P2-35
J4-6
RXD
P2-40
J4-3
TXD-
P2-50
J4-8
SYSTEM +5V
P3-25
J3-1
RDA-3
P3-26
J3-2
RDB-3
P3-28
J3-7
TDB-3
P3-27
J3-8
TDA-3
P3-29
J2-1
RDA-4
P3-30
J2-2
RDB-4
P3-32
J2-7
TDB-4
P3-31
J2-8
TDA-4
P3-33
J1-1
RDA-5
P3-34
J1-2
RDB-5
P3-36
J1-7
TDB-5
P3-35
J1-8
TDA-5
7-21
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
VPI Chassis
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
7-22
Alstom Signaling Inc.
Maintenance
SECTION 8 – MAINTENANCE
8.1
GENERAL
This section contains specific procedures for preventive and corrective maintenance
and for troubleshooting the VPI system. Unless otherwise noted, references to the
CPU/PD board also apply to the CPU board and references to CSEX apply to CSEX1
and CSEX3.
WARNING
Disruption of Vital controller service poses a potential threat to rail safety.
Before shutting down an interlocking for any reason, you must notify the
railroad dispatcher in charge of the affected route(s). Take all steps
necessary to ensure the safe passage of traffic is maintained.
8.1.1
Service Log
A service log should be kept on the VPI system to record test results and keep track of
any service performed. A log should describe any malfunctions, corrective action taken
and all preventive maintenance performed. The log can also be used to maintain a
spare parts inventory by recording the quantities and type of printed circuit boards and
spare parts that have been used as replacements.
P2086B, Volume 1, Rev. D, Nov/13
8-23
Alstom Signaling Inc.
Maintenance
8.1.2
Spare Parts
WARNING
VPI contains special safety circuit components which must only be replaced
by components specified by the Alstom part number.
These original-design replacement parts are manufactured to the same
standards as the original parts; their performance being verified. The use of
replacement parts that are not of the same Alstom part number could
potentially impair the safe performance of the system.
The railroad or transit system authority and the manufacturer of an
aftermarket (i.e., non-Alstom designated) part assume the responsibility that
the part will not adversely affect the safe performance of the system. The
authority and the manufacturer of the aftermarket part must analyze and
certify in writing that use of the part will not result in a failure of the system to
comply with safety regulations and safety performance. Completion of such
an analysis and certification is considered due diligence and standard
practice, will not be reviewed or approved by Alstom, and neither absolves
the authority and aftermarket part manufacturer of responsibility nor implies
approval by Alstom to use such an aftermarket part. The responsibility of any
consequences resulting from using such a part remains with the authority
and part manufacturer.
WARNING
Only Alstom VRD relay (P/N 56001-787-05) is to be used with the Alstom
VPI system. Alstom products are designed to function within all-Alstom
systems. The introduction of non-Alstom products into an Alstom VPI system
could have unintended and unforeseeable safety consequences
P2086B, Volume 1, Rev. D, Nov/13
8-24
Alstom Signaling Inc.
Maintenance
The VPI system is designed for long life and trouble-free operation. This equipment,
however, as with all electronic equipment may have an occasional component failure.
Spare boards can be ordered from Alstom based on your projected needs. The below
spares are recommended to support one VPI module:
•
A spare of each board type used in the module
•
A spare set of signature headers (Alstom 59473-871), see Appendix F
•
A spare set of signature PROMs (Alstom 39780-003), see Appendix F
•
A spare set of application data EPROMs (Vital and Non-Vital)
•
A spare set of system EPROMs (Vital and Non-Vital)
•
A spare lithium battery (P/N 52397-011-00)
Boards with static-sensitive components should be stored, transported, or shipped in
conductive Velostate bags and have printed circuit “Contabs” attached. Printed circuit
Contabs should be left on boards except for testing and installation.
8.1.3
Test Equipment
Field maintenance of the VPI system requires little in the way of external test
equipment. Built-in circuitry is used to test critical system functions and generate the
appropriate status messages on an externally connected Handheld Terminal (HHT) or
PC. A suitable terminal for VPI diagnostics is described in Section 2. In addition, all VPI
circuit boards have LED indicators that reveal the operating status of the board.
Besides these automated test tools, a standard multi-meter (Fluke Model 87 or similar)
will be helpful for checking the level of operating voltages, current levels, and for
continuity checks.
CAUTION
Before removal or installation of any boards, ensure that all VPI system
power has been removed. Failure to do so may result in damage to board
components.
P2086B, Volume 1, Rev. D, Nov/13
8-25
Alstom Signaling Inc.
Maintenance
8.1.4
Preventive Maintenance
No periodic adjustments are required to sustain continuous VPI operation. The module
should be checked periodically for damaged hardware or loose connections, broken or
corroded wiring, signs of overheating and build-up of dust or foreign material. Make sure
that all boards are properly seated in the module and that the module covers are
properly secured.
If the board contact fingers have been touched or show signs of contamination, clean
them with a contact cleaner such as Miller-Stephenson's Contact Renu, IBM Contact
Lubricant (part number 451053) or other approved solvent using a clean, lint-free cloth.
Check the VPI Power Supply voltage for a value of +5 ± 0.25 volts DC. Take corrective
action if necessary. This voltage check should be made on the test points of boards
installed in a system chassis or expansion chassis. Because of the different board
complements that are possible with VPI, it is recommended that the test points on any
processor board assemblies, e.g., CPU, CPU/PD, CSEX(n), VSC and TWC be selected
for this measurement. Input and output boards, whether Vital or non-vital are much
more tolerant of variations of the system logic voltage than the processors.
Use the Handheld Terminal (HHT), a PC running VT-100 terminal emulation software, a
CSEX board equipped with the Vital Diagnostic Protocol (VDP – see Alstom publication
P2346W), or Alstom’s Tracker® analyzer (see Alstom publication P2307) to interrogate
the system for system diagnostics. For example, a failure may cause a “SYS
WARNING” status message to be displayed which may indicate outputs that fail in a
non-fatal fashion such as open lamp filaments.
Check the LED status lamps on the boards for proper signals (refer to “Troubleshooting
with LED’s” later in this section).
Before starting any detailed troubleshooting, check for simple problems first such as
blown fuses, loose plugs, dirty board contacts, or improper voltages.
P2086B, Volume 1, Rev. D, Nov/13
8-26
Alstom Signaling Inc.
Maintenance
In addition, if the system has been serviced or turned off and will not restart, check the
following prior to beginning detailed troubleshooting:
•
Vital Input and Output boards have the proper signature headers and are in their
respective slots.
•
All on-board switches and jumpers are properly set (see “Board Reference Data”
later in this section).
•
Wiring between the Vital Relay Driver (VRD) board and the VRD Relay is intact.
•
Input power to the VRD board is between 9.0 and 16.0 volts.
•
Energizing the VRD Relay causes voltage between 9.0 to 16.0 volts to be applied to
the VPI input designated “VRDFRNT-DI”.
•
Application logic version in the CPU/PD board PROMs matches that dictated by the
revision signature wire wrapped on the Motherboard (at the CPU or CPU/PD board
slot).
P2086B, Volume 1, Rev. D, Nov/13
8-27
Alstom Signaling Inc.
Maintenance
8.2
BASIC DIAGNOSTIC FLOWCHART
At entrance rack,
verify problem is
actually VPI related,
not field apparatus.
Confirm system is operating
by checking CPU LEDs and
verifying HHT can communicate
with the CPU.
If CPU LED indicate Boolean
equation processing is taking
place, look at LEDs on boards
below. (1-sec. flashing)
If CPU not running, look at
CPU/PD board itself, including
both hardware and software.
Change CPU/PD
board or PROMs.
Check CSEX LEDs
to find if it is NV
Communication
problems.
Check VRD
LEDs to
verify VRD relay
is being driven.
(Checkwords OK)
Check I/O
Address LEDs
to verify CPU is
talking to I/O ports.
Check VSC LEDs
to verify
microprocessor
operation
and communication.
HHT can provide key info to
further define the problem
'A'
'B'
Figure 8-1. General Diagnostic Flowchart (Sheet 1 of 3)
P2086B, Volume 1, Rev. D, Nov/13
8-28
Alstom Signaling Inc.
Maintenance
'B'
from SHT. 1
I/O LEDs
Verify I/O boards are being
addressed by the CPU.
If boards are being addressed,
If no boards are being
addressed, check cabling,
signatures, and hardware.
check with HHT for specific
port error messages.
Check BOOLS for circuit
reason for the failure.
Interrogate memory locations
with HHT
Use ####Q and current .LVC file printout.
Note that the application logic may not let
the system actually do the required tasks.
For example, the interlocking will not unlock
to throw switches because the track circuit is
not working (down). Don't think about VPI
system itself, but of the affected circuits.
Using board reports, check
voltages supplied to power
groups on output boards.
SUMMARY: Once at the I/O level, determine if the system is trying to turn on or
read the correct port. If not, this indicates further system problems. If HHT shows a
port's memory location becoming true, the port is being forced to turn on.
Be aware that the application logic may be preventing an action from occuring by
system design.
Figure 8-1. General Diagnostic Flowchart (Sheet 2 of 3)
P2086B, Volume 1, Rev. D, Nov/13
8-29
Alstom Signaling Inc.
Maintenance
'A'
from SHT.1
CSEX LEDs
Verify a NV Communication problem
with CSEX LEDs.
Use LEDs to watch for proper
port being addressed.
SUMMARY: If there are communications problems, look at board LEDs first.
Study CAA reports to verify ports used, protocol, etc. With the diagnostic Query
command, look at the vital memory location to see if the message is sucessfully
being transferred from CSEX to CPU/PD.
Also, special test equipment can be used to look at the serial output messages.
Figure 8-1. General Diagnostic Flowchart (Sheet 3 of 3)
P2086B, Volume 1, Rev. D, Nov/13
8-30
Alstom Signaling Inc.
Maintenance
8.3
VITAL SYSTEM DIAGNOSTICS AVAILABLE ON THE CPU/PD BOARD
8.3.1
Use of Handheld Terminal (HHT), Diagnostics Terminal and the CSEX VDP
The CPU/PD board’s embedded diagnostic software provides operating status and
diagnostic information to the following devices:
•
An externally connected Handheld Terminal (HHT), as shown in Figure 8-2. The
HHT is used for diagnostics related to the CPU and CPU/PD boards. For CPU
board (59473-742) a Current Loop HHT (Alstom Part Number 31609-011-00) is
used. For CPU/PD boards (31166-029) an EIA232 HHT (Alstom part number
31609-012-00) is used. To perform diagnostics, the HHT is connected to the 9-pin
“D” connector (DB-9) at the front of the CPU/PD board or the 25-pin “D” connector
(DB-25) at the front of the CPU board.
CPU/PD
9-PIN CONNECTOR
Figure 8-2. Diagnosis With Handheld Terminal
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Maintenance
•
An externally connected “dumb terminal”, configured for 1200 baud, 8 data bits, 1
stop bit and no parity, can be used with the CPU/PD board. When not using the
Alstom hand held terminal, jumper W1 should be removed. A properly equipped
terminal can be used with the CPU board, also (consult Alstom for details). The
following is the wiring information to connect to a terminal:
Table 8–1. CPU/PD HHT Port Cable
Connector Pin
Signal
2
/XMIT
3
/RECV
5
Signal Common
•
An externally connected Personal Computer (PC) running Alstom’s Tracker
software.
•
A CSEX3 board equipped with Alstom’s Vital Diagnostic Protocol (VDP). This
protocol extracts diagnostic information from the CPU/PD board’s HHT port, and
presents this information in a user-friendly manner at the CSEX MAC (Maintenance
Access) port. Note that this feature does not apply to the CPU board. CPU/PD
diagnostics are reported to CSEX either serially or in parallel through on-board
shared memory. Refer to Alstom publication P2346W for a complete description of
the VDP and connection to the CPU/PD board.
Once per second, the system status (“SYSTEM OK”, “SYS WARNING” or “ERROR
ALERT”) is displayed on the HHT, dumb terminal or CSEX VDP diagnostic menu. The
HHT, terminal or VDP can also be used in an interactive manner to provide detailed
troubleshooting information. In most cases, faults can be localized to a specific board.
The following provides general instructions for using an HHT connected to the CPU or
CPU/PD board, and lists the interactive diagnostic commands that are supported. It may
be necessary to type the ‘C’ command (described below) to continue operation during
system start-up if an error is detected. This command allows display of any of the
diagnostic messages described herein. A CSEX board running the Vital Diagnostic
Protocol (VDP) automatically makes use of the CPU/PD board’s interactive commands
to extract and report diagnostic information.
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Maintenance
8.3.2
Top Level Vital Status Messages
After starting the Handheld Terminal, one of three top-level status messages appears
once a second:
“SYSTEM OK” – Displayed when all VPI functions are working properly (no errors
detected).
“SYS WARNING” – Indicates an error that has caused an abnormal or out-of-tolerance
condition. Continued VPI operation may still be possible (i.e. the VRD Relay stays up).
The meaning here is that system safety is unaffected.
“ERROR ALERT” – Indicates a “fatal” error. Continued VPI operation will not be
possible (i.e. the VRD Relay is down with all outputs disconnected). The meaning here
is that a system safety problem may exist.
If no message is shown, check for faulty wiring in the serial interface cable or inspect
the CPU/PD board to verify that it contains a valid set of EPROM software. If the
problem persists, replace the CPU/PD board.
Further interrogation is possible to help determine the exact cause of a top-level error
message (“SYS WARNING” or “ERROR ALERT”) by using a series of interactive
keyboard commands.
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8.3.3
HHT Keyboard Command Summary
In the following command descriptions, the information given in single quotes (‘x’)
represents the exact key or keys to press at the Handheld Terminal. The final key to
press for any command is ‘CR’ (Carriage Return) on an HHT or Enter on a terminal.
This action is required to initiate each command, although for brevity, it is explicitly
shown for only the first command’s description below. Note that if any keyboard
character is entered during the CPU board’s power-up cycle, it will halt.
Note: The following commands must be entered using upper-case
letters. The Vital processors will treat lower-case characters as
“invalid”.
‘C’ = Continue
This command instructs the VPI module to continue through its start-up sequence after
an error is encountered during system start-up. However, with some errors, it may not
be possible to continue until repairs are made. The ‘C’ command also causes the
system to display one of the three top level status messages (“SYSTEM OK”, “SYS
WARNING” or “ERROR ALERT”) without erasing stored error data. The Continue
command is initiated by pressing the ‘C’ key followed by the ‘CR’ (Carriage Return) key.
‘S’ = Start/Stop
This command removes the system from the “query”, “report” and “view errors” modes
described later. Exiting from the current mode is necessary when wishing to display
other diagnostic messages.
‘N’ = Next
This command instructs the system to display the next level of diagnostics, and is used
while in the “query”, “report” and “view errors” modes described below.
‘?’ = View Errors/Warnings
Use this command to display warning or error data after a “SYS WARNING” or “ERROR
ALERT” message has appeared. This command is ignored while the status is “SYSTEM
OK”. Step through all error/warning messages by using the ‘N’ (Next) command (see
below), and exit “view errors” mode by using the ‘S’ (Stop) command.
‘X’ = Erase
Erases all error and warning data that has been stored. If the problem persists, the error
data will appear again even after erasure.
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Maintenance
‘Q’ = Query Memory
This command is used to display the value of one or more Vital parameters in CPU
RAM, updated once a second. Parameter addresses are typically obtained from the
Vital application’s LVC compiled output report file. Use the ‘S’ command to exit from
“query” mode. The ‘Q’ command has several formats:
1.
‘wxyzQ’ – causes the system to once a second display the contents of four
consecutive bytes of CPU RAM, starting at the address entered immediately before
the ‘Q’. The starting address entered must be in hexadecimal format. The display
shows the lowest (least significant) three characters of the starting address,
followed by the contents of four bytes of RAM data in the form of eight hexadecimal
characters. Thus, if the command ‘wxyzQ’ is entered, the display shows
“xyz/12345678”. The eight characters (12345678) represent, from left to right, the
data in the RAM locations wxyz+3, wxyz+2, wxyz+1 and wxyz, respectively. Use the
‘N’ (Next) command to display four new bytes of data, starting at the RAM address
wxyz+4. RAM addresses for various system parameters are defined in the system
documents and are the offset values from the start of the RAM address area. The
entry required for the ‘Q’ command is the same value as the offset address from the
start of RAM.
2. ‘wxyzQnn’ – causes the system to place RAM address wxyz at position nn in the list
of 16 Vital parameters to be queried, and once a second output the true (1) or false
(0) states of the 16 Vital parameters whose addresses are currently in the list. In
this command, the address wxyz may be from one to four hexadecimal characters,
but an address of 0 (zero) is invalid. The position nn must be entered as two digits
ranging from position 01 to 16. Typically, wxyz is the address of a Vital application
parameter obtained from the application’s LVC compiled output report file. After this
command is entered, once a second the system displays the current true/false
states of the 16 Vital parameters in the format “110000111xx0011x” (for example).
The character x appears at positions in the list for which no address has yet been
specified by the user. The system retains the list of 16 addresses to query unless it
is restarted.
3. ‘wxyzQ00’ – causes the system to remove RAM address wxyz from the list of 16
Vital parameters to be queried, and once a second output the true/false states of
the 16 parameters whose addresses are currently in the list. In this command, a pair
of zeros follows the letter Q.
4. ‘Q00’ – causes the system to erase the entire list of 16 Vital RAM parameters to be
queried, and once a second output a message in the format “xxxxxxxxxxxxxxxx”.
5. ‘0Q00’ – causes the system to once a second output the true (1) or false (0) states
of the 16 Vital parameters currently in the list of addresses, without modification to
the list. In this command, a single zero precedes and a pair of zeros follows the
letter Q.
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Alstom Signaling Inc.
Maintenance
6. ‘Q’ – causes the system to show the addresses (four at a time) currently in the list of
16 Vital parameters to be queried, in the format “aaaa;aaaa;aaaa;aaaa”. Four
dashes (----) are used to indicate an empty position in the list of 16 addresses. Note
that initially all positions are empty, until the user enters the ‘wxyzQnn’ command
one or more times. Use the ‘N’ (Next) command to view the next four addresses in
the list.
'U' = Disable
Use this command to inhibit the “SYS WARNING” message (i.e. “OUT NOT ON”) which
appears when the VPI diagnostics encounters an output that is turned on but is
delivering no output current. This command may be appropriate when a no-current
condition is normal.
‘O’ = Enable
This command negates a previously-entered ‘U’ (Disable) command.
‘R’ = Report
This command routes configuration data to the Handheld Terminal. It provides CAA
system software and Vital Serial Controller (VSC) application logic configuration
information. Step through all configuration messages by using the ‘N’ (Next) command,
and exit “report” mode by using the ‘S’ (Stop) command.
‘Z’ = Ignore Command
Any command terminated by a ‘Z’ is ignored by the system.
8.3.4
Vital Diagnostic Charts
Table 8–2 and Table 8–3 lists errors according to the message displayed on the
Handheld Terminal and gives the corresponding user responses. Possible causes for
the error message and preliminary steps to resolve system failure are also provided. A
general system troubleshooting flowchart is given earlier in Figure 8-1.
When troubleshooting, if board replacement is indicated, refer to the procedures for
“Board Replacement” later in this section.
Notes: Table 8–2 and Table 8–3 mention “module number” in failure
messages. Module #1 is always the system module in a
multiple-module system, module #2 is Extender module #1,
module #3 is Extender module #2, and module #4 is Extender
module #3.
References to CPU/PD generally apply to CPU boards as well
(unless noted otherwise).
References to CSEX generally apply to CSEX1, and CSEX3
boards (unless noted otherwise).
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Alstom Signaling Inc.
Maintenance
Table 8–2. Troubleshooting Chart: Start-up Diagnostics (Cont.)
Message
Displayed
Possible Cause(s)
User Response
Corrective Action
No Message
Displayed
Faulty test cable or
invalid software on
CPU/PD board.
Further testing will not
be possible.
None
Inspect test cable
wiring.
Verify CPU/PD EPROM
is valid.
If problem persists,
replace CPU/PD board.
CPU RAM ERR
Failed
“Checkerboard” test
on system RAM.
System may still run
by not using defective
RAM.
C / ENTER
Replace CPU/PD
board.
POLY DIV ERR
Failure of PD portion
of CPU/PD board (PD
board in CPU system)
or ribbon cable.
N / ENTER
Failure
Messages
‘PD C3, 1 ERR’
‘PD C3, 2 ERR’
‘PD C1, 1 ERR’
‘PD C1, 2 ERR’
PD C1, 1N ERR’
‘PD C1, 2N
ERR’
‘PD LOAD ERR’
Record failure for
CPU/PD board in
module.
Replace PD board in
CPU system.
Inspect 60 way main
bus connections.
Inspect/replace
CPU/PD board.
Verify continuity of
ribbon cable.
PROM MEM ERR
CPU PROM failure.
System not likely to
operate normally.
SW2 on CPU board.
N / ENTER
Failure
Messages
‘ROUTINE
PROM’
‘ADSNOSHADOW’
‘ADS-SHADOW’
Record failure for
CPU/PD board in
module.
Replace with new CPU
PROM.
If all PROM failure
modes appear, replace
CPU/PD board.
Check
Application/System
software compatibility
for latest revision.
Verify SW2 on CPU
board is set properly.
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Alstom Signaling Inc.
Maintenance
Table 8–2. Troubleshooting Chart: Start-up Diagnostics (Cont.)
Message
Displayed
Possible Cause(s)
User Response
Corrective Action
CPU SIG ERR
Failure of CPU/PD
EPROM signature to
match the hardwired
signature on the
wirewrap pins of
Motherboard.
VRD will not
energize.
C / ENTER
Verify hardwired
signature on wirewrap
pins of Motherboard at
CPU/PD slot.
Verify CPU/PD EPROM
version number and
Motherboard signatures
match.
OUTPUT ERR
Failed test of one or
more AOCDs on an
Output board.
Wrong or defective
signature PROM or
incorrect address
wiring on Output
board.
System not likely to
operate under this
condition.
Hit ? to find bad
Output board
N / ENTER
Failure Message
‘OUT #x/yy/z’
Replace Output
board(s) indicated.
Check for defective
signature PROM.
Wrong signature
header on any or all I/O
Bus boards
Check I/O Bus Interface
board.
Verify continuity of
ribbon cable.
Check wirewrap
signature address and
related wiring.
x = Module number
y = Slot number
z = Port number
ENTER to repeat
VRD INTER ERR
Dual-Port RAM
Interface failure on
VRD board.
CPU/PD board fault.
System not likely to
operate under this
condition.
P2086B, Volume 1, Rev. D, Nov/13
C / ENTER
8-38
Reinitialize CPU/PD to
test VRD Interface
RAM.
If test repeatedly fails,
replace VRD board.
If test fails again,
replace CPU/PD board.
If test continues to fail,
check bus connections
on module
Motherboard.
Alstom Signaling Inc.
Maintenance
Table 8–2. Troubleshooting Chart: Start-up Diagnostics (Cont.)
Message
Displayed
CSE INTER ERR
VSC INTER ERR
Possible Cause(s)
Dual-Port RAM
Interface failure on
CSEX board.
System will operate
under this condition.
Dual-Port RAM
Interface failure on
VSC board.
System will operate
under this condition.
P2086B, Volume 1, Rev. D, Nov/13
User Response
Corrective Action
N / ENTER
Failure Message
‘CSE BD #x/yy’
Reinitialize CPU to test
CSEX Interface RAM.
Verify board is plugged
in.
If test repeatedly fails,
replace CSEX board.
If test continues to fail,
check bus connections
on module Motherboard
and for bent pins on I/O
Bus Interface board.
Check continuity of
ribbon cable(s).
x = Module number
y = Slot number
N / ENTER
Failure Message
‘VSC BD #x/yy’
x = Module number
y = Slot number
8-39
Reinitialize CPU/PD to
test VSC Interface
RAM.
If test repeatedly fails,
replace VSC board.
If test fails again,
replace CPU/PD board.
If test continues to fail,
check bus connections
on module
Motherboard.
Alstom Signaling Inc.
Maintenance
Table 8–3. Troubleshooting Chart: Diagnostics During System Operation (Cont.)
Possible
Cause(s)
POLY DIV
ERR
Failure of test
performed on
CPU/PD board once
each 1-second main
cycle.
CPU/PD (or PD)
board bad.
N / ENTER
Possible Failure
Modes
‘PD C3, 1 ERR’
‘PD C3, 2 ERR’
‘PD C1, 1 ERR’
‘PD C1, 2 ERR’
‘PD C1, 1N ERR’
‘PD C1, 2N ERR’
‘PD LOAD ERR’
Record failure for
CPU/PD (or PD)
board in module.
Inspect 60 way main
bus connections.
Inspect/replace
CPU/PD (or PD)
board.
MAIN CWD
ERR
One or more of 20
main checkwords
delivered to the VRD
board in error.
N / ENTER
Failure Message
‘MAIN CWD#xx’
Course of action
depends on which
checkword is in
error.
If CHKMEM
appears, verify on
CPU/PD board that
EPROMS are
properly installed.
If all checkwords
indicate bad,
VRDFRNT-DI input
was energized while
VRD board was not
driving VRD relay.
This condition
results from a test
setup or wiring error.
If other checkwords
are bad, replace
CPU/PD board.
ERROR ALERT
Message
Displayed
User Response
ERROR ALERT
xx = Main checkword
number in HEX in error
N / ENTER to continue
After all failed main
checkwords have been
displayed, ‘END ERR
DATA’ appears.
ERROR ALERT
VRD XFR ERR
VRD Relay detected
de-energized via the
VRDFRNT-DI input
and checkwords
sent to VRD board
determined to be
correct.
P2086B, Volume 1, Rev. D, Nov/13
C / ENTER
Corrective Action
If VRD Relay
continuously down,
replace VRD board.
If VRD Relay
intermittently down,
check 60 way main
bus cable.
8-40
Alstom Signaling Inc.
Maintenance
Table 8–3. Troubleshooting Chart: Diagnostics During System Operation (Cont.)
Message
Displayed
ERROR ALERT
OUTPUT ERR
Possible
Cause(s)
Failure of a Recheck
checkword delivered
to the VRD board
once at the
beginning of each
50 ms period.
Bad output port of
board.
User Response
N / ENTER
Failure Message
‘OUT# x/yy/z’
x = Module number
y = Slot number
z = Port number
N / ENTER to continue
Corrective Action
Output board in
question.
Verify external
connections and
field equipment.
Check board
address.
Check signature
PROMs.
After all failed output
ports have been
displayed, ‘END ERR
DATA’ appears.
TRE VAL ERR
ERROR ALERT
Note: This
message follows
OUTPUT ERR.
N / ENTER
Failure Message
‘TREVAL#xx/yy’
xx = Port group
yy = Port number
Inspect/replace
output board in
question.
Verify external
connections and
field equipment.
N / ENTER to continue
After all failed output
ports have been
displayed, ‘END ERR
DATA’ appears.
RCHK CWD
ERR
ERROR ALERT
Erroneous TRE
values returned from
output ports. These
cause incorrect
Recheck
checkwords to go to
VRD board.
Bad Output board.
Note: This
message follows
OUTPUT ERR.
Failure of a Recheck
checkword being
delivered to VRD
board.
Bad Output board.
Note: Recheck
checkword numbers 01
and 04 are summations
of all other
checkwords. Thus, if
any checkword is in
error so will 01 and 04
be in error.
P2086B, Volume 1, Rev. D, Nov/13
N / ENTER
Failure Message
‘RCHK CWD#xx’
xx = Checkword number
Inspect/replace
output board in
question.
Verify external
connections and
field equipment.
N / ENTER to continue
After all failed output
ports have been
displayed, ‘END ERR
DATA’ appears.
8-41
Alstom Signaling Inc.
Maintenance
Table 8–3. Troubleshooting Chart: Diagnostics During System Operation (Cont.)
Message
Displayed
SYS WARNING
BAD IN DATA
SYS WARNING
OUT NOT ON
Possible
Cause(s)
One of more of the
Vital Input Ports
returned “Corrupted”
circulation data.
Corrupted data is
only recognized as
faulty after two or
more consecutive 1second cycles for a
particular port.
Output port has
been turned on but
returned circulation
data shows no
current flowing
through the output
port circuit.
Possible burned out
lamp or other open
condition.
Note: This
diagnostic may appear
for ‘on’ ACO ports.
User Response
N / ENTER
Failure Message
‘IN# x/yy/z’
x = Module number
y = Slot number
z = Port number
U / ENTER
Inhibits ‘OUT NOT
ON’ message.
O / ENTER
Nullifies the U /
ENTER command.
Corrective Action
Determine if input
port changes state
twice in two seconds
during normal
operation.
If error reappears,
after clearing all
saved error data,
replace Input board.
Check wirewrap
connections on
Motherboard,
signature headers
on Input board and
I/O bus Interface
boards.
Check load on this
port to determine if it
is within proper
current range.
If load on port (field
equipment) is
operational, replace
output board.
N / ENTER
Failure Message
‘OUT# x/yy/z’
x = Module number
y = Slot number
z = Port number
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Alstom Signaling Inc.
Maintenance
Table 8–3. Troubleshooting Chart: Diagnostics During System Operation (Cont.)
Message
Displayed
SYS WARNING
XPR RSLT
ERR
Evaluated
expression returned
a result that was not
a checkword in Ch.
1 or Ch. 2.
User Response
N / ENTER
Failure Message
‘XPR#xxx/CHy’
xxx = the Expression
Y = Channel Number of
failed expression
N / ENTER to continue
After all failed
expressions have been
displayed, ‘END ERR
DATA’ appears.
Corrective Action
Determine if error
data from other
failures may have
contributed to the
expression result
failure.
Examine parameter
values of the product
term which failed, to
determine whether a
parameter value is
an incorrect
codeword.
NO VRD
FRONT
VRDFRNT-DI is
false and
communication
between CPU/PD
and VRD boards
remain intact.
C / ENTER
Verify voltage
appears on Vital
Input board (DI) and
DI board LED lights.
If not,
troubleshooting
external to the VPI
module is required.
If DI board LED
lights, replace board.
Verify continuity of
cable wiring.
Verify VRD switch in
position F.
VSC DIAG
ERR
CPU/PD failed to
obtain data from a
VSC board on a 1second basis.
VSC program has
failed and has
stopped or is
undergoing reset
condition.
VSC (3) DIP
switches in wrong
position.
N / ENTER
Failure Message
‘VSC BD#x/yy’
Check bus
connections on
module
Motherboard.
Replace VSC board
if condition
continues.
Verify VSC switches
are set properly per
application.
SYS WARNING
SYS WARNING
Possible
Cause(s)
P2086B, Volume 1, Rev. D, Nov/13
x = Module number
y = Slot number
8-43
Alstom Signaling Inc.
Maintenance
Table 8–3. Troubleshooting Chart: Diagnostics During System Operation (Cont.)
Message
Displayed
SYS WARNING
CSEX DIAG
ERR
SYS WARNING
V TIMER ERR
Possible
Cause(s)
User Response
Failure of CPU to
obtain data from a
CSEX board on a 1second basis.
Indicates CSEX
program has failed
and has stopped or
is undergoing reset
condition.
N / ENTER
Failure Message
‘CSEX BD#x/yy’
Vital Timer
expression (FSVT or
PPVT) returned a
result that was not a
codeword for Ch. 1
or CH. 2, or an error
in reading time
selection jumpers for
a FSVT expression.
Note: FSVT = FieldSettable Vital Timer
PPVT =
Permanently
Programmed Vital
Timer (time is coded
into PROM)
N / ENTER
Failure Message
‘FSVT SW ERR’ =
error on Vital timer
‘SW a/bb/c/dd’
x = Module number
y = Slot number
a = switch 3 (1-8)
bb = wafer-type (TM,
UM, TS, US) jumpers
c = Module number
dd = Slot number
Failure Message
‘PPVT XPR#bbb’
Where
bbb =
Hexadecimal number of
PPVT expression
P2086B, Volume 1, Rev. D, Nov/13
8-44
Corrective Action
Check bus
connections on
module
Motherboard.
Type ‘X’ to clear and
monitor how often it
occurs.
Replace CSEX
board if condition
continues.
Check jumpers
installed on CSEX
board to proper
positions.
Check recorded
times on Timer
board label.
If error is due to a
Vital switch read,
check for proper
time selection
jumper's placement
(only one pin per
wafer).
If error is related to
FSVT or PPVT
timeout (not board
jumpers), use the
query RAM to
examine parameters
of final timer
expressions.
Replace FSVT
board if condition
persists.
Alstom Signaling Inc.
Maintenance
8.4
TROUBLESHOOTING WITH LEDS
This should determine
if problem is within
Vital Interface, CSEX,
or beyond.
Use HHT to further
check operation and
I/O.
If these indications
are present, VPI is
processing.
3. On = VRD being
driven, VRD should
be UP.
2. Flashing 1-Sec.=
board is being
addressed.
I/O BUS
INTERFACE
READ
CSEX
RELAY DRIVE
1 SEC CYCLE
NON-VITAL
INPUT
NON-VITAL
OUTPUT
VITAL RELAY
DRIVER
CPU/PD
WRITE
VSC
DIRECT
INPUT
WRITE
TIMER
VITAL
OUTPUT
1. Flashing 1-Sec. =
CPU is processing.
Figure 8-3 shows the on-off status, relative position, name, and function of diagnostic
LEDs in a typical VPI module. The following pages show the sequence that should be
followed for initial LED troubleshooting in a typical module. CAA file information is given
for installations where the CAA package is provided.
Figure 8-3. LED Troubleshooting Sequence (Sheet 1 of 5)
P2086B, Volume 1, Rev. D, Nov/13
8-45
Alstom Signaling Inc.
NON-VITAL
INPUT
CSEX
CPU/PD
NON-VITAL
OUTPUT
VITAL RELAY
DRIVER
I/O BUS
INTERFACE
VSC
DIRECT
INPUT
TIMER
VITAL
OUTPUT
P2086B, Volume 1, Rev. D, Nov/13
8-46
HHT will indicate
output energized but
not drawing current.
5. Vital Output
ON = output
energized.
(See front cover
label for source.)
HHT should indicate
trouble on ports.
4. Vital Input
(Recessed from
front of board)
ON = presence of
energy at specific
input.
(See front cover
label for source.)
Maintenance
Figure 8-3. LED Troubleshooting Sequence (Sheet 2 of 5)
Alstom Signaling Inc.
NON-VITAL
INPUT
NON-VITAL
OUTPUT
VITAL RELAY
DRIVER
P2086B, Volume 1, Rev. D, Nov/13
8-47
CSEX
RUNNING
APPLICATION
CPU/PD
I/O BUS
INTERFACE
VSC
DIRECT
INPUT
TIMER
VITAL
OUTPUT
(Output may not be
driving, see front
cover label for
source or driven
device.)
= Output turned ON.
or
7. Non-Vital Input and
Output LEDs
= Input energized
6. Should be ON if
CSEX is processing.
If local control is
possible, probably
a non-vital
communication or
code system error.
If CSEX is not
processing, neither
local control nor
remote control will
function.
Maintenance
Figure 8-3. LED Troubleshooting Sequence (Sheet 3 of 5)
Alstom Signaling Inc.
NON-VITAL
INPUT
NON-VITAL
OUTPUT
VITAL RELAY
DRIVER
CSEX
CPU/PD
I/O BUS
INTERFACE
VSC
DIRECT
INPUT
TIMER
VITAL
OUTPUT
P2086B, Volume 1, Rev. D, Nov/13
and logic.
order, analyze system
communications are in
If all CSEX (Non-vital)
format.
Pattern depends on
and outgoing data.
8. Flashes with incoming
Maintenance
Figure 8-3. LED Troubleshooting Sequence (Sheet 4 of 5)
8-48
Alstom Signaling Inc.
NON-VITAL
INPUT
CSEX
CPU/PD
NON-VITAL
OUTPUT
VITAL RELAY
DRIVER
P2086B, Volume 1, Rev. D, Nov/13
8-49
I/O BUS
INTERFACE
MSG RCV
1 SECOND
MSG XMIT
VSC
DIRECT
INPUT
TIMER
VITAL
OUTPUT
and .VSL file)
(See system plans
= Board processing.
10. FLASHING
with remote end.
= VSC communicating
9. FLASHING
Maintenance
Figure 8-3. LED Troubleshooting Sequence (Sheet 5 of 5)
Alstom Signaling Inc.
Maintenance
8.5
NON-VITAL SYSTEM DIAGNOSTICS AVAILABLE ON THE CSEX BOARD
Examples of displayed CSEX diagnostic menus with features are described in this
section. These examples are graphic representations and may vary slightly from what is
actually displayed.
8.5.1
Operational Overview
A terminal or PC connected to the Maintenance Access (MAC) port on the CSEX board
is needed for displaying its diagnostic menus (refer to Figure 8-4). These menus access
the CenTraCode II operating system and vary in use; some are used to report system
status while others are used for manual control.
VT-100 Terminal or equivalent
RS-232 Cable Connection
F-M Null Modem
CSEX Board
MAC
Port
RESET
SWITCH
Figure 8-4. Connection to the CSEX MAC Port
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Alstom Signaling Inc.
Maintenance
To access the diagnostics program through the MAC port, any terminal compatible with
Digital Equipment Corporation’s VT-100 may be used, or an IBM PC or compatible with
the proper terminal emulation software may be used. Alstom recommends a batteryoperated laptop PC equipped with terminal emulation software that allows capture of the
serial data stream. Display modes showing the codeline’s traffic can be invoked, and a
PC used as a display terminal allows the capture of displayed information to disk files
for further analysis at a future date. The following equipment is required for correct
operation of the MAC port:
1. A VT-100 compatible terminal (ANSI standard X3.64-1979) or an IBM PC (or
compatible) running VT-100 terminal emulation software. The required
communication setup is: 24 lines by 80 columns, 9600 baud (typical), 8 data bits, 1
stop bit, no parity, and no flow control.
2. Serial interface cable: standard DB-25 to DB-9 EIA232 null modem cable no longer
than 25 feet.
3. Proper application documentation for the location of interest.
4. Cabling as follows:
Table 8–4. CSEX1 Current Loop
CSEX1
(DB-9)
B&B 232
PCL
Converter
(DB-25)
B&B 232
PCL
Converter
(DB-25)
Terminal or
Computer
(DB-25)
B&B 232
PCL
Converter
(DB-25)
Terminal or
Computer
(DB-9)
1
RX+
14
2 (RX)
2 (TX)
2 (RX)
3 (TX)
8
RX-
19
3 (TX)
3 (RX)
3 (TX)
2 (RX)
5
TX+
25
7 (GND)
7 (GND)
7 (GND)
5 (GND)
7
TX-
23
Table 8–5. CSEX3 EIA232
CSEX3
(DB-9)
Terminal or
Computer (DB-25)
CSEX3
(DB-9)
Terminal or Computer
(DB-9)
2 (RX)
2 (TX)
2 (RX)
3 (TX)
3 (TX)
3 (RX)
3 (TX)
2 (RX)
5 (GND)
7 (GND)
5 (GND)
5 (GND)
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Maintenance
8.5.2
Using Menus
Diagnostics functions are selected from the CSEX menus. The term “menu” is used to
describe a list of choices that can access other lists of choices or diagnostic test topics
by selecting one of the options displayed near the bottom of the screen display. A menu
may be a portion of a screen display. If a menu is the predominant feature of a screen,
that screen is typically named according to the menu displayed (e.g. the “Main Menu”).
Any menu selection (or option) can be made as follows:
Press the Right or Left Arrow key or the Space Bar to highlight the menu or option of
interest and then press the Enter key.
Press the first letter of a menu or option. This letter is usually displayed in uppercase.
Press ‘E’ (Exit) to exit from any menu, although certain submenus are exited by
pressing ‘Q’ (Quit).
Simultaneously press Ctrl and ‘E’ to return directly to the Main Menu from any submenu.
After a menu option is selected, additional information may be required and the user will
be prompted to add specific data.
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Alstom Signaling Inc.
Maintenance
8.5.3
Menu Structure
Figure 8-5 shows the selection path from the CenTraCode II Main Menu to the other
menus available. The Main Menu is essentially divided into two functional parts,
Emulation and System. This “menu tree” provides an overview of the non-vital VPI
system diagnostic menus and their options.
This section describes each menu or screen, available options and user selection path.
The path lists in order the selection process for the menu or screen being described.
The menus normally used are listed first and then the entire available menu structure is
listed.
CAUTION
Certain diagnostic menu options can have an effect on non-vital system
operations. Be careful to return to the Main Menu when done accessing the
diagnostic information. Diagnostic tasks run at a lower priority than those
system tasks supporting the primary purpose of the application. Because of
this, some displays may at times appear to be incorrect. This usually will
occur because the presentation of the data on the terminal screen occurs
after the event being presented.
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Alstom Signaling Inc.
4
OPTIONAL EMBEDDED DataLogger (see P2326D)
NOT INTENDED FOR ACTUAL USER OPERATION
EMULATION DIAGNOSTICS MENU SHOWN IS FOR DataTrain VIII
OPTIONAL VITAL DIAGNOSTIC PROTOCOL (see P2346W)
OPTIONAL TRAIN-TO-WAYSIDE COMMUNICATIONS MODULE
4
5
6
P2086B, Volume 1, Rev. D, Nov/13
Select
Port
8-54
Characteristics
and contents of
messages to be
sent or waiting at
buffers
Reset
Message
Counts
Reset
Counts of
DataTrain VIII
messages sent &
received (by type)
Counts
Manually
post a
message
to the
application
Post
Local
Select
Port
6
5
Flags
View/set
communications
flags
View/set
communications
timers
Timers
Display
application/
emulation
messages
Disp
View/set protocol
operating mode
Show Info
View Port
Setup
Characteristics and
contents of the Next/Last
station's control, indication
and special messages sent
from this port
Select
Port
System
MAIN MENU
Emulation
Monitor
message
traffic on
serial ports
Select
Port
System
1
3
3
Enter User
Password
3
1
Buffers
View current state of
inputs and outputs
Local
View serial port
status, and modify
configuration
Select
Address
View individual
memory location
in real time
Obtain application
parameter addresses
from LCS File
View section of
RAM
(memory dump)
Select
Address
Set System
Real-Time
Clock
I/O DC Line Ports Clock Memory Variable
2
Emulation Monitor System Diagnostic Logger HHT Tracker Password W
Emulation
Port Next Last Options Msg Diags Reset TWC Vital_Diags
3
SCREEN GIVEN IS DISPLAY ONLY
1
2
Maintenance
Figure 8-5. Menu Tree
Alstom Signaling Inc.
Maintenance
8.5.4
CSEX Main Menu
After power is applied and the system is initialized, the CSEX Main Menu (Figure 8-6) is
displayed on the terminal screen connected to the MAC port. If the Main Menu is not
displayed, simultaneously press ‘Ctrl’ and ‘E’ to jump from any submenu back to the
Main Menu. If any CSEX board resets occurred since the last time the system was
turned on, this information will appear above the Main Menu. This reset log is cleared
once the board is turned off.
Note that if the diagnostic password option has been activated, the password must be
entered prior to modifying settings that affect system operation.
When a choice is made in the Main Menu, a submenu may appear. The available submenus are Emulation, Monitor, Diagnostic and Logger. The menus and selections are
explained below. The Main Menu choices HHT_Use, Tracker and W are intended for
use by external software utilities, such as Alstom’s Tracker program (refer to Alstom
publication P2307), and are not discussed herein. Only menu choices used for normal
system analysis are discussed in this section.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Main Menu
Emulation Monitor System Diagnostic Logger HHT_Use Tracker Password W
Support Emulations Used
Figure 8-6. CSEX Main Menu
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Alstom Signaling Inc.
Maintenance
The following table describes the options available in the CSEX Main Menu. Many of
these options are explained more fully later in this section.
Table 8–6. CenTraCode II Main Menu Choices (Cont.)
Option
Description
Emulation
Invokes the Emulation Menu used to diagnose problems related to
communication protocol emulation operation. Subsequent menus
accessible from the Emulation Menu via its Diags menu choice are
fully documented in the respective Alstom pamphlet for each specific
protocol emulation installed (refer to the Alstom publication P2346
series).
Monitor
Starts the operation of the data monitor used to display message
traffic on specific serial ports. The Monitor Menu is displayed showing
the available data monitor options.
System
Displays the system configuration information consisting of:
• The application’s CSEX ID string
• System and CAA drawing numbers
• Application compilation time and revision
• System compilation time and revision
• Optional DataLogger compilation time and revision
• Serial ports usage and protocol emulation revision
Diagnostic
Provides access to system diagnostics used to locate hardware
problems, and evaluate software operation.
Logger
Provides access to the Alstom Embedded DataLogger diagnostic
menus. CSEX offers detailed event diagnostic capability when the
optional DataLogger module is stored in EPROMs on the CSEX board.
For details on this advanced data logging feature refer to Alstom
Publication P2326D.
HHT_Use
Permits use of the Handheld Terminal with a minimal subset of
diagnostics. Press ‘V’ (VT-100) to exit from HHT mode. This menu
choice is for the exclusive use of Alstom’s Tracker diagnostic utility
program that runs on a PC, and is not for actual user operation.
Tracker
This menu choice is for the exclusive use of Alstom’s Tracker
diagnostic utility program that runs on a PC, and is not for actual user
operation.
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Alstom Signaling Inc.
Maintenance
Table 8–6. CenTraCode II Main Menu Choices (Cont.)
Option
Password
Description
Permits entry of an application password to allow modification of
system settings. If a diagnostic password has been specified in the
non-vital application, the password must be entered before modifying
any setting that affect system operation. Only authorized persons
should know the diagnostic password.
Initially, “Password Disabled” appears at the upper left of the Main
Menu; however, if no password has been defined in the application,
then no message appears and the Password menu choice is disabled.
Otherwise, select Password and then enter the correct diagnostic
password; “Password Enabled” will now be displayed. The operator
may now activate features that affect system operation. If there is no
MAC port activity for more than 30 minutes, however, the system will
automatically disable the diagnostic password forcing authorized
personnel to reenter it.
W
This menu choice is for the exclusive use of Alstom’s Watcher
diagnostic utility program that runs on a PC, and is not for actual user
operation.
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Alstom Signaling Inc.
Maintenance
8.5.5
Emulation Menu
The Emulation Menu (see Figure 8-7) is displayed by selecting Emulation from the Main
Menu. The Emulation Menu provides access to communication protocol emulations
loaded in the CenTraCode system. Each protocol emulation, such as Alstom’s
DataTrain VIII (DT8), is assigned to a specific serial port in the non-vital application.
Selection Path:
•
Main Menu
•
Emulation
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Next Last Optns Msg Diags Reset TWC Vital_Diags Exit
Figure 8-7. Emulation Menu
Refer to Table 8–7 for a brief description of the available options in the Emulation Menu,
after which the menu choices are described in more detail.
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Alstom Signaling Inc.
Maintenance
Table 8–7. Emulation Menu Choices
Option
Description
Port
Select the serial port of interest (i.e. enter the port number from 1 to 5)
and view the port’s setup. The serial port number must be specified
prior to using the Next, Last, Optns, Msg or Diags menu choices.
Next
Display the addresses and current contents of control, indication and
Special Message buffers for the next station on the selected serial
port; if only one station is defined for the codeline port, then the Next
and Last options behave identically.
Last
Display the addresses and current contents of control, indication and
Special Message buffers for the previous station on the selected serial
port
Optns
View the serial port setup: baud rate and the data format (data bits,
stop bits, parity).
Msg
Observe message traffic (controls and indications) between the nonvital application logic and the emulation, and enter and manually post
a control or a Special Message to the application logic.
Diags
Execute protocol emulation specific diagnostics.
Reset
Reset the entire system. Use this choice with care since it causes the
CSEX software to reinitiate its start-up sequence, as if the system
were turned off then back on.
TWC
Access the Train-to-Wayside Communications (TWC) diagnostics
menu (if applicable).
Vital_Diags
Access the optional Vital Diagnostic Protocol (VDP) diagnostics menu,
described in Alstom publication P2346W.
Exit
Return to the Main Menu.
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Alstom Signaling Inc.
Maintenance
8.5.5.1
Emulation Menu Choice: Port
The Port menu choice allows the user to specify the CSEX serial port (1 to 5) on which
the communication protocol is installed. The serial port number must be specified before
using the Next, Last, Optns, Msg or Diags options in the Emulation Menu. Both the port
usage and the type of protocol loaded are displayed, an example of which is shown in
Figure 8-8.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Next Last Optns Msg Diags Reset TWC Vital_Diags Exit
Port 1 has 1 stations using 51612-001-23 REV F36 Aug 31 2001, 13:49:56
DATATRAIN (R) VIII
Figure 8-8. Emulation Menu – Select the Serial Port
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Alstom Signaling Inc.
Maintenance
8.5.5.2
Emulation Menu Choice: Next or Last
When the Next or Last menu choice is selected, the current information for a single
station is displayed once. This information is not updated in real time. See Figure 8-9 for
a sample screen. The Next and Last menu choices are most useful for a port having
multiple stations, else information for station 1 will always be displayed when Next or
Last is selected.
The station information consists of:
•
Control and indication station addresses and the total number of binary bits in each
address.
•
The length of each message: control, indication and Special.
Each message’s starting buffer address in RAM (intended for Alstom technical
personnel only).
The most recently posted control, indication and Special Messages.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Next Last Optns Msg Diags Reset TWC Vital_Diags Exit
Station #1
Control address(08) = 00000050
Message length = 128, Located at 0000:77EC
Last message posted:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Indication address(08) = 00000050
Message length = 536, Located at 0000:786D
Last message posted: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10
Special message
Message length = 0, Located at 0000:0000
Last message posted:
Figure 8-9. Emulation Menu – View a Station’s Messages
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Alstom Signaling Inc.
Maintenance
This example shows that the control address for station 1 is 50 with a length of 8 bits.
The message itself contains 128 bits (i.e. parameters) and is located in memory
beginning at address 0000:77EC. The message contents are shown as a series of 16
hexadecimal bytes, eight bits each. In this example, all 128 bits in the last received
control message are false (0).
The indication address is also 50 and has a length of eight bits. The message itself is
536 bits in length and is located in memory beginning at address 0000:786D. The last
indication sent is 00 00 00 00 … 00 00 00 00 10. Refer to Table 8–8 to convert data
from hexadecimal to binary. In this example, no Special Message buffer is defined in the
application for station 1.
Table 8–8. Hexadecimal to Binary Conversion
Hex
Binary
Hex
Binary
Hex
Binary
Hex
Binary
0
0000
4
0100
8
1000
C
1100
1
0001
5
0101
9
1001
D
1101
2
0010
6
0110
A
1010
E
1110
3
0011
7
0111
B
1011
F
1111
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Alstom Signaling Inc.
Maintenance
8.5.5.3
Emulation Menu Choice: Optns
The Optns menu choice is used to view the selected communication port’s setup. Figure
8-10 shows an example screen if Optns is selected.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Next Last Optns Msg Diags Reset TWC Vital_Diags Exit
Baud rate = 1200, 8 Data Bits, 1 Stop bits, Even parity
Figure 8-10. Emulation Menu – View Port Setup
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Alstom Signaling Inc.
Maintenance
8.5.5.4
Emulation Menu Choice: Msg
Message flow between the communication protocol installed on a serial port and the
non-vital application logic can be monitored using the Msg menu choice. A new menu is
displayed (see Figure 8-11) offering the following selections: Post, Disp (Display), Spcl
(Special), and Mode. These options are discussed in detail below.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode
Exit
Figure 8-11. Emulation Menu – Message Sub-Menu
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Alstom Signaling Inc.
Maintenance
8.5.5.5
Emulation/Message Sub-Menu Choice: Post
The Post menu choice allows user-entered keyboard input to replace the control
message normally posted by the protocol emulation. This feature is useful to determine
if a problem is in the application or the emulation.
To post a control, select the Post option. If more than one station exists, a prompt for
the station number will appear. In this case, enter the proper station number (the
maximum number allowed is displayed). A prompt showing the size of the control
message appears, at which point enter the new data as a series of hexadecimal bytes.
When the entry is complete, the message is posted to the application logic. At most 96
bits (12 bytes) may be manually posted. Note that if the protocol loaded on this port
receives a valid control message, it will be posted by the protocol, thus overwriting the
control that was manually posted.
Figure 8-12 shows an example screen if the Post option is selected for a control
message containing 16 bits (2 bytes).
WARNING
Posting control data in this manner will cause changes to the operation of the
system.
Post Disp Spcl Mode
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Post Message Interface
Exit
WARNING: OPERATION WILL BE ALTERED. Enter message in HEX (2 BYTES):
New Byte (62H):
Figure 8-12. Post a Control Message
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Alstom Signaling Inc.
Maintenance
8.5.5.6
Emulation/Message Sub-Menu Choice: Disp
The Disp menu choice displays the data portion of messages posted between the
protocol emulation and the non-vital application logic, updated in real-time. Figure 8-13
shows a typical screen when the display format is set to “Original”; various data display
formats are offered via the Mode menu choice discussed later in this section.
The terms “control” and “indication” refer to inbound (received) and outbound (sent)
messages, respectively. A Special Message is a bi-directional buffer containing
protocol-specific flags used to report or control message flow. Depending upon the
application, no Special Message buffer may be defined. The use of flags in the Special
Message buffer varies among the communication protocols supported in VPI. For
specifics, refer to each protocol’s manual (Alstom publication series P2346).
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode
Exit
Last control posted:
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Last indication posted:
00
Last Special message posted:
Figure 8-13. Display Messages in Real-Time
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Alstom Signaling Inc.
Maintenance
8.5.5.7
Emulation/Message Sub-Menu Choice: Spcl
The Spcl menu choice allows user-entered keyboard input to be posted to the protocol’s
Special Message buffer. To post a Special Message, select the Spcl option. If more
than one station exists, a prompt for the station number will appear. In this case, enter
the proper station number (the maximum number allowed is displayed). A prompt
showing the size of the Special Message appears, at which point enter the new data as
a series of hexadecimal bytes. When the entry is complete, the message will be posted
to the application logic. At most 96 bits (12 bytes) may be manually posted. Note that if
the protocol loaded on this port receives messages, this may cause the protocol to write
to the Special Message buffer, potentially overwriting the information that was manually
posted.
Figure 8-14 shows an example screen if the Spcl option is selected for a Special
Message containing 24 bits (3 bytes).
WARNING
Posting special message data in this manner will cause changes to the
operation of the system.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode
Exit
WARNING: OPERATION WILL BE ALTERED. Enter message in HEX (3 BYTES):
New Byte (0CH):
Figure 8-14. Post a Special Message
P2086B, Volume 1, Rev. D, Nov/13
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Alstom Signaling Inc.
Maintenance
8.5.5.8
Emulation/Message Sub-Menu Choice: Mode
The Mode menu choice results in the display of several additional menu options (see
Figure 8-15) that affect the format of message data displayed using the Disp option in
the Message Submenu (as shown in Figure 8-13). After the display format has been set
to either Original, New Hex, Binary or Inverse, message contents are automatically
displayed and updated in real-time as if the Disp menu choice had been selected.
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode Exit
Original New Hex
Binary Inverse Exit
Figure 8-15. Select the Message Display Mode
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Alstom Signaling Inc.
Maintenance
The following table describes the options in this menu:
Table 8–9. Message Display Modes (Cont.)
Option
Description
Original
Restores the display format to the default setting, as was illustrated in
Figure 8-13. In this format, data for a single station is shown as a
series of hexadecimal bytes, wrapping between lines on the display
based on the message lengths for controls, indications and Special
Messages.
New Hex
In this format, message data is shown 24 hexadecimal bytes at a time
from left to right on a single line per station for up to four stations, with
the station number shown at the start of each line of data (see Figure
8-16). Multiple stations’ data (up to four) is shown on subsequent lines
as needed. If a message (control, indication or Special) exceeds 192
bits (24 bytes), use the ‘V’ (increment byte numbers) and ‘B’
(decrement byte numbers) keys to bring additional data bytes (one at a
time) into view. At most 24 bytes of a message’s data may be viewed
at a time in this format. If more than four stations are defined on the
port, use the ‘G’ and Space Bar keys to view data for additional
stations. Press the ‘H’ key to bring the display back to the first station,
first byte setting.
Binary
This display format is similar to New Hex except that message data is
shown eight bytes at a time in binary (eight bits per byte). The least
significant bit of each byte is shown at the left of each byte of data. For
example, the hexadecimal byte 0x01 is shown as 10000000 in Binary
format. Use this format to view message data exactly as posted to the
non-vital application logic. Figure 8-17 shows the same data as in
Figure 8-16 (New Hex format), but in Binary format instead.
Inverse
This display format is similar to Binary except that the least significant
bit of each byte is shown at the right of each byte of data. For example,
the hexadecimal byte 0x01 is shown as 00000001 in Inverse format.
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Alstom Signaling Inc.
Maintenance
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode Exit V_Left B_Right G_Up _Down Home
Bit 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Last control posted:
01
00 04 00 00 00 00 00 26 00 51 00 F2 00 00 00
02
00 00 00 00 00
03
00 00 00 00 00 00
04
00 00 00 00 00 00 00 00 00 00 00 00
Last indication posted:
01
1C 02 4A 00 01
02
00
03
00
04
00 00
Last Special message posted:
01
0A 12 00
Figure 8-16. Display Messages – New Hex Display Option
Alstom SIGNALING
CenTraCode II (R) Maintenance
Emulation Control Module
Port Message Interface
Post Disp Spcl Mode Exit V_Left B_Right G_Up _Down
Bit 01 02 03 04 05 06 07 08
Last control posted:
01
00000000 01000000 00000000 00000000 00000000
02
00000000 00000000 00000000 00000000 00000000
03
00000000 00000000 00000000 00000000 00000000
04
00000000 00000000 00000000 00000000 00000000
Last indication posted:
01
00111000 01000000 01010010 00000000 10000000
02
00000000
03
00000000
04
00000000 00000000
Last Special message posted:
01
01010000 01001000 00000000
System
Home
00000000 00000000 01100100
00000000
00000000 00000000 00000000
Figure 8-17. Display Messages – Binary Display Option
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Alstom Signaling Inc.
Maintenance
8.5.6
Emulation Diagnostics Menu
Select Diags from the Emulation Menu for protocol-specific diagnostic functions. The
following is a sampling of Datatrain VIII specific diagnostic menus. Refer to Alstom
publication P2346E for detailed information on Alstom’s DataTrain VIII protocol. Figure
8-18 shows a typical protocol diagnostics menu, specifically the DataTrain VIII
Diagnostics Menu.
Selection Path:
Main Menu | Emulation | Port (serial port selection from 1 to 5) | Diags
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
Counts Reset Show Info Local Timers Flags Exit
Figure 8-18. DataTrain VIII Diagnostics Menu
DT8 Counts Screen (Emulation Diagnostics)
Select the DataTrain VIII Counts menu choice to check the status of communications on
the selected port. This dynamically updated screen may be out of step with the actual
I/O because of a particular combination of application choices. Figure 8-19 shows a
typical Datatrain VIII messages counts screen.
Selection Path:
Main Menu | Emulation | Port (serial port selection from 1 to 5) |Diags |Counts
While viewing the messages counts, use the Reset option to set the number of
messages both sent and received to zero (doing so has no effect on system operation).
In this screen “ain” is the total number of DataTrain VIII Acknowledge messages (type
AA) received, whereas “aout” is the total number of Acknowledge messages sent. “bin”
is the number of Poll messages (type AB) received, etc.
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Alstom Signaling Inc.
Maintenance
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Emulation Control Module
addr ain bin cin din ein aout bout cout dout eout ack c_state
50 0 0 0 0 0 0 0 0 0 55 55 1
Msg Aborts = 1
Counts Reset Show Info Local Timers Flags Exit
Figure 8-19. DataTrain VIII Counts Screen
Several additional DataTrain VIII diagnostic screens are available. Refer to Alstom
publication P2346E for detail on the DataTrain VIII protocol.
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Alstom Signaling Inc.
Maintenance
8.5.7
Monitor Menu
The data monitor screen is viewed by selecting Monitor from the Main Menu (Figure
8-6). Use the data monitor to observe message traffic on one or more code system
ports, as shown in Figure 8-20.
Selection Path:
Main Menu | Monitor | Port (port selection from 1 to 5)
Alstom SIGNALING
CenTraCode II (R) Maintenance System
Monitor Module
Logging: ON Scroll: ON
DC events: OFF
Serial messages: REMOTE
Field Changes: OFF
Other messages: OFF
ANSI mode: OFF
Ports: 1
Local I/O Change DC Other Ansi Scroll Port EXIT
>T<
>R<
>S<
>T<
>R<
>S<
AE
00
00
AE
00
00
50
00
00
50
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00 00 00 00
00 00 00 00 00 00 00
00 00 00 00 00 00 00
00 00 00 00 00 00 00
Figure 8-20. Data Monitor Screen
Data monitor operation is a background task. The displayed information may be preempted by other processor operations of a higher priority. As a result, it may not be
possible to report all code system port message traffic in monitor mode. Split bytes and
CRC checksums are not shown on this display.
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The following table provides a description of the choices available in the Monitor Menu.
Table 8–10. Monitor Menu Choices
Option
Description
Local
Toggle the Local/Remote serial message flag. When in Local mode,
only local messages are displayed.
I/O
Toggle the input/output status display.
Change
Toggle the field changes display. When on, field I/O are displayed in
order of their occurrence.
DC
Display DC type events (not used in electronic code applications).
Other
Display communication error messages and other miscellaneous
message types.
Ansi
Select ANSI mode in which the unit sends control codes to format the
screen so that data appears in organized order. These codes cannot
be used if a printer or other devices is connected to the port.
Scroll
Start or stop updating the screen so that message traffic can be
monitored and displayed in real time.
Port
Select the number of the port (or ports), from 1 to 5, to monitor and
display. Activity on multiple ports may be observed at the same time.
EXIT
Exit the data monitor. Note that Ctrl + ‘E’ should not be used to exit
from the data monitor screen.
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The status of the data monitor fields is displayed at the top of the screen, as shown in
the following table.
Table 8–11. Data Monitor Status Indicators
Field
Description
Logging
On/off status of the data monitor; this is normally turned on.
Scroll
On/off status of the display; turn “Scroll” on for real-time display of
message traffic.
DC Events
On/off status of the DC display; this is normally turned off.
Serial
Messages
Serial message type (remote or local); this is normally set to remote.
Field Changes
Field changes display is turned on or off; this is normally turned off.
Other
Messages
Other messages display is turned on or off; this must be on for error
messages to be displayed.
ANSI Mode
ANSI display mode is turned on or off; this is normally turned off.
Ports
Reports message traffic for only the code line ports displayed.
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When “Scroll” is on, message traffic on the selected port(s) is displayed. A descriptor
indicating the type of message received or transmitted precedes each message.
Table 8–12. Message Descriptors
Message
Type
Description
>T<
Transmitted message (e.g. an indication).
>R<
Received message (e.g. a control).
>P<
Received poll message.
>S<
Supervisory or status message.
>-CFG-<
Received system configuration message.
ERROR
The received message contained an error.
Communication problems can be monitored in this screen and will be evidenced by the
display of error messages. Specific messages vary between the communication
protocols supported by Alstom. Note that “Other Messages” must be turned on in order
for error messages to be displayed by the data monitor.
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8.5.8
System Configuration Information
System configuration information is displayed by selecting System from the Main Menu
(Figure 8-6). This screen shows system configuration information, including the system
and CAA drawing numbers, application compilation time, system compilation time, and
active serial ports and their usage. No options are available from this screen; press any
key to return to the Main Menu. Figure 8-21 shows a typical system configuration
screen.
Selection Path:
Main Menu | System
Alstom SIGNALING
CenTraCode (R) II Maintenance System
Main Menu
Application Software : 33028-982GR00H Generated : 08/31/2001 13:51
CSEX ID : LOCATION XYZ
CAA Drawing No. : 31746-029 GR00
System Generated: 51615-408-12 Rev H12 Jul 21 2000, 16:14:23
51612-012-016 Rev A16 CenTraCode II Data Logger Apr 30 2001 at 12:44:50
Port 1: 51612-001-23 REV F36 Aug 31, 2001, 13:49:56 DATATRAIN(R) VIII
Port 2: Not used
Port 3: Not used
Port 4: Not used
Port 5: Not used
Figure 8-21. CenTraCode II System Configuration Screen
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8.5.9
System Diagnostics Menu
The System Diagnostics Menu is displayed by selecting Diagnostic from the Main Menu
(Figure 8-6). The System Diagnostics Menu provides access to the hardware so that
low level testing can be done. The menu also provides access to many board functions
such as the non-vital I/O, serial ports, DC interface, memory, and much more. Some
options when executed may result in disruption of online operation. These tests are only
intended to be run when the system is offline. Figure 8-22 shows the System
Diagnostics Menu.
Selection Path:
Main Menu | Diagnostic
Alstom SIGNALING
CenTraCode (R) II Maintenance System
System Diagnostics
I/O DC-line Ports Clock Memory Variable Show_Port Next Test_Ports ROM_Chksum
Ok_Stack_Test Exit
Figure 8-22. CenTraCode II System Diagnostics Menu
System diagnostic options can be selected from the System Diagnostics Menu and from
a Secondary Diagnostics Menu (described later) that is accessed via the Next menu
choice in the System Diagnostics Menu. Each menu choice leads to a submenu or
requires user input. The choices available in the System Diagnostics Menu are listed
next. Most menu choices are intended for use by Alstom technical personnel for system
troubleshooting, and are not designed for field maintainer use. Some options that affect
system operation can be password-protected.
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Table 8–13. System Diagnostic Menu Choices (Cont.)
Option
I/O
Description
This option leads to a submenu. Use the Local menu choice in this
submenu to view the current state of all non-vital inputs and outputs
in the VPI system. I/O states are updated in real-time only after the
Disp menu choice has been selected. The state of an input port is
either on (1) or off (0), and each is debounced at the rate shown
(e.g. 50 ms).
The state of each output port depends upon its definition in the
application, and is shown as a single hexadecimal digit Each bit (four
total) of this hexadecimal digit represents the various types of nonvital outputs (NVO) available in a VPI system, as shown below:
Code
NVO State
0001 (1)
Steady on
0010 (2)
0100 (4)
Source
Pulse, width 1
0101 (5)
Pulse, width 2
1000 (8)
Normal flash, phase A
1001 (9)
1100 (C)
Fast flash, phase A
Normal flash, phase B
1101 (D)
Fast flash, phase B
From the I/O submenu, individual outputs may be turned on and off
manually using the Off, Pulse and Flash menu choices. To do so,
first halt the non-vital application logic using the Caa menu choice.
Note that this action will affect normal system operation. Use the
Rate and Mode menu choices to vary the type of each pulsed or
flashed output port, and use the All menu choice to apply the latest
output type selected to all displayed output ports. The Src/Snk (sink
and source) menu choice is applicable to CenTraCode II-s only, and
not to CSEX.
DC-line
Monitor the DC codeline, or toggle a DC relay. This menu choice is
primarily intended for use by Alstom technical personnel.
Ports
View a code line port’s setup and current status, and manually
modify its configuration (using the CFG submenu choice). Also
allows hardware control lines to be manually toggled. This menu
choice is primarily intended for use by Alstom technical personnel.
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Table 8–13. System Diagnostic Menu Choices (Cont.)
Option
Description
Clock
Set the system’s battery-backed real-time clock (RTC) date/time
registers. The RTC is used primary to time-stamp events stored by
Alstom’s optional DataLogger module (refer to Alstom publication
P2326D). The CSEX clock must be initialized when the VPI system
is first put into service, power to the module is left off for more than
48 hours, or when the CSEX board’s EPROMs are replaced. To set
the RTC, use the Clock menu choice followed by the Time (T), Date
(D) and then the Initialize (I) submenu choices. Take care to enter
the date and time in the exact format shown. Select Exit (E) when
done.
Memory
Display an area of CSEX system memory, 256 bytes at a time, and
optionally modify a byte of memory. The RAM starting address must
first be entered in Intel-hex segment:offset notation (i.e., ssss:oooo).
This menu choice is primarily intended for use by Alstom technical
personnel.
Variable
Examine the contents of a non-vital memory location. The address to
be monitored must be entered in Intel-hex segment:offset notation
(i.e. ssss:oooo). Typically this is the address of a non-vital
application parameter obtained from the Symbol Table Report in the
application’s LCS file. Either a 1- or 2-byte (i.e., integer) location may
be monitored. Press any key to stop monitoring the variable.
Show_Port
Examine the contents of a CPU I/O port. This menu choice is to be
used by Alstom technical personnel only.
Next
Advance to the next level of CenTraCode II diagnostics and display
the Secondary Diagnostics Menu described next in this section.
Test_Ports
Enable the system’s “serial port test”. Doing so will severely
encumber system operation and is to be used by Alstom technical
personnel only.
ROM_Chksum
Display the checksum stored in the combined system/application
program memory (PROM).
Ok_Stack_Test
Test stack space used by the currently running system task. This
menu choice is to be used by Alstom technical personnel only.
Exit
Return to the Main Menu.
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The Secondary Diagnostics Menu is accessed using the Next menu choice in the
System Diagnostics Menu. It offers additional diagnostic features, most of which are
intended for use by Alstom technical personnel for system troubleshooting, and are not
designed for field maintainer use. The choices in the Secondary Diagnostics Menu are
described next.
Table 8–14. Secondary Diagnostics Menu Choices
Option
Description
Mode
Change the operating mode of one of the system’s tasks. This menu
choice affects system operation and is to be used by Alstom
technical personnel only.
Time
Computes and displays average timing of the non-vital application
logic and the tasks running in the system. This is a non-destructive
test. Typically the calculation is based on 1000 tasking loops and a
timing base of 1 and a resolution of 1. This menu choice is primarily
intended for use by Alstom technical personnel.
Remove
Remove a task from the system’s round-robin task loop. This menu
choice affects system operation and is to be used by Alstom
technical personnel only.
Insert
Insert a task into the system’s round-robin task loop. This menu
choice affects system operation and is to be used by Alstom
technical personnel only.
CAA
Suspend/resume operation of the non-vital application logic. This
menu choice affects system operation and is to be used by Alstom
technical personnel only.
Oprtr
Change the operating mode of one of the system’s tasks (similar to
the Mode menu choice). This menu choice affects system operation
and is to be used by Alstom technical personnel only.
Disp
Display information on all currently installed system tasks, such as
stack space and usage. This menu choice is primarily intended for
use by Alstom technical personnel.
Reset
Show the total number of system resets since power up, and
optionally perform a manual system reset. Use this choice with care
since it causes the CSEX software to reinitiate its start-up sequence,
as if the system were turned off and back on.
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Table 8–14. Secondary Diagnostics Menu Choices
Option
Description
Sys_Err
List all system errors logged since power up. Refer to Table 8–15 for
all system errors that may be logged by the self-checking mechanism
built into the CSEX System Software. All accumulated errors (up to
20) are automatically shown above the Main Menu, or may be
viewed by selecting the Sys_Err menu choice in the Secondary
Diagnostics Menu. In the latter case, errors may be erased from
memory by selecting ‘R’ (Reset).
Exit
Return to the System Diagnostics Menu.
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The following table lists all CenTraCode system errors that may be displayed at the
MAC port diagnostic menu by the self-checking mechanism built into the CenTraCode
System Software. Note that all logged errors are lost by the system in the event of
power loss. The error codes shown in this table apply to the 2-digit diagnostic display on
CSEX3 and CenTraCode II-s boards only. In most cases, contact Alstom to resolve the
cause of displayed errors.
All accumulated errors (up to 20) are automatically shown above the Main Menu, or
may be viewed by selecting the Sys_Err menu choice in the Secondary Diagnostics
Menu. Displayed error messages are of the form:
“Logged mm dd hh:mm:ss – Error – message”
Table 8–15 details message and its associated 2-digit error code (applicable to CSEX3
and CenTraCode II-s only). In this table, TCB stands for the “Task Control Block”
number, whose value is meaningful only to Alstom technical personnel.
Table 8–15. System Errors (Cont.)
Code
Displayed Error Message
Possible Cause(s)
00
None
No errors detected (normal operation).
11
Memory Shortage on port n
Insufficient system RAM for
application requirements.
12
No protocol on port n
No valid communication protocol
installed on this serial port.
13
Protocol init on port n
Protocol emulation initialization failure.
14
Tasking on port n
Failure in loading a port’s task.
15
Ring on port n
Failure in RAM allocation for a port’s
serial ring buffers.
16
Port on port n
Failure in RAM allocation for a port’s
internal data structures.
17
CAA Indication Flag on port n
Invalid value for a RAM indication
buffer flag.
18
CAA Control Flag on port n
Invalid value for a RAM control buffer
flag.
19
CAA Spcl Msg Flag on port n
Invalid value for a RAM special buffer
flag.
1a
Protocol Error n
Error code for protocol emulation
initialization (error 13) or other failure.
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Table 8–15. System Errors (Cont.)
Code
Displayed Error Message
Possible Cause(s)
1b
Unknown reset TCB nn Active
Reset due to unknown cause:
Momentary power loss
Reset button manually pressed
Miscellaneous hardware or software
failure
1c
Watchdog caused reset TBC nn
Active
The main task loop has stalled – the
system performs an automatic reset.
1d
Software reset called
Operator-induced software reset
caused by:
Diagnostic input switch (CenTraCode
II-s or CSEX3 only)
MAC port diagnostics – Reset option
PROM or RAM failure (automatic
system reset)
1e
Prom error at n
Test of RAM or PROM failed – the
system performs automatic reset with
the diagnostic display showing Error
1d.
n Meaning
1 System’s startup RAM test failed
2 System’s startup PROM checksum
verification failed
3 Not assigned (future)
4 System’s periodic PROM checksum
test failed
1f
Reset due to stack crash, task number A task’s stack or its local memory area
nn
has been corrupted, or the diagnostic
test of a serial port’s local memory
area failed – the system performs an
automatic reset.
20
CRC error in port n local memory
Diagnostic test of a serial port’s local
memory area failed – the system
performs an automatic reset.
22
Application is not running
The application logic is no longer
running – the system performs an
automatic reset.
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Table 8–15. System Errors (Cont.)
Code
Displayed Error Message
Possible Cause(s)
23
Flag error – Pointer nnnn
Application buffer flag locked “in use”
and the application logic is no longer
running – the system performs an
automatic reset with the diagnostic
display showing Error 22.
24
CS:IP error–last TCB active nn
Executing code from RAM (invalid) –
the system performs an automatic
reset.
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8.6
8.6.1
EMBEDDED DATALOGGER (DL)
General Information
An Alstom Signaling CenTraCode (CTC) system is composed of several software
modules. Each module is dedicated to performing a specific function in the system.
Although all modules do not share data with each other, all have links to the CTC
operating system software. Alstom’s optional Embedded DataLogger module provides
the user with real-time on-line event logging with time-stamping and reporting
capabilities. Complete detail on DataLogger can be found in Alstom publication
P2346D.
When used in an application, the DataLogger (DL) module provides interfaces suitable
for accepting data to be logged from other installed modules. It also provides three NonVital Application (NVA) monitoring modules. These modules perform specific functions
and pass data to the DL for storage. The first of the three modules is dedicated to
monitoring changes in user-composed messages called User Non-Vital Messages
(UNVM) or simply User Messages. The second module is dedicated to monitoring
changes occurring at Non-Vital Inputs (NVI) and the third is dedicated to monitoring
changes occurring at Non-Vital Outputs (NVO).
8.6.2
Real-Time Clock
All logged data bears a time stamp resolved to one second relative to the system clock.
The CSEX3 CPU boards are each equipped with a battery-supported, hardware-based
Real-Time Clock (RTC). Time is kept by a software clock in the CSEX1 CPU board.
Since a CSEX1 board has no battery protection, its software clock is lost and must be
resynchronized with real time whenever the board is reset.
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8.6.3
Memory Usage
Each CTC system reserves a portion of battery-backed memory (BBRAM) for data
logging – 64K in CSEX1 and 256K in CSEX3. The memory in CSEX1 is volatile (without
battery support), whereas the memory in CSEX3 is battery-backed. The DL partitions its
assigned memory space into three major components: the Scratch Pad, the Directory,
and the Data Log Area (see Figure 8-23).
Scratch Pad (234 bytes)
Operating parameters and
intermediate variables are stored in
this area.
Directory (3840 bytes)
This area contains room for 192
Directory Frames (20 bytes each).
Data Log Area (CSEX1: 61,462 bytes)
(CSEX3: 258,070 bytes)
Log Frames are stored in this area.
Figure 8-23. DataLogger Memory Usage
Scratch Pad: The DL program reserves 234 bytes of its memory to support
housekeeping activities. This secured area, referred to as the Scratch Pad, holds
DataLogger’s operating parameters and intermediate data.
Directory: Another 3,840 bytes of the DataLogger’s memory hold Directory Frames. This
area is a circular buffer large enough to hold 192 Directory Frames. A record is entered
in this area to mark the creation of a new directory, typically each hour. Each record has
a fixed length of 20 bytes and is referred to as a Directory Frame.
Data Log Area: The remaining portion of DataLogger’s memory is used for recording
logged events, called Log Frames. The first 17 bytes of each Log Frame contain
overhead information that distinguishes the different types of event data. Log Frames
are variable in length due to the various types of data that may be logged.
The Data Log Area is a circular buffer. Events are logged in consecutive memory
locations until the end of the area has been reached, at which time the DL restarts at
the beginning of the Data Log Area to store subsequent event data. This “wrap around”
causes the data stored at the beginning of memory to be overwritten. This overwrite can
be inhibited by utilizing the Timed Data Protection mechanism provided by the DL.
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8.6.4
Directory Frames
A Directory Frame is stored when any of the following events occur:
•
System Reset: when the CTC system is reset or powered up.
•
Start of Each Hour: when the system clock advances to a new hour.
•
Clock Setting: when the operator modifies the system date or time through the
DataLogger’s password protected clock-setting utility.
•
End of Memory: when the DL reaches the end of the Data Log Area (i.e. end of
actual memory), and Timed Data Protection has expired for the oldest directory
data.
•
Erasure of Current Directory: when an erase command is issued for the currently
open directory.
In all five instances, the creation of a new Directory Frame can be inhibited by the
enforcement of Timed Data Protection wherein logs are protected from being
overwritten until the data is older than the user-specified duration. A new Directory
Frame will not be created until after timed protection expires.
A Directory Frame contains the following information:
•
Date and time of creation
•
Primary and secondary status indicators
•
A log count (number of events)
•
A pointer (i.e. address) to the first logged event associated with this directory
•
A moving pointer to the last event associated with this directory
8.6.5
Log Frames
A Log Frame is composed of event and descriptive data. An event’s data is generated
by different CTC software modules and passed to the DL for storage. The descriptive
portion of a Log Frame has a fixed length used to identify the type and source of the
event data.
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8.6.6
Logging Capacity
The logging capacity of DataLogger can be roughly expressed in terms of the maximum
number of events that can be stored. To do so, the following example assumes that
DataLogger is configured to log only changes to User Message parameters, and that a
single parameter changes state in each event. In this case, each stored event (i.e. Log
Frame) will require 19 bytes of memory: 17 bytes of overhead plus 2 bytes of data for
the parameter that changed state. CSEX3 have 258070 bytes of RAM for data logging.
Therefore, in this example, 13582 events (258070/19) will be logged before memory
becomes full. Be aware that this is approximate, since periodically (typically every hour)
DataLogger also automatically stores a snapshot of all parameters.
To estimate capacity in total logging time, estimate how many events will typically occur
each hour. Using the previous example and assuming an average of 4 events per
minute (i.e. 240 per hour), DataLogger memory will become full in about 56.6 hours
(13582/240) – approximately 2.3 days. Adjust this calculation based upon the expected
frequency of events.
In a given application, it may be determined that typically multiple parameters change at
once, and are therefore logged as a single event. In this case, a typical event log will
contain more than just a single parameter change and will be larger than the 19 bytes
shown in the example above. Calculate the size (in total number of bytes) of a typical
Log Frame as follows:
•
17 bytes of overhead; plus
•
2 bytes multiplied by the average number of parameters that change state in each
event
For example, if a typical event contains three parameter state changes, the size of a
typical Log Frame will be 23 bytes (17+2*3) resulting in a storage capacity of 11220
events (258070/23).
8.6.7
Data Protection
The DL stores Log Frames in contiguous memory locations. When the DL runs out of
room in the Data Log Area, it seeks to overwrite the logs that belong to the oldest
directory. An optional Timed Data Protection mechanism exists to allow users to prevent
logs from being overwritten. The user specifies the minimum length a Directory Frame is
to be saved after is it created. The specification is made once and applies uniformly to
all directories.
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8.6.8
Log Area Reclamation
The DL reclaims an entire directory's Data Log Area at a time. Given the same log
sources and types, the size of a directory's memory area varies with the number of logs
taken. Areas occupied by periods of heavy traffic will be larger than those with little or
no traffic. When the DL reclaims a Data Log Area, the status indicator in the Directory
Frame that describes the area is set to expired. Data in an expired area cannot be
meaningfully interpreted.
Provisions, accessible through the DataLogger’s diagnostics, exist to allow a user to
erase and recover memory blocks. When an area is erased, the status in its Directory
Frame is set to erased. The erasure of an area is simply a change in status and is not
destructive to the previously logged data in that area. However, an erased area loses its
timed protection. When the DL runs out of room and encounters an erased area, it will
set the area to expired and proceed to overwrite it with new logs.
The status of unexpired and unerased directories is normally set to valid. An erased
area can be recovered only as long as the DL has not run out of memory and set the
directory’s status to expired.
8.6.9
System Overloading
A CenTraCode system primarily serves as a code system emulator. Its flexibility has
allowed it to fill a much wider range of applications. However, it is possible to overload a
CTC system by setting up the DL to record a wide range of frequently-changing
parameters in a system configured with fast communication protocols for code system
emulation. Application designers should limit loading to essential requirements and set
up the DL to record only needed parameters.
Another example of how a system can be overloaded is to configure the DL to log code
line messages (i.e. serial controls and indications) in Direct mode. Direct mode
introduces an overhead that handicaps code line systems that operate with short
inter-scan delays (the time interval between messages received by the CTC system).
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8.7
8.7.1
TRACKER ANALYZER
General Information
The Tracker™ Remote Diagnostic Analyzer, an Alstom software innovation, is a costeffective and time-saving solution for monitoring and troubleshooting faults in the VPI®
vital processor interlocking control system, CenTraCode® communication system (as
implemented in CSEX boards) and other field control systems (hereafter referred to as
devices). Complete Tracker documentation is available in Alstom Publication P2307.
Although not essential for using the Tracker analyzer, the user should have some
knowledge of the terminology used in microprocessor-based control equipment to fully
understand and interpret error codes and diagnostic messages.
8.7.2
System Overview
Figure 8-24 shows a typical Tracker analyzer installation. The equipment supplied may
vary from that pictured depending on specific system requirements. For information on
additional or specialized equipment, contact an Alstom Sales Representative.
FIELD DEVICES
VPI
SYSTEM 1
VPI
SYSTEM 2
CenTraCode II
CODE SYSTEM
OTHERS
PRINTER
TELEPHONE
MODEM
PERSONAL
COMPUTER
TRACKER
DISK
Figure 8-24. Typical System Using Tracker Software
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In the convenience of an office setting, the Tracker Remote Diagnostic Analyzer
software provides full-time simultaneous monitoring of multiple field locations. Using
customized “Instruction Files” Tracker can be configured to sound an alarm when a
malfunction occurs. When a fault is detected, Tracker can automatically diagnose the
problem to indicate the fault or field condition, and display the information to the
operator. This helps ensure that proper spares are taken to the site the first time,
minimizing system down time.
Tracker permits historical logging of data so that the events leading up to a failure can
be later analyzed for possible trends. By knowing the conditions leading to a device
failure, preventive action may be possible to protect against future problems.
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8.8
BOARD REPLACEMENT
Some board types have configuration data that must remain intact if the board is
replaced with a spare. In all cases check the front cover label for proper board number
and signature. If the board being replaced contains jumpers or switches, make sure
they are configured the exact same way on the spare board.
The CPU, CPU/PD, VSC, CSE, and CSEX boards contain system software and
application logic that must be reinstalled on replacement boards and verified by
procedures outlined later in this Section. Doing this is essential to restoring proper
operation to the VPI system.
Besides software, other items that require removal from failed circuit boards and
reinstallation on replacement boards are:
•
Output Board Signature PROMs (39780-003)
•
Input Board and I/O Bus Interface Board Signature headers (59473-871)
•
Time selection jumpers for the Vital Timer Board
CAUTION
Replacement of all system and application EPROMs, Signature PROMs,
Signature headers, and other ICs should be performed at a static-safe work
station, using proper IC removal/insertion tools to eliminate the introduction
of static discharge into the device, or bending of device leads.
8.8.1
Signature PROM
Each Vital Output board has a 16-pin plug-in PROM. At time of design of the
application, the signature PROM is selected to key the board to a particular module slot.
Because of this, whenever a faulty or suspect board is replaced, the same PROM must
be installed on the spare board. Both the signature PROM and the signature number for
each slot housing a Vital output board are indicated on the module front cover label.
This number is shown in the form of "SIG=#", where # is a number 1 to 40. The # and
the Signature number are identical. See Appendix F for a complete list.
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Maintenance
8.8.2
Signature Headers
The I/O Bus Interface board (59473-827) and the Vital Input Boards (59473-867)
contain a 36-pin IC Signature Header. There are 16 varieties of this header (Signatures
A through P). Each I/O Bus Interface and Vital Input board requires a different header to
be established before field installation. The headers are a Vital part of the VPI system
and are used to associate either board type with a specific module slot. Because these
headers are keyed to a module slot, like boards may not be substituted without first
installing the correct header. See Appendix F for a complete list.
8.8.3
Field-Settable Vital Timer
A part of every Field-Settable Vital Timer board is a sealed time matrix where one to
eight time settings can be programmed. When board replacement is necessary, ensure
that the time settings on the spare board are identical to those of the board being
replaced. The matrix must be then sealed and the label on the front of edge of the timer
board must be updated with information regarding the timing functions used in that
system. Only after these steps have been taken should the spare timer board be
installed in the module.
Verification of the programmed timing functions is performed much the same as with
electromechanical (relay) timers and is described later in the next subsection.
8.8.4
Board Replacement Procedures
Once a faulty board is identified using the procedures described earlier, follow these
steps to replace it and to verify proper operation of the new board. While these tests
apply to many types of VPI repairs, they must not be considered as exhaustive
procedures applicable to all possible situations. Use them as guidelines to develop tests
that are suited to the requirements of your specific installation.
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Maintenance
8.8.5
Vital Boards
CAUTION
When replacing boards in a Vital, electronic system, the user should be
guided by the instructions and requirements of the operating agency with
regard to any testing that must be performed before placing the altered
equipment back in service.
8.8.5.1
CPU Board, P/N 59473-742-00
Table 8–16. CPU Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed CPU board.
3
Remove VPI system and application EPROM from the failed CPU board. If
replacement CPU board has software installed that has been previously
subjected to full system verification, proceed to Step 5.
4
Install software on the replacement CPU board.
5
Verify that jumper and switch settings on the replacement CPU board are the
same as the failed CPU board.
6
Install replacement CPU board and observe the processor messages for
errors.
7
If there are no errors, verification of replacement board functionality is
complete.
8
It is necessary to record the system configuration data (using Table 2–1 /
Table 2–2 in Section 2), especially when using spare software sets.
9
Use a terminal connected to the CPU board and record system configuration
data as described in Section 2 (Installation and Setup).
CAUTION
Verify that the configuration data matches exactly that recorded
when the system was last commissioned for service. If the data
does not match, do not place system in service until the reason for
the discrepancy is found and accepted. This may require running
the Application Data Verifier (ADV) program and comparing current
system documentation to that archived when the system was
commissioned for service.
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Maintenance
Table 8–16. CPU Board Replacement
Step
Procedure
10
Once system and application EPROMs have been verified, return the VPI
system to service. Observe system operation for at least five minutes to
ensure that all errors have been corrected.
11
Record maintenance performed in the Service Log.
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8.8.5.2
PD Board P/N 59473-737-00
Table 8–17. PD Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed PD board.
3
Install replacement PD board and observe the Handheld Terminal for errors.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.5.3
CPU/PD Board P/N 31166-029-00
Table 8–18. CPU/PD Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Remove VPI system and application EPROM from the failed board. If
replacement CPU/PD board has software installed that has been previously
subjected to full system verification, proceed to step 5.
4
Install software on the replacement board.
5
Verify that jumper and switch settings on the replacement board are the same
as the failed board.
6
Install replacement board and observe the processor messages for errors.
7
If there are no errors, verification of board functionality is complete.
8
It is necessary to record the system configuration data (using Table 2–1 /
Table 2–2 in Section 2), especially when using spare software sets.
9
Use a terminal connected to CPU/PD board and record system configuration
data as described in Section 2 (Installation and Setup).
CAUTION
Verify that the configuration data matches exactly that recorded
when the system was last commissioned for service. If the data
does not match, do not place system in service until the reason for
the discrepancy is found and accepted. This may require running
the application data verifier (ADV) and comparing current system
documentation to that archived when the system was
commissioned for service.
10
Once system and application EPROMs have been verified, return VPI system
to service. Observe system operation for at least 5 minutes to ensure that all
errors have been corrected.
11
Record maintenance performed in the Service Log.
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Maintenance
8.8.5.4
Vital Relay Driver Board, P/N 59473-740-00
Table 8–19. Vital Relay Driver Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Ensure rotary switch SW1 is set to position “F”.
5
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.5.5
Vital Serial Controller Board, P/N 59473-939-00
Table 8–20. Vital Serial Controller Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Remove EPROM containing system and application oriented software and
install it on the replacement board. Ensure that all switch and jumper settings
on the replacement board match the settings of the failed board.
4
Install replacement board and observe Handheld Terminal for errors.
5
If no errors, verify board functionality. Observe system operation at both ends
of the affected serial link. Do this by viewing in system memory, specific Vital
serial link functions using the ‘Q’ (Query) diagnostic command. Exercise the
system logic such that you can observe several serial link functions, first
getting a permissive and then subsequent restrictive state.
6
Using Handheld Terminal connected to CPU/PD board, record system
configuration information on Table 2–1 / Table 2–2 as shown in Section 2
(Installation and Setup).
CAUTION
Verify that the configuration data matches exactly that recorded
when the system was last commissioned for service. If the data
does not match, do not place system in service until the reason for
the discrepancy is found and accepted. This may require running
the application data verifier (ADV) and comparing current system
documentation to that archived when the system was
commissioned for service.
7
Date and initial configuration data log.
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Maintenance
8.8.5.6
Code Rate Generator Board, P/N 31166-261-00
Table 8–21. Code Rate Generator Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Apply system power and observe Handheld Terminal for further errors.
5
If no errors, verify board functionality. Exercise the system logic such that
each output is energized and then de-energized. Do this for all outputs on the
board. Observe the system for proper operation by ensuring that the wayside
equipment connected to each output is operating properly and matches the
associated output indicator.
6
Return VPI system to service and record maintenance performed in the
Service Log.
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8.8.5.7
I/O Bus Interface Board, P/N 59473-827-00
Table 8–22. I/O Bus Interface Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Remove Signature header (59473-871) and install it on the replacement
board.
4
Install replacement board and observe Handheld Terminal for errors.
5
If no errors, verify board functionality. Energize and subsequently de-energize
each input and verify the system operates as intended.
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8.8.5.8
Vital Input Board, P/N 59473-867-00
Table 8–23. Vital Input Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Remove Signature header (59473-871) and install it on the replacement
circuit board.
4
Install replacement board and observe Handheld Terminal for errors.
5
If no errors, verify board functionality. Energize and subsequently de-energize
each input and verify system operates as intended.
6
Return VPI system to service and record maintenance performed in the
Service Log.
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8.8.5.9
Vital Output Boards,
P/N 59473-739, -747, -749, -937, -977-00
Table 8–24. Vital Output Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Remove Signature PROM (39780-003) and install it on the replacement
board.
4
Install replacement board.
5
Apply system power and observe Handheld Terminal for further errors.
6
If no errors, verify board functionality. Exercise the system logic such that
each output is energized and then de-energized. Do this for all outputs on the
board. Observe the system for proper operation by ensuring that the wayside
equipment connected to each output is operating properly and matches the
associated output indicator.
7
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.5.10
Field-Settable Vital Timer Board, P/N 59473-894-00
Table 8–25. Field-Settable Vital Timer Board Replacement
Step
Procedure
1
Remove system power.
2
Configure time settings on spare timer board as required (see timer setting
example in Section 4).
3
Remove the failed board and verify time settings match those of the spare
board.
4
Install replacement board.
5
Using separate time reference (stop watch, etc.), verify that each time function
executes the time selected. Date and initial label on the timer board.
6
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6
8.8.6.1
Non-Vital Boards
Code System Emulator – CSE Board, P/N 59473-741-00
Table 8–26. Code System Emulator Board Replacement
Step
Procedure
1
Remove system power and communications power.
2
Remove the failed board.
3
Remove EPROM containing system and application logic where applicable.
4
Install software on replacement board.
5
Make sure jumper settings are correct.
6
Install replacement board.
7
Verify board functionality by exercising local and remote control operations,
non-vital logic operation and/or non-vital field indications and communication
(all where applicable).
8
Return VPI system to service and record maintenance performed in the
Service Log.
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8.8.6.2
Code System Emulator Extended – CSEX1 Board, P/N 59473-938-00
Table 8–27. CSEE 1 Board Replacement
Step
Procedure
1
Remove system power and communications power.
2
Remove the failed board.
3
Remove EPROM containing system and application logic where applicable.
4
Install software on replacement board.
5
Make sure jumper settings and switch positions are correct.
6
Install replacement board.
7
Verify board functionality by exercising local and remote control operations,
non-vital logic operation and/or non-vital field indications and communication
(all where applicable).
8
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.3
Code System Emulator Extended 3 – CSEX3 Board, P/N 31166-175-00
Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
Procedure
1
Remove system power and communications power.
2
Remove the failed board from the NVIP module using the ejectors located on
the printed circuit board edges.
Note the slot number on the NVIP module from which the board is removed
and place the board on a flat, anti-static surface.
3
In the maintenance log,
• record the part number and serial number of the suspected faulty board.
• record the part number and serial number of the replacement board.
4
Verify that the part number and jumper positions of the replacement board
match the part number and jumper positions of the failed board.
5
On the original board, change JP3 jumper positions 7 to 8 to 6 to 8 for the
board "Battery in Storage" to extend battery shelf life.
Application Program
FLASH Chips
ODD
EVEN
JP3
2
8
1
7
JP3
2
1
8
7
JP3-7 TO 8
BATTERY IN USE
JP3-6 TO 8
BATTERY IN
STORAGE
CAUTION
Using a device other than the recommended extraction tool may
cause damage to the PCB or its components.
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Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
Procedure
6
Extraction
Tip
Extraction
Slot
Extraction
Slot
Plastic Leaded
Chip Carrier
(PLCC)
Application Program
FLASH Chips
Socket
ODD
EVEN
JP3
2
8
1
7
JP3
2
1
8
7
JP3-7 TO 8
BATTERY IN USE
JP3-6 TO 8
BATTERY IN
STORAGE
On the original board, identify the “ODD” and “EVEN” EEPROM Chips located
on the PCB. EEPROM Chips may be labeled “ODD” and “EVEN” to match the
EEPROM filename extension.
WARNING
The EEPROM chips are not interchangeable. Prior to removal,
record the location and orientation sockets. The “ODD” EEPROM
chip is located in the socket marked “ODD.” The “EVEN” EEPROM
chip is located in the socket marked “EVEN.” Ensure that each
EEPROM chip is correctly inserted in its corresponding socket on
the replacement PCB.
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Maintenance
Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
Procedure
7
Use an AMP PLCC Extraction Tool (P/N 821980-1) to remove the “ODD” and
“EVEN” EEPROM Chips.
Use the following procedure:
• Insert the extraction tips of the Extraction Tool into the extraction slots of
the socket until the tool bottoms on the socket (see Figure above).
• Slowly squeeze the tool handles while maintaining a slight downward
force toward the socket until the EEPROM backs out of the socket. Do
not pull upward to loosen the EEPROM.
• Lift the Extraction Tool only after the EEPROM is fully disengaged from
its socket.
• Remove the EEPROM and the Extraction Tool.
8
Install the “ODD” and “EVEN” EEPROM Chips removed in Step 7 onto the
replacement CSEX3 Board.
• Ensure the notch on the EEPROM Chip aligns with the notch in the
socket and the EEPROM Chip leads align with the socket leads.
• Press the EEPROM Chip into the socket firmly, with evenly distributed
pressure. Refer to the exploded view in Figure above.
9
Verify that the jumper configurations of JP1, JP2, and JP3 and the switch
settings are identical to the jumper configurations of JP1, JP2, and JP3 and the
switch settings on the original board. If the configurations are different from the
original board, adjust the jumpers to match the original board. Refer to Table
8–29 and Table 8–30.
10
On the replacement board, change JP3 jumper positions 6 to 8 (refer to Step 5)
to JP3 jumper positions 7 to 8 to enable the board battery to power the batterybacked RAM for the DataLogger to function.
11
Insert the replacement board into the slot that the original board was placed on
the NVIP Module.
12
Reapply the logic power by turning the LOAD OFF/ON toggle switch located on
the 5-Volt Logic Power Supply to the “ON” position.
Note: The display on the CSEX3 Board will change from “8.8.” to “00”
without a reset activated (the display will read “1 b” when a reset
button is pressed).
If it remains at 8.8, it is likely that the ODD and EVEN EEPROM
chips were swapped during Step 8 of this procedure; refer to
Step 13, Procedure 2-d, to check for swapped EEPROM chips.
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Maintenance
Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
13
Procedure
Verify board functionality by observing that the following board-edge LEDs are
illuminated (refer to Figure 7-5, for location of the CSEX3 LEDs):
• DS1 (PCB label name: ISO5V)
• DS2 (PCB label name: PWR)
• DS3 (PCB label name: RUN)
• DS4 (PCB label name: APPL EXEC)
If all of these LED conditions are observed to be correct, proceed to Step 14.
However, if these LEDs conditions are not observed, use the following
procedure to resolve the problem:
13a
Procedure 1: If the DS2 (PCB label name: PWR) LED is not illuminated:
a.
Verify the presence of between 4.8 to 5.1 Volts DC, at test jacks TP3
(+5V) and TP4 (COM). The preferred voltage is 5.0 Volts DC.
b.
Proceed to Procedure 2.
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Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
Procedure
13b
Procedure 2. If the DS3 (RUN) and the DS4 (APPL EXEC) LEDs are not illuminated or the
display remains at “8.8”:
a.
Remove the 5-Volt Logic Power from the NVIP module before
removing the CSEX3 board.
b.
Remove the CSEX3 Board.
c.
Verify that JP1, JP2, and JP3 jumpers and switch settings are
configured correctly.
d.
Verify that the EEPROM Chips have been installed correctly. If the
DS3 (RUN) and the DS4 (APPL EXEC) LEDs are not illuminated or the
display shows “8.8.”, the “ODD” and “EVEN” EEPROM Chips may
have been interchanged or misaligned during installation onto the
replacement CSEX3 Board.
• If the ODD and EVEN EEPROMs were installed with the notch
incorrectly oriented in the socket, they may be damaged if
allowed to remain in place. In this case, remove the EEPROMS
and reinstall them; ensure the notch on each EEPROM aligns
with the notch in the socket and the EEPROM leads align with
the socket leads.
• If the EEPROMs were swapped during installation (i.e. the ODD
chip in the EVEN socket, etc.), they will not be damaged, but the
CSEX3 will not operate; in this case, remove the EEPROMS
and be certain chips and sockets are exactly matched
ODD/ODD and EVEN/EVEN when reinstalled.
• Always ensure the EEPROMS are firmly placed in their sockets.
e.
Reinstall the CSEX3 Board.
f.
Reapply the 5-Volt Logic Power by turning the LOAD OFF/ON toggle
switch on the 5-Volt Logic Power Supply to the “ON” position.
If these steps do not resolve the problem, one or both of the EEPROM
chips may be defective and need to be replaced.
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Maintenance
Table 8–28. CSEX3 Board Replacement Procedure (Cont.)
Step
Procedure
13c
Procedure 3. If the DS2 (PWR) LED is illuminated but the DS1 (ISO5V) is not:
a.
Remove the 5-Volt Logic Power from the NVIP module before
removing the CSEX3 board.
b.
Observing the procedures described in Steps 2 to 9, remove the failed
CSEX3 Board, change its jumpers, and relocate the EEPROMs onto a
replacement CSEX3 Board.
c.
Insert the replacement board into the slot that the original board was
placed on the NVIP Module.
d.
Reapply the logic power by turning the LOAD OFF/ON toggle switches
on the 5-Volt Logic Power Supply to the “ON” position.
14
Confirm that the NVIP PROBLEM Light on the Alarm Panel is dark.
15
Connect the Laptop PC to the CSEX3 Board (see Section 3.4).
16
Set and Initialize the CSEX3 Board’s Real Time Clock (RTC) using the Clock
Screen, accessible via the Selection Path Main Menu | Diagnostic | Clock.
17
Reset the DataLogger using the Reset Screen, accessible via the Selection
Path Main Menu | Logger | Util | Reset.
18
Set up and run NVIP processor, non-vital logic operations, and non-vital field
indications (as applicable).
19
Return the system to service and record the maintenance performed in the
Service Log.
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Maintenance
Table 8–29. CSEX3 Board Configuration Jumpers
Jumpers
Function Options
JP1
Select either MAC Port Power connected or disconnected:
• JP1-1 to JP1-2 – MAC Port Power connected (for HHT use only)
• JP1-3 to JP1-4 – MAC Port Power disconnected
Select Auxiliary Board A1/ALE signal line:
• JP1-5 to JP1-6 – None selected
• JP1-6 to JP1-8 – ALE signal line selected
• JP1-7 to JP1-8 – A1 signal line selected
JP2
Select either Watchdog normal operation or disabled:
• JP2-1 to JP2-3 – Disable Watchdog reset (for emulator use only)
• JP2-3 to JP2-5 – Normal operation
Select Auxiliary Board Clock rate:
• JP2-2 to JP2-4 – 14.7456 MHz clock selected
• JP2-4 to JP2-6 – 20 MHz clock selected
• JP2-6 to JP2-8 – No clock selected
JP3
Select Flash Write disabled or enabled:
• JP3-1 to JP3-3 – Flash Write Always Disabled
• JP3-2 to JP3-4 – Clip lead enabled (to enable, connect TP5 to
common)
• JP3-3 to JP3-4 – Flash Write enabled
Select either Battery connected or disconnected:
• JP3-6 to JP3-8 – Battery disconnected
• JP3-7 to JP3-8 – Battery connected (do not use this position if no
battery is installed)
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Maintenance
Table 8–30. CSEX3 Board Configuration Switches
Switches
Function (and Options where available)
SW1
Select either the Front or Back connector for MAC Port access:
• F – Front DB9 Connector access is selected when switch is set to
this position
• B – P3 Connector (back) access is selected when switch is set to
this position
SW2
SW3
SW5
SW6
Select RS-232/RS-422 mode or DC mode for Channel 2:
• ON – RS-232/422/483 mode is selected when all switch actuators
are set towards the front of the board
• DC→ – DC code line mode is selected when all switch actuators
are set towards the back of the board, indicated on the board by
DC→
SW4
Select Port-2 Communication mode:
• ON – RS-232 mode is selected when All Switches are placed in
the ON position
• Not ON – RS-422/485 mode is selected when All Switches are not
placed in the ON position
SW7
Select Port-1 Communication mode:
• ON – RS-232 mode is selected when All Switches are placed in
the ON position
• Not ON – RS-422/485 mode is selected when All Switches are not
placed in the ON position
SW8
Pushbutton causes the CSEX3 Board to Reset
SW9
Application Switch (not used in NVIP)
SW10
Application Switch (not used in NVIP)
SW11
Enter/Select Switch
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Maintenance
8.8.6.4
Non-Vital Input Board, P/N 59473-757-00
Table 8–31. Non-Vital Input Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.5
Non-Vital Input Differential Board, P/N 31166-106-00
Table 8–32. Non-Vital Input Differential Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.6
Non-Vital Input Differential Switch Board, P/N 31166-276-00
Table 8–33. Non-Vital Input Differential Switch Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Set input switch as required.
5
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.7
Non-Vital Output Boards, P/N 59473-785, -936-00 and 31166-123-00
Table 8–34. Non-Vital Output Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.8
Non-Vital Output Relay Board, P/N 31166-238-00
Table 8–35. Non-Vital Output Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.9
Non-Vital TWC Main Board, P/N 59473-996-00
Table 8–36. Non-Vital TWC Main Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.10
Non-Vital TWC Auxiliary Board, P/N 59473-995-00
Table 8–37. Non-Vital TWC Auxiliary Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
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Maintenance
8.8.6.11
Non-Vital TWC Attenuator Board, P/N 31166-021-00
Table 8–38. Non-Vital TWC Attenuator Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
P2086B, Volume 1, Rev. D, Nov/13
8-123
Alstom Signaling Inc.
Maintenance
8.8.6.12
Non-Vital TWC Modem Board, P/N 31166-099-00
Table 8–39. Non-Vital TWC Modem Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
P2086B, Volume 1, Rev. D, Nov/13
8-124
Alstom Signaling Inc.
Maintenance
8.8.6.13
Non-Vital TWC Multiplexer Board, P/N 31166-100-00
Table 8–40. Non-Vital TWC Multiplexer Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
P2086B, Volume 1, Rev. D, Nov/13
8-125
Alstom Signaling Inc.
Maintenance
8.8.6.14
Non-Vital TWC FSK Board, P/N 31166-119-00
Table 8–41. Non-Vital TWC FSK Board Replacement
Step
Procedure
1
Remove system power.
2
Remove the failed board.
3
Install replacement board.
4
Return VPI system to service and record maintenance performed in the
Service Log.
P2086B, Volume 1, Rev. D, Nov/13
8-126
Alstom Signaling Inc.
Maintenance
8.9
PROCEDURE TO VERIFY VPI BOARD FUNCTIONALITY
The following section covers verification testing of Vital input and output boards. The
procedures indicate that the ports should be verified by testing the function controlled by
the input or output. The technician must be familiar with the operation of the related
portion of the system. The technician identifies a specific input or output device, then it
is “exercised” to verify that it is properly interfaced with the VPI system by noting that
the expected response occurs. Specific examples of each possible verification scenario
are not provided, as the number of possible combinations is too large to be useful.
8.9.1
I/O Interface Board
Objective: To test that the I/OB Board communicates to I/O boards
Table 8–42. I/O Interface Board Functionality Verification
Step
Procedure
1
Using the functionality test procedure for a Vital Input Board, verify one port of
each Input Board controlled by the I/OB Board.
2
Using the functionality test procedure for a Vital Output Board, verify one port
of each Output Board controlled by the I/OB Board.
8.9.2
Vital Input Boards
Objective: To test each input port
Table 8–43. Vital Input Board Functionality Verification
Step
Procedure
1
Using VPI Module Label or VPI Output Report LVC, note the functions
assigned to each input. For example: VRDFRNT-DI; input from VRD relay,
NWP-DI; input from switch machine.
2
Using Book of Plans, note the required input condition for each of the listed
functions.
3
Enable then disable each input, noting the functional response to the input
status change.
P2086B, Volume 1, Rev. D, Nov/13
8-127
Alstom Signaling Inc.
Maintenance
8.9.3
Vital Output Boards
Objective: To test each output port
Table 8–44. Vital Output Board Functionality Verification
Step
Procedure
1
Using VPI Module Label or VPI Output Report LVC, note the functions
assigned to each output. For example: NW-DBO; output to switch machine,
GO-SBO; output to AF module Go circuit.
2
Using Book of Plans, note the apparatus connected to each of the listed
functions.
3
By initiating the appropriate request, enable then disable each output, noting
the response of the apparatus to the output status change.
8.9.4
Field-Settable Vital Timer Board
Objective: To test each timer
Table 8–45. Field-Settable Vital Timer Board Functionality Verification
Step
Procedure
1
Using VPI Module Label or VPI Output Report LVC, note the route approach
locking function that is assigned to each timer.
2
For each timer:
2a
Select the route.
2b
Cancel selected route.
2c
Start stopwatch when LED for timer begins to blink; stop timing when
light ceases to blink.
2d
Verify time matches jumper setting.
2e
Write time setting on timer board.
P2086B, Volume 1, Rev. D, Nov/13
8-128
Alstom Signaling Inc.
Board Reference Data
SECTION 9 – BOARD REFERENCE DATA
9.1
GENERAL
The following figures show the orientation of LEDs, switches, jumpers and plug-in
EPROMs for all applicable boards in the VPI system.
9.2
LED LOCATION AND DEFINITION
Figure 9-1 through Figure 9-19 show the orientation and definition of the board edge
LEDs.
9.2.1
CPU Board LED Indications, P/N 59473-742
CENTRAL
PROCESSOR
UNIT
(CPU)
INDICATIONS LIGHT WHEN:
FLASHING, BUT MOSTLY OFF 1
MAIN DATA BUS IS ACCESSED BY OTHER THAN CPU
OFF 2
USED IN A DUAL CPU SYSTEM
ON 3
INTERRRUPT IS REQUESTED
FLASHING, BUT MOSTLY OFF 4
INTERRUPT IS BEING PROCESSED
OFF 5
HARDWARE RESET, CAUSED BY EPROM
OFF 6
IN DUAL CPU SYSTEM
OFF 7
ROCKER SWITCH IS IN PROGRAM MODE
ALL POSSIBLE COMBINATIONS 8
FLASHING 9
EXTENDED MEMORY NOT PRESENT IN IC8 & IC20
BEGINNING OF EACH 1 SECOND CYCLE
Figure 9-1. CPU Board LED Indications, P/N 59473-742
P2086B, Volume 1, Rev. D, Nov/13
9–1
Alstom Signaling Inc.
Board Reference Data
9.2.2
PD Board LED Indications, P/N 59473-737
POLYNOMIAL DIVIDER
(PD)
INDICATION LIGHTS WHEN:
FLASHING
1
INPUT DATA IS VERIFIED
FLASHING
2
INPUT DATA IS VERIFIED
FLASHING
3
INPUT DATA IS VERIFIED
FLASHING
4
INPUT DATA IS VERIFIED
FLASHING
5
LOWER 16 BITS OF SHIFT REGISTER ARE ENABLED
FLASHING
6
UPPER 16 BITS OF SHIFT REGISTER ARE ENABLED
FLASHING
7
CPU READS LOWER SHIFT REGISTER
FLASHING
8
CPU READS UPPER SHIFT REGISTER
FLASHING
9
PD BOARD IS ADDRESSED BY CPU BOARD
FLASHING
10
DIFFERENT DATA VERIFICATION CONFIGURATION IS SELECTED
Figure 9-2. PD Board LED Indications, P/N 59473-737
P2086B, Volume 1, Rev. D, Nov/13
9–2
Alstom Signaling Inc.
Board Reference Data
9.2.3
CPU/PD Board LED Indications, P/N 31166-029
Figure 9-3. CPU/PD Board LED Indications, P/N 31166-029
* This indicator, if present, serves no purpose. The intended use has never been
implemented.
P2086B, Volume 1, Rev. D, Nov/13
9–3
Alstom Signaling Inc.
Board Reference Data
9.2.4
VRD Board LED Indications, P/N 59473-740
VITAL RELAY
DRIVER
(VRD)
Mostly On
Flashing
Flashing Mostly On
1
2
3
LIGHTS WHEN VRD BOARD IS OUTPUTTING
DRIVE TO RELAY
(DOES NOT VERIFY RELAY IS ENERGIZED)
LIGHTS WHEN MAIN CPU FINISHES FILLING THE
VRD'S DUAL-PORTED RAM WITH CHECKWORDS
LIGHTS WHEN VRD RELEASES DUAL-PORTED
RAM TO GET NEW MESSAGE FROM CPU
Figure 9-4. VRD Board LED Indications, P/N 59473-740
P2086B, Volume 1, Rev. D, Nov/13
9–4
Alstom Signaling Inc.
Board Reference Data
9.2.5
VSC Board LED Indications, P/N 59473-939
VITAL SYSTEM
CONTROLLER
(VSC)
INDICATION LIGHTS WHEN:
Flashing Once Per Second
Off
Flashing Once Per Second
Off (Spare)
Flashing Once Per Second
Flashing Once Per Second
Flashing Once Per Second
Flashing Once Per Second
1
VSC TRANSMITS
2
5VDC POWER LOW
3
CPU CYCLES (ONCE EACH SECOND)
4
SPARE
5
TRANSMIT DATA RECEIVED FROM CPU
6
CHAN. 1/CHAN. 2 TRANSMIT MESSAGES ARE FORMED
7
MESSAGE RECEIVED FROM VSC
Flashing Once Per Second
8
DATA IS BEING SENT TO CPU BOARD
Flashing Once Per Second
9
VSC PROCESSING RECEIVED MESSAGE DATA
On During Power Up Of Application Data
10
Off 11
POWER UP APPLICATION DATA FROM CPU BOARD
RESET IS ACTIVATED
Figure 9-5. VSC Board LED Indications, P/N 59473-939
P2086B, Volume 1, Rev. D, Nov/13
9–5
Alstom Signaling Inc.
Board Reference Data
9.2.6
I/OB Board LED Indications, P/N 59473-827
I/O BUS INTERFACE
(I/O B)
FLASHING
1
FLASHING
2
LIGHTS WHEN DATA FROM INPUTS OR OUTPUTS
IS LOADED INTO SHIFT REGISTERS
LIGHTS WHEN DATA IN SHIFT REGISTERS
IS READ BY MAIN CPU
Figure 9-6. I/OB Board LED Indications, P/N 59473-827
P2086B, Volume 1, Rev. D, Nov/13
9–6
Alstom Signaling Inc.
Board Reference Data
9.2.7
CRG Board LED Indications, P/N 31166-261
CODE RATE GENERATOR
(CRG)
Port DisplayIlluminates for
selected output port
number, 1 through 8
Code Rate Displayscolls 3-digit code rate
in pulses per minute
Up/Down Rocker Switchfor port display select
Reset Switch
Figure 9-7. CRG Board LED Indications, P/N 31166-261
P2086B, Volume 1, Rev. D, Nov/13
9–7
Alstom Signaling Inc.
Board Reference Data
9.2.8
DI Board LED Indications, P/N 59473-738, 59473-867
DIRECT INPUT
(DI)
OFF, ON
1
Input #1
OFF, ON
2
Input #2
OFF, ON
3
Input #3
OFF, ON
4
Input #4
OFF, ON
5
Input #5
OFF, ON
6
Input #6
OFF, ON
7
Input #7
OFF, ON
8
Input #8
INDICATIONS 1-8:
LIGHT WHEN EXTERNAL ENERGY
IS APPLIED TO INPUT
INDICATION 9:
FLASHING, BUT MOSTLY OFF
9
FLASHING, BUT MOSTLY OFF
10
Read (RD)
LIGHTS WHEN DATA IS READ FROM INPUT
BOARD
Write (WR)
INDICATION 10:
LIGHTS WHEN DATA IS WRITTEN TO INPUT
BOARD
OFF, ON
11
Input #9
OFF, ON
12
Input #10
OFF, ON
13
Input #11
OFF, ON
14
Input #12
OFF, ON
15
Input #13
OFF, ON
16
Input #14
OFF, ON
17
Input #15
OFF, ON
18
Input #16
INDICATIONS 11-18:
LIGHT WHEN EXTERNAL ENERGY
IS APPLIED TO INPUT
Figure 9-8. DI Board LED Indications, P/N 59473-738, 59473-867
P2086B, Volume 1, Rev. D, Nov/13
9–8
Alstom Signaling Inc.
Board Reference Data
9.2.9
SBO, DBO, DBO-50V, LDO, ACO Board LED Indications, P/N 59473-739,
59473-747, 59473-977, 59473-749, 59473-937
VITAL OUTPUT
(SBO) (DBO) (LDO) (ACO)
INDICATION 1:
FLASHING, BUT MOSTLY OFF
1
Read (RD)
FLASHING, BUT MOSTLY OFF
2
Write (WR)
OFF, ON, FLASHING
3
Output #1
OFF, ON, FLASHING
4
Output #2
OFF, ON, FLASHING
5
Output #3
OFF, ON, FLASHING
6
Output #4
OFF, ON, FLASHING
7
Output #5
OFF, ON, FLASHING
8
Output #6
OFF, ON, FLASHING
9
Output #7
OFF, ON, FLASHING
10
Output #8
LIGHT WHEN RECHECK DATA IS
READ FROM BOARD
INDICATION 2:
LIGHT WHEN OUTPUT PORTS
ARE UPDATED
INDICATIONS 3-10:
LIGHT WHEN OUTPUT IS COMMANDED
TO BE ON BY CPU
Figure 9-9. SBO, DBO, DBO-50V, LDO, ACO Board LED Indications
P/N 59473-739, 59473-747, 59473-977, 59473-749, 59473-937
P2086B, Volume 1, Rev. D, Nov/13
9–9
Alstom Signaling Inc.
Board Reference Data
9.2.10
FSVT Board LED Indications, P/N 59473-894
FIELD SETTABLE VITAL TIMER
(FSVT)
OFF, ON, FLASHING
8
Timer #8
OFF, ON, FLASHING
7
Timer #7
OFF, ON, FLASHING
6
Timer #6
OFF, ON, FLASHING
5
Timer #5
OFF, ON, FLASHING
4
Timer #4
OFF, ON, FLASHING
3
Timer #3
OFF, ON, FLASHING
2
Timer #2
OFF, ON, FLASHING
1
Timer #1
TIMER INDICATIONS 1-8:
LIGHTS FLASHING WHEN TIMER
RUNNING, LIGHTS STEADY WHEN
TIME HAS COMPLETED BUT NOT
RESET.
Figure 9-10. FSVT Board LED Indications, P/N 59473-894
P2086B, Volume 1, Rev. D, Nov/13
9–10
Alstom Signaling Inc.
Board Reference Data
9.2.11
CSE Board LED Indications, P/N 59473-741
CODE SYSTEM
EMULATOR
(CSE)
CR9
OUT1
CR8
OUT2
CR7
OUT3
CR6
OUT4
CR5
MGNT
CR4
BDSEL
CR3
IOINT
CR2
EMSEL
CR1
HRESET
Figure 9-11. CSE Board LED Indications, P/N 59473-741
P2086B, Volume 1, Rev. D, Nov/13
9–11
Alstom Signaling Inc.
Board Reference Data
9.2.12
CSEX1 Board LED Indications, P/N 59473-938
EXTENDED
CODE SYSTEM
EMULATOR
(CSEX)
OFF, ON
OFF, ON
OFF, ON
19
18
17
Chan. 4 Transmit
OFF, ON
OFF, ON
OFF, ON
OFF
16
15
14
13
Chan. 3 Receive
Chan. 5 Receive
OFF 12
OFF 11
OFF, ON 10
ON
9
Chan. 4 Receive
Chan. 3 Transmit
Chan. 5 Transmit
CPU Has Reset
LOW POWER (On if Less than 4.5V)
Chan. 2 is in Control
Chan. 1 is in Control
Application Program is Running
OFF
ON
ON
ON
8
7
6
5
Chan. 2
Chan. 2
Chan. 2
Chan. 2
Receive Error Condition
Invalid Address
Is Transmitting
Valid Address Received
OFF
OFF
OFF, ON
ON
4
3
2
1
Chan. 1 Receive Error Condition
Chan. 1 Invalid Address
Chan. 1 Is Transmitting
Chan. 1 Valid Address Received
Note: These readouts apply for Datatrain 8.
See protocol emulations manual
P2345E; other protocol manuals
available as part of P2346 family
may show use of these indicators
differently.
Figure 9-12. CSEX1 Board LED Indications, P/N 59473-938
P2086B, Volume 1, Rev. D, Nov/13
9–12
Alstom Signaling Inc.
Board Reference Data
9.2.13
CSEX3 Board LED Indications, P/N 31166-175
CODE SYSTEM
EMULATOR
EXTENDED 3
(CSEX3)
DS1
ISO5V (Isolated +5V Power)
DS2
DS3
DS4
PWR (System +5V Power)
RUN (System Running)
APPL EXEC (Application Running)
DS5
DS6
5TX (Channel 5 Transmit)
5RX (Channel 5 Receive)
DS7
DS8
4TX (Channel 4 Transmit)
4RX (Channel 4 Receive)
DS9
DS10
3TX (Channel 3 Transmit)
3RX (Channel 3 Receive)
DS11
DS12
DS13
DS14
DS15
2NORMAL (Channel 2, Future Use)
2RX ERROR (Channel 2 Receive Error Condition)
2INVAL ADDR (Channel 2 Invalid Address)
2RESPONSE (Channel 2 Is Transmitting)
2ADDR OK (Channel 2 Valid Address Received)
DS16
DS17
DS18
DS19
DS20
1NORMAL (Channel 1, Future Use)
1RX ERROR (Channel 1 Receive Error Condition)
1INVAL ADDR (Channel 1 Invalid Address)
1RESPONSE (Channel 1 Is Transmitting)
1ADDR OK (Channel 1 Valid Address Received)
DS21
7-Segment Displays
DS22
Figure 9-13. CSEX3 Board LED Indications, P/N 31166-175
P2086B, Volume 1, Rev. D, Nov/13
9–13
Alstom Signaling Inc.
Board Reference Data
9.2.14
NVI Board LED Indications, P/N 59473-757
NON-VITAL INPUT
(NVI)
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
40
39
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
32
31
38
37
36
35
34
33
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Input #1
Input #2
Input #3
Input #4
Input #5
Input #6
Input #7
Input #8
Input #9
Input #10
Input #11
Input #12
Input #13
Input #14
Input #15
Input #16
INDICATIONS 25-40:
LIGHT WHEN ENERGY IS APPLIED TO
EXTERNAL INPUT
LIGHTS WHEN ANOTHER NON_VITAL I/O BOARD IS ACCESSED
LIGHTS WHEN ADDRESS ON I/OBUS IS ACCEPTABLE
LIGHTS WHEN INPUT DATA IS LATCHED
LIGHTS WHEN BOARD IS ADDRESSED BY CSEX
LIGHTS WHEN INPUTS 25-32 ARE READ
LIGHTS WHEN INPUTS 17-24 ARE READ
LIGHTS WHEN INPUTS 9-16 ARE READ
LIGHTS WHEN INPUTS 1-8 ARE READ
Input #17
Input #18
Input #19
Input #20
Input #21
Input #22
Input #23
Input #24
Input #25
Input #26
Input #27
Input #28
Input #29
Input #30
Input #31
Input #32
INDICATIONS 1-16:
LIGHT WHEN ENERGY IS APPLIED TO
EXTERNAL INPUT
Figure 9-14. NVI Board LED Indications, P/N 59473-757
P2086B, Volume 1, Rev. D, Nov/13
9–14
Alstom Signaling Inc.
Board Reference Data
9.2.15
NVID and NVIDSW Board LED Indications, P/N 31166-106 and 31166-276
NON-VITAL INPUT
(NVID) (NVIDSW)
Input #1
Input #2
Input #3
Input #4
Input #5
Input #6
Input #7
Input #8
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
1
2
3
4
5
6
7
8
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
9
10
11
12
13
14
15
16
Input #9
Input #10
Input #11
Input #12
Input #13
Input #14
Input #15
Input #16
17
18
19
20
21
22
23
24
LIGHTS WHEN ANOTHER NON-VITAL I/O BOARD IS ACCESSED
LIGHTS WHEN ADDRESS ON I/OBUS IS ACCEPTABLE
LIGHTS WHEN INPUT DATA IS LATCHED
LIGHTS WHEN BOARD IS ADDRESSED BY CSEX
25
26
27
28
29
30
31
32
Input #17
Input #18
Input #19
Input #20
Input #21
Input #22
Input #23
Input #24
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
OFF, ON
33
34
35
36
37
38
39
40
INDICATORS 1-16:
LIGHT WHEN ENERGY IS APPLIED TO
EXTERNAL INPUT
LIGHTS WHEN INPUTS 25-32 ARE READ
LIGHTS WHEN INPUTS 17-24 ARE READ
LIGHTS WHEN INPUTS 9-16 ARE READ
LIGHTS WHEN INPUTS 1-8 ARE READ
Input #25
Input #26
Input #27
Input #28
Input #29
Input #30
Input #31
Input #32
INDICATORS 25-40:
LIGHT WHEN ENERGY IS APPLIED TO
EXTERNAL INPUT
Figure 9-15. NVID and NVIDSW Board LED Indications
P/N 31166-106 and 31166-276
P2086B, Volume 1, Rev. D, Nov/13
9–15
Alstom Signaling Inc.
Board Reference Data
9.2.16
NVO, NVOAC and NVO-SNK Board LED Indications
P/N 59473-785, 59473-936, 31166-123
NON-VITAL
OUTPUT
(NVO) (NVOAC) (NVO-SNK)
OFF, ON
OFF, ON
OFF, ON
OFF, ON
1
2
3
4
Output #1
Output #2
Output #3
Output #4
OFF, ON
OFF, ON
OFF, ON
OFF, ON
5
6
7
8
Output #5
Output #6
Output #7
Output #8
OFF, ON
OFF, ON
OFF, ON
OFF, ON
9
10
11
12
Output #9
Output #10
Output #11
Output #12
OFF, ON
OFF, ON
OFF, ON
OFF, ON
13
14
15
16
Output #13
Output #14
Output #15
Output #16
17
18
19
20
Lights When This Board Is Addressed
Lights When CSEX Commands All Outputs Disabled (Usually On Start-up)
Lights When An Acceptable Address Occurs
Lights When An Acceptable Address Occurs
21
22
23
24
Lights When Output Data Is Latched Into Drivers For Outputs 25-32
Lights When Output Data Is Latched Into Drivers For Outputs 17-24
Lights When Output Data Is Latched Into Drivers For Outputs 9-16
Lights When Output Data Is Latched Into Drivers For Outputs 1-8
OFF, ON
OFF, ON
OFF, ON
OFF, ON
25
26
27
28
Output #17
Output #18
Output #19
Output #20
OFF, ON
OFF, ON
OFF, ON
OFF, ON
29
30
31
32
Output #21
OFF, ON
OFF, ON
OFF, ON
OFF, ON
33
34
35
36
Output #25
Output #26
Output #27
Output #28
OFF, ON
OFF, ON
OFF, ON
OFF, ON
37
38
39
40
Output #29
Output #30
Output #31
Output #32
INDICATORS 1-16:
LIGHT WHEN OUTPUT IS TURNED ON
Output #22
Output #23
Output #24
INDICATORS 25-40:
LIGHT WHEN OUTPUT IS TURNED ON
Figure 9-16. NVO, NVOAC and NVO-SNK Board LED Indications
P/N 59473-785, 59473-936, 31166-123
P2086B, Volume 1, Rev. D, Nov/13
9–16
Alstom Signaling Inc.
Board Reference Data
9.2.17
NVORELAY Board LED Indications, P/N 31166-238
DS1
Output #1
DS2
Output #2
DS3
Output #3
DS4
Output #4
DS5
Output #5
DS6
Output #6
DS7
Output #7
DS8
Output #8
DS9
Output #9
DS10
Output #10
DS11
Output #11
DS12
DS41
DS13
Output #12
Group 1 & 2 Power
Output #13
DS14
Output #14
DS15
Output #15
DS16
Output #16
DS17
DS18
Board Select
DS19
I/O Select
Data Output Enabled
DS20
External Select
DS21
Group 4 Select
DS22
Group 3 Select
DS23
Group 2 Select
DS24
DS25
Group 1 Select
Output #17
DS26
Output #18
DS27
Output #19
DS28
Output #20
Group 3&4 Power
DS42
DS29
DS30
Output #21
DS31
Output #23
DS32
Output #24
DS33
Output #25
DS34
Output #26
DS35
Output #27
DS36
Output #28
DS37
Output #29
DS38
Output #30
DS39
Output #31
DS40
Output #32
Output #22
Figure 9-17. NVORELAY Board LED Indications, P/N 31166-238
P2086B, Volume 1, Rev. D, Nov/13
9–17
Alstom Signaling Inc.
Board Reference Data
9.2.18
NVTWC-MOD Board LED Indications, P/N 31166-099
S1
DS2
DS6
DS7
RESET SWITCH
RECEIVE ID (SPACE)
TRANSMIT ID
RECEIVE ID (MARK)
DS8
PROGRAMED STOP
DS9
BIT CLOCK 18 Hz
DS10
TRACK SYNC 3Hz
DS11
BOARD SELECT
CHANNEL 3
DS13
RECEIVE ID (SPACE)
CHANNEL 1
DS17
RECEIVE ID (MARK)
DS18
TRANSMIT ID
DS19
PROGRAMED STOP
DS20
BIT CLOCK 18 Hz
DS21
TRACK SYNC 3Hz
DS22
RESET
J2 MAC PORT
E1 COMMON
E2 +5 VOLTS
Figure 9-18. NVTWC-MOD Board LED Indications, P/N 31166-099
P2086B, Volume 1, Rev. D, Nov/13
9–18
Alstom Signaling Inc.
Board Reference Data
9.2.19
NVTWC-FSK Board LED Indications, P/N 31166-119
S1
Reset Switch
E1
E2
Channel 4 Receive Data
Channel 4 Demodulated Data
E3
E4
Channel 3 Demodulated Data
Channel 3 Receive Data
E5
E6
Channel 2 Demodulated Data
Channel 2 Receive Data
E7
E8
Channel 1 Demodulated Data
Channel 1 Receive Data
DS1
DS2
DS3
DS4
Channel 1 Receive
Channel 2 Receive
Channel 3 Receive
Channel 4 Receive
DS5
DS6
DS7
DS8
Channel 4 Receive Enable
Channel 3 Receive Enable
Channel 2 Receive Enable
Channel 1 Receive Enable
DS9
DS10
DS11
DS12
Channel 4 Transmit
Channel 3 Transmit
Channel 2 Transmit
Channel 1 Transmit
DS13
DS14
Board Select
Board Reset
J2
MAC Port
E9
+5 volts
E10
Common
Figure 9-19. NVTWC-FSK Board LED Indications, P/N 31166-119
P2086B, Volume 1, Rev. D, Nov/13
9–19
Alstom Signaling Inc.
Board Reference Data
9.2.20
NVTWC-MUX Board LED Indications, P/N 31166-100
RESET SWITCH
DS1
TRANSMIT
DS2
RECEIVE
DS3
PROGRAMMED STOP
DS4
BIT CLOCK 18 Hz
DS5
TRACK SYNC 3Hz
DS6
TRANSMIT
DS7
RECEIVE
DS8
PROGRAMMED STOP
DS9
BIT CLOCK 18 Hz
DS10
BOARD SELECT
DS12
TRANSMIT
DS13
RECEIVE
DS14
PROGRAMMED STOP
DS15
BIT CLOCK 18 Hz
CHANNEL 2
TRACK SYNC 3Hz
DS17
RECEIVE
DS18
TRANSMIT
DS19
PROGRAMMED STOP
DS20
CHANNEL 3
TRACK SYNC 3Hz
DS11
DS16
CHANNEL 4
CHANNEL 1
BIT CLOCK 18 Hz
DS21
TRACK SYNC 3Hz
DS22
RESET
J2 MAC PORT
E1
COMMON TEST POINT
E2
+5VDC TEST POINT
Figure 9-20. NVTWC-MUX Board LED Indications, P/N 31166-100
P2086B, Volume 1, Rev. D, Nov/13
9–20
Alstom Signaling Inc.
Board Reference Data
9.3
BOARD LAYOUT
Figure 9-21 through Figure 9-66 show board layouts including jumper locations,
interconnections and other information needed for maintenance related activities.
CPU Board, P/N 59473-742-00
PROGRAM CPU CONTROLS
9.3.1
MANUAL
RESET
SW1
SHADOW APP.
EPROM
SHADOW APP.
EPROM
U8
U20
LEDs
DIP
SWITCH
(See Next Page)
SW2
APPLICATION
EPROM
APPLICATION
EPROM
HANDHELD
TERMINAL
CONNECTION
PC4
U5
U17
APPLICATION
EPROM
APPLICATION
EPROM
U4
U16
SYSTEM
EPROM
SYSTEM
EPROM
U3
U15
SYSTEM
EPROM
U2
SYSTEM
EPROM
U14
MAIN CPU 8086
59473-742 GR.
Figure 9-21. CPU Board, P/N 59473-742-00
P2086B, Volume 1, Rev. D, Nov/13
9–21
Alstom Signaling Inc.
Board Reference Data
Switch Section
1
Indicates Side of
Switch that is Down
1
2
3
4
POS B
SW2
Front
of
Board
POS A
Figure 9-22. CPU Board DIP Switch Settings
Table 9–1. CPU Board Switch 2 (SW2) Normal Functions
Switch
Section
Position
1
A
Two System PROMs (Normal Configuration)
1
B
Four System PROMs
2
B
Allows Use of Handheld Terminal for Diagnostics
(Connects Current Loop Receive)
3
A
Normal Operation Position
4
B
Enables Watchdog Timer (Auto Reset Function)
P2086B, Volume 1, Rev. D, Nov/13
Function
9–22
Alstom Signaling Inc.
Board Reference Data
9.3.2
PD Board, P/N 59473-737-00
Figure 9-23. PD Board, P/N 59473-737-00
P2086B, Volume 1, Rev. D, Nov/13
9–23
Alstom Signaling Inc.
Board Reference Data
9.3.3
CPU/PD Board, P/N 31166-029-00
S2
COMMUNICATIONS
OPTIONS
HHT
CONNECTION
LEDs
RAM
U14
RAM
U15
SYSTEM
EPROM
U16
SYSTEM
EPROM
U17
MANUAL
APPLICATION
EPROM
RESET
CPU
U18
APPLICATION
EPROM
U19
U13
31166-029 GR.
Figure 9-24. CPU/PD Board, P/N 31166-029-00
P2086B, Volume 1, Rev. D, Nov/13
9–24
Alstom Signaling Inc.
Board Reference Data
2
3
4
CTS1
1
CTS0
THIS SIDE
DOWN FOR
DIFFERENTIAL
RXD1
RXD0
RS232
1
Switch Section
Indicates Side of
Switch that is Down
Figure 9-25. CPU/PD Board DIP Switch S2 Settings
Table 9–2. SW2 DIP Switch Settings
Position
Position A
Position B
1
* MAC Port 0 Rx Rs232
2
Port 1 Rx Rs232
* CRG Port 1 Rx Rs422
3
* MAC Port 0 CTS Rs232
MAC Port 0 CTS Rs422
4
Port 1 CTS Rs232
MAC Port 0 Rx Rs422
* Port 1 CTS Rs422
* = default settings, differential is Rs422
P2086B, Volume 1, Rev. D, Nov/13
9–25
Alstom Signaling Inc.
Board Reference Data
Table 9–3. MAC Port Rear and Front Wiring
Description
Rear, P3-
Front, J1-
RX Rs232
33
3
TX Rs232
29
2
RTS Rs232 (Not supported, do not wire)
34
8
CTS Rs232 (Not supported, do not wire)
30
7
COM Rs232 (Com for HHT)
27
5
RXA (+) Rs422 (+5 for HHT)
35
9
RXB (-) Rs422
28
1
TXA (+) Rs422
32
4
TXB (-) Rs422
31
6
P2086B, Volume 1, Rev. D, Nov/13
9–26
Alstom Signaling Inc.
Board Reference Data
9.3.4
VRD Board, P/N 59473-740-00
LED
TP3
VRD Reset
Pushbutton
IC14
SW2
LEDs
TP2
TP4
16 Position
Switch
(See Next Page)
SW1
TP1
VITAL RELAY DRIVER
TP5
59473-740 GR
Figure 9-26. VRD Board, P/N 59473-740-00
P2086B, Volume 1, Rev. D, Nov/13
9–27
Alstom Signaling Inc.
Board Reference Data
VRD Reset
Pushbutton
F
C
A
E
8
0
2
6
Place Rotary
Switch in Position
"F" for Auto
Restart
4
Figure 9-27. VRD Board SW1 Switch Setting
P2086B, Volume 1, Rev. D, Nov/13
9–28
Alstom Signaling Inc.
Board Reference Data
9.3.5
VSC Board, P/N 59473 939-00
POS
P3
JU10
8
HHT
PORT
OFF
1
S1*
JU11
JU13
JU12
ON
LEDs
8
1
P2
S2*
SYSTEM
EPROM
LEDs
APPLICATION
EPROM
S3
RESET
P1
4
S4*
DUAL PORT RAM
IC29
1
OFF
5V COM
TP10
VITAL SERIAL CONTROLLER
59473-939-KN
Figure 9-28. VSC Board, P/N 59473 939-00
P2086B, Volume 1, Rev. D, Nov/13
9–29
Alstom Signaling Inc.
Board Reference Data
9.3.6
VSC Board, P/N 59473-939-00 with T1 Adapter Board Layout
TB5
TB5
S1 1
A
TB1
POS
T1 ADAPTER
4
B
OFF
TB3
PORT
TB4
TB2
HHT
P3
S1*
ON
LEDs
8
1
P2
S2*
SYSTEM
EPROM
LEDs
APPLICATION
EPROM
S3
RESET
P1
4
S4*
DUAL PORT RAM
IC29
1
OFF
5V COM
TP10
VITAL SERIAL CONTROLLER
59473-939-KN
Figure 9-29. VSC Board, P/N 59473-939-00 with T1 Adapter Board Layout
P2086B, Volume 1, Rev. D, Nov/13
9–30
Alstom Signaling Inc.
Board Reference Data
Switch Position
1
Indicates Side of
Switch that is Down
1
ON
2
3
OFF
4
5
6
7
8
OPEN
S1 - CONFIGURES HANDSHAKE SIGNAL TO THE SERIAL
COMMUNICATIONS CONTROLLER
Figure 9-30. VSC Board DIP Switch S1 Settings
Note: All OFF when using the 31166-058-01 daughter board
assembly.
Table 9–4. VSC Board DIP Switch S1 Settings
Switch
Position
OFF
ON
1
Transmit Data Out Disabled
*Transmit Data Out Enabled
2
MED Transmit Sync Disabled
*MED Transmit Sync Enabled
3
*Non-Valid Manchester Code To
Scc-Cts\ Disabled
Non-Valid Manchester Code To
Scc-Cts\ Enabled
4
*Not Used
5
Receive Data From MED Disabled
*Receive Data From MED Enabled
6
Transmit Clock From MED Disabled
*Transmit Clock From MED Enabled
7
Receive Clock From MED Disabled
*Receive Clock From MED Enabled
8
*Not Used
* Default switch position when not using the 31166-058-01 daughter board
P2086B, Volume 1, Rev. D, Nov/13
9–31
Alstom Signaling Inc.
Board Reference Data
Switch Section
1
Indicates Side of
Switch that is Down
1
ON
2
OFF
3
4
5
6
7
8
OPEN
S2 - OPERATIONAL FUNCTIONS
Figure 9-31. VSC Board DIP Switch S2 Settings
Table 9–5. VSC Board DIP Switch S2 Settings
Switch
Section
OFF
ON
1
* Async data 1 enabled
** Sync data 1 enabled
2
* Async data 2 enabled
** Sync data 2 enabled
3
*Not used
4
*Not used
5
*Not used
6
*Not used
7
9600 Baud select 1
** 19.2 Baud select 1
8
9600 Baud select 2
** 19.2 Baud select 2
* = Default for VSC with 31166-058-01 daughter board
* * = Default for VSC without 31166-058-01 daughter board
P2086B, Volume 1, Rev. D, Nov/13
9–32
Alstom Signaling Inc.
Board Reference Data
The following jumpers affect the operation of the direct wire interface only. When using
the 31166-058-01 daughter board they have no effect on the board operation. Refer to
Figure 9-28 for the location of the following jumpers.
Table 9–6. Line Termination Jumpers for Copper Pair Interface
Jumper
Installed
Function/Explanation
JU10
yes
Connects the back-to-back junction of suppressors CR6 & CR7
to the logic common. This provides transient protection for the
direct wire transmitter.
JU11
yes
Connects the back-to-back junction of suppressors CR4 & CR5
to the logic common. This provides transient protection for the
direct wire receiver.
JU12
no
Transmitter output level 1:2 (JU13 not installed)
JU13
yes
Transmitter output level 1:1 (JU12 not installed)
Switch Section
1
Indicates Depressed
Side of Switch
1
2
3
4
OFF
ON
S4 - MISCELLANEOUS FUNCTIONS
Figure 9-32. VSC Board DIP Switch S4 Settings
P2086B, Volume 1, Rev. D, Nov/13
9–33
Alstom Signaling Inc.
Board Reference Data
Table 9–7. VSC S4 Miscellaneous Function Settings
Switch
Section
OFF
ON
1
*Enable Auto Watchdog Reset
Disable Reset
2
*Memory Select 16K X 8 EPROM
(System, U16)
Memory Select 32K X 8 EPROM
(System, U16)
3
*Memory Select 16K X 8 EPROM
(Application, U18)
Memory Select 32K X 8 EPROM
(Application, U18)
4
Select Alternate Reset Vector
*Select Normal Reset Vector
* Default Switch Position
WARNING
Although the VSC board assembly is equipped with a 9-pin connector that is
similar to that used by other processors for diagnostic information and
access to internal status, there are no diagnostics available with this board
assembly. Attempts to access diagnostics on this assembly may result in
interruption to the operation of the VSC functions and VSC parameters. This
in turn may affect the operation of the interlockings that depend upon the
VSC parameters.
P2086B, Volume 1, Rev. D, Nov/13
9–34
Alstom Signaling Inc.
Board Reference Data
1
Pin 1 End
TB5
Terminal
Block ID
Shorting Jumper
Switch Section
Indicates Side of
Switch that is Down
TB5
T1 ADAPTER
S1 1
A
4
TB1
B
TB4
TB3
TB2
Figure 9-33. 31166-058-01 Daughterboard
For normal operation of the daughterboard, all sections of S1 should be set in the “A”
position. There are five (5) terminal blocks on the daughterboard. For the operating
positions of them refer to the table below.
Terminal Block
Jumper Position
TB1
1-2
TB2
2-3
TB3
2-3
TB4
1-2
TB5
1-2
P2086B, Volume 1, Rev. D, Nov/13
9–35
Alstom Signaling Inc.
Board Reference Data
9.3.7
CRG Board, P/N 31166-261-00
Figure 9-34. CRG Board, P/N 31166-261-00
P2086B, Volume 1, Rev. D, Nov/13
9–36
Alstom Signaling Inc.
Board Reference Data
I/OB Board, P/N 59473-827-00
LEDs
PC2
SIGNATURE
PC1
MAIN BUS
PC4
HEADER
I/O BUS
PC3
BUFFERED MAIN BUS
9.3.8
I/0 BUS INTERFACE
59473-827 GR.
Figure 9-35. I/OB Board, P/N 59473-827-00
P2086B, Volume 1, Rev. D, Nov/13
9–37
Alstom Signaling Inc.
Board Reference Data
9.3.9
DI Board, P/N 59473-867-00
AD
TP5
SN
TP4
+5V
TP3
TP7
5VCOM
TP2
TP6
DR
TP1
TP9
LEDs
SIGNATURE
HEADER
TP8
VITAL INPUT
59473-867 GR
Figure 9-36. DI Board, P/N 59473-867-00
P2086B, Volume 1, Rev. D, Nov/13
9–38
Alstom Signaling Inc.
Board Reference Data
SBO Board, P/N 59473-739-00
CR83
1
FL1
+
R43
Q14
CH1
CR24
T7
C55
IC26
R80
P3
RV7
L10
L9
RV6
1
T5
CH3
CR20
IC24
R72
Q21
1
RV5
C26
C51
IC23
49
R70
R69
R35
C13
R67
R31
+
R7
C35
1
R196
R34
C22
RN2
IC1
R33
L4
C27
Q10
IC2
R68
R199
1
IC12
C12
IC3
TP4
1
RN4
P2
H1
C9
C8
C7
COM
TP2
IC17
1
IC18
IC27
IC15
IC16
TP3
T4
L5
R28
Q8
+5V
TP1
FL5
1
R74
R73
IC28
CR5
CR18
1
R66
R65
R30
IC22
R64
+
35
L11
VR2
C10
R60
Q18
R19
R57
P1
RV2
R58
R20
C42
CH7
CR12
T1
L8
C31
R13
Q3
Q2
R55
R16
IC20
R56
1
Q17
R51
R11
R54
RV1
R3
C39
R12
R14
1
R53
R15
C41
CH8
IC19
R52
1
C30
Q1
C43
RV3
IC21
1
R4
R192
TP6
RN5
SINGLE BREAK OUTPUT
FL8
T2
CH6
CR14
C38
R191
1
IC8
IC42
IC11
C3
CR89
C47
L7
C28
R18
Q5
Q4
IC9
IC10
TP7
C40
CR90
R62
R61
R25
R17
C1
FL7
R5
C37
R194
R59
R21
CR2
C17
CR87
R24
1
C45
FL6
1
Q19
R22
C20
L12
T3
CH5
CR16
1
CR3
C11
C46
L6
C29
R23
Q7
Q6
R63
R26
RV4
R6
1
IC4
RN1
IC5
RN3
C44
C23
R29
C36
R193
C18
1
Q20
R27
CR4
CH8
C14
C50
CH4
CR1
FL4
1
R8
C34
R195
TP8
1
C48
FL3
T6
R38
Q12
IC13
IC6
TP5
R71
R36
R40
R32
C2
CR88
R76
Q22
R39
Q9
CR6
IC25
R37
C49
C19
CR85
R77
CH2
CR22
Q11
CR7
CR86
R78
R45
C54
L3
C24
C52
C16
FL2
1
R9
R75
R41
Q13
CH1
CR84
R44
C33
R197
C21
C4
CR8
Q23
R42
IC7
CR9
C15
R82
R81
R50
L1
IC14
WR
C25
Q15
C53
VR1
R49
R79
R46
35
Q24
RV8
R1
R10
C32
+
T8
L2
R48
Q16
R198
C5
C6
R2
RD
CR10
CR26
R47
+
9.3.10
Figure 9-37. SBO Board, P/N 59473-739-00
P2086B, Volume 1, Rev. D, Nov/13
9–39
Alstom Signaling Inc.
Board Reference Data
9.3.11
DBO Board, P/N 59473-747-00
LEDs
LED
LED
TP3
TP6
LED
TP5
TP4
LED
LED
LED
SIGNATURE
PROM
TP2
LED
LED
TP1
59473-747 GR.
Figure 9-38. DBO Board, P/N 59473-747-00
P2086B, Volume 1, Rev. D, Nov/13
9–40
Alstom Signaling Inc.
Board Reference Data
DBO-50V Board, P/N 59473-977-00
+
+
+
1
RV4
+
+
49
CR30
R56
R55
C53
+
+
+
C52
U11
1
R117
+
1
CR35
C64
RV5
VR23
+
+
RV6
C73
+
Q28
FL12
VR27
FL13 VR28
RV7
C86
CR45
+
R102
R101
CR44
Q32
VR26
C85
C84
+
R114
R113
R112
FL14
VR30
VR31
C96
FL15 VR32
1
RV8
C97
CR50
+
CH8
+
R116
R115
CR49
C93
C94
VR22
FL11 VR24
C83
T16
35
C75
CR40
R88
R87
CR39
T14
FL10
C74
C72
CR48
CR47
CH7
C92
+
C51
R74
R73
CR34
VR19
FL9 VR20
Q24
R100
R99
R98
+
T15
R108
Q31
C99
C63
+
+
RV3
CR29
C50
T12
C62
C82
C91
R111
R110
R109
C90
C89
R107
L8
C88
Q30
C61
CR43
CR42
CH6
C81
VR29
U25
Q20
R86
R85
R84
+
Q27
U29
R105
R106
C87
T13
Q26
+
Q29
CR46
T10
C71
C80
R97
R96
R95
R94
C76
R103
R104
U18
VR18
CR38
CR37
CH5
C70
+
VR25
C79
C78
R93
L7
C77
R91
R92
TB3
R202
R72
R71
R70
+
C69
R83
R82
R81
R80
Q23
U28
CR41
U10
C60
+
VR21
C68
C67
R79
L6
C66
Q25
T11
Q22
R89
R90
CR25
R42
R41
R201
U24
CR33
CR32
C59
C58
R69
R68
R67
R66
Q21
Q19
C65
CH8
CR10
U23
U27
R77
R78
CR9
VR16
C98
C42
U17
U16
VR17
C57
C56
R65
L5
C55
T9
Q18
CR36
C43 VR15
C49
1 TB6
TB5
U26
C54
R75
R76
FL8 VR14
U21
Q17
1
TB4
R63
R64
CR8
RV2
CR24
CH4
U15
U14
U20
R204
1
CR31
CR20
R28
R27
C40
U9
C48
U13
R60
R203
R61
R62
RV1
CR19
Q16
C41
U8
U7
U22
CR7
FL7 VR12
C44
C31
T8
TB2
CR6
U19
E2
COM
C32 VR11
TB1
1
C46
U12
FL6 VR10
1
+
R59
VR8
FL5
Q12
U6
U5
CR5
C11
R14
R13
T6
R54
R53
R52
+
C47
T7
R58
+
Q14
R57
Q15
VR7
C30
CR28
CR27
CH3
C39
C38
R44
R45
R46
+5V
E1 C45
R51
R48
CR26
C37
C36
R47
L4
R43
C35
CR4
R50
R49
C34
FL4 VR6
C33
C29
U4
Q13
FL3 FL2
C22
C21
C20
R40
R39
R38
VR13
FL1 VR4
Q8
C19
CR23
CR22
CH2
Q11
T5
Q10
+
R32
+
R34
R30
R31
VR3
C9
T4
C18
C28
C27
R37
C26
C25
R33
L3
C24
R36
R35
C23
R29
VR2
CR15
R26
R25
R24
VR9
U3
Q9
C8
CR18
CR17
CH1
+
Q7
T3
Q6
+
R18
35
CR14
C7
C17
C16
R23
R22
R21
R20
R16
R17
Q4
R12
R11
R10
+
VR5
C15
C14
R19
L2
C13
R15
CR16
T2
C10
U2
C12
CR21
+
Q3
T1
Q2
Q5
CH1
CR3
C6
R6
R4
WR
C5
C4
C3
R2
R3
CR2
R9
R5
C2
R1
L1
RD
CR11
CR1
R8
R7
C1
CR13
CR12
VR1
U1
Q1
+
9.3.12
C95
FL16
DOUBLE BREAK OUTPUT 50V
Figure 9-39. DBO-50V Board, P/N 59473-977-00
P2086B, Volume 1, Rev. D, Nov/13
9–41
Alstom Signaling Inc.
Board Reference Data
9.3.13
LDO Board, P/N 59473-749-00
LEDs
TP8
TP7
TP6
LED
LED
TP4
SIGNATURE
PROM
LED
TP5
LED
5VCOM
TP2
LED
TP3
LED
+5V
TP1
LED
LED
59473-749 GR.
Figure 9-40. LDO Board, P/N 59473-749-00
P2086B, Volume 1, Rev. D, Nov/13
9–42
Alstom Signaling Inc.
Board Reference Data
9.3.14
ACO Board, P/N 59473-937-00
LEDs
LED
LED
TP1
LED
LED
TP4
TP6
TP5
LED
+5V
TP2
LED
SIGNATURE PROM
LED
TP3
5VCOM
LED
AC OUTPUT
59473-937 GR.
Figure 9-41. ACO Board, P/N 59473-937-00
P2086B, Volume 1, Rev. D, Nov/13
9–43
Alstom Signaling Inc.
Board Reference Data
FSVT Board, P/N 59473-894-00
TS7
TS5
9
8
7
TM7 6
5
4
3
2
1
0
UM7
TB9
TB27
TB26
TB17
TIMER
7
TB25
ONE JUMPER MUST BE INSTALLED IN EACH COLUMN
O O
JUMPER ORIENTATION
US7
9
8
7
6 TM6
5
4
3
2
1
0
US5
9
8
7
TM5 6
5
4
3
2
1
0
UM5
TB19
TB18
TIMER
5
INITLS.
9
8
7
TM3 6
5
TIMER
4
3
3
2
1
0
UM3
TB28
1
DATE
CHECKED
TB11
TB10
TB31
TB30
TB29
TB20
TS3
TS1
9
8
7
6
5 TIMER
4
8
3
2
1
0
TS8
UM8
TB21
9
8
7
6 TM4
5
4
3
2
1
0
US3
9
8
7
6 TM2
5
4
3
2
1
0
US1
TIME
SETTING
TB3
9
8
7
TM1 6
5
TIMER
4
1
3
2
1
0
TB23
TB22
9
8
7
6 TM8
5
4
3
2
1
0
UM6
TB13
TB12
TB1
TB32
TS6
TB15
TB14
TB4
TB2
US8
TB24
TS4
TB7
TB6
UM4
UM2
TS2
TB16
TB5
UM1
9
8
7
6
5 TIMER
4
6
3
2
1
0
US6
US4
US2
NAME
TB8
P3
9
8
7
6
5 TIMER
4
4
3
2
1
0
36
TIMER
NO.
1
2
3
4
5
6
7
8
9
8
7
6
5 TIMER
4
2
3
2
1
0
9.3.15
49
RN4
IC14
IC25
IC13
IC29
IC24
IC33
C6
CR9
RN3
TP3
IC12
RN7
RN2
IC32
C5
PC1
IC28
RN1
IC7
C8
RN6
IC20
C2
IC19
NM 5-8
IC8
C9
1
IC9
COM
IC31
C3
IC22
IC21
TP1
TEST POINTS
TP2
IC10
LBL0
IC23
+
IC11
+5V
IC34
P2
CR12
CR11
CR10
RN9
C4
12
11
10
9
RN8
C7
CR16
CR15
CR14
CR13
LBL1
NONFIELD SET
16
15
14
13
1
IC27
2
P1
IC6
IC18
RN5
IC1
TIMER 4
TIMER 3
TIMER 2
TIMER 1
CR4
CR3
CR2
CR1
IC5
IC30
IC17
IC4
IC16
IC26
C1
CR8
CR7
CR6
CR5
NM 1-4
TIMER 8
TIMER 7
TIMER 6
TIMER 5
IC3
IC15
IC2
VITAL TIMER
Figure 9-42. FSVT Board, P/N 59473-894-00
P2086B, Volume 1, Rev. D, Nov/13
9–44
Alstom Signaling Inc.
Board Reference Data
SET FOR
12 MINUTES, 45 SECONDS
ONE JUMPER MUST BE INSTALLED IN EACH COLUMN
JUMPER ORIENTATION:
TB1
TB2
TB3
TB4
9
9
50
8
7
6
5
50
8
7
6
5
40
30
20
4
3
2
40
30
20
4
3
2
10
0
1
0
10
0
1
0
T.MIN
U.MIN
T.SEC
U.SEC
(0 to 59 Min. & 59 Sec.)
SET FOR
4 MINUTES, 10 SECONDS
TB1
TB2
TB3
9
8
7
6
5
50
40
30
20
50
40
4
3
30
20
10
0
2
1
0
10
0
T.MIN
TB4
9
8
7
U.MIN
T.SEC
6
5
4
3
2
1
0
U.SEC
(0 to 59 Min. & 59 Sec.)
Figure 9-43. Timer Setting Example
P2086B, Volume 1, Rev. D, Nov/13
9–45
Alstom Signaling Inc.
Board Reference Data
9.3.16
CSE Board, P/N 59473-741-00
Figure 9-44. CSE Board, P/N 59473-741-00
P2086B, Volume 1, Rev. D, Nov/13
9–46
Alstom Signaling Inc.
Board Reference Data
9.3.17
CSEX1 Board, P/N 59473-938-00
P3
WATCH
DOG
TIMER
JUMPER
DB9
MAINTENANCE
INTERFACE
COMMUNICATIONS
JUMPER
S
RESET
T
SWITCH
TP2 +5V
CR19
P2
CR18
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
LEDs for
CR7
CR6
CR5
Code
CR4
System
CR3
CR2
CR1
TP3 COM
U36
Sy EP
steRO
m M
U49
Sy EP
steRO
m M
U37
Ap
plicEP
ati RO
on M
U38
U50
Ap
plicEP
ati RO
on M
U51
U39
P1
U52
TP
1
SYSTEM
EPROM
JUMPERS
CSEX BOARD 59473-938
APPLICATION
EPROM
JUMPERS
Figure 9-45. CSEX1 Board, P/N 59473-938-00
P2086B, Volume 1, Rev. D, Nov/13
9–47
Alstom Signaling Inc.
Board Reference Data
9.3.18
CSEX3 Board, P/N 31166-175-00
Figure 9-46. CSEX3 Board, P/N 31166-175-00
P2086B, Volume 1, Rev. D, Nov/13
9–48
Alstom Signaling Inc.
Board Reference Data
9.3.19
NVI Board, P/N 59473-757-00
Figure 9-47. NVI Board, P/N 59473-757-00
P2086B, Volume 1, Rev. D, Nov/13
9–49
Alstom Signaling Inc.
Board Reference Data
9.3.20
NVID Board, P/N 31166-106-00
U6
U7
U1
U9
R7
R8
TB1
IN5
R35
RV4
R36
RV5
R37
CR6
RV6
R38
CR7
RV7
R39
CR8
RV8
R40
RV9
R41
RV10
R42
RV11
R43
CR12
RV12
R44
CR13
RV13
R45
RV14
R46
RV15
R47
RV16
R48
1
IN6
CR9
U10
IN7
R9
CR10
IN8
R10
DS8
U11
R102
R12
DS9
U2
R13
U12
IN10
1
IN9
CR11
R11
CR14
R14
IN11
C2
IN13
CR15
R15
U13
IN12
CR16
TB2
R16
TB6
+V1
1
TB9
2
TB7
1
IN15
1
U22
1
1
IN14
COM2
49
COM1
2
2
2
DS16
U23
U27
C6
E1
ESL
R106
U3
U28
U24
C7
C3
C9
COM
DS17
ISL
LCH
TB8
+V2
IN16
+5V
P3
R6
IN4
RV3
CR5
R5
C1
IN3
R34
CR4
R4
U8
DS1
RV2
CR3
R3
IN1
IN2
R33
CR2
R2
R101
RV1
CR1
R1
35
NONVITAL INPUT 6V
P2
BSL
U29
GR4
R105
TB3
1
GR3
U25
U30
GR2
C10
GR1
U26
C8
DS24
COM
E2
+
C11
IN17
TB10
1
2
1
+V4
1
COM3
TB12
2
1
TB11
1
COM4
IN19
2
TB13
2
DS25
IN18
+V3
IN20
IN21
U14
IN22
IN23
DS32
R103
DS33
U17
IN27
C4
IN26
U4
U16
IN25
IN28
R18
CR18
R19
CR19
R20
CR20
R21
CR21
R22
CR22
R23
CR23
CR24
TB4
IN29
CR17
R24
1
IN31
U19
IN32
DS40
R104
U20
U5
C5
U21
CR25
R50
RV19
R51
RV20
R52
RV21
R53
RV22
R54
RV23
R55
RV24
R56
RV25
R57
RV26
R58
RV27
R59
R26
CR26
R27
CR27
CR28
RV28
R60
R28
R29
CR29
RV29
R61
R30
CR30
RV30
R62
R31
CR31
RV31
R63
R32
CR32
RV32
R64
1
TB5
R25
R49
RV18
P1
U18
IN30
RV17
35
U15
IN24
R17
1
Figure 9-48. NVID Board, P/N 31166-106-00
P2086B, Volume 1, Rev. D, Nov/13
9–50
Alstom Signaling Inc.
Board Reference Data
9.3.21
NVIDSW Board, P/N 31166-276-00
Figure 9-49. NVIDSW Board, P/N 31166-276-00
P2086B, Volume 1, Rev. D, Nov/13
9–51
Alstom Signaling Inc.
Board Reference Data
9.3.22
NVO Board, P/N 59473-785-00
Figure 9-50. NVO Board, P/N 59473-785-00
P2086B, Volume 1, Rev. D, Nov/13
9–52
Alstom Signaling Inc.
Board Reference Data
NVOAC Board, P/N 59473-936-00
R33
RV1
RV3
C20
RV4
R97
C25
R101
C24
R106
C28
RV10
RV12
R105
C34
R110
C33
R109
RV5
R98
C29
R111
R107
C35
C26
C30
R112
R102
R103
C31
R108
C21
C27
R99
C22
R104
RV6
P3
RV7
RV8
RV9
RV11
1
RV13
RV15
RV14
C32
49
RV16
C52
U13
U9
1
R202
C1
C10
C9
C13
U7
U4
C14
U10
P2
U1
U2
U3
C2
C11
C5
U11
C7
R201
1
17
R82
1
RV17
RV19
C40
RV24
R117
R121
RV28
C44
C49
R126
C48
R125
35
RV20
RV22
C36
C45
RV21
R113
R118
RV23
R127
C37
C50
C46
R123
C51
R128
R122
C47
C41
C42
R124
R119
R115
C43
R120
C38
C39
R114
R116
RV26
P1
K27
RV25
K25
RV27
RV29
Q31
RV31
RV30
K29
RV32
1
K31
R32
R95
R31
R96
K32
R64
R93
R29
R94
K30
Q30
R63
K23
Q29
R62
R30
K28
Q28
K26
29
R28
R91
R27
R92
Q27
R60
R61
R89
R25
R90
K24
25
Q26
R59
K21
Q25
R58
R26
K19
Q24
R57
K22
R87
R23
R88
K20
Q23
K17
21
R85
R21
R86
RV18
R84
Q21
R56
R24
U12
R83
R19
R54
Q22
C6
Q19
K18
R20 Q20
CR38
CR39
CR40
NONVITAL AC OUTPUT
R81
R17
R22
CR35
CR36
CR37
+
W1
W2
C8
U8
Q17
R49
R55
CR33
CR34
U6
C12
Q16
R53
CR31
CR32
R79
R15
R80
1
R16
Q15
C3
R14 Q14
R47
R52
CR29
CR30
C23
C15
R18 Q18
R51
CR26
CR27
CR28
R129
R13
R78
C4
IOSEL
ESEL
CR4
CR5
CR6
LG4
PWR
LG3
LG4
CR7
CR8
TP1
+5V R50
CR25
R77
TP3
R46
CR23
CR24
TP2
COM
CR1
CR3 CR2
SEL
R48
DO
Q13
K15
R12 Q12
K13
Q11
R44
R45
K11
13
CR21
CR22
Q10
R43
K16
9
R10
R75
R11
R76
Q9
R42
CR19
CR20
R73
R9
R74
K14
Q8
K10 K12
R8
K9
R71
R7
R72
R41
R100
Q7
R40
CR16
CR17
CR18
K7
5
Q6
K5
R69
R5
R70
R6
K8
Q5
R38
R39
K6
Q4
K3
R67
R3
R68
R37
CR13
CR14
CR15
Q3
R36
R4
RV2
Q2
K1
R2
R35
K4
1
CR9
CR10
CR11
CR12
K2
R65
R1
R66
35
Q1
R34
+
9.3.23
Q32
Figure 9-51. NVOAC Board, P/N 59473-936-00
P2086B, Volume 1, Rev. D, Nov/13
9–53
Alstom Signaling Inc.
Board Reference Data
9.3.24
NVO-SNK Board, P/N 31166-123-00
NON-VITAL OUTPUT
35
R56
R96
R39
R136
R120
R161
C24
R80
R79
R119
+
R40
R16
R160
C23
U18
Q8
U10
U26
Q16
U38
Q24
Q32
SU32
CR40
SU31
CR56
R15
CR39
CR38
R14
CR48
R55
R38
R37
R54
R36
R78
R77
R76
R95
CR64
R135
CR72
R94
R118
R117
R134
R159
SU30
R158
R116
SU29
R157
SU28
CR37
U9
Q15
U17
Q7
Q23
U25
Q31
U37
P3
SU27
CR36
SU26
CR55
R13
CR35
CR34
R12
CR47
R53
R35
R34
R52
R75
R93
CR63
R133
CR71
R92
R115
R114
R132
R156
R74
R73
SU25
R155
R113
C22
R154
+
R33
CR33
C21
Q6
U8
Q14
U16
U36
Q22
U24
Q30
SU24
CR32
CR54
R11
CR31
R10
CR30
SU23
R51
CR46
R32
R50
R31
R30
CR62
R91
R90
R72
R112
R111
R71
R70
CR70
R131
R130
1
SU22
R153
R152
R151
R110
SU21
CR29
SU20
U7
U15
Q5
U23
Q13
Q29
U35
Q21
SU19
CR28
CR53
R9
CR27
CR45
CR26
R29
SU18
R49
R129
CR61
R89
CR69
R69
SU17
R109
R150
49
CR25
TP2
RN2
CR24
C6
CR23
C8
U30
U40
U44
TP3
C14
CR22
CR21
U6
C2
C5
C7
U29
C13
U43
JU2
P2
CR20
C4
CR19
RN1
U39
U28
CR18
C3
U5
C1
U42
C11
U41
+
C10
CR17
C12
JU1
U27
C9
TP1
R137
CR16
1
C20
+
CR15
CR14
C19
R48
R28
R8
R88
R108
R128
R149
C18
R68
R27
R67
R107
+
CR13
R148
C17
CR12
U4
Q4
Q20
U22
Q12
U14
Q28
U34
SU16
SU15
CR11
CR52
R7
CR10
CR44
R47
R46
CR9
R26
R25
R6
CR60
R106
R87
R66
R65
R86
CR68
R126
R147
R105
R64
R24
R127
SU14
R146
R145
R104
SU13
35
SU12
CR8
U3
Q3
Q11
U13
Q19
U21
Q27
U33
SU11
CR7
SU10
CR51
R5
CR6
CR43
R45
R44
R23
R4
R63
CR59
R125
CR67
R103
R124
R22
R62
R102
R144
R143
R21
R61
R101
R142
SU9
C16
+
CR5
R85
R84
C15
CR4
U2
U12
Q2
U20
Q10
U32
Q18
Q26
SU8
P1
CR3
CR50
R3
CR2
CR1
CR42
R20
R2
SU7
R83
R43
R42
R19
R18
R60
CR58
R100
R99
R82
R59
R58
R123
R122
R98
CR66
R141
SU6
R140
R139
SU5
SU4
U1
Q1
Q9
U11
Q17
U19
Q25
U31
SU3
R1
SU2
CR41
R41
CR49
R81
CR57
R121
CR65
1
R17
R57
R97
R138
SU1
Figure 9-52. NVO-SNK Board, P/N 31166-123-00
P2086B, Volume 1, Rev. D, Nov/13
9–54
Alstom Signaling Inc.
Board Reference Data
9.3.25
NVORELAY Board, P/N 31166-238-00
K1
CR2
SU1
K4
K3
SU5
SU6
K10
SU8
SU7
Q10
+
Q9
CR10
CR9
SU9
K11
K12
SU10
Q12
CR12
SU11
1
Q11
CR11
P3
K8
Q8
CR8
GR1,8
SU4
Q6
CR6
Q7
DS9
TP1
DS8
SU3
K9
C2
DS7
SU2
K6
K7
CR7
PS1
DS6
CR5
+5V
DS5
Q5
DS4
CR4
K5
+
DS2
DS3
CR3
Q4
GR1,1
NVR OUTPUT BOARD
DS1
Q3
C1
35
Q2
Q1
CR1
K2
GR2,1
K13
K14
DS10
CR13
CR14
DS12
SU13
K16
K15
CR15
DS13
SU14
Q16
GR1,2 POWER
Q15
DS41
SU12
Q14
Q13
DS11
CR16
SU15
SU16
DS14
R1
R2
C3
TP2
+5V
DS15
U3
GR2,8
DS17
BD SEL
DS18
EN DATA \
DS19
IO SEL
DS20
EXT SEL
DS21
GR4 SEL
DS22
GR3 SEL
DS23
GR2 SEL
DS24
GR1 SEL
DS25
GR3,1
49
C5
C4
DS16
U2
U1
C6
R3
U5
U4
P2
R4
U6
U7
+
C13
C12
R5
C10
H1
C9
C11
+
C8
TP5
GND
C7
R6
U10
1
U9
U8
C17
C16
C15
TP3
GND
DS26
TP6
+5V
C14
DS27
R7
DS28
K20
+
CR20
K22
K21
CR24
+
Q24
Q23
CR23
DS36
GR4,8
CR28
K29
K30
CR30
K31
SU28
SU29
K32
SU30
1
CR32
Q32
Q31
CR31
SU26
SU27
Q30
Q29
CR29
SU25
K28
Q28
CR27
Q27
DS39
SU24
P1
CR26
K27
DS38
SU22
SU23
K26
Q26
CR25
Q25
C19
PS2
K25
SU20
SU21
K24
K23
DS35
DS37
CR22
Q22
Q21
CR21
TP4
+5V
GR4,1
SU18
SU19
35
GR3,8
DS34
DS40
SU17
Q20
CR19
Q19
C18
DS31
DS33
CR18
K19
DS30
DS32
K18
Q18
CR17
DS29
Q17
GR3,4 POWER
R9
R8
K17
DS42
SU31
SU32
Figure 9-53. NVORELAY Board, P/N 31166-238-00
P2086B, Volume 1, Rev. D, Nov/13
9–55
Alstom Signaling Inc.
Board Reference Data
9.3.26
TWCMAIN Board, P/N 59473-996-00
Figure 9-54. TWCMAIN Board, P/N 59473-996-00
P2086B, Volume 1, Rev. D, Nov/13
9–56
Alstom Signaling Inc.
Board Reference Data
9.3.27
TWCAUX Board, P/N 59473-995-00
C8
TB2
R1
R2
C1
C10
U1
U4
U5
R103
C4
C11
TB1
Y1
C2
U6
R101
C12
U7
C6
C13
C5
U2
R102
C3
U8 C9
R104
Y2
R3
C14
U3
MODEM, AUX BD
C1 A1
C32 A32
P1
C7
U9
Figure 9-55. TWCAUX Board, P/N 59473-995-00
P2086B, Volume 1, Rev. D, Nov/13
9–57
Alstom Signaling Inc.
Board Reference Data
9.3.28
TWCATT Board, P/N 31166-021-00
Figure 9-56. TWCATT Board, P/N 31166-021-00
P2086B, Volume 1, Rev. D, Nov/13
9–58
Alstom Signaling Inc.
Board Reference Data
9.3.29
NVTWC-MOD Board, P/N 31166-099-00
P3
RESET
SWITCH
S1
LEDS
P2
MICRO
PROCESSOR
LEDS
MAC
P1
PORT
Figure 9-57. NVTWC-MOD Board, P/N 31166-099-00
P2086B, Volume 1, Rev. D, Nov/13
9–59
Alstom Signaling Inc.
Board Reference Data
9.3.30
NVTWC-MUX Board, P/N 31166-100-00
P3
RESET
SWITCH
S1
LEDS
P2
MICRO
PROCESSOR
LEDS
P1
MAC
PORT
Figure 9-58. NVTWC-MUX Board, P/N 31166-100-00
P2086B, Volume 1, Rev. D, Nov/13
9–60
Alstom Signaling Inc.
Board Reference Data
NVTWC-FSK Board, P/N 31166-119-00
R1
R2
R3
C2
R201
+
C3
RXSPACE 4
U1
Q2
Q1
35
C1
C7
R8
R9
C14
R13
RXLOCK 3
R17
R18
R19
R20
R23
R24
R25
+
U7
C21
R22
C20
W1
R21
E2
+
U8
C17
C18
R28
R29
Q5
Q4
C25
R30
U9
E3
R33
+
R35
R37
R36
C34
C31
R40
C36
C43
C37
Q6
RCV IN 2
C41
C46
R44
R46
R43
R45
C45
C44
R48
U15
C50
R50
R51
R52
C47
C49
R49
R47
C52
C51
1
U11
U10
E7
RCV IN 1
R39
U13
C48
R302
R53
R54
C56
C55
U16
C57
U18
U17
C54
+
+
U14
DEMOD DATA 1
E8
C33
C38
U12
C40
C39
E6
R32
C30
CR5
CR4
R38
C35
DEMOD DATA 2
E5
R31
R34
C32
+
C29
R41
R42
C28
C42
E4
P3
C22
R301
R26
R27
C27
RCV IN 3
U5
C12
U3
R16
E1
C26
CR3
Q3
C23
DEMOD DATA 4
DEMOD DATA 3
C8
U4
C11
CR1
U6
C24
CR2
R10
R11
C10
C16
U2
C19
RXMARK 3
RCV IN 4
C4
R12
RXSPACE 3
C13
R5
R4
R7
+
S1
C6
C9
C5
C15
RXMARK 4
R14
R15
RXLOCK 4
+
R6
+
9.3.31
C58
C61
U22
C65
RXON
C62
+
R202
U19
U20
C63
C59
1 TB1
+
+
C53
+
+
49
C60
Y1
C64
7
8
DS1
2
DS2
DS3
R203
C66
R55
U21
C67
U23
C68
L1
DS4
C71
R56
C73
U24
C70
TEST
C69
U25
C72
U26
C78
U27
DS5
DS6
+
DS7
DS8
C74
C76
C77
R204
C75
TXID
59
U28
DS9
1
2
60
DS10
C80
R57
C83
C82
C81
R58
R59
U29
Q7
+
DS12
R62
C87
C95
C86
DS14
R68
J2
C90
C105
+
C100
R78
R87
R88
R89
U36
C107
C111
Q11
R94
R95
E9
Q10
C108
C121
C122
C118
C117
R91
R90
R93
C115
C114
C113
R98
C112
35
C101
R92
+5V
+
C98
C97
R303
R84
R86
R85
C109
CR9
C116
R97
CR8
R96
U40
U41
C119
P1
R205
R99
R206
C120
U39
U38
C125
Q12
RXLOCK 2
R102
R104
R105
R106
R107
R109
U42
C126
C127
R108
RXMARK 2
C129
R207
RXSPACE 1
R111
RXLOCK 1
RXMARK 1
R113
R114
R110
R112
C124
C123
+
RXSPACE 2
E10
+
COM
U33
C93
R81
R83
R100
R101
C104
U37
R73
R75
R76
R79
Q9
U34
U35
R103
U32
C92
+
+
+
C102
R80
R82
C110
C91
C89
R67
U31
R72
R74
C103
W2
1 C106
C96
U30
C94
R61
C84
CR7
R66
R71
C99
R77
5
R69
R70
+
RESET
R65
Q8
R60
R63
CR6
C88
R64
C85
DS13
+
BD SEL
6
1
C79
DS11
9
+
J1
C128
R304
1
TWC MODEM
Figure 9-59. NVTWC-FSK Board, P/N 31166-119-00
P2086B, Volume 1, Rev. D, Nov/13
9–61
Alstom Signaling Inc.
P2086B, Volume 1, Rev. D, Nov/13
9–62
ID-15
x3
SYSTEM ID
x1
ID-0
CPU-PD
INTERFACE
ID-15
J3
9 16
8 1
J3A
x3
x2
x1
x0
SITE ID
REV ID
SYSTEM ID
J3B
2
1
9
8
19
20
2
1
4
TB5
5
J2
RS422
TB1
RS422
ID-0
3
12
11
12
11
6
2
1
S
TB6
12
11
COMM CHAN 1
RS232
TB2
CH0
S
CH1
1
2
+5V
J1
TB7 TB8
1
2
CD
TB3 TB4
1
2
+5V
1
2
CD
12
11
COMM CHAN 0
RS232
2
1
11
10
8
9
7
S
B
21
87
A
21
REV ID
x0
16
1
2
87
SITE ID
x2
J6
SYSTEM ID WIRING
CONNECTIONS TO COMMON OR
UNBROKEN LINKS ARE LOGIC "0".
1 OPEN CONNECTIONS OR BROKEN
J4
LINKS ARE LOGIC "1".
1
1
SYSTEM ID
2
12
60
9.3.32
16
16
COM
2
J5
1
P3
Board Reference Data
BPIC CPU/PD Board, P/N 31166-336-00
Figure 9-60. BPIC CPU/PD Board, P/N 31166-336-00
Alstom Signaling Inc.
Board Reference Data
9.3.33
BPIC Vital Output Board, P/N 31166-194-00
Figure 9-61. BPIC Vital Output Board, P/N 31166-194-00
P2086B, Volume 1, Rev. D, Nov/13
9–63
Alstom Signaling Inc.
Board Reference Data
BPIC Vital Input Board, P/N 31166-195-00
1
9.3.34
12
11
10
9
8
7
6
5
4
3
2
16
1
16
1
Figure 9-62. BPIC Vital Input Board, P/N 31166-195-00
P2086B, Volume 1, Rev. D, Nov/13
9–64
Alstom Signaling Inc.
Board Reference Data
9.3.35
BPIC Non-Vital I/O Board, P/N 31166-196-00
12
11
10
9
8
7
6
5
4
3
2
1
Figure 9-63. BPIC Non-Vital I/O Board, P/N 31166-196-00
P2086B, Volume 1, Rev. D, Nov/13
9–65
Alstom Signaling Inc.
Board Reference Data
9.3.36
BPIC Vital Relay / Power Board, P/N 31166-197-00
12
11
10
9
8
7
6
5
4
3
2
1
Figure 9-64. BPIC Vital Relay / Power Board, P/N 31166-197-00
P2086B, Volume 1, Rev. D, Nov/13
9–66
Alstom Signaling Inc.
Board Reference Data
9.3.37
BPIC Vital Serial Controller Board, P/N 31166-198-00
Figure 9-65. BPIC Vital Serial Controller Board, P/N 31166-198-00
P2086B, Volume 1, Rev. D, Nov/13
9–67
Alstom Signaling Inc.
Board Reference Data
9.3.38
BPIC Communications Board, P/N 31166-199-00
Figure 9-66. BPIC Communications Board, P/N 31166-199-00.
P2086B, Volume 1, Rev. D, Nov/13
9–68
Alstom Signaling Inc.
Glossary
APPENDIX A – GLOSSARY
A.1
COMMON ABBREVIATIONS
Abbreviations used throughout this manual are provided in Table A–1
Table A–1. Glossary (Cont.)
Term
Definition or Explanation
AAR
American Association of Railroads, Replaced by AREMA
AC
Alternating Current
AF
Audio Frequency
Algorithm
A step-by-step procedure used to solve a problem
AREMA
American Railway Engineering and Maintenance of way Association
ARES
Advanced Railroad Electronic System
ATC
Automatic Train Control
ATCS
Advanced Train Control System
BBRAM
Battery-Backed RAM
BOM
Bill of Materials, a listing of the components that make up an
assembly
Byte
This is a group of eight bits handled as a unit
Clock
A device in a CPU that sends out electrical pulses at a fixed rate;
the control unit uses the pulses to synchronize its operation
Compiler
Circuit that translates a high-level computer language into machine
language
CPU
Central Processing Unit- the computer section that handles the
actual processing of data into information
Data
Simply stated, it is another name for information
DC
Direct Current
Demultiplexing
The process of extracting a specific signal from a circuit carrying
multiple (multiplexed) signals
Diagnostic
The process of detection and isolation of either a malfunction or
mistake
Diagnostic
Routine
A routine designed specifically to locate a malfunction in the
computer
DIP
Dual In-line Package
P2086B, Volume 1, Rev. D, Nov/13
A–1
Alstom Signaling Inc.
Glossary
Table A–1. Glossary (Cont.)
Term
Definition or Explanation
DOT
Department Of Transportation
DPRAM
Dual-Ported Random Access Memory
Dual Port
Memory
A shared memory (random access memory) that provides a
mechanism for exchanging data between separate processor
busses
DUART
Dual Universal Asynchronous Receiver/Transmitter
EMI
Electromagnetic Interference
EPROM
Erasable Programmable Read-Only Memory
Fail-Safe
The concept that if a system fails only a safe result will occur
Failure Mode
The effect by which a failure is observed, for example, short circuit
Firmware
Instructions stored on a ROM chip
FPGA
Field Programmable Gate Array
FRA
Federal Railroad Administration
Handshaking
Process
The exchange of predetermined signals for control purposes while
establishing a connection between two data sets or modems; also,
where predetermined arrangements of characters are exchanged by
the receiving and transmitting equipment to establish
synchronization
Hardware
The electronic section of the computer that stores and manipulates
symbols under the direction of the computer
HHT
Hand-Held Terminal
I/O
Input/Output
Initialization
The process of setting a circuit or portion of a circuit to a known
state (typically on power-up or reset)
Interface
The equipment that enables one kind of hardware to be recognized
and processed by another kind of hardware
Interrupt
The computer instruction that tells the computer to stop a program
and do some other, more important task
Latch
A mode of operation for a circuit in which an output's state is
maintained
LED
Light-Emitting Diode
Logic Symbol
A symbol used to graphically represent a logic element.
LSB
Least Significant Bit
P2086B, Volume 1, Rev. D, Nov/13
A–2
Alstom Signaling Inc.
Glossary
Table A–1. Glossary (Cont.)
Term
Definition or Explanation
MAC
Maintenance ACess Port. A connection point for a VT100
compatible terminal used to access Non-Vital diagnostics
Modem
A piece of equipment that connects data terminal equipment to a
communication line
MOV
Metal Oxide Varistor, used for voltage surge suppression
MSB
Most Significant Bit
N/A
Not Applicable
NC
No Connection
Non-Vital Circuit
This circuit provides either support or secondary services for the
Vital networks; its failure is not considered critical to the safe
operation of a railroad
PD
Polynomial Divider
Polynomial
A sum of two or more algebraic terms, each of which consists of a
constant multiplied by one or more variables raised to a nonnegative integral power
P/N
Part Number (also known as Drawing Number)
Port
A place of access to a device where energy may be supplied or
withdrawn, or where the device may be observed or measured
PPM
Pulses Per Minute
Primordial
The logic rules applied to functions to be performed which assure
safe operation
Processing
The conversion of raw data into usable information.
Program
A series of instructions for the computer to follow
PROM
Programmable Read-Only Memory- programmable memory devices
that store firmware
RAM
Random Access Memory- this part of memory temporarily stores
information that is constantly being changed in the computer; here,
words may be stored (written) or read (retrieved) in any order at
random
Register
Where digital information is temporarily stored in a CPU or other
digital logic device
Reset
It changes a bit value to zero or an output to an inactive condition
ROM
Read-Only Memory- this part of memory is built in during the
manufacturing process; ROM stays intact even after the computer is
turned off
P2086B, Volume 1, Rev. D, Nov/13
A–3
Alstom Signaling Inc.
Glossary
Table A–1. Glossary (Cont.)
Term
Definition or Explanation
RTC
Real-Time Clock
Signature
Header
Its purpose is to associate a type of board to its assigned position in
the system. This device consists of a small plug-in printed circuit
board or a PROM IC chip
Simulator
A special program that represents the behavior of a system
SMT
Surface Mount Technology
Software
Programs that direct the activity of the computer
SRAM
Static Random Access Memory
Subroutine
A section of a program that carries out a specific operation
Task
A program that is run as an independent unit
TWC
Train-to-Wayside Communications
UART
Universal Asynchronous Receiver Transmitter
USART
Universal Synchronous/Asynchronous Receiver/Transmitter
Vital Component
or Circuit
Any device, circuit or software module used to implement a Vital
function; a Vital circuit is so named because its function is critical to
the operation of certain signals and track equipment
Vital Function
A system, subsystem, equipment or component that provides a
function critical to safety; it is implemented using fail-safe hardware
and/or relays
VPI
Vital Processor Interlocking
Watchdog Timer
A form of internal timer that is used to detect a possible malfunction;
also, it is a timer set by a program to prevent the system from
looping endlessly
Word
This is a group of two bytes
XOR
eXclusive OR
P2086B, Volume 1, Rev. D, Nov/13
A–4
Alstom Signaling Inc.
VPI Capacity Guidelines
APPENDIX B – VPI CAPACITY GUIDELINES
B.1
CAPACITY OVERVIEW
Several factors dictate how large an application one VPI system can handle. Due to the
various hardware configurations and application logic requirements, it can be difficult to
determine before design completion whether the application size exceeds that which
one system can properly execute. However, there are criteria available that define when
an upper boundary is approached. A general guideline for estimating the capacity of an
applied VPI system is given below. This guideline is based on which processor board is
used: CPU or CPU/PD. Processing time estimates can be made using a spreadsheet
with the VPI CAA. Consult Alstom if a more exact system estimate is required than the
general guidelines provide.
B.2
HARDWARE CRITERIA
For the largest applied system there are certain limits concerning the number of certain
printed circuit boards that may be used. Board usage limits are fixed by the module form
factor while others are established by system processing. Below is a list by board type
and the maximum number of boards allowed per VPI system. This list has Vital boards
presented first and non-vital boards last.
B.2.1
Vital Boards
Table B–1. VPI Vital Board Limitations (Cont.)
Board Type
CPU
CPU/PD
CPU and PD or CPU/PD
1 board each/system
1 board/system
VRD
1 board/system
1 board/system
I/O Bus Interface
14 Vital addresses per/Vital
I/O group
1 board/Vital I/O group
4 maximum/system
1 board/Vital I/O group
Vital Inputs (all types)
16 Inputs/board
1 Vital Address/board
10 boards/system
20 boards/system
Vital Timer
8 Field-settable
Timers/board
1 Vital Address/board
2 boards/system
2 boards/system
Vital Outputs (all types)
8 Outputs/board
1 Vital Address/2 boards
16 boards/system
40 boards/system
P2086B, Volume 1, Rev. D, Nov/13
B–1
Alstom Signaling Inc.
VPI Capacity Guidelines
Table B–1. VPI Vital Board Limitations (Cont.)
Board Type
CPU
CPU/PD
VSC (Note 4)
4 boards/system
4 (10) boards/system #GVSC -#MVSC - #CRG
MVSC, GVSC (Note 4)
N/A
2 boards per system
(4 (10)VSC and
MVSC/GVSC and CRG
max.)
CRG (Note 4)
N/A
3 boards/system
B.2.2
Non-Vital Boards
Table B–2. VPI Non-Vital Board Limitations
Board Type
CPU
CPU/PD
CSEX1or CSEX3
4 boards/system
Non-Vital I/O (including
TWC boards)
20 boards/CSEX subsystem 20 boards/CSEX subsystem
TWC
4 boards/CSEX subsystem
4 boards/CSEX subsystem
TWC Attenuator
1 board/CSEX subsystem
1 board/CSEX subsystem
NVTWC Modem
NVTWC Multiplexer
NVTWC FSK
8 boards of these
combinations/CSEX
subsystem
8 boards of these
combinations/CSEX
subsystem
P2086B, Volume 1, Rev. D, Nov/13
B–2
4 boards/system
Alstom Signaling Inc.
VPI Capacity Guidelines
B.2.3
Application Criteria
Table B–3. VPI Application Criteria
Board Limits
CPU
CPU/PD
Vital Equation size per system
800 Boolean equations
(Quantity dependent upon average
expression complexity)
2000 to 3000 Boolean
equations
Maximum product terms/Vital
equations
63
63
Maximum parameters/product
terms
63
63
Vital Software Timers
100 per system
300 per system
CPU-to-VSC Parameters
200 per VSC subsystem
200 per VSC subsystem
VSC-to-CPU Parameters
200 per VSC subsystem
200 per VSC subsystem
CPU/PD-to-GVSC Parameters
N/A
450 per GVSC
subsystem
GVSC-to-CPU/PD Parameters
N/A
450 per GVSC
subsystem
CPU/PD-to-MVSC Parameters
N/A
450 per MVSC
subsystem
MVSC-to-CPU/PD Parameters
N/A
450 per MVSC
subsystem
CPU/PD-to-CRG Parameters
N/A
80 per CRG subsystem
CRG-to-CPU/PD Parameters
N/A
8 per CRG subsystem
CPU-to-CSEX Parameters
800 per CSEX
subsystem
800 per CSEX
subsystem (See Note 5)
CSEX-to-CPU Parameters
(See Note 3)
400 per CSEX
subsystem
400 per CSEX
subsystem
Non-Vital Equation size
1500 per CSEX1
subsystem
4000 per CSEX3
subsystem
1500 per CSEX1
subsystem
4000 per CSEX3
subsystem
Non-Vital Software Timers
200 per CSEX
subsystem
200 per CSEX
subsystem
P2086B, Volume 1, Rev. D, Nov/13
B–3
Alstom Signaling Inc.
VPI Capacity Guidelines
Note 1: The CPU/PD board cannot simultaneously use all features at
maximum limits. Therefore, when planning for system capacity,
you must consider processing time, plus application EPROM
and system RAM limits.
Note 2: References to CSEX indicate any of the CSEX1 or CSEX3
boards.
Note 3: System-wide limit of 759 CSEX-to-CPU
independent of distribution on CSEX boards.
parameters
Note 4: Starting with CAA 31746-026, this limit is 10 minus (#MVSC +
#GVSC + #CRG). Also dependent on #CSEX boards, see
Appendix G for details
Note 5: Starting with CAA 31746-023K, -030B and up, 1600 parameters
per CSEX subsystem.
P2086B, Volume 1, Rev. D, Nov/13
B–4
Alstom Signaling Inc.
Module Wiring and Special Tools
APPENDIX C – MODULE WIRING AND SPECIAL TOOLS
Some VPI racks may have connections from the entrance racks to the rear plane of the
VPI Module made as direct wiring and not with wires terminated in plug couplers. Over
time perhaps some of the wires may have been pulled on, leaving the wires either loose
or pulled out of the crimp terminal. Should this be the case, 16-20 gauge wires can be
reattached to the module with the proper size terminals and crimping tools.
Figures C-1, C-2 and C-3 show the back plane of the module and required tools. Figure
C-4 shows how to use the pin and socket extraction tool when working with 14-, 28-, 50and 75-way plug couplers (receptacles). Refer to P2086B Vol. 4 for a complete
reference to wiring and special tools.
DIRECT WIRE
TOENTRANCE RACK
MOTHERBOARD
EXPANSION BUS CABLE
BACK PANEL
DIRECT WIRE
TOENTRANCE RACK
SYSTEMBUS
JUMPER CABLE
DISCRETE WIRING
PLUGCOUPLER
Figure C–1. Direct Wiring Option on Rear Plane of VPI Module
P2086B, Volume 1, Rev. D, Nov/13
C–1
Alstom Signaling Inc.
Module Wiring and Special Tools
CONNECTOR PIN
(NOT TO SCALE)
CONTACT AREA
ALSTOM TERMINAL & WIRE REFERENCE
AMP TOOL
PART #
90285-1
TERMINALS
PART NO.
WIRE SIZE
(AWG.)
COLOR
CODE
55871-145
16-20
WHITE
WIRE
CRIMP
STRAIN RELIEF
CRIMP
LOCKING
DETENT
Figure C–2. Terminal Crimp Tool
ALSTOM PART NUMBER
AMP PART NUMBER
59688-048-00
91073-1
Figure C–3. Terminal Extraction Tools
P2086B, Volume 1, Rev. D, Nov/13
C–2
Alstom Signaling Inc.
Module Wiring and Special Tools
Figure C–4. Pin and Socket Extraction Tool
P2086B, Volume 1, Rev. D, Nov/13
C–3
Alstom Signaling Inc.
Module Wiring and Special Tools
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
C–4
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
APPENDIX D – ALSTOM VPI APPLICATION DESIGN AND
TEST POLICY
P2086B, Volume 1, Rev. D, Nov/13
D–1
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–2
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–3
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–4
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–5
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–6
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
P2086B, Volume 1, Rev. D, Nov/13
D–7
Alstom Signaling Inc.
Alstom VPI Application Design and Test Policy
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
D–8
Alstom Signaling Inc.
Circuit Board Keying
APPENDIX E – CIRCUIT BOARD KEYING
All circuit boards used in the VPI system are mechanically keyed to a specific slot in the
VPI module.
SECONDARY
SIDE
Figure E-1. Registration Keying of Circuit Board
P2086B, Volume 1, Rev. D, Nov/13
E–1
Alstom Signaling Inc.
Circuit Board Keying
Figure E-2. Registration Keying Numbering
Note 1: Spaces 1 through 11 only are used for registration.
Note 2: Insert plug (01097-027), narrow end first as far as it will go into
keying plug slot.
Note 3: Minimum finger dimension after slotting -0.050 inch.
Note 4: Numbering shown from secondary side. P1 and P3 not shown.
Note 5: Keying slots to be milled in per dimensions shown.
Note 6: Code indicates the location of keys. See registration code chart.
P2086B, Volume 1, Rev. D, Nov/13
E–2
Alstom Signaling Inc.
Circuit Board Keying
Vital and Non-Vital PC board keying information is provided in the table below.
Table E–1. Vital and Non-Vital PC Board Keying Information (Cont.)
Board Type
Keying Code
CPU (59473-742-01 to 04, 08,09)
2-5
CPU/PD (31166-029-01, 02,10,11)
2-4-5
VRD (59473-740-01, 02)
3-4
VSC (59473-939-01, 03-06)
2-8
VSC (59473-939-02)
2-9
IOB (59473-736-01, -827-01)
2-3
DI (59473-738-01, -867-01,02)
1-2
DI (59473-867-03)
1-8
SBO (59473-739-01)
1-3
DBO (59473-747-01, -02)
1-4
DBO (59473-747-03)
4-8
DBO-50V (59473-977)
2-10
LDO (59473-749-01,02,03,04)
1-5
ACO (59473-937-01,02)
1-10
FSVT (59473-748,-894-01,02)
3-6
CSE (59473-741-01 to 10)
3-5
CSEX1 (59473-938-01)
1-11
CSEX3 (31166-175-01)
1-3-5-7-8-11
NVI (59473-757-02)
1-6
NVI (59473-757-03)
2-6
NVI (31166-106-02)
6-9
NVID (31166-106-01)
5-9
NVO (59473-785-01, -03)
1-7
NVO (59473-785-02, -04, -05)
2-7
NVOAC (59473-936-01,02)
1-9
NVO-SNK (31166-123-01)
1-4
NVRELAY (31166-238-01)
7-9
NVRELAY (31166-238-01)
7-10
TWCMAIN (59473-996-01)
4-6
P2086B, Volume 1, Rev. D, Nov/13
E–3
Alstom Signaling Inc.
Circuit Board Keying
Table E–1. Vital and Non-Vital PC Board Keying Information (Cont.)
Board Type
Keying Code
TWCMAIN (59473-996-02)
3-9
TWCATT (31166-021-01)
4-5
TWCATT (31166-021-02)
3-11
TWCATT (31166-021-03)
5-6
NVTWC-MOD (31166-099-02)
6-8
NVTWC-MUX(31166-100-01)
5-10
NVTWC-FSK(31166-119-02, 03, 04)
6-11
CRG (31166-261-01, -03)
2-11
CRG (31166-261-02, -04)
3-10
P2086B, Volume 1, Rev. D, Nov/13
E–4
Alstom Signaling Inc.
Signature Headers and PROMs
APPENDIX F – SIGNATURE HEADERS AND PROMS
This appendix provides VPI circuit boards Signature Header and PROM information.
Address Signature Headers (for Vital inputs and I/O Bus boards) have assigned
signature letters, summarized in Table F–1.
Table F–1. Address Signature Headers
Address Signature Header Drawing
Number
Address Signature Letter
59473-871-01
A
59473-871-02
B
59473-871-03
C
59473-871-04
D
59473-871-05
E
59473-871-06
F
59473-871-07
G
59473-871-08
H
59473-871-09
I
59473-871-10
J
59473-871-11
K
59473-871-12
L
59473-871-13
M
59473-871-14
N
59473-871-15
O
59473-871-16
P
P2086B, Volume 1, Rev. D, Nov/13
F–1
Alstom Signaling Inc.
Signature Headers and PROMs
Address Signature PROMs for all Vital output boards except LDO2 are provided in
Table F–2.
Table F–2. Signature PROMs
Signature
Number
(Vital
Output
Signature
Board
PROM Drawing
Number)
Number
Selectable
Signature
PROM Switch
Settings
tens
ones
Signature
Number
(Vital
Output
Signature
Board
PROM Drawing
Number)
Number
Selectable
Signature
PROM Switch
Settings
tens
ones
1
39780-003-01
0
1
21
39780-003-21
2
1
2
39780-003-02
0
2
22
39780-003-22
2
2
3
39780-003-03
0
3
23
39780-003-23
2
3
4
39780-003-04
0
4
24
39780-003-24
2
4
5
39780-003-05
0
5
25
39780-003-25
2
5
6
39780-003-06
0
6
26
39780-003-26
2
6
7
39780-003-07
0
7
27
39780-003-27
2
7
8
39780-003-08
0
8
28
39780-003-28
2
8
9
39780-003-09
0
9
29
39780-003-29
2
9
10
39780-003-10
1
0
30
39780-003-30
3
0
11
39780-003-11
1
1
31
39780-003-31
3
1
12
39780-003-12
1
2
32
39780-003-32
3
2
13
39780-003-13
1
3
33
39780-003-33
3
3
14
39780-003-14
1
4
34
39780-003-34
3
4
15
39780-003-15
1
5
35
39780-003-35
3
5
16
39780-003-16
1
6
36
39780-003-36
3
6
17
39780-003-17
1
7
37
39780-003-37
3
7
18
39780-003-18
1
8
38
39780-003-38
3
8
19
39780-003-19
1
9
39
39780-003-39
3
9
20
39780-003-20
2
0
40
39780-003-40
4
0
P2086B, Volume 1, Rev. D, Nov/13
F–2
Alstom Signaling Inc.
Signature Headers and PROMs
The figure below shows the Selectable Signature PROM assembly. The locations of key
reference points are indicated to assist in installing and configuring the device. The
figure shows the selection of “01” to be installed on the first Vital output board of a
system.
Pin 1
Tens
Switch
Ones
Switch
Figure F–5. Selectable Signature PROM Assembly
Note 1 This assembly is designed to replace a 16-pin integrated circuit
that is installed in a Vital output board of a VPI system. The
Alstom drawing numbers of these integrated circuits are listed in
the table above under the heading “Signature PROM Drawing
Number” .
Note 2 The location and orientation of the 16-pin socket where this
assembly is to be installed varies for the different board types.
Be careful to observe the location of Pin 1 when installing this
assembly.
Note 3 This assembly should be handled carefully as damage to the 16
machined pins may result. While the pins on this assembly are
quite strong, they are made of a material that cannot be bent
often without breaking.
P2086B, Volume 1, Rev. D, Nov/13
F–3
Alstom Signaling Inc.
Signature Headers and PROMs
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
F–4
Alstom Signaling Inc.
Allowable VSC/CSEX Board Combinations
APPENDIX G – ALLOWABLE VSC/CSEX BOARD
COMBINATIONS
The following board placement rules are applicable for the VPI CAA 31746-026 and
later.
Table G–1. Board Placement Rules (Cont.)
Total Number
of VSC Type
Boards
Allowable
CSEX Boards:
System
Module
Allowable
CSEX Boards:
Extender
Module
0
4
4
-
-
1
4
4
1
0
4
4
0
1
4
4
2
0
4
4
1
1
4
4
0
2
4
4
3
0
4
4
2
1
4
4
1
2
4
4
0
3
4
4
4
0
4
4
3
1
4
4
2
2
4
4
1
3
4
4
0
4
3
4
5
0
4
4
4
1
4
4
3
2
4
4
2
3
4
4
1
4
4
3
0
5
2
3
4
5
P2086B, Volume 1, Rev. D, Nov/13
G–1
Allowable VSC Allowable VSC
type Boards:
type Boards:
System
Extender
Module
Module
Alstom Signaling Inc.
Allowable VSC/CSEX Board Combinations
Table G–1. Board Placement Rules (Cont.)
Total Number
of VSC Type
Boards
Allowable
CSEX Boards:
System
Module
Allowable
CSEX Boards:
Extender
Module
6
2
4
6
0
3
4
5
1
4
4
4
2
4
4
3
3
4
4
2
4
4
3
1
5
4
2
0
6
1
4
7
0
2
4
6
1
3
4
5
2
4
4
4
3
4
4
3
4
4
3
2
5
4
2
1
6
4
1
0
7
0
4
8
0
1
4
7
1
2
4
6
2
3
4
5
3
4
4
4
4
4
3
3
5
4
2
2
6
4
1
1
7
4
0
0
8
7
8
P2086B, Volume 1, Rev. D, Nov/13
G–2
Allowable VSC Allowable VSC
type Boards:
type Boards:
System
Extender
Module
Module
Alstom Signaling Inc.
Allowable VSC/CSEX Board Combinations
Table G–1. Board Placement Rules (Cont.)
Total Number
of VSC Type
Boards
Allowable
CSEX Boards:
System
Module
Allowable
CSEX Boards:
Extender
Module
9
0
4
8
1
1
4
7
2
2
4
6
3
3
4
5
4
4
3
4
5
4
2
3
6
4
1
2
7
4
0
1
8
0
4
8
2
1
4
7
3
2
4
6
4
3
3
5
5
4
2
4
6
4
1
3
7
4
0
2
8
10
P2086B, Volume 1, Rev. D, Nov/13
G–3
Allowable VSC Allowable VSC
type Boards:
type Boards:
System
Extender
Module
Module
Alstom Signaling Inc.
Allowable VSC/CSEX Board Combinations
In the following table, # represents the total number of a particular board type.
VSC Type Board
Maximum Allowable VSC Type Boards
Total VSC type boards
10
Vital Serial Communications (VSC)
10 – (#MVSC + #GVSC + #CRG)
Multidrop Vital Serial Communications
(MVSC)
2 – #GVSC
Genrakode Vital Serial Communications
(GVSC)
2 – #MVSC
Code Rate Generator (CRG)
3
P2086B, Volume 1, Rev. D, Nov/13
G–4
Alstom Signaling Inc.
CRG Application Guidelines
APPENDIX H – CRG APPLICATION GUIDELINES
H.1
GENERAL OVERVIEW
The VPI Code Rate Generator (CRG) Board, 31166-261, is a Vital output board
developed for use in a VPI system. CRG outputs (ports) are requested by CPU/PD via
direct Vital serial communications rather than through the motherboard and I/O Bus.
CRG responds back to CPU/PD with port status indications and port recheck data. The
CPU/PD board can communicate with a maximum of three CRG boards to produce cab
code rates from within the VPI system. Each CRG board contains eight Vital outputs.
Each output on the Group 1 and Group 3 CRG boards is used to interface to a solid
state relay load. The Group 4 CRG board is used to interface to a Vital Code Following
Relay. The CAAPE is used to configure the CRG boards within the system and to define
the application parameters.
The port status indications from CRG are nonvital and indicate whether the CRG
outputs have been commanded to generate the code rates as requested by the
CPU/PD application logic. The port status indication is true if the CRG is able to
properly decode the code rate request from CPU/PD and the application logic has
requested only one valid rate that is supported by the CRG.
Power to the CRG outputs is controlled by the VPI resident VRD. CRG generates port
recheck data via AOCD and transmits the result to CPU/PD every 250 milliseconds.
CPU/PD uses this information in the formation of recheck checkwords for VRD. If the
CRG fails to generate the proper data, VRD will de-energize thus turning off all Vital
outputs.
H.2
APPLICATION PARAMETERS
The CAAPE is used to configure the control and indication parameters for CRG
application. The following table defines the parameters for turning on the CRG outputs.
Each of the eight outputs is assigned ten parameters according to these definitions.
P2086B, Volume 1, Rev. D, Nov/13
H–1
Alstom Signaling Inc.
CRG Application Guidelines
H.3
CPU/PD TO CRG PARAMETERS
Table H–1. CPU/PD to CRG Parameters
Parameter Number
CRG GR. 1 and 3
CRG GR. 4
1
0
0
2
50 ppm
50 ppm
3
75 ppm
75 ppm
4
120 ppm
120 ppm
5
180 ppm
180 ppm
6
spare
270 ppm
7
spare
420 ppm
8
spare
ON
9
spare
spare
10
spare
spare
The following table defines the port status parameters from CRG. For each CRG board,
there are eight parameters assigned according to these definitions.
Table H–2. CRG to CPU/PD Parameters
Parameter Number
Definition
1
Port 1 status
2
Port 2 status
3
Port 3 status
4
Port 4 status
5
Port 5 status
6
Port 6 status
7
Port 7 status
8
Port 8 status
P2086B, Volume 1, Rev. D, Nov/13
H–2
Alstom Signaling Inc.
CRG Application Guidelines
H.4
INSTALLATION AND OPERATION
The CRG board may be placed in any slot of any module, of the VPI system, that is not
on the P1 system bus. The CRG P1 connector provides the multidrop 4-wire
communications with CPU/PD and provides the board identification (board ID) wire
jumpers. The board ID jumpers are assigned by the VPI CAA and are listed in the
compiler-generated LVC report under the board report (shown as address wiring) and
wire table sections. Application Engineering assigned cable numbers 55816-065-01 or
55816-065-02 as the cable between CRG and CPU/PD. This cable provides for the
communications and the wire jumpers, however it can restrict the placement of the CRG
board within the system. The CRG P2 connector provides +5V and 5VCOM to the
board. The CRG P3 connector provides the eight 2-wire outputs and the Vital power
input. Application Engineering assigned cable number 55816-064-81. The required Vital
power is +8V to +16V through a front contact of the VPI VRD relay, or a repeater. This
allows VPI to shut off the CRG outputs due to failure. VPI requires correct validation of
CRG outputs, as well as all other VPI Vital outputs, in order to energize VRD.
H.5
CPU/PD REQUIREMENTS
The CPU/PD board contains DIP switch S2 for configuring the HHT serial
communications and the CRG serial communications, see Figure 9-26 in section 9 of
this manual. The RXD1 and CTS1 must be set to differential in order to make the
communications connections between CRG and CPU/PD.
The CPU/PD board supports single or multiple CRG boards in a system, per VPI CAA
31746-026 and later. In order to support CRG, the CPU/PD board requires
modifications. The differential serial communication receive lines require a pull-up/pulldown configuration. Modification drawing MD31166-029-26 provides details about
adding two wires to the CPU/PD board if it is not already equipped.
H.6
TERMINAL BLOCK CONFIGURATION
Terminal Block
Pins Shunted
Definition
TB7
None
Shunt on pins 1-2 for HHT
operation. HHT
configuration is not currently
supported in the
diagnostics.
TB9
2-3 or None
Watchdog Time Delay
TB10
1-2
Watchdog jumper
other
None
P2086B, Volume 1, Rev. D, Nov/13
H–3
Alstom Signaling Inc.
CRG Application Guidelines
H.7
DISPLAYS AND DIAGNOSTICS
Figure 9-7, in section 9 of this manual, depicts the front edge of the CRG board.
Included are two 7-segment displays. During normal operation, the top display indicates
the port number, 1 through 8, (selected from the on-board rocker switch) and the bottom
display indicates the requested code rate. The code rate consists of a dash (-) and three
code rate digits, scrolling at a 1-second rate. The dash indicates the start of the code
rate display. Additional displays are as follows:
Table H–3. CRG Board Display and Diagnostics (Cont.)
Display
Diagnostics
The display of 'P'/'U' (power-up) indicates CRG is awaiting program
verification from CPU/PD. This occurs during start-up for initialization.
Each CRG output defaults to 0ppm code rate. This display also indicates
code rate command messages are received from CPU/PD, serial
communications are active. This display is not supported in the 40025313 CRG software.
The display of 'P'/blank indicates the program verification is not valid.
This may result from any of the following:
The software resident on the CPU/PD (U16, U17, U18, U19) and CRG
(U23) are not compatible. One, or both, may be the improper version.
The VRD may energize.
The software resident on the CRG (U23, U13, U19) are not compatible.
Any may be the improper version. The VRD will not energize.
The CRG board ID is not configured properly.
This display also indicates code rate command messages are received
from CPU/PD, serial communications are active. However, the code rate
data is invalid. Each CRG output defaults to 0ppm code rate.
P2086B, Volume 1, Rev. D, Nov/13
H–4
Alstom Signaling Inc.
CRG Application Guidelines
Table H–3. CRG Board Display and Diagnostics (Cont.)
Display
Diagnostics
The display of '.'/blank indicates the CRG board is running, but there is
no recheck communication between CPU/PD and CRG. Each CRG
output defaults to 0ppm code rate. This may result from any of the
following:
The CPU/PD board is reset.
Improper serial communication cable connection between CPU/PD and
CRG boards.
CPU/PD switch S2 is not set properly.
If CPU/PD board is running, verify CRG data in CPU/PD Report is
correct. If information is not shown, verify CPU/PD switch S2 is set as
shown in Figure 9-26, see section 9 of this manual. Verify the system
software version on the CPU/PD board (U16, U17) is the same as that
expected by the VPI compiler and application (U18, U19). The CPU/PD
diagnostic may show a 'MAIN CWD #0F' error message if the software
versions are not compatible. VRD will be de-energized.
The display of r/F indicates a failure during the CRG RAM test at powerup. Diagnostic messages are posted to the terminal to indicate the failure
mode.
The display of d/F indicates a failure during the CRG Polynomial Divider
test at power-up. Diagnostic messages are posted to the terminal to
indicate the failure mode.
P2086B, Volume 1, Rev. D, Nov/13
H–5
Alstom Signaling Inc.
CRG Application Guidelines
Table H–3. CRG Board Display and Diagnostics (Cont.)
Display
Diagnostics
The display of 8./8. indicates the CRG board has undergone a reset. The
display continuously flashes under any of the following conditions:
The watchdog jumper TB10 is not connected
The User Interface FPGA U25 is not programmed
The system software device U23 is not programmed.
P2086B, Volume 1, Rev. D, Nov/13
H–6
Alstom Signaling Inc.
CRG Application Guidelines
A VT100 configured at 9600 baud, 8 data bits, 1 stop bit, no parity may be connected to
the CRG MAC port. The CRG will indicate board configuration during start-up. There
are also diagnostic commands that can be entered for software report, board ID and
jumper assignments. The available commands are shown in the following table:
Command
Definition
DCR
Display Code Rates - Displays the code rate
transmitted by each port. This information is updated
once per second if valid code rate command
messages are received from CPU/PD. The displayed
rates for a port will be zero under the following
conditions:
Zero rate is requested from CPU/PD
More than one rate (for a port) is requested from
CPU/PD
A non-supported rate (spare) is requested from
CPU/PD
CRG is unable to decode a valid rate. This may be
due to incompatible software versions between CRG
and CPU/PD. The 7-segment displays should show
'P'/blank.
DID
Display ID - Displays the board ID and jumper
configuration read by the CRG board
MEM
Memory Monitor - Allows the query of internal RAM
buffers
RPT
Configuration Report - Displays board resident
software revision
?
Command Summary - Displays a list of the
available diagnostic commands
The CPU/PD report now includes records for the software revision of each CRG board
configured in the system. This information is the same information displayed using the
CRG configuration report command and is transmitted to CPU/PD during start-up.
P2086B, Volume 1, Rev. D, Nov/13
H–7
Alstom Signaling Inc.
CRG Application Guidelines
THIS PAGE INTENTIONALLY LEFT BLANK.
P2086B, Volume 1, Rev. D, Nov/13
H–8
Alstom Signaling Inc.
FOR QUESTIONS AND INQUIRIES, CONTACT CUSTOMER SERVICE AT
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OR
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ALSTOM SIGNALING INC.
1025 JOHN STREET
WEST HENRIETTA, NY 14586