Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
Evaluation of Sense Amplifier Flip-Flop with
Completion Detection Signal
Sushmita M.G
M.Tech VLSI Design and Embedded Systems
Department of ECE
R. V. College of Engineering®, Bengaluru-59
Email: sushmitagogi@gmail.com
Abstract— Sense amplifier is a part of read circuitry used to
read data from memory. It amplifies the low voltage signals to
high logic level signal. It has wide range of applications such as
in memory storage, level shifter and bus driver. This paper
explains the design of Sense Amplifier based flip flop (SAFF)
with control signal as Transition Completion Detection (TCD).
The flip flop (FF) is designed in gpdk180nm technology and
simulated using Cadence tool. Performance analysis of
Conventional SAFF, Power PC master slave flip flop and
SAFF with control signal TCD are compared in terms of delay,
power and power delay product. Power for different value of
voltage is compared for designed FF. Simulation results show
that, 6% reduction of power for Sense amplifier FF with
control signal TCD compared to Power PC Master slave FF at
1 volt supply voltage. Compared to Conventional SAFF,
designed SAFF with control signal TCD reduces clock to Q
delay about 4.7%. To analyze the working operation of SAFF
with control signal TCD, a new circuit proposed and is
designed using 2:1 multiplexer. Simulation result shows that,
power and clock to Q delay of designed circuit are in the order
of 26.87 µwatt and 30.23 nsec respectively.
Keywords— Sense Amplifier based Flip Flop (SAFF), Flip
Flop (FF), Memory, Level shifter.
I.
INTRODUCTION
With the development of VLSI technology, day by day
market trends keeps on expanding. Reduction of power in
the portable devices has become primary concern. Power
minimization is becoming a challenging task on each and
every individual [1]. For example like mobile phone, laptop,
tablet devices are equipped with battery system, reduction of
power becomes important issue in the battery operated
systems. With the advancement in technology, new
designed circuit dissipates more power. Several
conventional techniques are proposed to reduce the power
dissipation but there is an increase in the demand for low
power CMOS design. In sequential logic, flip flop is the
used as a storage element in digital camera, mobile phones,
computers memory. But more amount of power is consumed
by flip flops. Thus, the design of flip flops with low power
and small delay is necessary. Conventional SAFF suffers
from the two problems, first one is dependency of Q delay
on Qb delay and second one is wrong data may latched by
sense amplifier stage. To solve the problems of conventional
sense amplifier, a new circuit is designed with control
signal. In this paper, design of SAFF with control signal
TCD is designed using gpdk180nm technology and
implemented using Cadence tool. Performance analysis of
conventional SAFF, Power PC FF and SAFF with control
Prof. Sowmya K.B
Assistant Professor, Department of Electronics
and Communication Engineering
R. V. College of Engineering®, Bengaluru-59
Email: sowmyakb@rvce.edu.in
signal TCD are compared in terms of clock to Q delay,
power and power delay product. SAFF with control signal
TCD is designed using two technologies (gpdk45nm and
gpdk180nm) and performance analysis is compared for the
FF. New design is proposed to analyze the working
operation of Sense Amplifier flip flop with control signal
TCD using multiplexer. Proposed design is implemented
using Cadence tool.
The paper is organized as follows- In Section II literature
survey related to the previous work is reviewed. Section III
explains the working of conventional SAFF, Power PC FF
and SAFF with control signal TCD circuit are discussed. In
Section IV Evaluation of SAFF with control signal using
multiplexer is presented. In Section V, simulation results of
designed flip flop and comparison of obatined results are
discussed. Conclusion is discussed in Section VI.
II. LITERATURE SURVEY
This section gives the information about previous work
related to the SAFF.
Hanwool Jeong [2], proposed a new design of Sense
amplifier based flip flop with TCD. The FF is implemented
using 22nm FinFET technology. In this paper, parameters
like energy consumption, speed, operation yield, area and
hold time of circuits are compared. The proposed SAFF
with TCD operates two times faster in speed compared to
master slave FF at 0.3-0.4 volt. Anoop D [3] proposed a
sense amplifier flip flop. Proposed FF is implemented using
180nm technology. In this paper, designed SAFF is
compared with conventional SAFF in terms of power, PDP,
rise and fall delay. The proposed SAFF design shows,
improvement in the delay and power delay product and are
in the order of 95 ps and 39 fJ. In [4], a Sense Amplifier
based FF implemented using 0.25µ technology. Devisha
Gupta [5], describes the design of S R and Nikolic SAFF.
Designed circuits are implemented using 90 nm CMOS
technology. In this paper, parameters like power dissipation
and delay for the designed slave latch are compared at 1V
supply voltage. Simulation result shows that, delay and
power dissipation of Nikolic slave latch is less compared to
SR latch. Antonio G [6], presented a new design of sense
amplifier based flip flop implemented using 0.25µm
technology. The proposed flip-flop provides reduced power
dissipation and glitch-free circuit operation. Simulated result
shows that, improvement in the delay and the power
dissipation.
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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
III. FLIP FLOPS DESIGN
A. Conventional Sense Amplifier based Flip-Flop
Sense amplifier based flip flop consists of two stage SA
stage and NAND based SR latch. Schematic diagram of
SAFF as shown in Fig. 1. Conventional SAFF is designed
and simulated using Cadence tool (180nm technology).
When clock input clk is low state, P1 and P4 transitors are
turned ON. Both Sb and Rb node are precharged to VDD and
N1 and N2 transistors are turned OFF. During this state
transistors P2 and P3 are OFF latch satage holds the flip flop
state. N6 transistor is similar to evaluate switch in dynamic
circuits and is turned OFF when clock signal is low. For
high clock input signal, N6 transistor turns ON and data
input is zero then differential input pair (N3 and N4) is
enabled. Difference between the input signal is amplified on
the output nodes on Sb and Rb. Differential input pair N3 is
turned OFF and N4 are turned ON. Then one of the node (Sb
or Rb) is 0 and the other node remains at VDD. Output Q and
Qb becomes one and zero during high phase of clock signal
and data input is zero. Output waveform of SAFF is shown
in Fig. 5.1.
FF consists of two latches in the circuit and are master and
slave latch. Main advantages of this FF are having a low
latency path and power keeper structure [9].
Fig. 2: Schematic circuit of Power PC Master Slave FF
When input clock signal is zero, master latch is enabled and
slave latch is in hold mode. Transistors MN3 and MP3 are
ON and MP2, MN2 are OFF output retains its previous
value. When clock signal is high, slave latch is enabled
transistors MP6 and MN6 are turned ON. Transistors MN5
and MP5 are turned OFF, value stored will be propagated to
the output node through slave stage. The drawback of this
FF is data to Q delay of FF is large due to its positive value
of setup time [8], [11], [12]. Output waveform of Power PC
master slave flip flop is shown in Fig. 5.2.
C. Sense Amplifier based flip flop with control signal TCD
In this section, working operation of SAFF is discussed. It is
modified circuit of conventional SAFF. The designed
circuit, solve the problems of previous Sense amplifier
based flip flop. The designed circuit uses control signal
TCD signal to indicate the transition completion of sense
amplifier stage. Circuit diagram of designed SAFF with
control signal TCD [2] is shown in Fig. 3.1. Control signal
Transition Completion (TC) is generated by NAND gate and
inputs to the gate are Sb and Rb.
Fig. 1: Schematic circuit of Conventional SAFF
The shorting of transitor N5 is drived by V DD and it
provides static operation by guaranteeing a pull down path
for either Sb or Rb and provides leakage path. Simulation
results and output waveform of designed FF are shown in
Fig. 5.1. The main advantage of SAFF is near zero setup
time. The drawback of conventional SAFF [7] is high clock
to Q delay due to its slow operation of the slave latch stage.
B. Power PC Master Slave Flip-Flop
Power PC is an example of static structures. Schematic
circuit of Power PC master slave flip flop is shown in Fig. 2.
When clock signal and data input are low, transistors MP1
and MP4 are turned ON, both Sb and Rb are charged to high
which makes TC signal low. Due to data input is zero, MN2
transistor is turned OFF and MN3 is turned ON. TC signal
will turn OFF transistors MN 4, MN8 and MN11. Transistor
MP5 is turned OFF then output Q will be zero. At the rising
edge of the clock, evaluate transistor MN1 turns on and
differential input pair (MN2 and MN3) is enabled.
Difference between the input signal is amplified on the
output nodes on Sb and Rb. One of Sb or Rb becomes low
which makes NAND gate output (TC signal) to be high.
Then transistors MP5 and MN8 are turned ON. MP5
transistor is charged to VDD then it is discharged to zero
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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
through transistor MN8. Output Q becomes zero, this will
turn on transistor MP7 and output Qb becomes one. It
indicates that output depends on data input value that is
when clock input is high and data input is zero then output
Q becomes zero.
modified circuit of SAFF for glitch protection is shown in
Fig. 5.4.
SAFF with control signal TCD is designed using
gpdk180nm and gpdk45nm technologies. Schematic circuit
designed in gpdk45nm is similar to gpdk180nm technology.
Output waveform of both design are shown in Fig. 5.3 and
Fig. 5.5. TC signal is connected to transistor MN4 and it will
turn ON MN4 transistor after the transition of SA stage.
Thus the designed circuit is free from reduction in the speed
of operation. The designed FF improves the performance of
the FF. Simulation results of the designed FF are listed in
Table IV. In gpdk180nm technology, NMOS and PMOS
transistors W/L ratio are 2µm/180 nm and 4 µm/180 nm.
Fig. 3.2: Schematic circuit of SAFF with control signal TCD for glitch
protection
IV. EVALUATION OF SENSE AMPLIFIER BASED FLIPFLOP WITH CONTROL SIGNAL TCD USING
MULTIPLEXER
To analyze working operation of SAFF with control signal
TCD a new circuit is proposed and is designed using
multiplexer. The circuit consists of two blocks multiplexer
and SAFF with control signal. The Output of 2:1
multiplexer is given to the data input of SAFF with control
signal TCD and is shown in Fig. 4.1. Proposed circuit is
simulated using Cadence tool (gpdk180nm technology).
Schematic circuit of the design is shown in Fig . 4.3.
A
B
0 2:1 Y
Mux
1
S
D
SAFF with
control
signal TCD
CLK
Q
Qb
Clock
Fig. 4.1: Block diagram of SAFF with control signal TCD using
Multiplexer
Fig. 3.1: Schematic circuit of SAFF with control signal TCD
Glitch occurs in SAFF with control signal TCD in the
output nodes at falling edge of the clock. At the falling edge
of clock both TC and Sb are high, MN8 and MN7 transistors
are turned ON. This causes glitch in the output node Q.
Glitch in the pull-down paths of Q and Qb can be reduced
by adding clock gating NMOSs and circuit diagram of glitch
protection circuit is shown in Fig 3.2. Output waveform of
2:1 multiplexer consists of one select line and two inputs. If
select line input of multiplexer is zero then ‘A’ input is
selected otherwise ‘B’ input is selected and is shown in
Table I. Output Y of multiplexer is given to the designed
SAFF with control signal TCD. The designed FF works
similar to D flip flop. Output Y of 2:1 multiplexer is
represented as follows
Y= Sb.A + S.B
(1)
When select line of multiplexer is 1 then B input is selected
and is given to the data input D of the FF. Expression of
output Y is shown in Equation 1. When clock and data input
both are high then output Q of FF becomes one and Qb
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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
becomes zero. Output waveform of the designed circuit is
shown in Fig. 5.6. Schematic circuit of 2:1 multiplexer is
shown in Fig. 4.2.
TABLE I. TRUTH TABLE OF 2:1 MULTIPLEXER
Select
line S
0
0
1
1
Inputs
B
X
X
1
0
A
0
1
X
X
Output
(Y)
0
1
1
0
If select line is zero, ‘A’ input is selected and is given to
data input of the designed flip flop. Then data input value
becomes same as input ‘A’. Consider input ‘A’ is zero then
data input becomes zero. For high clock input, output Q
becomes zero. It works similar to the D flip flop.
Output waveform of conventional SAFF, Master slave FF,
SAFF with control signal TCD, modified circuit for glitch
protection and SAFF with control signal TCD designed
using multiplexer are shown in Fig. 5.1 to Fig. 5.6. Results
obtained from the simulation are listed in Table II-V.
A. Output waveform of designed flip flops
Output waveform of conventional SAFF, Power PC FF,
SAFF with control signal TCD and SAFF with control
signal using the multiplexer are shown in Fig. 5.1 to Fig.
5.6.
Fig. 5.1: Output waveform of Conventional SAFF
Fig. 4.2: Schematic circuit of 2:1 multiplexer using Static CMOS designed
using gpdk180nm technology
Fig. 5.2: Output waveform of Power PC Master Slave FF
Fig. 4.3: Schematic circuit SAFF with control signal using Multiplexer
V. SIMULATION RESULTS
The SAFF with transition completion detection,
conventional SAFF and Master slave FFs are designed using
gpdk180nm technology and simulated using Cadence tool.
For the transient analysis of designed circuit stop time of
120 nsec is considered.
Fig. 5.3: Output waveform of SAFF with control signal TCD
using gpdk180nm technology
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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
TABLE II. MEASURED CHARACTERISTICS OF DIFFERENT FLIPFLOP DESIGN
Average
Power(µwatt)
Parameter
Clock to Q
delay(ns)
Power Delay
Product(pJ)
Conventional
SAFF
14.07
25.23
0.354
Master slave FF
21.66
20.12
0.435
25.2
24.04
0.605
24.59
24.02
0.590
Circuit Name
SAFF with control
signal TCD
Modified SAFF for
glitch protection
Fig. 5.4: Output waveform of SAFF with control signal TCD
for glitch protection
From Table II, it is observed that SAFF control signal with
TCD consumes more power compared to master slave flip
flop at 1.8 volt supply voltage due to Q, Rb, Sb and TC
switched ON every clock cycle whereas in Master slave flip
flop circuit only CLK and CLKb switching takes place.
Clock to Q delay of designed FF with control signal TCD is
less compared to conventional SAFF [10]. Comparison of
power for different values of voltage is made and it is shown
in Table III.
TABLE III. COMPARISON OF POWER FOR DIFFERENT VALUE OF
VOLTAGE
Power(µwatt)
Conventional
SAFF
Power PC
Master Slave
FF
1
3.859
6.211
Modified circuit
of SAFF with
control signal
TCD
5.839
1.4
7.903
12.35
12.27
1.8
14.07
21.66
24.59
2.2
22.59
34.82
34.24
2.6
33.82
52.54
50.28
3
47.88
75.34
70.9
Voltage
(volt)
Fig. 5.5: Output waveform of SAFF with control signal TCD
using gpdk45nm technology
From the Table III, it is observed that power increases with
increases in voltage value. For supply voltage of 1 volt,
modified SAFF with control signal TCD consumes less
power compared to Master Slave FF and more power
compared to Conventional SAFF.
SAFF with control signal TCD is designed using gpdk45nm
and gpdk180nm technologies. Parameters like power and
delay are compared for designed FF. Results obtained from
the simulations are listed in Table IV.
Fig. 5.6: Output waveform of SAFF with control signal TCD
using Multiplexer
B. Result Analysis of designed flip flop
Performance analysis is carried out by doing transient
analysis of designed FF. Parameters like power, delay and
power delay product for the designed FF are compared and
are listed in Table II.
TABLE IV. COMPARISON OF PARAMETERS OF SAFF WITH
CONTROL SIGNAL TCD DESIGNED USING DIFFERENT
TECHNOLOGIES
Technology
gpdk45 nm
gpdk180 nm
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Average
Power(µwatt)
Parameter
Clock to Q
delay(ns)
Power Delay
Product(pJ)
0.1233
20.11
2.479*10-3
5.886
24.04
0.141
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Proceedings of the Third International Conference on Electronics Communication and Aerospace Technology [ICECA 2019]
IEEE Conference Record # 45616; IEEE Xplore ISBN: 978-1-7281-0167-5
From Table IV, it is clear that SAFF with control signal
designed using gpdk45nm technology requires less power
and clock to Q delay compared to circuit designed using
gpdk180nm technology.
Working operation of SAFF with control signal TCD
designed using multiplexer is discussed in section IV.
Multiplexer is designed using static CMOS method.
Simulation results of SAFF with control signal TCD using
multiplexer is listed in Table V.
TABLE V. MEASURED CHARACTERISTICS OF SAFF WITH
CONTROL SIGNAL TCD USING MULTIPLEXER
delay of the designed circuit are in the order of 26.87 µwatt
and 30.23 nsec respectively.
ACKNOWLEDGMENT
This project work is supported as part of major project for
M.Tech, VLSI Design and Embedded Systems Post
Graduate Program in the R. V. College of Engineering®,
Bengaluru - 560059.
REFERENCES
Sudha. H, Sahana Uppin “ Design of Low Power Flip flop using
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Engineering, vol. 5, Issue 5, May 2016.
[2] Hanwool Jeong, Tae Woo Oh, Seung Chul Song and Seong-Ook Jung
“Sense-Amplifier-Based Flip-Flop with Transition Completion
Detection for Low-Voltage Operation” IEEE Transactions on Very
Large Scale Integration Systems, 2018.
[3] Anoop D, Dr. Nithin Kumar Y.B, Dr Vasantha M. H “High
performance Sense Amplifier based Flip flop for driver applications”
IEEE International Symposium on Nano-electronic and Information
Systems, 2017.
[4] Borivoje. Nikolic, Vojin G. Oklobdzija, Michhael Ming Tak Leung
and James Kar Shing Chiu “Improved Sense Amplifier based flip
flop: Design and Measurements” IEEE Journal of Solid State Circuits,
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[5] Devisha Gupta, Rockey Bhardwaj “Performance Comparison of SR
and Nikolic Sense Amplifier based Energy Resumption Flip-Flops at
90nm CMOS Technology” Second International Conference on
Inventive Systems and Control, 2018.
[6] Antonio G. M. Strollo, Davide De Caro, Ettore Naoli and Nicola
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[7] A. Selvapandian “Design and Analysis of Power Efficient Sense
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[8] Krishnapriya K P, V. J. Arul Karthick “ analysis of Low Power flip
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[9] Kalarikkal Absel, Lijo Manuel and R K Kavitha “Low Power Dual
Dynamic Node Pulsed Hybrid Flip Flop Featuring Efficient
Embedded Logic” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, vol.21, no.9, September 2013.
[10] Yeo Kiat Seng, Goh Wang Ling, Lim Hoe Gee and Zhang Wenle “
New Conditional sampling Sense amplifier based flip flop for high
performance and low power application” IEEE international
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[11] Akila M, Sathiskumar M and Sukanya T “A Novel Analysis on Low
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[1]
Circuit Name
SAFF
with
control
signal
using
multiplexer
Average
Power(µwatt)
Parameter
Clock to Q
delay(ns)
Power Delay
Product(pJ)
26.87
30.23
0.812
From the Table V, it is observed that SAFF with control
signal TCD designed using multiplexer requires more power
and clock to Q delay compared to other FF designs as listed
in Table II.
VI. CONCLUSION
Sense amplifier based Flip Flop with control signal TCD
and modified circuit of SAFF with control signal TCD for
glitch protection are designed and simulated using Cadence
tool. Further, conventional SAFF and Power PC Master
Slave flip flop have been designed using gpdk180nm
technology and simulated using Cadence tool. Performance
analysis of designed FF is compared in terms of average
power consumption, clock to Q delay and power delay
product. Simulation is carried for different values of voltage
to understand the variation of power with respect to voltage.
For supply voltage of 1 V, SAFF with control signal TCD,
Power PC master slave flip flop and Conventional SAFF
consumes power in the order of 5.839 µwatt, 6.21 µwatt and
3.859 µwatt respectively. Simulation results show that,
compared to Power PC master slave flip flop, designed
SAFF with control signal TCD consumes less power and it
shows 6% reduction of power at 1V supply voltage. Clock
to Q delay of SAFF with control signal TCD reduced by
4.7% compared to conventional SAFF.
SAFF with control signal TCD is designed and simulated
using gpdk45nm and gpdk180nm technologies at 1V supply
voltage. Comparative analysis show that, FF designed using
gpdk45nm technology reduces power and clock to Q delay
compared to FF designed using gpdk180nm technology.
SAFF with control signal TCD using multiplexer is
designed and analyzed in terms of power and clock to Q
delay. Simulation result shows that, power and clock to Q
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