sensors
Article
A CMOS PSR Enhancer with 87.3 mV PVT-Insensitive Dropout
Voltage for Sensor Circuits
Jianyu Zhang
and Pak Kwong Chan *
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore;
zh0028yu@e.ntu.edu.sg
* Correspondence: epkchan@ntu.edu.sg; Tel.: +65-67904513
Citation: Zhang, J.; Chan, P.K. A
CMOS PSR Enhancer with 87.3 mV
PVT-Insensitive Dropout Voltage for
Abstract: A new power supply rejection (PSR) based enhancer with small and stable dropout
voltage is presented in this work. It is implemented using TSMC-40 nm process technology and
powered by 1.2 V supply voltage. A number of circuit techniques are proposed in this work. These
include the temperature compensation for Level-Shifted Flipped Voltage Follower (LSFVF) and the
Complementary-To-Absolute Temperature (CTAT) current reference. The typical output voltage and
dropout voltage of the enhancer is 1.1127 V and 87.3 mV, respectively. The Monte-Carlo simulation of
this output voltage yields a mean T.C. of 29.4 ppm/◦ C from −20 ◦ C and 80 ◦ C. Besides, the dropout
voltage has been verified with good immunity against Process, Temperature and Process (PVT)
variation through the worst-case simulation. Consuming only 4.75 µA, the circuit can drive load
up to 500 µA to yield additional PSR improvement of 36 dB and 20 dB of PSR at 1 Hz and 1 MHz,
respectively for the sensor circuit of interest. This is demonstrated through the application of an
enhancer on the instrumentation Differential Difference Amplifier (DDA) for sensing floating bridge
sensor signal. The comparative Monte-Carlo simulation results on a respective DDA circuit have
revealed that the process sensitivity of output voltage of this work has achieved 14 times reduction in
transient metrics with respect to that of the conventional counterpart over the operation temperature
range in typical operation condition. Due to simplicity without voltage reference and operational
amplifier(s), low power and small consumption of supply voltage headroom, the proposed work is
very useful for supply noise sensitive analog or sensor circuit applications.
Sensor Circuits. Sensors 2021, 21, 7856.
https://doi.org/10.3390/s21237856
Academic Editor: Alfio Dario Grasso
Keywords: PSR enhancer; regulator; dropout voltage; temperature compensation; current reference; voltage reference; FVF circuit; PVT variation; sensor circuit; Differential Difference Amplifier;
operational amplifier
Received: 1 November 2021
Accepted: 24 November 2021
Published: 25 November 2021
Publisher’s Note: MDPI stays neutral
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Copyright: © 2021 by the authors.
Licensee MDPI, Basel, Switzerland.
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distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
1. Introduction
With the continuous advancement of integrated circuit design and manufacturing
technology, sensor circuits and systems tend to be integrated together on one single chip.
For analog circuits, especially sensor circuits, a high-quality supply source is often needed
to maintain their function and accuracy. Although specific circuit methods can be employed
to improve the performance of sensor circuits arising from the reduced supply sensitivity
in VCO based sensor [1] and reduced supply noise in image sensor [2], these methods are
only applicable for the limited case examples. In order to increase power supply rejection
(PSR), the sensor circuit employing the feedback design [3,4] to the bridge sensing elements
is a popular method. However, it relies on splitting a full bridge sensing element into two
half bridge sensors. This may not be adequate for many general applications. Due to the
feedback mechanism, the loop gain, and the stability become the critical parameters that
deal with the PSR performance and frequency compensation, respectively. Besides, other
temperature sensors [5–7] and an optical mouse sensor [8] have addressed the importance
of supply issues based on the impact of supply sensitivity or supply noise on the sensor
circuit performance. Regarding recent trend towards low-power consumption, one of the
Sensors 2021, 21, 7856. https://doi.org/10.3390/s21237856
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dressed the importance of supply issues based on the impact of supply sensitivity or supply noise on the sensor circuit performance. Regarding recent trend towards low-power
consumption, one of the previously reported supply circuits [9] can consume low power.
previously
reported
supplytopology
circuits [9]
can consume
power. Unfortunately,
the circuit
Unfortunately,
the circuit
suffers
from thelow
disadvantage
of requiring higher
suptopology
suffers
from
the
disadvantage
of
requiring
higher
supply.
Therefore,
low-power
ply. Therefore, low-power low-voltage performance becomes one of main agendas in senlow-voltage
performance
becomes circuits
one of main
agendas in low
sensor
circuitwireless
design. sensor
The
sor circuit design.
The exemplary
are low-voltage,
dropout
exemplary
circuits
are
low-voltage,
low
dropout
wireless
sensor
node
[10]
and
low-power
node [10] and low-power low-voltage biomedical sensor IC [11]. Based on the above dislow-voltage biomedical sensor IC [11]. Based on the above discussed sensor applications,
cussed sensor applications, the Low Dropout (LDO) Regulator is regarded as the common
the Low Dropout (LDO) Regulator is regarded as the common building block used to
building block used to produce a stable supply voltage to sustain the sensor circuit perproduce a stable supply voltage to sustain the sensor circuit performance whilst providing
formance whilst providing adequate PSR as another important characteristic in sensor
adequate PSR as another important characteristic in sensor circuits and systems. Figure 1
circuits and systems. Figure 1 shows the general structure of a sensor circuit powered by
shows the general structure of a sensor circuit powered by a LDO regulator in which a
a LDO regulator in which a voltage reference is generated by a bias circuit to define the
voltage reference is generated by a bias circuit to define the output voltage of a regulator.
output voltage of a regulator.
Figure1.1.AASensor
SensorCircuit
CircuitPowered
Poweredbybya aLDO
LDORegulator.
Regulator.
Figure
However,ininthe
theevent
eventthat
thatthe
thePSR
PSRoffered
offeredbybythe
theregulator
regulatorisisnot
notadequate,
adequate,a aPSR
PSR
However,
enhancer
[12],
which
usually
serves
as
the
secondary
regulator,
can
be
employed
in
analog
enhancer [12], which usually serves as the secondary regulator, can be employed in analog
circuitdesign.
design.The
Theexemplary
exemplarycircuit
circuitblock
blockdiagram
diagramisisdepicted
depictedininFigure
Figure2.2.As
Ascan
canbe
beseen,
seen,
circuit
theenhancer
enhancercomprises
comprises aa voltage reference and
function.
Its
the
and aaLDO
LDOregulator
regulatorwith
withscaling
scaling
function.
output
voltage,
VOUT,
is designed
to betoclose
to the
LDO LDO
regulator
output
line in
Its
output
voltage,
VOUT,
is designed
be close
toprimary
the primary
regulator
output
which
the output
voltagevoltage
is denoted
as VOUT_LDO
The difference
between Vbetween
OUT and V
line
in which
the output
is denoted
as V.OUT_LDO
. The difference
VDD_OUT
OUT
of the
PSR enhancer
defines
the defines
dropoutthe
voltage.
Such
the dropout
and
VDD_OUT
of the PSR
enhancer
dropout
voltage.
Such thevoltage
dropoutshould
voltagebe
made be
as small
order to
operation
headroom
becausebecause
the price
should
made as
as possible
small as in
possible
in offer
ordermaximal
to offer maximal
operation
headroom
the
price
be the reduction
of sensor
headroom.
importantly,
paid
forpaid
that for
willthat
be will
the reduction
of sensor
supplysupply
headroom.
More More
importantly,
when
when
the sensor
is targeted
low voltage
applications,
this
the
design
the sensor
circuitcircuit
is targeted
for lowfor
voltage
applications,
this raises
theraises
design
challenges
challenges
about the
dropout
voltage contributed
by the PSR
enhancer
in
about the stability
of stability
dropout of
voltage
contributed
by the PSR enhancer
in context
of procontext
of process,
and temperature
(PVT)
variation.
This is then
to
cess, voltage,
and voltage,
temperature
(PVT) variation.
This
is then translated
totranslated
the problems
the
problems
arising
from
the
stability
of
the
enhancer’s
voltage
reference,
as
well
as
its
arising from the stability of the enhancer’s voltage reference, as well as its driving LDO
driving
with goal
the ultimate
goala to
produce
a small
dropout
which
circuit, LDO
with circuit,
the ultimate
to produce
small
dropout
voltage
whichvoltage
can sustain
the
can
sustain
the proper
of a PSR
enhancer.
For
an example,
consider
a dropout
proper
operation
of a operation
PSR enhancer.
For an
example,
consider
a dropout
voltage
of 0.1 V
voltage
ofV0.1
V from
1.2 Vor
supply
or below
a sensor
circuit,
this
requires
a
from 1.2
supply
voltage
belowvoltage
in a sensor
circuit,inthis
requires
a lot of
circuit
design
lot
of circuit design
considerations
dedicated
to low-power
low-supply
considerations
dedicated
to low-power
low-supply
voltage
reference voltage
design, reference
as well as
design,
well as scaling
design in
conjunction
with simultaneously
addressing
scalingasregulator
designregulator
in conjunction
with
simultaneously
addressing PSR
concerns.
PSR
concerns.
Apart
from
that,
the
PSR
enhancer
serves
as
an
extra
block
in
the sensor
Apart from that, the PSR enhancer serves as an extra block in the sensor applications,
thus
applications,
thus
increasing
the costTo
as the
penalty.
To relax
the issue,
the circuit
topology
increasing the
cost
as the penalty.
relax
the issue,
the circuit
topology
of the
PSR enofhancer
the PSR
enhancer
should be
designed
with This
simplicity.
Thismotivation
raises the motivation
ofto
this
should
be designed
with
simplicity.
raises the
of this work
dework
to
design
a
cost-effective
PSR
enhancer,
not
only
to
improve
PSR,
but
also
to
produce
sign a cost-effective PSR enhancer, not only to improve PSR, but also to produce a stable
a and
stable
anddropout
small dropout
withimmunity
good immunity
thevariation.
PVT variation.
small
voltagevoltage
with good
againstagainst
the PVT
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Figure
2. A
Circuit
Powered
by by
a LDO
Regulator
with
a PSR
Enhancer.
Figure
2. Sensor
A Sensor
Circuit
Powered
a LDO
Regulator
with
a PSR
Enhancer.
2. Conventional
PSR
Enhancer
Circuit
and
Design
Considerations
2. Conventional
PSR
Enhancer
Circuit
and
ItsIts
Design
Considerations
PSR
enhancers
with
low
dropoutvoltage
voltageare
arenecessary
necessaryfor
forsensitive
sensitiveor
or accurate
accurate sensensor
PSR
enhancers
with
low
dropout
circuits.
To
meet
the
requirement
of
high
PSR
for
sensor
circuit
in
low-voltage
low-power
sor circuits. To meet the requirement of high PSR for sensor circuit in low-voltage lowapplications,
circuit circuit
design considerations
are conducted.
At this juncture,
MOSFET
device
power
applications,
design considerations
are conducted.
At this
juncture,
operated
in the
sub-threshold
region [13] isregion
often preferred
over
the Bipolar
Junction
MOSFET
device
operated
in the sub-threshold
[13] is often
preferred
over the
BiTransistor
(BJT)
counterparts
[14]. To provide
a LDO regulator
polar
Junction
Transistor
(BJT) counterparts
[14].the
Todriving
providecharacteristic,
the driving characteristic,
a
or buffer-like
operational
(op-amp)
circuit
is oftencircuit
needed.
Of particular
note,
LDO
regulator or
buffer-likeamplifier
operational
amplifier
(op-amp)
is often
needed. Of
the regulator/buffer
should be arranged
a separate
stage
design,
rather
than
particular
note, the regulator/buffer
should beinarranged
in driving
a separate
driving
stage
design,
embedding
with
the
voltage
reference
in
the
topology
of
the
merged
design.
The
reason
rather than embedding with the voltage reference in the topology of the merged design.
forreason
usingfor
cascade
topologytopology
is that any
influence
arisingarising
from the
small
voltage
The
using cascade
is that
any influence
from
the dropout
small dropout
will
not
contribute
the
stress
to
the
output
of
the
voltage
reference
stage
if
it
were
designed
voltage will not contribute the stress to the output of the voltage reference stage if it were
with anwith
embedded
buffer. buffer.
It is important
to noteto
that
sufficient
headroom
allowed
designed
an embedded
It is important
note
that sufficient
headroom
al-for
the
voltage
reference
output
is
easily
scaled
to
the
targeted
dropout
voltage
through
lowed for the voltage reference output is easily scaled to the targeted dropout voltagethe
regulator
or op-amp,
with aetc.
scaling
AttentionAttention
is also paid
to the
PSR
through
the regulator
oretc.
op-amp,
with anetwork.
scaling network.
is also
paid
to issue,
the
which
pertains
to
the
circuit
topology
or
frequency
compensation
technique
in
regulator
PSR issue, which pertains to the circuit topology or frequency compensation technique in or
op-ampor
design.
Furthermore,
the output the
stage
of thestage
regulator
op-amp buffer
should
regulator
op-amp
design. Furthermore,
output
of theorregulator
or op-amp
tolerate the change of dropout voltage without deteriorating the open-loop gain function,
buffer should tolerate the change of dropout voltage without deteriorating the open-loop
as the change of dropout voltage will stress the output transistor of the regulator or op-amp
gain function, as the change of dropout voltage will stress the output transistor of the
based buffer circuit.
regulator or op-amp based buffer circuit.
Based on these design considerations, an exemplary op-amp based PSR enhancer that
Based on these design considerations, an exemplary op-amp based PSR enhancer that
features good PSR topology [15,16] for the enhancer design is depicted in Figure 3. The
features good PSR topology [15,16] for the enhancer design is depicted in Figure 3. The
enhancer comprises a reference voltage generator and a LDO regulator.
enhancer comprises a reference voltage generator and a LDO regulator.
For the Reference Voltage Generator, M1 and M2 work in the subthreshold region.
For the Reference Voltage Generator, M1 and
M2 work in the subthreshold region. As
As such, the temperature characteristic similar to that of BJT. The VREF , which is equal to
such, the temperature characteristic similar to that of BJT. The VREF, which is equal to VSG1
VSG1 plus VR1 , is a combination of PTAT and CTAT voltage. The output of OA1 yields the
plus VR1, is a combination of PTAT and CTAT voltage. The output of OA1 yields the refreference voltage as:
erence voltage as:
R
S
VREF ( T ) = VSG1 ( T𝑅
(1)
) + 1 nV𝑆T ln 2
1 R
2
S1
𝑉𝑅𝐸𝐹 (𝑇) = 𝑉𝑆𝐺1 (𝑇) + 𝑛𝑉𝑇2ln⁡( )
(1)
𝑅2
𝑆1
where S1 and S2 are the aspect ratio of M1 and
M2 , respectively.
Thus, a temperature
where
S1 and S2Vare
the
aspect
ratio
of
M
1 and Madjusting
2, respectively.
Thus,
a
temperature
insensitive,
,
can
be
realized
through
the
ratio
of
R1 and R2 . insenBesides,
REF
sitive,
VREF, can be realized
through adjusting
the ratio
of R1 and
R2. Besides,
the employthe employment
of sub-threshold
based MOS
transistors
permits
the reference
voltage
ment
of sub-threshold
transistors
the reference
voltage
generator
to
generator
to operatebased
at lowMOS
supply
voltage permits
and consume
low power.
The
OA1, shown
operate
at
low
supply
voltage
and
consume
low
power.
The
OA1,
shown
in
Figure
4,
is
in Figure 4, is a PMOS-input two-stage amplifier with a source follower output stagea to
PMOS-input
two-stage
amplifier
with
a source
follower
output stage
to avoidresulting
the resistive
avoid the resistive
loading
effect
that
influences
the open-loop
function,
in the
loading
effect that
influences
function,
resulting
in theheadroom
degradation
of PSR. at
degradation
of PSR.
Due tothe
theopen-loop
use of source
follower,
the output
is reduced
Due
the use of V
source
follower,
thetooutput
headroom
reducedvoltage
at the trade-off
of VREF
thetotrade-off
is unable
produce
the smallisdropout
design. Regarding
REF and
theis low-dropout
voltage
VREF
denoted
in Figure
will be scaled
and
unable to produce
thedesign
small requirement,
dropout voltage
design.
Regarding
the3,low-dropout
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voltage design requirement, VREF denoted in Figure 3, will be scaled in the LDO regulato
through the scale factor (1 + R4/R5). To minimize the regulator’s circuit complexity, th
power transistor
stage canVbe
toFigure
cascade
withbethe
first-stage
differential
voltage
design requirement,
REFarranged
denoted in
3, will
scaled
in the LDO
regulatoramplifie
inthrough
the
LDO
regulator
through
the
scale
factor
(1
+
R
/R
).
To
minimize
the
regulator’s
4
5
the scale
factor (1 +amplifier
R4/R5). Totopology
minimize as
theshown
regulator’s
circuit5.complexity,
the
OA2 to form
a two-stage
in Figure
The well-known
ca
circuit
complexity,
the power
stage
can bewith
arranged
to cascadedifferential
with the first-stage
power
transistor stage
can betransistor
arranged
toapplied
cascade
the first-stage
code compensation
technique
[17] is
to obtain
a good PSR metric.amplifier
Finally, the siz
differential
amplifier
OA2 toamplifier
form a two-stage amplifier
topology
as 5.
shown
in Figure 5. The
OA2
to form
a two-stage
as shown
Figure
Theenhancer
well-known
cas- is liste
of each
component
pertaining totopology
Figures 3–5
in theinconventional
design
well-known
cascode
compensation
technique
[17]
is
applied
to
obtain
a
good
PSR metric.
code
compensation
technique
[17]
is
applied
to
obtain
a
good
PSR
metric.
Finally,
the
size
in Table
Finally,
the1.size of each component pertaining to Figures 3–5 in the conventional enhancer
of each component pertaining to Figures 3–5 in the conventional enhancer design is listed
design
is listed
in Table 1.
in Table
1.
Figure3.3.Conventional
PSREnhancer
Enhancerwith
withPSR
PSRDesign
DesignAware.
Aware.
Figure
PSR
Figure 3.Conventional
Conventional
PSR
Enhancer
with
PSR
Design
Aware.
Figure 4. Schematic of OA1 for Reference Voltage Generator in Enhancer.
Figure
Schematic
of OA1
for Reference
Voltage
Generator
in Enhancer.
Figure
4. 4.
Schematic
of OA1
for Reference
Voltage
Generator
in Enhancer.
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Figure5.5.Schematic
SchematicofofOA2
OA2for
forRegulator
RegulatorininEnhancer.
Enhancer.
Figure
Table 1. Sizes of the Devices in the Conventional Design.
Table 1. Sizes of the Devices in the Conventional Design.
Device
Size
Device
Size
Device
Size
Device
Size
M1
40/4 (μm/μm)
MB1,2
10/0.5 (μm/μm)
M
40/4 (µm/µm)
M
10/0.5 (µm/µm)
M2 1
320/4 (μm/μm)
MB3,4B1,2
10/2 (μm/μm)
M2
320/4 (µm/µm)
MB3,4
10/2 (µm/µm)
MPMP
1000/0.16
(μm/μm)
MB5MB5
8.7/1
(μm/μm)
1000/0.16
(µm/µm)
8.7/1
(µm/µm)
MM
A1,2
50/1
(μm/μm)
MB6,7
5.6/1
(μm/μm)
50/1
(µm/µm)
MB6,7
5.6/1
(µm/µm)
A1,2
(µm/µm)
MB8,9
2/0.5
(µm/µm)
A3,4
MM
A3,4
3/13/1
(μm/μm)
MB8,9
2/0.5
(μm/μm)
MA5
2/1 (µm/µm)
MB10,11
10/1 (µm/µm)
MA5
2/1 (μm/μm)
MB10,11
10/1 (μm/μm)
MA6
1.7/1 (µm/µm)
MB12,13
5/1 (µm/µm)
MM
A6
1.7/1
(μm/μm)
M
B12,13
5/1
(μm/μm)
1.4/1 (µm/µm)
MB14,15
2/0.16
(µm/µm)
A7
MM
A7 A8
1.4/1
(μm/μm)
M
B14,15
2/0.16
20/2 (µm/µm)
MB16,17
4/2(μm/μm)
(µm/µm)
10/1
(µm/µm)
R1
283 kΩ
MM
A8 A9
20/2
(μm/μm)
MB16,17
4/2 (μm/μm)
M
6/1
(µm/µm)
R
kΩ
A10,11
MA9
10/1 (μm/μm)
R1 2
28399
kΩ
MA12,13
5/0.2 (µm/µm)
R3
283 kΩ
MM
A10,11
6/11/1
(μm/μm)
R2 R
99515
kΩkΩ
(µm/µm)
4
A14,15
MA12,13
5/0.2 (μm/μm)
R3 R5
283614
kΩkΩ
RA1
18.9 kΩ
RB1
27.8 kΩ
CM
MA14,15
1/1 (μm/μm)
R4for OA1
5150.8
kΩpF
C
for
OA2
0.4
C
RA1
18.9 kΩ
R5
614 kΩpF
RB1
27.8 kΩ
CM for OA1
0.8 pF
3. Proposed PSR Enhancer with PVT-Insensitive
Dropout
CC for
OA2 Voltage
0.4 pF
3.1. Proposed Enhancer Design
3. Proposed
PSR Enhancer
withisPVT-Insensitive
Voltage of the Level-Shifted
The proposed
PSR enhancer
shown in FigureDropout
6. It is composed
Flipped
Voltage
Follower
(LSFVF)
[18]
based
on
the
LDO
regulator
and the CTAT bias
3.1. Proposed Enhancer Design
current generator with a capacitive start-up circuit. The FVF based regulator has the
The proposed PSR enhancer is shown in Figure 6. It is composed of the Level-Shifted
key advantage of simplicity. The use of LSFVF topology is to relax the power transistor
Flipped Voltage Follower (LSFVF) [18] based on the LDO regulator and the CTAT bias
operation headroom at the expense of a slight increase in complexity. This is considered
current generator with a capacitive start-up circuit. The FVF based regulator has the key
an important design consideration due to small dropout voltage requirement. Moreover,
advantage of simplicity. The use of LSFVF topology is to relax the power transistor
the LSFVF topology also provides a fast response in terms of transient performance, even
operation headroom at the expense of a slight increase in complexity. This is considered
biased with low quiescent conditions. This helps to reduce the transient spikes in the
an important design consideration due to small dropout voltage requirement. Moreover,
supply line of low-power sensor circuit. Referring to the LSFVF regulator, it consists of the
the LSFVF
topology
alsocontrol
provides
a fast response
in termscurrent
of transient
performance,
even
power
transistor
M8 , the
transistor
M7 , the cascode
source
with transistors
biased
with
low
quiescent
conditions.
This
helps
to
reduce
the
transient
spikes
in
the
M11 and M12 , and the source follower-based level shifter with transistors M9 and M10 . The
supply line
of low-power
sensortransistor
circuit. Referring
to the LSFVF
regulator,
it consists
intrinsic
dc biasing
to the control
M7 is obtained
from the
composite
transistorof
the
power
transistor
M
8, the control transistor M7, the cascode current source with
(M5 and M6 ) with the cascode current source (M13 and M14 ) and the pseudo-resistor [19]
transistors
M11 filter
and M
12, and the source follower-based level shifter with transistors M9
based
low-pass
(LPF).
Further details of the design of LPF will be discussed in the
and
M
10. The intrinsic dc biasing to the control transistor M7 is obtained from the
subsequent Section. Of particular note, in order to avoid the influence of leakage effect
composite
transistor
(M5 andtransistor
M6) with M
the, cascode
current source (M13 and M14) and the
to
the dc biasing
of control
7 high threshold transistors M5 , M6 , and M7
pseudo-resistor [19] based low-pass filter (LPF). Further details of the design of LPF will
Sensors 2021, 21, x FOR PEER REVIEW
6 of 19
Sensors 2021, 21, 7856
6 of 20
be discussed in the subsequent Section. Of particular note, in order to avoid the influence
of leakage effect to the dc biasing of control transistor M7, high threshold transistors M5,
are employed. Such the biasing implementation has the key advantage of eliminating
M6, and M7 are employed. Such the biasing implementation has the key advantage of
the complicated voltage generator as well as voltage reference in typical FVF regulator
eliminating the complicated voltage generator as well as voltage reference in typical FVF
design [20]. Good PSR is still obtained due to the use of LPF for filtering the dc supply
regulator design [20]. Good PSR is still obtained due to the use of LPF for filtering the dc
noise. As the result, the proposed topology offers a more compact topology with respect to
supply noise. As the result, the proposed topology offers a more compact topology with
that of the conventional counterpart.
respect to that of the conventional counterpart.
Figure
Figure 6.
6. Proposed
Proposed PSR
PSR Enhancer.
Enhancer.
Regarding
thebiasing
biasingcircuit
circuitinin
Figure
is designed
in a of
form
of aCTAT
newcurrent
CTAT
Regarding the
Figure
6, it6,isitdesigned
in a form
a new
current
source, comprising
transistors
M1–M
4 –M
and19M
15–M19 together
the network
start-up
source, comprising
transistors
M1 –M4 and
M15
together
with thewith
start-up
comprising
transistors
M20 –M21 M
and
a 21capacitor
C1 . ThisCself-biasing
networknetwork
usually
network
comprising
transistors
20–M
and a capacitor
1. This self-biasing
performsperforms
PTAT current
in a conventional
design. However,
by connecting
usually
PTATgeneration
current generation
in a conventional
design.
However, the
by
gate of triode
M3 to transistor
the gate ofM
the
composite
transistor
(M1 andtransistor
M4 ), it is (M
possible
connecting
thetransistor
gate of triode
3 to
the gate of
the composite
1 and
that
coefficient
(T.C.) effectcoefficient
of the triode
transistor
the
M
4), the
it isnegative
possibletemperature
that the negative
temperature
(T.C.)
effect dominates
of the triode
PTAT effectdominates
arising from
current
source
topology.
current
source
transistor
thethePTAT
effect
arising
fromConsequently,
the current the
source
topology.
behaves CTAT the
characteristic.
However,
theCTAT
concern
is that under
high temperature
and
Consequently,
current source
behaves
characteristic.
However,
the concern
is
fast
corner
case,
the
transistor
M
may
cut
off
itself.
In
order
to
sustain
the
operating
that under high temperature and fast
corner case, the transistor M3 may cut off itself. In
3
temperature
range
100 degree
C, a limitedrange
current
injected
to C,
theabulk
of Mcurrent
3 so as to
order
to sustain
thefor
operating
temperature
foris100
degree
limited
is
reduce
its
threshold
voltage.
injected to the bulk of M3 so as to reduce its threshold voltage.
The rationale
rationalefor
forthis
thisdesign
designisisthat
that
the
replica
clamping
structure
formed
by1,M
The
the
replica
clamping
structure
formed
by M
M14,
M4 and
Mthe
the biasing
circuit
matches
the clamping
structure
formed
M
2 inbiasing
5 , M6Mand
and
M2 in
circuit
matches
the clamping
structure
formed
by Mby
5, M
6 and
7 in
M
in
the
LSFVF
toplogy.
Therefore,
the
design
has
addressed
the
tracking
issue
so
as
to
7
the LSFVF toplogy. Therefore, the design has addressed the tracking issue so as to
minimize
the
impact
on
the
dropout
voltage
in
the
presence
of
process
variation.
Besides,
minimize the impact on the dropout voltage in the presence of process variation. Besides,
the generated
generated ΔV
∆VSG
ineach
eachstructure
structureisisalmost
almostindependent
independent of
of supply
supply voltage
voltage change.
change. This
This
SGin
the
is
translated
to
the
dropout
voltage
insensitive
to
the
supply
voltage.
Finally,
referring
to
is translated to the dropout voltage insensitive to the supply voltage. Finally, referring to
the
temperature
compensation,
the
generated
CTAT
current
will
compensate
the
change
of
the temperature compensation, the generated CTAT current will compensate the change
dropout
voltage
against
the
temperature.
Consider
the
output
voltage
of
LSFVF
regulator,
of dropout voltage against the temperature. Consider the output voltage of LSFVF
it decreases
with increasing
temperature
due to thedue
PTAT
effect
of clamping
structure
regulator,
it decreases
with increasing
temperature
to the
PTAT
effect of clamping
(M5 –M7 ). In other words, the increase in dropout voltage comes from the increase in
structure (M5–M7). In other words, the increase in dropout voltage comes from the
temperature. Besides, it is interesting to observe that if the loop produced by the sourceincrease in temperature. Besides, it is interesting to observe that if the loop produced by
gate volage of M8 , the source-gate voltage of M9 and the source-drain voltage of M7 are
the source-gate volage
of M8, the source-gate voltage of M9 and the source-drain voltage
made negative T.C., it is able to compensate the positive T.C. introduced by the clamping
of M7 are made negative T.C., it is able to compensate the positive T.C. introduced by the
structure (M5 –M7 ). However, if a long channel transistor of M7 is employed with small
clamping structure
(M5–M7). However, if a long channel transistor of M7 is employed with
channel length modulation (CLM) effect, its VSD7 will absorb the temperature-induced
small channel length modulation (CLM) effect,
its VSD7 will absorb the temperaturevoltage change caused by the sum of source-gate voltages through M8 and M9 . Therefore,
induced voltage change caused by the sum of source-gate voltages through
M8 and M9.
it may be difficult to impose the negative T.C. voltage change caused by VSG8 (T) and VSG9
Therefore, it may be difficult to impose the negative T.C. voltage change caused
by VSG8(T)
(T) on VOUT (T). To tackle the issue, the CTAT current source and the short-channel length
M7 with CLM effect are employed in this proposed design; this permits VSD7 (T) to behave
Sensors 2021, 21, x FOR PEER REVIEW
Sensors 2021, 21, 7856
7 of 19
and VSG9 (T) on VOUT(T). To tackle the issue, the CTAT current source and the short-channel
7 of 20
length M7 with CLM effect are employed in this proposed design; this permits VSD7(T)
to
behave negative T.C. characteristic. Further proof will be given in the subsequent Section.
As such, the combined negative T.C. contributed by the temperature compensation
transistor structure (M7–M9) becomes the key part for temperature compensation. In brief,
negative T.C. characteristic. Further proof will be given in the subsequent Section. As
due to the use of the replica structure, simple temperature compensation in the topological
such, the combined negative T.C. contributed by the temperature compensation transistor
network and
all transistor-based
designs for obtaining a better tracking characteristic, the
structure
(M7 –M
9 ) becomes the key part for temperature compensation. In brief, due to the
dropout
voltage
of
the
PSR
enhancer
is almost independent
of in
PVT
This
yields
use of the replica structure, simple temperature
compensation
thevariation.
topological
network
a
stable
output
voltage
from
the
enhancer
to
power
the
sensor
circuit
of
interest.
and all transistor-based designs for obtaining a better tracking characteristic, the dropout
Regarding
theenhancer
frequencyiscompensation
of the regulator,
it is stabilized
by the cascode
voltage
of the PSR
almost independent
of PVT variation.
This yields
a stable
compensation
[21]
in
conjunction
of
Miller
RC
frequency
compensation.
This leads to
output voltage from the enhancer to power the sensor circuit of interest.
goodRegarding
stability under
low quiescent
power design.
the frequency
compensation
of the regulator, it is stabilized by the cascode
compensation [21] in conjunction of Miller RC frequency compensation. This leads to good
3.2. Low-Pass
Filter
PSR Enhancer
stability
under
lowin
quiescent
power design.
The LPF circuit is depicted in Figure 7. Taking into account the small silicon area
3.2.
Low-Pass
Filter on
in PSR
Enhancerfilter design using a pseudo resistor RF and a MOS cadesign,
it is based
a first-order
pacitor
. Thecircuit
pseudo
comprises
units
(MR1into
–MR5account
) in seriesthe
topology
to realize
TheCFLPF
is resistor
depicted
in Figure57.
Taking
small silicon
areaa
large resistance
for on
useain
low frequency,
which using
starts afrom
1 Hzresistor
and above.
Duea to
the
design,
it is based
first-order
filter design
pseudo
RF and
MOS
capacitor
pseudo
resistor
comprises
units (MR1 –M
) in series in
topology
to reduce
realize
extremelyClarge
high
threshold
MOS5 transistors
areR5employed
order to
F . Thevalue,
athe
large
resistance
for This
use insuggests
low frequency,
which Vstarts
from 1toHz
above. Due
the
leakage
current.
the potential
C1 is close
VC2and
. Regarding
theto
MOS
extremely
value,
thresholdMOS
MOShigh-threshold
transistors are transistor
employedwith
in order
to reduce
capacitor, itlarge
is based
onhigh
a thick-oxide
the gate
as the
the
current.
This
the potential and
VC1 bulk
is close
to VC2
. Regarding
thetermiMOS
top leakage
plate terminal
and
thesuggests
shorted drain-source
to form
the
bottom plate
capacitor,
it
is
based
on
a
thick-oxide
MOS
high-threshold
transistor
with
the
gate
as
nal. The formation of a large time constant by the LPF will cause the slow start-up of the
the
top
plateToterminal
and issue,
the shorted
drain-source
and bulk
to form the
bottom plate
terminal.
circuit.
tackle this
a digital
start-up, which
comprises
a capacitive
start-up
netThe
of a transistor
large time M
constant
by the LPF
will cause
ofCthe
circuit.
workformation
formed by
22, six inverter
transistors
(M23the
–Mslow
28), a start-up
capacitor
2 and
five
To
tackle
this issue,
a digital
which are
comprises
a capacitive
network
MOS
switching
transistors
(Mstart-up,
29–M33), which
connected
in parallelstart-up
with respective
formed
a transistor
transistors
(Mis
C2 voltage
and fiveof
MOS
22 , six inverter
23 –M
28 ), a capacitor
pseudo by
resistor
unit, isMproposed.
When
the system
powered
on, a peak
VC3
switching
transistors
(M
–M
),
which
are
connected
in
parallel
with
respective
pseudo
29
33 of C2. Hence, a reversed pulse signal is generated on VC4,
will appear due to the charging
resistor
unit,
is on
proposed.
When
the system
a peak
voltage
C3 will
which will
turn
the switches
realized
by M29istopowered
M33. Thison,
allows
VC1 to
chargeof
CFVrapidly.
appear
due
to
the
charging
of
C
.
Hence,
a
reversed
pulse
signal
is
generated
on
V
,
2
C4 which
After the pulse signal, all the switches
will be turned off. Then, the LPF establishes
a RC
will
turn
onathe
switches
to M33 . Of
This
allows Vnote,
charge
CF rapidly.
29 biasing.
C1 tothe
circuit
with
charged
CF torealized
provideby
theMdc
particular
off resistance
of
After
the
pulse
signal,
all
the
switches
will
be
turned
off.
Then,
the
LPF
establishes
a
RC
each MOS switch is not infinite. It will reduce the MOS pseudo resistor unit resistance
circuit
with paralleling
a charged Cwith
the OFF
dc biasing.
particular
note,
the off resistance
F to provide
value when
a non-ideal
switch. Of
This
leads to the
employment
of five
of
each
MOS
switch
is
not
infinite.
It
will
reduce
the
MOS
pseudo
resistor
unit resistance
serial pseudo resistors. Nevertheless, the effective silicon area of each pseudo
resistor is
value
when small.
paralleling
with a non-ideal
OFF switch.
Thisresistors
leads to the
of five
considered
The penalty
for the increase
of pseudo
is ofemployment
little concern.
serialThe
pseudo
resistors.
Nevertheless,
the
effective
silicon
area
of
each
pseudo
resistor
is
size of each component, which are pertaining to the proposed PSR enhancer in
considered
small.
The
penalty
for
the
increase
of
pseudo
resistors
is
of
little
concern.
Figure 6 and the low pass filter in Figure 7 are given in Table 2.
Figure 7.
7. Low pass filter with
with digital
digital start-up.
start-up.
Figure
The size of each component, which are pertaining to the proposed PSR enhancer in
Figure 6 and the low pass filter in Figure 7 are given in Table 2.
Sensors 2021, 21, 7856
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Table 2. Sizes of the devices in the proposed design.
Device
Size
Device
Size
M1
M2,4
M3
M5
M6,7
M8
M9
M10
1.7/0.3 (µm/µm)
20/0.3 (µm/µm)
2.1/4.5 (µm/µm)
3/0.3 (µm/µm)
14/0.3 (µm/µm)
1000/0.16 (µm/µm)
10/0.1 (µm/µm)
1.9/0.3 (µm/µm)
4/2 (µm/µm)
5/1 (µm/µm)
0.12/5 (µm/µm)
1/0.3 (µm/µm)
M22
M23,25,27
M24,26,28
M29–33
MR1-R5
MC
RM
C1
C2
CM
CC
CL
0.32/4 (µm/µm)
4/0.04 (µm/µm)
2/0.04 (µm/µm)
0.32/1 (µm/µm)
0.32/1 (µm/µm)
100/100 (µm/µm)
5 kΩ
0.1 pF
1 pF
1 pF
2.5 pF
1 pF–10 pF
M11,13,15,17
M12,14,16,18
M19
M20,21
3.3. Temperature Analysis of the Building Blocks in PSR Enhancer
3.3.1. CTAT Biasing Current IB (T)
When a PMOS transistor works in subthreshold region [22–24], the source-drain
current ISD (T) is obtained as
ISD ( T ) = µ p ( T )COX VT
2
= IS ·S·e
VSG (T)+Vtp (T)
V
W
− SD(T )
nVT
·e
·[1 − e VT ]·[1 − λVSD ( T )]
L
VSG ( T )+Vtp ( T )
nVT
·[1 − e
−
VSD ( T )
VT
]·[1 − λVSD ( T )]
(2)
where Is = µP COX VT 2 , µP is the carrier mobility, COX is the gate oxide capacitance, n is the
subthreshold slope which is a constant between 1 and 3, VT = KT/q is the thermal voltage,
K is the Boltzmann constant, T is the temperature, q is the electronic charge, S = W/L is
the aspect ratio, W is the channel width, L is the channel length. λ is the channel length
modulation factor and it has a negative value for PMOS transistor. Further to that, the
temperature-dependent threshold voltage and mobility are given as follows:
Vtp ( T ) = Vtp0 + k t ( T − T0 )
(3)
µ p ( T ) = µ p ( T0 )·( T/T0 )−m
(4)
where Vtp0 is the threshold voltage at reference temperature T0 = 300 K, kt and m are
constants pertaining to process technology. When VSD (T) > 3VT , the exponential VSD (T)
term in (2) can be ignored and (2) can be rewritten as follows:
ISD ( T ) ≈ IS ·S·e
VSG ( T )+Vtp ( T )
nVT
·[1 − λVSD ( T )]
(5)
Thus, the approximated expression of VSG (T) for a long channel length transistor
becomes
ISD ( T )
VSG ( T ) ≈ −Vtp ( T ) + nVT ln
≈ −Vtp ( T )
(6)
S· IS
where ISD (T) ≈ S·IS . To compensate the negative temperature coefficient of the output
voltage, a bias circuit without a resistor, which aims to generate an appropriate CTAT bias
current, is proposed in Figure 6. M1 , M2 and M4 operate in the subthreshold region over the
targeted temperature range (−20 to 80 ◦ C). Through selecting same type of high threshold
voltage transistor and establishing the replica ∆VSG (T) clamping topology (shaded area) in
CTAT current generator with respect to that in core regulator as illustrated in Figure 6, such
Sensors 2021, 21, 7856
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as the ∆VSG (T) becomes the source-drain voltage across the triode transistor M3 . Therefore,
VSD3 (T) = VSG1 (T) − VSG2 (T) = ∆VSG (T). Since VSD1 (T) and VSD2 (T) > 3VT , this gives
KT
S2
VSD3 ( T ) = VSG1 ( T ) − VSG2 ( T ) = Vtp2 ( T ) − Vtp1 ( T ) + n
ln
q
S1
KT
S2
≈n
(7)
ln
q
S1
In view of the identical type of transistor being used for M1 and M2 , the threshold
voltage difference is negligible. Based on (7), VSD3 (T) can be regarded as a PTAT voltage.
M3 works in linear region to act as an active resistor, the equivalent resistance between the
source and drain of M3 is given as
R3 ( T ) =
1
h
µ p ( T )COX S3 VSG1 ( T ) + Vtp3 ( T ) − 21 VSD3 ( T )
i
(8)
Using (6)–(8), the bias current expression is obtained as follows:
VSD3 ( T )
R3 ( T )
S2
KT
1
≈ µ p ( T )COX S3 ·n
ln
·{Vtp3 ( T ) − Vtp1 ( T ) + Vtp2 ( T ) }
q
S1
2
= C1 T −m · C2 T − C3 T 2
IB ( T ) =
dIB ( T )
= −C4 T −m + C5 T 1−m
dT
(9)
(10)
(11)
where
C1 = µ p ( T0 ) T0 m COX S3 n
Vtp0_1 + Vtp0_2
S2
K
ln
, C2 = Vtp0_3 −
+ T0 C3 ,
q
S1
2
C3 = k t1 − k t3 , C4 = (m − 1)C1 C2 , C5 = (m − 2)C1 C3 ,
Since M1 and M2 are the same type of transistors, the kt1 and kt2 are identical. Factor m
has a typical value of 2.2 for silicon [25], and the parameters C1 , C2 , C3 , C4 , C5 are constants
with positive value. From (11), it can be deduced that IB (T) exhibits a CTAT characteristic
over the temperature range of T < C4 /C5 , and the estimation of IB (T) will be discussed in
the subsequent Section. Of particular note, the value of C4 /C5 is above 2T0 (600 K) which
is beyond the operation temperature range of the transistor. Thus, the CTAT bias current
IB (T) is used for temperature compensation of VOUT (T). Although IB (T) slightly exhibits
nonlinearity, it does not jeopardize the temperature compensation significantly. Due to
the fact that the bias circuit is designed with all MOS transistors, it offers better tracking
characteristics in terms of process variation as another key advantage. As such, the entire
PVT performance will be promising by means of the proposed CTAT current source.
3.3.2. Temperature-Compensated VOUT (T) in LSFVF Topology
The output voltage of the enhancer, which is shown in Figure 6, can be expressed as
VOUT ( T ) = VDD − VSG5 ( T ) + VSG7 ( T )
(12)
Since the transistors M5 –M8 work in the subthreshold region, it is apparent that
VOUT (T) is a CTAT voltage because ∆VSG (T) is a PTAT voltage based on (7).
Sensors 2021, 21, 7856
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For M7 , due to the use of a short channel transistor, the CLM is taken into consideration.
This yields:
IB ( T )
VSG7 ( T ) = nVT ln {
} − Vtp7 ( T )
(13)
IS S7 [1 − λVSD7 ( T )]
Substituting (13) into (12), we get
S7
VOUT ( T ) = VDD − nVT ln
− Vtp7 ( T ) + Vtp5 ( T ) − nVT ln[1 − λVSD7 (T)]
S5
S7
KT
KT
ln
+ nλ
V (T )
≈ VDD − n
q
S5
q SD7
(14)
From (14), it is obvious that if VSD7 (T) in the third term of VOUT (T) is made CTAT
characteristic, the last two terms will conunteract each other. Regarding Figure 6, the
VSD7 (T) can be written as
VSD7 ( T ) = VOUT ( T ) − VD7 ( T )
= VDD − ∆k − [VDD − VSG8 ( T ) − VSG9 ( T )] = −∆k + VSG8 ( T ) + VSG9 ( T )
(15)
where ∆k is the design value of the temperature-insensitive dropout voltage and ∆k = VDD
− VOUT = 87.3 mV. Since both M8 and M9 work in the subthreshold region, substituting
the expressions for VSG8 (T), VSG9 (T) using (6), and rewriting (15), we obtain
I · I · S8 · S9
KT
VSD7 ( T ) ≈ −∆k − Vtp0_8 + Vtp0_9 + ( T − T0 )·(k t8 + k t9 ) − n
ln [ S8 S9
] (16)
q
M · IB ( T )2
where factor M is the current mirror ratio between M10 and M5 . As can be observed from
(16), −∆k is a constant term, −[Vtp0_8 + Vtp0_9 + (T − T0 )·(kt8 + kt9 )] is a CTAT term for
PMOS, and the CTAT IB (T) will translate the last term into CTAT counterpart. As a result,
VSD7 (T) yields the CTAT characteristic. Subsituting (16) into (14), VOUT (T) can be rewritten
as follows:
KT
S7
KT VOUT ( T ) = VDD − n
ln
∆k + Vtp0_8 + Vtp0_9 − T0 (k t8 + k t9 )
+ n(−λ)
q
S5
q
+ (−λ) T 2 {(
I · I ·S ·S
nK
nK 2
) ln [ S8 S9 8 2 9 ] +
(k t8 + k t9 )}
q
q
M · IB ( T )
= VDD − N1 · T + N2 · T + N3 · T 2
(17)
(18)
where
K
N1 = n ln
q
S7
S5
N2 = −nλ
N3 = −λ(
K
∆k + Vtp0_8 + Vtp0_9 − T0 (k t8 + k t9 )
q
nK 2
I · I ·S ·S
nK
) ln [ S8 S9 8 2 9 ] − λ (k t8 + k t9 )
q
q
M · IB ( T )
As indicated in (18), the negated PTAT term -N1 ·T will be counteracted by the positive
CTAT terms which are contributed by dominant linear term N2 ·T and small quadratic
N3 ·T2 . They are introduced by the temperature-dependent threshold voltages Vtp8 (T) and
Vtp9 (T), the design value of dropout voltage ∆k , the channel length modulation factor λ of
M7 and the CTAT current source IB (T). The small quadratic term will display the quadratic
effect only at high temperature.
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4. Results and Discussions
The proposed PVT-insensitive PSR enhancer, as depicted in Figure 6, is simulated
using TSMC-40 nm CMOS process technology.
Figure 8 shows the simulated PSR at different capacitive loads and load currents.
From Figure 8, the enhancer offers −36 dB PSR from 1 Hz to 100 kHz. In this design,
the maximum load current of the enhancer is 500 µA. When the load current exceeds
Sensors 2021, 21, x FOR PEER REVIEW its maximum value, the power transistor M will enter the linear region, and11
19
theof circuit
8
performance will be compromised. Therefore, there is a trade-off between the driving
capacity and the silicon area. In this work, the proposed enhancer is focused on light load
current
less and
thanthe
1 mA
and the
typicalrange
frequency
range
for system
the sensor
which
is lesswhich
than 1is mA
typical
frequency
for the
sensor
is ofsystem
few is
of
few
MHz
or
less.
Therefore,
there
is
no
strict
demand
on
layout
issues
in
view
of the
MHz or less. Therefore, there is no strict demand on layout issues in view of the insignifinsignificant
routing
parasitics.
icant routing parasitics.
Figure
8. PSR
of the
Design
at Different
Capacitive
Loads
and and
LoadLoad
Currents.
Figure
8. PSR
ofProposed
the Proposed
Design
at Different
Capacitive
Loads
Currents.
Figure
9a illustrates
the variation
of CTAT
bias current
IB(T) atIdifferent
process corFigure
9a illustrates
the variation
of CTAT
bias current
process
B (T) at different
nerscorners
(FF, TT,(FF,
SS)TT,
at the
temperatures,
rangingranging
from −20
°C to
80 ◦°C.
The
(T)The
SS) operation
at the operation
temperatures,
from
−20
C to
80 I◦BC.
decreases
with increasing
temperatures
across the across
operation
temperature
range. It shows
IB (T) decreases
with increasing
temperatures
the operation
temperature
range. It
shows
0.8 the
µA SS
under
theatSS80corner
at 80
0.49 the
µA TT
under
the at
TT80corner
at 0.2
80 ◦μA
C and
0.8 μA
under
corner
°C, 0.49
μA◦ C,
under
corner
°C and
◦ C. This confirms the CTAT characteristic as revealed
0.2the
µAFF
under
theatFF80corner
at 80
under
corner
°C. This
confirms
the CTAT characteristic as revealed in (10).
in (10).the
Regarding
the output
voltage,
VOUT (T),with
it is different
evaluated
with different
process
Regarding
output voltage,
VOUT(T),
it is evaluated
process
corners, temcorners,
temperatures
and loading
currents. results
The simulated
results
are shown
in Figure
peratures
and
loading currents.
The simulated
are shown
in Figure
9b. Based
on 9b.
◦ C in TT case under the load
Based
on
the
nominal
value
of
V
(T)
of
1.1127
V
at
27
the nominal value of VOUT(T) of 1.1127OUT
V at 27 °C in TT case under the load current of 60
of 60 µA,
the maximum
variation
is mV
onlyacross
+1.8 mV/
−1.6 mVtemperature
across two extreme
μA, current
the maximum
variation
is only +1.8
mV/−1.6
two extreme
corcorners.
For other
loadand
currents
of 0the
µAchange
and 500ofµA,
the
VOUT (T) is
ners.temperature
For other load
currents
of 0 μA
500 μA,
VOUT
(T)change
is +2.9ofmV/−1.8
mV/
1.8 mV
at 27 ◦of
C. process
For variation
of process
VOUT (T) by
shifts
up/down
mV+2.9
at 27
°C.−For
variation
corners,
VOUT(T)corners,
shifts up/down
about
+11.3 by
aboutmV
+11.3
mV/
9.7 mV from
thecase.
nominal
case. This
is considered
acceptably
mV/−9.7
from
the−nominal
value
This value
is considered
acceptably
small.
Besides, small.
it
◦
Besides,
it
is
observed
that
V
(T)
displays
an
increase
at
a
high
temperature
of
85
OUT
is observed that VOUT(T) displays an increase at a high temperature of 85 °C under FF cor- C
under
FF rise
corner
andcorner,
little rise
corner,
is dueintoIBthe
(T), causing
ner and
little
at TT
thisatisTT
due
to thethis
decrease
(T),decrease
causing in
theIBcircuit
more the
circuit
more
sensitive
to
biasing
parameters.
sensitive to biasing parameters.
Sensors 2021, 21, 7856
μA, the maximum variation is only +1.8 mV/−1.6 mV across two extreme temperature corners. For other load currents of 0 μA and 500 μA, the change of VOUT(T) is +2.9 mV/−1.8
mV at 27 °C. For variation of process corners, VOUT(T) shifts up/down by about +11.3
mV/−9.7 mV from the nominal value case. This is considered acceptably small. Besides, it
is observed that VOUT(T) displays an increase at a high temperature of 85 °C under FF cor12 of 20
ner and little rise at TT corner, this is due to the decrease in IB(T), causing the circuit more
sensitive to biasing parameters.
Sensors 2021, 21, x FOR PEER REVIEW
12 of 19
(a)
(b)
Figure 9.
9. (a)Temperature
(a)Temperature characteristic
characteristic of
of IIB(T);
(T); (b)Temperature
(b)Temperature characteristic
characteristic of
of V
VOUT(T).
Figure
B
OUT (T).
The comparison between the theoretical estimation of IB(T) and VOUT(T) on basis of
the theoretical
estimation
IB (T) 10a,b,
and VOUT
(T) on basis
of
(10) The
and comparison
(18) and theirbetween
simulation
results are depicted
inof
Figure
respectively.
It has
(10)
(18) and that
theirthe
simulation
results
are depicted
in Figure
respectively.
It has
beenand
suggested
theoretical
predictions
correlate
very 10a,b,
well with
the simulation
been
suggested
that the theoretical predictions correlate very well with the simulation
results
for both parameters.
results for both parameters.
(a)
(b)
Figure
Figure10.
10.Comparison
Comparisonbetween
betweentheoretical
theoreticalpredictions
predictionsand
andsimulation
simulationresults
resultsunder
undertypical
typicalcase
caseofof
(a)IIBB(T);
(T); (b)
(b) V
VOUT
OUT(T).
(a)
(T).
Besides,
simulations are
are conducted
conductedtotoobserve
observethe
thedropout
dropoutvoltage
voltage
unBesides, different simulations
under
der
three
process
corners,
V ±on
10%
VDD
and different
operation
temperatures
three
process
corners,
1.2 V1.2
± 10%
VDDon
and
different
operation
temperatures
in Figure
◦ C, 95.2 mV
in
11. The
results
have indicated
87.3 mV
the TT
at 27mV
11.Figure
The results
have
indicated
87.3 mV under
theunder
TT corner
at corner
27 °C, 95.2
under the
◦
◦ C. The dropout
under
the SS
corner
at 27
andunder
79.5 mV
under
the at
FF27corner
at 27
SS corner
at 27
°C, and
79.5C,mV
the FF
corner
°C. The
dropout
voltage has
voltage
has
been
observed
to
be
almost
invariant
to
the
change
of
supply
voltage;
few
been observed to be almost invariant to the change of supply voltage; a few mVashifts
mV
shifts
across
the
entire
operation
temperature
range
and
about
a
few
mV
change
over
across the entire operation temperature range and about a few mV change over extreme
extreme
process corners.
This
tochange
the total
of +9.9mV
mV/
−9.5the
mV
under PVT
the
process corners.
This led to
theled
total
of change
+9.9 mV/−9.5
under
extreme
extreme
PVT
case
consideration.
The
result
has
confirmed
that
the
dropout
voltage
exhibits
case consideration. The result has confirmed that the dropout voltage exhibits good imgood
immunity
the combined
PVT effect.
munity
against against
the combined
PVT effect.
Sensors 2021, 21, 7856
11. The results have indicated 87.3 mV under the TT corner at 27 °C, 95.2 mV under the
SS corner at 27 °C, and 79.5 mV under the FF corner at 27 °C. The dropout voltage has
been observed to be almost invariant to the change of supply voltage; a few mV shifts
across the entire operation temperature range and about a few mV change over extreme
process corners. This led to the total change of +9.9 mV/−9.5 mV under the extreme
PVT
13 of
20
case consideration. The result has confirmed that the dropout voltage exhibits good immunity against the combined PVT effect.
Figure 11.
11. Variation
of dropout
voltage
at different
process corners,
voltages
andvoltages
temperaFigure
Variation
of dropout
voltage
at different
processsupply
corners,
supply
tures.
and temperatures.
To demonstrate the performance of the PSR enhancer for sensor circuit application,
a Differential Difference Amplifier (DDA) [26], which serves as the instrumentational
amplifier for detecting a full bridge sensor signal is employed. For fair comparison, the
conventional enhancer and the proposed enhancer are designed with identical static power
consumption and identical supply voltage of 1.2 V using TSMC 40 nm CMOS technology.
Sensors 2021, 21, x FOR PEER REVIEW
13 of of
19
Table 3 summarizes the static power of building blocks in each design. The schematic
DDA is depicted in Figure 12. It is a standard architecture with the first- being a stage
folded-cascade differential amplifier and the second being a non-inverting gain stage with
a feedforward
path tothe
form
the push-pull
output
stage. The
current
of the
To demonstrate
performance
of the
PSR enhancer
for
sensorconsumption
circuit application,
DDA
is
60
µA
at
about
1.1
V
supply
line
from
each
enhancer.
This
is
treated
as
the
typical
a Differential Difference Amplifier (DDA) [26], which serves as the instrumentational amoperation condition for each enhancer. The performance summary is listed in Table 4.
plifier for detecting a full bridge sensor signal is employed. For fair comparison, the conventional enhancer and the proposed enhancer are designed with identical static power
Table 3. Power allocation in proposed and conventional enhancer with 1.2 V supply voltage.
consumption and identical supply voltage of 1.2 V using TSMC 40 nm CMOS technology.
Table 3 summarizes the static power of building blocksPower
in each
design. TheAdditional
schematic of
Output
Enhancer
Total Power
Bias Circuit
DDA is depicted in Figure 12. It is a standard architectureStage
with the first- being
Blocka stage
folded-cascade
and the
being a0.98
non-inverting
gainNone
stage with
Proposed Workdifferential
4.75 amplifier
µA
1.96second
µA
µA
a feedforward
of the
Conventionalpath to form the push-pull output stage. The current consumption
VREF Generator
4.75 µA
1.96 µA
0.98 µA
Design
8.67
DDA is
60 μA at about 1.1 V supply line from each enhancer. This is treated as
theµA
typical
operation condition for each enhancer. The performance summary is listed in Table 4.
Figure 12. Schematic of the DDA.
Table 3. Power allocation in proposed and conventional enhancer with 1.2 V supply voltage.
Enhancer
Proposed Work
Total
Power
4.75 μA
Conventional Design 4.75 μA
1.96 μA
Power Output
Stage
0.98 μA
1.96 μA
0.98 μA
Bias Circuit
Additional Block
None
VREF Generator 8.67
μA
Sensors 2021, 21, 7856
14 of 20
Table 4. Performance summary of the DDA.
Sensors 2021, 21, x FOR PEER REVIEW
Supply Voltage
Power Consumption
RL
CL
1.1 V
Open Loop Gain
60 µA
PSR
100 kΩ
CMRR
30 pF
Bandwidth
77.8 dB
−77.4 dB@1 Hz
315 Hz
Unit Gain Frequency
Phase Margin
2.2 MHz
69◦
87.4 dB
Input-Referred
Noise
√
97 nV/ Hz@1 kHz
The comparative simulation results are given in Figure 13 and Table 5. It can be conof 19
cluded that both low-frequency and high-frequency PSR are improved using the14proposed
design, with respect to the DDA designs with and without a conventional enhancer.
Figure
13. Comparison
of PSR
for DDA
under
different
design
cases.
Figure
13. Comparison
of PSR
for DDA
under
different
design
cases.
Table
5. Comparison
of PSR
lowatand
for DDA
design cases
powTable
5. Comparison
of at
PSR
lowhigh
andfrequency
high frequency
forunder
DDAdifferent
under different
design
cases
ered about 1.1 V from the respective enhancer with 1.2 V supply.
powered about 1.1 V from the respective enhancer with 1.2 V supply.
Frequency
Without Enhancer
Conventional Enhancer
Proposed Enhancer
Frequency
Without Enhancer
Conventional Enhancer
Proposed Enhancer
1 Hz
−77 dB
−105 dB
−115 dB
1 Hz
−77 dB
−105 dB
−115 dB
1 MHz
−26 dB
−32 dB
−50 dB
1 MHz
−26 dB
−32 dB
−50 dB
For time-domain evaluation, the respective noise signal with amplitude of 100
mVpp@1 For
MHz,
100 mVpp@10 evaluation,
kHz and 100 the
mVpprespective
@20 Hz is applied
the Vwith
DD of DDA
which of
time-domain
noise on
signal
amplitude
is configured
with
a closed-loop
gainkHz
of 20.
In this
simulation,
the input common-mode
100 mVpp @1
MHz,
100 mVpp @10
and
100 mV
pp @20 Hz is applied on the VDD of
dc signal
is 550 is
mV,
whereas the
signal
is 20
The time-domain
DDA which
configured
withdifferential-mode
a closed-loop gain
of 20.
InmV
thispp.simulation,
the input
output
responses ofdcthe
DDA,
are compared
with
without the proposed
common-mode
signal
is 550
mV, whereas
theand
differential-mode
signal isenhancer
20 mVpp in
. The
Figure
14.
It
can
be
observed
that
the
supply
noise
associated
with
the
amplified
input
time-domain output responses of the DDA, are compared with and without the proposed
signal
is significantly
the output
DDA.
enhancer
in Figure attenuated
14. It can beat
observed
thatof
the
supply noise associated with the amplified
input signal is significantly attenuated at the output of DDA.
For time-domain evaluation, the respective noise signal with amplitude of 100
mVpp@1 MHz, 100 mVpp@10 kHz and 100 mVpp@20 Hz is applied on the VDD of DDA which
is configured with a closed-loop gain of 20. In this simulation, the input common-mode
dc signal is 550 mV, whereas the differential-mode signal is 20 mVpp. The time-domain
output responses of the DDA, are compared with and without the proposed enhancer in
Sensors 2021, 21, 7856
Figure 14. It can be observed that the supply noise associated with the amplified input
signal is significantly attenuated at the output of DDA.
2021, 21, x FOR PEER REVIEW
15 of 20
15 of 19
(a)
(b)
(c)
Figure 14. Comparison
of time-domain
outputofresponses
of DDAs
with and
without
proposed
Figure 14. Comparison
of time-domain
output responses
DDAs with
and without
proposed
enhancer
at endifferent noise
hancer
at@1
different
noise
mV(c)
pp@1
100
mVpp@10 kHz; (c) 100 mVpp@20 Hz.
levels: (a) 100
mVpp
MHz; (b)
100levels:
mVpp(a)
@10100
kHz;
100MHz;
mVpp(b)
@20
Hz.
Figure 15 depicts
the spread
of output
voltage
for the voltage
proposed
and enhancer, and
Figure
15 depicts
the spread
of output
forPSR
the enhancer,
proposed PSR
the conventional
at a typicalone
loadatcurrent
of load
60 μA
is compared
with
the Monte-Carlo
theone
conventional
a typical
current
of 60 µA
is compared
with the Monte-Carlo
pertaining
process andvariations.
temperature
variations.
With 200 simulation
simulation runssimulation
pertainingruns
to process
and to
temperature
With
200 simulation
thevoltage
mean output
voltage of enhancer
the proposed
enhancer
is between
1.1106VV to 1.1140 V at
runs, the mean runs,
output
of the proposed
is between
1.1106
V to 1.1140
different temperatures.
maximum
standard
derivation
at different temperatures.
As observed, As
the observed,
maximumthe
standard
derivation
is about
6.5 mVis about 6.5 mV
across
the
operation
temperature
range.
On
the
contrary,
the
conventional
across the operation temperature range. On the contrary, the conventional design displaysdesign displays
thevoltage
mean output
voltage
1.0735 V
V, but the
maximum standard
the mean output
between
1.0735between
V and 1.10465
V, and
but 1.10465
the maximum
standard
reach100
upmV.
to about
100 mV.toCompared
to the conventional
derivation can derivation
reach up tocan
about
Compared
the conventional
circuit withcircuit
(i) with (i) 2.9%
VOUT
and≈100
(ii) ∆V
≈ 100 mVstandard
in maximum
standard
2.9% change inchange
mean Vin
OUTmean
and (ii)
ΔVOUT
mVOUT
in maximum
derivation,
thederivation, the
proposed
displaysin0.3%
change
mean
VOUT
and
∆Vfor
≈ 6.5 mV for maximum
OUT
proposed design
displaysdesign
0.3% change
mean
VOUT in
and
ΔVOUT
≈ 6.5
mV
maximum
standard
derivation,
respectively.
From
these
results,
the
proposed
design
standard derivation, respectively. From these results, the proposed design offers
veryoffers very good
stability
of
output
voltage
in
worst
case
consideration.
Consider
the
process
good stability of output voltage in worst case consideration. Consider the process sensi- sensitivity, it is
defined
as (Standard
Derivation/Mean
value)
× 100%.
This
gives
7.028%for
for conventional
tivity, it is defined
as (Standard
Derivation/Mean
value)
× 100%.
This
gives
7.028%
◦ C. This shows that the proposed work
design
and
0.514%
for
the
proposed
design
at
27
conventional design and 0.514% for the proposed design at 27 °C. This shows that the
.
proposed workhas
hasaa14-fold
14-foldimprovement
improvementin
inthe
the reduction
reductionof
of process
process sensitivity
sensitivity for
for V
VOUT
OUT.
Sensors 2021, 21, 7856
proposed design displays 0.3% change in mean VOUT and ΔVOUT ≈ 6.5 mV for maximum
standard derivation, respectively. From these results, the proposed design offers very
good stability of output voltage in worst case consideration. Consider the process sensitivity, it is defined as (Standard Derivation/Mean value) × 100%. This gives 7.028% for
conventional design and 0.514% for the proposed design at 27 °C. This shows that the
16 of 20
proposed work has a 14-fold improvement in the reduction of process sensitivity for VOUT.
Sensors 2021, 21, x FOR PEER REVIEW
16 of 19
(a)
(b)
(c)
(d)
(e)
(f)
◦ C; (b)
◦ C;
Figure15.
15.Monte-Carlo
Monte-Carlo
simulation
ofOUT
VOUT
ofproposed
the proposed
enhancer
(a) °C;
@−(b)
20 @27
Figure
simulation
of V
of the
enhancer
(a) @−20
°C; @27
(c) @80
◦
◦
◦
◦
°C;
and
conventional
enhancer
(d)
@−20
°C;
(e)
@27
°C;
(f)
@80
°C.
(c) @80 C; and conventional enhancer (d) @−20 C; (e) @27 C; (f) @80 C.
ForT.C.
T.C.evaluation,
evaluation,Figure
Figure
16a
shows
output
voltage
change
against
the temFor
16a
shows
thethe
output
voltage
change
against
the temperperature
for
the
proposed
and
conventional
PSR
enhancer
under
60
µA
typical
loading
ature for the proposed and conventional PSR enhancer under 60 μA typical loading
concondition
and
1.2
V
supply
voltage,
Over
the
entire
operation
temperature
range,
the
dition and 1.2 V supply voltage, Over the entire operation temperature range, the variavariation
ofisVonly
only
3.38
in the proposed
whereas
9.71inmV
the
tion
of VOUT
3.38
mV
in mV
the proposed
design,design,
whereas
that ofthat
9.71ofmV
thein
conOUT is
◦ C and 87.60 ppm/◦ C
conventional
design.
This yields
the nominal
ofppm/°C
30.38 ppm/
ventional
design.
This yields
the nominal
T.C. ofT.C.
30.38
and 87.60
ppm/°C for both
for bothrespectively.
circuits, respectively.
are considered
comparable
in nominal
operation
concircuits,
They are They
considered
comparable
in nominal
operation
conditions.
ditions.
In
order
to
assess
the
sustainability
of
T.C.
under
process
variation,
Figure
16b
In order to assess the sustainability of T.C. under process variation, Figure 16b depicts the
depicts
the
Monte-Carlo
simulation
results
of
the
T.C.
for
V
in
both
circuits.
The
OUT The obtained mean
Monte-Carlo simulation results of the T.C. for VOUT in both circuits.
◦ C and
obtained
mean T.C.
and standard
the is
proposed
work and
is 29.4
T.C.
and standard
derivation
of thederivation
proposed of
work
29.4 ppm/°C
8.7ppm/
ppm/°C,
re◦
8.7 ppm/ These
C, respectively.
These
figures are
interpreted
as at and
least100
10 times
100 times
spectively.
figures are
interpreted
as at
least 10 times
times and
smaller
than
smaller
thanconventional
those of the counterpart
conventionalunder
counterpart
under MCItevaluation.
It has
suggested
those
of the
MC evaluation.
has suggested
that
it is not
that
it
is
not
easy
for
the
conventional
circuit
to
sustain
its
output
stability
against
the
easy for the conventional circuit to sustain its output stability against the temperature and
temperature
and
process
variation
when
encountering
small
dropout
voltage
design.
process variation when encountering small dropout voltage design.
Figure 17 illustrates the load transient responses with two load current steps for 60 µA
and 500 µA for each enhancer based on the circuit capacitive load of 5 pF. At the edge time
of 300 ns, the undershoots of the proposed work are 47.3 mV@60 µA and 90.6 mV@500 µA,
whereas the overshoots are 30.8 mV@60 µA and 73.3 mV@500 µA, respectively. Referring
to the conventional design, the undershoots are 78.7 mV@60 µA and 140.5 mV@500 µA
and the overshoots are 57.9 mV@60 µA and 95.0 mV@500 µA. It can be concluded that the
proposed enhancer has achieved smaller undershoot and overshoot. This has demonstrated
the advantage of using LSFVF topology for ease of obtaining better transient metrics.
(a)
(b)
Figure 16. Comparison between conventional design and proposed work of (a) temperature characteristic of VOUT under nominal case; (b) Monte-Carlo simulation of T.C. of VOUT.
Figure 17 illustrates the load transient responses with two load current steps for 60
μA and 500 μA for each enhancer based on the circuit capacitive load of 5 pF. At the edge
Sensors 2021, 21, 7856
In order to assess the sustainability of T.C. under process variation, Figure 16b depicts the
Monte-Carlo simulation results of the T.C. for VOUT in both circuits. The obtained mean
T.C. and standard derivation of the proposed work is 29.4 ppm/°C and 8.7 ppm/°C, respectively. These figures are interpreted as at least 10 times and 100 times smaller than
those of the conventional counterpart under MC evaluation. It has suggested that it17isofnot
20
easy for the conventional circuit to sustain its output stability against the temperature and
process variation when encountering small dropout voltage design.
(a)
(b)
Sensors 2021, 21, x FOR PEER REVIEWFigure
17characofchar19
Figure16.
16.Comparison
Comparisonbetween
betweenconventional
conventionaldesign
designand
andproposed
proposedwork
work
temperature
ofof
(a)(a)
temperature
acteristic
ofOUT
VOUTunder
undernominal
nominalcase;
case;
(b)
Monte-Carlo
simulation
T.C.
VOUT. .
teristic
of V
(b)
Monte-Carlo
simulation
ofof
T.C.
ofof
VOUT
Figure 17 illustrates the load transient responses with two load current steps for 60
μA and 500 μA for each enhancer based on the circuit capacitive load of 5 pF. At the edge
time of 300 ns, the undershoots of the proposed work are 47.3 mV@60 μA and 90.6
mV@500 μA, whereas the overshoots are 30.8 mV@60 μA and 73.3 mV@500 μA, respectively. Referring to the conventional design, the undershoots are 78.7 mV@60 μA and 140.5
mV@500 μA and the overshoots are 57.9 mV@60 μA and 95.0 mV@500 μA. It can be concluded that the proposed enhancer has achieved smaller undershoot and overshoot. This
has demonstrated the advantage of using LSFVF topology for ease of obtaining better
transient metrics.
(a)
(b)
(c)
(d)
Figure
Figure17.
17.Transient
Transientresponse
responsewith
with6060μA
µAcurrent
currentpulse
pulseofof(a)
(a)conventional
conventionaldesign;
design;(b)
(b)proposed
proposed
work;
and
with
500
μA
current
pulse
of
(c)
conventional
design;
(d)
proposed
work.
work; and with 500 µA current pulse of (c) conventional design; (d) proposed work.
Thecomparison
comparisonbetween
betweenthe
theconventional
conventionalPSR
PSRenhancer
enhancerand
andthe
theproposed
proposedwork
workisis
The
summarized
in
Table
6.
As
can
be
revealed,
the
proposed
enhancer
offers
better
perforsummarized in Table 6. As can be revealed, the proposed enhancer offers better performance
such
as
reduced
process
sensitivity
in
V
,
improved
transient
metrics,
mance such as reduced process sensitivity in VOUT,OUT
improved transient metrics, betterbetter
PSR
PSR metrics
and simpler
topology
with respect
to of
those
of conventional
metrics
and simpler
circuitcircuit
topology
with respect
to those
conventional
designdesign
at iden-at
identical
consumption,
and process
technology
under low-power
tical
powerpower
consumption,
supplysupply
voltagevoltage
and process
technology
under low-power
circuit
circuit Further
design. performance
Further performance
enhancement
canachieved
also be achieved
if higher
power is
design.
enhancement
can also be
if higher power
is allowed
in the design.
inallowed
the design.
Table 6. Performance comparison of the simulation results between the conventional PSR enhancer
and the Proposed Work at Typical Case.
Conventional Design
This Work
Sensors 2021, 21, 7856
18 of 20
Table 6. Performance comparison of the simulation results between the conventional PSR enhancer
and the Proposed Work at Typical Case.
Process Technology
Power Transistor Size
Current Consumption IQ (µA)
Supply Voltage (V)
VOUT @60 µA_Load (V)
Minimum ILOAD, min (µA)
Maximum ILOAD, max (µA)
∆ILOAD (µA)
Voltage Reference Required
Op-amp Required
∆VOUT (−20–80 ◦ C) (mV)
PSR Bandwidth (kHz)
PSR @ 1 Hz, 1 MHz (dB)
Mean of VOUT (V), 200 samples
SD of VOUT (mV), 200 samples
T.C. (1 sample @nominal) (ppm/◦ C)
Mean T.C. (200 samples) (ppm/◦ C)
SD T.C. (200 samples) (ppm/◦ C)
Process Sensitivity for VOUT
Edge Time (µs)
∆VOUT (mV) @500 µA
Edge Time Ratio K
FOM3 [27] (mV)
Conventional Design
This Work
40 nm CMOS
PMOS (1 mm/160 nm)
4.75
1.2
1.1085
0
500
500
Yes
Yes
9.71 1
65.5
−31.6, −8.1
1.0920
76.7
87.60 1
320.6 2
779.8
7.028%
0.3
140.5
1
1.33475
40 nm CMOS
PMOS (1 mm/160 nm)
4.75
1.2
1.1127
0
500
500
No
No
3.38 1
107.2
−36.0, −20.2
1.1123
5.72
30.38 1
29.4 2
8.7
0.514%
0.3
90.6
1
0.86070
1
At TT corner with 60 µA load condition 2 Monte-Carlo simulation results under 60 µA load condition and
T.C. = [∆VOUT /(∆T × VOUT_normal )] × 106 ppm/◦ C, VOUT_normal = VOUT @27 ◦ C 3 FOM = K·∆VOUT · (IQ +
ILOAD, min )/∆ILOAD .
5. Conclusions
A new PVT-insensitive dropout voltage based PSR enhancer on the basis of LSFVF
topology dedicated to sensor circuit applications is presented. Its functions are similar
to the second regulator, which is inserted between the main regulator and the sensor
circuit and is subject to performance degradation under a noisy supply line. Through the
proposed topological temperature compensation method, the new CTAT current source, the
replica circuit block design approach and all MOS transistors design approaches in critical
circuit building blocks for obtaining better tracking characteristics, the proposed work
permits a small value of dropout voltage in the design whilst providing good immunity
against PVT variation. This is translated to the good stability of output voltage. The
circuit is verified by extensive simulation results. Besides, the circuit eliminates the use
of operational amplifier(s) as well as the voltage reference. Taking advantage of circuit
simplicity, it reduces the silicon area and dissipates low static power consumption. The
proposed PSR enhancer and its circuit design techniques will be easily extended to other
analog circuit applications, in which the supply voltage headroom, the stability of dropout
voltage and the limited circuit’s PSR parameter are of main concern.
Author Contributions: Conceptualization: J.Z., P.K.C.; Validation: J.Z. and P.K.C.; Writing: J.Z.; Review and Editing: P.K.C. All authors have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.
Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.
Data Availability Statement: Not applicable.
Conflicts of Interest: The authors declare no conflict of interest.
Sensors 2021, 21, 7856
19 of 20
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