ELECTRONIC DEVICES
AND CIRCUITS
S Salivahanan is the Principal of SSN College of Engineering,
Chennai. He obtained his B.E. in Electronics and Communication
Engineering from PSG College of Technology, Coimbatore; M.E.
degree in Communication Systems from NIT, Trichy, and Ph.D.
in the area of Microwave Integrated Circuits from Madurai
Kamaraj University. He has over three decades of teaching,
research, administration and industrial experience, both in
India and abroad, with stints at NIT, Trichy, A.C. College of Engineering and
Technology, Karaikudi; R.V. College of Engineering, Bangalore; Dayananda Sagar
College of Engineering, Bangalore; Mepco Schlenk Engineering College, Sivakasi;
and Bannari Amman Institute of Technology, Sathyamangalam.
Dr Salivahanan served as a mentor for the M.S. degree under the distance-learning
programme offered by Birla Institute of Technology and Science, Pilani. He has
industrial experience as Scientist/Engineer at Space Applications Centre, ISRO,
Ahmedabad; Telecommunication Engineer at State Organisation of Electricity,
Iraq; and Electronics Engineer at Electric Dar Establishment, Kingdom of Saudi
Arabia.
He is the author of 26 popular books which include Basic Electrical, Electronics
and Computer Engineering; Electronic Devices and Circuits and Linear Integrated
Circuits, all published by McGraw Hill Education (India), and Digital Signal
Processing by McGraw Hill Education (India) and McGraw-Hill International
which has also been translated into Mandarin, the most popular version of the
Chinese language. He has published several papers at national and international
levels.
Professor Salivahanan is the recipient of Bharatiya Vidya Bhavan National Award
for Best Engineering College Principal for 2011 from ISTE, and IEEE Outstanding
Branch Counsellor and Advisor Award in the Asia-Pacific region for 1996–97.
He was the Chairman of IEEE Madras Section for two years, 2008 and 2009, and
Syndicate Member of Anna University.
He is a Senior Member of IEEE, Fellow of IETE, Fellow of Institution of Engineers
(India), Life Member of ISTE and Life Member of Society for EMC Engineers.
He is also a member of IEEE Societies in Microwave Theory and Techniques,
Communications, Signal Processing, and Aerospace and Electronics.
N Suresh Kumar is the Principal of Velammal College of
Engineering and Technology, Madurai. He received his B.E.
degree in Electronics and Communication Engineering from
Thiagarajar College of Engineering, Madurai; M.E. degree
in Microwave and Optical Engineering from A.C. College of
Engineering Technology, Karaikudi; and Ph.D. degree in the field
of EMI/EMC from Madurai Kamaraj University. He has over two
decades of teaching, administration and research experience and has authored
8 books, all published by McGraw Hill Education (India). He has published and
presented many research papers in international journals and conferences. His
areas of interest include Microwave Communication, Optical Communication and
Electromagnetic Compatibility. He is a life member of IETE and ISTE.
ELECTRONIC DEVICES
AND CIRCUITS
S Salivahanan
Principal
SSN College of Engineering
Chennai, Tamil Nadu
N Suresh Kumar
Principal
Velammal College of Engineering and Technology
Madurai, Tamil Nadu
McGraw Hill Education (India) Private Limited
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Electronic Devices and Circuits
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Cover:
Preface
ix
1.1 Introduction 1.1
1.2 Insulator, Semiconductor and Metal Classification using
Energy-band Diagrams 1.1
1.3 Semiconductor—Mobility and Conductivity 1.3
1.4 Classification of Semiconductors 1.7
1.5 Drift and Diffusion Currents 1.10
1.6 Charge Densities in Semiconductors 1.13
1.7 Hall Effect 1.19
1.8 Continuity Equation 1.22
1.9 Law of Junction 1.26
1.10 Fermi–dirac Function 1.28
1.11 Fermi Level in Intrinsic and Extrinsic Semiconductors 1.30
Review Questions 1.36
Objective-Type Questions 1.37
Answers 1.39
2.2
2.3
2.4
2.5
2.6
Theory of PN Junction Diode 2.1
Quantitative Theory of PN Diode Currents 2.5
Diode Current Equation 2.8
V–I Characteristics 2.10
Temperature Dependence of V-I Characteristics
of Diodes 2.14
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
Diode Resistance 2.19
Diode Capacitance 2.25
Energy-Band Diagram of PN Junction Diode 2.31
Zener Diode 2.32
Breakdown Mechanisms 2.33
Zener Diode Applications 2.35
Light Emitting diode (LED) 2.43
Liquid Crystal Display (LCD) 2.45
Junction Type Photoconductive Cell 2.47
Varactor Diode 2.50
Tunnel Diode 2.51
PNPN Diode (Shockley Diode) 2.55
SCR (Silicon Controlled Rectifier) 2.55
TRIAC (Triode a.c. Switch) 2.64
DIAC (Diode a.c. switch) 2.66
UJT (Unijunction Transistor) Relaxation Oscillator 2.67
Review Questions 2.71
Objective-Type Questions 2.74
Answers 2.80
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Introduction 3.1
Linear Mode Power Supply 3.1
P—N Junction Diode as a Rectifier 3.2
Basic Rectifier Setup 3.3
Comparison of Rectifiers 3.22
Harmonic Components in a Rectifier Circuit 3.25
Filters 3.26
Comparison of Filters 3.40
Review Questions 3.40
Objecvtive-Type Questions 3.42
Answers 3.45
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Introduction 4.1
Bipolar Junction Transistor 4.1
Transistor Current Components 4.2
Operation of a NPN Transistor 4.2
Operation of PNP Transistor 4.4
Transistor Configuration 4.6
Transistor as an Amplifier 4.16
4.8 Large Signal, d.c. and Small Signal CE Values
of Current Gain 4.17
4.9 Ebers–Moll Model 4.30
4.10 Breakdown in Transistors 4.32
4.11 Phototransistor 4.34
4.12 Typical Transistor Junction Voltage Values 4.35
4.13 Types of FET 4.35
4.14 Construction of N-Channel JFET 4.35
4.15 Operation of N-Channel JFET 4.38
4.16 Characteristic Parameters of the JFET 4.41
4.17 Expression for Saturation Drain Current 4.45
4.18 Slope of the Transfer Characteristic at Idss 4.47
4.19 Comparison of JFET and BJT 4.49
4.20 Applications of JFET 4.49
4.21 Metal Oxide Semiconductor Field Effect Transistor
(MOSFET) 4.50
4.22 Enhancement Mosfet 4.50
4.23 Depletion Mosfet 4.52
4.24 Comparison of MOSFET with JFET 4.55
4.25 Handling Precautions for Mosfet 4.55
4.26 Comparison of N- with P-Channel Mosfets 4.57
4.27 Comparison of N- with P-Channel FETs 4.57
4.28 Use of JFET as Voltage-Variable Resistor 4.58
4.29 Applications of MOSFET in CMOS Circuits 4.58
4.30 Advantages of BJT Over MOSFET 4.60
Review Questions 4.61
Objective-Type Questions 4.63
Answers 4.70
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction 5.1
Bias Stability 5.1
Methods of Transistor Biasing 5.9
Bias Compensation 5.40
Thermal Stability and Heat Sink 5.43
Biasing the FET 5.46
Biasing the Mosfet 5.50
Review Questions 5.64
Objective-Type Questions 5.65
Answers 5.69
6.2 Two-Port Devices and Network Parameters 6.1
6.3 The Hybrid Model for Two-port Network 6.4
6.4 Analysis of a Transistor Amplifier Circuit using
h-parameters 6.7
6.5 Simplified CE Hybrid Model 6.16
6.6 Analysis of CE Configuration using Approximate Model 6.18
6.7 Analysis of CC amplifier using the Approximate Model 6.23
6.8 Analysis of CB Amplifier using the Approximate Model 6.26
6.9 BJT Amplifiers 6.29
6.10 Single Stage Amplifiers 6.30
6.11 Small Signal Analysis of Single Stage BJT Amplifiers 6.35
6.12 Distortion in Amplifiers 6.63
6.13 Miller’s Theorem and its Dual 6.64
6.14 Design of Single Stage RC Coupled Amplifier using BJT 6.66
6.15 FET Amplifiers 6.71
6.16 The FET Small-signal Model 6.80
Review Questions 6.83
Objective-Type Question 6.85
Answers 6.88
Appendix A: Specifications of Semiconductor Devices
Appendix B: Probable Value of General Physical Constants
Appendix C: Conversion Factors and Prefixes
A.1
A.11
A.12
Explosive development and exciting progress have occurred in the field of electronics in the past few decades. A large number of solid-state devices and integrated circuits incorporating millions of active devices on a single chip have
been invented. The past four decades have witnessed several unprecedented
and exciting developments in the field of electronics. Hence, Electronic Devices
and Circuits has become an important core subject in the field of Electronics,
Electrical, Computer Science, Instrumentation and Mechanical Engineering.
The study of electronic devices and circuits provides an opportunity to explore
the operation of electronic devices, mainly diodes and transistors, two of the
most important building blocks in electronic circuits. A single textbook covering
all aspects of semiconductor devices and circuits satisfying the requirements of
engineering college teachers and students is the need of the day. We have made
a sincere attempt to bring out such a textbook.
The text is based on a series of lecture courses given to electronics, electrical and
computer engineering undergraduates in their first, second and (part of) third
years and, hence, the coverage of the subject has been organised in a more logically acceptable manner. The language used in explaining the various concepts
is extremely simple. Since a proper understanding of the subject would involve a
serious attempt to solve a variety of problems, a wide variety of problems with
step-by-step solutions are provided for every concept.
Pedagogy includes
150 Solved Examples
180 MCQ
200 Figures
This book is divided into 6 units. Unit 1 deals with Semiconductor Physics. Unit 2
explains Junction Diode Characteristics and Special Semiconductor Devices in
great detail. Unit 3 explains the concepts of rectifiers and filters. Unit 4 deals
with transistor characteristics of both BJT and FET. Unit 5 deals with transistor
biasing and thermal stabilisation. Unit 6 deals with Small Signal Low Frequency
Transistor Amplifier models of both BJT and FET.
We sincerely thank the managements of SSN College of Engineering, Chennai,
and Velammal College of Engineering and Technology, Madurai, for their constant encouragement, and for providing necessary facilities for completing this
project. We express our deep gratitude to Dr. P. Balakrishnan, Former Director
of Directorate of Technical Education, Government of Tamil Nadu, for giving
a Foreword to the first edition of this book. We express thanks to our colleagues
for their useful comments, which have improved the book considerably over the
previous edition. We are thankful to Mr. S. Karthie alias Ayyadurai, Assistant
Professor, SSN College of Engineering, for his help in the preparation of additional material and proof correction.
We are highly appreciative of Mr. S. Sankar Kumar for efficiently word processing the manuscript of the first edition. Our thanks are also due to Mr.
R. Gopalakrishnan for word processing the additional manuscript. We are
grateful to the editorial and production teams including Mrs. Vibha Mahajan,
Mr. Ebi John Amos and Ms. Shalini Jha of McGraw Hill Education (India) for
their initiation and support to bring out this book in a short span of time.
We would also like to take this opportunity to thank the numerous reviewers for
their useful comments and suggestions. Their names are given below:
G Ramakrishna
Vaishnavi Institute of Technology, Chittoor, Andhra Pradesh
A Hazrathiah
Narayana Engineering College, Nellore, Andhra Pradesh
P Rajesh Kumar
University College of Engineering, Vishakhapatnam, Andhra
Pradesh
Vijayakishore
Srinivasa Institute of Technology & Management Studies,
Chittor
Professor Salivahanan is greatly thankful to his wife, Kalavathy, and sons
Santhosh Kanna and Subadesh Kanna; Professor Suresh Kumar expresses
his heartfelt thanks to his wife, Andal, and daughters Sree Naga Gowri and
Sree Naga Vani for their spirit of self-denial and enormous patience during the
preparation of this book. We welcome suggestions for the improvement of the
book.
S. SALIVAHANAN
N. SURESH KUMAR
McGraw-Hill Education (India) invites suggestions and comments from you,
all of which can be sent to info.india@mheducation.com (kindly mention the title
and author name in the subject line).
Piracy-related issues may also be reported.
II Year-1 SEMESTER
T
P
C
3+1
0
3
Semi Conductor Physics: Insulators, Semi conductors and Metals classification using energy band diagrams, mobility and conductivity, electrons
and holes in intrinsic semi conductors, extrinsic semi conductors, drift and
diffusion, charge densities in semiconductors, Hall effect, continuity equation, low of junction, Fermi Dirac function, Fermi level in intrinsic and
extrinsic Semiconductors
UNIT-II
Junction Diode Characteristics: Open circuited p-n junction, Biased p-n
junction, p-n junction diode, current components in PN junction Diode,
diode equation, V-I Characteristics, temperature dependence on V-I characteristics, Diode resistance, Diode capacitance, energy band diagram of
PN junction Diode.
Special Semiconductor Devices: Zener Diode, Breakdown mechanisms,
Zener diode applications, LED, LCD, Photo diode, Varactor diode,
Tunnel Diode, DIAC, TRIAC, SCR, UJT. Construction, operation and
characteristics of all the diodes is required to be considered.
UNIT-III
Rectifiers and Filters: Basic Rectifier setup, Half wave rectifier, full wave
rectifier, bridge rectifier derivations of characteristics of rectifiers, rectifier
circuits-operation, input and output waveforms; Filters; Inductor filter,
Capacitor filter, L-section filter, p-section filter, Multiple L-section and
Multiple-section filter, comparison of various filter circuits in terms of
ripple factors.
UNIT-IV
Transistor Characteristics:
BJT: Junction transistor, transistor current components, transistor equation, transistor configurations, transistor as an amplifier, characteristics
of transistor in Common Base, Common Emitter and Common Collector
configurations, Ebers-Moll model of a transistor punch through/reach
through, photo transistor, typical transistor junction voltage values.
FET: FET types, construction, operation, characteristics, parameters,
MOSFET-type, construction, operation, characteristics, comparison
between JFET and MOSFET.
UNIT-V
Transistor Biasing and Thermal Stabilization: Need for biasing, operating
point, load line analysis, BJT biasing-methods, basic stability, fixed bias,
collector to base bias, selfbias, Stabilization against variations in VBE, Ic,
and stability factors, (S, S¢, S¢¢), compensation, Thermal runaway, Thermal
stability. FET Biasing-methods and stabilization.
UNIT-VI
Small Signal Low Frequency Transistor Amplifier Methods:
BJT: Two port network, Transistor hybrid model, determination of
h-parameters, conversion of h-parameters, generalized analysis of transistor amplifier model using h-parameters, Analysis, of CB, CE and CC
amplifier using exact and approximate analysis, Comparison of transistor
amplifiers.
FET: Generalized analysis of small signal model, Analysis of CG, CS and
CD amplifiers, comparison of FET amplifiers.
Electronics has been defined as that branch of science and technology which relates
to the conduction of electricity through vacuum by electrons alone or through gases
by electrons and ions. Basically, it is a study of electron devices and their utilization. An electron device is that in which electrons flow through a vacuum or gas
or semiconductor. In the beginning of the 20th century, electron theory began to
take technological shape and it has enjoyed an explosive development in the last
four decades.
Electronics has a wide range of applications, such as, rectification, amplification, power generation, industrial control, photo-electricity, communications,
and so on. The electronic industry turns out a variety of items in the range of
consumer electronics, control and industrial electronics, communication and
broadcasting equipment, biomedical equipment, calculators, computers, microprocessors, aerospace and defence equipment and components.
A semiconductor is a material that has a resistivity value in between that of a
conductor and an insulator. The conductivity of a semiconductor material can
be varied under an external electric field. Devices made from semiconductor
materials are the foundation of modern electronics which includes radios, computers, telephones, and many other devices. Semiconductor devices include the
transistor, many kinds of diodes including the light emitting diode, the silicon
controlled rectifier, and digital and analog integrated circuits.
This chapter deals with the classification of semiconductors based on energyband diagrams. It also discusses doping in semiconductors, Hall effect and
Fermi level in semiconductors.
A very poor conductor of electricity is called an insulator; an excellent conductor is a metal; and a material whose conductivity lies between these two extremes
is a semiconductor. A material may be classified as one of these three depending
upon its energy-band structure.
An insulator is a material having extremely poor electrical conductivity. The
energy-band structure indicated schematically in Fig. 1.1(a). The forbidden
energy gap is large; for diamond the gap energy is about 6 eV. If additional
energy is given to an electron in the upper level of valence band, this electron
attempts to cross the forbidden energy gap and enter the conduction band.
However in an insulator, the additional energy which may ordinarily be given to
an electron is, in general, much smaller than this high value of forbidden energy
gap. Hence no electrical conduction is possible. The number of free electrons in
an insulator is very small, roughly about 107 electrons/m3.
Conduction
band
Free
electrons
Eg = 6 eV
CB
Forbidden
band
Eg = 1 eV
VB
Holes
Valence
band
(a)
(b)
(c)
valence and conduction bands. The valence band is only partially filled and the
conduction band extends beyond the upper end of filled valence band. The outer
electrons of an atom are as much associated with one ion as with another, so
that the electron attachment to any individual atom is almost zero. The band
occupied by the valence electrons may not be completely filled and that there are
no forbidden levels at higher energies. Depending upon the metal, at least one,
and sometimes two or three, electrons per atom are free to move throughout the
interior of the metal under the action of applied fields. When an electric field
is applied, few electrons may acquire enough additional energy and move to
higher energy within the conduction band. Thus the electrons become mobile.
Since the additional energy required for transfer of electrons from valence band
to conduction band is extremely small, the conductivity of metal is excellent.
In electron-gas theory description of a metal, the metal is visualized as a region
containing a periodic three-dimensional array of heavy, tightly bound ions permeated with a swarm of electrons that may move about quite freely. According
to this theory, the electrons in a metal are continuously moving and the direction
of flight changes whenever the electron collides with other electrons. The average distance travelled by an electron between successive collisions is called as
mean-free-path of an electron. In the absence of any applied potential, the average current in a metal is zero because the number of electrons passing through
unit area in any direction is almost same as the number of electrons passing
through the same unit area in the opposite direction. This can be attributed to
the random nature of motion of electrons.
When a constant electric field E (volts per metre) is applied to a metal, the electrons would be accelerated and the velocity would increase indefinitely with time.
However, because of collision of electrons, electrons lose energy and a steadystate condition is reached where a finite value of drift velocity vd is attained. The
drift velocity, vd is in the direction opposite to that of the electric field and its
magnitude is proportional to E. Thus,
vd = mE
(1.1)
where m = mobility of the electron, m2/volt-second. Due to the applied field,
a steady-state drift velocity has been superimposed upon the random thermal
motion of the electrons. Such a directed flow of electrons constitutes a current.
If the concentration of free electrons is n (electrons per cubic meter), the current
density J (amperes per square metre) is
where
J = nqvd = nqmE = sE
(1.2)
s = nqm
(1.3)
–1
s is the conductivity of the metal in (ohm-metre) . For a good conductor n is
very large, approximately, 1028 electrons/m3. Equation (1.2) can be recognized
as Ohm’s law which states that the conduction current density is proportional to
the applied electric field. The energy acquired by the electrons from the applied
field is given to the lattice ions as a result of collisions. Hence, power is dissipated within the metal by the electrons, and the power density (Joule heat) is
given by
JE = sE 2 watts/metre3
(1.4)
The conductivity of a material is proportional to the concentration of free electrons. The number of free electrons in a semiconductor lies between 107 and
1028 electrons/m3. Thus, a semiconductor has conductivity much greater than
that of an insulator but much smaller than that of a metal. Typically, semiconductor has forbidden energy gap of about 1 eV. The most important practical
semiconductor materials are germanium and silicon, which have values of Eg of
0.785 and 1.21 eV, respectively, at 0 degree Kelvin. Energies of this magnitude
normally cannot be acquired from an applied field. At low temperatures the
valence band remains full, the conduction band empty, and these materials are
insulators at low temperatures. The conductivity of these materials increases
with temperature and hence these materials are called as intrinsic semiconductors. As the temperature is increased, some of the electrons in the valence band
acquire thermal energy greater than the gap energy and move into the conduction band. These electrons are now free to move about under the influence of
even a small applied field. These free electrons, also called as conduction electrons, constitute for conduction and the material becomes slightly conducting.
The current density due to the motion of electrons is given by
Jn = nmnqE = snE
(1.5)
where, mn is the electron mobility, and the suffix ‘n’ represents that the respective
terms are due to motion of electrons. The absence of an electron in the valence
band is represented by a small circle and is called a hole. The hole may serve as
a carrier of electricity whose effectiveness is comparable with the free electron.
The hole conduction current density is given by
Jp = pmpqE = spE
(1.6)
where mp is the hole mobility and p is the hole concentration.
Hence, the total current density J in a semiconductor is given by
J = (nmn + pmp)qE = sE
(1.7)
where s = (nmn + pmp)q is the total conductivity of a semiconductor. For a pure
semiconductor (intrinsic semiconductor), the number of free electrons is exactly
same as the number of holes. Thus, the total current density is
J = ni (mn + mp) qE
(1.8)
where ni = n = p is the intrinsic concentration of a semiconductor.
The conductivity of an intrinsic semiconductor can be increased by introducing certain impurity atoms into the crystal. This results in allowable energy
states which lie in the forbidden energy gap and these impurity levels also contribute to the conduction. Such a semiconductor material is called an extrinsic
semiconductor.
An electron travelling through a crystal under the influence
of an externally applied field hardly notices the electrostatic field of the ions
making up the lattice, i.e. it behaves as if the applied field were the only one
present. This is the basis of the electron gas approximation and the assumption
will now be looked at a little more closely. If the electrons were to experience
only the applied field, E, then immediately after a collision it would accelerate
in the direction of the field with an acceleration a, proportional to the applied
force, i.e.
qE = ma
(1.9)
where the constant of proportionality is the electron mass, m. When quantum
theory is applied to the problem of an electron moving through a crystal lattice,
it predicts that under the action of an applied field the electron acceleration will
indeed be proportional to the field, but that the constant of proportionality will
be different from the normal mass of an electron:
qE = mna
(1.10)
The field due to the lattice ions can, therefore, be ignored providing we treat the
electrons inside the crystal as if they had a slightly different mass to the real electron mass or, to put it another way, the effect of the lattice ions on an electron is
to make it behave as if it had a different mass. This new mass is called the effective mass of the electron, mn, and the effective mass of a hole, mp, can be similarly defined. In general, mn and mp are not the same. Usually, mn is of the same
order as m; in germanium, for instance, mn = 0.2 m and in silicon, mn = 0.4 m.
The value of effective mass is an important parameter for any semiconductor,
especially from the device point of view. Certain semiconductors, for instance,
have low electron effective mass and hence high electron mobility. This makes
them very suitable for high-frequency devices. The III-V semiconductor GaAs
comes into this category and some of the best microwave transistors are made
from this material.
In a pure semiconductor, the number of holes is equal to the number of electrons. Thermal agitation continues to produce new electron-hole pairs and the
electron-hole pair disappears because of recombination. With each electronhole pair created, two charge-carrying particles are formed. One is negative
which is the free electron with mobility m n. The other is positive, i.e. the hole
with mobility mp. The electrons and holes move in opposite directions in an
electric field E, but since they are of opposite sign, the current due to each is
in the same direction. Hence, the total current density J within the intrinsic
semiconductor is given by
J = Jn + Jp
= q ◊ n ◊ mn E + q ◊ p ◊ mp ◊ E
= (nm n + pmp)qE
= sE
where
(1.11)
Jn = electron drift current density
Jp = hole drift current density
n = number of electrons per unit volume, i.e. magnitude of free-electron (negative) concentration
p = number of holes per unit volume, i.e. magnitude of hole
(positive) concentration
E = applied electric field strength, V/m
q = charge of electron or hole, Coulomb
Hence, s is the conductivity of a semiconductor which is equal to (n m n + p mp)
q. The resistivity (r) of a semiconductor is the reciprocal of conductivity, i.e.
1
r = __
s.
It is evident from the above equation that current density within a semiconductor is directly proportional to the applied electric field.
For pure (intrinsic) semiconductor, n = p = ni, where ni is the intrinsic carrier
concentration.
J = ni (m n + mp) qE
Therefore,
and conductivity of an intrinsic semiconductor is si = q ◊ ni (m n + mp). Hence it is
clear that conductivity of an intrinsic semiconductor depends upon its intrinsic
concentration (ni) and the mobility of electrons (m n) and holes (mp). The intrinsic conductivity of germanium and silicon increase by approximately 5 per
cent per °C and 7 per cent per °C rise in temperature respectively due to the
influence of n .
The conductivity of an
intrinsic semiconductor,
si = q ◊ ni(mn + mp) = q ◊ (n mn + pmp)
(1.12)
For N-type semiconductor, as n>>p, then the conductivity, s = q ◊ n ◊ mn.
For P-type semiconductor, as p>>n, the conductivity, s = q ◊ p ◊ mp.
The mobility of free electrons and holes in pure germanium are 3800 and 1800
cm2 /V-s respectively. The corresponding values for pure silicon are 1300 and 500
cm2/V-s, respectively. Determine the values of intrinsic conductivity for both germanium and silicon. Assume ni = 2.5 × 1013 cm–3 for germanium and ni = 1.5 × 1010 cm–3
for silicon at room temperature.
Solution
(i) The intrinsic conductivity for germanium,
si = qni (m n + mp)
= (1.602 × 10 –19) (2.5 × 1013) (3800 + 1800)
= 0.0224 S/cm
(ii) The intrinsic conductivity for silicon,
si = qni (m n + mp)
= (1.602 × 10 –19) (1.5 × 1010) (1300 + 500)
= 4.32 × 10 –6 S/cm
Semiconductors are classified as (i) intrinsic (pure) and (ii) extrinsic (impure)
types. The extrinsic semiconductors are of N-type and P-type.
A pure semiconductor is called intrinsic semiconductor. As already explained in the first chapter, even at room temperature,
some of the valence electrons may acquire sufficient energy to enter the conduction band to form free electrons. Under the influence of electric field, these
electrons constitute electric current. A missing electron in the valence band
leaves a vacant space there, which is known as a hole, as shown in Fig. 1.2.
Holes also contribute to electric current.
Free electron
Energy
in eV
CB (Conduction Band)
Hole
VB (Valence Band)
In an intrinsic semiconductor, even at room temperature, electron-hole pairs
are created. When electric field is applied across an intrinsic semiconductor,
the current conduction takes place due to free electrons and holes. Under the
influence of electric field, total current through the semiconductor is the sum
of currents due to free electrons and holes.
Though the total current inside the semiconductor is due to free electrons and
holes, the current in the external wire is fully by electrons. In Fig. 1.3, holes
being positively charged move towards the negative terminal of the battery. As
the holes reach the negative terminal of the battery, electrons enter the semiconductor near the terminal (X ) and combine with the holes. At the same time,
the loosely held electrons near the positive terminal (Y ) are attracted towards
the positive terminal. This creates new holes near the positive terminal which
again drift towards the negative terminal.
Due to the poor conduction at room temperature,
the intrinsic semiconductor as such, is not useful in the electronic devices.
Hence, the current conduction capability of the intrinsic semiconductor should
Holes
X
Y
–
–
–
Free electrons
–
+
be increased. This can be achieved by adding a small amount of impurity to
the intrinsic semiconductor, so that it becomes impure or extrinsic semiconductor. This process of adding impurity is known as doping.
The amount of impurity added is extremely small, say 1 to 2 atoms of impurity
for 106 intrinsic atoms.
A small amount of pentavalent impurities such as
arsenic, antimony or phosphorus is added to the pure semiconductor (germanium or silicon crystal) to get N-type semiconductor.
Germanium atom has four valence electrons and antimony has five valence
electrons. As shown in Fig. 1.4, each antimony atom forms a covalent bond
with surrounding four germanium atoms. Thus, four valence electrons of antimony atom form covalent bond with four valence electrons of individual germanium atom and fifth valence electron is left free which is loosely bound to
the antimony atom.
This loosely bound electron can be easily excited from the valence band to the
conduction band by the application of electric field or increasing the thermal
energy. Thus, every antimony atom contributes one conduction electron without creating a hole. Such pentavalent impurities are called donor impurities
because it donates one electron for conduction. On giving an electron for conduction, the donor atom becomes positively charged ion because it loses one
electron. But it cannot take part in conduction because it is firmly fixed in the
crystal lattice.
Thus, the addition of pentavalent impurity (antimony) increases the number of
electrons in the conduction band thereby increasing the conductivity of N-type
semiconductor. As a result of doping, the number of free electrons far exceeds
the number of holes in an N-type semiconductor. So electrons are called majority carriers and holes are called minority carriers.
A small amount of trivalent impurity such as aluminium or boron is added to the pure semiconductor to get the P-type semiconductor. Germanium (Ge) atom has four valence electrons and boron has three
valence electrons as shown in Fig. 1.5. Three valence electrons in boron form
covalent bond with four surrounding atoms of Ge leaving one bond incomplete
which gives rise to a hole. Thus trivalent impurity (boron) when added to the
intrinsic semiconductor (germanium) introduces a large number of holes in
the valence band. These positively charged holes increase the conductivity of
P-type semiconductor. Trivalent impurities such as boron is called acceptor
impurity because it accepts free electrons in the place of holes. As each boron
atom donates a hole for conduction, it becomes a negatively charged ion. As
the number of holes is very much greater than the number of free electrons in a
P-type material, holes are termed as majority carriers and electrons as minority carriers.
The flow of charge, i.e current, through a semiconductor material are of two
types, namely drift and diffusion. The net current that flows through a PN
junction diode also has two components, viz. (i) drift current and (ii) diffusion
current.
When an electric field is applied across the semiconductor
material, the charge carriers attain a certain drift velocity vd , which is equal
to the product of the mobility of the charge carriers and the applied electric
field intensity, E. The holes move towards the negative terminal of the battery and electrons move towards the positive terminal. This combined effect
of movement of the charge carriers constitutes a current known as the drift
current. Thus the drift current is defined as the flow of electric current due to
the motion of the charge carriers under the influence of an external electric
field. The drift current density due to the charge carriers such as free electrons
and holes are the current passing through a square centimeter perpendicular
to the direction of flow. The equation for the drift current density, Jn, due to
free electrons is given by
Jn = qnmnE A/cm2
and the drift current density, Jp, due to holes is given by
Jp = qpmpE A/cm2
where
n = number of free electrons per cubic centimetre
p = number of holes per cubic centimetre
mn = mobility of electrons in cm2 /V-s
mp = mobility of holes in cm2 /V-s
E = applied electric field intensity in V/cm
q = charge of an electron = 1.602 × 10 –19 coulomb.
It is possible for an electric current to flow in a semiconductor even in the absence of the applied voltage provided a concentration
gradient exists in the material. A concentration gradient exists if the number
of either electrons or holes is greater in one region of a semiconductor as compared to the rest of the region. In a semiconductor material, the charge carriers
have the tendency to move from the region of higher concentration to that of
lower concentration of the same type of charge carriers. Thus, the movement
of charge carriers takes place resulting in a current called diffusion current. The
diffusion current depends on the material of the semiconductor, type of charge
carriers and the concentration gradient.
As indicated in Fig. 1.6 (a), the hole concentration p(x) in a semiconductor bar
varies from a high value to a low value along the x-axis and is constant in the
y- and z-directions.
Diffusion current density due to holes, Jp, is given by
dp
Jp = – qDp ___ A/cm2
dx
(1.13)
Since the hole density p(x) decreases with increasing x as shown in Fig. 1.6 (b),
dp/dx is negative and the minus sign in the above equation is needed in order
that Jp has a positive sign in the positive x-direction.
Diffusion current density due to the free electrons, Jn, is given by
dn
Jn = qDn ___ A/cm2
dx
where dn/dx and dp/dx are the concentration gradients for electrons and holes
respectively, in the x-direction and Dn and Dp are the diffusion coefficients
expressed in cm2 /s for electrons and holes, respectively.
The total current in a semiconductor is the sum of drift current and diffusion current. Therefore, for a P-type semiconductor, the total
current per unit area, i.e. the total current density is given by
dp
Jp = qpmpE – qDp ___
dx
Similarly, the total current density for an N-type semiconductor is given by
dn
Jn = qn mn E + qDn ___
dx
There exists a definite relationship between the mobility and diffusion coefficient of a particular type of charge carrier in the same semiconductor. The
higher the value of mobility of a charge carrier, the greater will be its tendency to diffuse. The equation which relates the mobility m and the diffusion
coefficient D is known as the Einstein relationship. The Einstein relationship is
expressed as
D
Dn ___
kT
___p = ___
(1.14)
mp
mn = q = VT
The importance of Einstein relationship is that it can be used to determine Dp
(or Dn), if the mobility of holes (or electrons) is measured experimentally. For
an intrinsic silicon, Dp = 13 cm2 /s and Dn = 34 cm2 /s. For an intrinsic germanium, Dp = 47 cm2 /s and Dn = 99 cm 2 /s
As shown in Fig. 1.6 the excess hole or electron densities fall off exponentially with distance as a result of the recombination of
these excess minority carriers with the majority carriers of the semiconductor.
Here, the excess charge carriers have a finite life time, t, before they are totally
destroyed by recombination. The average distance that on excess charge carrier can diffuse during its life time is called the diffusion length L, which is given
by
___
L = ÷Dt
where D is the diffusion coefficient that may be related to the drift mobility, m,
through the Einstein relation as
kT
D = m ___
q
If the transverse length of the semiconductor is greater than the diffusion
length L, then the terminal currents are the recombination currents arising out
of the recombination, as every electron lost by recombination is supplanted by
the terminal electrode to maintain the charge neutrality.
If a pure semiconductor is doped with N-type impurities, the number of electrons in the conduction band increases above a level and the number of holes
in the valence band decreases below a level, which would be available in the
intrinsic (pure) semiconductor. Similarly, the addition of P-type impurities to
a pure semiconductor increases the number of holes in the valence band above
a level and decreases the number of electrons in the conduction band below
a level, which would have been available in the intrinsic semiconductor. This
is because the rate of recombination increases due to the presence of a large
number of free electrons (or holes).
Further, the experimental results state that under thermal equilibrium for any
semiconductor, the product of the number of holes and the number of electrons
is constant and is independent of the amount of donor and acceptor impurity
doping. This relation is known as mass-action law and is given by
n.p = ni2
(1.15)
where n is the number of free electrons per unit volume, p the number of holes
per unit volume and ni the intrinsic concentration.
While considering the conductivity of the doped semiconductors, only the
dominant majority charge carriers have to be considered.
The law of massaction has given the relationship between free electron concentration and hole
concentration. These concentrations are further related by the Law of Electrical
Neutrality as explained below.
Let ND be the concentration of donor atoms in an N-type semiconductor. In
order to maintain the electric neutrality of the crystal, we have
nN = ND + pN
ª ND
where nN and pN are the electron and hole concentration in the N-type semiconductor. The value of pN is obtained from the relations of mass-action law as
n2i
___
pN = n
N
n2i
___
ª
, which is << nN
ND
or
ND.
Similarly, in a P-type semiconductor we have
pP = NA + nP
ª NA
where NA, pP and nP are the concentrations of acceptor impurities, holes and
electrons respectively in a P-type semiconductor.
n2i
From mass-action law,
nP = __
pp
Therefore,
n2i
___
nP =
, which is << pP or NA
NA
The conductivity of an N-type semiconductor is
given by
sN = qnN mn ª qND mn, since nN ª ND.
The conductivity of a P-type semiconductor is given by
sP = qpP mP ª qNA mP, since pP ª NA.
The doping of intrinsic semiconductor considerably increases its conductivity.
If the concentration of donor atoms added to a P-type semiconductor exceeds
the concentration of acceptor atoms, i.e. ND >> NA, then the semiconductor is
converted from a P-type to N-type. Similarly, a large number of acceptor atoms
added to an N-type semiconductor can convert it to a P-type semiconductor
if NA >> ND. This concept is precisely used in the fabrication of PN junction,
which is an essential part of semiconductor devices and integrated circuits.
Find the conductivity of silicon (a) in intrinsic condition at a room temperature of
300 K, (b) with donor impurity of 1 in 108, (c) with acceptor impurity of 1 in 5 ×
107, and (d) with both the above impurities present simultaneously. Given that ni for
silicon at 300 K is 1.5 × 1010 cm–3, mn = 1300 cm2/V-s, mp = 500 cm2/V-s, number of
Si atoms per cm3 = 5 × 1022.
Solution
(a) In intrinsic condition, n = p = ni
Hence,
si = qni (mn + mp)
= (1.602 × 10–19) (1.5 × 1010) (1300 + 500)
= 4.32 × 10–6 S/cm
(b) Number of silicon atoms/cm3 = 5 × 1022
Hence,
5 × 1022
ND = _______
= 5 × 1014 cm–3
108
Further,
n ª ND
Therefore,
n2i
n2i
__
___
p = n ª
ND
(1.5 × 1010)2
= ___________
= 0.46 × 106 cm–3
5 × 1014
Thus, p << n. Hence, p may be neglected while calculating the
conductivity.
Hence,
s = nqmn = NDqmn
= (5 × 1014) (1.602 × 10–19) (1300)
= 0.104 S/cm.
5 × 1022
NA = _______
= 1015 cm–3
5 × 107
(c)
Further,
p ª NA
Hence,
n2i
n2i
__
___
n = p ª
NA
(1.5 × 1010)2
= ___________
= 2.25 × 105 cm–3
1015
Thus, p >> n. Hence, n may be neglected while calculating the
conductivity.
s = pqmP = NAqmP
Hence,
= (1015 × 1.602 × 10–19 × 500)
= 0.08 S/cm.
(d) With both types of impurities present simultaneously, the net acceptor
impurity density is,
N¢A = NA – ND = 1015 – 5 × 1014 = 5 × 1014 cm–3
s = N¢A qmp
Hence,
= (5 × 1014) (1.602 × 10–19) (500)
= 0.04 S/cm.
Determine the resistivity of germanium (a) in instrinsic condition at 300 K, (b) with
donor impurity of 1 in 107, (c) with acceptor impurity of 1 in 108, and (d) with both
the above impurities simultaneously. Given that for germanium at room temperature ni = 2.5 × 1013/cm3, mn = 3800 cm2/V-Vs, mp = 1800 cm2/V-Vs and a number of
Germanium atoms/cm3 = 4.4 × 1022.
Solution
(a) n = p = ni = 2.5 × 1013 cm–3
Therefore, conductivity,
s = qni(mn + mp)
= (1.602 × 10–19)(2.5 × 1013)(3800 + 1800)
Hence, resistivity,
(b)
Also,
Therefore,
= 0.0224 S/cm
1 ______
1
r = __
s = 0.0224 = 44.64 W-cm
4.4 × 1022
ND = _________
= 4.4 × 1015 cm–3
107
n = ND
n2i
n2i
___
p = __
=
n ND
(2.5 × 1013)2
= ___________
= 1.42 × 1011 holes/cm3
4.4 × 1015
Here, as n >> p, p can be neglected.
Therefore, conductivity,
s = nqmn = NDqmn
= (4.4 × 1015) (1.602 × 10–19) (3800) = 2.675
S/cm
Hence, resistivity,
1 _____
1
r = __
s = 2.675 = 0.374 W-cm
4.4 × 1022
NA = _________
= 4.4 × 1014 cm–3
108
p = NA
(c)
Also,
n2i
n2i
___
n = ___
=
p
NA
Therefore,
(2.5 × 1013)2
= ___________
= 1.42 × 1012 electrons/cm3
4.4 × 1014
Here, as p >> n, n may be neglected. Then
Conductivity,
s = pqmp = NAqmp
= (4.4 × 1014) (1.602 × 10–19) (1800) = 0.1267 S/cm
1 ______
1
Hence resistivity, r = __
s = 0.1267 = 7.89 W-cm
(d) With both p and n type impurities present,
ND = 4.4 × 1015 cm–3 and NA = 4.4 × 1014 cm–3
Therefore, the net donor density N¢D is
N¢D = (ND – NA) = (4.4 × 1015 – 4.4 × 1014)
= 3.96 × 1015 cm–3
Therefore, effective n = N¢D = 3.96 × 1015 cm–3
n2i
(2.5 × 1013)2
p = ____ = ___________
N¢D
3.96 × 1015
= 1.578 × 1011 cm–3
( )
n2i
____
is very small compared with ND ¢ and may be neglected in
N¢D
calculating the effective conductivity.
Here again p =
Therefore,
Hence, resistivity
s = N¢D qmn
= (3.96 × 1015) (1.6 × 10 –19) (3800) = 2.408 S/cm
1 _____
1
r = __
s = 2.408 = 0.415 W-cm
A sample of silicon at a given temperature T in intrinsic condition has a resistivity of
25 × 104 W-cm. The sample is now doped to the extent of 4 × 1010 donor atoms/cm3 and
1010 acceptor atoms/cm3. Find the total conduction current density if an electric field
of 4 V/cm is applied across the sample. Given that mn = 1250 cm2/V-s, mp = 475 cm2/V-s
at the given temperature.
Solution
1
si = qni (mn + mp) = ________4
25 × 10
Therefore,
si
1
ni = _________ = _________________________________
q(mn + mp) (25 × 104) (1.602 × 10–19) (1250 + 475)
= 1.45 × 1010 cm–3
Net donor density ND (= n) = (4 × 1010 – 1010)
= 3 × 1010 cm–3
Hence,
n2i
(1.45 × 1010)2
p = ____ = ____________
= 0.7 × 1010 cm–3
10
ND
3 × 10
Hence,
s = q(nmn + pmp)
= (1.602 × 10 –19) (3 × 1010 × 1250 + 0.7 × 1010 × 475)
= 6.532 × 10 –6 S/cm
Therefore, total conduction current density,
J = sE = 6.532 × 10 –6 × 4
= 26.128 × 10 –6 A/cm2
Find the concentration (densities) of holes and electrons in N-type Silicon at 300 K,
if the conductivity is 300 S/cm. Also find these values for P-type silicon. Given that
for Silicon at 300 K, ni = 1.5 × 1010/cm3, mn = 1300 cm2/V-s and mp = 500 cm2/V-s.
Solution
(a) Concentration in N-type silicon
The conductivity of an N-type silicon is s = qnmn
s
Concentration of electrons,
n = ____
qmn
300
= ___________________
= 1.442 × 1018 cm–3
–19
(1.602 × 10 ) (1300)
n2i (1.5 × 1010)2
__
Hence, concentration of holes, p = n = ___________
= 1.56 × 102 cm–3
1.442 × 1018
(b) Concentration in P-type silicon
The conductivity of a P-type silicon is s = qpmp
s
Hence, concentration of holes p = ____
qmp
300
= __________________
= 3.75 × 1018 cm–3
(1.602 × 10–19) (500)
n2i (1.5 × 1010)2
__
and concentration of electrons, n = p = ___________
= 0.6 × 102 cm–3
3.75 × 1018
A specimen of pure germanium at 300 K has a density of charge carriers 2.5 × 1019/
m3. It is doped with donor impurity atoms at the rate of one impurity atom every
106 atoms of germanium. All impurity atoms are supposed to be ionised. The density
of germanium atom is 4.2 × 1028 atoms/m3. Calculate the resistivity of the doped
germanium if electron mobility is 0.38 m2/V-s.
If the germanium bar is 5 × 10–3 m long and has a cross sectional area of (5 × 10–6)2
m2, determine its resistance and the voltage drop across the semiconductor bar for a
current of 1 m A flowing through it.
Solution
Also,
Density of added impurity atoms is
4.2 × 1028
ND = _________
= 4.2 × 1022 atoms/m3
106
n ª ND
n2i
n2i
__
___
p = n =
ND
Therefore,
(2.5 × 1019)2
= ___________
= 1.488 × 106 m–3
4.2 × 1022
Here, as p << n, p may be neglected.
Therefore,
s = qND mn
= (1.602 × 10 –19) (4.2 × 1022) (0.38) = 2.554 × 103 S/m
Therefore, resistivity,
1 __________
1
–3
r = __
s = 2.554 × 103 = 0.392 × 10 W -m
Resistance,
rL 0.392 × 10–3 × 5 × 10–3
R = ___ = ____________________
A
(5 × 10–6)2
= 78.4 kW
Voltage drop,
V = RI = 78.4 × 103 × 10 –6 = 78.4 mV
When a transverse magnetic field B is applied to a specimen (thin strip of metal
or semiconductor) carrying current I, an electric field E is induced in the direction perpendicular to both I and B. This phenomenon is known as the Hall
effect.
A Hall effect measurement experimentally confirms the validity of the concept
that it is possible for two independent types of charge carriers, electrons and
holes, to exist in a semiconductor.
The schematic arrangement of the semiconductor, the magnetic field and the
current flow pertaining to the Hall effect are shown in Fig. 1.7. Under the equilibrium condition, the electric field intensity, E, due to the Hall effect must exert
a force on the carrier of charge, q, which just balances the magnetic force, i.e.
qE = Bqvd
where vd is the drift velocity. Also, the electric field intensity due to Hall effect
is
VH
E = ___
d
where d is the distance between surfaces 1 and 2, and VH is the Hall voltage
appearing between surfaces 1 and 2. In an N-type semiconductor, the current is
carried by electrons and these electrons will be forced downward towards side 1
which becomes negatively charged with respect to side 2.
y
2
d
l
w
x
B
1
z
The current density (J ) is related to charge density ( r) by
J = rvd
Further, the current density (J ) is related to current (I ) by
I
I
J = _____ = ___
Area wd
where w is the width of the specimen in the direction of magnetic field (B).
Combining the above relations, we get
BJd ___
BI
VH = Ed = B vd d = ____
r = rw
The Hall coefficient, RH, is defined by
1
RH = __
r
RH
so that VH = ___
w BI. A measurement of the Hall coefficient RH determines not
only the sign of the charge carriers but also their concentration. The Hall coefficient for a P-type semiconductor is positive, whereas it is a negative for an
N-type semiconductor. This is true because the Hall voltage in a P-type semiconductor is of opposite polarity to that in an N-type semiconductor.
The advantage of Hall effect transducers is that they are non-contact devices
with high resolution and small size.
The Hall effect is used to find whether a semiconductor is N-or
P-type and to determine the carrier concentration. If terminal 2 becomes charged
positively with respect to terminal 1, the semiconductor must be N-type and r
= nq, where n is the electron concentration. On the other hand, if the polarity of
VH is positive at terminal 1 with respect to terminal 2, the semiconductor must
be P-type and r = pq, where p is the hole concentration.
The mobility ( m) can also be calculated with simultaneous measurement of the
conductivity (s). The conductivity and the mobility are related by the equation
s = rm or m = s RH.
Therefore, the conductivity for N-type semiconductor is s = nqmn and for P-type
semiconductor, s = pqmp, where mn is the electron mobility and mp is the hole
mobility.
Thus, if the conductivity of a semiconductor is also measured along with RH,
then mobility can be determined from the following relations.
s
For N-type semiconductor,
mn = ___
nq = sRH
s
and for P-type semiconductor, mp = ___
pq = sRH
Since VH is proportional to B for a given current I, Hall effect can be used to
measure the a.c. power and the strength of magnetic field and sense the angular
position of static magnetic fields in a magnetic field meter. It is also used in
an instrument called Hall effect multiplier which gives the output proportional
to the product of two input signals. If I is made proportional to one of the
inputs and B is made proportional to the second signal, then from the equation,
BI
VH = ___
rw , VH will be proportional to the product of two inputs. Hall devices
for such applications are made from a thin wafer or film of indium antimonide
(InSb) or indium arsenide. As the material has a very high electron mobility, it
has high Hall coefficient and high sensitivity.
An electrical current can be controlled by a magnetic field because the magnetic
field changes the resistances of some elements with which it comes in contact. In
the magnetic bubble memory, while read-out, the Hall effect element is passed
over the bubble. Hence, a change in current of the circuit will create, say, a one.
If there is no bubble, there will be a zero and there will be no current change in
the output circuit. The read-in device would have an opposite effect, wherein the
Hall device creates a magnetic field when supplied with a pulse of current. This,
in turn, creates a little domain and then a magnetic bubble is created.
Some of the other applications are in measurement of velocity, rpm, sorting,
limit sensing and non-contact current measurements.
An N-type semiconductor has a Hall coefficient of 200 cm3/C and its conductivity is
10 S/m. Find its electron mobility.
Solution
Given RH = 200 cm3/C and s = 10 S/m
Therefore, the electron mobility, mn = sRH = 10 × 200 = 2000 cm2/V-s
The conductivity of an N-type semiconductor is 10 S/m and its electron mobility is
50 × 10 – 4 m2/V-s. Determine the electron concentration.
Given s = 10 s/m and mn = 50 × 10 – 4 m2/V-s
s
We know that the electron mobility, mn = ___
nq
Solution
Therefore, the electron concentration,
s _____________________
10
n = ___
mq = 50 × 10 – 4 × 1.6 × 10 – 19
= 12.5 × 1021 m– 3
A current of 20 A is passed through a thin metal strip, which is subjected to a magnetic flux density of 1.2 Wb/m2. The magnetic field is directed perpendicular to the
current. The thickness of the strip in the direction of the magnetic field is 0.5 mm.
The Hall voltage is 60 V. Find the electron density.
Solution
Given: I = 20 A, B = 1.2 Wb/m2, VH = 60 V and w = 0.5 mm
We know that the number of conduction electrons, i.e. electron density,
1.2 × 20
BI
n = ______ = _________________________
= 5 × 1021 m3
VH qw 60 × 1.6 × 10 – 19 × 0.5 × 10 – 3
The fundamental law governing the flow of charge is called the Continuity
Equation. The continuity equation as applied to semiconductors describes how
p holes/m
3
Area A
Ip
Ip + dIp
x
x + dx
the carrier concentration in a given elemental volume of the crystal varies with
time and distance. The variation in density is attributable to two basic causes,
viz. (i) the rate of generation and loss by recombination of carriers within the
element, and (ii) drift of carriers into or out of the element. The continuity
equations enable us to calculate the excess density of electrons or holes in time
and space.
As shown in Fig. 1.8, consider an infinitesimal N-type semiconductor bar of
volume of area A and length dx and the average minority carrier (hole) concentration p, which is very small compared with the density of majority carriers.
At time t, if minority carriers (holes) are injected, the minority current entering the volume at x is Ip and leaving at x + dx is Ip + d Ip which is predominantly
due to diffusion. The minority carrier concentration injected into one end of
the semiconductor bar decreases exponentially, with distance into the specimen, as a result of diffusion and recombination. Here, d Ip is the decrease in
number of coulombs per second within the volume.
dIp
Since the magnitude of the carrier charge is q, then ___
p equals the decrease in
the number of holes per second within the elemental volume Aμx. As the curIp
rent density Jp = __, we have
A
dI
dJp
p
1
1 ___
___
___
__
qA ◊ dx = q ◊ dx = decrease in hole concentration per second, due to
current Ip.
We know that there is an increase of holes per unit volume per second given
by G = po /tp due to thermal generation. Further, there is a decrease of holes
per unit volume per second given by R = p/tp due to recombination but charge
can neither be created nor destroyed. Hence, increase in holes per unit volume
per second, dp/dt, must equal the algebraic sum of all the increases in hole
concentration. Thus,
∂Jp
p – po __
∂p
1 ___
___
= – _____
–
q ∂x
tp
∂t
where
dp
Jp = – qDp ___ + qpmp E
dx
Therefore,
p – po
∂p
d(pE)
d2p
___
____
= – _____
+
D
– mp _____
p
2
t
dx
∂t
p
dx
This is the continuity equation or equation of conservation of charge for holes
stating the condition of dynamic equilibrium for the density of mobile carrier
holes. Here, partial derivatives have been used since both p and Jp are functions of both t and x.
Similarly, the continuity equation for electrons states the condition of dynamic
equilibrium for the density of mobile carrier electrons and is given by
where
Therefore,
no – n 1 ___
∂Jn
∂n _____
___
= tn – __
q
∂t
∂x
dn
Jn = – qDn ___ + qn mn E
dx
n
–
n
d(nE)
∂n
d2n
o
___
= – _____
+ Dn ____2 – mn _____
t
dx
∂t
n
dx
We now consider three special cases of continuity equation.
For this
special case, the continuity equation can be changed into
p – po
∂p
___
= – _____
tp
∂t
Solving the above equation, we get
p – po = A1 e–t/tp where A is a constant
For this special case, the continuity equation can be changed into
p – po
d2p
____
0 = – ______
+
D
p
tp
dx2
p – po
d2p _____
____
=
2
tp Dp
dx
Solving the above equation, we get
p – po = A1 e–x/Lp + A2 ex/Lp
where A1 and A2 are constants.
_____
Lp = ÷Dp tp = diffusion length for holes
Let P(x, t) = P (x) e jw t
For this special case the continuity equation can be changed into
P(x)
d2 P(x)
_______
jwP(x) = – ____
+
D
p
tp
dx2
(1 + jwtp)
d2P _________
____
=
P
2
dx
L2p
At w = 0,
d2 P ___
P
____
= 2
2
dx
Lp
The above equation is the same as that of the second special case.
semiconductor bar shown in Fig. 1.6(a). This bar is uniformly doped with donar
atoms so that the charge concentration n = ND is uniform throughout the bar
on which radiation falls on one end of the bar at x = 0. Near the illuminated
surface, the bound electrons in the covalent bonds capture some of the photons.
This energy transfer results in breaking of covalent bonds and generation of
hole-electron pairs.
The minority carrier (hole) concentration p is very small compared with the doping level, i.e., p < n. The condition p = p + p0 << n which states that the minority
concentration is much smaller than the majority concentration is called the lowlevel injection. The controlling differential equation for p is
p – p0
d2p _____
___
=
2
tp Dp
dx
The diffusion length for holes Lp is given by
_____
Lp = ÷Dp tp
The differential equation for the injected concentration p = p – p 0 becomes
d2p ___
P
____
=
dx2 L2p
The solution of the equation is
p(x) = A1 e–x/ALp + A2 ex/Lp
when x Æ •, A2 = 0. At x = 0, the injected concentration P(0) to satisfy this
boundary condition, A1 = P(0). Therefore,
p(x) = P(0) e–x/Lp = P(x) – p 0
Here the hole concentration decreases exponentially with distance as shown in
Fig. 1.6(b).
The minority (hole) diffusion current is Ip = AJp, where A
is the area of cross-section of the bar. Therefore,
Aq Dp P(0)
Ip (x) = __________ e–x/Lp
Lp
Aq Dp
= ______ (P(0) – p(0) e–x/Lp
Lp
This current decreases exponentially with distance x as that of minority carrier
concentration.
The majority (electron) diffusion current is
Dn
dp
dn
AqDn ___ = AqDn ___ = – ___ Ip
Dp
dx
dx
dp
where Ip = –AqDn___. The magnitude of ratio of majority to minority diffusion
dx
current is Dn /Dp ª 3 for Si and 2 for Ge.
For an open circuit semiconductor bar, the sum of the hole and
electron currents should be zero everywhere. Therefore, a majority (electron)
drift current Ind exist such that
(
)
Dn Ip
Ip + Ind – _____ = 0
Dp
Therefore,
(
)
Dn
Ind = ___ – 1 Ip
Dp
The hole drift current Ipd is given by
mp Dn
p ___
___
Ipd = AqpmpE = __
n mn Dp – 1 Ip
(
where the electric field,
(
)
)
Dn
1
E = ______ ___ – 1 Ip
Aqn mn Dp
Here, as p << n, then Ipd << Ip, i.e., the hole drift current is negligible compared
to the hole diffusion current.
A PN junction is formed by joining a P-type impurity and N-type impurity.
When a forward bias is applied to a PN junction, holes are injected from the
P-side into the N-side. Due to this, the concentration of holes in the N-side (pn) is
increased from its thermal equilibrium value (pno) and injected hole concentration
Pn(x) decreases exponentially with respect to the distance (x).
Pn(x) = pn – pno = Pn(0)e–x/Lp
where Lp is the diffusion length of holes in the N-material.
Pn(x) = pno + Pn(0)e–x/Lp
Injected hole concentration at x = 0 is
Pn(0) = pn(0) – pno
These several components of hole concentration in the N-side of a forwardbiased PN junction are shown in Fig. 1.9, in which the density pn(x) decreases
exponentially with distance (x).
Let pp and pn be the hole concentration at the edges of the space charge in the
P- and N- sides respectively. Let VB = (V0 – V) be the effective barrier potential
across the depletion layer. Then
pp = Pn = eVB /VT
(1.16)
where VT is the volt-equivalent of temperature.
This is the Boltzmann’s relation of kinetic gas theory. This equation is valid as
long as the hole current is small compared with diffusion or drift current. This
condition is called low-level injection.
Under open-circuit condition (i.e. V = 0), pp = ppo, pn = pno and VB = V0.
For a P-type material, we know that
NV
NV
EF – Evp = kT ln ___ = kT ln ___
Pp
NA
The above equation can be changed into
ppo = Pno eVo/VT
(1.17)
Under forward-bias condition, let V be the applied voltage, then the effective
barrier voltage
VB = Vo – V
The hole concentration throughout the P-side is constant and equal to the thermal equilibrium value (pp – ppo). The hole concentration varies exponentially
with distance into the N-side.
At
x = 0, pn = pn(0)
Equation (1.16) can be changed into
Ppo = Pn (0) e(V0 – V)/VT
(1.18)
Comparing Eqn. (1.17) and Eqn. (1.18), we get
Pn(0) = pno eV/VT
This boundary condition is called the law of junction.
An electron inside the metal must possess an energy level that is at least greater
than the surface barrier energy EB, so as to escape to a higher level. It is therefore
important to know about the energies possessed by the electrons in a metal. This
is given by the energy distribution function.
The distribution in energy of the free electrons in a metal is
dn = rdE
where dn is the number of electrons per cubic meter whose energies lie in the
energy interval dE and r is the density of electrons in a given energy interval.
It is assumed that there are no potential variations within the metal, since only
free electrons are considered. Hence there must be the same number of electrons
in each cubic metre of the metal. That is, the density in space (electrons per
cubic metre) is a constant. However, there will be electrons having all possible
energies within each unit volume of the metal. This distribution in energy is
expressed by
r = f (E) N(E)
where N(E) is the density of states in the conductance band, and f (E) is the
probability that a quantum state with energy ‘E’ is occupied by an electron.
Therefore,
1
__
N(E) = g E 2
Here, g is a constant defined by
3
3
__
__
4p
g = ___3 (2m) 2 (1.602 × 10 – 19) 2 = 6.82 × 1027
h
3
– __
where the dimensions of g are (m – 3) (eV) 2 , m is the mass of the electron in kg
and h is the Planck’s constant in Joule-second.
The Fermi–Dirac probability function f (E) specifies
the fraction of all states at energy E (in eV) occupied under conditions of thermal equilibrium. From quantum physics,
1
f (E) = ___________
(E – EF)/kT
1+e
where k is the Boltzman constant in eV/K, T is the temperature in K and EF is
the Fermi level or characteristic energy for the crystal in eV.
The Fermi level represents the energy state with 50% probability of being filled
1
if no forbidden band exists. That is, if E = EF , then f (E) = __ for any value of
2
temperature.
The plots of f (E) Vs (E – EF) and (E – EF) Vs f (E) are shown in Fig. 1.10 (a), and
Fig. 1.10 (b) respectively for T = 0 K and larger values of temperature.
E – EF, eV
T=0K
f (E )
1.0
T = 300 K
0.8
T = 2500 K
0.6
0.4
0.2
0
– 1.0 – 0.6 – 0.2 0 0.2
(a)
0.6
1.0
E – EF, eV
1.0
0.8
0.6
0.4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
T = 2500 K
T = 300 K
T=0K
0
0.2 0.4 0.6 0.8 1.0 f (E )
(b)
At T = 0 K, the following conditions exist:
(i) If E > EF , the exponential term becomes infinite and f (E) = 0. Consequently,
there is no probability of finding an occupied quantum state of energy
greater than EF at absolute zero temperature.
(ii) If E < EF, the exponential becomes zero and f (E) = 1. All quantum levels
with energies less than EF will be occupied at T = 0 K.
From the above equations, we get at absolute zero temperature,
1
__
g E 2 ; for E < EF
r=
0 ; for E > EF
It implies that there are no electrons at 0 K which have energies in excess of EF.
Therefore, the Fermi energy is the maximum energy that any electron may possess at absolute zero temperature.
The relationship given by the above equation is called the completely degenerate
energy distribution function. In fact, all particles should have zero energy at 0 K.
Based on Pauli's exclusion principle, it is also to be mentioned that, since no two
electrons has the same set of quantum numbers, not all the electrons can have
the same energy even at 0 K.
EF may be obtained on the basis of the completely degenerate function. The total number of free electrons is given by
EF
3
1
__
__
2
n = Ú g E 2 dE = __ g EF 2
3
0
2
i.e.
3n __
EF = ___ 3 ,
2g
Therefore,
EF = 3.64 × 10–19 n 3
( )
where g = 6.82 × 1027
2
__
Since the density of free electrons, n, varies from metal to metal, EF will also vary
among metals. Generally, the numerical value of EF is less than 10 eV.
To calculate the conductivity of a semiconductor, the concentration of free
electrons n and the concentration of free holes p must be known.
dn = N(E) f(E) dE
where dn represents the number of conduction electrons per cubic meter whose
energies lie between E and E + dE and N(E) is the density of states. In a semiconductor, the lowest energy in the conduction band is EC and hence,
N(E) = g (E – EC )1/2
The Fermi Dirac probability function f (E) is given by
1
f (E ) = ____________
(E – EF)/kT
1+e
where EF is the Fermi level or characteristic energy for the crystal in eV.
The concentration of electrons in the conduction band is,
•
n =Ú
EC
N(E) f (E) dE
For E ≥ EC, E – EF > > kT,
–(E – EF)/kT
f (E ) =
•
1
__
n =Ú
and
g (E – EC) 2 e–(E – EF)/kT dE
EC
(E – Ec) = x2 i.e. E = x2 + Ec and dE = 2xdx
Substitute
At
x = 0, E = Ec,
At
x = •, E = •
(
n = Ú0
Therefore,
)
x2 + Ec – EF
___________
g xe ^–
[2xdx]
kT
•
(
Ec – EF
– _______
kT
= 2g e
) Ú•
0
x2e
•
__ 2n! a
2 2
We know that, Ú 0 x2n e – x /a dx = ÷p ___ __
n! 2
( )
x2
– ___
kT dx
2n+ 1
___
Here, n = 1 and a = ÷kT
Therefore,
Substituting
n=
(
Ec – EF
– _______
2g e kT
___
÷kT 3
) × 2 ÷__p ( ____
)
2
3
__
)2
3
__
4p
g = ___3 (2mn (1.602 × 10 – 19) 2 , we have
h
3
__
__
3
3
__
__
÷p (kT) 2
4p
–
___
________
–
19
n = 2 × 3 (2mn) 2 (1.602 × 10 ) 2 ×
×e
4
h
E –E
( _______
kT )
(
2mnpkT
= 2 _______
h2
(
2pmnkT
where Nc = 2 _______
h2
electron.
)
3
__
2
3
__
2
)
3
__
× (1.602 ×10 – 19) 2 e
(
Ec – EF
– _______
kT
c
F
E –E
) = Nc e – ( _______
kT )
c
F
3
__
(1.602 × 10 – 19) 2 , where mn is the effective mass of an
When the maximum energy in the valence band is EV, the density of states is
given by
N(E) = g (EV – E )1/2
The Fermi function of a hole is [1 – f (E )] and is given by
e(E – EF)/kT
1 – f (E) = ____________
= e–(EF – E)/kT
1 + e(E – EF)/kT
where EF – E >> kT for E £ EV.
The concentration of holes in the valence band is,
EV
p = Ú g (EV – E)1/2 e–(EF – E)/kT dE
–•
This integral evaluates to
p = NV e– (EF – EV)/kT
where
(
2pmp kT
NV = 2 ________
h2
hole.
)
3/2
(1.602 × 10–19)3/2, where mp is the effective mass of a
In the case of intrinsic material,
the crystal must be electrically neutral.
n i = pi
Therefore,
NC e–(EC – EF)/kT = NV e–(EF – EV)/kT
Taking the logarithm on both sides,
EC + EV – 2EF
NC
ln ____ = _____________
NV
kT
EC + EV kT NC
EF = ________ – ___ ln ___
NV
2
2
If the effective masses of a free electron and hole are the same,
NC = NV
EC + EV
EF = ________
2
From the above equation, at the centre of the forbidden energy band, Fermi
level is present.
Then,
If a pentavalent substance (antimony, phosphorous or arsenic) is added as an impurity to pure germanium, four of the five
valance electrons of the impurity atoms will occupy covalent bonds and the
fifth electron will be available as a carrier of current. These impurities donate
excess electron carriers and are hence called donor or N-type impurities.
If a trivalent impurity (boron, gallium or indium) is added to an intrinsic semiconductor, only three covalent bonds are filled, and the vacancy in the fourth
bond constitutes a hole. These impurities are known as acceptor or P-type
impurities.
The Fermi level in an
N-type material is given by
NC
EF = EC + kT ln ___
where ND = NC e – (EC – EF)/kT, the concentration of donor atoms.
The Fermi level in a P-type material is given by
NV
EF = EV + kT ln ___
NA
where NA = NV e–(EF – EV)/kT, the concentration of acceptor atoms. The change
in the position of Fermi level in N- and P-type semiconductors is shown in
Fig. 1.11.
In an N-type semiconductor, as temperature T increases, more number of electron-hole pairs are formed. At very
high temperature T, the concentration of thermally generated electrons in the
conduction band will be far greater than the concentration of donor electrons.
In such a case, as concentration of electrons and holes become equal, the semiconductor becomes essentially intrinsic and EF returns to the middle of the
forbidden energy gap. Hence, it is concluded that as the temperature of the
Conduction band
EC
Conduction band
EC
Energy
ED
EF
EG
EF
EV
EA
EV
Valence band
0
0.5
f (E )
(a)
Valence band
1.0
0
0.5
f (E )
(b)
1.0
P-type and N-type semiconductor increases, EF progressively moves towards
the middle of the forbidden energy gap.
In an N-type semiconductor, the Fermi level is 0.3 eV below the conduction level at
a room temperature of 300 K. If the temperature is increased to 360 K, determine
the new position of the Fermi level.
Solution
Therefore,
The Fermi level in an N-type material is given by
NC
EF = EC – kT ln ___
ND
NC
(EC – EF ) = kT ln ___
ND
NC
At T = 300 K, 0.3 = 300 K ln ___
ND
Similarly,
E C – EF1
(1)
NC
= 360 K ln ___
ND
(2)
Equation (2) divided by Eqn. (1) gives
EC – EF1 ____
360
________
=
0.3
300
360
Therefore,
EC – EF1 = ____ × 0.3 = 0.36 eV
300
Hence, the new position of the Fermi level lies 0.36 eV below the conduction
level.
In a P-type semiconductor, the Fermi level is 0.3 eV above the valance band at a
room temperature of 300 K. Determine the new position of the Fermi level for temperatures of (a) 350 K and (b) 400 K.
The Fermi level in a P-type material is given by
NV
EF = EV + kT ln ___
NA
N
V
Therefore,
(EF – EV) = kT ln ___
NA
NV
At T = 300 K, 0.3 = 300 k ln ___
NA
NV
(a) At T = 350 K, (EF1 – EV) = 350k ln ___
NA
Hence, from the above equation
Solution
EF1 – EV ____
350
________
=
0.3
300
350
Therefore,
EF1 – EV = ____ × 0.3 = 0.35 eV
300
N
V
(b) At T = 400 K, (E F2 – EV) = 400 k ln ___
NA
Hence, from the above equation,
Therefore,
EF2 – EV ____
400
________
=
0.3
300
400
____
EF2 – EV =
× 0.3 = 0.4 eV
300
In an N-type semiconductor, the Fermi level lies 0.2 eV below the conduction band.
Find the new position of Fermi level if the concentration of donor atoms is increased
by a factor to (a) 4, and (b) 8. Assume kT = 0.025 eV.
Solution
by
In an N-type material, the concentration of donor atoms is given
ND = NC e–(EC – EF)/kT
Let initially ND = NDO, EF = EFO and EC – EFO = 0.2 eV
NDO = NC e –0.2/0.025 = NC e –8
Therefore,
(a) When ND = 4NDO and E F = EF1, then
4NDO = NC e– (EC – EF )/0.025 = NC e–40 (EC – EF )
1
Therefore,
1
4 × NC e–8 = NC e–40(EC – EF1)
Therefore,
4 = e–40 (EC – EF1) + 8
Taking natural logarithm on both sides, we get
ln 4 = – 40 (EC – EF1) + 8
1.386 = – 40(EC – EF1) + 8
Therefore,
EC – EF1 = 0.165 eV
(b) When ND = 8NDO and EF = EF2, then
ln 8 = – 40 (EC – EF2) + 8
2.08 = – 40 (EC – EF2) + 8
Therefore,
EC – EF2 = 0.148 eV
In a P-type semiconductor, the Fermi level lies 0.4 eV above the valence band.
Determine the new position of Fermi level if the concentration of acceptor atoms is
multiplied by a factor of (a) 0.5, and (b) 4. Assume kT = 0.025 eV.
Solution
by
In a P-type material, the concentration of acceptor atoms is given
NA = NV e–(EF – EV)/kT
Let initially NA = NAO, EF = EFO and EFO – EV = 0.4 eV
Therefore,
NAO = NV e – 0.4/0.025 = NV e –16
(a) When NA = 0.5, NAO and EF = EF1, then
0.5NAO = NV e–(EF1 – EV)/0.025 = NV e–40 (EF1 – EV)
Therefore,
Therefore,
0.5 × NV e–16 = NV e–40(EF1 – EV)
0.5 = e–40 (EF1 + EV) + 16
Taking natural logarithm on both sides, we get
ln (0.5) = – 40(EF1 – EV) + 16
Therefore,
EF1 – EV = 0.417 eV
(b) When NA = 4NAO and EF = EF2, then
ln 4 = – 40(EF2 – EV) + 16
Therefore,
EF2 – EV = 0.365 eV
The PN junction diode is a semiconductor device with two semiconductor materials in physical contact, one with excess of holes (P-type) and other with excess
of electrons (N-type). A PN junction diode may be formed from a single-crystal
intrinsic semiconductor by doping part of it with acceptor impurities and the
remaining with donors. Such junctions can form the basis of very efficient rectifiers. The most important characteristic of a PN junction is its ability to allow
the flow of current in only one direction. In the opposite direction, it offers very
high resistance. The high vacuum diode has largely been replaced by silicon and
selenium rectifiers. Semiconductor diodes find wide applications in all phases of
electronics, viz. radio and TV, optoelectronics, power supplies, industrial electronics, instrumentation, computers, etc. The chapter deals with the working of
a PN junction diode and its characteristics.
In addition to the PN junction diode, other types of diodes like zener diode, varactor diode and tunnel diode are also discussed in this chapter and they are manufactured for specific applications. These special diodes are two-terminal devices
with their doping levels carefully selected to give the desired characteristics.
Thyristor, in general, is a semiconductor device having three or more junctions.
Such a device acts as a switch without any bias and can be fabricated to have
voltage ratings of several hundred volts and current ratings from a few amperes
to almost thousand amperes. The family of thyristors consists of PNPN diode
(Shockley diode), SCR, TRIAC, DIAC, etc. which are discussed here. This chapter also discusses the operation and characteristics of special semiconductor
devices like LED, LCD, photodiode and UJT.
In a piece of semiconductor material, if one half is doped by P-type impurity
and the other half is doped by N-type impurity, a PN junction is formed. The
plane dividing the two halves or zones is called PN junction. As shown in Fig.
2.1, the N-type material has high concentration of free electrons, while P-type
material has high concentration of holes. Therefore, at the junction there is a
tendency for the free electrons to diffuse over to the P-side and holes to the
N-side. This process is called diffusion. As the free electrons move across the
junction from N-type to P-type, the donor ions become positively charged.
Hence a positive charge is built on the N-side of the junction. The free electrons that cross the junction uncover the negative acceptor ions by filling in
the holes. Therefore, a net negative charge is established on the P-side of the
junction. This net negative charge on the P-side prevents further diffusion
of electrons into the P-side. Similarly, the net positive charge on the N-side
repels the hole crossing from P-side to N-side. Thus a barrier is set-up near
the junction which prevents further movement of charge carriers. i.e. electrons
and holes. As a consequence of the induced electric field across the depletion layer, an electrostatic potential difference is established between P-and
N-regions, which is called the potential barrier, junction barrier, diffusion
potential, or contact potential, Vo. The magnitude of the contact potential Vo
varies with doping levels and temperature. Vo is 0.3 V for germanium and 0.72
V for silicon.
The electrostatic field across the junction caused by the positively charged
N-type region tends to drive the holes away from the junction and negatively
charged P-type region tends to drive the electrons away from the junction. The
majority holes diffusing out of the P-region leave behind negatively charged
acceptor atoms bound to the lattice, thus exposing negative space charge in
a previously neutral region. Similarly, electrons diffusing from the N-region
expose positively ionised donor atoms, and a double space charge layer builds
up at the junction as shown in Figs. 2.1(a) and (c).
It is noticed that the space-charge layers are of opposite sign to the majority
carriers diffusing into them, which tends to reduce the diffusion rate. Thus, the
double space of the layer causes an electric field to be set up across the junction
directed from N- to P-regions, which is in such a direction to inhibit diffusion
of majority electrons and holes, as illustrated in Figs. 2.1(a) and (d). The shape
of the charge density, r, depends upon how the diode is doped, Thus, the junction region is depleted of mobile charge carriers. Hence, it is called the depletion
region (layer), the space charge region, or the transition region. The depletion
region is of order 0.5 mm thick. There are no mobile carriers in this very narrow
depletion layer. Hence no current flows across the junction and the system is in
equilibrium. To the left of this depletion layer, the carrier concentration is p ª
NA, and to its right it is n ª ND.
Let us now consider the width of the depletion
region in the junction of Fig. 2.1. The region contains space charge due to the fact
that, donors on the N-side and acceptors on the P-side have lost their accompanying electrons and holes. Hence, an electric field is established which, in turn,
causes a difference in potential energy, qVo, between the two parts of the specimen. Thus, a potential is built up across the junction and Fig. 2.1(e) represents the
Exposed ionised
acceptors
Exposed ionised
donors
E
P
–
–
+
+
–
–
+
+
–
–
+
+
N
(a)
10
10
10
24
Holes
20
16
Electrons
(b)
Space-charge
density, r
Space–charge
region
Charge
density r
+
x1
x
–
x2
x
x=0
(c) (ii) For graded or grown junction
(c) (i) For abrupt or alloy junction
Electric
field, E
x
(d)
Voltage,
V
V2
X1
X2
V0
Distance, x
V1
(e)
X=0
variation in potential. Here, P-side of the junction is at a lower potential than the
N-side which means that the electrons on the P-side have a great potential
energy.
In this analysis, let us consider an Alloy Junction in which there is an abrupt
change from acceptor ions on P-side to donor ions on N-side. Assume that the
concentration of electrons and holes in the depletion region is negligible and
that all of the donors and acceptors are ionised. Hence, the regions of space
charge may be described as
r = – qNA, 0 > x > X1
r = +qND, X2 > x > 0
r = 0, elsewhere
where r is the space charge density, as indicated in Fig. 2.1(c)(i). The axes have
been chosen in Fig. 2.1(e) in such a way that V1 and X1 have negative values.
The potential variation in the space charge region can be calculated by using
Poission’s equation, which is given by
r(x, y, z)
—2 V = – ________
e e
0 r
where er is the relative permittivity. The relevant equation for the required onedimensional problem is
r
d2 V
____
= – ____
2
e
0 er
dx
Applying the above equation to the P-side of the junction, we get
qNA
d2 V ____
____
=e e
2
0 r
dx
Integrating twice, we get
2
qN
Ax
______
V=
+ Cx + D
2e0 er
where C and D are the constants of integration.
From Fig. 2.1(e), we have V = 0 at x = 0, and hence D = 0. When x < X1 on the
dV
P-side, the potential is constant, so that ___ = 0 at x = X1.
dx
Hence,
qNA
C = – _____◊ X1
eo er
Therefore,
qNA x2 qNA
V = _______ – ____
eo er ◊ X1 ◊ x
2eo er
i.e.
qNA __
x2
V = ____
eo er 2 – X1 ◊ x
(
)
As V = V1 at x = X1, we have
qNA
V1 = – _____ ◊ X12
2eo er
If we apply the same procedure to the N-side, we get
qND
V2 = _____ ◊ X22
2eo er
Therefore, the total built-in potential or the contact potential is Vo, where
q
Vo = V2 – V1 = _____ ( NA X12 + ND X22 )
2eo er
We know the fact that the positive charge on the N-side must be equal in magnitude to the negative charge on the P-side for the neutral specimen. Hence,
NAX1 = – NDX2
and substituting this relationship in the above equation and using the fact that
X1 is a negative quantity, we get
[
2eo er Vo
X1 = – _____________
NA
qNA 1 + ___
ND
Similarly,
[
(
)
2eo er Vo
X2 = _____________
ND
qND 1 + ___
NA
(
)
]
1/2
]
1/2
The total depletion width, W = X2 – X1 and hence, W2 =X21 + X22 – 2X1 X2, and
then substituting for X1 and X2 from the above equations, we find
[
(
2 eo er Vo ________
NA + ND
W = ________
q
NA ND
)]
1/2
Here, in an alloy junction, the depletion width W is proportional to (Vo)1/2.
In a Grown Junction, the charge density (r) varies linearly with distance (x)
as shown in Fig. 2.1(c)(ii). If a similar analysis is carried for this junction, it is
found that W varies as (Vo)1/3 instead of (Vo)1/2.
Let us now derive the expression for the total current as a function of applied
voltage assuming that the width of the depletion region is zero. When a forward bias is applied to a diode, holes are injected from the P-side into the
N-side. Due to this, the concentration of holes in the N-side (pn) is increased
from its thermal equilibrium value (pno) and injected hole concentration [Pn
(x)] decreases exponentially with respect to distance (x).
Pn (x) = pn – pno = Pn (0) e–x/Lp
where Lp is the diffusion length for holes in the N-material.
pn (x) = pno + Pn (0) e–x/Lp
(2.1)
Injected hole concentration at x = 0 is
Pn (0) = pn (0) – pno
(2.2)
In these several components of hole concentration in the N-side of a forward
biased diode the density pn (x) decreases exponentially with distance (x).
Let pp and pn be the hole concentration at the edges of the space charge in the
P-and N-sides, respectively. Let VB (= Vo – V) be the effective barrier potential
across the depletion layer. Then
pp = Pn eVB /V
T
(2.3)
where V T is the volt-equivalent of temperature.
This is the Boltzmann’s relation of kinetic gas theory. This equation is valid as
long as the hole current is small compared with diffusion or drift current. This
condition is called low level injection.
Under open circuit condition (i.e. V = 0), pp = ppo, pn = pno and VB = Vo. Equation
(2.20) can be changed into
ppo = pno eVo /VT
(2.4)
Under forward bias condition let V be the applied voltage, then the effective
barrier voltage
VB = Vo – V
The hole concentration throughout the P-side is constant and equal to the thermal equilibrium value (pp = ppo). The hole concentration varies exponentially
with distance into the N-side.
At x = 0, pn = pn (0)
Equation (2.3) can be changed into
ppo = pn (0) e(Vo – V) /VT
(2.5)
Comparing Eqs (2.4) and (2.5),
pn(0) = pno eV /VT
This boundary condition is called the law of the junction. Substituting this into
Eq. (2.2), we get
Pn(0) = pno ( eV/VT – 1 )
(2.6)
The diffusion hole current in the N-side is
dpn(x)
Ipn (x) = – Ae Dp______
dx
d
= – Ae Dp ___ [ pno + Pn(0) e–x/Lp ]
dx
AeDp Pn(0)
= __________ e–x/Lp
Lp
From this equation, it is evident that the injected hole current decreases exponentially with distance.
The hole current crossing the junction into the N-side
with x = 0 is
AeDp Pn(0) AeDp pno
Ipn(0) = __________ = ________ ( eV/VT – 1 )
Lp
Lp
The electron current crossing the junction into the P-side with x = 0 is
AeDn Np(0) AeDn npo
Inp(0) = __________ = ________ (eV/VT – 1)
Ln
Ln
The total diode current,
I = Ipn (0) + Inp (0) = Io ( eV/VT – 1 )
Ae Dp pno AeDn npo
where Io = _________ + ________ = reverse saturation current.
Lp
Ln
If we consider carrier generation and recombination in the space-charge region,
the general equation of the diode current is approximately given by
I = Io [ e(V/h VT) – 1 ]
where V = external voltage applied to the diode, and h = a constant, 1 for germanium and 2 for silicon.
2
n2i
i
___
___
We know that pn =
and np =
. Applying
ND
NA
these relationships in the above equation of reverse saturation current, Io, we
get
[
]
Dp
Dn
Io = Ae ______ + ______ n2i
Lp ND Ln NA
where 2i = Ao T3 e–EGo /kT = Ao T3 e–VGo/VT, where VGo is a voltage which is
numerically equal to the forbidden gap energy EGo in electron volts.
For a germanium diode, the diffusion constants Dp and Dn vary approximately
inversely proportional to T.
Hence, the temperature dependence of Io is
–VGo
_____
VT
Io = K1 T 2 e
where K1 is a constant independent of temperature.
For a silicon diode, Io is proportional to ni instead of n2i . Hence,
3
__
–VGo
_____
Io = K2 T 2 e 2VT
where K 2 is a constant independent of temperature.
The diode current equation relating the voltage V and current I is given by
I = Io [ e(V/hVT) – 1 ]
where
where
I=
Io =
V=
h =
VT =
diode current
diode reverse saturation current at room temperature
external voltage applied to the diode
a constant, 1 for germanium and 2 for silicon
kT/q= T/11600, volt-equivalent of temperature, i.e., thermal
voltage,
k = Boltzmann’s constant (1.38 × 10 –3 J/K)
q = charge of the electron (1.602 × 10 –19 C)
T = temperature of the diode junction (K) = (°C + 273°)
At room temperature, (T = 300 K), V T = 26 mV. Substituting this value in the
current equation, we get
I = Io [e (40 V/h) – 1]
Therefore, for germanium diode, I = Io [e40V – 1], since h = 1 for germanium.
For silicon diode, I = Io [e20V – 1], since h = 2 for silicon.
If the value of applied voltage is greater than unity, then the equation of diode
current for germanium,
I = Io (e40V)
and for silicon,
I = Io (e20V)
When the diode is reverse biased, its current equation may be obtained by
changing the sign of the applied voltage V. Thus, the diode current with reverse
bias is
I = Io [ e(–V/h VT) – 1 ]
If V >> V T, then the term e(–V/h VT) << 1, therefore I ª – Io, termed as reverse
saturation current, which is valid as long as the external voltage is below the
breakdown value.
When a reverse bias is applied to a germanium PN junction diode, the reverse saturation current at room temperature is 0.3 mA. Determine the current flowing in the
diode when 0.15 V forward bias is applied at room temperature.
Solution
Given Io = 0.3 × 10 –6 A and VF = 0.15 V
The current flowing through the PN diode under forward bias is
I = Io ( e40 VF – 1 )
= 0.3 × 10 –6 (e40 × 0.15 – 1)
= 120.73 mA
The reverse saturation current of a silicon PN junction diode is 10 mA. Calculate the
diode current for the forward-bias voltage of 0.6 V at 25 °C.
Solution
Given
VF = 0.6 V, T = 273 + 25 = 298 K
Io = 10 mA = 1 × 10 –5 A and h = 2 for silicon.
The volt-equivalent of the temperature (T ) is
298
T
VT = ______ = ______ = 25.7 × 10–3 V
11,600 11,600
(
VF
____
–1
Therefore, the diode current, I = Io e hVT
(
)
0.6
_____________
I = 10–5 e 2 × 25.7 × 10–3 – 1
)
= 1.174 A
The diode current is 0.6 mA when the applied voltage is 400 mV, and 20 mA when
kT
the applied voltage is 500 mV. Determine h. Assume ___
q = 25 mV
Solution
The diode current,
Therefore,
I = Io
(e
qV
____
hkT
(
qV
____
–1
)
)
qV
____
0.6 × 10 –3 = Io e hkT – 1 = Io e hkT
400
____
16
___
500
____
20
___
= Io ◊ e 25h = Io ◊ e h
Also,
20 × 10 –3 = Io ◊ e 25h = Io ◊ e h
(1)
(2)
Dividing Eq. (2) by Eq. (1), we get
20
___
Io ◊ e h
20 × 10
_________
______
=
16
___
0.6 × 10–3
Io ◊ e h
–3
4
__
100
____
= eh
3
Taking natural logarithms on both sides, we get
100 4
loge ____ = __
h
3
Therefore,
4
3.507 = __
h
Therefore,
4
h = _____ = 1.14
3.507
Find the voltage at which the reverse current in a germanium PN junction diode
attains a value of 90% of its saturation value at room temperature.
Solution
We know that the current of a PN junction diode is
(
(e
V
___
)
– 1)
I = Io e VT – 1
Therefore,
where
– 0.90 Io = Io
V
___
VT
T
V T = ______ = 26 mV
11,600
(
V
_____
–0.9 = e 0.026 – 1
)
V
_____
0.1 = e 0.026
Therefore,
V = – 0.06 V
When positive terminal of the battery is connected to the P-type and negative
terminal to the N-type of the PN junction diode, the bias applied is known as
forward bias.
As shown in Fig. 2.2, the applied potential with external battery acts in opposition to the internal potential barrier and disturbs the
equilibrium. As soon as equilibrium is disturbed by the application of
an external voltage, the Fermi level is no longer continuous across the
junction. Under the forward bias condition, the applied positive potential repels the holes in P-type region so that the holes move towards the
Holes flow
P
+
–
+
N
–
+
–
+
–
+
+
+
+
–
+
+
+
+
+
–
+
–
+
–
–
+
–
+
–
+
–
+
–
+
–
+
–
Electrons flow
+
W
–
junction and the applied negative potential repels the electrons in the
N-type region and the electrons move towards the junction. Eventually, when
the applied potential is more than the internal barrier potential, the depletion
region and internal potential barrier disappear.
Under forward bias condition, the V–I characteristics of a PN unction diode are shown in Fig. 2.3. As
the forward voltage (VF ) is increased, for VF < VO, the forward current IF is
almost zero (region OA) because the potential barrier prevents the holes from
P-region and electrons from N-region to flow across the depletion region in the
opposite direction.
IF(mA )
Ge Si
B
0
A
0.3 V
0.7 V
VF(V )
For VF > VO, the potential barrier at the junction completely disappears and
hence, the holes cross the junction from P-type to N-type and the electrons
cross the junction in the opposite direction, resulting in relatively large current
flow in the external circuit.
A feature worth to be noted in the forward characteristics shown in Fig. 2.3 is
the cut in or threshold voltage (Vr) below which the current is very small. It is
0.3 V and 0.7 V for germanium and silicon, respectively. At the cut in voltage,
the potential barrier is overcome and the current through the junction starts to
increase rapidly.
When the negative terminal of the battery is connected to the P-type and positive terminal of the battery is connected to the N-type of the PN junction, the
bias applied is known as reverse bias.
P
–
N
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
W
Holes
+
V
Electrons
Under applied reverse bias as shown in Fig. 2.4, holes which
form the majority carriers of the P-side move towards the negative terminal
of the battery and electrons which form the majority carrier of the N-side are
attracted towards the positive terminal of the battery. Hence, the width of the
depletion region which is depleted of mobile charge carriers increases. Thus,
the electric field produced by applied reverse bias, is in the same direction as
the electric field of the potential barrier. Hence, the resultant potential barrier
is increased which prevents the flow of majority
carriers in both directions;
___
the depletion width, W, is proportional to ÷Vo under reverse bias. Therefore,
theoretically no current should flow in the external circuit. But in practice, a
very small current of the order of a few microamperes flows under reverse bias
as shown in Fig. 2.5. Electrons forming covalent bonds of the semiconductor
atoms in the P- and N-type regions may absorb sufficient energy from heat and
light to cause breaking of some covalent bonds. Hence electron–hole pairs are
continually produced in both the regions. Under the reverse bias condition, the
thermally generated holes in the P-region are attracted towards the negative
terminal of the battery and the electrons in the N-region are attracted towards
the positive terminal of the battery. Consequently, the minority carriers, electrons in the P-region and holes in the N-region, wander over to the junction
and flow towards their majority carrier side giving rise to a small reverse current. This current is known as reverse saturation current, Io. The magnitude of
IF
VR
VF
0
Breakdown
voltage
IR(mA )
reverse saturation current mainly depends upon junction temperature because
the major source of minority carriers is thermally broken covalent bonds.
For large applied reverse bias, the free electrons from the N-type moving
towards the positive terminal of the battery acquire sufficient energy to move
with high velocity to dislodge valence electrons from semiconductor atoms in
the crystal. These newly liberated electrons, in turn, acquire sufficient energy
to dislodge other parent electrons. Thus, a large number of free electrons are
formed which is commonly called as an avalanche of free electrons. This leads
to the breakdown of the junction leading to very large reverse current. The
reverse voltage at which the junction breakdown occurs is known as Breakdown
Voltage, VBD.
Figure 2.6 shows the current-voltage characteristics of PN junction. The characteristics of the PN junction vary enormously depending upon the polarity of
the applied voltage. For a forward-bias voltage, the current increases exponentially with the increase of voltage. A small change in the forward-bias voltage
increases the corresponding forward-bias current by orders of magnitude and
hence the forward-bias PN junction will have a very small resistance. The level
of current flowing across a forward-biased PN junction largely depends upon
the junction area. In the reverse-bias direction, the current remains small, i.e.,
almost zero, irrespective of the magnitude of the applied voltage and hence the
reverse-bias PN junction will have a high resitance. The reverse bias current
depends on the area, temperature and type of semiconductor material.
The semiconductor device that displays these I-V characteristics is called a PN
junction diode. Figure 2.7 shows the PN junction diode with forward-bias and
reverse-bias and their circuit symbols. The metal contacts are indicated with
which the homogeneous P-type and N-type materials are provided. Thus two
metal-semiconductor junctions, one at each end of the diode, are introduced.
The contact potential across these junctions is approximately independent of the
direction and magnitude of the current. A contact of this type is called an ohmic
contact, which has low resistance. In the forward-bias, a relatively large current
IF (mA)
4
3
2
1
VR(V )
– 1.0
IR = –Io
1.0
VF(V )
is produced by a fairly small applied voltage. In the reverse-bias, only a very
small current, ranging from nanoamps to microamps is produced. The diode
can be used as a voltage controlled switch, i.e., OFF for a reverse-bias voltage
and ON for a forward-bias voltage.
When a diode is reverse-biased by atleast 0.1V, the diode current is IR = – Io.
As the current is in the reverse direction and is a constant, it is called the diode
reverse saturation current. Real diodes exhibit reverse-bias current that are considerably larger than Io. This additional current is called a generation current
which is due to electrons and holes being generated within the space-charge
region. A typical value of I0 may be 10 – 14 A and a typical value of reverse-bias
current may be 10 – 9 A.
The reverse saturation current Io is temperature dependent while voltage equivalent of temperature VT is also temperature dependent. Hence, the diode current
involving Io and VT is temperature dependent. The overall diode characteristics
depends on the temperature.
The dependence of Io on temperature T is given by
Io = KT me – VGo /hVT
where
(2.7)
K = constant independent of temperature (not the Boltzmann’s
constant)
m = 2 for Ge and 1.5 for Si
and VGo = forbidden energy gap = 0.785 V for Ge and 1.21 V for Si.
As temperature increases, the value of Io increases and hence the diode current
increases. To keep diode current constant, it is necessary to reduce the applied
voltage V of the diode.
Let us calculate, the rate of change of the applied voltage to keep the diode curdI
rent constant. For a constant diode current, ____ = 0. Hence, a change in voltage
dT
has to be calculated.
A diode current equation is given by
I = Io (eV/hVT – 1)
Since I >> Io for a forward characteristics, we have
I = Io eV/hVT
(2.8)
Substituting (Eq. 2.7) into Eq. 2.8, we get
I = KT m e – VGO /hVT ◊ eV/hVT
= KT m e(V–VGO)/hVT
(2.9)
Since VT = kT, where k is Boltzmann’s constant,
I = KT m e(V – VGO)/h kT
For a constant diode current, dI/dT = 0. Hence, differentiating the above equation with respect to T, we get
dI
d V – VGo
___
= K mT m – 1 e(V – VGo)/hkT + Tm e (V – VGo)/hkT ◊ ___ _______
dT
dT
hkT
[
)]
(
= K e(V – VGo)/hkT
[
(
dV
___
– (V – VGo) × 1
m T
dT
T
mT m – 1 + ___ __________________
hk
T2
[
(
dV
mTm
Tm
= K e(V–VGo)/hkT _____ + _____2 T ___ – (V – VGo
T
dT
hkT
)]
)]
Note that VGo is forbidden energy gap at 0 K and hence it is a constant from
differentiation point of view.
Taking Tm outside and rearranging the above equation, we get
dI
___
= K e(V–VGo)/hkT × T m
dT
[
(
)
dV
mhkT + T ___ – (V – VGo)
dT
________________________
hkT 2
]
[
(
)]
[
(
)]
dV
Tm
= K e (V – VGo)/hkT × _____2 mhkT + T ___ – (V – VGo)
dT
hkT
Replacing kT with VT, we get
dV
dI
T m–1
___
= K e (V – VGo)/hkT × _____ mhVT + T ___ – (V – VGo)
hVT
dT
dT
dI
Now ___ = 0 for constant diode current. Hence, equating the above equation to
dT
zero, we get
dV
mhVT + T ____ – (V – VGo) = 0
dT
dV
T ___ = V – VGo – mhVT
dT
V – (VGo – mhVT)
dV ________________
___
=
T
dT
This is the required change in voltage necessary to keep diode current constant.
Hence, for germanium, at cut-in voltage V = Vg = 0.2 V and with m = 2, h = 1,
T = 30 K and VGo = 0.785 V in the above equation, we get
0.2 – (0.785 + 2 × 1 × 26 × 10 – 3)
dV ____________________________
___
=
= – 2.12 mV/°C for Ge
300
dT
The negative sign indicates that the voltage must be reduced at a rate of 2.12 mV
per degree change in temperature to keep diode current constant.
dV
Similarly, ___ = – 2.3 mV/°C, for Si
dT
dV
Practically, the value of ___ is assumed to be –2.5 mV/°C for either Ge or Si at
dT
room temperature.
Thus,
dV
___
= – 2.5 mV/°C
dT
(2.10)
The negative sign indicates that dV/dT decreases with increase in temperature.
To study by what rate Io changes with respect to temperature, consider Eq. (2.7)
again. That is,
Io = KTm e–VGo/hVT
Taking logarithm on both sides, we get
ln (Io) = ln (KTm e – VGo/hVT)
VGo
= ln K + ln Tm – ____
hVT
Substituting VT = kT, we get
VGo
= ln K + m ln T – ____
hVT
VGo
ln (Io) = ln K + m ln T – ____
hkT
Differentiating this equation with respect to T, we get
( )
VGo
d ln (Io)
m VGo – 1
m
_______
= 0 + __ – ____ ◊ ___
= __ + _____2
2
T hk
T
dT
T
hkT
Replacing kT with VT we have
VGo
d [ln Io] __
m
_______
= + ______
T hTVT
dT
For germanium, substituting the values of various terms terms at room temperature, we get
d [ln Io] ____
0.785
2
_______
=
+ __________________ = 0.11 per °C
300 1 × 300 × 26 × 10 – 3
dT
This indicates that Io increases by 11 % per degree rise in temperature. For silicon, we get
d [ln Io]
_______
= 0.08 per °C
dT
This indicates that Io increases by 8% per degree rise in temperature.
Practically it is found that the reverse saturation current Io increases by 7 % per
°C change in temperature for both silicon and germanium diodes. If at T°C is
1 mA, then at (T + 1) °C, it becomes 1.07 mA and so on. From this, it can be
concluded that reverse saturation current approximately doubles i.e 1.0710 for
every 10°C rise in temperature.
The above result can be mathematically represented as,
(
T2 – T1
_______
10
I02 = 2
)I
01
DT
( ___
)
= 2 10 I01
where I02 is the, reverse saturation current at T2 and I01 is the reverse saturation
current at T1.
The rise in temperature increases the generation of electron–hole pairs in semiconductors and increases their conductivity. As a result, the current through
the PN junction diode increases with temperature as given by the diode current
equation,
I = Io [e(V/hVT) – 1]
The reverse saturation current Io of diode increases approximately 7 percent/°C
for both germanium and silicon. Since (1.07)10 ª 2, reverse saturation current
approximately doubles for every 10°C rise in temperature. Hence, if the temperature is incrcased at fixed voltage, the current I increases. To bring the current I to its original value, the voltage V has to be reduced. It is found that at
dV
room temperature for either germanium or silicon, ___ ª – 2.5 mV/°C in order to
dT
maintain the current I to a constant value.
At room temperature, i.e. at 300 K, the value of barrier voltage or cut-in voltage is about 0.3 V for germanium and 0.7 V for silicon. The barrier voltage is
temperature dependent and it decreases by 2 mV/°C for both germanium and
silicon. This fact may be expressed in mathematical form, which is given by
Io2 = Io1 × 2 (T2 – T1)/10
where Io1 = saturation current of the diode at temperature (T1), and I02 = saturation current of the diode at temperature (T2).
Figure 2.8 shows the effect of increased temperature on the characteristic curve
of a PN junction diode. A germanium diode can be used up to a maximum of
75 °C and a silicon diode to a maximum of 175 °C.
IF (mA)
75° C
25° C
VF (volts)
VR (volts)
0
25° C
75° C
IR (mA)
The voltage across a silicon diode at room temperature (300 K) is 0.7 Volts when
2 mA current flows through it. If the voltage increases to 0.75 V, calculate the diode
current (assume VT = 26 mV).
Solution
Given data
Room temperature = 300 K
Voltage across a silicon diode, VD1 = 0.7 V
Current through the diode ID1 = 2 mA
When the voltage increases to 0.75 V, VD2, then
–3
Io (eVD2/VTh – 1) ________________
ID2 ______________
e0.75/26 × 10 × 2 – 1
___
=
=
= 2.615
–3
ID1 I (eVD1/VTh – 1)
e0.7/26×10 × 2 – 1
o
Therefore,
ID2 = 2.615 × ID1
= 2.615 × 2 × 10 – 3 = 5.23 mA
A silicon diode has a saturation current of 7.5 mA at room temperature 300 K.
Calculate the saturation current at 400 K.
Solution
Given Io1 = 7.5 × 10 – 6 A at T1 = 300 K = 27°C and T2 = 400
K = 127°C
Therefore, the saturation current at 400 K is
Io2 = Io1 × 2(T2 – T1)/10
= 7.5 × 10 – 6 × 2(127 – 27)/10
= 7.5 × 10 – 6 × 210 = 7.68 mA
The reverse saturation current of the Ge transistor is 2 mA at room temperature of
25°C and increases by a factor of 2 for each temperature increase of 10°C. Find the
reverse saturation current of the transistor at a temperature of 75°C.
Solution
Given Io1 = 2 mA at T1 = 25°C, T2 = 75°C
Therefore, the reverse saturation current of the transistor at T2 = 75°C is
Io2 = Io1 × 2(T2 – T1)/10 = 2 × 10 – 6 × 2(
75 – 25
______
10
)
= 2 × 10 – 6 × 25 = 64 mA
An ideal diode should offer zero resistance in forward bias and infinite resistance in the reverse bias. But in practice no diode can act as an ideal diode, i.e.
an actual diode does not behave as a perfect conductor when forward biased and
as a perfect insulator when reverse biased. Let us consider four resistances of the
I (mA)
I
V
0
VF (V )
diode (a) d.c. or static resistance, (b) a.c. or dynamic resistance, (c) average a.c.
resistance and (d) reverse resistance.
It is defined as the ratio of the voltage to the
current, V/I, in the forward bias characteristics of the PN junction diode. In the
forward bias characteristics of the diode as shown in Fig. 2.9, the d.c. or static
resistance (RF) at the operating point can be determined by using the correV
sponding levels of voltage V and current I, i.e. RF = __. Here, the d.c. resistance
I
is independent of the shape of the characteristics in the region surrounding the
point of interest. The d.c. resistance levels at the knee and below will be greater
than the resistance levels obtained for the characteristics above the knee. Hence,
the d.c. resistance will be low when the diode current is high. As the static resistance varies widely with V and I, it is not a useful parameter.
It is defined as the reciprocal of the slope of
the volt-ampere characteristics.
change in voltage
DV
rf = _______________________ = ___
resulting change in current DI
A straight line drawn tangent to the curve through the Quiescent Point (Q-point)
as shown in Fig. 2.10(a) will define a specific change in voltage and current
which may be used to determine the a.c. or dynamic resistance for this region
of the diode characteristics. As shown in Fig. 2.10(b), for a small change in
voltage, there will be a corresponding change in current, which is equidistant to
either side of the Q-point. Hence, the a.c. or dynamic resistance is determined
DV
as rf = ___.
DI
The derivative of a function at a point is equal to the slope of the tangent line
drawn at the point. The Schockley’s equation for the forward and reverse bias
regions is defined by
I = Io (eV/hVT – 1)
IF (mA)
30
DI
25
20
DV
15
10
Q-point
Dv
DI
6
4
2
DI
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DV
(b)
(a)
Taking the derivative of the above equation w.r.t. the applied voltage, V, we
get
d
dI
___
= ___ [I (eV/hVT – 1)]
dV dV o
[
1
= Io ____ ◊ eV/hVT
hVT
]
IoeV/hVT
= __________
hVT
I + Io
= _____
hVT
Generally I >> Io in the vertical-slope section of the characteristics. Therefore,
dI ____
I
___
@
dV hVT
Therefore,
hVT
dV
___
= rf = ____
I
dI
hVT
The dynamic resistance varies inversely with current, i.e. rf = ____, where
I
VT = T/1600, the volt equivalent of temperature (T) of the diode junction (K)
and h is a constant whose value is equal to 1 for Germanium and 2 for Silicon
diodes. At room temperature VT = 26 mV.
a.c. resistance of a diode is the sum of bulk resistance rb and junction resistance rj. Bulk resistance (rb) is the sum of ohmic resistance of the P-and N-type
semiconductors.
It is the resistance associated with the device for the
region if the input signal is sufficiently large to produce a wide range of the characteristics as shown in Fig. 2.11. Therefore,
|
DV
rav = ___ point to point
DI
As with the d.c. and a.c. resistance levels, the lower the level of currents used to
determine the average, the higher is the resistance level.
It is the resistance offered by the PN junction diode under
reverse bias condition. It is very large compared to the forward resistance, which
is in the range of several MW.
IF (mA)
20
15
DI
10
5
0 0.1 0.20.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VF (V )
Dv
Determine the forward resistance of a PN junction diode when the forward current
is 5 mA at T = 300 K. Assume silicon diode.
Solution Given For a silicon diode, the forward current, I = 5 mA,
T = 300 K
hVT
T
Forward resistance of a PN junction diode, rf = ____, where VT = ______ and
I
11,600
h = 2 for silicon
T
2 × ______
11,600
2 × 300
Therefore, rf = __________
= ________________
= 10.34 W
–3
5 × 10
11,600 × 5 × 10 – 3
Find the value of dc resistance and ac resistance of a germanium junction diode at
25°C with Io = 25 mA and at an applied voltage of 0.2 V across the diode.
[JNTU Dec. 2004, May 2007]
Solution
Given
Io = 25 mA, T = 25°C = 298 K and V = 0.2 Volts
(
d.c. resistance
)
(
)
V
0.2
I = Io _______
= 25 × 10 – 6 __________
= 54.79 mA
26×10 – 3
ehVT – 1
e
–1
V
0.2
RF = __ = ___________
= 3.65 W
I 54.79 × 10 – 3
For germanium,
KT
h = 1, VT = ___
q = 25.71 mV
a.c. resistance
hVT 25.71 × 10 – 3
rf = ____ = ___________
= 0.47 W
I
54.79 × 10 – 3
Calculate the dynamic forward and reverse resistance of a PN junction diode when
the applied voltage is 0.25 V at T = 300 K given Io = 2 mA.
[JNTU Dec. 2004, Aug. 2008]
Solution
Given
At
V = 0.25 V, T = 300 K, Io = 2 mA
T = 300 K, VT = 26 mV.
Assuming it to be silicon diode, h = 2
Therefore,
(
)
(
)
____
0.25
I = Io e hVT – 1 = 2 × 10 – 6 _____________
= 0.24 mA
2 × 26 × 10 – 3
e
–1
V
hVT 2 × 26 × 10 – 3
rf = ____ = ____________
= 216.67 W
I
0.24 × 10 – 3
For germanium diode, h = 1.
(
)
(
)
V
0.25
I = Io _______
= 2 × 10 – 6 __________
= 0.03 A
26×10 – 3
ehVT – 1
e
–1
Reverse resistance
hVT 26 × 10 – 3
rf = ____ = _________ = 0.867 W
I
0.03
V ________
0.25
__
=
= 125 kW
I
2 × 10 – 6
A PN-junction diode has a reverse saturation current of 30 mA at a temperature,
of 125°C. At the same temperature, find the dynamic resistance for 0.2 V bias in
forward and reverse directions.
[JNTU Aug. 2006, May 2007, Feb. 2010]
Solution
V = 0.2 V
Given The reverse saturation current, Io = 30 × 10 – 6 A and
hVT
We know that the dynamic resistance = _______
IoeV/hVT
125 + 273
T
Here, h = 1 for germanium and VT = ______ = _________ = 34.3 mV
11,600
11,600
34.3 × 10 – 3
Therefore, forward dynamic resistance rf = ____________________
= 3.356 W
30 × 10 – 6 (e0.2/34.3×10 – 3)
Reverse dynamic resistance,
hVT
34.3 × 10 – 3
rr = ________
= ______________________
= 389.5 kW
– V/hVT
Ioe
30 × 10 – 6 (e – 0.2/34.3 × 10 – 3)
If two similar Germanium diodes are connected back to back and the voltage V is
impressed upon, calculate the voltage across each diode and current through each
diode. Assume similar value of Io = 1 mA for both the diodes and h = 1.
[JNTU Dec. 2004]
Solution
The arrangement is shown in Fig. 2.12.
I0
D1
D2
VD
VD
1
2
+ –
V
As D1 is reverse biased, the total current flowing in the circuit is I0 = 1mA. The
diode D2 is forward biased and its forward current is equal to the reverse current
I0 = 1mA, which can flow as D1 is reverse biased.
For diode D2, I = I0 = 1 mA and voltage across D2 is VD2.
I = I0 [eV/hVT – 1]
Therefore,
VD /hVT
or
Hence,
I0 = I0 [e
2
– 1]
VD /hVT
e
=1+1=2
V
D2
____
= ln 2
hVT
2
VD2 = hVT × ln 2 = 1 × 26 × 10 – 3 × 0.6931 = 0.01802 V
Therefore,
VD1 = V – VD2 = V – 0.01802 V
The current through the diodes D1 and D2 is I = I0 = 1 mA
Determine the forward resistance of a PN junction diode, when the forward current
is 5 mA at T = 300 K. Assume Silicon diode.
Solution Given: For a silicon diode, the forward current, I = 5 mA.
T = 300 K
hVT
T
Forward resistance of a PN junction diode, rf = ____ where VT = ______ and
I
11,600
h = 2 for silicon
T
2 × ______
11,600 ________________
2 × 300
__________
Therefore, rf =
=
= 10.34 W
–3
5 × 10
11,600 × 5 × 10 – 3
Under reverse bias condition, the majority carriers move away from the junction, thereby uncovering more immobile charges. Hence, the width of the
space–charge layer at the junction increases with reverse voltage. This increase
in uncovered charge with applied voltage may be considered a capacitive effect.
The parallel layers of oppositely charged immobile ions on the two sides of the
junction form the capacitance, CT, which is expressed as
| |
dQ
CT = ___
dV
where dQ is the increase in charge caused by a change in voltage dV. A change
in voltage dV in a time dt will result in a current I = dQ/dt given by
dV
I = CT ___
dt
Therefore CT is important while considering a diode or a transistor as a circuit
element. The quantity CT is called the transition, space–charge, barrier or
depletion region capacitance.
A PN junction is formed from a single-crystal intrinsic semiconductor by doping
part of it with acceptor impurities and the remaining with donors. A junction
between P-type and N-type materials may be fabricated in a variety of ways.
The change in impurity concentration from P to N-type semiconductor occurs
in a very short length, typically much less than 1 mm. In an abrupt PN junction,
there is a sudden step change from acceptor ions on one side to donor ions on
the other side. Such a junction is fabricated by placing trivalent indium against
N-type germanium and heating the combination to a high temperature for a
short time. Since some of the indium dissolves into the germanium, the N-type
germanium is changed into P-type at the junction. Such a step-graded junction
P-type
N-type
(a)
Charge density
ND
NA
Wp
W
Wn
(b)
Potential
VB
x=0
x = Wp
is called an alloy, or fussion junction. A step-graded junction is also formed
between emitter and base of an integrated transistor.
A diffused junction is graded in which case the donor and acceptor concentrations are functions of distance across the junction. Then the acceptor density, NA, gradually decreases and the donor density, ND, gradully increases till
NA = ND is reached. Therefore, ND increases and NA decreases to zero.
It is not necessary for the abrupt junction to be symmetrical, that is, the doping
concentrations at either side of the junction are dissimilar.
As shown in Fig. 2.13, consider a PN diode which is asymmetrically doped at
the junction. Since the net charge is zero, then eNAWp = eNDWn.
If NA >> ND , then Wp << Wn ª W. The relationship between potential and
d2V eNA
charge density is given by the Poisson’s equation, ____2 = ____
e
dx
Integrating the above equation twice,
eNA 2
ÚÚ d2V = ÚÚ ____
e dx
Therefore,
eNAx2
V = ______
2e
At x = Wp ª W, V = VB, the barrier potential that appears across the uncovered
acceptor ions. Thus
eNA W2
VB = _______
(2.11)
2e
Here VB = V0 – V, where V is a negative number for an applied reverse bias and
V0 is the contact potential. Hence, the width of the depletion layer increases with
___
applied reverse voltage, i.e., VB μ W2. Therefore, W μ ÷VB .
The total charge density of a P-type material with area of the junction A is
given by
Q = eNAWA
Differentiating the above equation w.r.t. V, we get
dQ
dW
CT = ___ = AeNA ____
dV
dV
| |
| |
(2.12)
Differentiating Eq. (2.11) w.r.t. V, we get
| |
eNA 2W dW
1 = ________ ____
2e
dV
Therefore,
e
dW
= _______
| ____
dV | eN W
(2.13)
A
Substituting Eq. (2.13) in Eq. (2.12), we get
| |
dQ
e
CT = ___ = AeNA _______
eNA W
dV
Therefore,
eA
CT = ___.
W
Here, e is the permittivity of the material, A the cross-sectional area of the
junction and W is the width of the depletion layer over which the ions are
uncovered. The depletion width, W, is given by
[
(
2eo er(Vo – V) ________
NA + ND
W = ____________
q
NA ND
)]
1/2
where V is the applied voltage and Vo is the barrier potential, or the
contact potential.
When no external voltage is applied, i.e. V = 0, the width of the depletion
region of a PN junction diode is of the order of 0.5 microns. The movement
of majority carriers across the junction causes opposite charges to be stored
at this distance W apart. This depletion region acts as a dielectric between the
two conducting P- and N-regions. Therefore, these regions act as a parallel
plate capacitor whose transition capacitance CT is approximately 20 pF with
no external bias.
When forward bias +V is applied, the effective barrier potential, VB = [Vo –
(+V)], is lowered and hence the width of the depletion region W decreases and
CT increases. Under reverse bias condition, the majority carriers move away
from the junction, thereby uncovering more immobile charges. Now the effective barrier potential, VB = [Vo – (–V)], is increased and hence, W increases
with reverse voltage and CT decreases correspondingly. The values of CT range
from 5 to 200 pF, the larger values being for the high power diodes. This property of voltage variable capacitance with the reverse bias appears in varactors,
vari-caps or volta-caps.
The capacitance that exists in a forward biased junction is called a diffusion or
storage capacitance (CD), whose value is usually much larger than CT, which
exists in a reverse-biased junction. This is also defined as the rate of change of
dQ
injected charge with applied voltage, i.e., CD = ___, where dQ represents the
dV
change in the number of minority carriers stored outside the depletion region
when a change in voltage across the diode, dV, is applied.
Let us assume that the P material in one side of the diode
is heavily doped in comparison with the N side. Since the holes move from the
P to the N side, the hole current I ª Ipn (0).
The excess minority charge Q existing on the N side is given by
•
Q = Ú AePn(0) e
–x/Lp
0
[
AePn(0) e–x/Lp
dx = ____________
– 1/Lp
]
•
= Lp AePn(0)
0
Differentiating the above equation, we get
d[Pn(0)]
dQ
CD = ___ = AeLp _______
(2.14)
dV
dV
We know that the diffusion hole current in the N-side is Ipn (x) = AeDpPn(0)/
Lp e–x/Lp. The hole current crossing the junction into the N-side with x = 0 is
AeDp Pn(0)
Ipn (0) = __________.
Lp
AeDp Pn(0)
Therefore,
I = __________
Lp
ILp
Pn (0) = _____
AeDp
Differentiating the above equation w.r.t. “V”, we get
d[Pn(0)] ___
dI _____
_______
=
dV
dV AeDp
Upon substituting in Eq. (2.14), we have
2
dQ dI L p
CD = ___ = ___ ___
dV dV Dp
L2p
dI
___
___
Therefore, CD = gt, where g =
is the diode conductance and t =
is the
Dp
dV
mean life time of holes in the N-region.
I
From diode current equation, g = ____.
hVT
Therefore,
tI
CD = ____.
hVT
where t is the mean life time for holes and electrons.
Diffusion capacitance CD increases exponentially with forward bias or, alternatively, that it is proportional to diode forward current, I. The values of CD
range from 10 to 1000 pF, the larger values being associated with the diode
carrying a larger anode current, I.
The effect of CD is negligible for a reverse-biased PN junction. As the value of
CD is inversely proportional to frequency, it is high at low frequencies and it
decreases with the increase in frequency.
The energy band diagram for a PN junction is shown in Fig. 2.14, where the Fermi
level EF is closer to the conduction band edge Ecn in the N-type material while it
is closer to the valence band edge Evp in the P-type material. It is clear that the
conduction band edge Ecp in the P-type material is higher than the conduction
band edge Ecn in the N-type material. Similarly, the valence band edge Evp in the
P-type material is higher than the valence band edge Evn in the N-type material. As illustrated in Fig. 2.14, E1 and E 2 indicate the shifts in the Fermi level
from the intrinsic conditions in the P and N materials respectively. Then the
total shift in the energy level E 0 is given by
E 0 = E1 + E 2 = Ecp – Ecn = Evp – Evn
This energy E 0 (in eV) is the potential energy of the electrons at the PN junction, and is equal to qV0, where V0 is the contact potential (in volts) or contact
difference of potential or the barrier potential.
A contact difference of potential exists
across an open circuited PN junction. We now proceed to obtain an expression
for E 0. From Fig. 2.14, we find that
1
EF – Evp = __ EG – E1
(2.15)
2
1
Ecn – EF = __ EG – E 2
2
Combining Eqs (2.15) and (2.16), we get
(2.16)
E 0 = E1 + E 2 = EG – (Ecn – EF ) – (EF – Evp)
(2.17)
We know that
np = NC NV e–EG /kT and
np = n2i (Mass-action law)
From the above equations, we get
NC NV
EG = kT ln ______
n2i
(2.18)
NC
We know that for N-type material EF = EC – kT ln ___. Therefore, from this
ND
equation, we get
NC
NC
___
Ecn – EF = kT ln ___
nn = kT ln ND
(2.19)
NV
Similarly for P-type material EF = EV + kT ln ___. Therefore, from this equaNA
tion, we get
NV
NV
___
EF – Evp = kT ln ___
pp = kT ln NA
(2.20)
Substituting from Eqs (2.18), (2.19) and (2.20) into Eqn. (2.17), we get
[
NC NV
NV
NC
___
___
E 0 = kT ln ______
–
ln
–
ln
ND
NA
n2i
[
NC NV ___
ND ___
NA
= kT ln ______
×
×
2
NC NV
ni
ND NA
= kT ln ______
n2i
]
]
(2.21)
As E 0 = qVo, then the contact difference of potential or barrier voltage is given
by
ND NA
kT ______
Vo = ___
q ln n 2
i
In the above equations, Es in electron volts and k is in electron volt per degree
Kelvin. The contact difference of potential Vo is expressed in volt and is
numerically equal to E 0. From Eqn. (2.21) we note that Eo (hence Vo) depends
upon the equilibrium concentrations and not on the charge density in the transition region.
An alternative expression for E 0 may be obtained by substituting the equations
n2i
n2i
___
____
2
of nn ª ND, pn =
, n p = ni , pp ª NA and np =
into Eqn. (2.21). Then we
ND n p
NA
get
ppo
nno
___
E0 = kT ln ___
p = kT ln n
no
po
(2.22)
where subscript 0 represents the thermal equilibrium condition.
(a) The resistivities of the P-region and N-region of a germanium diode are 6 W-cm
and 4W-cm, respectively. Calculate the contact potential Vo and potential energy
barrier Eo. (b) If the doping densities of both P and N-regions are doubled, determine Vo and Eo. Given that q = 1.602 × 10–19 C, ni = 2.5 × 1013/cm3, mp = 1800
cm2/V-s, mn = 3800 cm2 /V-s and VT = 0.026 V at 300 K.
Solution
(a) Resistivity,
1 _______
1
r = __
s = NA qmp 6 W – cm
Therefore,
1
1
NA = _____ = _____________________
= 0.579 × 1015/cm3
6qmp 6 × 1.602 × 10–19 × 1800
Similarly,
1
1
ND = _____ =_____________________
= 0.411 × 1015/cm3
4qmn 4 × 1.602 × 10–19 × 3800
Therefore,
ND NA
0.579 × 0.411 × 1030
V0 = VT ln ______
= 0.026 ln __________________
= 0.1545 V
2
ni
(2.5 × 1013)2
Hence
E 0 = 0.1545 eV
(b)
2 × 0.579 × 1015 × 2 × 0.411 × 1015
V0 = 0.026 ln ______________________________
= 0.1906 V
(2.5 × 1013)2
Therefore,
E 0 = 0.1906 eV
Consider that a PN junction has P-type and N-type materials in close physical
contact at the junction on an atomic scale. Hence, the energy band diagrams of
these two regions undergo relative shift to equalise the Fermi level. The Fermi
level EF should be constant throughout the specimen at equilibrium. The distribution of electrons or holes in allowed energy states is dependent on the
position of the Fermi level. If this is not so, electrons on one side of the junction would have an average energy higher than those on the other side, and this
causes transfer of electrons and energy until the Fermi levels on the two sides
get equalised. However, such a shift does not disturb the relative position of the
conduction band, valence band and Fermi level in any region. Equalisation of
Fermi levels in the P and N materials of a PN junction is similar to equalisation
of levels of water in two containers on being joined together.
P region
Space
charge
region
Conduction band
N region
Conduction band
Ecp
1/2EG
1/2EG
EF
Evp
E0
Ecn
E1
EF 1/2 E
G
E2
E0
E0
Valence band
1/2 EG
Evn
Valence band
When the reverse voltage reaches breakdown voltage in normal PN junction
diode, the current through the junction and the power dissipated at the junction will be high. Such an operation is destructive and the diode gets damaged.
Whereas diodes can be designed with adequate power dissipation capabilities
to operate in the breakdown region. One such
IF (mA)
diode is known as Zener diode. Zener diode is
heavily doped than the ordinary diode.
From the V–I characteristics of the Zener diode,
shown in Fig. 2.15, it is found that the operation of Zener diode is same as that of ordinary
PN diode under forward-biased condition.
Whereas under reverse-baised condition, breakdown of the junction occurs. The breakdown
voltage depends upon the amount of doping. If
the diode is heavily doped, depletion layer will
be thin and, consequently, breakdown occurs at
VR
VZ
VF
A
0
B
IR (mA)
lower reverse voltage and further, the breakdown voltage is sharp. Whereas a
lightly doped diode has a higher breakdown voltage. Thus, breakdown voltage
can be selected with the amount of doping.
The sharp increasing current under breakdown conditions are due to the following two mechanisms.
(1) Avalanche breakdown
(2) Zener breakdown.
As the applied reverse bias increases, the field across the junction increases
correspondingly. Thermally generated carriers while traversing the junction
acquire a large amount of kinetic energy from this field. As a result the velocity of these carriers increases. These electrons disrupt covalent bond by colliding with immobile ions and create new electron-hole pairs. These new carriers
again acquire sufficient energy from the field and collide with other immobile
ions thereby generating further electron–hole pairs. This process is cumulative
in nature and results in generation of avalanche of charge carriers within a short
time. This mechanism of carrier generation is known as Avalanche multiplication. This process results in flow of large amount of current at the same value
of reverse bias.
When the P and N regions are heavily doped, direct rupture of covalent bonds
takes place because of the strong electric fields, at the junction of PN diode. The
new electron–hole pairs so created increase the reverse current in a reverse biased
PN diode. The increase in current takes place at a constant value of reverse bias
typically below 6 V for heavily doped diodes. As a result of heavy doping of P
and N regions, the depletion region width becomes very small and for an applied
voltage of 6 V or less, the field across the depletion region becomes very high,
of the order of 107 V/m, making conditions suitable for Zener breakdown. For
lightly doped diodes, Zener breakdown voltage becomes high and breakdown
is then predominantly by Avalanche multiplication. Though Zener breakdown
occurs for lower breakdown voltage and Avalanche breakdown occurs for
higher breakdown voltage, such diodes are normally called Zener diodes.
Let us consider two resistances of the Zener diode (i) d.c.
or static resistance, and (ii) a.c. or dynamic resistance.
It is the ratio of total Zener diode
voltage to total diode current measured at the given operating point, i.e.
VZQ
RZ = ____. For more precise calculation, a Zener diode can be replaled by
IZQ
an ideal battery in series with a small Zener resistance RZ.
It is defined as voltage difference
DVZ
divided by current difference at the given operating point, i.e. rZ = ____. If
DIZ
the dynamic resistance is less, then the Zener diode will be better as a voltage regulator.
The Zener diode will perform satisfactorily only if it is
operated within certain limiting values. They are the following:
It is the minimum reverse current where
the breakdown becomes stable. If a Zener diode has to remain in the breakdown region, the current through it has to be more than IZ min.
It is related to the power rating PZ max as
PZ max
IZ max = ______
VZ
where VZ is the Zener voltage. This parameter gives the maximum current
a Zener diode can handle without exceeding its power rating.
The power dissipation of a Zener
diode equals the product of its Zener voltage and current, i.e. PZ = VZ ◊
IZ. As long as PZ is less than the maximum power rating PZ max, the Zener
diode can operate in the breakdown region without being destroyed.
The Zener voltage VZ changes with the temperature. The percentage change in
the Zener voltage VZ for every °C change in temperature is called temperature
coefficient (TC) of a Zener diode. It is denoted as TC and expressed as % / °C.
Mathematically it can be defined as
DVZ
TC = ___________ × [100] % / °C
VZ (T1 – T0)
where T1 is the final temperature of junction while T0 is generally 25°C at which
normal Zener voltage VZ is specified. DVZ is the resulting change in the Zener
voltage due to the temperature variation.
A positive value of TC indicates that there is an increase in VZ due to increase
in temperature or decrease in VZ due to decrease in temperature. The negative
value of TC indicates that there is an increase in VZ due to decrease in temperature or decrease in VZ due to increase in temperature.
From the above equation, we have
VZ TC (T1 – T0) VZ TC DT
DVZ = ______________ = _________
100
100
where DT is the change in temperature.
Sometimes TC for a Zener diode is expressed in mV/°C and in such a case, the
corresponding change in VZ can be obtained as
DVZ = TC (T1 – T0) = TC × DT
For a Zener diode with VZ less than 6 V, the temperature coefficient is negative and hence VZ decreases as temperature increases. While for a Zener diode
with VZ greater than 6 V, the temperature coefficient is positive and hence VZ
increases as temperature increases.
From the Zener characteristics shown in Fig. 2.15, under the reverse bias condition, the voltage across the diode remains almost constant although the current
through the diode increases as shown in region AB. Thus, the voltage across
the Zener diode serves as a reference voltage. Hence, the diode can be used as a
voltage regulator.
In Fig. 2.16 it is required to provide constant voltage across load resistance RL,
whereas the input voltage may be varying over a range. As shown, Zener diode
is reverse biased and as long as the input voltage does not fall below VZ (Zener
breakdown voltage), the voltage across the diode will be constant and hence the
load voltage will also be constant.
In an unregulated power supply, the output voltage changes whenever the input
voltage or load changes. An ideal regulated power supply is an electronic circuit
designed to provide a predetermined d.c. voltage Vo which is independent of the
load current and variations in the input voltage. A voltage regulator is an electronic circuit that provides a stable d.c. voltage independent of the load current,
temperature and a.c. line voltage variations.
The output d.c. voltage Vo depends on the
input unregulated d.c. voltage Vin, load current IL and temperature T. Hence,
the change in output voltage of power supply can be expressed as follows:
∂o
∂Vo
∂Vo
DVo = ____ DVin + ____ DIL + ____ DT
∂Vin
∂IL
∂T
DVo = SV DVin + Ro DIL + ST DT
or
where the three coefficients are defined as
DVo
SV = ____ | D IL = 0; DT = 0
DVin
DVo
Output resistance,
Ro = ____ | Vin = 0; DT = 0
DIL
DVo
Temperature coefficient, ST = ____ | DVin = 0; DIL = 0
DT
Input regulation factor,
Smaller the value of the three coefficients, better the regulation of the power
supply.
Line regulation is defined as the change in output voltage
for a change in line supply voltage, keeping the load current and temperature
constant. Line regulation is given by
change in output voltage DVo
Line regulation = ______________________ = ____
DVin
change in input voltage
Load regulation is defined as a change in regulated output
voltage as the load current changes from no load to full load. It is expressed as
a percentage of no load voltage or full load voltage.
Vno load – Vfull load
% Load regulation = _______________ × 100
Vno load
Vno load – Vfull load
or % Load regulation = _______________ × 100
Vfull load
where Vno load the output voltage at zero load current and Vfull load the output
voltage at rated load current. This is usually denoted in percentage. The plot of
the output voltage Vo versus the load current IL for a full-wave rectifier is given
in Fig. 2.17. The drop in the characteristics is a measure of the internal resistance
of the power supply.
Vo
2 Vm
p
ld.c.(rf )
lL
A zener diode, under reverse bias breakdown
condition, can be used to regulate the voltage across a load, irrespective of the
supply voltage or load current variations. A simple zener voltage regulator circuit is shown in Fig. 2.18. The zener diode is selected with Vz equal to the voltage
desired across the load. The zener diode has a characteristic that under reverse
bias condition, the voltage across it practically remains constant, even if the
current through it changes by a large extent. Under normal conditions, the input
current Ii = IL + IZ flows through resistor R. The input voltage Vi can be written
as Vi = IiR + Vz = (IL + Iz) R + Vz.
+
li = l z + l L
+ R –
+
+
li
lz
Vi
Vz
–
–
RL
V
–
When the input voltage Vi increases (say due to supply voltage variations), as
the voltage across zener diode remains constant, the drop across resistor R will
increase with a corresponding increase in IL + IZ. As VZ is a constant, the voltage across the load will also remain constant and hence, IL will be a constant.
Therefore, an increase in IL + IZ will result in an increase in IZ which will not
alter the voltage across the load.
It must be ensured that the reverse voltage applied to the zener diode never
exceeds PIV of the diode and at the same time, the applied input voltage must
be greater than the breakdown voltage of the zener diode for its operation. The
zener diodes can be used as ‘stand-alone’ regulator circuits and also as reference
voltage sources.
Design a Zener shunt voltage regulator with the following specifications: Vo = 10 V;
Vin = 20–30 V; IL = (30–50) mA; Iz = (20–40) mA
Solution
Refer to Fig. 2.18.
Selection of zener diode
Vz = Vo = 10 V
Iz max = 40 mA
Pz = Vz × Iz max = 10 × 40 × 10 – 3 = 0.4 W
Hence a 0.5WZ 10 zener can be selected.
Value of load resistance, RL
Vo
10
RL min = _____ = _________
= 200 W
IL max 50 × 10 – 3
Vo
10
RL max = _____ = _________
= 333 W
IL min 30 × 10 –3
Value of input resistance, R
Vin(max) – Vo
R max = ____________
ILmin + Iz(max)
30 – 10
= _______________
= 286 W
(30 + 40) × 10 – 3
Vin (min) – Vo
R min = ____________
IL max + Iz (min)
20 – 10
= _______________
= 143 W
(50 + 20) × 10 – 3
Therefore,
Rmax + Rmin
R = ___________ = 215 W
2
In a Zener regulator, the d.c. input is 10 V ± 20%. The output requirements are
5 V, 20 mA. Assume Iz(min) and Iz(max) as 5 mA and 80 mA respectively. Design the
Zener regulator.
Solution
The minimum Zener current is Iz (min) = 5 mA when the input voltage is minimum. Here the input voltage varies between 10 V ± 20% i.e. 8 V and
12 V.
Therefore, the input voltage Vi(min) = 8 V
Given load current IL = 20 mA and the voltage across the load, V0 = 5 V.
Therefore,
V0
5V
RL = ___ = _________
= 250 W
IL 20 × 10 – 3
Hence, the series resistance
Vi(min) – V0
R = ___________
(Iz(min) + IL)
(8 – 5)
= ______________
= 120 W
(5 + 20) × 10 – 3
The various values are given in the Zener regulator shown in Fig. 2.19.
If d.c. unregulated input is 20 V, V0 = 10 V and load current is 0–20 mA, design the
regulator. Assume for the Zener, Iz(min) = 10 mA and Iz(max) = 100 mA.
Solution
Given input voltage, Vi = 20 V
Output voltage
V0 = 10 V
Load current varies from 0 to 20 mA
Iz(min) = 10 mA, Iz(max) = 100 mA
Here,
Vz = V0 = 10 V (constant)
Applying KVL to a closed-loop circuit, Vi = IR + Vz
Hence,
20 = IR + 10
or
IR = 10
10
Therefore, R = ___ W, where I is the loop current in amperes
I
(i) Let
Iz = Iz(min) = 10 mA and IL = 0
The total current I = IL + Iz = 10 mA
Therefore,
V0
10
Rmax = ______ = ________
= 1000 W
Iz (min)
10 × 10–3
(ii) For Iz = Iz(max) = 100 mA and IL = 20 mA
I = IL + Iz (max) = 20 × 10–3 +100 = 120 mA
Therefore
10
Rmin = _________
= 83.33 W
120 × 10–3
(iii) The range of R varies from 83.33 W to 1000 W.
Design a Zener voltage regulator to meet the following specifications: Output voltage = 5 V, Load current = 10 mA, Zener wattage = 400 mW and Input voltage
= 10 V ± 2 V.
Solution
Given
V0 = 5 V, IL = 10 mA
V0
5
RL = ___ = _________
= 500 W
IL 10 × 10 – 3
Here, load resistance is
Maximum Zener Current
400 mW
Iz(max) = ________ = 80 mA
5V
The minimum input voltage required will be when Iz = 0. Under this condition,
I = IL = 10 mA
Minimum input voltage Vi(min) = Vo + IR
Hence,
or
Thererfore,
Vi(min) = 10 – 2 = 8 V
8 = 5 + (10 × 10 – 3) R
3
Rmax = _________
= 300 W
10 × 10 – 3
Now, maximum input voltage,
Vi(max) = V0 + [Iz (max) + IL]R = 5 + [(80 + 10)10 – 3]R
or
12 = 5 + (90 × 10 – 3)R
7
Rmin = _________
= 77.77 W
90 × 10 – 3
The value of R is chosen between 77.77 W and 300 W.
A 24 V, 600 mW Zener diode is used for providing a 24 V stabilized supply to a
variable load. If the input voltage is 32 V, calculate (a) the value of series resistance
required and (b) diode current when the load is 1200 .
Solution
Given V0 = 24 V, Vi = 32 V, PZ = 600 mW and RL = 1200 W
The load current,
V0
24
IL = ___ = _____ = 20 mA
RL 1200
Pz 600 × 10 – 3
Max. Zener current, Iz(max) = ___ = __________ = 25 mA
V0
24
Vi – V0
8
32 – 24
1600
Rmax = _____________ = _______________
= _________ = _____ = 177.78 W
IL(min) + Iz(max) (20 + 25) × 10 – 3 45 × 10 – 3
9
A Zener voltage regulator circuit is to maintain constant voltage at 60 V, over a
current range from 5 to 50 mA. The input supply voltage is 200 V. Determine the
value of resistance R to be connected in the circuit, for voltage regulation from load
current IL = 0 mA to IL max, the maximum possible value of IL. What is the value
[JNTU Dec. 2005, Aug. 2008]
of IL max?
Solution
Given Vz = Vo = 60 V and Vin = 200 V
(a) To find the value of resistance (R):
Vin – Vo
R = _____________
Iz(max) + IL(min)
200 – 60
140
= _________
= _________
= 2.8 kW
–3
50 × 10
50 × 10 – 3
(b) To find the value of IL(max):
If Iz(max) = 50 mA, IL(min) = 0 mA
If Iz(min) = 5 mA, IL(max) = 45 mA
Therefore,
IL(max) = 45 mA
For the Zener voltage regulation shown, determine the range of RL and IL that gives
the stabilizer voltage of 10 V.
[JNTU April 2003]
1 kW
R
Vin = 40 V
I
IZ
VZ = 10 V
IL
RL Vo = 10 V
24mA
mA
IlZZmax
(max)==24
Solution
From the circuit, I = IZ + IL
But from R,
Vin – Vo 40 – 10
I = _______ = _______3 = 30 mA
R
1 × 10
When IL is minimum, IZ is maximum and vice versa.
I = IZ(max) + IL(min)
30 mA = 24 mA + IL(min)
Therefore,
IL(min) = 6 mA
But
Vo
IL(min) = _______
RL(max)
Vo
10
RL(max) = ______ = ________ = 1.667 kW
IL(min) 6 × 10 – 3
and
I = IZ(min) + IL(max)
30 mA = 5 mA + IL(max)
IL(max) = 25 mA
But
Vo
IL(max) = ______
RL( min)
Vo
10
RL(min) = ______ = _________
= 400 W
IL(max) 25 × 10 – 3
Hence, the range of IL is 6 mA to 25 mA and that of RL is 400 W to 1.667 kW.
Determine the range of input voltage that maintains the output voltage of 10 V, for
the regulator circuit shown.
[JNTU April 2003]
1 kW
I
R
IZ
Vin
IL
VZ = 10 V
RL = 10 kW
IZmax = 24 mA
Solution
As Vo = 10 V constant and RL = 10 kW constant, we have
Vo
10
IL = ___ = ________3 = 1 mA
RL 10 × 10
When
Now
Therefore,
Vin = Vin (max), IZ = IZ (max)
I = IZ + IL
Imax = IZ(max) + IL = 24 mA + 1 mA = 2 mA.
Vin(max) – VZ
___________
= 25 mA
R
Therefore,
Vin(max) –10 = 1 × 103(25 × 10 – 3)
Vin(max) = 35 V.
When
Vin = Vin(min),
IZ = IZ(min) = 5 mA
Therefore,
Imin = IZ(min) + IL = 5 mA + 1 mA = 6 mA
Vin (min) – Vz
___________
= 6 × 10–3
R
Vin(min) –10 = 1 × 103(6 × 10 – 3)
Vin(min) = 16 V
The Light Emitting Diode (LED) is a PN junction device which emits light when
forward biased, by a phenomenon called electroluminescence. In all semiconductor PN junctions, some of the energy will be radiated as heat and some in
the form of photons. In silicon and germanium, greater percentage of energy is
given out in the form of heat and the emitted light is insignificant. In other materials such as gallium phosphide (GaP) or gallium arsenide phosphide (GaAsP),
the number of photons of light energy emitted is sufficient to create a visible
light source. Here, the charge carrier recombination takes place when electrons
from the N-side cross the junction and recombine with the holes on the P-side.
LED under forward bias and its symbol are shown in Figs. 2.24(a) and (b),
respectively. When an LED is forward biased, the electrons and holes move
towards the junction and recombination takes place. As a result of recombination, the electrons lying in the conduction bands of N-region fall into the holes
lying in the valence band of a P-region. The difference of energy between the
conduction band and the valence band is radiated in the form of light energy.
Each recombination causes radiation of light energy. Light is generated by
recombination of electrons and holes whereby their excess energy is transferred
to an emitted photon. The brightness of the emitted light is directly proportional
to the forward bias current.
Figure 2.24(c) shows the basic structure of an LED showing recombination of
carriers and emission of light. Here, an N-type layer is grown on a substrate and
a P-type is deposited on it by diffusion. Since carrier recombination takes place
in the P-layer, it is kept uppermost. The metal anode connections are made at
the outer edges of the P-layer so as to allow more central surface area for the
light to escape. LEDs are manufactured with domed lenses in order to reduce
the reabsorption problem. A metal (gold) film is applied to the bottom of the
substrate for reflecting as much light as possible to the surface of the device and
also to provide cathode connection. LEDs are always encased to protect their
delicate wires.
The efficiency of generation of light increases with the increases in injected current and with a decrease in temperature. The light is concentrated near the junction as the carriers are available within a diffusion length of the junction.
LEDs radiate different colours such as red, green, yellow, orange, blue and
white. Some of the LEDs emit infrared (invisible) light also. The wavelength of
emitted light depends on the energy gap of the material. Hence, the colour of the
emitted light depends on the type of material used is given as follows.
P
+
N
–
(b)
(a)
Emitted light
Metal
contact (+)
P
Charge carrier
combination
N
Metal
contact (–)
Electrons
Holes
(c)
Gallium arsenide (GaAs) – infrared radiation (invisible)
Gallium phosphide (GaP) – red or green
Gallium arsenide phosphide (GaAsP) – red or yellow
In order to protect LEDs, resistance of 1 kW or 1.5 kW must be connected in
series with the LED. LEDs emit no light when reverse biased. LEDs operate
at voltage levels from 1.5 to 3.3 V, with the current of some tens of milliamperes. The power requirement is typically from 10 to 150 mW with a life time
of 1,00,000 + hours. LEDs can be switched ON and OFF at a very fast speed
of 1 ns.
They are used in burglar alarm systems, picture phones, multimeters, calculators, digital meters, microprocessors, digital computers, electronic telephone
exchange, intercoms, electronic panels, digital watches, solid state video displays and optical communication systems. Also, there are two-lead LED lamps
which contain two LEDs, so that a reversal in biasing will change the colour
from green to red, or vice-versa.
When the emitted light is coherent, i.e. essentially monocromatic, then such a
diode is referred to as an Injection Laser Diode (ILD). The LED and ILD are
the two main types used as optical sources. ILD has a shorter rise time than
LED, which makes the ILD more suitable for wide-bandwidth and high-datarate applications. In addition, more optical power can be coupled into a fiber
with an ILD, which is important for long distance transmission. A disadvantage
of the ILD is the strong temperature dependence of the output characteristic
curve.
Liquid Crystal Displays (LCDs) are used for display of numeric and alphanumeric character in dot matrix and segmental displays. The two liquid crystal
materials which are commonly used in display technology are nematic and cholesteric whose schematic arrangement of molecules is shown in Fig. 2.25(a). The
most popular liquid crystal structure is the Nematic Liquid Crystal (NLC). In
this type, all the molecules align themselves approximately parallel to a unique
axis (director), while retaining the complete translational freedom. The liquid is
normally transparent, but if subjected to a strong electric field, disruption of the
well ordered crystal structure takes place causing the liquid to polarise and turn
opaque. The removal of the applied electric field allows the crystal structure to
regain its original form and the material becomes transparent.
Based on the construction, LCDs are classified into two types. They are (i)
Dynamic scattering type, and (ii) Field effect type.
The construction of a dynamic scattering liquid crystal cell is shown in Fig. 2.25(b). The display consists of two glass plates, each
coated with tin oxide (SnO2) on the inside with transparent electrodes separated
by a liquid crystal layer, 5 to 50 mm thick. The oxide coating on the front sheet
Helix axis
Pitch
Director
(i)
(ii)
(a)
Liquid crystal
Transparent electrode
Glass
Spacer
Transparent electrode for transmissive type (or) Reflecting electrode for reflective type
(b)
is etched to produce a single or multi-segment pattern of characters, with each
segment properly insulated from each other. A weak electric field applied to a
liquid crystal tends to align molecules in the direction of the field. As soon as
the voltage exceeds a certain threshold value, the domain structure collapses
and the appearance is changed. As the voltage grows further, the flow becomes
turbulent and the substance turns optically in homogenous. In this disordered
state, the liquid crystal scatters light. Thus, when the liquid is not activated, it is
transparent. When the liquid is activated, the molecular turbulence causes light
to be scattered in all directions and the cell appears to be bright. This phenomenon is called dynamic scattering.
The construction of a field effect LCD display is similar to
that of the dynamic scattering type, with the exception that two thin polarising
optical filters are placed at the inside of each glass sheet. The LCD material is of
twisted nematic type which twists the light (change in direction of polarisation)
passing through the cell when the latter is not energised. This allows light to pass
through the optical filters and the cell appears bright. When the cell is energised,
no twisting of light takes place and the cell appears dull.
Liquid crystal cells are of two types: (i) Transmittive type, and (ii) Reflective type.
In the transmittive type cell, both glass sheets are transparent so that light from
a rear source is scattered in the forward direction when the cell is activated.
The reflective type cell has a reflecting surface on one side of the glass sheet.
The incident light on the front surface of the cell is dynamically scattered by an
activated cell. Both types of cells appear quite bright when activated even under
ambient light conditions.
Liquid crystals consume small amount of energy. In a seven-segment display
the current drawn is about 25 mA for dynamic scattering cells and 300 mA for
field effect cells. LCDs require a.c. voltage supply. A typical voltage supply to
dynamic scattering LCDs is 30 V peak-to-peak with 50 Hz. LCDs are normally
used for seven-segmental displays.
(i) The voltages required are small.
(ii) They have a low power consumption. A seven segment display requires
about 140 W (20 W per segment), whereas LEDs require about 40 mW
per numeral.
(iii) They are economical.
(i) LCDs are very slow devices. The turn ON and turn OFF times are quite
large. The turn ON time is typically of the order of a few ms, while the turn
OFF time is 10 ms.
(ii) When used on d.c., their life span is quite small. Therefore, they are used
with a.c. supplies having a frequency less than 50 Hz.
(iii) They occupy a large area.
Silicon photodiode is a light sensitive device, also called photodetector, which converts light signals into electrical signals. The construction and
symbol of a photodiode are shown in Fig. 2.26. The diode is made of a semiconductor PN junction kept in a sealed plastic or glass casing. The cover is so
designed that the light rays are allowed to fall on one surface across the junction.
The remaining sides of the casing are painted to restrict the penetration of light
rays. A lens permits light to fall on the junction. When light falls on the reverse
biased PN photodiode junction, hole-electron pairs are created. The movement
of these hole-electron pairs in a properly connected circuit results in current
flow. The magnitude of the photocurrent depends on the number of charge carriers generated and hence, on the illumination of the diode element. This current
is also affected by the frequency of the light falling on the junction of the photodiode. The magnitude of the current under large reverse bias is given by
I = IS + Io (1 – eV/hVT)
where Io
IS
V
VT
h
= reverse saturation current
= short-circuit current which is proportional to the light intensity
= voltage across the diode
= volt equivalent of temperature
= parameter, 1 for Ge and 2 for Si.
The characteristics of a photodiode are shown in Fig. 2.27. The reverse current
increases in direct proportion to the level of illumination. Even when no light is
applied, there is a minimum reverse leakage current called dark current, flowing
through the device. Germanium has a higher dark current than silicon, but it
also has a higher level of reverse current.
Photodiodes are used as light detectors, demodulators and encoders. They are
also used in optical communication system, high speed counting and switch-
ing circuits. Further, they are used in computer card punching and tapes, light
operated switches, sound track films and electronic control circuits.
Phototransistor or Photodiode is a much more sensitive
semiconductor photodevice than the PN photodiode. The current produced by
a photodiode is very low which cannot be directly used in control applications.
Therefore, this current should be amplified before applying to control circuits.
The phototransistor is a light detector which combines a photodiode and a transistor amplifier. When the phototransistor is illuminated, it permits a larger flow
of current.
Figure 2.28 shows the circuit of an NPN phototran-sistor. It is usually connected in a CE configuration with the base open. A lens focuses the light on the
base-collector junction. Although the phototran-sistor has three sections, only
two leads, the emitter and collector leads, are generally used. In this device,
base current is supplied by the current created by the light falling on the basecollector photodiode junction.
When there is no radiant excitation, the minority carriers are generated thermally, and the electrons crossing from the base to the collector and the holes
crossing from the collector to the base constitute the reverse saturation collector
current ICO. With IB = 0, the collector current is given by
IC = (b + 1) ICO
When the light is turned ON, additional minority carriers are photogenerated
and the total collector current is
IC = (b + 1)(ICO + IL)
where IL is the reverse saturation current due to the light.
Current in a phototransistor is dependent mainly on the intensity of light entering the lens and is less affected by the voltage applied to the external circuit.
Figure 2.29 shows a graph of collector current IC as a function of collectoremitter voltage VCE and as a function of illumination H.
The phototransistors find extensive applica-tions in high-speed reading of computer punched cards and tapes, light detection systems, light operated switches,
reading of film sound track, production line counting of objects which interrupt
a light beam, etc.
The varactor, also called a varicap, tuning or voltage variable capacitor diode,
is a junction diode with a small impurity dose at its junction, which has the
useful property that its junction or transition capacitance is easily varied
electronically.
When any diode is reverse biased, a depletion region is formed, as seen in Fig.
2.30. The larger the reverse bias applied across the diode, the width of the depletion layer “W ” becomes wider. Conversely, by decreasing the reverse bias voltage, the depletion region width “W” becomes narrower. This depletion region
is devoid of majority carriers and acts like an insulator preventing conduction
P
N
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
+
+
–
–
W
Holes
Electrons
–
+
V
between the N and P regions of the diode, just like a dielectric, which separates
the two plates of a capacitor. The varactor diode with its symbol is shown in
Fig. 2.31(a).
As the capacitance is inversely proportional to the distance between the plates
(CT μ 1/W), the transition capacitance CT varies inversely with the reverse voltage as shown in Fig. 2.31(b). Consequently, an increase in reverse bias voltage
will result in an increase in the depletion region width and a subsequent decrease
in transition capacitance CT. At zero volt, the varactor depletion region W is
small and the capacitance is large at approximately 600 pF. When the reverse
bias voltage across the varactor is 15 V, the capacitance is 30 pF.
The varactor diodes are used in FM radio and TV receivers, AFC circuits, self
adjusting bridge circuits and adjustable bandpass filters. With improvement in
the type of materials used and construction, varactor diodes find application in
tuning of LC resonant circuit in microwave frequency multipliers and in very
low noise microwave parametric amplifiers.
The Tunnel or Esaki diode is a thin-junction diode which exhibits negative resistance under low forward bias conditions.
An ordinary PN junction diode has an impurity concentration of about 1 part
in 108. With this amount of doping, the width of the depletion layer is of the
order of 5 microns. This potential barrier restrains the flow of carriers from the
majority carrier side to the minority carrier side. If the concentration of impurity atoms is greatly increased to the level of 1 part in 103, the device characteristics are completely changed. The width of the junction barrier varies inversely
as the square root of the impurity concentration and therefore, is reduced from
5 microns to less than 100 Å (10–8 m). This thickness is only about 1/50th of the
wavelength of visible light. For such thin potential energy barriers, the electrons will penetrate through the junction rather than surmounting them. This
quantum mechanical behavior is referred to as tunneling and hence, these highimpurity-density PN junction devices are called tunnel diodes.
The V–I characteristic for a typical germanium tunnel diode is shown in Fig.
2.32. It is seen that at first forward current rises sharply as applied voltage is
increased, where it would have risen slowly for an ordinary PN junction diode
(which is shown as dashed line for comparison). Also, reverse current is much
larger for comparable back bias than in other diodes due to the thinness of the
junction. The interesting portion of the characteristic starts at the point A on the
curve, i.e. the peak voltage. As the forward bias is increased beyond this point,
the forward current drops and continues to drop until point B is reached. This
is the valley voltage. At B, the current starts to increase once again and does
so very rapidly as bias is increased further. Beyond this point, characteristic
resembles that of an ordinary diode. Apart from the peak voltage and valley
voltage, the other two parameters normally used to specify the diode behaviour
are the peak current and the peak-to-valley current ratio, which are 2 mA and
10 respectively, as shown.
2 mA
I
A
Negative
resistance
Tunnel
diode
B
0.2 mA
–v
O
50 mV
300 mV
Ordinary
diode
–I
The V–I characteristic of the tunnel diode illustrates that it exhibits dynamic
resistance between A and B. Figure 2.33 shows energy level diagrams of the
tunnel diode for three interesting bias levels. The shaded areas show the energy
states occupied by electrons in the valence band, whereas the cross hatched
regions represent energy states in the conduction band occupied by the electrons.
Electrons in conduction
band
Empty energy level
Electrons in
valance band
N
P
(a) Zero bias voltage
N
P
(b) Peak voltage
N
P
(c) Valley voltage
The levels to which the energy states are occupied by electrons on either side of
the junctions are shown by dotted lines. When the bias is zero, these lines are
at the same height. Unless energy is imparted to the electrons from some external source, the energy possessed by the electrons on the N–side of the junction
is insufficient to permit to climb over the junction barrier to reach the P-side.
However, quantum mechanics show that there is a finite probability for the electrons to tunnel through the junction to reach the other side, provided there are
allowed empty energy states in the P-side of the junction at the same energy
level. Hence, the forward current is zero.
When a small forward bias is applied to the junction, the energy level of the
P-side is lower as compared with the N-side. As shown in Fig. 2.33(b), electrons in the conduction band of the N-side see empty energy level on the P-side.
Hence, tunneling from N-side to P-side takes place. Tunneling in other directions is not possible because the valence band electrons on the P-side are now
opposite to the forbidden energy gap on the N-side. The energy band diagram
shown in Fig. 2.33(b), is for the peak of the diode characteristic.
When the forward bias is raised beyond this point, tunneling will decrease as
shown in Fig. 2.33(c). The energy of the P-side is now depressed further, with
the result that fewer conduction band electrons on the N-side are opposite to the
unoccupied P-side energy levels. As the bias is raised, forward current drops.
This corresponds to the negative resistance region of the diode characteristic. As
forward bias is raised still further, tunneling stops altogether and it behaves as a
normal PN junction diode.
The equivalent circuit of the tunnel diode
when biased in the negative resistance region
is as shown in Fig. 2.34. In the circuit, Rs
is the series resistance and Ls is the series
inductance which may be ignored except
at highest frequencies. The resulting diode
equivalent circuit is thus reduced to parallel
combination of the junction capacitance Cj
and the negative resistance –Rn. Typical values of the circuit components are Rs = 6 W,
Ls = 0.1 nH, Cj = 0.6 pF and Rn = 75 W.
Ls
Cj
Rs
–Rn
1. Tunnel diode is used as an ultra-high speed switch with switching speed of
the order of ns or ps
2. As logic memory storage device
3. As microwave oscillator
4. In relaxation oscillator circuit
5. As an amplifier
1.
2.
3.
4.
Low noise
Ease of operation
High speed
Low power
1. Voltage range over which it can be operated is 1 V less
2. Being a two terminal device, there is no isolation between the input and
output circuit.
As shown in Fig. 2.36, it is a four layer PNPN silicon device with two terminals.
When an external voltage is applied to the device in such a way that anode is
positive with respect to cathode, junctions J1 and J3 are forward biased and J2 is
reverse biased. Then the applied voltage appears across the reverse biased junction J2. Now the current flowing through the device is only reverse saturation
current.
However, as this applied voltage is increased, the current increases slowly until
the so called firing or breakover voltage
(VBO) is reached. Once firing takes place,
the current increases abruptly and the
voltage drop across the device decreases
sharply. At this point, the diode switches
over from ‘OFF’ to ‘ON’state. Once the
device is fired into conduction, a minimum
amount of current known a holding current,
IH, is required to flow to keep the device
in ON state. To turn the device OFF from
ON state, the current has to be reduced
below IH by reducing the applied voltage
close to zero, i.e. below holding voltage,
VH. Thus the diode acts as a switch during forward bias condition. The characteristic curve of a PNPN diode is shown in
Fig. 2.37.
Forward current
Reverse voltage
Saturation region
IH(mA)
Negative resistance region
IBO(mA)
Cut-off region
VH
VBO
Forward voltage
Avalanche
breakdown
Reverse current
The basic structure and circuit symbol of SCR is shown in Fig. 2.38. It is a
four layer three terminal device in which the end P-layer acts as anode, the end
N-layer acts as cathode and P-layer nearer to cathode acts as gate. As leak-
Anode (A)
A
P1
J1
N1
J2
Gate (G)
P2
J3
N2
G
K
Cathode (K)
(b) Circuit symbol
(a) Basic structure
age current in silicon is very small compared to germanium, SCRs are made of
silicon and not germanium.
SCR acts as a switch when it is forward biased. When the gate is kept open, i.e.
gate current IG = 0, operation of SCR is similar to PNPN diode. When IG < 0, the
amount of reverse bias applied to J2 is increased. So the breakover voltage VBO
is increased. When IG > 0, the amount of reverse bias applied to J2 is decreased
thereby decreasing the breakover voltage. With very large positive gate current,
breakover may occur at a very low voltage such that the characteristics of SCR
is similar to that of ordinary PN diode. As the voltage at which SCR is switched
‘ON’ can be controlled by varying the gate current IG, it is commonly called as
Forward current
IHO
With large
Reverse
voltage
IG > o
IG = o
IG < o
IBO
IG
VH VBO Forward voltage
Avalanche
breakdown
Reverse current
controlled switch. Once SCR is turned ON, the gate loses control, i.e. the gate
cannot be used to switch the device OFF. One way to turn the device OFF is by
lowering the anode current below the holding current IH by reducing the supply
voltage below holding voltage VH, keeping the gate open.
SCR is used in relay control, motor control, phase control, heater control, battery chargers, inverters, regulated power supplies and as static switches.
The operation of SCR can be explained in a
very simple way by considering it in terms of two transistors, called as the two
transistor version of SCR. As shown in Fig. 2.40, an SCR can be split into two
parts and displaced mechanically from one another but connected electrically.
Thus the device may be considered to be constituted by two transistors T1 (PNP)
and T2 (NPN) connected back to back.
T1
B
E
JE
C
JC
G
Ie1
N1
IC1
Ig
P2
Ib2
P1
Ie2
T2
JC
N1
JE
P2
Ib1 = IC2
N2
Ia
A
C
B
T2
Ik
K
E
Assuming the leakage current of T1 to be negligibly small, we obtain
Ib1 = IA – Ie1 = IA – a1IA = (1 – a1) IA
(2.23)
Also, from the Fig. 2.40, it is clear that
and
Ib1 = IC2
(2.24)
IC2 = a2IK
(2.25)
Substituting the values given in Eqs (2.24) and (2.25) in Eq. (2.23), we get
(1 – a1) IA = a2IK
We know that
IK = IA + Ig
Substituting Eq. (2.27) in Eq. (2.26), we obtain
(1 – a1) IA = a2 (IA + Ig)
i.e.
(1 – a1 – a2)IA = a2Ig
(2.26)
(2.27)
i.e.
[
a2Ig
IA = ___________
1 – (a1 + a2)
]
(2.28)
Equation (2.28) indicates that if (a1 + a2) = 1, then IA = •, i.e. the anode current
IA suddenly reaches a very high value approaching infinity. Therefore, the device
suddenly triggers into ON state from the original OFF state. This characteristic
of the device is known as its regenerative action.
The value of (a1 + a2) can be made almost equal to unity by giving a proper
value of positive current Ig for a short duration. This signal Ig applied at the gate
which is the base of T2 will cause a flow of collector current IC2 by transferring
T2 to its ON state. As IC2 = Ib1, the transistor T1 will also be switched ON. Now,
the action is regenerative since each of the transistors would supply base current
to the other. At this point even if the gate signal is removed, the device keeps on
conducting, till the current level is maintained to a minimum value of holding
current.
Holding current is the minimum value of current to hold
the device in ON-state. For turning the device OFF, the anode current should be
lowered below IH by increasing the external circuit resistance.
for control purposes. The minimum gate current is the minimum value of current required at the gate for triggering the device. The maximum gate current is
the maximum value of current applied to the device without damaging the gate.
More the gate current, earlier is the triggering of the device and vice-versa.
Voltage safety factor Vf is a ratio which is related
to the PIV, the RMS value of the normal operating voltage as,
peak inverse voltage (PIV)
__
Vf = __________________________________
÷2 × rms value of the operating voltage
The value of Vf normally lies between 2 and 2.7. For a safe operation, the normal working voltage of the device is much below its PIV.
SCRs are much superior in performance than ordinary diode rectifiers. They
find their main applications as rectifiers. Some of the rectifier circuits have been
explained in the following sections.
Though the SCR is basically a switch, it can be used
in linear applications like rectification. Fig. 2.41 shows the circuit of an SCR
half wave rectifier.
Trigger
circuit
SCR
a.c.
input
RL
V0
(a)
V0
Vm
V1
0
q
p
q
wt
(b)
During the negative halfcycle, the SCR does not conduct irrespective of the gate
current, as the anode is negative with respect to cathode and also PIV is less than
the reverse breakdown voltage.
During the positive half cycle of a.c. voltage appearing across secondary, the
SCR will conduct provided proper gate current is made to flow. The greater the
gate current, the lesser the supply voltage at which the SCR is triggered ON.
Referring to Fig. 2.41(b), the gate current is adjusted to such a value that SCR
is turned ON at a positive voltage V1 of a.c. secondary voltage which is less than
the peak voltage Vm. Beyond this, the SCR will be conducting till the applied
voltage becomes zero. The angle at which the SCR starts conducting during the
positive half cycle is called firing angle q. Therefore, the conduction angle is
(180° – q).
The SCR will block not only the negative part of the applied sinusoidal voltage, but will also block the part of the positive waveform up to a point SCR is
triggered ON. If the angle q is zero, this will be an ordinary half wave rectification. Therefore by proper adjustment of gate current, the SCR can be made to
conduct full or part of a positive half cycle, thereby controlling the power fed
to the load.
Let V = Vm sin wt be alternating voltage that appear across the secondary of the transformer. In SCR halfwave rectifier. q is the firing angle and
the rectifier conducts from q to 180° (p radians) during the positive half cycle.
Therefore, average or d.c. output,
p
Vm
1
1
Vav = ___ Ú Vm sin wt dwt = ___ [– Vm cos wt]pq = ___ (1 + cos q)
2p q
2p
2p
Vm
For q = 0°, Vav = ___
p . Here the full positive half cycle will appear across the load.
This is the value of average voltage for ordinary halfwave rectifier.
Vm
When q = 90°, Vav = ___. This shows that greater the firing angle q, the smaller
2p
is the average voltage and vice-versa.
___________________
Similarly,
_____________________
÷
V2m
1
Vrms = ___ Ú (Vm sin wt)2 dwt = ___ Ú (1 – cos 2 wt) dwt
2p q
4p q
÷
p
÷
[
_________________
V2m
sin 2 wt
= ___ wt – _______
4p
2
]
p
q
p
[ (
Vm 1
sin 2q
= ___ __
p – q + ______
2 p
2
)]
1
__
2
Vm
If q = 0, then Vrms = ___
2
The SCR full wave rectifier is shown in Fig. 2.42. It is
exactly similar to an ordinary full wave rectifier except that the two diodes have
been replaced by two SCRs. The angle of conduction can be changed by adjusting the gate currents.
During the positive half cycle of the input signal, anode of SCR1 becomes positive and at the same time the anode of SCR2 becomes negative. When the input
voltage reaches V1 as shown in Fig. 2.42(b), SCR1 starts conducting and therefore only the shaded portion of positive half cycle will pass through the load.
During the negative half cycle of the input, the anode of SCR1 becomes negative
and the anode of SCR2 becomes positive. Hence, SCR1 does not conduct and
SCR2 conducts when the input voltage becomes V1.
The main advantage of this circuit over ordinary full wave rectifier circuit is that
any voltage can be made available at the output by simply changing the firing
angle of the SCRs.
Referring to Fig. 2.42, let V = Vm sin wt be the alternating voltage
that appears between center tap and either end of secondary and q be the firing
angle.
p
Vm
Vm
1
___
___
p
Vav = __
p Ú Vm sin wt dwt = p [– cos wt]q = p [1 + cos q]
q
This is double that of a half wave rectifier, as negative half cycle is also
rectified.
In an SCR half wave rectifier, the forward breakdown voltage of SCR is 110 V for
a gate current of 1 mA. If a 50 Hz sinusoidal voltage of 220 V peak is applied, find
firing angle, conduction angle, average voltage, average current, power output and
the time during which SCR remains OFF. Assume load resistance is 100 W and the
holding current to be zero.
Solution
We know that V1 = Vm sin q
110 = 220 sin q
Therefore, firing angle,
sin q = 0.5
q = sin–1 (0.5) = 30°
Conduction angle
Average voltage,
i.e.
= 180° – q = 180° – 30° = 150°
Vm
Vav = ___ (1 + cos q)
2p
220
= ____ (1 + cos 30°) = 65.37 V
2p
Average current,
Iav = Vav/RL = 65.37/100 = 0.6537 A
Power output
As
= Vav Iav = (65.37) (0.6537) = 42.7326 W
V1 = Vm sin q = Vm sin w t
p
w t = q = 30° = __
6
p
__
2p × 50t =
6
Therefore, the time during which the SCR remains OFF is
t = 1/(2 × 6 × 50) = 1/600 = 1.667 ms
A full wave controlled rectifier employs 2 SCRs and 2 diodes in bridge configuration
to rectify 230 V, 50 Hz a.c. mains and give an output of 150 V to a resistive load of
10 W. Find the firing angle, the time during which the SCR remains OFF and the
load current.
Solution
For an SCR full-wave rectifier,
Vm
Vd.c. = ___
p (1 + cos q)
__
230 × ÷2
150 = ________
(1 + cos q)
p
Therefore,
q = 63.33°
For 50 Hz, T = 20 ms for 360°
Therefore
Load current,
20
t = ____ × 63.33° = 3.52 ms
360°
Vav 150
Iav = ___ = ____ = 15 A
RL
10
When an SCR full wave rectifier is connected across a sinusoidal voltage of 400
sin 314t, the RMS value of the current flowing through the device is 20 A. Find the
power rating of the SCR.
Solution
As the supply voltage is 400 sin 314t, Vm = 400 V
__
__
Peak inverse voltage (PIV) = ÷3 Vm = ÷3 × 400 = 692.8 V
rms value of current = 20 A
Average value of current, Iav = rms value/form factor = 20/1.11 = 18 A
Power rating of the SCR = PIV × Iav = 692.8 × 18 = 12.47 kW
The SCR bridge rectifier is shown in Fig. 2.43. During
the positive half cycle of the input a.c. voltage, SCR1 and diode D1 conduct
whereas SCR2 and diode D2 do not conduct. During the negative half cycle,
SCR2 and diode D2 conduct. As shown in Fig. 2.43(b), the conduction angle
and hence the output voltage can be changed by adjusting the gate currents of
Vm
SCR1 and SCR2. Here, the d.c. output voltage, Vav = ___
p [1 + cos q], which is
equal to that of SCR full wave rectifier.
SCR2
D1
Trigger
circuit
AC
input
SCR1
D2
RL
(a)
V0
Vm
V1
0
q
p
wt
q
(b)
Vo
If the current is lowered below IH by
increasing the external circuit resistance, the SCR will switch OFF.
+VCC
+VCC
RL
RL
The
LASCR shown in Fig. 2.44 is triggered by irradiating with light. The
arrows represent incoming light that
passes through a window and falls on
Trip
the depletion layer closer to the middle
level
junction J2 of SCR. The incident light
generates electron-hole pairs in the
(a)
(b)
device thus increasing the number of
charge carriers. This leads to the instantaneous flow of current within the
device and the device turns ON. For
light triggering to occur, the device must have high value of rate of change of
voltage with time, dV/dt.
TRIAC is a three terminal semiconductor switching device which can control
alternating current in a load. Its three terminals are MT1, MT2 and the gate
(G). The basic structure and circuit symbol of a TRIAC are shown in Fig. 2.45.
TRIAC is equivalent to two SCRs connected in parallel but in the reverse direction as shown in Fig. 2.46. So, a TRIAC will act as a switch for both directions.
The characteristics of a Triac are shown in Fig. 2.47.
MT1
G
N
N
P
MT1
MT2
N
G
P
N
MT2
(a)
(b)
Like an SCR, a TRIAC also starts conducting only when the breakover voltage
is reached. Earlier to that the leakage current which is very small in magnitude
flows through the device and therefore remains in the OFF state. The device,
when starts conducting, allows very heavy amount of current to flow through it.
The high inrush of current must be limited using external resistance, or it may
otherwise damage the device.
During the positive half cycle, MT1 is positive with respect to MT2, whereas
MT2 is positive with respect to MT1 during negative half cycle. A TRIAC is a
bidirectional device and can be triggered either by a positive or by a negative
gate signal. By applying proper signal at the gate, the breakover voltage, i.e.
firing angle of the device can be changed; thus phase control process can be
achieved.
+l
ON state
MT2 (+ve)
OFF
state
–V
–VBO
IH
–VH
V
O VH
IH
MT1 (+ve)
ON
state
–l
+VBO
OFF
state
TRIAC is used for illumination control, temperature control, liquid level control, motor speed control and as static switch to turn a.c. power ON and OFF.
Nowadays, the DIAC–TRIAC pairs are increasingly being replaced by a single
component unit known as quadrac. Its main limitation in comparison to SCR is
its low power handling capacity.
The construction and symbol of DIAC are shown in Fig. 2.48. DIAC is a three
layer, two terminal semiconductor device.
MT1
MT1
MT1 and MT2 are the two main terminals
which are interchangeable. It acts as a bidirectional Avalanche diode. It does not have
N
any control terminal. It has two junctions
P
J1
J1 and J2. Though the DIAC resembles a
N
bipolar transistor, the central layer is free
J2
from any connection with the terminals.
P
N
From the characteristic of a DIAC shown
in Fig. 2.49, it acts as a switch in both directions. As the doping level at the two ends
MT2
of the device is the same, the DIAC has
MT2
(a)
identical characteristics for both positive
(b)
and negative half of an a.c. cycle. During
the positive half cycle, MT1 is positive with
respect to MT2 whereas MT2 is positive
with respect to MT1 in the negative half
cycle. At voltage less than the breakover voltage, a very small amount of current called the leakage current flows through the device and the device remains
in OFF state. When the voltage level reaches the breakover voltage, the device
starts conducting and it exhibits negative resistance characteristics, i.e. the
Forward
current
ON
IBO
OFF
–VBO
VBO
Reverse
voltage
OFF
IBO
ON
Reverse
current
Forward
voltage
current flowing in the device starts increasing and the voltage across it starts
decreasing.
The DIAC is not a control device. It is used as triggering device in Triac
phase control circuits used for light dimming, motor speed control and heater
control.
UJT is a three terminal semiconductor switching device. As it has only one PN
junction and three leads, it is commonly called as Unijunction transistor.
The basic structure of UJT is shown in Fig. 2.50(a). It consists of a lightly doped
N-type Silicon bar with a heavily doped P-type material alloyed to its one side
closer to B2 for producing single PN junction. The circuit symbol of UJT is
shown in Fig. 2.50(b). Here the emitter leg is drawn at an angle to the vertical
and the arrow indicates the direction of the conventional current.
Referring to Fig. 2.50(c), the interbase resistance
between B2 and B1 of the silicon bar is RBB = RB1 + RB2. With emitter terminal
open, if voltage VBB is applied between the two bases, a voltage gradient is established along the N-type bar. The voltage drop across RB1 is given by V1 = hVBB,
where the intrinsic stand-off ratio h = RB1/(RB1 + RB2). The typical value of h
ranges from 0.56 to 0.75. This voltage V1 reverse biases the PN junction and
emitter current is cut-off. But a small leakage current flows from B2 to emitter
due to minority carriers. If a positive voltage VE is applied to the emitter, the PN
junction will remain reverse biased so long as VE is less than V1. If VE exceeds V1
by the cut-in voltage Vg , the diode becomes forward biased. Under this condition, holes are injected into N-type bar. These holes are repelled by the terminal
B2 and are attracted by the terminal B1. Accumulation of holes in E to B1 region
Base 2 (B2)
B2
B2
Emitter (E)
+
P
RB2
E
E +
N
VE
–
Base 1 (B1)
B1
(a)
(b)
VBB
D
V1
RB1
–
B1
(c)
reduces the resistance in this section and hence emitter current IE is increased
and is limited by VE. The device is now in the ‘ON’ state.
If a negative voltage is applied to the emitter, PN junction remains reverse biased
and the emitter current is cut-off. The device is now in the ‘OFF’ state.
Figure 2.51 shows a family of input characteristics of UJT. Here, up to the
peak point P, the diode is reverse biased and hence, the region to the left of the
peak point is called cut-off region. The UJT has a stable firing voltage VP which
depends linearly on VBB and a small firing current IP (ª 25 mA). At P, the peak
voltage VP = hVBB + Vg , the diode starts conducting and holes are injected into
N-layer. Hence, resistance decreases thereby decreasing VE for the increase in
IE. So, there is a negative resistance region from peak point P to valley point V.
After the valley point, the device is driven into saturation and behaves like a conventional forward biased PN junction diode. The region to the right of the valley
point is called saturation region. In the valley point, the resistance changes from
negative to positive. The resistance remains positive in the saturation region.
For very large IE, the characteristic asymptotically approaches the curve for
IB2 = 0.
VE
VP
Negative
resistance
region
(P) Peak point
Saturation
region
(V) Valley point
lB2 = 0
Cut-off
region
lP
lV
lE
Leakage
current
A unique characteristic of UJT is, when it is triggered, the emitter current increases
regeneratively until it is limited by emitter power supply. Due to this negative
resistance property, a UJT can be employed in a variety of applications, viz.
sawtooth wave generator, pulse generator, switching, timing and phase control
circuits.
The relaxation oscillator using UJT which is meant
for generating sawtooth waveform is shown in Fig. 2.52. It consists of a UJT
and a capacitor CE which is charged through RE as the supply voltage VBB is
switched ON.
The voltage across the capacitor increases exponentially and when the capacitor
voltage reaches the peak point voltage VP, the UJT starts conducting and the
capacitor voltage is discharged rapidly through EB1 and R1. After the peak point
voltage of UJT is reached, it provides negative resistance to the discharge path
which is useful in the working of the relaxation oscillator. As the capacitor voltage reaches zero, the device then cuts off and capacitor CE starts to charge again.
This cycle is repeated continuously generating a sawtooth waveform across CE.
The inclusion of external resistors R2 and R1 in series with B2 and B1 provides
spike waveforms. When the UJT fires, the sudden surge of current through B1
causes drop across R1, which provides positive going spikes. Also, at the time of
firing, fall of VEBI causes I2 to increase rapidly which generates negative going
spikes across R2.
By changing the values of capacitance CE or resistance RE, frequency of the
output waveform can be changed as desired, since these values control the time
constant RE CE of the capacitor charging circuit.
The time period and hence the frequency of the sawtooth wave can be calculated as follows. Assuming that the capacitor is initially
uncharged, the voltage VC across the capacitor prior to breakdown is given by
VC = VBB (1 – e – t/RE CE)
where RE CE = charging time constant of resistor-capacitor circuit, and t = time
from the commencement of the waveform.
The discharge of the capacitor occurs when VC is equal to the peak-point voltage VP, i.e.
VP = hVBB = VBB (1 – e – t/RE CE)
h = 1 – e– t/RE CE
e– t/RE CE = (1 – h)
1
t = RE CE loge ______
(1 – h)
Therefore,
1
= 2.303 RE CE log10 ______
(1 – h)
If the discharge time of the capacitor is neglected, then t = T, the period of the
wave.
Therefore, frequency of oscillation of sawtooth wave,
1
1
fo = __ = ______________________
T
1
2.303 RE CE log10 ______
(1 – h)
Design a UJT relaxation oscillator to generate a sawtooth waveform at a frequency
of 500 Hz. Assume the supply voltage VBB = 20 V, VP = 2.9 V, VV = 1.118 V,
IP = 1.6 mA and IV = 3.5 mA.
Solution
We know that
We know that hmin = 0.56
1
fo = ______________________
1
2.303 RE CE log10 ______
(1 – h)
For determining RE, we have
VBB – VP
20 – 2.9
RE < ________, i.e. RE < _________
= 10.7 kW
IP
1.6 × 10 – 3
VBB – VV
20 – 1.118
RE > ________, i.e. RE > _________
= 5.36 kW
IV
3.5 × 10 – 3
Therefore, RE is selected as 10 kW.
(
1
1
____
= 2.303 × 10 × 103 CE log10 _________
500
(1 – 0.56)
Therefore,
1
CE = _____________________
= 0.24 mF
500 × 2.303 × 104 × 0.36
So, CE is selected as 0.22 mF.
Let the required pulse voltage at B1 = 5 V
Let the peak pulse current, IE = 250 mA.
)
Therefore,
VR1
5
R1 = ____ = _________
= 20 W
IE
250 × 10–3
So, R1 is selected to be 22 W.
We select the voltage characteristics for VB1B2 = 4 V.
Therefore,
VR2 = 20 – (4 + 5) = 11 V
11
R2 = ____ × 103 = 44 W
250
So, R2 is selected as 100 W.
A UJT has a firing potential of 20 V. It is connected across the capacitor of a series
circuit with R = 100 kW and C = 1000 pF supplied by a source of 40 V d.c.
Calculate the time period of the sawtooth waveform generated.
Solution
Given, RE = 100 kW and CE = 1000 pF
VBB = 40 V, VP = 20 V
(
–t
_____
VP = VBB 1– e RECE
(
–t
_____
20 = 40 1 – e RECE
)
)
1
e–t/RECE = __
2
–t
1
_____
= ln __
RECE
2
t
_____
= ln (2)
RECE
t = ln (2) × RECE
Therefore, t = 0.693 × 100 × 103 × 1000 × 10 – 12 = 0.693 × 10 – 4 = 69.3 ms
All electronic circuits need dc power supply either from battery or power pack
units. It may not be economical and convenient to depend upon battery power
supply. Hence, many electronic equipment contain circuits which convert the ac
supply voltage into dc voltage at the required level. The unit containing these
circuits is called the Linear Mode Power Supply (LMPS). In the absence of ac
mains supply, the dc supply from battery can be converted into required ac
voltage which may be used by computer and other electronic systems for their
operation. Also, in certain applications, dc to dc conversion is required. Such a
power supply unit that converts dc into ac or dc is called Switched Mode Power
Supply (SMPS).
1. Linear mode power supply (LMPS): ac/dc power supply—Converter
2. Switched mode power supply (SMPS): (i) dc/dc power supply—converter
(ii) dc/ac power supply—Inverter
An ac/dc power supply converts ac mains (230 V, 50 Hz) into required dc voltages and is found in all mains operable systems.
DC/DC power supplies or dc/dc converters are used in portable systems, DC/
AC power supplies or inverter are used in portable main operable system and
as a supplement to ac mains in non-portable mains operable system, where a
disruption in the power supply can affect the job being done by the system.
An inverter is a form of UPS (Uninterrupted Power Supply) or SPS (Standby
Power Supply) and is very popular in computer system.
Based on the regular concept, power supplies are classified as either linear or
switched mode power supply. The main difference between LMPS and SMPS is
seen from their block diagrams given in Figs 3.1(a) and (b).
The basic building blocks of the linear power supply are shown in Fig. 3.2.
A transformer supplies ac voltage at the required level. This bidirectional ac
voltage is converted into a unidirectional pulsating dc using a rectifier. The
unwanted ripple contents of this pulsating dc are removed by a filter to get pure
dc voltage. The output of the filter is fed to a regulator which gives a steady dc
output independent of load variations and input supply fluctuations.
1. The most important consideration in designing a power supply is the dc
voltage at the output. It should be able to give minimum operable dc
voltage at the rated current.
2. It should be able to furnish the maximum current needed for the unit,
maintaining the voltage constant. In other words, the regulation of the
power supply should be good.
3. The ac ripple should be low.
4. The power supply should be protected in the event of short-circuit on the load
side.
5. Over voltage (spike and surges) protection must be incorporated.
6. The response of the power supply to temperature changes should be
minimum.
A PN junction diode is a two terminal device that is polarity sensitive. When the
diode is forward biased, the diode conducts and allows current to flow through
it without any resistance, i.e. the diode is ON. When the diode is reverse biased,
the diode does not conduct and no current flows through it, i.e. the diode is
OFF, or providing a blocking function. Thus an ideal diode acts as a switch,
either open or closed, depending upon the polarity of the voltage placed across
it. The ideal diode has zero resistance under forward bias and infinite resistance
under reverse bias.
Rectifier is defined as an electronic device used for converting a.c. voltage into
unidirectional voltage. A rectifier utilizes unidirectional conduction device like
a vacuum diode or PN junction diode. Rectifiers are classified depending upon
the period of conduction as half-wave rectifier and full-wave rectifier.
It converts an a.c. voltage into a pulsating d.c. voltage using only one half of
the applied a.c. voltage. The rectifying diode conducts during one half of the
a.c. cycle only. Figure 3.3 shows the basic circuit and waveforms of a half-wave
rectifier.
Let Vi be the voltage to the primary of the transformer and given by the
equation
Vi = Vm sin w t; Vm >> Vg
where Vg is the cut-in voltage of the diode. During the positive half cycle of
the input signal, the anode of the diode becomes more positive with respect
to the cathode and hence, diode D conducts. For an ideal diode, the forward
voltage drop is zero. So the whole input voltage will appear across the load
resistance, RL.
During negative half cycle of the input signal, the anode of the diode becomes
negative with respect to the cathode and hence, diode D does not conduct. For
an ideal diode, the impedance offered by the diode is infinity. So the whole input
voltage appears across diode D. Hence, the voltage drop across RL is zero.
The ratio of rms value of a.c. component to the d.c. component in the output is known as ripple factor ( G ).
rms value of a.c. component Vr, rms
G = _________________________ = ______
Vd.c.
d.c. value of component
_________
where
÷
2
Vr, rms = V2rms – Vd.c.
__________
G=
÷( )
Vrms
____
Vd.c.
2
–1
Vav is the average or the d.c. content of the voltage across the load and is given
by
1
Vav = Vd.c. = ___
2p
[
p
2p
Ú Vm sin wtd(wt) + Ú 0.d(wt)
p
0
]
Vm
Vm
= ___ [– cos wt]p0 = ___
p
2p
Vd.c.
Vm
Im
Id.c = ____ = _____ = ___
RL
p RL p
Therefore,
If the values of diode forward resistance (rf ) and the transformer secondary
winding resistance (rs) are also taken into account, then
Vm
Vd.c. = ___
p – Id.c.(rs + rf)
Vd.c.
Vm
Id.c. = ____________ = ______________
(rs + rf) + RL p (rs + rf + RL)
The rms voltage at the load resistance can be calculated as
[
p
1
Vrms = ___ Ú V2m sin2 wtd(wt)
2p 0
= Vm
[
p
1
___
Ú (1 – cos 2 wt) d(wt)
4p 0
___________
Therefore,
G =
÷[
]
1
__
2
V____
m /2
Vm /p
]
2
–1 =
_______
]
1
__
2
Vm
= ___
2
÷( __2 ) – 1 = 1.21
p
2
From this expression, it is clear that the amount of a.c. present in the output is
121% of the d.c. voltage. So the half-wave rectifier is not practically useful in
converting a.c. into d.c.
The ratio of d.c. output power to a.c. input power is known as
rectifier efficiency (h).
d.c. output power
d.c.
h = ________________ = ____
Pa.c.
a.c. input power
(Vd.c.)2
Vm 2
______
___
R
p
L
4
= _______2 = ______2 = __2 = 0.406 = 40.6%
V
(V
)
p
m
___
rms
______
2
RL
( )
( )
The maximum efficiency of a half-wave rectifier is 40.6%.
It is defined as the maximum reverse voltage that
a diode can withstand without destroying the junction. The peak inverse voltage
across a diode is the peak of the negative half cycle. For half-wave rectifier, PIV
is Vm.
In the design of any power supply,
the rating of the transformer should be determined. This can be done with a
knowledge of the d.c. power delivered to the load and the type of rectifying
circuit used.
d.c. power delivered to the load
TUF = __________________________________
a.c. rating of the transformer secondary
Pd.c.
= _________
Pa.c. rated
In the half-wave
rectifying circuit, the rated voltage of the transformer second__
ary is Vm /÷2 , but the actual rms current flowing through the winding is only
__
Im
___
, not Im /÷2 .
2
I 2m
V 2m ___
1
___
___
__
R
2 L
2 R
2÷2
L
p
p
________
_______
____
TUF =
=
= 2 = 0.287
Vm ___
Im ___
Vm ____
Vm
p
___
__ ×
__
2
÷2
÷2 2
The TUF for a half-wave rectifier is 0.287.
rms value
Form factor = ____________
average value
Vm/2
p
= ____ = __ = 1.57
Vm /p 2
peak value
Peak factor = __________
rms value
Vm
= _____ = 2
Vm/2
A half-wave rectifier, having a resistive load of 1000 , rectifies an alternating voltage
of 325 V peak value and the diode has a forward resistance of 100 . Calculate (a)
peak, average and rms value of current (b) d.c. power output (c) a.c. input power,
and (d) efficiency of the rectifier.
Solution
(a) Peak value of current,
Vm
325
Im = _______ = __________ = 295.45 mA
rf + RL 100 + 1000
Average current,
Im ______
295.45
Id.c. = ___
p = p mA = 94.046 mA
RMS value of current,
Im
295.45
Irms = ___ = ______ = 147.725 mA
2
2
(b) The d.c. power output, Pd.c. = I2d.c. × RL
= (94.046 × 10 – 3)2 × 1000 = 8.845 W
(c) The a.c. input power,
Pa.c. = (Irms)2 × (rf + RL)
= (147.725 × 10 – 3)2 (1100) = 24 W
Pd.c. 8.845
(d) Efficiency of rectification, h = ____ = _____ = 36.85%.
Pa.c.
24
A half-wave rectifier is used to supply 24 V d.c. to a resistive load of 500 and the
diode has a forward resistance of 50 . Calculate the maximum value of the a.c.
voltage required at the input.
Solution
Average value of load current,
Vd.c.
24
Id.c. = ____ = _____ = 48 mA
RL
1000
Maximum value of load current, Im= p × Id.c. = p × 48 mA = 150.8 mA
Therefore, maximum a.c. voltage required at the input,
Vm = Im × (rf + RL)
= 150.8 × 10 – 3 × 550 = 82.94 V
An a.c. supply of 230 V is applied to a half-wave rectifier circuit through transformer of turns ratio 5:1. Assume the diode is an ideal one. The load resistance is 300 . Find (a) d.c. output voltage (b) PIV (c) maximum, and
(d) average values of power delivered to the load.
Solution
(a) The transformer secondary voltage
230
= ____ = 46 V
5
__
Maximum value of secondary voltage, Vm = ÷2 × 46 = 65 V
Therefore, d.c. output voltage,
(b) PIV of a diode
Vm ___
65
Vd.c. = ___
p = p = 20.7 V
Vm = 65 V
(c) Maximum value of load current,
Vm
65
Im = ___ = ____ = 0.217 A
RL 300
Therefore, maximum value of power delivered to the load,
Pm = I2m × RL = (0.217)2 × 300 = 14.1 W
Vd.c. 20.7
(d) The average value of load current, Id.c. = ____ = ____ = 0.069 A
RL
300
Therefore, average value of power delivered to the load,
2
Pd.c. = Id.c.
× RL = (0.069)2 × 300 = 1.43 W
An HWR has a load of 3.5 k . If the diode resistance and secondary coil resistance
together have a resistance of 800 and the input voltage has a signal voltage of
peak value 240 V. Calculate
(a)
(b)
(c)
(d)
peak average and rms value of current flowing
d.c. power output
a.c. power input
efficiency of the rectifier
[JNTU May 2003, Dec. 2003]
Solution
Load resistance in an HWR, RL = 3.5 kW
Diode and secondary coil resistance, rf + rs = 800 W
Peak value of input voltage = 240 V
(a) Peak value of current,
Vm
240
Im = __________ = _____ = 55.81 mA
rs + rf + RL 4300
Im ___________
55.81 × 10 – 3
Average value of current, Id.c. = ___
= 17.77 mA
p =
p
Im 55.81 × 10 – 3
The rms value of current, Irms = ___ = ___________ = 27.905 mA
2
2
(b) The d.c. power output is
Pd.c. = (Id.c.)2 RL = (17.77 × 10 – 3)2 × 3500 = 1.105 W
(c) The a.c. power input is
Pa.c. = (Irms)2 × (rf + RL) = (27.905 × 10 – 3)2 × 4300 = 3.348 W
(d) Efficiency of the rectifier is
Pd.c. 1.105
h = ____ = _____ × 100 = 33%
Pa.c. 3.348
An HWR circuit supplies 100 mA d.c. to a 250 load. Find the d.c. output voltage, PIV rating of a diode and the rms voltage for the transformer supplying the
[JNTU May 2008, Jan. 2010]
rectifier.
Solution
Given Id.c. = 100 mA,RL = 250 W
(a) The d.c. output voltage, Vd.c. = Id.c. × RL = 100 × 10 – 3 × 250 = 25 V
(b) The maximum value of secondary voltage,
Vm = p × Vd.c. = p × 25 = 78.54 V
(c) PIV rating of a diode,
Vm = 78.54 V
(d) The rms voltage for the transformer supplying the rectifier
Vm 78.54
Vrms = ___ = _____ = 39.27 V
2
2
A voltage of 200 cos t is applied to HWR with load resistance of 5 k . Find
the maximum d.c. current component, rms current, ripple factor, TUF and rectifier
efficiency.
[JNTU May 2008, Jan 2010]
Solution
Given applied voltage = 200 cosw t, Vm = 200 V, RL = 5 kW
(a) To find d.c. current:
Vm
200
Im = ___ = _______3 = 40 mA
RL 5 × 10
Therefore,
Im _________
40 × 10 – 3
Id.c. = ___
=
= 12.73 mA
p
p
(b) To find rms current:
Im 40 × 10 – 3
Irms = ___ = _________ = 20 mA
2
2
__________
G=
(c) Ripple factor:
(d) To determine TUF:
÷( )
Irms
____
Id.c.
2
–1=
_________________
÷(
20 × 10 – 3
___________
12.73 × 10 – 3
2
)
–1 = 1.21
Pd.c.
TUF = ________
Pa.c. (rated)
Pd.c. = I 2d.c.RL = (12.73 × 10 – 3)2 × 5 × 103 = 0.81 W
Vm ___
Im ____
200 40 × 10 – 3
__ ×
Pa.c. (rated) = ___
= __ × _________ = 2.828
2
2
÷2
÷2
Therefore,
Pd.c.
0.81
TUF = ________ = _____ = 0.2863
Pa.c. (rated) 2.828
(e) Rectifier efficiency:
Pd.c.
h = ____
Pa.c.
Pd.c. = 0.81 W
2
Pa.c. = Irms
RL = (20 × 10 – 3)2 × 5 × 103 = 2 W
Therefore,
Pd.c.
0.81
h = ____ × 100 = ____ × 100 = 40.5%
Pa.c.
2
A diode has an internal resistance of 20 and 1000 load from a 110 V rms source
of supply. Calculate (i) the efficiency of rectification and (ii) the percentage regula[JNTU May 2006, Aug. 2008]
tion from no load to full load.
Solution
Given rf = 20 W, RL = 1000 W and Vrms (secondary) = 110 V
The half-wave rectifier uses a single diode.
__
Therefore,
Vm = ÷2 Vrms (secondary) = 155.56 V
Vm
155.56
Im = _______ = _________ = 0.1525 A
rf + RL 20 + 1000
Im ______
0.1525
Id.c. = ___
p = p = 0.04854 A
Vd.c. = Id.c.RL = 0.04854 × 1000 = 48.54 V
Pd.c. = Vd.c.Id.c. = 48.54 × 0.04854 = 2.36 W
2
( ) (r + R ) ( since I
Im
2
Pa.c. = Irms
(rf + RL) = ___
2
(
0.1525
= ______
2
Efficiency,
f
L
rms
Im
= ___ for half-wave
2
2
) (20 + 1000) = 5.93 W
Pd.c.
2.36
h = ____ × 100 = ____ × 100 = 39.7346%
Pa.c.
5.93
Vm
___
V
–
V
p –Vd.c.
NL
FL
Percentage of line regulation = _________ × 100 = ________ × 100
VFL
Vd.c.
155.56
______
p – 48.54
_____________
=
× 100 = 2%
48.54
Show that maximum d.c. output power Pd.c. = Vd.c. × Id.c. in a half-wave single phase
circuit occurs when the load resistance equals diode resistance rf .
[JNTU Dec. 2004]
Solution
For a half-wave rectifier,
Vm
Im = _______
rf + RL
Im _________
Vm
Id.c. = ___
p = p(rf + RL)
and
Vd.c. = Id.c. × RL
Therefore,
V2mRL
2
Pd.c. = Vd.c. × Id.c. = Id.c.
RL = __________
p2(rf + RL)2
For this power to be maximum,
dPd.c.
_____
dRL
=0
] [
]
(rf + RL)2 – RL × 2 (rf + RL)
V2mRL
V2m ________________________
d __________
____
___
=
=0
dRL p2(rf + RL)2
p2
(rf + RL)4
[
(rf + RL)2 – 2RL(rf + RL) = 0
r2f + 2rf RL + R2L – 2rf RL – 2R2L = 0
)
r2f – R2L = 0
R2L = r2f
Thus, the power output is maximum if RL = rf
The transformer of a half-wave rectifier has a secondary voltage of 30 Vrms with a
winding resistance of 10 . The semiconductor diode in the circuit has a forward
resistance of 100 . Calculate (a) No load d.c. voltage, (b) d.c. output voltage at
IL = 25 mA, (c) % regulation at IL = 25 mA, (d) ripple voltage across the load,
(e) ripple frequency, (f ) ripple factor, (g) d.c. power output, and (h) PIV of the semi[JNTU Aug. 2008]
conductor diode.
Solution
Vrms (secondary) = 30 V, rs = 10 W, rf = 100 W
__
__
Vm = ÷2 × Vrms = ÷2 × 30 = 42.4264 V
Vm _______
42.4264
Vd.c. = ___
= 13.5047 V
p =
p
(a)
(b)
IL = Id.c. = 25 mA
Here
Therefore,
Im
Vm
______________
Vd.c. = Id.c.RL = ___
p RL = p (rf + rs + RL) × RL
Vd.c.
RL = ____
Id.c.
Vd.c.
Vm
Vd.c. = _______________ × ____
Id.c.
Vd.c.
p rf + rs + ____
Id.c.
(
)
42.426Vd.c.
1
Vd.c. = ______________________ × _________
Vd.c.
25 × 10 – 3
p 100 + 10 + _________
25 × 10 – 3
(
)
Vd.c. (110 + 40Vd.c.) = 540.1897 Vd.c.
540.1897 – 110
Vd.c. = _____________ = 10.7547 V
40
Vd.c. (NL) –Vd.c. (FL)
(c) Percentage of regulation = _______________ × 100
Vd.c. (FL)
13.5047 – 10.7547
= ________________ × 100 = 25.569%
10.7547
Vd.c.
Vm
10.7547
(d) Im = __________, where RL = ____ = _________
= 430.188 V
rf + rs + RL
Id.c. 25 × 10 – 3
Therefore,
42.4264
Im = _________________ = 0.07854 A
100 + 10 + 430.188
Im
Irms = ___ = 0.03927 A
2
_________
G=
Ripple voltage
÷( )
Irms
____
Id.c.
2
______________
0.03927
–1 = 1.21
(÷ _________
25 × 10 )
2
–1 =
–3
G × Vd.c. = 1.21 × 10.7547 = 13.02791 V
(e) Ripple frequency, f = 50Hz
(f) G = ripple factor = 1.21
(g) Pd.c.= Vd.c.Id.c. = 10.7547 × 25 × 10 – 3 = 0.2688 W
(h) PIV = Vm = 42.4264 V
It converts an a.c. voltage into a pulsating d.c. voltage using both half cycles of
the applied a.c. voltage. It uses two diodes of which one diode conducts during
one half-cycle while the other diode conducts during the other half-cycle of the
applied a.c. voltage. There are two types of full-wave rectifiers, viz (i) full-wave
rectifier with center tapped transformer, and (ii) full-wave rectifier without
transformer (bridge rectifier).
Figure 3.4 shows the basic circuit and waveforms of full-wave rectifier with a
center tap transformer. During positive half of the input signal, anode of diode
D1 becomes positive and at the same time the anode of diode D2 becomes
negative. Hence, D1 conducts and D2 does not conduct. The load current flows
through D1 and the voltage drop across RL will be equal to the input voltage.
During the negative half-cycle of the input, the anode of D1 becomes negative
and the anode of D2 becomes positive. Hence, D1 does not conduct and D2 conducts. The load current flows through D2 and the voltage drop across RL will be
equal to the input voltage.
___________
÷( )
Vrms
____
Vd.c.
G=
2
–1
The average voltage or d.c. voltage available across the load resistance is
p
1
Vd.c. = __
p Ú Vm sin wt d(wt)
0
Vm
2Vm
____
p
= ___
p [– cos wt]0 = p
Vd.c. 2Vm 2Im
Im
__
Id.c. = ____ = ____ = ____
and Irms = ___
p
RL
pRL
÷2
If the diode forward resistance (rf ) and the transformer secondary winding resistance (rs) are included in the analysis, then
2Vm
Vd.c = ____
p – Id.c. (rs + rf )
Vd.c.
2Vm
Id.c. = ____________ = _____________
(rs + rf) + RL
p(rs + rf + RL)
RMS value of the voltage at the load resistance is
___________________
Vrms =
÷[
÷(
]
p
Vm
1
__
___
2
2
__
p Ú Vm sin wt d(wt) = ÷2
0
_____________
__
Therefore,
G =
V
m /÷2
______
2 /p
2
)
______
÷
p2
– 1 = __ – 1 = 0.482
8
The ratio of d.c. output power to a.c. input power is known as
rectifier efficiency (h).
d.c. output power Pd.c.
h = ________________ = ____
Pa.c.
a.c. input power
[ ]
2Vm 2
____
2
(V
)
/R
p
8
d.c.
L
= _________
= _______
= ___2 = 0.812 = 81.2%
2
V
(Vrms)2/RL
p
m
___
__
÷2
[ ]
The maximum efficiency of a full-wave rectifier is 81.2%.
The average TUF in a full-wave rectifying circuit is determined by considering the primary and secondary windings
separately and it gives a value of 0.693.
rms value of the output voltage
Form factor = ______________________________
average value of the output voltage
__
Vm /÷2
p__
= ______ = ____
= 1.11
2Vm /p 2÷2
__
Vm
peak value of the output voltage
__ = ÷2
Peak factor = ____________________________ = ______
rms value of the output voltage Vm /÷2
Peak inverse voltage for full-wave rectifier is 2Vm because the entire secondary
voltage appears across the non-conducting diode.
A 230 V, 60 Hz voltage is applied to the primary of a 5:1 step-down, center-tap
transformer use in a full wave rectifier having a load of 900 . If the diode resistance
and secondary coil resistance together has a resistance of 100 , determine (a) d.c.
voltage across the load, (b) d.c. current flowing through the load, (c) d.c. power
delivered to the load, (d) PIV across each diode, (e) ripple voltage and its frequency,
and (f) rectification efficiency.
[JNTU May 2003, 2004, May 2007, June 2009]
Solution
230
The voltage across the two ends of secondary = ____ = 46 V
5
46
Voltage from center tapping to one end, Vrms = ___ = 23 V
2
__
2Vm ___________
2 × 23 × ÷2
(a) The d.c. voltage across the load, Vd.c.= ____
= 20.7 V
p =
p
Vd.c.
20.7
(b) The d.c. current flowing through the load, Id.c. = ___________ = _____
(rs + rf +RL) 1000
= 20.7 mA
2
(c) The d.c. power delivered to the load, Pd.c = (Id.c.) × RL = (20.7 × 10 – 3)2 ×
900 = 0.386 W
__
(d) PIV across each diode = 2Vm = 2 × 23 × ÷2 = 65 V
_____________
(e) Ripple voltage,
Vr, rms = ÷(Vrms)2 – (Vd.c.)2
____________
= ÷(23)2 – (20.7)2 = 10.05 V
Frequency of ripple voltage = 2 × 60 = 120 Hz
(f) Rectification efficiency,
2
Pd.c.
(Vd.c.)2/RL
(V
d.c.)
______
h = ___ = _________
=
Pa.c.
(Vrms)2/RL
(Vrms)2
(20.7)2 ______
428.49
______
=
=
= 0.81
2
529
(23)
Therefore, percentage of rectification efficiency = 81%
A full-wave rectifier has a centre-tap transformer of 100-0-100 V and each one of
the diodes is rated at Imax = 400 mA and Iav = 150 mA. Neglecting the voltage drop
across the diodes, determine (a) the value of load resistor that gives the largest d.c.
power output, (b) d.c. load voltage and current, and (c) PIV of each diode.
Solution
(a) We know that the maximum value of current flowing through the diode for
normal operation should not exceed 80% of its rated current.
Therefore,
Imax = 0.8 × 400 = 320 mA
The maximum value of the secondary voltage,
__
Vm = ÷2 ×100 = 141.4 V
Therefore, the value of load resistor that gives the largest d.c. power
output
Vm
141.4
RL = ____ = __________
= 442 W
Imax 320 × 10 – 3
2Vm _________
2 × 141.4
(b) The d.c. (load) voltage, Vd.c. = ____
= 90 V
p =
p
V____
90
d.c.
The d.c. load current, Id.c. =
= ____ = 0.204 A
442
(c) PIV of each diode
= 2Vm = 2 × 141.4 = 282.8 V
A full-wave rectifier delivers 50 W to a load of 200
calculate the a.c. ripple voltage across the load.
Solution
The d.c. power delivered to the load,
Pd.c.
V 2d.c.
_____
=
RL
_________
________
Vd.c. = ÷Pd.c. × RL = ÷50 × 200 = 100 V
Therefore,
The ripple factor,
i.e.
. If the ripple factor is 1%,
Va.c.
G = ____
Vd.c.
Va.c.
0.01 = ____
100
Therefore, the a.c. ripple voltage across the load, Va.c. = 1 V
In a full-wave rectifier, the transformer rms secondary voltage from center tap to
each end of the secondary is 50 V. The load resistance is 900 . If the diode resistance and transformer secondary winding resistance together has a resistance of
100 , determine the average load current and rms value of load current?
[JNTU Jan. 2010]
Solution
Voltage from centre tapping to one end, Vrms = 50 V
__
Vm
Vrms × ÷2
70.7
Maximum load current, Im = __________ = __________ = _____ = 70.7 mA
rs + rf + RL rs + rf + RL 1000
2Im ______________
2 × 70.7 × 10 – 3
Average load current, Id.c. = ____
= 45 mA
p =
p
Im __________
70.7 ×__10 – 3
__ =
RMS value of load current, Irms = ___
= 50 mA
÷2
÷2
A full-wave rectifier circuit uses two silicon diodes with a forward resistance of
20 each. A d.c. voltmeter connected across the load of 1 k reads 55.4 Volts.
Calculate
(a) Irms
(b) average voltage across each diode
(c) ripple factor and
(d) transformer secondary voltage rating.
[JNTU May 2007]
So lution
Given
Vd.c. = 55.4 V and RL = 1 kW
(a)
Vd.c.
55.4
Id.c. = ________ = _________ = 54.31 mA
(rf + RL) 20 + 1000
We know that
2Im
Im
___
__
Id.c. = ____
p and Irms = ÷2
p
p
Im = Id.c. × __ = 54.31 × 10 – 3 × __ = 85.31 mA
2
2
Im ___________
85.31 ×
10 – 3
__ =
__
Irms = ___
= 60.32 mA
÷2
÷2
(b) The average voltage across each silicon diode will be 0.72 V.
(c) To find ripple factor G
_________
G=
÷( )
÷(
Irms
____
Id.c.
2
–1
_________________
=
60.32 × 10 – 3
___________
54.31 × 10 – 3
2
)
–1 = 0.4833
To find transformer secondary voltage rating
We know that,
2Vm
Vd.c. = ____
p –Id.c. (rs + rf)
where rf is the diode forward resistance and rs is the transformer secondary
winding resistance.
2Vm
2Vm
____
–3
55.4 = ____
–
54.31
×
10
×
20
=
p
p – 1.086
2Vm
56.49 = ____
p
Therefore,
p
Vm = 56.49 × __ = 88.73 V
2
Vm _____
88.73
__ =
__ = 62.74 V
Vrms = ___
÷2
÷2
Hence, transformer secondary voltage rating is 65 V – 0 = 65 V.
Determine (a) dc output voltage (b) PIV and (c) rectification efficiency for the
circuit shown in Fig. 3.5.
[JNTU May 2008, Aug 2008 and June 2009]
Solution
Vrms (primary) = 230 V, N1 : N2 = 5 : 1, RL = 100 W
Vrms (primary) = R.M.S. voltage from either end of secondary to center tap
Vrms (primary)
N1
________________
= ___
2Vrms (secondary) N2
230
Vrms (secondary) = _____ = 23 V
5×2
__
__
Vm = ÷2 Vrms (secondary) = ÷2 × 23 = 32.53 V
Vm
32.53
Im = ___________ = _____ + 0 + 0 = 0.3253 A
RL + rS + rf
100
2Im __________
2 × 0.3253
Idc = ____
= 0.2071 A
p =
p
(a) Vdc = Idc RL = 0.2071 × 100 = 20.71 V
(b) PIV = 2Vm = 2 × 32.53 = 65.06 V
(c) Pdc = I 2dc RL = (0.2071)2 × 100 = 4.289 W
Pdc
4.289
Therefore, percentage of efficiency, h = ___ × 100 = _____ × 100 = 81.07%
Pac
5.29
Draw the circuit diagram of a full-wave rectifier using center tapped transformer
to obtain an output d.c. voltage of Vdc = 18 V at 200 mA and Vdc no load equals
to 20 V. Assume suitable value of rf and transformer resistance and also mention
transformer rating and sketch the input and output waveforms. [JNTU Dec. 2004]
Solution
The circuit diagram of a full-wave rectifier using centre tapped
transformer is shown in Fig. 3.6(a).
A
D1
iL
id1
+
Vdc
RL
–
A.C. Supply
id2
B
Given
D2
Vdc = 18 V, Idc = 200 mA and Vdc (NL) = 20 V
Vdc (FL) = Idc RL
18 = 200 × 10– 3 RL
Therefore,
Assume
Now
Therefore,
RL = 90 W
rf = 2W and rs = 8W
p
p
Vm = __ × Vdc (NL) = __ × 20 = 31.42 V
2
2
Vm _____
31.42
__ =
__ = 22.21 V
Vrms = ___
÷2
÷2
Hence, the transformer secondary voltage rating = 22.21 – 0 = 22.21 V
Vm
31.42
Im = __________ = _________ = 0.3142 V
rs + rf + RL 8 + 2 + 90
Im ______
0.3142
__ =
__ = 0.2221 A
Irms = ___
÷2
÷2
VA rating of transformer = Irms Vrms = 22.21 × 0.2221 = 4.93 VA
The waveforms are as shown in Fig. 3.6(b).
S
In a full wave rectifier, the required dc voltage is 9 V and the diode drop is 0.8 V.
Calculate ac rms input voltage required in case of bridge rectifier circuit and center
tapped full wave rectifier circuit.
[JNTU May 2004, Aug 2008]
Solution
The dc voltage across the load of the full wave rectifier circuit,
__
2÷2 × Vrms
2Vm
__________
Vdc = ____
– 0.8
p – 0.8 =
p
where Vrms is the rms input voltage from center tapping to one end. That is,
__
2÷2 Vrms
9.8 = ________
p
Therefore,
9.8p
__ = 10.885 V.
Vrms = ____
2÷2
Hence, the voltage across the two ends of the secondary = 2 × 10.885
= 21.77 V
__
2÷2 Vrms
In the bridge rectifier, Vdc = 9 = ________
– 2 × 0.8
p
10.6p
__ = 11.77V.
Therefore, the voltage across two ends of secondary, Vrms = _____
2÷2
The need for a centre-tapped transformer in a full-wave rectifier is eliminated
in the bridge rectifier. As shown in Fig. 3.7, the bridge rectifier has four diodes
connected to form a bridge. The a.c. input voltage is applied to the diagonally
opposite ends of the bridge. The load resistance is connected between the other
two ends of the bridge.
Vin
Vm
D4
D1
2p
p
a.c
V
input in
wt
–Vm
D3
D2
RL
Vo
Vo
Vm
0
(a)
2p
p
wt
(b)
For the positive half-cycle of the input a.c. voltage, diodes D1 and D3 conduct,
whereas diodes D2 and D4 do not conduct. The conducting diodes will be in
series through the load resistance RL. So the load current flows through RL.
During the negative half-cycle of the input a.c. voltage, diodes D2 and D4 conduct, whereas diodes D1 and D3 do not conduct. The conducting diode D2 and
D4 will be in series through the load RL and the current flows through RL in the
same direction as in the previous half-cycle. Thus a bidirectional wave is converted into an unidirectional one.
The average values of output voltage and load current for bridge rectifier are the
same as for a center-tapped full-wave rectifier. Hence,
2Vm
Vd.c. = ____
p
Vd.c. 2Vm 2Im
and Id.c. = ____ = _____ = ____
p
RL
p RL
If the values of the transformer secondary winding resistance (rs) and diode
forward resistance (rf) are considered in the analysis, then
2Vm
Vd.c. = ____
p – Id.c. (rs + rf )
2Im _____________
2Vm
Id.c. = ____
p = p(rs + rf + RL)
The maximum efficiency of a bridge rectifier is 81.2% and the ripple factor is
0.48. The PIV is Vm.
In the bridge rectifier, the ripple factor
and efficiency of the rectification are the same as for the full-wave rectifier. The
PIV across either of the non-conducting diodes is equal to the peak value of the
transformer secondary voltage, Vm. The bulky center tapped transformer is not
required. Transformer utilisation factor is considerably high. Since the current
flowing in the transformer secondary is purely alternating, the TUF increases
to 0.812, which is the main reason for the popularity of a bridge rectifier. The
bridge rectifiers are used in applications allowing floating output terminals, i.e.
no output terminal is grounded.
The bridge rectifier has only one disadvantage that it requires four diodes as
compared to two diodes for centre-tapped full-wave rectifier. But the diodes are
readily available at cheaper rate in the market. Apart from this, the PIV rating
required for the diodes in a bridge rectifier is only half of that for a centre tapped
full-wave rectifier. This is a great advantage, which offsets the disadvantage of
using extra two diodes in a bridge rectifier.
The comparison of rectifiers is given in Table 3.1.
Particulars
Type of rectifier
Half-wave
Full-wave
Bridge
1
2
4
Maximum efficiency
40.6%
81.2%
81.2%
Vd.c. (no load)
Vm/p
2Vm/p
2Vm/p
Average current/diode
Id.c.
Id.c./2
Id.c./2
Ripple factor
1.21
0.48
0.48
Peak inverse voltage
Vm
2Vm
Vm
f
2f
2f
Transformer utilisation factor
0.287
0.693
0.812
Form factor
1.57
1.11
1.11
No. of diodes
Output frequency
__
Peak factor
2
÷2
__
÷2
A 230 V, 50 Hz voltage is applied to the primary of a 4:1 step-down transformer
used in a bridge rectifier having a load resistance of 600 . Assuming the diodes to
be ideal, determine (a) d.c. output voltage, (b) d.c. power delivered to the load, (c)
PIV, and (d) output frequency.
Solution
(a) The rms value of the transformer secondary voltage,
Vrms(primary) 230
Vrms (secondary) = ____________ = ____ = 57.5 V
4
Turros ratio
The maximum value of the secondary voltage
__
Vm = ÷2 × 57.5 = 81.3 V
Therefore, d.c. output voltage,
2Vm ________
2 × 81.3
Vd.c. = ____
= 52 V
p =
p
(b) The d.c. power delivered to the load,
Pd.c.
V2d.c.
522
____
=
= _____ = 2.704 W
RL
1000
(c) PIV across each diode
= Vm = 81.3 V
(d) Output frequency
= 2 × 50 = 100 Hz
In a bridge rectifier, the transformer is connected to 200 V, 60 Hz mains and the
turns ratio of the step down transformer is 11:1. Assuming the diode is ideal, find
[JNTU May 2003]
(a) Vd.c. (b) Id.c. and (c) PIV.
Solution Given in a bridge rectifier, input voltage = 200 V, 60 Hz and turns
ratio = 11:1
(a) To find the voltage across load, Vd.c.
2Vm
Vd.c. = ____
p
__
where
Vm = ÷2 Vrms (secondary)
Vrms (primary) 200
Vrms (secondary) = __________ = ____ = 18.18 V
11
Turns ratio
__
Therefore
Hence,
Vm = 18.18 × ÷2 = 25.7 V
2 × 25.7
Vd.c. = ________
= 16.36 V
p
(b) To find Id.c.
Assuming that, RL = 600 W, then
Vd.c. 16.36
Id.c. = ____ = _____ = 27.26 mA
RL
600
(c) To find PIV
PIV = Vm = 25.7 V
A bridge rectifier uses four identical diodes having forward resistance of 5 and
the secondary voltage is 30 V(rms). Determine the d.c. output voltage for Id.c. = 200
mA and value of the output ripple voltage.
[JNTU May 2004, June 2009]
Given transformer secondary resistance = 5 W
Solution
Secondary voltage
Vrms = 30 V, Id.c. = 200 mA
Since only two diodes of the bridge rectifier circuit will conduct during positive of negative half cycle of the input signal, the diode forward resistance,
rf = 2 × 5 W = 10 W
We know that,
__
__
2Vm
Vd.c. = ____
p – Id.c. (rf + rs) where Vm = ÷2 Vrms = ÷2 × 30 V
__
Therefore,
2 × ÷2 × 30
Vd.c. = ___________
– 200 × 10–3 (10 +5) = 24 V
p
rms value of ripple at the output
Ripple factor = ____________________________
average value of output voltage
Therefore,
rms value of ripple at the output
0.48 = ____________________________
24
Hence, rms value of ripple at the output = 0.48 × 24 = 11.52 V
In a full wave rectifier, the required d.c. voltage is 9 V and the diode drop is 0.8 V.
Calculate a.c. rms input voltage required in center tapped full wave rectifier and
bridge rectifier circuits.
Solution
(a) The d.c. voltage across the load of the center tapped full wave
rectifier circuit,
__
Vd.c.
2 ÷2 × Vrms
2Vm
__________
= 9 = ____
–
0.8
=
– 0.8
p
p
where Vrms is the rms input voltage from center tapping to on end. That is,
__
2 ÷2 Vrms
9.8 = ________
p
Therefore,
9.8p
__ = 10.885 V
Vrms = ____
2 ÷2
Hence, the voltage across the two ends of the secondary = 2 × 10.885
= 21.77 V
__
2 ÷2 Vrms
________
(b) In the bridge rectifier,Vd.c. = 9 =
– 2 × 0.8
p
10.6p
__ = 11.77 V.
Therefore, the voltage across two ends of secondary, Vrms = _____
2 ÷2
The term harmonic is defined as “a sinusoidal component of a periodic waveform or quantity possessing a frequency, which is an integral multiple of the
fundamental frequency.” By definition, a perfect sine wave has no harmonics, except fundamental component at one frequency. Harmonics are present
in waveforms that are not perfect sine waves due to distortion from nonlinear
loads. The French mathematician named Fourier discovered that a distorted
waveform can be represented as a series of sine waves, with each being an integer
multiple of the fundamental frequency and each with a specific magnitude.
That is, the harmonic frequencies are integer multiples [2, 3, 4,….] of the fundamental frequency. For example, the second harmonic on a 50 Hz system is
2 × 50 or 100 Hz. The sixth harmonic in a 50 Hz system, or the fifth harmonic
in a 60 Hz system is 300 Hz. There are a number of different types of equipment
that may experience faulty operations or failures due to high harmonic voltage
and/ or current levels. The amount of the harmonic voltage and current levels
that a system can tolerate is dependent on the equipment and the source.
The sum of the fundamental and all the harmonics is called the Fourier series.
This series can be viewed as a spectrum analysis where the fundamental frequency and the harmonic component are identified.
The result of such an analysis for the current waveform of a half-wave rectifier
circuit using a single diode is given by
[
cos kwt
1 __
1
2
S
__
____________
i = Im __
p + 2 sinwt – p k = 2,4,6 (k +1) (k – 1)
]
The angular frequency of the power supply is the lowest angular frequency present in the above expression. All the other terms are the even harmonics of the
power frequency.
The full-wave rectifier consists of two half-wave rectifier circuits, arranged in
such a way that one circuit conducts during one half cycle and the second circuit
operates during the second half cycle. Therefore, the currents are functionally
related by the expression i1 (a) = i2 (a + p). Thus, the total current of the fullwave rectifier is i = i1 + i2 as expressed by
cos k wt
2 __
4 ________
S
____________
i = Im __
p – p k = even (k +1) (k – 1)
kπ0
From the above equation, it can be seen that the fundamental angular frequency
is eliminated and the lowest frequency is the second harmonic term 2w. This
is the advantage that the full-wave rectifier presents in filtering of the output.
Additionally, the current pulses in the two halves of the transformer winding
are in such directions that the magnetic cycles formed through the iron core is
essentially that of the alternating current. This avoids any d.c. saturation of the
transformer core that could give rise to additional harmonics at the output.
[
]
The output of a rectifier contains d.c. component as well as a.c. component.
Filters are used to minimise the undesirable a.c., i.e. ripple leaving only the d.c.
component to appear at the output.
The ripple in the rectified wave being very high, the factor being 48% in the fullwave rectifier; majority of the applications which cannot tolerate this, will need
an output which has been further processed.
Figure 3.8 shows the concept of a filter, where the full-wave rectified output
voltage is applied at its input. The output of a filter is not exactly a constant d.c.
level. But it also contains a small amount of a.c. component. Some important
filters are:
(i) Inductor filter
(ii) Capacitor filter
(iii) LC or L-section filter
(iv) CLC or p-type filter
Figure 3.9 shows the inductor filter. When the output of the rectifier passes
through an inductor, it blocks the a.c. component and allows only the d.c.
component to reach the load.
The ripple factor of the Inductor filter is given by
RL
__
G = _______
3÷2 wL
L
Vin
RL
Vo
It shows that the ripple factor will decrease when L is increased and RL is
decreased. Clearly, the inductor filter is more effective only when the load current is high (small RL). The larger value of the inductor can reduce the ripple
and at the same time the output d.c. voltage will be lowered as the inductor has
a higher d.c. resistance.
The operation of the inductor filter depends on its well known fundamental
property to oppose any change of current passing through it.
To analyse this filter for a full-wave, the Fourier series can be written as
2Vm 4V
m __
1
1
1
____
___
___
...
Vo = ____
p – p 3 cos 2 w t + 15 cos 4w t + 35 cos 6 w t +
2Vm
The d.c. component is ____
p .
[
]
Assuming the third and higher terms contribute little output, the output voltage
is
2Vm 4Vm
Vo = ____ – ____ cos 2 wt
2p
3p
The diode, choke and transformer resistances can be neglected since they are very
Vm
small as compared with RL. Therefore, the d.c. component of current Im = ___.
RL
The impedance of series combination of L and RL at 2w is
__________
___________
Z = ÷R2L + (2 wL)2 = ÷R2L + 4w2 L2
Therefore, for the a.c. component,
Vm
___________
Im = ____________
÷R2L + 4w2 2
Therefore, the resulting current i is given by,
2Vm 4Vm cos (2wt – j)
___________
i = _____ – ____ ____________
p RL
3p R2 + 4w2 L2
÷ L
( )
2wL
where j = tan–1 ____ .
The ripple factor, which can be defined as the ratio of the rms value of the ripple
to the d.c. value of the wave, is
4Vm
_________________
__ ___________
3p÷2 ÷R2L + 4w2 L2
2__ ___________
1
_________________
G=
= ____
◊ __________
2V
3÷2
m
4w2 L2
_____
______
1
+
p RL
R2L
2 2
4w
L
If ______
>> 1, then a simplified expression for G is
R2L
÷
RL
__
G = _______
3÷2 wL
In case the load resistance is infinity, i.e. the output is an open circuit, then the
ripple factor is
2__
G = ____
= 0.471
3÷2
This is slightly less than the value of 0.482. The difference being attributable to
the omission of higher harmonics as mentioned. It is clear that the inductor filter
should only be used where RL is consistently small.
Calculate the value of inductance to use in the inductor filter connected to a fullwave rectifier operating at 60 Hz to provide a d.c. output with 4% ripple for a 100
load.
Solution
Therefore,
RL
__
We know that the ripple factor for inductor filter is G = _______
3÷2 wL
0.0625
100
__
0.04 = ________________
= ______
L
3÷2 (2p × 60 × L)
0.0625
L = ______ = 1.5625 H
0.04
An inexpensive filter for light loads is found in the capacitor filter which is
connected directly across the load, as shown in Fig. 3.10(a). The property of a
capacitor is that it allows a.c. component and blocks the d.c. component. The
operation of a capacitor filter is to short the ripple to ground but leave the d.c. to
appear at the output when it is connected across a pulsating d.c. voltage.
During the positive half-cycle, the capacitor charges up to the peak value of the
transformer secondary voltage, Vm, and will try to maintain this value as the fullwave input drops to zero. The capacitor will discharge through RL slowly until
the transformer secondary voltage again increases to a value greater than the
capacitor voltage (equal to the load voltage). The diode conducts for a period
which depends on the capacitor voltage. The diode will conduct when the transformer secondary voltage becomes more than the ‘cut-in’ voltage of the diode.
The diode stops conducting when the transformer voltage becomes less than the
diode voltage. This is called cut-out voltage.
Referring to Fig. 3.10(b) with slight approximation, the ripple voltage waveform
can be assumed as triangular. From the cut-in point to the cut-out point, whatever charge the capacitor acquires is equal to the charge the capacitor has lost
during the period of non-conduction, i.e. from cut-out point to the next cut-in
point.
The charge it has acquired
= Vr, p–p × C
The charge it has lost
= Id.c. × T2
Therefore,
= Id.c. × T2
If the value of the capacitor is fairly large, or the value of the load resistance is
very large, then it can be assumed that the time T2 is equal to half the periodic
time of the waveform.
T 1
T2 = __ = __ ,
2 2f
i.e.
then
Id.c.
Vr, p – p = ____
2fC
With the assumptions made above, the ripple waveform will be triangular in
nature and the rms value of the ripple is given by
Vr, p – p
__
Vr, rms = ______
2÷3
Therefore from the above equation, we have
Id.c.
__
Vr, rms = ______
4÷3 fC
Vd.c.
Vd.c.
__
= _________
, since Id.c. = ____
RL
4÷3 fCRL
Therefore, ripple factor
Vr, rms
1
__
G = ______ = _________
Vd.c.
4÷3 fCRL
The ripple may be decreased by increasing C or RL (or both) with a resulting
increase in d.c. output voltage.
2890
If f = 50 Hz, C in mF and RL in W, G = _____.
CRL
Calculate the value of capacitance to use in a capacitor filter connected to a fullwave rectifier operating at a standard aircraft power frequency of 400 Hz, if the
ripple factor is 10% for a load of 500 .
Solution
We know that the ripple factor for capacitor filter is
1
__
G = _________
4÷3 fCRL
Therefore,
0.722 × 10 – 6
1
__
0.01 = ___________________
= ___________
C
4÷3 × 400 × C × 500
0.722 × 10 – 6
C = ___________ = 72.2 mF
0.01
A15-0-15 Volts (rms) ideal transformer is used with a full-wave rectifier circuit with
diodes having forward drop of 1 Volt. The load is a resistance of 100 Ohm and a
capacitor of 10,000 F is used as a filter across the load resistance. Calculate the
d.c. load current and voltage.
[JNTU Dec. 2004, June 2009]
Solution
Given transformer secondary voltage = 15-0-15 V (rms);
Diode forward drop
= 1 V; RL = 100 W; C = 10,000 mF
We know that,
Vr, p – p
Id.c.
Vd.c. = Vm – ______ = Vm – ____
2
4fC
Therefore,
Vd.c.
Vd.c.
Vd.c. = Vm – _______ , since Id.c. = ____
RL
RL 4fC
[
[
]
]
4f RLC
Simplifying, we get Vd.c. = __________ Vm
4f RLC + 1
__
__
Vm = Vrms × ÷2 = 15 × ÷2
We know that
[
]
__
4 × 50 × 100 × 10000 × 10 – 6
Therefore, d.c. = ____________________________
× 15 × ÷2 = 21.105 V
–6
4 × 50 × 100 × 10000 × 10 + 1
Considering the given voltage drop of 1 volt due to diodes,
Vd.c. = 21.105 – 1 = 20.105 V
Vd.c. 20.105
Id.c. = ____ = ______ = 0.20105 A
RL
100
A full-wave rectified voltage of 18 V peak is applied across a 500 F filter capacitor. Calculate the ripple and d.c. voltages if the load takes a current of 100 mA.
[JNTU May 2007]
Solution
Given Vm = 18 V, C = 500 mF and Id.c. = 100 mA
Id.c.
100 × 10 – 3
Vd.c. = Vm – ____ = 18 – __________________
= 17 V
4fC
4 × 50 × 500 × 10 – 6
Id.c.
100 × 10 – 3
__
__
Vr, rms = ______
= ____________________
= 0.577 V
4÷3 fC 4÷3 × 50 × 500 × 10 – 6
Therefore, ripple
Vr, rms 0.577
G = _____ = _____ × 100 = 3.39%
Vd.c.
17
A bridge rectifier with capacitor filter is fed from 220 V to 40 V step-down transformer. If average d.c. current in load is 1 A and capacitor filter of 800 F, calculate the load regulation and ripple factor. Assume power line frequency of 50 Hz.
Neglect diode forward resistance and d.c. resistance of secondary of transformer.
[JNTU Aug. 2008]
Solution
Vrms (secondary) = 40 V, Id.c. = 1A, C = 800 mF and f = 50 Hz
__
__
Vm = ÷2 Vrms = ÷2 × 40 = 56.5685 V
Id.c.
1
Vd.c. (FL) = Vm – ____ = 56.5685 – __________________
= 50.3185 V
4fC
4 × 50 × 800 × 10 – 6
On no load,
Hence,
Id.c. = 0
Vd.c. (NL) = Vm = 56.5685 V
Vd.c. (NL) – Vd.c. (NL)
Therefore, percentage of regulation = ________________ × 100
I d.c. (NL)
56.5685 – 50.3185
= ________________ × 100 = 12.42%
50.1385
Vd.c.
50.1385
RL = ____ = _______ = 50.1385 W
Id.c.
1
1
1
__
__
G = _________
= ______________________________
= 0.0717, i.e. 7.17%
4 ÷3 fCRL 4 ÷3 × 50 × 800 × 10 – 6 × 50.3185
We know that the ripple factor is directly proportional to the load resistance
RL in the inductor filter and inversely proportional to RL in the capacitor filter.
Therefore, if these two filters are combined as LC filter or L-section filter as
shown in Fig. 3.11, the ripple factor will be independent of RL.
If the value of the inductance is increased, it will increase the time of conduction. At some critical value of inductance, one diode, either D1 or D2 in full-wave
rectifier, will always be conducting.
From Fourier series, the output voltage can be expressed as
2Vm 4Vm
Vo = ____ – ____ cos 2 wt
3
The d.c. output voltage,
2Vm
Vd.c. = ____
__
Therefore,
4Vm ___
÷2 Vd.c.
1
__ ◊
= _____
= ___ ◊ ____
3
3 ÷2 XL
Irms
This current flowing through Xc creates the ripple voltage in the output.
__
Therefore,
Vr, rms
XC
÷2
= Irms ◊ XC = ___ ◊ Vd.c. ◊ ___
XL
3
__
Vr, rms ÷2 XC
The ripple factor, G = ______ = ___ ◊ ___
Vd.c.
3 XL
__
÷2
1
1
= ___ ◊ ______
, since XC = ____ and XL = 2wL
3 4w2CL
2wC
1.194
If f = 50 Hz, C is in mF and L is in Henry, ripple factor G = _____ .
LC
It was assumed in the analysis given above that for a critical
value of inductor, either of the diodes is always conducting, i.e. current does not
fall to zero. The incoming current consists of two components:
Vd.c.
(i) Id.c. = ____ and (ii) a sinusoidal varying components with peak value of
4Vm
______
. The negative peak of the a.c. current must always be less than d.c., i.e.,
3 XL
__
Vd.c.
RL
÷2 Irms £ ____.
__
We know that for LC filter,
2Vd.c. Vd.c.
Hence _____ £ ____,
XL
RL
Irms
÷2 Vd.c.
= ___ × ____
XL
3
2
i.e. XL ≥ __ RL
3
RL
i.e., LC = ___, where LC is the critical inductance.
3w
2
It should be noted that the condition XL ≥ __ RL cannot be satisfied for all load
3
requirements. At no load, i.e. when the load resistance is infinity, the value
of the inductance will also tend to be infinity. To overcome this problem, a
bleeder resistor RB, is connected in parallel with the load resistance as shown
in Fig. 3.12. Therefore, a minimum current will always be present for optimum
L
Full-wave
rectified input
Vi
C
RB
RL
operation of the inductor. It improves voltage regulation of the supply by acting
as the pre-load on the supply. Also, it provides safety by acting as a discharging
path for capacitor.
Design a filter for full-wave circuit with LC filter to provide an output voltage of 10
V with a load current of 200 mA and the ripple is limited to 2%.
Solution
10
The effective load resistance RL = __________
= 50 W
200 × 10 – 3
1.194
We know that the ripple factor, G = _____
LC
1.194
0.02 = _____
LC
i.e.
1.194
LC = _____ = 59.7
0.02
i.e.
50
Critical value of L = ___ = _______ = 53 mH
3w 3 × 2 f
Taking L = 60 mH (about 20% higher), C will be about 1000 mF.
A full wave rectifier (FWR) supplies a load requiring 300 V at 200 mA. Calculate
the transformer secondary voltage for (a) a capacitor input filter using a capacitor
of 10 mF, and (b) a choke input filter using a choke of 10 H and a capacitance of 10
F. Neglect the resistance of choke.
[JNTU May & Sept. 2006, Feb. 2010]
Solution
Given
Vd.c. = 300 V; Id.c. = 200 mA
(a) For the capacitor filter with C = 10 mF,
Id.c.
Vd.c. = Vm – ____
4fC
200 × 10–3
300 = Vm – _______________
= Vm – 100
4(50) (10 × 10–6)
Therefore,
Vm = 400 V(p – p)
Vm
__ = 282.84 V
Vrms = ___
÷2
(b) For the choke, i.e., LC filter with L = 10 H; C = 10 mF
2Vm
Vd.c. = ____
p
2Vm
300 = ____
p
Therefore,
Vm = 471.23 V
Vm
__ = 333.21 V
Vrms = ___
÷2
Determine the ripple factor of an L-type choke input filter comprising a 10 H choke
and 8 F capacitor used with an FWR. Compare with a simple 8 F capacitor input
filter at a load current of 50 mA and also at 150 mA. Assume the d.c. voltage of
50V.
[JNTU May 2008, Jan. 2010]
Vd.c. = 50 V, L = 10 H, C = 8 mF
Solution
Assume f = 50 Hz i.e. w = 2p f = 100p rad/s.
For LC filter, the ripple factor is
1
1
__
__
G = _________
= __________________________
= 0.01492, i.e. 1.492%
2
2
6÷2 w LC
6÷2 ×(100p) × 10 × 8 × 10 – 6
For simple capacitor filter, C = 8 mF.
(i) At
IL = 50 mA,
Vd.c.
50
RL = ____ = _________
= 1000 W
IL
50 × 10 – 3
1
1
__
__
G = ________
= _________________________
= 0.3608, i.e. 36.08%
4÷3 fCRL 4 ÷3 × 50 × 8 × 10 – 6 × 1000
(ii) At
IL = 150 mA,
Vd.c.
50
RL = ____ = __________
= 333.33 W
IL
150 × 10 – 3
1
1
__
__
G = ________
= __________________________
= 1.082, i.e. 108.2%
4÷3 fCRL 4÷3 × 50 × 8 × 10 – 6 × 333.33
Thus it is inferred that LC choke input filter is more effective than capacitor
input filter and the ripple factor of LC choke input filter does not depend on the
load resistance.
In a full-wave rectifier using an LC filter L = 10 H, C = 100 F and RL = 500 .
Calculate Id.c.,Vd.c. and ripple factor for an input of Vi = 30 sin (100 t)V.
[JNTU Dec. 2004, Aug. 2008]
Solution
Comparing the input with Vi = Vm sin wt
Vm (secondary) = Vm = 30 V
2Vm ______
2 × 30
Vd.c. = ____
p = p = 19.0985 V
Vd.c. 19.0985
Id.c. = ____ = _______ = 0.03819 A = 38.19 mA
RL
500
1
__
Ripple factor = _________
6÷2 w2LC
1
__
= ____________________________
= 1.194 × 10 – 3
6÷2 × (100p)2 × 10 × 100 × 10 – 6
The filtering level can be improved by using two of more L-section filters in series,
as shown in Fig. 3.13. It is assumed that the reactance of all the inductances are
much larger than the reactance of the capacitors and the reactance of the last capacitor is small compared with the resistance of the load. Under these conditions, the
impedance between 3 and 3¢ is XC2, the impedance between 2 and 2¢ is XC1, and the
impedance between 1 and 1¢ is XL1. The alternating current I1 through L1 is, given by
L1
2
1
L2
3
+
I1
I2
C1
C2
RL
Vo
–
1¢
2¢
3¢
__
I1 =
2 Vd.c. ____
÷______
1
3
XL1
The a.c. voltage across C1 is given by
V22¢ = I1XC1
The alternating current I2 through L2 is given by
V22¢
I2 = ____
XL2
The a.c. voltage across C2 and hence across the load is given by
__
V33¢
XC2XC1 ÷2 Vd.c. XC2 XC1
= I2XC2 = I1 _______ = ______ ____ ____
XL2
XL2 XL1
3
The ripple factor is obtained by dividing the above equation by Vd.c.. Hence,
__
÷2 XC1 XC2
G = ___ ____ ____
3 XL1 XL2
The generalized expression for any number of sections can be obtained by comparing the above equation with that of a single L-section. For example, the ripple factor of a multiple L-section filter (Gn) is given by
__
n
( )
÷2 XC
Gn = ___ ___
3 XL
__
÷2
1
= ___ ___________
3 (16p 2f 2LC)n
where n is the number of similar L-sections.
Figure 3.14 shows the CLC or p-type filter which basically consists of a capacitor
filter followed by an LC section. This filter provided a fairly smooth output, and
is characterized by a highly peaked diode currents and poor regulation.
L1
Full-wave
rectified input
Vi
C1
C2
RL Vo
The action of a p-section filter can best be understood by considering the inductor and the second capacitor as an L-section filter that acts upon the triangular
output-voltage wave from the first capacitor. The output voltage is then approximately that from the input capacitor, decreased by the d.c. voltage drop in the
inductor. The ripple contained in this output is reduced by the L-section filter.
The ripple voltage can be calculated by analyzing the triangular wave into a
Fourier series and then multiplying each component by XC2/XL1 for this harmonic. The Fourier analysis of this waveform is given by
Vr
sin 2w t _______
sin 6wt º
_______
v = Vd.c. – ___
+
–
p sin 2w t –
2
3
(
We know that
Id.c.
Vr = ____
2fC1
The rms second-harmonic voltage is
__
Id.c.
Vr
__ = ÷2 Id.c.XC1
__ = ________
Vrms = V 2¢ = ____
2pfC1÷2
p÷2
)
where XC1 is the reactance of C1 at the second-harmonic frequency.
The voltage V 2¢ is impressed on an L-section, and the output ripple is V 2¢XC2/
XL1.
Hence the ripple factor is
__
__ XC1 X
Vrms
÷2 Id.c.XC1 XC2
C2
G = ____ = _________ ____ = ÷2 ____ ____
Vd.c.
Vd.c.
XL1
RL XL1
where all reactance are calculated at the second-harmonic frequency.
For f = 60 Hz, the above equation reduces to
3,300
G = _________
C1C2L1RL
In order to obtain pure d.c. at the output, more number of p-sections may be
used in series. Such a filter using more than one p-section, as shown in Fig. 3.15,
is called multiple p-section filter.
L1
Full-wave
rectified input
Vi
L2
C1
C2
Section
I
C2
C3
RL Vo
Section
II
The ripple factor for multiple p-section filler is given by
__ XC1 X X
XCn
C2 C3
G = ÷2 ____ ____ ____ º ______
RL XL1 XL2
XL(n – 1)
where n is the number of p-sections.
Design a CLC or -section filter for Vd.c. = 10 V, IL = 200 mA and
Solution
10
RL = __________
= 50 W
200 × 10 – 3
5700
114
0.02 = ___________ = _______
LC1 C2 × 50 LC1 C2
= 2%.
If we assume L = 10 H and C1 = C2 = C, we have
114 11.4
0.02 = ____2 = ____
C2
____
C 2 = 570; therefore, C = ÷570 ª 24 mF
A full-wave single-phase rectifier employs a -section filter consisting of two 4 F
capacitances and a 20 H choke. The transformer voltage to the centre tap is 300 V
rms. The load current is 500 mA. Calculate the d.c. output voltage and the ripple
voltage. The resistance of the choke is 200 .
Solution
C1 = C2 = 4 mF, L = 20 H
Id.c. = 500 mA, Rx = 200 W
Maximum value of secondary voltage,
__
Vs (max) = ÷2 × 300 = 424.2 V
Vd.c.
270.19
RL = ____ = __________
= 540 W
Id.c. 500 × 10 – 3
Vr
Vd.c. = Vs (max) – ___ – Id.c.Rx
2
Ripple voltage,
Id.c.
Vr = ____
2fC
500 × 10 – 3
= ________________
= 1.25 mV
2 × 50 × 4 × 10 – 6
1.25 × 10 – 3
D.C. output voltage, Vd.c. = 424.2 – __________ – (500 × 10–3 × 200)
2
= 324.19 V
Consider the CLC filter with the inductor L replaced by a resistor R. This type
of filter called RC filter is shown in Fig. 3.16. The expression for the ripple factor
can be obtained by replacing XL by R. Then,
__ XC1 XC2
G = ÷2 ____ ◊ ____
RL R
Therefore, if resistor R is chosen equal to the reactance of the inductor which it
replaces, the ripple remains unchanged.
The resistance R will increase the voltage drop and hence, the regulation will
be poor. This type of filters are often used for economic reasons, as well as the
space and weight requirement of the iron-cored choke for the LC filter. Such RC
filters are often used only for low current power supplies.
Table 3.2 shows the comparison of various types of filters, when used with fullwave circuits. In all these filters, the resistances of diodes, transformer and filter
elements are considered negligible and a 60 Hz power line is assumed.
Types of Filter
None
L
C
L-Section
p-Section
Vd.c. at no load
0.636 Vm
0.636 Vm
Vm
Vm
Vm
Vd.c. at load Id.c.
0.636 Vm
0.636 Vm
Ripple factor G
0.48
RL
_______
16000L
2410
_____
CRL
0.83
____
LC
3330
_________
LC1C2RL
Peak inverse
voltage (PIV)
2 Vm
2 Vm
2 Vm
2 Vm
2 Vm
4170Id.c.
Vm – _______ 0.636 Vm
C
4170Id.c.
Vm – _______
C
÷
÷
÷
÷
÷
÷
÷
÷
÷
A Bipolar Junction Transistor (BJT) is a three-terminal semiconductor device
in which the operation depends on the interaction of both majority and minority carriers and hence, the name bipolar. The BJT is analogous to a vacuum
triode and is comparatively smaller in size. It is used in amplifier and oscillator
circuits, and as a switch in digital circuits. It has wide applications in computers, satellites and other modern communication systems. The FET is a device
in which the flow of current through the conducting region is controlled by
an electric field. Hence, the name Field Effect Transistor (FET). As current
conduction is only by majority carriers, the FET is said to be a unipolar device.
The construction, operation, characteristics and applications of both BJTs and
FETs are discussed in this chapter.
The BJT consists of a silicon (or germanium) crystal in which a thin layer of
N-type Silicon is sandwiched between two layers of P-type silicon. This transistor is referred to as PNP. Alternatively, in an NPN transistor, a layer of P-type
material is sandwiched between two layers of N-type material. The two types of
the BJT are represented in Fig. 4.1.
The symbolic representation of the two types of the BJT is shown in Fig. 4.2.
The three portions of the transistor are Emitter, Base and Collector, shown as
E
C
B
(a)
E
C
B
(b)
E, B and C, respectively. The arrow on the emitter specifies the direction of current flow when the EB junction is forward biased.
Emitter is heavily doped so that it can inject a large number of charge carriers
into the base. Base is lightly doped and very thin. It passes most of the injected
charge carriers from the emitter into the collector. Collector is moderately
doped.
As shown in Fig. 4.3, usually the emitter-base junction is forward biased and
collector-base junction is reverse biased. Due to the forward bias on the emitter-base junction an emitter current flows through the base into the collector.
Though the, collector-base junction is reverse biased, almost the entire emitter
current flows through the collector circuit.
As shown in Fig. 4.4, the forward bias applied to the emitter base junction of an
NPN transistor causes a lot of electrons from the emitter region to crossover to
the base region. As the base is lightly doped with P-type impurity, the number
of holes in the base region is very small and hence the number of electrons that
combine with holes in the P-type base region is also very small. Hence a few
electrons combine with holes to constitute a base current IB. The remaining electrons (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the base and collector current summed up gives the emitter
current, i.e. IE = – (IC + IB).
In the external circuit of the NPN bipolar junction transistor, the magnitudes of
the emitter current IE, the base current IB and the collector current IC are related
by IE = IC + IB.
As shown in Fig. 4.5, the forward bias applied to the emitter-base junction of a
PNP transistor causes a lot of holes from the emitter region to crossover to the
base region as the base is lightly doped with N-types impurity. The number of
electrons in the base region is very small and hence the number of holes combined with electrons in the N-type base region is also very small. Hence a few
holes combined with electrons to constitute a base current IB. The remaining
holes (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the collector and base current when summed up gives the
emitter current, i.e. IE = – (IC + IB).
In the external circuit of the PNP bipolar junction transistor, the magnitudes of
the emitter current IE, the base current IB and the collector current IC are related
by
IE = IC + IB
(4.1)
This equation gives the fundamental relationship between the currents in a bipolar transistor circuit. Also, this fundamental equation shows that there are current amplification factors a and b in common base transistor configuration and
common emitter transistor configuration respectively for the static (d.c.) currents, and for small changes in the currents.
The large signal current gain of a common
base transistor is defined as the ratio of the negative of the collector-current
increment to the emitter-current change from cut-off (IE = 0) to IE, i.e.
(IC – ICBO)
a = – __________
(4.2)
IE – 0
where ICBO (or ICO) is the reverse saturation current flowing through the reverse
biased collector-base junction, i.e. the collector to base leakage current with
emitter open. As the magnitude of ICBO is negligible when compared to IE, the
above expression can be written as
IC
a = __
IE
(4.3)
Since IC and IE are flowing in opposite directions, a is always positive. Typical
value of a ranges from 0.90 to 0.995. Also, a is not a constant but varies with
emitter current IE, collector voltage VCB and temperature.
In the active region of the transistor, the emitter is forward biased and the collector is reverse biased. The generalised expression for collector current IC for collector junction voltage VC and emitter current
IE is given by
IC = – a IE + ICBO (1 – eVc/VT)
(4.4)
If VC is negative and |Vc | is very large compared with VT , then the above equation reduces to
IC = – a IE + ICBO
(4.5)
If VC, i.e. VCB, is few volts, IC is independent of VC. Hence the collector current
IC is determined only by the fraction a of the current IE flowing in the emitter.
IC = – a IE + ICBO
Since IC and IE are flowing in opposite directions,
IE = – (IC + IB)
IC = – a [– (IC + IB)] + ICBO
Therefore,
IC – a IC = a IB + ICBO
IC (1– a) = a IB + ICBO
ICBO
a
IC = _____ IB + _____
1–a
1–a
Since
a
b = _____ ,
1–a
(4.6)
the above expression becomes
IC = (1 + b) ICBO + b IB
(4.7)
In the common-emitter (CE) transistor circuit,
IB is the input current and IC is the output current. If the base circuit is open, i.e,
IB = 0, then a small collector current flows from the collector to emitter. This is
denoted as ICEO, the collector-emitter current with base open. This current ICEO
is also called the collector to emitter leakage current.
In this CE configuration of the transistor, the emitter-base junction is forwardbiased and collector-base junction is reverse-biased and hence the collector current IC is the sum of the part of the emitter current IE that reaches the collector,
and the collector-emitter leakage current ICEO. Therefore, the part of IE, which
reaches collector is equal to (IC – ICEO).
Hence, the large-signal current gain (b) is defined as,
(IC – ICEO)
b = __________
IB
(4.8)
IC = bIB + ICEO
(4.9)
From the equation, we have
Comparing Eqs. (4.7) and (4.9), we get the relationship between the leakage
currents of transistor common-base (CB) and common-emitter (CE) configurations as
ICEO = (1 + b) ICBO
(4.10)
From this equation, it is evident that the collector-emitter leakage current (ICEO)
in CE configuration is (1 + b) times larger than that in CB configuration. As
ICBO is temperature-dependent, ICEO varies by large amount when temperature
of the junctions changes.
The magnitude of emitter-current is
IE = IC + IB
Substituting Eqn. (4.7) in the above equation, we get
IE = (1 + b) ICBO + (1 + b) IB
(4.11)
Substituting Eqn. (4.6) into Eqn. (4.11), we have
1
1
IE = _____ ICBO + _____ IB
1–a
1–a
(4.12)
The d.c. current gain is defined as the ratio of
the collector current IC to the base current IB. That is,
IC
bd.c. = hFE = __
IB
(4.13)
As IC is large compared with ICEO, the large signal current gain (b) and the d.c.
current gain (hFE) are approximately equal.
When a transistor is to be connected in a circuit, one terminal is used as an input
terminal, the other terminal is used as an output terminal and the third terminal
is common to the input and output. Depending upon the input, output and common terminal, a transistor can be connected in three configurations. They are:
(i) Common base (CB) configuration, (ii) Common emitter (CE) configuration,
and (iii) Common collector (CC) configuration.
This is also called grounded base configuration. In
this configuration, emitter is the input terminal, collector is the output terminal and base is the common terminal.
This is also called grounded emitter configuration. In
this configuration, base is the input terminal, collector is the output terminal and emitter is the common terminal.
This is also called grounded collector configuration.
In this configuration, base is the input terminal, emitter is the output terminal and collector is the common terminal.
The supply voltage connections for normal operation of an NPN transistor in
the three configurations are shown in Fig. 4.6.
IC
IB
C
B
IE
+
–
E
+
–
E
C
B
–
+
IE
IC
+
–
IB
(a)
(b)
IE
E
IB
B
–
+
C
+
–
IC
(c)
The circuit diagram for determining the static characteristics curves of an NPN
transistor in the common base configuration is shown in Fig. 4.7.
To determine the input characteristics, the collectorbase voltage VCB is kept constant at zero volt and the emitter current IE is
increased from zero in suitable equal steps by increasing VEB. This is repeated
IE
–
–
–
VEE
V
+
A
VEB
+
IC
C
E
+
IC –
A
B
IB
VCB
+
+
V
–
+
V
– cc
for higher fixed values of VCB. A curve is drawn between emitter current IE
and emitter-base voltage VEB at constant collector-base voltage VCB. The input
characteristics thus obtained are shown in Fig. 4.8.
IE (mA)
VCB > 1 V VCB = 0 V
3.5
3
2.5
2
1.5
1
0.5
0.1 0.2 0.3 0.4 0.5 0.6
0.7 0.8 VEB (V)
When VCB is equal to zero and the emitter-base junction is forward biased as
shown in the characteristics, the junction behaves as a forward biased diode
so that emitter current IE increases rapidly with small increase in emitter-base
voltage VEB. When VCB is increased keeping VEB constant, the width of the base
region will decrease. This effect results in an increase of IE. Therefore, the curves
shift towards the left as VCB is increased.
To determine the output characteristics, the emitter
current IE is kept constant at a suitable value by adjusting the emitter-base voltage VEB. Then VCB is increased in suitable equal steps and the collector current
IC is noted for each value of IE. This is repeated for different fixed values of IE.
Now the curves of IC versus VCB are plotted for constant values of IE and the
output characteristics thus obtained is shown in Fig. 4.9.
From the characteristics, it is seen that for a constant value of IE, IC is independent of VCB and the curves are parallel to the axis of VCB. Further, IC flows
even when VCB is equal to zero. As the emitter-base junction is forward biased,
the majority carriers, i.e. electrons, from the emitter are injected into the base
region. Due to the action of the internal potential barrier at the reverse biased
collector-base junction, they flow to the collector region and give rise to IC even
when VCB is equal to zero.
As the collector voltage VCC is made
to increase the reverse bias, the space charge width between collector and base
tends to increase, with the result that the effective width of the base decreases.
This dependency of base-width on collector-to-emitter voltage is known as the
Early effect. This decrease in effective base-width has three consequences:
(i) There is less chance for recombination within the base region. Hence, a
increases with increasing |VCB|.
(ii) The charge gradient is increased within the base, and consequently, the
current of minority carriers injected across the emitter junction increases.
(iii) For extremely large voltages, the effective base-width may be reduced to
zero, causing voltage breakdown in the transistor. This phenomenon is
called the punch through.
For higher values of VCB, due to Early effect, the value of a increases. For example, a changes, say from 0.98 to 0.985. Hence, there is a very small positive slope
in the CB output characteristics and hence the output resistance is not zero.
The slope of the CB characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly
known as common base hybrid parameters or h-parameters.
It is defined as the ratio of the change in (input) emitter voltage to the change in (input) emitter current with the (output) collector
voltage VCB kept constant. Therefore,
DVEB
hib = _____, VCB constant
DIE
(4.14)
It is the slope of CB input characteristics IE versus VEB as shown in Fig. 6.8. The
typical value of hib ranges from 20 W to 50 W.
collector current to the corresponding change in the (output) collector voltage
with the (input) emitter current IE kept constant. Therefore,
DIC
hob = _____, IE constant
(4.15)
DVCB
It is the slope of CB output characteristics IC versus VCB as shown in Fig. 6.9.
The typical value of this parameter is of the order of 0.1 to 10 m mhos.
put) collector current to the corresponding change in the (input) emitter current
keeping the (output) collector voltage VCB constant. Hence,
DIC
hfb = ____ , VCB constant.
DIE
(4.16)
It is the slope of IC versus IE curve. Its typical value varies from 0.9 to 1.0.
It is defined as the ratio of the change in the
(input) emitter voltage and the corresponding change in (output) collector voltage with constant (input) emitter current, IE.
Hence,
DVEB
hrb = _____ , IE constant
DVCB
(4.17)
It is the slope of VEB versus VCB curve. Its typical value is of the order of 10 – 5
to 10 – 4.
To determine the input characteristics, the collector to
emitter voltage is kept constant at zero volt and base current is increased from
zero in equal steps by increasing VBE in the circuit shown in Fig. 4.10.
The value of VBE is noted for each setting of IB. This procedure is repeated for
higher fixed values of VCE, and the curves of IB Vs. VBE are drawn. The input
characteristics thus obtained are shown in Fig. 4.11.
When VCE = 0, the emitter-base junction is forward biased and the junction
behaves as a forward biased diode. Hence the input characteristic for VCE = 0 is
similar to that of a forward-biased diode. When VCE is increased, the width of
the depletion region at the reverse biased collector-base junction will increase.
Hence, the effective width of the base will decrease. This effect causes a decrease
in the base current IB. Hence, to get the same value of Ib as that for VCE = 0, VBE
should be increased. Therefore, the curve shifts to the right as VCE increases.
IB (mA)
250
VCE = 0V VCE > 0 V
200
150
100
50
0
0.2
0.4
0.6
0.8
VBE(V)
To determine the output characteristics, the base
current IB is kept constant at a suitable value by adjusting base-emitter voltage, VBE. The magnitude of collector-emitter voltage VCE is increased in suitable
equal steps from zero and the collector current IC is noted for each setting VCE.
Now the curves of IC versus VCE are plotted for different constant values of IB.
The output characteristics thus obtained are shown in Fig. 4.12.
From Eqs. (4.6) and (4.7), we have
a
b = _____ and
1–a
IC = (1 + b) ICBO + b IB
For larger values of VCE, due to early effect, a very small change in a is reflected
0.98
in a very large change in b. For example, when a = 0.98, b = _______ = 49. If
1 – 0.98
0.985
a increases to 0.985, then b = ________ = 66. Here, a slight increase in a by
1 – 0.985
about 0.5% results in an increase in b by about 34%. Hence, the output characteristics of CE configuration show a larger slope when compared with CB
configuration.
The output characteristics have three regions, namely, saturation region, cut-off
region and active region. The region of curves to the left of the line OA is called
the saturation region (hatched), and the line OA is called the saturation line. In
this region, both junctions are forward biased and an increase in the base current does not cause a corresponding large change in IC. The ratio of VCE(sat) to
IC in this region is called saturation resistance.
The region below the curve for IB = 0 is called the cut-off region (hatched). In
this region, both junctions are reverse biased. When the operating point for the
transistor enters the cut-off region, the transistor is OFF. Hence, the collector
current becomes almost zero and the collector voltage almost equals VCC, the
collector supply voltage. The transistor is virtually an open circuit between collector and emitter.
The central region where the curves are uniform in spacing and slope is called
the active region (unhatched). In this region, emitter-base junction is forward
biased and the collector-base junction is reverse biased. If the transistor is to be
used as a linear amplifier, it should be operated in the active region.
If the base current is subsequently driven large and positive, the transistor
switches into the saturation region via the active region, which is traversed at
a rate that is dependent on factors such as gain and frequency response. In this
ON condition, large collector current flows and collector voltage falls to a very
low value, called VCEsat, typically around 0.2 V for a silicon transistor. The transistor is virtually a short circuit in this state.
High speed switching circuits are designed in such a way that transistors are
not allowed to saturate, thus reducing switching times between ON and OFF
times.
The slope of the CE characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly
known as common emitter hybrid parameters or h-parameters.
It is defined as the ratio of the change in (input) base
VCE kept constant. Therefore,
DVBE
hie = _____, VCE constant
DIB
(4.18)
It is the slope of CE input characteristics IB versus VBE as shown in Fig. 4.11.
The typical value of hie ranges from 500 to 2000 W.
It is defined as the ratio of change in the (output)
collector current to the corresponding change in the (output) collector voltage
with the (input) base current IB kept constant. Therefore,
DIC
hoe = _____ , IB constant
DVCE
(4.19)
It is the slope of CE output characteristic IC versus VCE as shown in Fig. 4.12.
The typical value of this parameter is of the order of 0.1 to 10 m mhos.
It is defined as a ratio of the change in the (output) collector current to the corresponding change in the (input) base current
keeping the (output) collector voltage VCE constant. Hence,
DIC
hfe = ____, VCE constant
DIB
(4.20)
It is the slope of IC versus IB curve. Its typical value varies from 20 to 200.
It is defined as the ratio of the change in the
(input) base voltage and the corresponding change in (output) collector voltage
with constant (input) base current, IB. Hence,
DVBE
hre = _____ , IB constant
DVCE
(4.21)
It is the slope of VBE versus VCE curve. Its typical value is of the order of 10–5
to 10–4.
The circuit diagram for determining the static characteristics of an NPN transistor in the common collector configuration is shown in Fig. 4.13.
To determine the input characteristics, VEC is kept at
a suitable fixed value. The base-collector voltage VBC is increased in equal steps
and the corresponding increase in IB is noted. This is repeated for different fixed
values of VEC. Plots of VBC versus IB for different values of VEC shown in Fig.
4.14 are the input characteristics.
The output characteristics shown in Fig. 4.15 are the
same as those of the common emitter configuration.
Property
CB
CE
Input resistance
Low (about 100 W) Moderate
CC
High
(about 750 W)
(about 750 kW)
Output resistance
High
(about 450 kW)
Moderate
(about 45 kW)
Low
(about 25 W)
Current gain
1
High
High
Voltage gain
About 150
About 500
Less than 1
180°
0 or 360°
Phase shift between 0 or 360°
input & output
voltages
Applications
for high frequency for audio frequency
circuits
circuits
for impedance
matching
In a transistor amplifier with a.c. input signal, the ratio of change in output
current to the change in input current is known as the current amplification
factor.
DIC
In the CB configuration the current amplification factor, a = ____
(4.22)
DIE
DIC
In the CE configuration the current amplification factor, b = ____
DIB
(4.23)
DIE
In the CC configuration the current amplification factor, g = ____
DIB
(4.24)
We know that D IE = D IC + D IB
By definition,
D IC = a D IE
Therefore,
D IE = a D IE + D IB
i.e.
D IB = D IE (1 – a)
Dividing both sides by D IC, we get
DIB ____
DIE
____
=
(1 – a)
DIC DIC
Therefore,
1 __
1
__
= a (1 – a)
b
a
b = ______
(1 – a)
Rearranging, we also get
b
a = ______ ,
(1 + b)
1 __
1
or __
a–b=1
(4.25)
From this relationship, it is clear that as a approaches unity, b approaches infinity. The CE configuration is used for almost all transistor applications because
of its high current gain, b.
IB is the
input current and IE is the output current.
DIE
From Eq. (4.22),
g = ____
DIB
Substituting
D IB = D IE – D IC, we get
DIE
g = _________
DIE – DIC
Dividing the numerator and denominator on RHS by DIE, we get
DIE
____
DIE
1
g = _________ = _____
DI
DI
1–a
C
E
____
– ____
DIE DIE
Therefore,
1
g = _____ = (b + 1)
1–a
(4.26)
A load resistor RL is connected in series with the collector supply voltage VCC of
CB transistor configuration as shown in Fig. 4.16.
A small change in the input voltage between emitter and base, say DVi, causes
a relatively larger change in emitter current, say DIE. A fraction of this change
in current is collected and passed through RL and is denoted by symbol a ¢.
Therefore the corresponding change in voltage across the load resistor RL due
to this current is DV0 = a¢ RL DIE.
DV0
Here, the voltage amplification Av = ____ is greater than unity and thus the
DVi
transistor acts as an amplifier.
We know from the characteristics of CE configuration, the current amplificaa
tion factor is b ∫ _____,
1–a
and
IC = (1 + b) ICBO + bIB
The above equation can be expressed as
IC – ICBO = bICBO + bIB
Therefore,
IC – ICBO
b = ___________
IB – (– ICBO)
The output characteristics of CE configuration show that in the cut-off region,
the values IE = 0, IC = ICBO and IB = – ICBO. Therefore, the above equation gives
the ratio of the collector-current increment to the base-current change from cutoff to IB, and hence b is called the large-signal current gain of common-emitter
transistor.
The d.c. current gain of the transistor is given by
IC
bd.c. ∫ hFE ∫ __
IB
Based on this hFE value, we can determine whether the transistor is in saturation
or not. For any transistor, in general, IB is large compared to ICBO. Under this
condition, the value of hFE ª b.
The small-signal CE forward short-circuit gain b ¢ is defined as the ratio of a
collector-current increment DIC for a small base-current change DIB, at a fixed
collector-to-emitter voltage VCE.
i.e.
|
∂IC
b ¢ ∫ ___
∂IB VCE
If b is independent of currents, then b ¢ = b ª hFE. However, b is a function of
∂b
current, then b ¢ = b + (ICBO + IB) ___. By using b ¢ = hfe and b ª hFE. Therefore,
∂IB
the above equation becomes
hFE
hfe = _________________
∂hFE
1 – (ICBO + IB) ____
∂IC
In Fig. 4.17, the hFE versus IC shows a maximum and hence hfe > hFE for smaller
currents, and hfe < hFE for larger currents. Therefore, the above equation is valid
only for the active region.
In a common-base transistor circuit, the emitter current IE is 10 mA and the collector current IC is 9.8 mA. Find the value of the base current IB.
Solution
Given
IE = 10 mA and IC = 9.8 mA
We know that emitter current is
IE = IB + IC
10 × 10–3 = IB + 9.8 × 10–3
i.e.
Therefore,
IB = 0.2 mA
In a common-base connection, the emitter current IE is 6.28 mA and the collector
current IC is 6.20 mA. Determine the common-base d.c. current gain.
Solution
Given
IE = 6.28 mA and IC = 6.20 mA
We know that common-base d.c. current gain,
IC 6.20 × 10 –3
a = __ = __________
= 0.987
IE 6.28 × 10 –3
The common-base d.c. current gain of a transistor is 0.967. If the emitter current is
10 mA, what is the value of base current?
Solution
Given
a = 0.967 and IE = 10 mA
The common-base d.c. current gain (a) is
IC
IC
a = 0.967 = __ = ________
IE 10 × 10–3
Therefore,
IC = 0.967 ¥ 10 × 10–3 = 9.67 mA
The emitter current
IE = IB + IC
10 × 10–3 = IB + 9.67 × 10–3
i.e.
Therefore,
IB = 0.33 mA
The transistor has IE = 10 mA and
Solution
Given
= 0.98. Determine the values of IC and IB.
IE = 10 mA and a = 0.98
IC
The common-base d.c. current gain, a = __
IE
i.e.
Therefore
The emitter current
10 × 10–3 = IB + 9.8 × 10–3
IB = 0.2 mA
i.e.
Therefore,
If a transistor has a
Solution
IC
0.98 = ________
10 × 10–3
IC = 0.98 ¥ 10 × 10–3 = 9.8 mA
IE = IB + IC
If
If
A transistor has
current.
of 0.97, find the value of . If
= 200, find the value of .
a
0.97
a = 0.97, b = _____ = _______ = 32.33
1 – a 1 – 0.97
b
200
b = 200, a = _____ = _______ = 0.995
b + 1 200 + 1
= 100. If the collector current is 40 mA, find the value of emitter
Solution
Given
b = 100 and IC = 40 mA
IC 40 × 10–3
b = 100 = __ = ________
IB
IB
IB = 40 × 10–3/100 = 0.4 mA and
Therefore,
IE = IB + IC = (0.4 + 40) ¥ 10 – 3 = 40.4 mA
A transistor has
Solution
= 150. Find the collector and base currents, if IE = 10 mA.
Given
b = 150 and IE = 10 mA
b
150
The common-base current gain, a = _____ = _______ = 0.993
b + 1 150 +1
IC
a = __
IE
Also,
IC
0.993 = ___
10
i.e.
Therefore,
IC = 0.993 ¥ 10 × 10–3 = 9.93 mA
The emitter current
IE = IB + IC
10 ¥ 10 – 3 = IB + 9.93 ¥ 10 – 3
i.e.
IB = (10 – 9.93) ¥ 10 – 3 = 0.07 mA
Therefore,
Determine the values of IB and IE for the transistor circuit if IC = 80 mA and
= 170.
Solution
Given
We know that (b),
Therefore,
and
b = 170 and IC = 80 mA
IC 80 × 10–3
b = 170 = __ = ________
IB
IB
80 × 10 – 3
IB = _________ = 0.47 mA
170
IE = IB + IC = (0.47 + 80) mA = 80.47 mA
Determine the values of IC and IE for the transistor circuit of
mA.
= 200 and IB = 0.125
Solution
IB = 0.125 mA and b = 200
IC
IC
b = 200 = __ = ___________
IB 0.125 × 10 – 3
Given
Therefore,
Therefore,
IC = 200 ¥ 0.125 ¥ 10 – 3 = 25 mA
and
IE = IB + IC = (0.125 + 25) ¥ 10 – 3 = 25.125 mA
Determine the values of IC and IB for the transistor circuit of IE = 12 mA and
= 100.
Solution
IE = 12 mA and b = 100
Given
IE
12 × 10 – 3
We know that base current, IB = _____ = _________ = 0.1188 mA
1 + 100
1+b
IC = IE – IB = (12 – 0.1188) ¥ 10 – 3 = 11.8812 mA
and collector current,
A transistor has IB = 100 A and IC = 2 A. Find (a) of the transistor, (b) of
the transistor, (c) emitter current IE, (d) if IB changes by + 25 A and IC changes by
+ 0.6 mA, find the new value of .
Solution
Given IB = 100 mA = 100 ¥ 10 – 6 A and IC = 2 mA = 2 ¥ 10 – 3 A.
(a) To find
of the transistor
IC
2 × 10 – 3
b = __ = __________
= 20
IB 100 × 10 – 6
(b) To find
of the transistor
b
20
a = _____ = ______ = 0.952
b + 1 1 + 20
(c) To find emitter current, IE
IE = IB + IC = 100 ¥ 10 – 6 + 2 ¥ 10 – 3 A
= (0.01 + 2) ¥ 10 – 3 = 2.01 ¥ 10 – 3 A = 2.01 mA
(d) To find the new value of
Therefore,
when DIB = 25 mA and DIC = 0.6 mA
IB = (100 + 25) mA = 125 mA
IC = (2 + 0.6) mA = 2.6 mA
New value of b of the transistor,
IC 2.6 × 10 – 3
b = __ = __________
= 20.8
IB 125 × 10 – 6
For a transistor circuit having
and IE.
Solution
= 0.98, ICBO = ICO = 5 A and IB = 100 A, find IC
a = 0.98, ICBO = ICO = 5 mA and IB = 100 mA
Given
The collector current is
ICO
a ◊ IB
0.98 × 100 × 10 – 6 5 × 10 – 6
IC = _____ + _____ = _______________ + _______ = 5.15 mA
1–a 1–a
1 – 0.98
1 – 0.98
The emitter current is
IE = IB + IC = 100 ¥ 10 – 6 + 5.15 ¥ 10 – 3 = 5.25 mA
Calculate the collector current and emitter for a transistor with adc = 0.99 and
ICBO = 50 mA when the base current is 20 mA.
[JNTU April/May 2007]
Solution
ICBO
adc IB
IC = ______ + ______
1 – adc 1 – adc
0.99 × 50 × 10–6
50 × 10–6
= ______________ + ________ = 9950 × 10–6 A
1 – 0.99
1 – 0.99
Given an NPN transistor for which a = 0.98, ICO = 2 mA and IEO = 1.6 mA. A common emitter connection is used and VCC = 12 V and RL = 4 kW. What is the minimum base current required in order that transistor enter in to saturation region.
Solution
Given a = 0.98, ICO = 2 mA, IEO = 1.6 mA and RL = 4 kW
We know that, VCC – IC RL – VCE(sat) = 0
We know that,
12 – IC × 4 × 103 – 0.3 = 0
11.7
IC = _______3 = 2.925 mA
4 × 10
ICO
a
IC = _____ IB + _____
1–a
1–a
0.98
2 × 10– 6
2.925 × 10–3 = _____ IB + ________
1.098
1 – 0.98
2 × 10–6
= 49 IB + _______
0.02
= 49 IB + 0.1 × 10–3
Therefore,
2.825 × 10–3
IB = ___________ = 57.56 mA
49
Calculate the values of IC and IE for a transistor with adc = 0.99 and ICBO = 5 mA.
[JNTU May 2003, Nov 2004]
IB is measured as 20 mA.
Solution
Given adc = 0.99, ICBO = 5 aA and IB 5 20 mA
ICBO
adc IB
0.99 × 20 × 10–6 5 × 10–6
IC = ______ + ______ = ______________ + _______ = 2.48 mA
1 – adc 1 – adc
1 – 0.99
1 – 0.99
Therefore, IE = IB + IC = 20 × 10–6 + 2.48 × 10–3 = 2.5 mA
A germanium transistor used in a complementary symmetry amplifier has ICBO = 10
A at 27°C and hFE = 50. (a) Find IC when IB = 0.25 mA and (b) assuming hFE does
not increase with temperature, find the value of new collector current, if the transistor’s temperature rises to 50°C.
Solution
Given ICBO = 10 mA and hFE (= b) = 50
(a) To find the value of collector current when IB = 0.25 mA
IC = b IB + (1 + b) ICBO
= 50 ¥ (0.25 ¥ 10 – 3) + (1 + 50) ¥ (10 ¥ 10– 6) A = 13.01 mA
(b) To find the value of new collector current if temperature rises to 50°C
We know that ICBO doubles for every 10°C rise in temperature. Therefore,
I ¢CBO (b = 50) = ICBO × 2 (T2 – T1)/10 = 10 ¥ 2(50 – 27)/10 mA
= 10 ¥ 22.3 mA = 49.2 mA
Therefore, the collector current at 50°C is
IC = b ◊ IB + (1 + b) I ¢CBO
= 50 ¥ (0.25 ¥ 10 – 3) + (1 + 50) ¥ 49.2 ¥ 10 – 6 A = 15.01 mA
When the emitter current of a transistor is changed by 1 mA, there is a change in
collector current by 0.99 mA. Find the current gain of the transistor.
Solution
DIC 0.99 × 10 – 3
The current gain of the transistor is a = ____ = __________
= 0.99
DIE
1 × 10 – 3
The d.c. current gain of a transistor in CE mode is 100. Determine its d.c. current
gain in CB mode.
Solution
The d.c. current gain of the transistor in CB mode is
bd.c.
ad.c. = _______
1 + bd.c.
100
= _______ = 0.99
1 + 100
When IE of a transistor is changed by 1 mA, its IC changes by 0.995 mA. Find its
common base current gain , and common-emitter current gain .
Solution
DIC 0.995 × 10 – 3
Common-base current gain is a = ____ = ___________
= 0.995
DIE
1 × 10 – 3
a
0.995
b = _____ = ________ = 199
1 – a 1 – 0.995
Common-emitter current gain is
The current gain of a transistor in CE mode is 49. Calculate its common-base current
gain. Find the base current when the emitter current is 3 mA. [JNTU Jan. 2010]
Solution
Given
We know that
b = 49
b
a = _____
1+b
49
Therefore, the common-base current gain is a = ______ = 0.98
1 + 49
IC
We also know that
a = __
IE
IC = aIE = 0.98 ¥ 3 ¥ 10 – 3 = 2.94 mA
Therefore,
Determine IC, IE and
Solution
for a transistor circuit having IB = 15 A and
= 150.
The collector current, IC = bIB = 150 ¥ 15 ¥ 10 – 6 = 2.25 mA
The emitter current, IE = IC + IB = 2.25 ¥ 10 – 3 + 15 ¥ 10 – 6 = 2.265 mA
Common-base current gain,
b
150
a = _____ = ____ = 0.9934
1 + b 151
Determine the base, collector and emitter currents and VCE for a CE circuit shown
in Fig. 4.18. For VCC = 10 V, VBB = 4 V, RB = 200 k , RC = 2 k , VBE (on) = 0.7
V, = 200.
Solution
Referring to Fig. 4.18, the base current is
VBB – VBE (on)
4 – 0.7
IB = _____________ = _________3 = 16.5 mA
RB
200 × 10
The collector current is
IC = bIB = 200 ¥ 16.5 ¥ 10 – 6 = 3.3 mA
The emitter current is
IE = IC + IB = 3.3 ¥ 10 – 3 + 16.5 ¥ 10 – 6 = 3.3165 mA
Therefore,
VCE = VCC – ICRC = 10 – 3.3 ¥ 10 – 3 ¥ 2 ¥ 103 = 3.4 V
Calculate the values of IC and IE for a transistor with d.c. = 0.99 and ICBO = 5 A.
IB is measured as 20 A.
[JNTU May 2003, Nov 2004 Jan. 2010]
Solution
Given ad.c. = 0.99, ICBO = 5 mA and IB = 20 mA
ICBO
ad.c.IB
0.99 × 20 × 10 – 6 5 × 10 – 6
IC = _______ + _______ = _______________ + ________ = 2.48 mA
1 – ad.c. 1 – ad.c.
1 – 0.99
1 – 0.99
Therefore, IE = IB + IC = 20 ¥ 10 – 6 + 2.48 ¥ 10 – 3 = 2.5 mA
The reverse leakage current of the transistor when connected in CB configuration is
0.2 A and it is 18 A when the same transistor is connected in CE configuration.
Calculate d.c. and d.c. of the transistor.
[JNTU May 2003]
Solution
The leakage current ICBO = 0.2 mA
ICEO = 18 mA
Assume that
IB = 30 mA
IE = IB + IC
IC = IE – IB = bIB + (1 + b) ICBO
We know that
ICBO
ICEO = _____ = (1 + b)ICBO
1–a
ICEO
18
b = ____ – 1 = ___ – 1 = 89
ICBO
0.2
Ic = bIB + (1 + b)ICBO
= 89 (30 ¥ 10– 3) + (1 + 89) (0.2 ¥ 10– 6)
= 2.67 A
ICBO
0.2 × 10 – 6
ad.c. = 1 – ____ = 1 – _________
= 0.988
ICEO
18 × 10 – 6
IC – ICBO
bd.c. = ________
IB – ICEO
2.67 – 0.2 × 10 – 6
= ___________________
= 89
30 × 10 – 3 – 18 × 10 – 6
If
d.c.
= 0.99 and ICBO = 50 A, find emitter current.
Solution
Assume that
Given ad.c. = 0.99 and ICBO = 50 mA,
IB = 1 mA
ICBO
ad.c. IB
0.99 (1 × 10 – 3) 50 × 10 – 6
IC = _______ + _______ = _____________ + _________
1 – ad.c. 1 – ad.c.
1 – 0.99
1 – 0.99
0.99 × 10 – 3 50 × 10 – 6
= __________ + _________ = 99 mA + 5 mA = 104 mA
0.01
0.01
IE = IC + IB = 104 mA + 1 mA = 105 mA
For the CE amplifier circuit shown in Fig. 4.19, find the
percentage change in collector current if the transistor with
hfc = 50 is replaced by another transistor with hfc = 150.
Assume VBE = 0.6.
[JNTU May 2006]
Solution
+ 12 V
R1
25 kW
RC
1 kW
R2
5 kW
RE
100 W
R2
5 × 103
VB = _______ × VCC = ________________
× 12 = 2 V
R1 + R2
5 × 103 + 25 × 103
VE = VB – VBE = 2 – 0.6 = 1.4 V
VE 1.4
IE = ___ = ____ = 14 mA
RE 100
Here,
IE
14 × 10 – 3
b = 50, IB = _____ = _________ = 274.5 mA
51
1+b
For
Therefore,
IC1 = bIB = 50 × 274.5 × 10 – 6 = 13.725 mA
IE
14 × 10 – 3
b = 150, IB = ______ = _________ = 92.715 mA
151
1+b
For
Therefore,
IC2 = bIB = 150 × 92.715 × 10 – 6 = 13.907 mA
Hence, the percentage change in collector current is calculated as
IC2 – ICE
13.907 × 10 – 3 – 13.725 × 10 × 10–3
________
× 100 = ______________________________
× 100 = 1.326%
IC1
13.725 × 10 – 3
Given an NPN transistor for which = 0.98, ICO = 2 A and ICEO = 16 A. A common emitter connection is used as shown in Fig. 4.20 with VCC = 12 V and RC = 4
k . What is the minimum base current required in order that transistor enter into
saturation region.
[JNTU Dec. 2005]
RC
4 kW
RB
VBB
Solution
RC = 4 kW
+ IB
12 V
–
+
VCC
–
Given a = 0.98, ICO = 2 mA, ICEO = 1.6 mA, VCC = 12 V and
VCC
12
IC(sat) = ____ = _______3 = 3 mA
RC
4 × 10
a
0.98
b = _____ = _______ = 49
1 – a 1 – 0.98
IC (sat)
IB(min) = _____
b
3 × 10 – 3
= ________ = 61.224 × 10 – 6 = 61.224 mA
49
A transistor operating in CB configuration has IC = 2.98 mA, IE = 3 mA and
ICO = 0.01 mA . What current will flow in the collector circuit of this transistor when
connected in CE configuration with a base current of 30 A? [JNTU, May 2008]
Solution
Given IC = 2.98 mA, IE = 3 mA, ICO = 0.01 mA and IB = 30 mA.
For CB configuration, IC = aIE + ICO
Therefore,
IC – ICO (2.98 – 0.01) × 10 – 3
a = _______ = _________________
= 0.99
IE
3 × 10–3
a
0.99
b = _____ = _______ = 99
1 – a 1 – 0.99
For CE configuration, IC = bIB + (1 + b) ICO
= 99 × 30 × 10 – 6 + (1 + 99) × 0.01 × 10 – 3 = 3.97 mA.
For the circuit shown in Fig. 4.21, determine IE, VC and VCE. Assume VBE = 0.7 V.
[JNTU April/May 2007]
VEE = 8 V
RF = 2.2 KΩ
Si
–VCE
VE
VC
IE
RC = 1.8 KΩ
VCC = 10 V
Solution Given VEE = 8 V, VCC = 10 V, VBE = 0.7 V, b = 100, RE = 2.2 kW
and RC = 1.8 kW
To find IE
From the circuit,
– 8 = IE RE + 0.7
– 8.7 = IERE
– 8.7
IE = ________3 = – 3.955 mA
2.2 × 10
To find VC
IC
IB = __
b
IC
1
IE = IC + IB = IC + __ = IC 1 + __
b
b
(
)
( )
101
– 3.955 mA = IC ____
100
Therefore,
Therefore,
IC = – 3.9154 mA
VC = 10 – IC RC
= 10 – 3.9154 × 10– 3 × 1.8 × 103 = 2.952 V
To find VCE
From the circuit,
10 – IC RC – VCE – IE (2.2 × 103) + 8 = 0s
10 – 7.048 – VCE – 8.7 + 8 = 0
VCE = 2.252 V
A transistor operating in CB configuration has IC = 2.98 mA, IE = 3 mA and
ICO = 0.01 mA. What current will flow in the collector circuit of this transistor when
connected in CE configuration with a base current of 30 mA?
[JNTU May/June 2008]
Solution Given IC = 2.98 mA, IE = 3 mA, ICO = 0.01 mA and IB = 30 mA.
For CB configuration,
IC = aIE + ICO
IC – ICO (2.98 – 0.01) × 10– 3
a = _______ = _________________
= 0.99
IE
3 × 10– 3
Therefore,
a
0.99
b = _____ = _______ = 99
1 – a 1 – 0.99
For CE configuration,
IC = bIB + (1 + b) ICO
= 99 × 30 × 10– 6 + (1 + 99) × 0.01 × 10– 3 = 3.97 mA.
The reverse saturation current in a transistor is 8 mA. If the transistor common base
current gain is 0.979, calculate the collector and emitter currents for 40 mA base
current.
[JNTU May/June 2008]
Solution Given ICO = 8 mA, a = 0.979 and IE = 40 mA
IC = aIE + ICO = 0.979 × 40 × 10– 6 + 8 × 10– 6 = 47.16 mA
The general expression for collector current IC of a transistor for any voltage
across collector junction VC and emitter current IE is
(
VC
___
IC = – aNIE – ICO e VT – 1
)
(4.27)
where aN is the current gain in normal operation and ICO is the collector junction
reverse saturation current.
In inverted mode of operation, the above equation can be written as
(
VE
___
IE = – aIIC – IEO e VT – 1
)
(4.28)
where aI is the inverted common-base current gain and IEO is the emitter junction reverse saturation current.
The above four parameters are related by the condition
aIICO = aNIEO
(4.29)
For many transistors IEO lies in the range 0.5 ICO to ICO .
Figure 4.22 shows the Ebers–Moll model for a PNP transistor. Here, two separate ideal diodes are connected back to back with saturation currents – IEO and
– ICO and there are two dependent current-controlled current sources shunting
the ideal diodes. The current sources account for the minority carrier transport
across the base. An application of Kirchoff’s current law to the collector node
of Fig. 4.22 gives
(
VC
___
IC = – aNIE + I = – aNIE + IO e VT – 1
)
(4.30)
where I is the diode current. As IO is the magnitude of reverse saturation current,
then IO = – ICO. Substituting this value of IO in Eqn. (4.30), we get
(
VC
___
IC = – aNIE – ICO e VT – 1
)
which is nothing but the general expression for collector current of a transistor
given in Eqn. (4.27). Hence, this model is valid for both forward and reverse
static voltages applied across the transistor junctions. Here, base spreading
resistance has been omitted and the difference between ICBO and ICO have been
neglected.
The dependent current sources may be removed from Fig. 4.23, provided
aN = aI = 0. If the base-width is made much larger than the diffusion length
of minority carriers in the base, all minority carriers will recombine in the base
and no minority carrier will be available to reach the collector. Therefore, the
transistor amplification factor a will become zero. As a result, transistor action
ceases. Hence, it is not possible to construct a transistor by simply placing two
isolated diodes back to back.
There is a possibility of voltage breakdown in the transistor at high voltages even
though the rated dissipation of the transistor is not exceeded. Therefore, there is
an upper limit to the maximum allowable collector junction voltage. There are
two types of breakdown, namely, Avalanche multiplication or Avalanche breakdown and reach-through or punch-through.
When a diode is reverse biased, there is a limit on the voltage that can be applied
which is the Avalanche voltage. Similarly, in the transistor, the maximum reverse
biasing voltage which may be applied before breakdown between the collector
and base terminals with the emitter open is called breakdown voltage BVCBO.
Therefore, an upper limit is set on the collector voltage VCB by avalanche breakdown in the reverse biased collector–base junction. Fields of order 106 V/m are
required in the depletion layer for breakdown to occur, which usually limits VCB
to a maximum of several tens of volts.
Breakdown may occur because of Avalanche multiplication of the current ICO
that crosses the collector junction. As a result of this multiplication, the current
becomes MICO, where M is the Avalanche multiplication factor. At the breakdown voltage BVCBO, multiplication factor M becomes infinite and the current
rises abruptly in the breakdown region, as shown in Fig. 4.24, there will be large
changes in current with small changes in applied voltage.
The Avalanche multiplication factor depends on the voltage VCB between collector and base, which has been found to be given empirically by
1
M = ____________n
V
CB
1 – ______
BVCBO
(
)
(4.31)
where the empirical constant, n, depends on the lattice material and the carrier
type, which is usually in the range of about 2 to 10; for N-type silicon n ª 4 and
for P-type n ª 2, and controls the sharpness of the onset breakdown. Taking
Avalanche multiplication into account, IC has the magnitude M a IE, where a is
the common base current gain. As a result, in the presence of Avalanche multiplication, the current gain of CB transistor has become Ma. As the effective current gain exceeds unity, the emitter circuit may then display negative resistance
effects, which can lead to undesirable instabilities.
IC
IB2 IB = 0
IB1
BVCEO
BVCBO
VCE
For the CE configuration, the collector to emitter breakdown voltage BVCEO
with base open is
____
BVCEO
÷
1
= BVCBO n ___
hFE
(4.32)
In general, BVCEO is 40–50% of BVCBO. This is the upper limit of VCE that can
be placed across the transistor without damaging it.
According to early effect, the width of the collector-junction transition region
increases with increased collector-junction voltage. As the voltage applied across
the junction VCB increases the transition region penetrates deeper into the base
and will have spread completely across the base to reach the emitter junction, as
the base is very thin. Thus, the collector voltage has reached through the base
region. This effect, known as reach-through, also affects the output characteristics of a transistor since IC versus VCB curves are no longer horizontal but take
on a positive slope indicating that the device has a finite output impedance that
is voltage dependent. Since the input characteristics are also affected, the input
impedance is also influenced by VCB.
It is possible to raise the punch-through voltage by increasing the doping concentration in the base, but this automatically reduces the emitter efficiency.
Punch-through takes place at a fixed voltage between collector and base and is
not dependent on circuit configuration, whereas Avalanche multiplication takes
place at different voltages depending upon the circuit configuration. Therefore,
the voltage limit of a particular transistor is determined by either of the two
types of breakdown, whichever occurs at lower voltage.
Phototransistor or Photodiode is a much more sensitive semiconductor photodevice than the PN photodiode. The current produced by a photodiode is very
low which cannot be directly used in control applications. Therefore, this current
should be amplified before applying to control circuits. The phototransistor is
a light detector which combines a photodiode and a transistor amplifier. When
the phototransistor is illuminated, it permits a larger flow of current.
Figure 4.25 shows the circuit of an NPN phototran-sistor. It is usually connected
in a CE configuration with the base open. A lens focuses the light on the basecollector junction. Although the phototransistor has three sections, only two
leads, the emitter and collector leads, are generally used. In this device, base current is supplied by the current created by the light falling on the base-collector
photodiode junction.
Light
C
N
P
N
B
RL
E
Output
+
V
–
When there is no radiant excitation, the minority carriers are generated thermally, and the electrons crossing from the base to the collector and the holes
crossing from the collector to the base constitute the reverse saturation collector
current ICO. With IB = 0, the collector current is given by
IC = (b + 1) ICO
When the light is turned ON, additional minority carriers are photogenerated
and the total collector current is
IC = (b + 1)(ICO + IL)
where IL is the reverse saturation current due to the light.
Current in a phototransistor is dependent mainly on the intensity of light entering the lens and is less affected by the voltage applied to the external circuit.
Figure 4.25 shows a graph of collector current IC as a function of collectoremitter voltage VCE and as a function of illumination H.
The phototransistors find extensive applications in high-speed reading of computer punched cards and tapes, light detection systems, light operated switches,
reading of film sound track, production line counting of objects which interrupt
a light beam, etc.
The specifications of some of the commonly used BJT-NPN small-signal transistor and BJT-PNP small-signal transistor are given in Table 4.2(a) and (b)
respectively.
Based on the construction, the FET can be classified into two types as Junction
FET (JFET) and Metal Oxide Semiconductor FET (MOSFET) or Insulated
Gate FET (IGFET) or Metal Oxide Silicon Transistor (MOST).
Depending upon the majority carriers, JFET has been classified into two
types, namely (i) N-channel JFET with electrons as the majority carriers, and
(iii) P-channel JFET with holes as the majority carriers.
It consists of a N-type bar which is made of silicon. Ohmic contacts (terminals),
made at the two ends of the bar, are called Source and Drain.
This terminal is connected to the negative pole of the battery.
Electrons which are the majority carriers in the N-type bar enter the bar through
this terminal.
This terminal is connected to the positive pole of the battery. The
majority carriers leave the bar through this terminal.
Heavily doped P-type silicon is diffused on both sides of the N-type
silicon bar by which PN junctions are formed. These layers are joined together
and called Gate G.
IC (max)
(mA)
100
100
100
100
100
100
200
200
600
700
800
1000
10000
15 A
30
30
30
500
2 Amps
1 Amp
30
Parameter
Type
BC107
BC108
BC109
BC547
BC548
BC549
2N2369A
2N3904
2N4401
2N3053
2N2222A
BFY50
BUY82
2N3055
2N916
2N2369
2N3040
BF184
BF185
BF195
SL100
PT4
AC176
BF115
145 mW
155 mW
4W
800
250
145
PD
(max)
(mW)
300
300
300
625
625
625
360
350
350
5.0 W
500
2800
30 W
115 W
360
360
360
145
30
32
20
50
20
20
30
20
VCEO
(max)
(Volts)
45
20
20
45
30
30
15
40
40
40
40
35
60
60
25
50
32
32
60
30
30
VCBO
(max)
(Volts)
50
30
30
50
30
30
40
60
60
60
75
80
150
70
45
40
40
30
45-165
83
80-320
50-280
67
67
110-450@2
110-800@2
200-800@2
110-800@2
110-800@2
110-800@2
20 (min)@100
100-300@10
100-300@150
50-250@ 150
100-300 @ 150
30(min)@150
40 (min) @ 1.5A
20-70 @ 4A
50-200 @ 10
40-120 @ 10
40-160 @ 150
75 to 750
hfe (min-max) @
IC (mA)
-
-
10
7
10
10
5
5
5
5
5
5
1
1
2
10
10
10
5
1.1
0.5
0.35
0.20
10
Vce(Volts)
230
Mc/S
3
-
200
220
300
300
300
300
300
250
500 (min)
300 (min)
250 (max)
100
300
60 (min)
60
0.8
300
500
50
300
fT @ MHz
-
AC128
PT6
SK100
-
-
BC177
BC178
BC179
BC557
BC558
BC559
2N3906
2N4403
BDY20
2N2222A
2N3040
-
Complement
AM for receivers class B
push pull stage
Amplifier and Radio
receiver
Radio receivers, Tape
recording
General Broadcast and
television
Low noise AN and FM
applications
Audio driver
General purpose
Low noise audio
Amplifier
Amplifier
Low noise audio
High-speed switch
Low level amplifier
General purpose
General purpose
High speed switch
General purpose
High power switch
O/P – SW
For IF amplifier
Applications
VCE
(Volts)
– 45
– 25
– 20
– 45
– 30
– 32
– 40
– 20
– 45
Parameter
Type
BC157
BC158
BC159
BC557
BC558
AF115
2N2904
AD162
BC177
VCB
– 50
– 32
– 60
– 50
– 30
– 32
– 25
– 30
(Volts)
– 50
IC
– 100
–2 A
– 0.6 A
– 100
– 100
– 10
– 100
– 100
(mA)
– 100
–5
–1
-
-
– 0.25
– 0.25
-
50-300
-
75
-
10 mA
10 mA
(Volts)
– 0.25 10 mA
Vce @ IC
175-500
50-300
20-40
110-300
75
150
125-500
75-500
75-260
hfe @ IC
-
-
2 mA
2 mA
-
2 mA
2 mA
2 mA
200
1.5
200
150
150
75
150
150
150
-
6W
-
-
10 mA
10 mA
10 mA
fT @ IC (MHz)
300
.6W
0.6 W
500
500
75
300
300
300
Ptot
(mW)
S.S.
Amplifier
S.S.
Amplifier
S.S.
Amplifier
4p. small sig.
4p. small sig.
RF.
Amplifier
mixer oscillator in SW
receiver
Switching
& driving
applications
Audio
matched pair
Audio driver
Use
BC107
-
-
BC157, DS557
BC158, DS558
AF125. AF200
BC179, BC309
BC177, BC212,
BC307
BC175, BC308
Comparable Types
The region BC of the N-type bar between the depletion region is
called the channel. Majority carriers move from the source to drain when a
potential difference VDS is applied between the source and drain.
When no voltage is applied between drain and
source, and gate and source, the thickness of the depletion regions around the
PN junction is uniform as shown in Fig. 4.26.
Depletion region
G
C
S
N
P
B
D
N
P
In this case, the PN junctions
are reverse biased and hence the thickness of the depletion region increases. As
VGS is decreased from zero, the reverse bias voltage across the PN junction is
increased and hence, the thickness of the depletion region in the channel also
increases until the two depletion regions make contact with each other. In this
condition, the channel is said to be cut-off. The value of VGS which is required
to cut-off the channel is called the cut-off voltage VC.
Drain is positive with respect
to the source with VGS = 0. Now the majority carriers (electrons) flow through
the N-channel from source to drain. Therefore the conventional current ID flows
from drain to source. The magnitude of the current will depend upon the following factors:
1. The number of majority carriers (electrons) available in the channel, i.e.
the conductivity of the channel.
2. The length L of the channel.
3. The cross-sectional area A of the channel at B.
4. The magnitude of the applied voltage VDS. Thus the channel acts as a resistor of resistance R given by
rL
R = ___
(4.33)
A
VDS AVDS
ID = ____ = _____
R
rL
(4.34)
where r is the resistivity of the channel. Because of the resistance of the channel and the applied voltage VDS, there is a gradual increase of positive potential
along the channel from source to drain. Thus the reverse voltage across the
PN junctions increases and hence the thickness of the depletion regions also
increases. Therefore, the channel is wedge shaped as shown in Fig. 4.27.
VGG
+
–
G
S
D
C
B
N
N
ID
P
–
VDD
+
As VDS is increased, the cross-sectional area of the channel will be reduced. At a
certain value VP of VDS, the cross-sectional area at B becomes minimum. At this
voltage, the channel is said to be pinched off and the drain voltage VP is called
the pinch-off voltage.
As a result of the decreasing cross-section of the channel with the increase of
VDS, the following results are obtained.
(i) As VDS is increased from zero, ID increases along OP, and the rate of
increase of ID with VDS decreases as shown in Fig. 4.28. The region from
VDS = 0V to VDS = VP is called the ohmic region. In the ohmic region,
ID (mA)
Ohmic
region
Break down
voltage
Pinch-off
region
C
IDSS
P
VGS = 0
B
VGS = –1 V
VGS = –2 V
VGS = –3 V
0
Vp
BVDGO
VDS (V )
the drain to source resistance ____ is related to the gate voltage VGS, in an
ID
almost linear manner. This is useful as a voltage variable resistor (VVR) or
voltage dependent resistor (VDR).
(ii) When VDS = VP, ID becomes maximum. When VDS is increased beyond
VP, the length of the pinch-off or saturation region increases. Hence, there
is no further increase of ID.
(iii) At a certain voltage corresponding to the point B, ID suddenly increases.
This effect is due to the Avalanche multiplication of electrons caused by
breaking of covalent bonds of silicon atoms in the depletion region between
the gate and the drain. The drain voltage at which the breakdown occurs is
denoted by BVDGO. The variation of ID with VDS when VGS = 0 is shown in
Fig. 4.27 by the curve OPBC.
DS
negative voltage less than the negative cut-off voltage, the reverse voltage across
the junction is further increased. Hence for a negative value of VGS, the curve of
ID versus VDS is similar to that for VGS = 0, but the values of VP and BVDGO are
lower, as shown in Fig. 4.29.
From the curves, it is seen that above the pinch-off voltage, at a constant value
of VDS, ID increases with an increase of VGS. Hence, a JFET is suitable for use as
a voltage amplifier, similar to a transistor amplifier.
It can be seen from the curve that for voltage VDS = VP, the drain current is not
reduced to zero. If the drain current is to be reduced to zero, the ohmic voltage
drop along the channel should also be reduced to zero. Further, the reverse biasing to the gate-source PN junction essential for pinching off the channel would
also be absent.
The drain current ID is controlled by the electric field that extends into the channel due to reverse biased voltage applied to the gate; hence, this device has been
given the name Field Effect Transistor.
In a bar of P-type semiconductor, the gate is formed due to N-type semiconductor. The working of the P-channel JFET will be similar to that of N-channel
JFET with proper alterations in the biasing circuits; in this case holes will be
the current carriers instead of electrons. The circuit symbols for N-channel and
P-channel JFETs are shown in Fig. 4.28. It should be noted that the direction of
the arrow points in the direction of conventional current which would flow into
the gate if the PN junction was forward biased.
In a JFET, the drain current ID depends upon the drain voltage VDS and the
gate voltage VGS. Any one of these variables may be fixed and the relation
between the other two are determined. These relations are determined by the
three parameters which are defined below.
It is the slope of the transfer
characteristic curves, and is defined by
( )
∂ID
gm = _____
∂VGS
DID
= _____, VDS held constant.
DVGS
VDS
It is the ratio of a small change in the drain current to the corresponding small
change in the gate voltage at a constant drain voltage. The change in ID and VGS
should be taken on the straight part of the transfer characteristics. It has the unit
of conductance in mho.
It is the reciprocal of the slope of the drain characteristics and is defined by
( )
∂VDS
rd = _____
∂ID
DVDS
= _____, VGS held constant.
DID
VGS
It is the ratio of a small change in the drain voltage to the corresponding small
change in the drain current at a constant gate voltage. It has the unit of resistance in ohms.
The drain resistance at VGS = 0 V, i.e. when the depletion regions of the channel are absent, is called as drain-source ON resistance, represented as RDS or
RDS(ON).
The reciprocal of rd is called the drain conductance. It is denoted by gd or gDS.
It is defined by
∂VDS
DVDS
m = _____ ID = – _____, ID held constant.
DVGS
∂VGS
( )
It is the ratio of a small change in the drain voltage to the corresponding small
change in the gate voltage at a constant drain current. Here, the negative sign
shows that when VGS is increased, VDS must be decreased for ID to remain
constant.
ID depends on VDS and VGS, the
functional equation can be expressed as
ID = f(VDS, VGS)
If the drain voltage is changed by a small amount from VDS to (VDS + DVDS)
and the gate voltage is changed by a small amount from VGS to (VGS + DVGS),
then the corresponding small change in ID may be obtained by applying Taylor’s
theorem with neglecting higher order terms. Thus the small change DID is given
by
DID
DID = _____
DVDS
( )
∂ID
DVDS + _____
VGS
∂VGS
( )
VDS
DVGS
Dividing both the sides of this equation by DVGS, we obtain
DID
∂ID
_____
= _____
DVGS
∂VDS
DVDS
∂ID
_____
+ _____
DVGS
∂VGS
( ) ( ) ( )
VGS
VDS
DID
If ID is constant, then _____ = 0
DVGS
Therefore, we have
DVDS
_____
DVGS
( ) ( ) ( )
∂ID
0 = _____
∂VDS
VGS
∂ID
+ _____
∂V
ID
GS
VDS
Substituting the values of the partial differential coefficients, we get
( )
1
0 = __
rd ( – m ) + gm
m = gm rd
Hence,
Therefore, amplification factor (m) is the product of drain resistance (rd) and
transconductance (gm).
The FET’s continuous power dissipation, PD, is the
product of ID and VDS.
A single-ended-geometry junction FET is shown in
Fig. 4.30 in which the diffusion is done from one side only. The substrate is of
P-type material which is epitaxially grown on an N-type channel. A P-type gate
Drain
Source
Channel
P
ID
N
Gate
P
p
(Substrate)
Source
is then diffused into the N-type channel. The substrate functions as a second
gate which is of relatively low resistivity material. The diffused gate is also of
very low resistivity material, allowing the depletion region to spread mostly into
the N-type channel. A slab of N-type semiconductor is sandwiched between two
layers of P-type material forming two PN junction in this device.
The gate reverse voltage that removes all the free charge from the channel is
called the pinch-off voltage VP. We consider that the P-type region is doped with
NA acceptor atoms, the N-type region is doped with ND donor atoms and the
junction formed is abrupt.
Moreover, if the acceptor impurity density is assumed to be much larger than
the donor density, then the depletion region width in the P-region will be much
smaller than the depletion width of the N-region i.e. NA >> ND, then WP << WN
and WP = W. We know that, the relationship between potential and charge
density is given by
– qND
d 2V ______
____
= e
2
dx
Integrating the above equation subject to boundary conditions, we get
– qND
dV ______
___
= e (x – W)
dx
Integrating again, we get
– qND
V = _____ (x2 – 2Wx)
2e
At x =
, V = VB which is the junction or barrier potential. Thus,
qNDW2
VB = _______
2e
As the barrier potential represents a reverse voltage, it is lowered by an applied
forward voltage V(x) at x and it is expressed as VB = VP – V(x). Now, the
space-charge width, Wn( ) = W(x) at a distance x along the channel in Fig. 4.31
becomes
{
2e
W(x) = – b( ) = ____ [V0 – V(x)]
qND
1
__
2
}
where e is the dielectric constant of channel material, q is the magnitude of
electronic charge, V0 is the junction contact potential at x, V(x) is the applied
potential across space-charge region at x and is a negative value for an applied
reverse bias, a is the metallurgical channel thickness between the substrate and
P+ gate region, a – b( ) is the penetration W( ) of depletion region into channel
at a point x along channel as shown in Fig. 4.30 and WPO is the depletion region
width at pinch-off.
If the drain current is zero, b(x) and V(x) are independent of x and hence b(x)
= b. If we substitute b(x) = b = 0 in the previous equation and solve for V with
the assumption that |V0| << |V|, the pinch-off voltage VP can be obtained as
qND
|VP| = ____a2
2e
Here, at pinch-off, the depletion width WPO = a when |VP| = |VGS| and hence
(
2e
WPO = ____VGS
qND
)
1/2
To study the effect of VGS, given VGS = V0 – V(x) in the space charge width
equation, we get
{
2e
a – b = ____ VGS
qND
Upon solving, we get
[
a2
a – b = ___ VGS
VP
]
}
1/2
1/2
Further simplifying,
( )
VGS
a–b
____
_____
a = VP
2
Therefore,
( 1 – __ba )
1/2
VGS
= ____
VP
Hence, the gate source voltage is
(
b
VGS = 1 – __
a
)
2
VP
For a reverse biased P+ N junction, VGS must be a negative voltage across the
gate junction and is independent of distance along the channel if ID = 0.
When a reverse gate voltage of 12 V is applied to JFET, the gate current is 1 nA.
Determine the resistance between gate and source.
Solution
VGS = 12 V, IG = 10–9 A.
VGS
12
Therefore, gate-to-source resistance = ____ = ____
= 12,000 MW
IG
10–9
When the reverse gate voltage of JFET changes from 4.0 to 3.9 V, the drain current
changes from 1.3 to 1.6 mA. Find the value of transconductance.
Solution
DVGS = 4.0 – 3.9 = 0.1 V
D ID = 1.6 – 1.3 = 0.3 mA
DID
0.3 × 10–3
Therefore, transconductance, gm = _____ = _________ = 3 m mho.
DVGS
0.1
An FET has a drain current of 4 mA. If IDSS = 8 mA and VGS(off ) = – 6 V. Find the
values of VGS and VP.
Solution
[
VGS
ID = IDSS 1 – _______
VGS(off)
[
VGS
4 = 8 1 + ____
6
]
2
]
2
__
VGS
4
1__
1 + ____ = __ = ___
= 0.707
6
8 ÷2
÷
Therefore,
VGS = – 1.76 V
VP = |VGS(off )| = 6V
For the transfer characteristics, VDS is maintained constant at a suitable value
greater than the pinch-off voltage VP. The gate voltage VGS is decreased from
zero till ID is reduced to zero. The transfer characteristics ID versus VGS is shown
in Fig. 4.32. The shape of the transfer characteristic is very nearly a parabola. It
is found that the characteristic is approximately represented by the parabola,
(
VGS
IDS = IDSS 1 – ____
VP
2
)
(4.35)
where IDS is the saturation drain current, IDSS is the value of IDS when VGS = 0,
and VP is the pinch-off voltage.
Differentiating Eq. (4.35) with respect to VGS we can obtain an expression for
gm.
∂IDS
VGS
_____
= IDSS × 2 1 – ____
VP
∂VGS
(
)( )
1
– ___
VP
dIDS
We know that gm = _____, VDS is constant.
dVGS
(
– 2 IDSS
VGS
Therefore, gm = _______ 1 – ____
VP
VP
)
(4.36)
Now from Eqn. (4.35), we have
____
(
) ÷
VGS
IDS
1 – ____ = ____
VP
IDSS
(4.37)
Substituting this value in Eqn. (4.36), we get
_______
– 2÷IDS IDSS
gm = ___________
VP
Suppose gm = gmo, when VGS = 0, then from Eqn. (4.36)
2IDSS
gmo = – _____
VP
(4.38)
Therefore, from Eqs (4.36) and (4.38)
(
VGS
gm = gmo 1 – ___
VP
)
(4.39)
Equation (4.37) shows that gm varies as the square root of the saturation drain
current IDS, and Eqn. (4.39) shows that gm decreases linearly with increase of
VGS.
From Eq. (4.37), we have
_______
– 2÷IDS IDSS
gm = ___________
VP
_______
– 2÷IDS IDSS
∂IDS
_____
= ___________
VP
∂VGS
or
Substituting IDS = IDSS,
∂IDS
2IDSS IDSS
_____
= – _____ = ____
VP
–VP
∂VGS
____
2
This equation shows that the tangent to the curve at IDS = IDSS, VGS = 0, will
– VP
have an intercept a _____ on the axis of VGS as shown in Fig. 4.31. Therefore, the
2
value of VP can be found by drawing the tangent at IDS = IDSS, VGS = 0.
The gate-source cut off voltage, VGS(off ), on the transfer characteristic is equal to
the pinch off voltage, VP, on the drain characteristics, i.e. VP = |VGS(off )|.
Therefore,
[
VGS
ID = 1 – _______
VGS(off)
]
2
An N-channel JFET has IDSS = 8 mA and VP = – 5 V. Determine the minimum
value of VDS for pinch-off region and the drain current IDS, for VGS = – 2V in the
pinch-off region.
Solution The minimum value of VDS for pinch-off to occur for VGS = – 2 V is
VDS min = VGS – VP = – 2 – (–5) = 3 V
[
VGS
IDS = IDSS 1 – ____
VP
]
2
= 8 × 10–3 [1 – (–2)/(–5)]2 = 2.88 mA
For an N-Channel silicon FET with a = 3 × 10–4 cm and ND = 1015 electrons/cm3,
find the pinch-off voltage.
[JNTU June 2009]
Solution
where
We know that the pinch-off voltage is
qND
|VP| = ____ a2
2e
e = dielectric constant of channel material (Si) = er e0 = 12 e0 ,
q = magnitude of electronic change = 1.602 × 10–19 C
a is in metres and ND is in electrons/m3
1.602 × 10–19 × 1021
|VP| = ___________________
× (3 × 10–6)2 = 6.8 V
–12
2 × 12 × 8.854 × 10
Therefore,
Determine the pinch-off voltage for an N-channel silicon FET with a channel width
of 5.6 × 10–4 cm and a donor concentration of 1015 /cm3. Given, the dielectric constant of Si is 12.
ND = 1015/cm3 = 1021/m3, e = er eo = 12 e0
Solution
a = 5.6 × 10– 4 cm = 5.6 × 10–6 m
qND
The pinch-off voltage, |VP| = ____ a2
2e
where
e = dielectric constant of channel material (Si) = er e0 = 12 e0
q = magnitude of electronic charge
a is in metres and ND is in electrons/m3
1.602 × 10–19 × 1021
|VP | = ____________________
× (5.6 × 10–6)2 = 23.6 V
2 × 12 × 8.854 × 10–12
For a P-channel silicon FET, with an effective channel width, a = 2 × 10–4 cm and
channel resistively r = 20 W – cm, find the pinch-off voltage
Solution
We know that the pinch-off voltage for P-channel FET,
qNA
VP = ____ × a2
2e
For silicon,
e = 12e0 and mp = 500 cm2/V – sec
1
s = __
r = pmp × q = NA mp × q
i.e.
1
1
_________
–4
qNA = ____
rmp = 20 × 500 = 1× 10
Therefore,
qNA
1 × 10– 4
VP = ____ × a2 = ___________________
× (2 × 10– 4)2 = 1.89 V
–12
2e
2 × 12 × 8.854 × 10
1. FET operation depends only on the flow of majority carriers-holes for
P-channel FETs and electrons for N-channel FETs. Therefore, they are
called Unipolar devices. Bipolar transistor (BJT) operation depends on
both minority and majority current carriers.
2. As FET has no junctions and the conduction is through an N-type or
P-type semiconductor material, FET is less noisy than BJT.
3. As the input circuit of FET is reverse biased, FET exhibits a much higher
input impedance (in the order of 100 M W) and lower output impedance
and there will be a high degree of isolation between input and output. So,
FET can act as an excellent buffer amplifier but the BJT has low input
impedance because its input circuit is forward biased.
4. FET is a voltage controlled device, i.e. voltage at the input terminal controls the output current, whereas BJT is a current controlled device, i.e. the
input current controls the output current.
5. FETs are much easier to fabricate and are particularly suitable for ICs
because they occupy less space than BJTs.
6. The performance of BJT is degraded by neutron radiation because of the
reduction in minority-carrier lifetime, whereas FET can tolerate a much
higher level of radiation since they do not rely on minority carriers for their
operation.
7. The performance of FET is relatively unaffected by ambient temperature
changes. As it has a negative temperature coefficient at high current levels, it prevents the FET from thermal breakdown. The BJT has a positive temperature co-efficient at high current levels which leads to thermal
breakdown.
8. Since FET does not suffer from minority carrier storage effects, it has
higher switching speeds and cut-off frequencies. BJT suffers from minority
carrier storage effects and therefore has lower switching speed and cut-off
frequencies.
9. FET amplifiers have low gain bandwidth product due to the junction
capacitive effects and produce more signal distortion except for small signal operation.
10. BJTs are cheaper to produce than FETs.
1. FET is used as a buffer in measuring instruments, receivers since it has high
input impedance and low output impedance.
2. FETs are used in RF amplifiers in FM tuners and in communication equipment for its low noise level.
3. Since the input capacitance is low, FETs are used in cascade amplifiers in
measuring and test equipments.
4. Since the device is voltage controlled, it is used as a voltage variable resistor
in operational amplifiers and tone controls.
5. FETs are used in mixer circuits in FM and TV receivers, and in communication equipment because inter modulation distortion is low.
6. It is used in oscillator circuits because frequency drift is low.
7. As the coupling capacitor is small, FETs are used in low frequency amplifiers in hearing aids and in inductive transducers.
8. FETs are used in digital circuits in computers, LSD and memory circuits
because of its small size.
MOSFET is the common term for the Insulated Gate Field Effect Transistor
(IGFET). There are two basic forms of MOSFET: (i) Enhancement MOSFET
on the semiconducting material, the thickness and hence the resistance of a conducting channel of a semiconducting material can be controlled.
In a depletion MOSFET, the controlling electric field reduces the number
of majority carriers available for conduction, whereas in the enhancement
MOSFET, application of electric field causes an increase in the majority carrier
density in the conducting regions of the transistor.
The construction of an N-channel enhancement MOSFET is
shown in Fig. 4.33(a) and the circuit symbols for an N-channel and a P-channel
enhancement MOSFET are shown in Fig. 4.33(b) and (c), respectively. As there
is no continuous channel in an enhancement MOSFET, this condition is represented by the broken line in the symbols.
Two highly doped N+ regions are diffused in a lightly doped substrate of P-type
silicon substrate. One N+ region is called the source S and the other one is called
the drain D. They are separated by 1 mil (10–3 inch). A thin insulating layer of
SiO2 is grown over the surface of the structure and holes are cut into the oxide
layer, allowing contact with source and drain. Then a thin layer of metal aluminium is formed over the layer of SiO2. This metal layer covers the entire channel region and it forms the gate G.
–
VGG
+
D
S
D
G
SiO2
Al
Substrate
N
+
N
Induced
N-channel
P-Type substrate
–
ID
+
B
G
+
G
S
(a)
(b) N
N-Channel
D
Substrate
B
G
S
(c) P
P-Channel
The metal area of the gate, in conjunction with the insulating oxide layer of SiO2
and the semiconductor channel forms a parallel plate capacitor. This device is
called the insulated gate FET because of the insulating layer of SiO2. This layer
gives an extremely high input impedance for the MOSFET.
If the substrate is grounded and a positive voltage is applied at the
gate, the positive charge on G induces an equal negative charge on the substrate
side between the source and drain regions. Thus, an electric field is produced
between the source and drain regions. The direction of the electric field is perpendicular to the plates of the capacitor through the oxide. The negative charge
of electrons which are minority carriers in the P-type substrate forms an inversion layer. As the positive voltage on the gate increases, the induced negative
charge in the semiconductor increases. Hence, the conductivity increases and
current flows from source to drain through the induced channel. Thus the drain
current is enhanced by the positive gate voltage as shown in Fig. 4.34.
8
VGS = +3V
6
+ 2V
Enhancement
ID (mA) 4
+ 1V
0V
–1V
2
–2V
–3V
0
5
10
15
Depletion
20
VDS(V)
The construction of an N-channel depletion MOSFET is shown in Fig. 4.35(a)
where an N-channel is diffused between the source and drain to the basic structure of MOSFET. The circuit symbols for an N-channel and a P-channel depletion MOSFET are shown in Figs. 4.35(b) and (c), respectively.
With VGS = 0 and the drain D at a positive potential with respect to the source, the
electrons (majority carriers) flow through the N-channel from S to D. Therefore,
the conventional current ID flows through the channel D to S. If the gate voltage
is made negative, positive charge consisting of holes is induced in the channel
through SiO2 of the gate-channel capacitor. The introduction of the positive
charge causes depletion of mobile electrons in the channel. Thus a depletion
–VGG
+
N + + + + +
N
ID
+
N-Channel
P-type substrate
–
+
VDD
(b) N-channel
(c) P-channel
region is produced in the channel. The shape of the depletion region depends
on VGS and VDS. Hence the channel will be wedge shaped as shown in Fig. 4.35.
When VDS is increased, ID increases and it becomes practically constant at a certain value of VDS, called the pinch-off voltage. The drain current ID almost gets
saturated beyond the pinch-off voltage.
Since the current in an FET is due to majority carriers (electrons for an N-type
material), the induced positive charges make the channel less conductive, and ID
drops as VGS is made negative.
The depletion MOSFET may also be operated in an enhancement mode. It is only
necessary to apply a positive gate voltage so that negative charges are induced
into the N-type channel. Hence, the conductivity of the channel increases and ID
increases. As the depletion MOSFET can be operated with bipolar input signals
irrespective of doping of the channel, it is also called as dual mode MOSFET.
The volt-ampere characteristics are indicated in Fig. 4.36.
The curve of ID versus VGS for constant VDS is called the transfer characteristics
of MOSFET and is shown in Fig. 4.36.
In actual MOSFET characteristic as shown in Fig. 4.37, a non-zero slope exists
beyond the saturation point. For the saturation region, i.e., (VDS > VDS (sat)),
the effective channel length decreases and this phenomenon is called channel
length modulation. For an N-channel device, the slope of the curve in the saturation region can be expressed by using the drain current ID given by
ID = KN (VGS – VTN)2 (1 + lVDS)
ID
Slope =
– VA = –
1
l
0
1
ro
VDS
where l is a positive quantity called the channel length modulation parameter or
l–1 is analogous to the early voltage in bipolar transistors, KN is the conduction
parameter and VTN is the threshold voltage. The curves are extended so that the
intercept at a point ID = 0, VDS = –VE which means that VE = 1/l.
The output resistance due to the channel length modulation is expressed by
–1
( )
∂ID
r0 = _____
∂VDS
|VGS = const.
The output resistance can be determined at the Q-point by
r0 = [lKN(VGSQ – VTN)2]–1
[ (
VGSQ
= lIDSS 1 – _____
VP
i.e.,
)]
2 –1
VE
1
r0 @ [ lIDQ ]–1 = _____ = ____
lIDQ IDQ
The output resistance is an important factor in the analysis of small signal equivalent circuit of MOSFET.
The threshold voltage VTN or VTP and onduction parameter KN or KP are functions of temperature. The magnitude of threshold voltage decreases with temperature and hence the drain current ID increases with temperature at a given
VGS. The conduction parameter is directly proportional to mobility mN or mP of
the carrier, which increases as the temperature decreases. Here the temperature
dependent of mobility is larger than that of the threshold voltage. Hence the
net effect of decreasing drain current at a given VGS due to increase in temperature provides a negative feedback condition and hence the stability for a power
MOSFET.
1. In enhancement and depletion types of MOSFET, the transverse electric
field induced across an insulating layer deposited on the semiconductor
material controls the conductivity of the channel. In the JFET, the transverse electric field across the reverse biased PN junction controls the conductivity of the channel.
2. The gate leakage current in a MOSFET is of the order of 10–12 A. Hence
the input resistance of a MOSFET is very high in the order of 1010 to 1015
W. The gate leakage current of a JFET is of the order of 10–9 A and its input
resistance is of the order of 108 W.
3. The output characteristics of the JFET are flatter than those of the
MOSFET and hence, the drain resistance of a JFET (0.1 to 1 MW) is much
higher than that of a MOSFET (1 to 50 kW).
4. JFETs are operated only in the depletion mode. The depletion type
MOSFET may be operated in both depletion and enhancement mode.
5. Comparing to JFET, MOSFETs are easier to fabricate.
6. MOSFET is very susceptible to overload voltage and needs special handling
during installation. It gets damaged easily if it is not properly handled.
7. MOSFET has zero offset voltage. As it is a symmetrical device, the source
and drain can be interchanged. These two properties are very useful in
analog signal switching.
8. Special digital CMOS circuits are available which involve near-zero power
dissipation and very low voltage and current requirements. This makes
them most suitable for portable systems.
MOSFETs are widely used in digital VLSI circuits than JFETs because of
their advantages.
The MOSFET has the drawback of being very susceptible to overload voltage
and may require special handling during installation. The MOSFET gets damaged easily if it is not properly handled. A very thin layer of SiO2, between the
gate and channel is damaged due to high voltage and even by static electricity.
The static electricity may result from the sliding of a device in a plastic bag. If
a person picks up the transistor by its case and brushes the gate against some
grounded object, a large electrostatic discharge may result. In a relatively dry
atmosphere, a static potential of 300 V is not uncommon on a person who has
high resistance soles on his footwear.
MOSFETs are protected by a shorting ring that is wrapped around all four
terminals during shipping and must remain in place until after the device is soldered into position. Prior to soldering, the technician should use a shorting strap
to discharge his static electricity and make sure that the tip of the soldering iron
is grounded. Once in circuit, there are usually low resistances present to prevent
Oxide Insulation
Gate 1 Gate 2
(Metal) (Metal)
P
P
N
Source
1
N
Drain 1
Source 2
N
Channel 1
(N)
Source
terminal
P
P
Channel 2
(N)
Substrate
(Bulk)
Unit No. 1
Gate-protection
Diodes
Drain 2
N
Unit No. 2
Drain
terminal
Gate protection
diodes
any excessive accumulation of electrostatic charge. However, the MOSFET
should never be inserted into or removed from a circuit with the power ON.
JFET is not subject to these restrictions, and even some MOSFETs have a built
in gate protection known as “integral gate protection,” a system built into the
device to get around the problem of high voltage on the gate causing a puncturing of the oxide layer. The manner in which this is done is shown in the cross
sectional view of Fig. 4.38. The symbol clearly shows that between each drain
and the source is placed a back-to-back (or front-to-front) pair of diodes, which
are built right into the P-type substrate.
These diodes are designed so that if either gate exceeds +10 V typically, with
respect to the source, the upper diode will conduct and the lower diode will
breakdown by Zener effect, providing a shunt path for excessive charge from
gate to source. Similarly, if the gate voltage exceeds –10 V, the lower diode conducts and the upper diode breaks down. The breakdown voltage from either
gate to source is in a range such that normal application of signal will not be
affected by the gate protection diodes. In addition to providing protection
against preinstallation high static voltages, these diodes also guard against incircuit transients.
The current-voltage relationships of the N-channel and P-channel MOSFETs
are given in Table 4.3.
N-Channel MOSFET
P-Channel MOSFET
Saturation region (VDS > VDS(sat))
ID = KN(VGS – VTN)2
Saturation region (VSD > VSD (sat))
ID = KP(VSG + VTP)2
Non saturation region (VDS < VDS(sat))
2
ID = KN[2(VGS – VTN)VDS – VDS
]
Non saturation region (VSD < VSD(sat))
ID = KP[2(VSG + VTP)VSD – V2 DS]
Transition point
Transition point
VDS(sat) = VGS – VTN
VSD(sat) = VSG + VTP
Enhancement mode
VTN > 0
Enhancement mode
VTP < 0
Depletion mode
VTN < 0
Depletion mode
VTP > 0
1. The P-channel enhancement MOSFET is very popular because it is much
easier and cheaper to produce than the N-channel device.
2. The hole mobility is nearly 2.5 times lower than the electron mobility. Thus,
a P-channel MOSFET occupies a larger area than an N-channel MOSFET
having the same ID rating.
3. The drain resistance of P-channel MOSFET is three times higher than that
for an identical N-channel MOSFET.
4. The N-channel MOSFET has the higher packing density which makes it
faster in switching applications due to the smaller junction areas and lower
inherent capacitances.
5. The N-channel MOSFET is smaller for the same complexity than P-channel
device.
6. Due to the positively charged contaminants, the N-channel MOSFET may
turn ON prematurely, whereas the P-channel device will not be affected.
1. In an N-channel JFET the current carriers are electrons, whereas the current carriers are holes in a P-channel JFET.
2. Mobility of electrons is large in N-channel JFET; mobility of holes is poor
in P-channel JFET.
3. The input noise in less in N-channel JFET than that of P-channel JFET.
4. The transconductance is larger in N-channel JFET than that of P-channel
JFET.
FET is operated in the constant-current portion of its output characteristics for
the linear applications. In the region before pinch-off, where VDS is small, the
drain to source resistance rd can be controlled by the bias voltage VGS. The FET
is useful as a Voltage Variable Resistor (VVR) or Voltage Dependent Resistor
(VDR).
ID
In JFET, the drain-to-source conductance gd = ____ for small values of VDS ,
VDS
which may also be expressed as,
[ ( )]
VGS
gd = gdo 1 – ____
VP
1
__
2
where gdo is the value of drain conductance when the bias voltage VGS is zero.
The variation of the rd with VGS can be closely approximated by the empirical
expression,
r0
rd = ________
1 – KVGS
where r0 = drain resistance at zero gate bias, and K = a constant, dependent
upon FET type.
Thus, small signal FET drain resistance rd varies with applied gate voltage VGS
and FET acts like a variable passive resistor.
FET finds wide applications where VVR property is useful. For example, the
VVR can be used in Automatic Gain Control (AGC) circuit of a multistage
amplifier.
The development of the digital CMOS logic led to the wide use of the MOSFET
devices, Mostly, they employ the P and N channel enhancement MOSFETs, as
the basic element. Power dissipation has become a major concern in the integrated circuits, since increasingly more number of transistors are packed into
smaller chips. The main use of the CMOS logic arose due to the fact that it
reduces the static power consumption, by (ideally) allowing zero current from
the power supply to the ground. The CMOS circuit accomplishes this reduction
of power dissipation by its operating characteristics. In the basic CMOS inverter
configuration, both the gates are tied together to the input signal. When the input
switches LOW, only the PMOS device conducts, providing the conducting path
for charging the output node. The NMOS device does not conduct due to LOW
at its gate. Thus, no power supply to ground path exists and power dissipation
due to the short-circuit is avoided. Similarly, when the input switches to HIGH
from LOW level, the PMOS devices stops conducting and the NMOS device
conducts. This discharges the output node to the ground bringing the output
to logic LOW. During this process, the PMOS device does not provide the path
from the power supply to the output node. Thus, the static power dissipation
from the power supply to ground is theoretically eliminated. This arrangement
greatly reduces power consumption and heat generation. However, during the
switching of the logic input and the resultant output signals, the short-circuit or
switching power dissipation occurs. At this time, both the MOSFETs will conduct briefly leading to dynamic power dissipation that depends on the frequency
of switching. Digital and analog CMOS applications are described below:
The growth of digital technologies like the microprocessor has provided the
motivation to advance MOSFET technology faster than any other type of silicon-based devices. The major advantage of MOSFETs for digital switching is
that the oxide layer between the gate and the channel prevents the d.c. current
from flowing through the gate. This further reduces the power consumption and
offers very large input impedance. The insulating oxide between the gate and
channel effectively isolates the MOSFET between logic stages. This allows a single MOSFET output in driving a considerable number of MOSFET inputs. The
bipolar transistor-based logic (such as TTL) does not have such a high impedance
input capability. This gate isolation realized by the MOS devices also makes it
easier for the designers to ignore to some extent, the loading effects felt between
the logic stages. However, this is limited by the operating frequency, since, as the
frequency increases, the input impedance of the MOSFETs decreases.
The advantages of MOSFETs realized in most of the digital circuits do not
reflect into the analog circuits. The two types of electronic circuits, namely, analog and digital, operate in different regions of the transistor operation. The digital circuits switch mostly outside the switching region or the Saturation region
of operation. On the other hand, the analog circuits mainly operate in the linear
region of operation. The bipolar junction transistor (BJT) has traditionally been
the analog designer’s transistor of choice, due largely to its higher transconductance and its higher output impedance (drain-voltage independence) in the
switching region.
Nevertheless, the MOSFETs are also widely used in many types of analog circuits because of certain advantages. The characteristics and performance of
many analog circuits can be designed by changing the sizes (length and width)
of the MOSFETs. On the other hand, the size of the bipolar device does not significantly affect the performance. The near zero gate current and the negligible
drain-source offset voltage of the MOSFETs make them ideal switching elements. This factor makes possible the realization of switched capacitor analog
circuits.
While operating in their linear region, the MOSFETs can be used as precision
resistors, which can have a much higher controlled resistance than the BJTs. In
high power circuits, MOSFETs have the advantage of not suffering from thermal runaway as BJTs do. Also, they can be formed into capacitors and gyrator
circuits which allow op-amps made from them to appear as inductors, thereby
allowing all of the normal analog devices, except for diodes (which can be made
smaller than a MOSFET), to be built entirely out of MOSFETs. This allows the
designer to realize a complete analog circuit to be made on a silicon chip, in a
much smaller chip area.
Some ICs combine both the analog and digital MOSFET circuitries on a single
mixed-signal integrated circuit, making the required board size even smaller.
This creates a need to isolate the analog circuits from the digital circuits in the
chip level, leading to the use of isolation rings and the need for the Siliconon-Insulator (SoI) chips. The main advantage of BJTs over MOSFETs, in
the analog design process is the ability of BJTs to handle a larger current in a
smaller space. Fabrication processes exit that incorporate both the BJTs and
MOSFETs configured into a single dvice. Mixed-transistor devices are called
Bi-FETs (Bipolar-FETs), if they contain either BJT-NFET or BJT-PFET combinations, or BiCMOS (Bipoar-CMOS) if they contain complementary BJTPFETs. Such devices have the advantages of both the insulated gates and higher
current density.
BJTs have some advantages over MOSFETs for at least two digital applications, Firstly, in high speed switching, they do not have the larger capacitance
factor imposed by the gate, which when multiplied by the resistance of the channel gives the intrinsic time constant of the process. The intrinsic time constant
places a limit on the speed performance at which a MOSFET can operate, since
the higher frequency signals may be filtered out. Widening the channel reduces
the resistance of the channel. However, it increases the capacitance by the same
amount. On the other hand, reducing the width of the channel increases the
resistance, but reduces the capacitance by the same amount. For example, if R
× C = Tc1, the value of 0.5 R × 2C = Tc1 and 2R × 0.5 = Tc1. There is no other
way to minimize the intrinsic time constant for a certain process. The various
processes using different channel lengths, channel heights, gate thicknesses and
materials will also have varying intrinsic time constants. This problem is mostly
avoided while using a BJT, since it does not use a gate.
The second application where the BJTs prove more advantageous over the
MOSFETs stems from the first reasoning. While driving several fan-out gates,
the resistance of the MOSFET is in series with the gate capacitances of the other
FETs, creating a secondary time constant. Delay circuits use this fact to create
a fixed signal delay by using a small CMOS device to send a signal to many
other, larger CMOS fan-out devices. The secondary time constant can be minimized by increasing the driving FET’s channel width to decrease its resistance
and decreasing the channel widths of the FETs being driven, for reducing the
fan-out or driven capacitance. However, its drawback is that, this increases the
capacitance of the driving FET and increases the resistance of the FETs being
driven. Usually this drawback is a negligible factor, while comparing with the
timing problem. The BJTs are better able to drive the other gates, since they
can provide more output current than the MOSFETs. This allows the FETs
being driven to get charged faster. Therefore, many integrated circuits employ
the MOSFET driven inputs and BiCMOS outputs.
÷
÷
The quiescent operating point of a transistor amplifier should be established
in the active region of its characteristics. Since the transistor parameters such
as b, ICO and VBE are functions of temperature, the operating point shifts with
changes in temperature. The stability of different methods of biasing transistor
(BJT, FET and MOSFET) circuits and compensation techniques for stabilizing
the operating point are discussed in this chapter.
The quiescent operating point of a transistor amplifier should be established
in the active region of its characteristics. Since the transistor parameters such
as b, ICO and VBE are functions of temperature, the operating point shifts with
changes in temperature. The stability of different methods of biasing transistor
(BJT, FET and MOSFET) circuits and compensation techniques for stabilizing
the operating point are discussed in this chapter.
In order to produce distortion-free output in amplifier circuits, the supply voltages and resistances in the circuit must be suitably chosen. These voltages and
resistances establish a set of d.c. voltage VCEQ and current ICQ to operate the transistor in the active region. These voltages and currents are called quiescent values
which determine the operating point or Q-point for the transistor. The process of
giving proper supply voltages and resistances for obtaining the desired Q-point
is called biasing. The circuits used for getting the desired and proper operating
point are known as biasing circuits.
The collector current for common-emitter amplifier is expressed by
IC = bIB + ICEO = bIB + (1 + b )ICO
Here the three variables hFE, i.e., b, IB and ICO are found to increase with temperature. For every 10°C rise in temperature, ICO doubles itself. When ICO increases,
IC increases significantly. This causes power dissipation to increase and hence to
make ICO increase. This will cause IC to increase further and the process becomes
cumulative which will lead to thermal runaway that will destroy the transistor.
In addition, the quiescent operating point can shift due to temperature changes
and the transistor can be driven into the region of saturation. The effect of b on
the Q-point is shown in Fig. 5.1. One more source of bias instability to be considered is due to the variation of VBE with temperature.VBE is about 0.6 V for
a silicon transistor and 0.2 V for a germanium transistor at room temperature.
As the temperature increases, |VBE | decreases at the rate of 2.5 mV/°C for both
silicon and germanium transistors. The transfer characteristic curve shifts to
the left at the rate of 2.5 mV/°C (at constant IC) for increasing temperature and
hence the operating point shifts accordingly. To establish the operating point in
the active region, compensation techniques are needed.
Referring to the biasing circuit of Fig. 5.2(a), the values of VCC
and RC are fixed and IC and VCE are dependent on RB.
Applying Kirchhoff’s voltage law to the collector circuit in Fig. 5.2(a), we get
VCC = IC RC + VCE.
The straight line represented by AB in Fig. 5.2(b) is called the d.c. load line.
The coordinates of the end point A are obtained by substituting VCE = 0 in the
VCC
above equation. Then IC = ____. Therefore, the coordinates of A are VCE = 0 and
RC
VCC
____
IC =
.
RC
The coordinates of B are obtained by substituting IC = 0 in the above equation.
Then VCE = VCC. Therefore, the coordinates of B are VCE = VCC and IC = 0. Thus,
the d.c. load line AB can be drawn if the values of RC and VCC are known.
As shown in Fig. 5.2(b), the optimum Q-point is located at the midpoint of the
d.c. load line AB between the saturation and cut-off regions, i.e. Q is exactly
midway between A and B. In order to get faithful amplification, the Q-point
must be well within the active region of the transistor.
Even though the Q-point is fixed properly, it is very important to ensure that the
operating point remains stable where it is originally fixed. If the Q-point shifts
nearer to either A or B, the output voltage and current get clipped, thereby output signal is distorted.
In practice, the Q-point tends to shift its position due to any or all of the following three main factors:
(i) Reverse saturation current, ICO, which doubles for every 10°C increase in
temperature.
(ii) Base-emitter voltage, VBE, which decreases by 2.5 mV per °C.
(iii) Transistor current gain, b, i.e., hFE which increases with temperature.
Referring to Fig. 5.2(a), the base current IB is kept constant since IB is approximately equal to VCC /RB. If the transistor is replaced by another one of the same
type, one cannot ensure that the new transistor will have identical parameters as
that of the first one. Parameters such as b vary over a range. This results in the
variation of collector current IC for a given IB. Hence, in the output characteristics, the spacing between the curves might increase or decrease which leads to the
shifting of the Q-point to a location which might be completely unsatisfactory.
After drawing the d.c. load line, the operating point Q is properly located at the center of the d.c. load line. This operating point is chosen
under zero input signal condition of the circuit. Hence, the a.c. load line should
also pass through the operating point Q. The effective a.c. load resistance, Ra.c.,
is the combination of RC parallel to RL, i.e. Ra.c. = RC || RL. So the slope of the
1
a.c. load line CQD will be – ____ .
Ra.c.
(
)
To draw an a.c. load line, two end points, viz. maximum VCE and maximum IC
when the signal is applied are required.
Maximum VCE = VCEQ + ICQ Ra.c., which locates the point D (0D) on the VCE
axis.
VCEQ
Maximum IC = ICQ + _____, which locates the point C (0C ) on the IC axis.
Ra.c.
By joining points C and D, a.c. load line CD is constructed. As RC > Ra.c., the
d.c. load line is less steep than the a.c. load line.
When the signal is zero, we have the exact d.c. conditions. From Fig. 5.2(b), it is
clear that the intersection of d.c. and a.c. load lines is the operating point Q.
In the transistor amplifier shown in Fig. 5.2(a), RC = 8 k , RL = 24 k and VCC =
24 V. Draw the d.c. load line and determine the optimum operating point. Also draw
the a.c. load line.
Solution
(a) d.c. load line:
Referring to Fig. 5.2(a), we have VCC = VCE + IC RC.
For drawing d.c. load line, the two end points, viz. maximum VCE point (at
IC = 0) and maximum IC point (at VCE = 0) are required.
Maximum
VCE = VCC = 24 V
VCC
24
Maximum IC = ____ = _______3 = 3 mA
RC
8 × 10
Therefore, the d.c. load line AB is drawn with the point B (0B = 24 V) on
the VCE axis and the point A (0A = 3 mA) on the IC axis, as shown in Fig.
5.2(b).
(b) For fixing the optimum operating point Q, mark the middle of the d.c. load
line AB and the corresponding VCE and IC values can be found.
Here,
VCC
VCEQ = ____ = 12 V
2
and ICQ = 1.5 mA
(c) a.c. load line:
To draw an a.c. load line, two end points viz. maximum VCE and maximum
IC when the signal is applied are required.
The a.c. load,
Maximum
8 × 24
Ra.c. = RC || RL = ______ = 6 kW
8 + 24
VCE = VCEQ + ICQ Ra.c.
= 12 + 1.5 ¥ 10–3 ¥ 6 ¥ 103 = 21 V
This locates the point D (0D = 21 V) on the VCE axis.
VCEQ
Maximum collector current = ICQ + _____
Ra.c.
12
= 1.5 ¥ 10 – 3 + _______3 = 3.5 mA
6 × 10
This locates the point C (0C = 3.5 mA) on the IC axis. By joining points C
and D, a.c. load line CD is constructed.
For the transistor amplifier shown in
Fig. 5.3(a), VCC = 12 V, R1 = 8 k ,
R2 = 4 k , RC = 1 k , RE = 1 k and RL
= 1.5 k . Assume VBE = 0.7 V. (a) Draw
the d.c. load line, (b) determine the operating point, and (c) draw the a.c. load
line.
(a)
Solution
(a) d.c. load line:
Referring to Fig. 5.3(a), we have
VCC = VCE + IC (RC + RE ).
To draw the d.c. load line, we need
two end points, viz. maximum VCE
point (at IC = 0) and maximum IC
point (at VCE = 0).
Maximum VCE = VCC = 12 V, which
locates the point B (0B = 12 V) of the d.c.
load line.
VCC
12
IC = ________ = ___________3 = 6 mA
RC + RE (1 +1) × 10
Maximum
This locates the point A (0A = 6 mA) of the d.c. load line. Figure 5.3(b)
shows the d.c. load line AB, with (12 V, 6 mA).
(b) Operating point Q
The voltage across
R2
R2 is V2 = _______ VCC
R1 + R2
Therefore,
4 × 103
V2 = ________3 × 12 = 4 V
12 × 10
V2 = VBE + IERE
Therefore,
V2 – VBE 4 – 0.7
IE = ________ = _______3 = 3.3 mA
RE
1 × 10
IC ª IE = 3.3 mA
VCE = VCC – IC (RC + RE)
= 12 – 3.3 ¥ 10 – 3 ¥ 2 ¥ 103 = 5.4 V
Therefore, the operating point Q is at 5.4 V and 3.3 mA, which is shown on
the d.c. load line.
(c) a.c. load line
To draw the a.c. load line, we need two end points, viz. maximum VCE and
maximum IC when signal is applied.
a.c. load,
1 × 1.5
Ra.c = RC || RL = _______ kW = 0.6 kW
2.5
Therefore, maximum
VCE = VCEQ + ICQ Ra.c.
= 5.4 + 3.3 ¥ 10 – 3 ¥ 0.6 ¥ 103 = 7.38 V
This locates the point C (0C = 7.38 V) on the VCE axis.
Maximum
VCEQ
IC = ICQ + _____
Ra.c.
5.4
= 3.3 ¥ 10 – 3 + ________3 = 12.3 mA
0.6 × 10
This locates the point D (0D = 12.3 mA) on the IC axis. By joining points
C and D, a.c. load line CD is constructed.
Design the circuit shown in Fig. 5.4, given
Q-point values are to be ICQ = 1 mA and
VCEQ = 6 V. Assume that VCC = 10 V,
= 100 and VBE (on) = 0.7 V.
VCC
RB
RC
Vi
Solution
The collector resistance is
VCC – VCEQ
10 – 6
RC = ___________ = _______
= 4 kW
ICQ
1 × 10–3
The base current is
ICQ 1 × 10–3
IBQ = ____ = _______ = 10 mA
100
b
The base resistance is
VCC – VBE (on)
10 – 0.7
RB = _____________ = _________
= 0.93 MW
IBQ
10 × 10 – 6
Determine the characteristics of a circuit shown in Fig. 5.5. Assume that
and VBE (on) = 0.7 V.
Solution
Referring to Fig. 5.5, Kirchhoff’s voltage law equation is
VBB = IBRB + VBE (on) + IERE
We know that
= 100
IE = IB + IC = IB + bIB = (1 + b )IB
The base current
VBB – VBE (on)
5 – 0.7
IB = ______________ = __________________
= 53.34 mA
RB + (1 + b) RE 20 × 103 + 101× 600
Therefore,
IC = bIB = 100 ¥ 53.34 ¥ 10–6
= 5.334 mA
IE = IC + IB = 5.334 ¥ 10 – 3 + 53.34 ¥ 10 – 6
= 5.38734 mA
VCE = VCC – ICRC – IE RE
= 10 – 5.334 ¥ 10 – 3 ¥ 400 – 5.38734 ¥ 10 – 3 ¥ 600 = 4.634 V
The Q point is at VCEQ = 4.634 V and ICQ = 5.334 mA
The collector current for the CE circuit of Fig. 5.2 is given by IC = bIB + (1 +
b) ICO. The three variables in the equation, b, IB and ICO increase with rise in
temperature. In particular, the reverse saturation current or leakage current ICO
changes greatly with temperature. Specifically, it doubles for every 10 °C rise in
temperature. The collector current IC causes the collector–base junction temperature to rise which, in turn, increase ICO, as a result IC will increase still further,
which will further rise the temperature at the collector–base junction. This process will become cumulative leading to “thermal runaway.” Consequently, the
ratings of the transistor are exceeded which may destroy the transistor itself.
The collector is normally made larger in size than the emitter in order to help
dissipate the heat developed at the collector junction.
However, if the circuit is designed such that the base current IB is made to
decrease automatically with rise in temperature, then the decrease in b IB will
compensate for the increase in (1 + b)ICO, keeping IC almost constant.
In power transistors, the heat developed at the collector junction may be removed
by the use of heat sink, which is a metal sheet fitted to the collector and whose
surface radiates heat quickly.
The extent to which the collector current IC is stabilised with varying ICO is
measured by a stability factor S. It is defined as the rate of change of collector
current IC with respect to the collector–base leakage current ICO, keeping both
the current IB and the current gain b constant
∂IC
dIC
DIC
S = _____ ª _____ ª _____, b and IB constant
∂ICO dICO DICO
(5.1)
The collector current for a CE amplifier is given by
IC = b IB + (b + 1)ICO
(5.2)
Differentiating the above equation with respect to IC, we get
dICO
dIB
1 = b ____ + (b + 1) _____
dIC
dIC
Therefore,
(
(b + 1)
dIB
1 – b ____ = ______
S
dIC
)
1+b
S = __________
dIB
1 – b ____
dIC
( )
(5.3)
From this equation, it is clear that this factor S should be as small as possible to
have better thermal stability.
The stability factor S¢ is defined as the rate of
change of IC with VBE, keeping ICO and b constant
∂IC
DIC
S ¢ = _____ ª _____
∂VBE DVBE
The stability factor S ¢¢ is defined as the rate of change of IC with respect to b,
keeping ICO and VBE constant
∂IC DIC
S¢¢ = ___ ª ____
∂b Db
The stability factors for some commonly used biasing circuits are discussed
below.
A common emitter amplifier using fixed bias circuit is shown in Fig. 5.6. The
d.c. analysis of the circuit yields the following equation.
VCC = IBRB + VBE
(5.4)
VCC – VBE
IB = _________
RB
Since this equation is independent of current IC, dIB/dIC = 0 and the stability
factor given in Eq. (5.3) reduces to
S =1+b
Therefore,
Since b is a large quantity, this is a very poor bias stable circuit. Therefore, in
practice, this circuit is not used for biasing the base.
The advantage of this method are: (a) simplicity, (b) small number of components
required, and (c) if the supply voltage is very large as compared to VBE of the transistor, then the base current becomes largely independent of the voltage VBE.
In the fixed bias compensation method shown in Fig. 5.7 a silicon transistor with
= 100 is used. VCC = 6 V, RC = 3 k . RB = 530 k . Draw the d.c. load line and
determine the operating point. What is the stability factor?
IC (mA)
2
Q
1
0
Solution
3
6
VCE (V )
(a) d.c. load line:
VCE = VCC – ICRC
When
When
IC = 0, VCE = VCC = 6 V
VCC
6
VCE = 0, IC = ____ = _______3 = 2 mA
RC
3 × 10
(b) Operating point Q:
For silicon transistor, VBE = 0.7 V
VCC = IBRB + VBE
Therefore,
VCC – VBE
6 – 0.7
IB = _________ = _________3 = 10 mA
RB
530 × 10
Therefore,
IC = bIB = 100 × 10 × 10 – 6 = 1 mA
VCE = VCC – ICRC = 6 – 1 × 10 – 3 × 3 × 103 = 3 V
Therefore operating point is VCEQ = 3 V and ICQ = 1 mA.
(c) Stability factor: S = 1 + b = 1 + 100 = 101
Find the collector current and collector-to-emitter voltage for the given circuit as
shown in Fig. 5.8.
Solution
For a silicon transistor, VBE = 0.7 V
Base current
VCC – VBE
9 – 0.7
IB = _________ = _________3 = 27.67 mA
RB
300 × 10
Collector current IC = bIB = 50 × 27.67 × 10 – 6 = 1.38 mA
Collector-to-emitter voltage
VCE = VCC – ICRC = 9 – 1.38 × 10 – 3 × 2 × 103 = 6.24 V
A germanium transistor having = 100 and VBE = 0.2 V is used in a fixed bias
amplifier circuit where VCC = 16 V, RC = 5 k and RB = 790 k . Determine its
operating point.
VCC = 16 V
RC = 5 k W
RB = 790 kW
b = 100
VBE = 0.2 V
For a germanium transistor, VBE = 0.2 V
Solution
Applying KVL to the base circuit, we have
VCC – IBRB – VBE = 0
Therefore,
VCC – VBE
16 – 0.2
IB = _________ = _________3 = 20 mA
RB
790 × 10
IC = bIB = 100 × 20 mA = 2 mA
Applying KVL to the collector circuit, we have
VCC – ICRC – VCE = 0
VCE = VCC – ICRC = 16 – 2 × 10 – 3 × 5 × 103 = 6 V
Hence, the operating point is IC = 2 mA and VCE = 6 V.
The circuit as shown in Fig. 5.10 has fixed bias using NPN transistor. Determine the
value of base current, collector current and collector to emitter voltage.
[JNTU Sept. 2008]
RB
180 kW
VCC = 25 V
RC
820 W
Vo
b = 80
Applying KVL to the base circuit, we have
Solution
VCC – IBRB – VBE = 0
Therefore,
VCC – VBE
25 – 0.7
IB = _________ = _________3 = 135 mA
RB
180 × 10
IC = bIB = 80 × 135 × 10 – 6 = 10.8 mA
Applying KVL to the collector circuit, we have
VCC – ICRC – VCE = 0
VCE = VCC – ICRC = 25 – 10.8 × 10 – 3 × 820 = 16.144 V
Therefore,
For a fixed bias configuration shown in Fig. 5.6, determine IC, RC, RB and VCE using
the following specifications: VCC = 12 V, VC = 6 V, = 80 and IB = 40 A.
[JNTU May 2008]
Solution
Assume VBE = 0.7 V for a silicon transistor.
IC = bIB = 80 × 40 mA = 3.2 mA
VCC – VC
12 – 6
RC = _________ = _________
= 1.875 kW
IC
3.2 × 10 – 3
VCC – VBE
12 – 0.7
RB = _________ = _________
= 282.5 kW
IB
40 × 10 – 6
Since emitter is grounded, VE = 0.
VCE = VC = 6 V
The emitter-feedback bias network shown in Fig. 5.11 contains an emitter resistor for improving the stability level over that of the fixed-bias configuration.
The analysis will be performed by first examining the base-emitter loop and then
using the results to investigate the collector-emitter loop.
Applying Kirchhoff’s voltage law for the base-feedback
emitter loop, we get
VCC – IBRB – VBE – IERE = 0
(5.5)
VCC – IBRB – VBE – (IB + IC) RE = 0
VCC – IB (RB + RE) – VBE – ICRE = 0
VCC – VBE = IB (RB + RE) + ICRE
VCC – VBE
RE
IB = _________ – ________ IC
RE + RB
RE + RB
(
Therefore,
)
(5.6)
Here VBE is independent of IC.
(
dIB
RE
____
= – ________
RE + RB
dIC
Hence,
)
(5.7)
Substituting Eq. (5.7) in Eq. (5.3), we get the stability factor as
1+b
S = ____________
RE
1+ b ________
RE + RB
(5.8)
bRE
Since 1 + _________ > 1, S < (1 + b). Note that the value of the stability factor
(RE + RB)
S is always lower in emitter-feedback bias circuit than that of the fixed bias circuit. Hence it is clear that a better thermal stability can be achieved in emitterfeedback bias circuit than the fixed-bias circuit.
emitter loop, we get
IE RE + VCE + IC RC – VCC = 0
Substituting IE = IC , we have
VCE – VCC + IC (RC + RE) = 0
and
VCE = VCC – IC (RC + RE)
(5.9)
VE is the voltage from emitter to ground and is determined by
VE = IERE
(5.10)
The voltage from collector to ground can be determined from
VCE = VC – VE
and
VC = VCE + VE
(5.11)
or
VC = VCC – ICRC
(5.12)
The voltage at the base with respect to ground can be determined from
or
VB = VCC – IBRE
(5.13)
VB = VBE + VE
(5.14)
For the emitter-feedback bias circuit, VCC = + 10 V, RC = 1.5 k , RB = 270 k and
RE = 1 k . Assuming = 50, determine (a) Stability factor, S (b) IB (c) IC (d) VCE
(e) VC (f) VE (g) VB and (h) VBC.
Solution
(a) The stability factor is
1+b
1 + 50
S = _____________ = _____________________
bR
(50 × 1 × 103)
E
1 + _________ 1 + _________________
(RE + RB)
1 × 103 + 270 × 103
51
51
= _________ = _____ = 43.04
1 + 0.185 1.185
VCC – VBE
10 – 0.7
9.3
(b) IB = ______________ = _____________________
= ____ = 28.97 mA
RB + (b + 1) RE 27 × 103 + (51) (1 × 103) 321
IC = bIB = (50) (28.97 × 10 – 6) = 1.45 mA
(c)
(d)
VCE = VCC – IC (RC + RE)
= 10 – 1.45 × 10 – 3 (1.5 × 103 + 1 × 103) = 10 – 3.62 = 6.38 V
(e)
VC = VCC – ICRC = 10 – 1.45 × 10 – 3 (1.5 × 103) = 7.825 V
(f)
VE = VC – VCE = 7.825 – 6.38 = 1.445 V
or
(g)
(h)
VE = IERE = ICRE = 1.45 × 10 – 3 × 1 × 103 = 1.45 V
VB = VBE + VE = 0.7 + 1.45 = 2.15 V
VBC = VB – VC = 2.15 – 7.825 = |5.675| V
(reverse bias as required)
Calculate d.c. bias voltage and currents in the circuit in Fig. 5.12. Neglect VBE of
transistor.
[JNTU June 2009]
Solution
Given: VCC = 20 V; RB = 400 kW, b = 100, RE = 1 kW; RC = 2 kW
IBRB + VBE + IERE = VCC
IC
__
R + 0 + (IC + IB) RE = 20
b B
[
]
RB
RE
IC ___ + RE + ___ = 20
b
b
Therefore,
20
IC = _______________________
= 4 mA
3
400 × 10
_________
+ 1 × 103 + 10
100
[
]
IC 4 × 10 – 3
IB = __ = ________ = 0.4 mA
100
b
VB = VBE + IERE
= 0 + 4 × 10 – 3 × 1 × 103 = 4 V, since IC ª IE
A common emitter amplifier using collector-to-base bias circuit is shown in Fig.
5.13. This circuit is the simplest way to provide some degree of stabilization to
the amplifier operating point.
If the collector current IC tends to increase due to either increase in temperature or the transistor has been replaced by the one with a higher b, the voltage drop across RC increases, thereby reducing the value or VCE. Therefore, IB
decreases which, in turn, compensates the increase in IC. Thus, greater stability
is obtained.
The loop equation for this circuit is
VCC = (IB + IC) RC + IBRB + VBE
VCC – VBE – ICRC
IB = ________________
RC + RB
i.e.
Therefore,
RC
dIB
____
= – ________
RC + RB
dIC
(5.15)
(5.16)
(5.17)
Substituting Eq. (5.17) into Eq. (5.3), we get
1+b
S = _______________
RC
1 + b ________
RC + RB
(
)
(5.18)
As can be seen, this value of the stability factor is smaller than the value obtained
by fixed bias circuit. Also, S can be made small and the stability can be improved
by making RB small or RC large.
If RC is very small, then S = (b + 1), i.e. stability is very poor. Hence, the value
of RC must be quite large for good stabilization. Thus, collector-to-base bias
arrangement is not satisfactory for the amplifier circuits like transformer coupled amplifier where the d.c. load resistance in collector circuit is very small. For
such amplifiers, emitter bias or self bias will be the most satisfactory transistor
biasing for stabilization.
In the biasing with feedback resistor method, a silicon transistor with feedback resistor is used. The operating point is at 7 V, 1 mA and VCC = 12 V. Assume = 100.
Determine (a) the value of RB, (b) stability factor, and (c) what will be the new operating point if = 50 with all other circuit values are same.
Solution Refer to Fig. 5.6. We know that for a silicon transistor, VBE = 0.7 V.
(a) To determine RB :
The operating point is at VCE = 7 V and IC = 1 mA
VCC – VCE
12 – 7
RC = __________ = ________
= 5 kW
IC
1 × 10 – 3
Here,
IC 1 × 10 – 3
IB = __ = ________ = 10 mA
100
b
Using the relation,
VCC – VBE – ICRC 12 – 0.7 – 1 × 10 – 3 × 5 × 103
RB = ________________ = _________________________
= 630 kW
IB
10 × 10 – 6
(b) Stability factor,
1+b
S = ______________
RC
1 + b ________
RC + RB
[
]
1 + 100
= ______________________
= 56.5
5 × 103
_____________
1 + 100
(5 + 630) × 103
[
]
(c) To determine new operating point when b = 50
VCC = bIBRC + IBRB + VBE
= IB (bRC + RB) + VBE
12 = IB (50 × 5 × 103 + 630 × 103) + 0.7
i.e.
11.3
IB = _________3 = 12.84 mA
880 × 10
IC = bIB = 50 × 12.84 × 10 – 6 = 0.642 mA
Therefore,
VCE = VCC – ICRC = 12 – 0.642 × 10 – 3 × 5 × 103 = 8.79 V
Therefore, the coordinates of the new operating point are
VCEQ = 8.79 V and ICQ = 0.642 mA.
An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and
RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to
base. Find the quiescent point and stability factor.
[JNTU May 2003, 2004, 2005 & 2006 Nov. 2010]
Solution
Given
VCC = 10 V, RC = 2 kW,
b = 50 and collector to base resistor RB = 100 kW
To determine the quiescent point: We know that for the collector to base bias
transistor circuit,
VCC = bIBRC + IBRB + VBE
Therefore,
VCC – VBE
IB = __________
RB + b ◊ RC
10 – 0.7
= _______________________
= 46.5 mA
100 × 103 + 50 × 2 × 10 – 3
Hence,
IC = b ◊ IB = 50 × 46.5 × 10 – 6 = 2.325 mA
VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V
Therefore, the co-ordinates of the new operating point are
VCEQ = 5.35 V and ICQ = 2.325 mA
To find the stability factor S:
1+b
S = ______________
RC
1 + b ________
RC + RB
[
]
1 + 50
= _________________________
= 25.75
2 × 103
1 + 50 _________________
2 × 103 + 100 × 103
[
]
In a collector to base CE amplifier circuit of Fig. 5.6 having VCC = 12 V, RC = 250
k , IB = 0.25 mA, = 100 and VCEQ = 8 V, calculate RB and stability factor.
Solution
Stability factor,
VCEQ
8
RB = _____ = __________
= 32 kW
IB
0.25 × 10 – 3
1+b
101
S = _______________ = _________________ = 56.9
RC
250
1 + 100 ________
1 + b ________
32 + 250
RC + RB
(
)
(
)
Calculate the quiescent current and voltage of collector to base bias arrangement
using the following data: VCC = 10 V, RB = 100 k , RC = 2 k , = 50 and also
specify a value of RB so that VCE = 7 V.
[JNTU May 2008]
Solution
(a) Applying KVL to the base circuit, we have
VCC – IB (1 + b) RC – IB RB – VBE = 0
VCC – VBE
10 – 0.7
Therefore, IB = ______________ = __________________________
= 46 mA
RB + (1 + b) RC 100 × 103 + (1 + 50) × 2 × 103
IC = bIB = 50 × 46 mA = 2.3 mA
Applying KVL to the collector circuit, we have
VCC – (IB + IC) RC – VCE = 0
Therefore,
VCE = VCC – (IB + IC) RC
= 10 – (46 × 10 – 6 + 2.3 × 10 – 3) × 2 × 103 = 5.308 V
VCC = 10 V
RB = 100 KW IC + IB
IB
RC = 2 KW
b = 50
Quiescent current, ICQ = 2.3 mA and
Quiescent voltage,VCEQ = 5.308 V
(b) Given
VCE = 7 V
(IB + IC) RC = VCC – VCE
(1 + b) IBRC = VCC – VCE
We have,
VCC – VCE
10 – 7
IB = __________ = ________________3 = 29.41 mA
(1 + b) RC (1 + 50) × 2 × 10
VCC = IBRB + VBE
VCE – VBE
7 – 0.7
RB = _________ = ___________
= 214.2 kW
IB
29.41 × 10 – 6
Figure 5.15 shows the collector-emitter feedback bias circuit that can be obtained
by applying both the collector-feedback and emitter-feedback. Here collectorfeedback is provided by connecting a resistance RB from the collector to the base
and emitter-feedback is provided by connection an emitter resistance RE from
the emitter to ground. Both the feedbacks are used to control the collector current IC and the base current IB in the opposite direction to increase the stability
as compared to the previous biasing circuits.
Applying Kirchhoff’s voltage law to the current, we get
(IB + IC) RE + VBE + IBRB + (IB + IC) RC – VCC = 0
Therefore,
(
)
VCC – VBE
RE + RC
IB = _____________ – _____________ IC
RE + RC + RB
RE + RC + RB
Since VBE is independent of IC,
(
RE + RC
dIB
____
= – _____________
RE + RC + RB
dIC
)
Substituting the above equation in Eq. (5.3), we get
1+b
S = ________________
b (RE + RC)
1 + _____________
RE + RC + RB
(5.19)
From this, it is clear that the stability of the collector-emitter feedback bias circuit is always better than that of the collector-feedback and emitter feedback
circuits.
A simple circuit used to establish a stable operating point is the self biasing
configuration. The self bias, also called as emitter bias, or emitter resistor and
potential divider circuit, that can be used for low collector resistance, is shown
in Fig. 5.16. The current in the emitter resistor RE causes a voltage drop which is
in the direction to reverse bias the emitter junction. For the transistor to remain
in the active region, the base-emitter junction has to be forward biased. The
required base bias is obtained from the power supply through the potential
divider network of the resistance R1 and R2.
If IC tends to increase,
say, due to increase in ICO with temperature, the current in RE increases. Hence,
the voltage drop across RE increases thereby decreasing the base current. As a
result, IC is maintained almost constant.
Applying Thevenin’s Theorem to the circuit of Fig. 5.16, for finding the base current, we have,
R2 VCC
VT = _______
R1 + R2
R1R2
and RB = _______
R1 + R2
The loop equation around the base circuit can be written as
VT = IBRB + VBE + (IB + IC) RE
Differentiating this equation with respect to IC, we get
RE
dIB
____
= – ________
RE + RB
dIC
Substituting this equation in Eq. (5.3), we get
1+b
S = ______________
RE
1 + b ________
RE + RB
(
Therefore,
)
RB
1 + ___
RE
S = (1 + b) __________
RB
1 + b + ___
RE
(5.20)
As can be seen, the value of S is equal to one if the ratio RB /RE is very small as
compared to 1. As this ratio becomes comparable to unity, and beyond towards
infinity, the value of the stability factor goes on increasing till S = 1 + b.
This improvement in the stability up to a factor equal to 1 is achieved at the cost
of power dissipation. To improve the stability, the equivalent resistance RB must
be decreased, forcing more current in the voltage divider network of R1 and R2.
Often, to prevent the loss of gain due to the negative feedback, RE is shunted by
a capacitor CE. The capacitive reactance XCE must be equal to about one-tenth
of the value of the resistance RE at the lowest operating frequency.
The stability factor S¢ is defined as the
rate of change of IC with VBE, keeping ICO and b constant.
∂IC
DIC
S ¢ = _____ = _____
∂VBE DVBE
From Fig. 5.16 (b),
VT = IBRB + VBE + IERE
= IB [RB + RE] + ICRE + VBE since [IE = IB + IC] (5.21)
We have
IC – (1 + b) ICO
IB = ______________
b
(5.22)
Substituting Eq. (5.21) in Eq. (5.22), we get
IC
ICO
VT = __ (RB + RE) + VBE + ICRE + ____ (1 + b) {RB + RE}
b
b
(5.23)
Differentiating the above equation w.r.t. VBE we get
dIC RB + RE
dIC
0 = _____ ________ + 1 + RE _____ + 0
dVBE
dVBE
b
(
[
)
dIC
RB + RE
– 1 = _____ RE + ________
dVBE
b
[
]
dIC RB + (1 + b) RE
– 1 = _____ ______________
dVBE
b
Therefore,
]
dIC
–b
S ¢ = _____ = ______________
dVBE RB + (1 + b) RE
(5.24)
The stability factor S¢¢ is defined as the rate
of change of IC w.r.t. to b, keeping ICO and VBE constant.
Rearranging Eq. (5.23), we have
IC
( )
1+b
b _____ ICO (RB + RE)
b
b (VT – VBE)
= ______________ + _____________________
RB + (1 + b) RE
RB + (1 + b) RE
(5.25)
Since b >> 1, the numerator of the second term can be written as
( )
1+b
(RB + RE) _____ ICO = (RB + RE) ICO
b
(5.26)
Substituting Eq. 5.26 in Eq. 5.25, we have
b (RB + RE) ICO
b (VT – VBE)
IC = ______________ + ______________
RE + (1 + b) RE RB + (1 + b) RE
Therefore,
b [VT – VBE + (RB + RE) ICO]
IC = _________________________
RB + (1 + b) RE
Let,
V ¢ = (RB + RE) ICO.
b [VT – VBE + V ¢]
IC = _______________
RB + (1 + b) RE
Differenting the above equation w.r.t. b and simplifying, we obtain
Therefore,
dIC
IC
SIC
S≤ = ___ = _________________ = ________
db
b
(1
+ b)
R
E
b 1 + b ________
RE + RB
[ (
)]
(5.27)
(5.28)
In a CE gtermanium transistor amplifier circuit, the bias is provided by self bias, i.e.
emitter resistor and potential divider arrangement (refer to Fig. 5.7). The various
parameters are: VCC = 16 V, RC = 3 k , RE = 2 k , R1 = 56 k , R2 = 20 k and
= 0.985. Determine (a) the coordinates of the operating point, and (b) the stability
factor S.
Solution
For a germanium transistor, VBE = 0.3 V. As a = 0.985,
a
0.985
b = _____ = ________ = 66
1 – a 1 – 0.985
(a) To find the coordinates of the operating point
Referring to Fig. 5.16, we have
R2
Thevenin’s voltage, VT = _______ VCC
R1 + R2
20 × 103
= ________
× 16 = 4.21 V
76 × 103
R1R2
20 × 103 × 56 × 103
Thevenin’s resistance, RB = _______ = _________________
R1 + R2
76 × 103
= 14.737 kW
The loop equation around the base circuit is
VT = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= __ RB + VBE + __ + IC RE
b
b
IC
1
4.21 = ___ × 14.737 × 103 + 0.3 + IC ___ + 1 × 2 × 103
66
66
(
)
3.91 = IC [0.223 + 2.03] × 103
3.91
Therefore,
IC = __________3 = 1.73 mA
2.253 × 10
Since IB is very small, IC ª IE = 1.73 mA
Therefore,
VCE = VCC – ICRC – IERE
= VCC – IC [RC + RE] = 16 – 1.73 × 10 – 3 × 5 × 103
= 7.35 V
Therefore, the coordinates of the operating point are IC = 1.73 mA and
VCE = 7.35 V.
(b) To find the stability factor S,
RB
1 + ___
RE
S = (1 + b) __________
RB
1 + b + ___
RE
14.737
1 + _______
2
______________
= (1 + 66)
14.737
______
1 + 66 +
2
8.3685
= 67 × _______ = 7.537
74.3685
Consider the self-bias circuit where VCC = 22.5 Volts, RC = 5.6 k , R2 = 10 k
and R1 = 90 k , hfe = 55, VBE = 0.6 V. The transistor operates in active region.
Determine (a) operating point, and (b) stability factor.
[JNTU June 2009]
So lution
For the given circuit, VBE = 0.6 V, hfe = 55
(a) To determine the operating point:
Rz
10 × 103
Thevenin’s voltage, VT = _______ VCC = _________3 × 22.5 = 2.25 V
R1 + R2
100 × 10
R1R2
10 × 103 × 90 × 103
Thevenin’s resistance, RB = _______ = _________________
= 9 kW
R1 + R2
100 × 103
The loop equation around the base circuit is
VB = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= ___ RB + VBE + ___ + IC RE
hfe
hfe
IC
1
2.25 = ___ × 9 × 103 + 0.6 + ___ + 1 IC × 1 × 103
55
55
(
)
2.25 = IC × 0.16 × 103 + 0.6 + 1.01 × IC × 103
2.25 = IC × 1.17 × 103 + 0.6
Therefore,
2.25 – 0.6
IC = _________3 = 1.41 mA
1.17 × 10
Since IB is very small, IC ª IE = 1.41 mA
Therefore,
VCE = VCC – ICRC – IERE =VCC – IC (RC + RE)
= 22.5 – 1.41 × 10 – 3 × 6.6 × 103 = 13.19 V
Operating point coordinates are VCE = 13.19 V and IC = 1.41 mA
(b) To find the stability factor, S
RB
9 × 103
1 + _______3
1 + ___
RE
1 × 10
56 × 10 560
S = (1 + b) __________ = (1 + 55) _______________
= _______ = ____ = 8.6
3
R
65
65
B
9
×
10
1 + b + ___
1 + 55 + _______3
RE
1 × 10
Figure 5.17 shows that d.c. bias circuit of a common emitter transistor amplifier.
Find the percentage change in collector current, if the transistor with hfe = 50 is
replaced by another transistor with hfe = 150. It is given that the base emitter drop
VBE = 0.6 V.
[JNTU June 2009]
+12 V
R1
25 kW
RC
1 kW
VT = VB
R2
5 kW
RE
100 W
Solution
(a) For the given circuit, VBE = 0.6 V, hfe = 50
Thevenin’s voltage,
R2
5 × 103
VT = ________ VCC = ________3 × 12 = 2 V
R1 + R2
30 × 10
R1R2
25 × 103 × 5 × 103
Thevenin’s resistance, RB = _______ = ________________
= 4.16 kW
R1 + R2
30 × 103
The loop equation around the base circuit is
VT = VB = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= ___ RB + VBE + ___ + IC RE
hfe
hfe
IC
1
2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103
50
50
(
)
2 – 0.6 = IC × (0.08 + 0.102) × 103
Therefore,
14
IC = __________3 = 7.69 mA
0.182 × 10
(b) For the given circuit,VBE = 0.6 V, hfe = 150
The loop equation around the base circuit is
VB = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= ___ RB + VBE + ___ + IC RE
hfe
hfe
IC
1
2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103
50
50
(
2 – 0.6 = IC × (0.028 + 0.1) × 103
Therefore,
1.4
IC = __________3 = 10.93 mA
0.128 × 10
10.93 – 7.69
Change in collector current = ___________ = 0.42 i.e. 42%
7.69
There is 42% change in IC when hfe changes from 50 to 150.
)
If the various parameters of a CE amplifier which uses the self-bias method are
VCC = 12 V, R1 = 10 k , R2 = 5 k , RC = 1 k , RE = 2 k and = 100, find
(a) the coordinates of the operating point and
(b) the stability factor, assuming the transistor to be silicon.
[JNTU 2008]
Solution
(a) To find the coordinates of the operating point
Refer to Fig. 5.16.
Thevenin’s voltage,
R2
5 × 103
VT = _______ VCC = ________3 × 12 = 4 V
R1 + R2
15 × 10
Thevenin’s resistance,
R1R2
5 × 103 × 10 × 103
RB = _________ = ________________
= 3.33 kW
(R1 + R2)
15 × 103
The loop equation around the basic circuit is
VT = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= __ RB + VBE + __ + IC RE
b
b
IC
1
4 = ____ × 3.33 × 103 + 0.7 + IC ____ + 1 × 2 × 103
100
100
(
)
3.3 = (33.3 + 2020) IC
3.3
IC = ______ = 1.61 mA
2053.3
Since IB is very small, IC ª IE = 1.61 mA
Therefore,
VCE = VCC – ICRC – IERE
= VCC – IC [RC + RE] = 12 – 1.61 × 10 – 3 × 3 × 103
= 7.17 V
Therefore, the coordinates of the operating point are IC = 1.61 mA and
VCE = 7.17 V.
(b) To find the stability factor S:
RB
3.33 × 103
1 + _________
1 + ___
RE
2 × 103
S = (1 + b) __________ = (1 + 100) ___________________
= 2.6
RB
3.33 × 103
___
_________
1+b+
1 + 100 +
RE
2 × 103
Determine the quiescent current and collector to emitter voltage for a germanium
transistor with = 50 in self biasing arrangement. Draw the circuit with a given
component value with VCC = 20 V, RC = 2 k , RE = 100 , R1 = 100 k and R2 =
5 k . Also find the stability factor.
For a germanium transistor, VBE = 0.3 V and b = 50
Solution
To find the coordinates of the operating point:
Thevenin’s voltage,
R2
VT = _______ VCC
R1 + R2
5 × 103
= _________3 × 20 = 0.95 V
105 × 10
Thevenin’s resistance,
R1R2
100 × 103 × 5 × 103
RB = _______ = _________________
= 4.76 kW
R1 + R2
105 × 103
The loop equation around the base circuit is
VT = IBRB + VBE + (IB + IC) RE
(
)
IC
IC
= __ RB + VBE + __ + IC RE
b
b
IC
51
0.95 = ___ × 4.76 × 103 + 0.3 + IC × ___ × 100
50
50
0.65 = 197.2 IC
Therefore,
0.65
IC = _____ = 3.296 mA
197.2
Since IB is very small,
IC = ª IE = 3.296 mA
Therefore,
VCE = VCC – ICRC – IERE
= VCC – IC (RC + RE)
= 20 – 3.296 × 10 – 3 × 2.01 × 103 = 13.375 V
Therefore, the coordinates of the operating point are IC = 3.296 mA and
VCE = 13.375 V.
To find the stability factor S:
RB
4.76 × 103
_________
1 + ___
1
+
RE
100
S = (1 + b) __________ = (1 + 50) __________________
= 25.18
R
B
4.76 × 103
1 + b + ___
1 + 50 + _________
RE
100
A germanium transistor is used in a self-biasing circuit configuration as shown below
with VCC = 16 V, RC = 1.5 k and = 50. The operating point desired is VCE = 8V
and IC = 4 mA. If a stability factor S = 10 is desired, calculate the values of R1 and
R2 and RE of the circuit (Fig. 5.18).
[JNTU May 2006]
VCC = 16 V
IC = 4 mA
RC = 1.5 kW
R1
C
VCE = 8 V
B
E
R2
RE
IE
Solution
To determine RE :
We know that,
VCC = VCE + IC (RC + RE)
16 = 8 + 4 × 10 – 3 (1.5 × 103 + RE)
Therefore,
RE = 500 W
To determine RTH:
Given
Stability factor
Upon solving, we get
S = 10
1+b
1 + 50
S = ______________ = _________________
R
500
E
__________
1 + b _________ 1 + 50 R + 500
RTH + RE
TH
(
RTH = 5.58 kW
To determine R2:
R2 = 0.1 b RE = 27.98 kW
To determine R1:
We know that,
R1R2
RTH = R1||R2 = _______
R1 + R2
R1 × 27.98 × 103
5.58 × 103 = _______________3
R1 + 27.98 × 10
Therefore,
R1 = 6.97 kW
)
A CE transistor amplifier with voltage divider bias circuit of Fig. 5.16 is designed to
establish the quiescent point at VCE = 12 V, IC = 2 mA and stability factor 5.1. If
VCC = 24 V, VBE = 0.7 V, = 50 and RC = 4.7 k , determine the values of resistors
RE, R1 and R2.
Solution
(a) To determine RE:
VCE = VCC – ICRC – IERE
= VCC – IC [RC + RE], since IC ª IE
12 = 24 – 2 × 10 – 3 [4.7 × 103 + RE]
Therefore,
RE = 1.3 kW
(b) To determine R1 and R2:
Stability factor,
R1R2
1+b
S = _______________, where RB = _________
RE
(R1 + R2)
1 + b ________
RE + RB
(
)
51
5.1 = _____________________
1.3 × 103
1 + 50 _____________
1.3 × 103 + RB
(
(
)
)
i.e.
1.3 × 103
51
1 + 50 _____________
= ___ = 10
3
5.1
1.3 × 10 + RB
Therefore,
(
)
50 × 1.3 × 103
_____________
=9
1.3 × 103 + RB
50 × 1.3 × 103
1.3 × 103 + RB = _____________ = 7.2 kW
9
RB = 5.9 kW
Also, we know that for a good voltage divider, the value of resistor R2 = 0.1
bRE
Therefore,
R2 = 0.1 × 50 × 1.3 × 103 = 6.5 kW
R1R2
RB = _______
R1 + R2
R1 × 6.5 × 103
5.9 × 103 = _____________3
R1 + 6.5 × 10
Simplifying, we get
R1 = 64 kW
In the circuit shown in Fig. 5.19, if IC = 2 mA and VCE = 3 V, calculate R1 and R3.
(Refer to Fig. 5.19)
[JNTU May 2008]
+ VCC = 15 V
I + IB
IC
R1
R3
b = 100
IB
VBE (ac1) = 0.5 V
VBE
R2
10 kW
R4 = 500 W
Solution
Given: b = 100, IC = 2 mA, VCE = 3 V, VBE = 0.6 V, R2 = 10 kW
and R4 = 500 W
IC
We know that
b = __
IB
Hence,
IC 2 × 10 – 3
IB = __ = ________ = 20 mA
100
b
VCC = ICR3 + VCE + IER4
IE = IC + IB = 20 × 10 – 6 + 2 × 10 – 3 = 2.02 mA
Substituting the values, we get
15 = 2 × 10 – 3 × R3 + 3 × 2.02 × 10 –3 × 500
Therefore,
R3 = 5.495 kW
VB = VBE + IER4 = 0.6 + 2.02 × 10 – 3 × 500 = 1.61
From the circuit,
R2VCC
VB = _______
R1 + R2
10 × 103 × 15
1.61 = ____________3
R1 + 10 × 10
Therefore,
R1 = 83.17 kW
Given a voltage divider bias circuit shown in Fig. 5.20, determine the Q point. Let
R1 = 56 kW, R2 = 12.2 kW, RC = 2 kW, RE = 400 W, VCC = 10 V, VBE (on) = 0.7 V
and b = 150.
Solution From the Thevenin equivalent circuit shown in Fig. 5.20(b), we get
RTH = R1||R2 = 56 kW||12.2 kW = 10 kW
(
)
R2
12.2
VTH = _______ VCC = _________ × 10 = 1.79 V
R1 + R2
56 + 12.2
With the help of Kirchhoff’s voltage law equation, we get
VTH – VBE (on)
1.79 – 0.7
IBQ = _______________ = _____________ = 15.5 mA
RTH + (1 + b) RE 10 + 151 × 0.4
Therefore, ICQ = bIBQ = 150 × 15.5 × 10– 6 = 2.32 mA
IEQ = IBQ + ICQ = 15.5 mA + 2.32 mA = 2.336 mA
VCEQ = VCC – ICQ RC – IEQ RE
= 10 – 2.32 × 10– 3 × 2 × 103 – 2.336 × 10– 3 × 400
= 4.426 V
The quiescent point is at VCEQ = 4.426 V and ICQ = 2.32 mA
For a circuit shown in Fig. 5.21 VCC = 22 V, RC = 2 kW, b = 60, VBE active = 0.6 V,
R1 = 100 kW. Calculate IB, VCE , IC and stability factor S.
Solution For the given circuit
VCC = R1[I1 + IB] + I1R2
VCC – IB R1
I1 = __________
R1 + R2
(1)
Further VCC = R1[I1 + IB] + VBE + IE RE
As
IE = IC + IB
= bIB + IB = (1 + b) IB
Hence
VCC = R1[I1 + IB] + VBE + (1 + b) IB RE
Substituting for I1 from Eq. (1), we get
[
[
]
VCC – IB R1
VCC = R1 __________ + IB + VBE + (1 + b) IB RE
R1 + R2
]
VCC + IB R2
VCC = R1 ___________ + VBE + (1 + b) IB RE
R1 + R2
Substituting for VCC , R1 , R2, VBE , b and RE
[
]
22 + IB × 5 × 103
22 = 100 × 103 _______________ + 0.6 + (1 + 60) IB × 100
(100 + 5) × 103
22 = 0.952 [22 + IB × 5 × 103] + 0.6 + 6100 IB
22 = 20.944 + 11,100 IB + 0.6
IB = 41.08 mA
IC = bIB = 60 × 41.08 × 10– 6 = 246 mA
Applying KVL to collector circuit, we get
VCC = IC RC + VCE + IE RE + IC RC + VCE + (1 + b) IB RE
Hence
VCE = VCC – IC RC – (1 + b) IB RE
= 22 – (2.46) × 10– 3 × 2 × 103 – (61) (41.08 × 10– 6) (100)
= 22 – 4.92 – 0.25 = 16.83 V
To find stability factor, (S):
Stability factor for voltage divider bias is
1+b
S = ______________, where RB = R1||R2
RE
1 + b ________
RE + RB
(
)
1 + 60
S = ________________________________
100
________________________
1 + 60
100 × 103 × 5 × 103
100 + _________________
(100 + 5) × 103
(
))
(
61
= ___________________
100
1 + 60 ____________
100 + 4761.9
(
)
61
= _____ = 27.3
2.234
An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and
RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to
base. Find the quiescent point and stability factor.
Solution
Given
VCC = 10 V, RC = 2 kW,
b = 50 and collector to base resistor, RB = 100 kW
To determine the quiescent point:
We know that the collector to base bias transistor circuit
VCC = bIBRC + IBRB + VBE
Therefore,
VCC – VBE
IB = __________
RB + b ◊ RC
10 – 0.7
= ______________________
= 46.5 mA
100 × 103 + 50 × 2 × 10+3
Hence,
IC = bIB = 50 × 46.5 × 10 – 6 = 2.325 mA
VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V
Therefore, the co-ordinates of the new operating point are
VCEQ = 5.35 V and ICQ = 2.325 mA
To find the stability factor S:
1+b
S = ______________
RC
1 + b ________
RC + RB
[
]
1 + 50
= _________________________
= 25.75
2 × 103
1 + 50 _________________
2 × 103 + 100 × 103
[
]
Design a voltage divider bias network using a supply of 24 V, = 110 and ICQ = 4
mA VCEQ = 8 V. Choose VE = VCC / 8.
JNTU May 2008]
Solution
Given: ICQ= 4 mA, VCEQ = 8 V, VE = VCC / 8, VCC = 24 V, b = 110
(a) To determine IB, IE and VE :
ICQ 4 × 103
IB = ____ = _______ = 36.36 mA
110
b
IE = IB + IC = 36.36 × 10 – 6 + 4 × 10 – 3 = 4.03636 mA
VCC 24
VE = ____ = ___ = 3 V
8
8
(b) To determine RE and R2:
VE
0.3
RE = ___ = _____________
= 743.244 W
IE 4.03636 × 10 – 3
Applying KVL to the collector circuit,
VCC – ICRC – VCE – VE = 0
Therefore,
VCC – VCE – VE 24 – 8 – 3
RC = ______________ = _________
= 3.25 kW
IC
4 × 10 – 3
(c) To determine R1 and R2
VB = VE + VBE = 3 + 0.7 = 3.7 V
Referring to Fig. 5.16, consider the current through R1 be I + IB and that through
R2 be I. Resistors R1 and R2 forms the potential divider. For proper operation
of potential divider, current I should be atleast ten times the IB. i.e. I ≥ 10 IB.
Therefore,
I = 10 IB = 10 × 36.36 × 10 – 6 = 363.6 mA
VB
3.7
R2 = ___ = ___________
= 10.176 kW
I
363.6 × 10 – 6
VCC – VB
24 – 3.7
R1 = _________ = ____________________
= 50.755 kW
I + IB
(363.6 + 36.36) × 10 – 6
Determine the stability factor for the circuit shown in Fig. 5.22.
[JNTU June 2009]
VCC
( I C + I 1)
RC
R1
I1
IB
R2
I2
IC
(IC + IB)
RE
Solution
VBE + (IC + IB) RE
I2 = ________________
R2
I1 = IB + I2
Therefore,
VBE + (IC + IB) RE
I1 = IB + ________________
R2
IBR2 + VBE + (IC + IB) RE
= _______________________
R2
Applying KVL to the collector, base-emitter loop, we have
VCC = (IC + I1) RC – I1R1 – VBE – (IC + IB) RE
= (IC + I1) RC + I1R1 + VBE + (IC + IB) RE
= ICRC + I1RC + I1R1 + VBE + ICRE + IBRE
= IC (RC + RE) + I1 (RC + R1) + VBE + IBRE
Substituting the value of I1 from the equation determined above, we get
IBR2 + VBE + (IC + IB) RE
VCC = IC (RC + RE) + _______________________ (RC + R1) + VBE + IBRE
R2
[
] [
(RC + R1)
(RE + R2) (RC + R1)
= IC RC + RE + _________ + IB RE + __________________
R2
R2
]
[
]
(RC + R1)
+ 1 + _________ VBE
R2
We know that IC = bIB + (1 + b) ICO
IC – (1 + b) ICO
IB = ______________
b
Therefore,
Substituting the value of IB, we get
[
]
RE (RC + R1)
IC – (1 + b) ICO
VCC = IC RC + RE + ____________ + ______________ ×
R2
b
[
] [
]
(RE + R2) (RC + R1)
(RC + R1)
RE + __________________ + 1 + _________ VBE
R2
R2
dIC
We know that S = _____. Hence, differentiating the above equation and assumdICO
ing VBE constant, we get
∂IC
RE (RC + R1)
∂IC
(RE + R2) (RC + R1)
1
0 = _____ RC + RE + ____________ + _____ × __ RE + __________________
R2
R2
∂ICO
∂ICO b
[
]
[
[
(RE + R2) (RC + R1)
(1 + b)
– ______ RE + __________________
R2
b
]
∂IC R2RC + R2RE + RERC + RER1
∂IC
1
= _____ __________________________ + _____ × __ ×
R2
∂ICO
∂ICO b
[
[
]
R2RE + RERC + RER1 + R2RC + R1R2
_________________________________
R2
[
]
1 + b R2 (RC + R1) + RE (R1 + R2 + RC)
– _____ _____________________________
R2
b
]
]
∂IC R2RC + RE (R1 + R2 + RC)
∂IC
1
= _____ _______________________ + _____ × __ ×
R2
∂ICO
∂ICO b
[
[
]
R2 (RC + R1) + RE (R1 + R2 + RC)
_____________________________
R2
[
]
1 + b R2 (RC + R1) + RE (R1 + R2 + RC)
– _____ _____________________________
R2
b
]
∂IC R2RC + RE (R1 + R2 + RC)
R2 (RC + R1) + RE (R1 + R2 + RC)
= _____ _______________________ + _____________________________
R2
bR2
∂ICO
[
] [
]
1+b
_____
[R2 (RC + R1) + RE (R1 + R2 + RC)]
∂IC _______________________________________________________
b
_____
=
R2 (RC + R1) + RE (R1 + R2 + RC)
∂ICO
R2RC + RE (R1 + R2 + RC) + _____________________________
b
1+b
_____
[R2 (RC + R1) + RE (R1 + R2 + RC)]
b
________________________________________________________
=
b(R2RC + RE (R1 + R2 + RC)) + R2 (RC + R1) + RE (R1 + R2 + RC)
________________________________________________________
b
∂IC
(1 + b) [R2 (RC + R1) + RE (R1 + R2 + RC)]
Stability factor, S = _____ = _____________________________________
∂ICO R1R2 + (b + 1) [R2RC + RE (R1 + R2 + RC)]
In a common base amplifier circuit, the equation for collector current IC is given
by
IC = aIE + ICO
dIC
S ª _____ = 1
dICO
Since this is highly stable, the common base amplifier circuit is not in need of
bias stabilization.
In fixed bias method discussed in Section 5.3.1, the stability factor is given by
S =1+b
Since b is normally a large quantity, this circuit provides very poor stability.
Therefore, the fixed biasing technique is not preferred for biasing the base.
In collector-to-base bias method, when RC is very small, S ª 1 + b, which is equal
to that of fixed bias. Hence, collector-to-base bias method is also not preferable.
RB
In self bias method discussed in Section 5.3.5, when ___ is very small, S ª 1,
RE
which provides good stability. Hence, self bias method is the best one over other
types of “biasing”.
The various biasing circuits considered in the previous sections used some types
of negative feedback to stabilise the operation point. Also, diodes, thermistors
and sensistors can be used to compensate for variations in current.
In Fig. 5.23 a thermistor, RT, having a negative temperature coefficient is connected in parallel with R2. The resistance of
thermistor decreases exponentially with increase of temperature. An increase
in temperature will decrease the base voltage VBE, reducing IB and IC. Bias
stabilization is also provided by RE and CE.
In Fig. 5.24 a sensistor, RS, having a positive temperature coefficient is connected across R1 (or RE). RS increase with temperature.
As temperature increases, the equivalent resistance of the parallel combination
of R1 and RS also increases and hence the base voltage VBE decrease, reducing IB
and IC. This reduced IC compensates for the increased IC caused by the increase
in ICO, VBE and b due to temperature rise.
Figure 5.25 shows the Thevenin’s
equivalent circuit of the voltage divider bias with bias compensation technique.
+ VCC
Rc
Vout
RB
Vin
VBE
RE
RD
–
–
V
+ DD
VD D
+
Here, VDD is separately used to keep diode in forward biased condition. If the
diode is of same material and type as the transistor, the voltage across the diode
VD will have the same temperature coefficient (2.5 m V/°C) as the base to emitter voltage VBE. If VBE changes by a small amount with change in temperature,
then VD also changes by the same amount and therefore, the changes cancel
each other.
We know that,
[
]
[RB + (1 + b) RE]
(RE + RB) (1 + b)
VBE = VT – ________________ IC + _______________ ICO
b
b
Rearranging, we have
[
]
[RB + (1 + b) RE]
(RE + RB) (1 + b)
_______________
IC = VT – VBE + _______________ ICO
b IC
b
Hence,
b [VT – VBE] + (RE + RB) (1 + b) ICO
IC = _______________________________
RB + (1 + b) RE
From KVL equation of the base circuit of Fig. 5.28, the above equation can be
written as
b [Vin – (VBE – VD)] + (RE + RB) (1 + b) ICO
IC = _____________________________________
RB + (1 + b) RE
Since variation of VD is same as VBE, the collector current IC will be insensitive
to variation in VBE.
Figure. 5.26 shows the diode
compensation technique used in voltage divider bias. Here, the diode is connected
in series with resistance R2 and it is in forward biased condition. Therefore,
+
RC
R1
IC
VCC
VD
D
VR2
R2
VB
RE
VE
–
VE VB – VBE
IE = ___ = ________
RE
RE
and
IC ª IE
When VBE changes with temperature, IC also changes. To cancel the change
in IC, a diode is used at the base terminal to compensate the change in VBE as
shown in Fig. 5.26. The voltage at the base, VB, becomes
VB = VR2 + VD
Substituting in the above equation for IC, we get
VR2 + VD – VBE
IC ª ______________
RE
If the diode is of the same material and type as the transistor, then the voltage
across the diode will have the same temperature coefficient (2.5 mV/°C ) as the
base to emitter voltage VBE. When VBE changes by a small amount with change
in temperature, VD also changes by the same amount and thus they cancel each
other and the collector current remains constant. Therefore,
VR2
IC = ____
RE
The change in VBE due to temperature is
compensated by a change in the diode voltage that keeps IC stable at Q point.
plifier with a diode D connected across the
base–emitter junction for compensation of
change in collector saturation current ICO.
The diode is of the same material as the tran-
sistor and it is reverse biased by the base–emitter junction voltage VBE, allowing
the diode reverse saturation current I0 to flow through diode D. The base current IB = I – Io.
As long as temperature is constant, diode D operates as a resistor. As the temperature increases, ICO of the transistor increases. Hence, to compensate for this,
the base current IB should be decreased.
The increase in temperature will also cause the leakage current Io through D to
increase and thereby decreasing the base current IB . This is the required action
to keep IC constant.
This method of bias compensation does not need a change in IC to effect the
change in IB, as both Io and ICO can track almost equally according to the change
in temperature.
TA
collector-base junction of the transistor is TJ °C. Due to heating within the transistor, TJ is higher than TA. As the temperature difference TJ – TA is greater, the
power dissipated in the transistor, PD will be greater, i.e. TJ – TA μ PD.
This equation can be written as TJ – TA = Q PD, where Q is the constant of proportionality and is called the thermal resistance. Rearranging the above equation
Q = TJ – TA /PD. Hence Q is measured in °C/W which may be as small as 0.2 °C/W
for a high power transistor that has an efficient heat sink or up to 1000 °C/W for
small signal, low power transistors which have no cooling provision.
As Q represents total thermal resistance from a transistor junction to the ambient temperature, it is commonly referred to as QJ – A. However, for power transistors, thermal resistance is given from junction to case, QJ – C.
The amount of power that may be safely dissipated in the transistor is given by
PD = (TJ – TA)/QJ – A
or
PD = (TJ – TC)/QJ – C
The thermal resistance from junction to ambience is considered to consist of
two parts.
QJ – A = QJ – C + QC – A
which indicates that heat dissipated in the junction must make its way to the
surrounding air through two series paths from junction to case and from case to
air. Hence, the power dissipated
PD = (TJ – TA)/QJ – A
= (TJ – TA)/(QJ – C + QC – A)
QJ – C is determined by the type of manufacture of the transistor and how it is
located in the case, but QC – A is determined by the surface area of the case or
flange and its contact with air. If the effective surface area of the transistor case
could be increased, the resistance to heat flow, or QC–A, could be decreased. This
can be achieved by the use of a heat sink.
The heat sink is a relatively large, finned, usually black metallic heat conducting
device placed in close contact with the transistor case or flange. Many versions
of heat sink exist depending upon the shape and size of the transistor. Larger the
heat sink, smaller will be its thermal resistance, QHS – A. This thermal resistance
is not added to QC – A in series, but is instead in parallel with it and if QHS – A is
much less than QC – A, then QC – A will be reduced significantly, thereby improving the dissipation capability of the transistor.
QJ – A = QJ – C + QC – A || QHS – A
Thus,
For a given transistor, the thermal resistance is 8 °C/W and for the ambient temperature TA is 27 °C. If the transistor dissipates 3 W of power, calculate the junction
temperature TJ.
Solution
Therefore,
We know that,
TJ = TA + QPD
TJ = 27 °C + (8 °C/W) × 3W
= 27 °C + 24 °C = 51°C
For a transistor, TJ = 160 °C, TA = 40 °C and QJ – A = 80 °C/W. Calculate the power
that the transistor can safely dissipate in free air.
TJ – TA 160 – 40 120
PD = _______ = ________ = ____ = 1.5 W
QJ – A
80
80
Determine the power dissipation capability of a transistor which has been mounted
with a heat sink having thermal resistance QHS – A = 8 °C/W, TA = 40 °C, TJ =
160 °C, QJ – C = 5 °C/W and QC – A = 85 °C/W.
Solution
We know that QJ – A = QJ – C + QC – A ||QHS – A
= 5 + 85 || 8
85 × 8
= 5 + ______ = 5 + 7.31 = 12.31 °C/W
85 + 8
TJ – TA 160 – 40
120
PD = _______ = ________ = _____ = 9.75 W
QJ – A
12.31
12.31
mounted directly on the metal chassis to increase the sufficient heat dissipation capability. Care should be taken while doing this because very often the
collector of the transistor is connected to the transistor case to increase heatdissipation capabilities. Hence, some provision for insulating the case from the
chassis, which is usually at ground potential, must be provided unless a common
collector is being employed.
One method of achieving this is to use a beryllium oxide insulating washer which
has a good thermal conductivity, as shown in Fig. 5.28(a). By using a zinc oxide
film Silicon compound between the washer and the chassis, heat transfer from
the transistor case to the chassis may be improved. An insulated clamp over
the top of the transistor may be used to help improve thermal dissipation and
increase pressure.
Fin-type
heat sink
When the transistor is mounted in Teflon (PTFE—Poly Tere Fluoro Ethylene)
sockets, it does not provide thermal conduction from transistor case to chassis.
Therefore, a press-on fin type of a black anodized heat sink may be used, as
shown in Fig. 5.28(b), for mounting transistors that are encased in a metal TO-5
package.
Case
Sillcone
grease
BeO
washer
Chassis
(a)
(b)
the popular mounting packages used for the power transistors which have dissipation in the order of 100 W. These have two leads for emitter and base but the
case, or the mounting flange of the case, is the collector terminal. So, it is necessary to insulate the case from the heat sink by the use of an insulating washer.
Figure 5.29 shows a typical heat sink that can accommodate a TO-3 power transistor package that provides cooling by conduction, convection and radiation.
Although measuring only 11.5 cm by 7.8 cm, it has a thermal dissipation equal
to that of a flat aluminium sheet 25 cm × 20 cm × 0.32 cm. The thermal resistance of this heat sink is 3°C/W.
For the proper functioning of a linear FET amplifier, it is necessary to maintain
the operating point Q stable in the central portion of the pinch off region. The
Q-point should be independent of device parameter variations and ambient temperature changes. This can be achieved by suitably selecting the gate to source
voltage (Vgs) and drain current(ID) which is referred to as biasing.
The Q-point, the quiescent point or operating point for a self-biased JFET is
established by determining the value of drain current ID for a desired value of
gate-to-source voltage, Vgs, or vice versa. However, if the data sheet of JFET
includes a transfer characteristics curve, then the Q-point may be determined by
using the procedure given below.
(i) Select a convenient value of drain current whose value is generally taken
half of the maximum possible value of drain current, IDSS, Then find the
voltage drop across source resistor, Rs, by
Vs = ID Rs
and the gate-to-source voltage from the equation
Vgs = – Vs
(ii) Plot the assumed value of drain current, ID, and the corresponding gate-tosource voltage, Vgs, on the transfer characteristics curve.
(iii) Draw a line through the plotted point and the origin. The point of intersection of the line and the curve gives the desired Q-point. Then, read the
co-ordinates of Q-point.
It is necessary to fix the Q-point near the mid-point of the transfer characteristic
curve of a JFET. The mid-point bias allows a maximum amount of drain current swing between the values of IDSS and the origin.
The following analytical method or graphical method can be used for the design
of self-bias circuit.
The values of the maximum drain current, IDSS, and the
gate-to-source cut-off voltage, Vgs(off) are noted down from the data sheets of
JFET.
The value of the drain current is determined by
[
Vgs
ID = 1 – ______
Vgs (off)
]
2
For example, if we select the gate-to-source voltage, Vgs = Vgs(off)/4, then the
value of the drain current will be
ID = IDSS {1 – 0.25}2 = IDSS (0.75)2 = 0.56 IDSS
Here, the drain current is slightly more than one-half of IDSS. But it will bias the
JFET close to the mid-point of the curve. The value of the drain resistor, RD, is
selected in such a way that the drain voltage, VD, is equal to half the drain supply
voltage, RD. The value of gate resistor, RG, is chosen arbitrarily large, so that it
prevents loading on the driving stages.
A self-bias line is drawn such that it intersects the transfer characteristic curve near its mid-point gives the required Q-point. Then the
co-ordinates of the Q-point are obtained. The value of source resistance, Rs, is
expressed by the ratio of gate-to-source voltage, Vgs, to the drain current, ID.
Therefore, the source resistance is given by
Vgs
Rs = ___
ID
However, a more accurate method is to draw a self bias line through the co-ordinates of IDSS and Vgs(off) as shown in Fig. 5.30. Then the point of intersection of
self-bias line and the transfer characteristic curve locates the Q-point. The value
of the source resistor is expressed by the relation
Vgs(off)
RS = ______
IDSS
The value of drain resistor, RD, and the gate
resistor, RG, are selected in the same way as discussed above for the analytical method.
An FET may have a combination of self bias
and fixed bias to provide stability of the quiescent drain current against device and temperature variations.
Figure 5.31 shows the self-bias circuit for an N-channel FET. When the drain
voltage VDD is applied, a drain current ID flows even in the absence of gate voltage (VG). The voltage drop across resistor Rs produced by the drain current is
given by Vs = ID Rs. This voltage drop reduces the gate to source reverse voltage
required for FET operation. The feedback resistor Rs prevents any variation in
FET drain current.
The drain voltage,
VD = VDD – ID RD
The drain-to-source voltage,
VDS = VD – Vs = (VDD – ID RD) – ID Rs
= VDD – ID(RD + Rs)
The gate-to-source voltage
Vgs = VGG – Vs = 0 – ID Rs = – IDRs
When drain current increases, the voltage drop across Rs increases. The increased
voltage drop increases the reverse gate to source voltage, which decreases
the effective width of the channel and hence, reduces the drain current. Now
the reduced drain current decreases the gate to source voltage which, in turn,
increases the effective width of channel thereby increasing the value of drain
current.
Figure 5.32(a) shows the voltage divider bias circuit and its Thevenin’s equivalent is shown in Fig. 5.32(b). Resistors R1 and R2 connected on the gate side
forms a voltage divider. The gate voltage,
(
)
R2
VGG = _______ VDD and
R1 + R2
R1R2
RG = _______
R1 + R2
The bias satisfies the equation Vgs = VGG – IDRs.
The drain to ground voltage, VD = VDD – IDRD. If the gate voltage VGG is very
large as compared to gate to source Vgs, the drain current is approximately constant. In practice, the voltage divider bias is less effective with JFET than BJT.
This is because, in BJT, VBE ª 0.7 (silicon) with only minor variations from one
transistor to another. But in a JFET, the Vgs can vary several volts from one
JFET to another.
The FET device needs d.c. bias for setting the gate to source voltage Vgs to give
desired drain-current ID. For a JFET, the drain current is limited by IDSS. Since
the FET has a high input impedance, it does not allow the gate current to flow
and the dc voltage of the gate set by a voltage divider or a fixed battery is not
affected or loaded by the FET.
The fixed bias circuit for an N-channel JFET shown in Fig. 5.33 is obtained by
using a supply VGG. This supply ensures that the gate is always negative with
respect to source and no current flows through resistor RG and gate terminal i.e.
IG = 0. The VGG supply provides a voltage Vgs to bias the N-channel JFET, but
no resulting current is drawn from the battery VGG. Resistor RG is included to
allow any ac signal applied through capacitor C to develop across RG. While any
ac signal will develop across RG, the d.c. voltage drop across RG is equal to IGRG
which is equal to zero volt.
Then, the gate to source voltage Vgs is
Vgs = VG – Vs = –VGG – 0 = –VGG
The drain-source current ID is then fixed by the gate-source voltage.
This current will cause a voltage drop the drain resistor RD and is given as
VDD = ID ◊ RD + VDS
VDD – VDS
ID = __________
RD
Figure 5.34 shows the drain-to-gate bias circuit for enhancement mode
MOSFET. Here, the gate bias voltage is
[
]
R1
Vgs = _______ VDS
R1 + Rf
This circuit offers the d.c. stabilisation through the feedback resistor Rf .
However, the input resistance is reduced because of Miller effect.
Also, the voltage divider biasing technique given for JFET can be used for the
enhancement MOSFET. Here, the d.c. stability is accomplished by the d.c. feedback through Rs.
But the self-bias technique given for JFET cannot be used for establishing an
operating point for the enhancement MOSFET because the voltage drop across
Rs is in a direction to reverse-bias the gate and it actually needs forward gate
bias.
Figure 5.35 shows an N-channel enhancement mode MOSFET common source
circuit with source resistor. The gate voltage is
(
)
R2
VG = VGS = _______ (VDD)
R1 + R2
and the gate-to-source voltage is
Vgs = VDD – VG
Assuming that Vgs > VTN and the MOSFET is biased in the saturation region,
the drain current is
ID = KN(Vgs – VTN)2
Here the threshold voltage VTN and conduction parameter KN are functions of
temperature.
The drain-to-source voltage is
VDS = VDD – IDRD
If VDS > VDS (sat) = Vgs – VTN, then the MOSFET is biased in the saturation
region. If VDS < VDS (sat) = Vgs – VTN, then the MOSFET is biased in the nonsaturation region, and the drain current is given by
ID = KN [2(Vgs – VTN) VDS – V2DS]
Both the self-bias technique and voltage divider bias circuit given for JFET can
be used to establish an operating point for the depletion mode MOSFET.
Calculate the operating point of the self-biased JFET having the supply voltage VDD
= 20 V, maximum value of drain current IDSS = 10 mA and Vgs = – 3 V at ID = 4
mA. Also, determine the values of resistors RD and Rs to obtain this bias condition.
Solution We know that the value of drain current at Q-point,
IDSS
10 × 10–3
IDQ = ____ = ________ = 5 mA
2
2
and the value of drain-to-source voltage at Q-point,
VDD 20
VDSQ = ____ = ___ = 10 V
2
2
Therefore, the operating point is at VDS = 10 V and ID = 5 mA.
Also, we know that the drain-to-source voltage,
VDS = VDD – IDRD
10 = 20 – (4 × 10–3) RD
20 – 10
RD = _______
= 2.5 kW
4 × 10–3
The source voltage or voltage across the source resistor Rs is
Therefore,
Vs = –Vgs = –3 V
i.e. 3 = ( 4 × 10–3) Rs
Also,
Vs = IDRs
Therefore,
3
Rs = _______ = 750 W
4 × 10–3
Calculate the values of Rs required to self bias an N-channel JFET with IDSS = 40
mA, VP = – 10 V and VGSQ = – 5 V.
[
Vgs
Solution We know that ID = IDSS 1 – ___
VP
]
2
Substituting the given values, we get
[
]
(–5) 2
ID = 40 × 10–3 1 – _____ = 10 mA
(–10)
| |
VDSQ
5
Rs = _____ = ________
= 500 W
ID
10 × 10–3
Therefore,
A JFET amplifier with a voltage divider biasing circuit has the following parameters: VP = – 2 V, IDSS = 4 mA, RD = 910 W, Rs = 3 kW, R1 = 12 MW, R2 = 8.57
MW and VDD = 24 V. Find the value of the drain current ID at the operating point.
Verify whether the FET will operate in the pinch-off region.
Solution We obtain
R2
8.57 × 106
VGG = VDD _______ = 24 _______________6 = 10 V
R1 + R2
(12 + 8.57) × 10
We know that
(
Vgs
ID = IDSS 1 – ___
VP
2
)
VGG – ID Rs 2
= IDSS 1 – __________ , where Vgs = VGG – ID Rs
VP
(
)
Expressing ID and IDSS in mA and RS in kW, we have
(
10 – ID × 3
ID = 4 × 1 – __________
–2
i.e.,
2
)
9I2D – 73ID + 144 = 0
Therefore,
ID = 3.39 mA or 4.72 mA
As ID = 4.72 mA > 4 mA = IDSS, this value is inappropriate. So, IDQ = 3.39 mA
is selected.
Therefore,
VGSQ = VGG – IDQRs = 10 – (3.39 × 10–3 × 3 × 103) = – 0.17 V
and VDSQ = VDD – IDQ (RD + Rs) = 24 – 3.39 × 10–3 (0.91 + 3) × 103 = 10.745 V
Then VDGQ = VDSQ – VGQS = 10.745 + 0.17 = 10.915 V
which is greater than |VP | = 2 V. Hence, the FET is in the pinch-off region.
A voltage divider bias is provided to an N-channel JFET circuit as shown in
Fig. 5.36. To establish IDSS = 10 mA, VP = –3.5 V, R1 + R2 = 20 kW, ID = 5 mA and
VDS = 5 V, determine the values of R1, R2 and RD.
Solution
Let us assume that the JFET is biased in the saturation region.
Then the d.c. drain current is given by
Vgs 2
ID = IDSS 1 – ___
VP
Therefore,
Vgs 2
5 = 10 1 – ______
(–3.5)
(
(
)
)
By solving, we get Vgs = –1.008 V
The voltage at the source terminal is
Vs = IDRs – 5 = (5 × 10–3) (0.5 × 103) – 5 = –2.5 V
The gate voltage is
VG = Vgs + Vs = –1.008 – 2.5 = –3.508 V
The gate voltage can be written as
R2
VG = _______ (10) – 5
R1 + R2
(
)
R2
Therefore, –3.508 = ________3 (10) – 5
20 × 10
i.e.,
R2 = 2.984 kW
and
R1 = 17.016 kW
The drain-to-source voltage is
VDS = 5 – IDRD – IDRs – (–5)
Substituting the specified values, we get
10 – VDS – ID Rs 10 – 5 – (5) (0.5)
RD = ______________ = ______________ = 0.5 kW
5
Vgs – VP = –1.24 – (–3.5) = 2.26 V
Here, since VDS > (Vgs – VP), the JFET is biased in the saturation region, which
satisfies the initial assumption.
For the circuit shown in Fig. 5.37, find the values of VDS and Vgs. Given, ID = 5 mA,
[JNTU May 2007]
VDD = 10 V, RD = 1 KW and Rs = 500 W.
Solution
VGG = Vgs + IDRs
Since
VGG = 0, Vgs = – IDRs = – 5 × 10–3 × 500 = – 2.5 V
We know that VDD = ID(RD + Rs) + VDS
Therefore,
VDS = VDD – ID(RD + Rs) = 10 – 5 × 10–3 (1500) = 2.5 V
For the common-source N-channel
MOSFET circuit shown in Fig.
5.38 with the threshold voltage
VTN = 1.5 V, conduction parameter
KN = 1 mA/V2, the channel-length
modulation parameter l = 0.01 V–1,
Ri = R1 || R2 = 100 kW and the current at the transition point IDt = 4 mA.
Design the MOSFET circuit with
voltage divider bias such that IDQ =
1.5 mA and Q-point is in the middle of
the saturation region.
VDD = 12 V
RD
R1
ID = 2 mA
V
CC
Vi
±
R2
Solution
To determine VDSt :
We know that
IDt = 4 = KN (VGst – VTN)2
= 1 (VGSt – 1.5)2
where the subscript t indicates transition point values.
Solving, we get
VGSt = 3.5 V
Therefore,
VDSt = VGSt – VTN = 3.5 – 1.5 = 2 V
If the Q-point is in the middle of the saturation region, then VDSQ = 7 V, which
gives 10 V peak-to-peak symmetrical output voltage.
From Fig. 5.36,
VDSQ = VDD – IDQRD
Therefore,
VDD – VDSQ 12 – 7
RD = ___________ = ______ = 3.33 kW
IDQ
1.5
Then
IDQ = 1.5 = KN (VGSQ – VTN)2
= (1) (VGSQ – 1.5)2
Therefore,
VGSQ = 2.73 V
Then,
R2
1
VGSQ = 2.73 = _______ (VDD) = ___
R1 + R2
R1
(
)
(V
( ) ( _______
R +R )
Ri
(100 × 103) (12)
2.73 = ___ (VDD) = ______________
R1
R1
By solving, we get
R1 = 439.6 kW and R2 = 129.45 kW
For the N-channel depletion mode MOSFET circuit shown in Fig. 5.39. VTN = –2 V and KN = 0.1
mA/V2. Assume that VDD = 5 V and Rs = 5 kW.
Determine ID and VDS.
R1 R2
1
2
DD)
Solution
Let us assume that the MOSFET is biased in the saturation region.
Then the d.c. drain current is
ID = KN (Vgs – VTN)2 = KN (–VTN)2
= (0.1) (–(–2))2 = 0.4 mA
The d.c. drain-to-source voltage is
VDS = VDD – IDRs = 5 – (0.4)(5) = 3 V
Then,
Since V
VDS(sat) = Vgs – VTN = 0 – (–2) = 2 V
>V
Determine the following for the network shown
in Fig. 5.40.
(i) VGSQ (ii) VDS (iii) VD
(iv) VG
(v) Vs
(i) VGSQ = – VGG = – 3V
[
]
Vgs 2
–3
(ii) IDQ = IDSS 1 – ___ = 12 × 10–3 1 – ___
VP
–6
[ ( ) ] = 3 mA
2
VDS = VDSQ = VDD – IDQRD
= 35 – 3 × 10–3 × 3.5 × 103 = 24.5 V
(iii) VD = VDS + Vs = 24.5 + 0 = 24.5 V
(v) VS = 0 V
(iv) VG = – 3V
Determine IDQ, VGSQ, VD, VDS, and VDG for the given network shown in Fig. 5.41.
Solution
To find expression for VGS :
R2
270
Vgs = _______ × VDD = ___________ × 20 = 2.28 V
R1 + R2
(2100 + 270)
Vgs = 1.5 ID
Therefore, Vgs = VG – Vs = (2.28 – 1.5 ID)
To find ID :
[
]
Vgs 2
ID = IDSS 1 – ___ mA
VP
[
(2.28 – 1.5 ID)
ID = 8 1 – ____________
–4
]
2
mA
8
Therefore, ID = ___ [4 + 2.28 – 1.5 ID]2 = 0.5 (6.28 – 1.5 ID)2
16
2ID = 39.44 – 18.84 ID + 2.25 I2D
2.25 I2D – 20.84 ID + 39.44 = 0
________________________
20.84 ± ÷(20.84)2 – (4 × 2.25 × 39.44)
Therefore, ID = ________________________________ = 6.6 mA or 2.6 mA
2 × 2.25
For ID = 6.6 mA, VDS is negative and hence this value may be neglected. Let us
choose ID = 2.65 mA.
Therefore, IDQ = 2.65 mA.
To find VGSQ :
VGSQ = 2.28 – 1.5 IDQ = 2.28 – (1.5 × 2.65) = – 1.695 V
To find VDSQ :
VDSQ = VDD – IDQ(RD + Rs)
VDSQ = 20 – 2.65 × 10–3 (4.7 + 1.5) × 10–3 = 3.57 V
Therefore,
To find VD, Vs and VDG :
Vs = IDRs = 2.65 × 10–3 × 1.5 × 10–3 = 3.975 V
VD = Vs + VDS = 3.975 + 3.57 = 7.545 V
VDG = VD – VG = 7.545 – 2.28 = 5.265 V
Hence,
For the given measurement Vs = 1.7 V for the
network as shown in Fig. 5.42, determine
(ii) VGSQ
(i) IDQ
(iii) IDSS
(iv) VD
(v) VDS
Solution
(i)
Given Vs = 1.7 V
Vs = IDRs
Vs 1.7
IDQ = ___ = ____ = 3.33 mA
Rs 510
(ii)
(iii)
VGSQ = VG – Vs = – Vs = – 1.7 V
(
Vgs
ID = IDSS 1 – ___
VP
2
)
ID
3.33 × 10–3
IDSS = _________2 = ___________2 = 10 mA
Vgs
(–1.7)
1 – ______
1 – ___
(–4)
VP
(
(iv)
(v)
) (
)
VD = VDD – IDRD = 18 – 3.33 × 10–3 × 2 × 103 = 11.34 V
VDS = VD – Vs = 11.34 – 1.7 = 9.64 V
For a circuit shown in Fig. 5.43, calculate
V0, Zi and Z0. Given input is Vi = 0.2 V(rms),
IDSS = 9 mA and VP = – 4.5 V.
Solution
Zi = RG = 10 MW
(
Vgs
ID = IDSS 1 – ___
VP
)
2
(
–IDRs
= 9 × 10–3 1 – ______
VP
2
)
(
(–1000 ID)
= 9 × 10–3 1 – _________
– 4.5
2
)
= 9 × 10–3 (1 – 222.22 ID)2
= 9 × 10–3(1 – 444.44 ID + 49383I D2 )
ID = 9 × 10–3 – 4ID + 444.45 I2D
Therefore, 444.45 I2D – 5ID + 9 × 10–3 = 0
Solving the quadratic equation, we get
ID = 2.25 mA or 9 mA
Since ID < IDSS, we take ID = 2.25 mA. Therefore,
2IDSS 2 × (9 × 10–3)
gmo = _____ = ____________ = 4 mS
4.5
|VP|
(
VGSQ
gm = gmo 1 – _____
VP
)
–3
where VGSQ = – IDRs = – 2.25 × 10 × 1000 = – 2.25 V
(
)
(2.25)
gm = 4 × 10–3 1 – ______ = 2 mS
(– 4.5)
1
1
_______
3
Zo = ___
gm || Rs = 2 × 10–3 || 1 × 10 = 333.33W
gm(rd || Rs)
gm Rs
2 × 10–3 × 1 × 103
AV = _____________ = _________ = ____________________
= 0.667
1 + gm(rd || Rs) 1 + gm Rs 1 + (2 × 10–3 × 1 × 103)
Vo = Vi × AV = 0.2 × 0.667 = 0.133 V
An N-channel JFET having VP = – 4 V and VDSS
= 10 mA is used in the circuit of Fig. 5.44. The
parameter values are VDD = 18 V, Rs = 2kW, R1 =
450 kW, and R2 = 90 kW. Determine ID and VDS.
Solution
To find VGS :
Vgs = VG – ID Rs
R2
90 × 103
VG = _______ × VDD = ______________3 × 18 = 3 V
R1 + R2
(450 + 90) × 10
Therefore,
Vgs = (3 – 2 × 103 ID)
To find ID :
ID = IDSS
[
]
[
Vgs 2
(3 – 2 × 103 ID)
1 – ___ = 10 × 10–3 1 – _____________
VP
–4
10 × 10–2
= ________ [4 + 3 – 2 × 103 ID]2
16
Therefore, 1.6 ID = 10–3 [7 – 2 × 103 ID]2
= 0.049 – 28 ID + 4 × 103 I2D
4 × 103 I2D – 29.6 ID + 0.049 = 0
_________________________
29.6 ± ÷(29.6)2 – 4 × 4 × 103 × 0.049
ID = ________________________________
2 × 4 × 103
]
2
Therefore, ID = 4.9 mA or 2.5 mA
If ID = 4.9 mA, then VDS would be negative and hence this is not acceptable.
Therefore,
IDQ = 2.5 mA
To find VDS :
VDS = VDD – IDQ(RD + Rs) = 18 – 2.5 × 10–3 (2 + 2) × 103 = 8 V
Determine Vgs, ID, VDS , VD and VG for the circuit shown in Fig. 5.45.
Solution
To find VGSQ :
For a self bias circuit, VGSQ = – IDRs = – ID × 103
To find ID :
[
[
]
Vgs 2
(1 × 103 ID)
ID = IDSS 1 – ___ = 8 × 10–3 1 + __________
VP
–6
[
1000 ID
= 8 × 10–3 1 – _______
6
]
2
Therefore, 36 ID = 8 × 10–3 [6 – 1000 ID]2
= 8 × 10–3 [36 – 12 × 103 ID + 106 I2D]
Hence,
8 × 103 I2D – 132ID + 0.288 = 0
________________________
132 ± ÷(132)2 – 4 × 8 × 103 × 0.288
ID = ______________________________
2 × 8 × 103
Therefore,
ID = 13.9 mA or 2.5 mA
]
2
But ID cannot be higher than IDSS, Therefore, ID = 2.5 mA
To find VDS :
VDS = VDD – ID(RD + Rs) = 20 – 2.5 × 10–3(3.3 + 1) × 103 = 9.25 V
To find Vgs, VD and Vs :
Vgs = 1 × 103 × ID = 1 × 103 × 2.5 × 10–3 = 2.5 V
Vs = IDRs = 2.5 × 10–3 × 1 × 103 = 2.5 V
VD = Vs + VDS = 2.5 + 9.25 = 11.75 V
Determine the following for the network shown in Fig. 5.46.
– VGSQ, VDQ, VD, VG, Vs and VDS .
Solution
VG = 0, Vs = IDRs
Vgs = VG – Vs = 0 – IDRs = – 680 ID
To find ID :
(
Vgs
We know that ID = IDSS 1 – ___
VP
2
)
( (
–680 ID
= 12 × 10–3 1 – _______
–6
154.12 I2D – 3.7 ID + 0.012 = 0
______________________
2.7 ± ÷(2.7)2 – 4 × 152.6 × 0.012
Therefore, ID = ____________________________
2 × 152.6
= 12.4 mA or 5.28 mA
Since ID is less than IDSS,
IDQ = 5.28 mA
To find VGSQ :
))
2
VGSQ = – 680 ID = – 680 × 5.28 × 10–3 = –3.6 V
To find Vs :
Vs = IDRs
= 5.28 × 10–3 × 680 = 3.6 V
To find VDS :
VDS = VDD – ID(RD + Rs)
= 12 – 5.28 × 10–3 ( 1.5 × 103 + 680 ) = 12 – 11.51 = 0.49 V
To find VD :
V =V +V
= 3.6 + 0.49 = 4.09 V
The equivalent circuit for a transistor can be drawn using simple approximations
by retaining its essential features, at the same time discarding its less important
qualities. These equivalent circuits will aid in analysing transistor circuits easily
and rapidly. In this chapter, small signal equivalent circuits of the transistor are
derived. Small signal operation is that in which the ac input signal voltages and
currents are in the order of ±10% of Q point voltages and currents.
A transistor can be treated as a two-port network. The terminal behaviour of
any two port network can be specified by the terminal voltages v1 and v2 at ports
1 and 2, respectively, and currents i1 and i2, entering ports 1 and 2, respectively,
as shown in Fig. 6.1. Of these four variables v1, v2, i1 and i2, two can be selected
as independent variables and the remaining two can be expressed in terms of
these independent variables. This leads to various two-port parameters out of
which the following three are more important.
(i) Z-parameters or Impedance parameters
(ii) Y-parameters or Admittance parameters
(iii) h-parameters or Hybrid parameters.
Here, i1 and i2 are taken as independent variables. The voltages v1 and v2 are
given by the equations
v1 = Z11ii + Z12i2
(6.1)
v2 = Z21i1 + Z22i2
(6.2)
These four impedance parameters, Z11, Z22, Z12 and Z21 are defined as follows:
v1
Z11 = __ with i2 = 0
i1
[ ]
= input impedance with output port open circuited
v2
Z22 = __ with i1 = 0
i2
[ ]
= output impedance with input port open circuited
v1
Z12 = __ with i1 = 0
i2
[ ]
= reverse transfer impedance with port 1 open circuited
v2
Z21 = __ with i2 = 0
i1
[ ]
= forward transfer impedance with port 2 open circuited.
Here, v1 and v2 are taken as independent variables. The currents i1 and i2 are
given by the equations
i1 = y11v1 + y12v2
(6.3)
i2 = y21v1 + y22v2
(6.4)
y11, y12, y21 and y22 represent short-circuit admittance parameters or simply
admittance parameters or y-parameters. They are defined as follows:
[ ]
i1
y11 = __
v1 with v2 = 0
= input admittance with port 2 short circuited
[ ]
i2
y22 = __
v2 with v1 = 0
= output admittance with port 1 short circuited
[ ]
i1
y12 = __
v2 with v1 = 0
= reverse transfer admittance with port 1 short circuited
[ ]
i2
y21 = __
v1 with v2 = 0
= forward transfer admittance with port 2 short circuited.
If the input current i1 and the output voltage v2 are taken as independent variables, the input voltage v1 and output current i2 can be written as
v1 = h11i1 + h12v2
(6.5)
i2 = h21i1 + h22v2
(6.6)
The four hybrid parameters h11, h12, h21 and h22 are defined as follows:
v1
h11 = __ with v2 = 0
i1
[ ]
= input impedance with output port short circuited
[ ]
i2
h22 = __
v2 with i1 = 0
= output admittance with input port open circuited
v1
h12 = __
v2 with i1 = 0
[ ]
= reverse voltage transfer ratio with input port open circuited
[]
i2
h21 = __ with v2 = 0
i1
= forward current gain with output port short circuited.
The dimensions of h-parameters are as follows:
h11 – W
h22 – mhos
h12, h21 – dimensionless
As the dimensions are not alike, i.e. they are hybrid in nature, these parameters
are called as hybrid parameters.
An alternative subscript notation recommended by IEEE is commonly used:
i = 11 = input; o = 22 = output
f = 21 = forward transfer; r = 12 = reverse transfer
When h-parameters are applied to transistors, it is a common practice to add
a second subscript to designate the type of configuration considered — e for
common emitter, b for common base and c for common collector. Thus, for a
common emitter (CE) configuration,
hie = h11e = short circuit input impedance
hoe = h22e = open circuit output admittance
hre = h12e = open circuit reverse voltage transfer ratio
hfe = h21e = short circuit forward current gain
Based on the definition of hybrid parameters, the mathematical, model for twoport networks known as h-parameter model can be developed. Equations (6.5)
and (6.6) can be written as
v1 = hi i1 + hrv2
(6.7)
i2 = hf i1 + hov2
(6.8)
The proposed model shown in Fig. 6.2 should satisfy these two equations and it
can be readily verified by writing Kirchhoff’s voltage law equation in the input
loop and Kirchhoff’s current law equation for the output node. It is to be noted
that the input circuit have a dependent voltage generator and the output circuit
contains a dependent current generator.
On extending the hybrid model for two-port network to a transistor, it is assumed
that the signal excursion about the Q point is small so that the transistor parameters may be considered constant over the signal excursion. Use of h-parameters
to describe a transistor have the following advantages:
(i) h-parameters are real numbers upto radio frequencies
(ii) they are easy to measure
(iii) they can be determined from the transistor static characteristics curves
(iv) they are convenient to use in circuit analysis and design
(v) easily convertable from one configuration to other
(vi) readily supplied by manufacturers.
In order to derive a hybrid model for transistor, consider the CE circuit of Fig.
6.3. The variables are iB, iC, vB (= vBE) and vC (= vCE). iB and vC are considered
as independent variables.
Then,
vB = f1(iB, vC)
(6.9)
iC = f2(iB, vC)
(6.10)
Making a Taylor’s series expansion around the quiescent point IB, VC and
neglecting higher order terms, the following two equations are obtained:
( )
( )
( )
( )
∂ f1
DvB = ___
∂ iB
∂ f1
DiB + ____
∂ vC
VC
IB
∂ f2
DiC = ___
∂ iB
∂ f2
DiB + ____
∂ vC
VC
IB
DvC
(6.11)
DvC
(6.12)
The partial derivatives are taken keeping the collector voltage or base current
constant as indicated by the subscript attached to the derivative. DvB, DvC, D iB
and DiC represent the small-signal (incremental) base and collector voltages and
currents. They are represented by symbols vb, vc, ib and ic, respectively. Hence,
Eqns (6.11) and (6.12) may be written as
vb = hieib + hrevc
ic = hfeib + hoevc
where
∂ f1
hie = ___
∂ iB
∂ vB
= ____
∂ iB
VC
DvB
ª ____
∂ iB
VC
vb
= __
ib
VC
∂ f1
hre = ____
∂ vC
∂ vB
= ____
∂ vC
IB
DvB
ª ____
DvC
IB
vb
= __
vc
( ) ( ) ( ) ()
( ) ( ) ( ) ()
IB
VC
IB
ic
C
RL
iB
B
vc
+
VCC
vB
E
–
(6.13)
(6.14)
∂ f2
hfe = ___
∂ iB
∂ iC
= ___
∂ iB
VC
DiC
ª ___
DiB
VC
ic
= __
ib
VC
∂ f2
hoe = ____
∂ vC
∂ iC
= ____
∂ vC
IB
DiC
ª ____
Dv
IB
C
ic
= __
vc
( ) ( ) ( ) ()
( ) ( ) ( ) ()
IB
VC
IB
(6.15)
(6.16)
The above equations define the h-parameters of the transistor in CE configuration. The same theory can be extended to transistors in other configurations.
The hybrid models and equations given in Table 6.1 are valid for NPN as well
as PNP transistors and hold good for all types of loads and methods of biasing.
Table 6.2 gives the typical h-parameter values for a transistor and Table 6.3
gives the conversion formulae to find the h-parameters for CC and CB configurations given the h-parameters for CE configuration.
1,100 W
hi
2.5 × 10
hr
–4
1,100 W
22 W
1
3 × 10 – 4
hf
50
–51
– 0.98
ho
25 mA/V
25 mA/V
0.49 mA/V
ic
=
ie
ib
hie
= ______
1 + hfe
hrc = 1
hie hoe
hrb = ______ – hre
1 + hfe
hfc = – (1 + hfe)
– hfe
hfb = ______
1 + hfe
hoc = hoe
hoe
hob = ______
1 + hfe
A transistor amplifier can be constructed by connecting an external load and
signal source as indicated in Fig. 6.4 and biasing the transistor properly.
The two-port active network of Fig. 6.5 represents a transistor in any one of
its configuration. The hybrid equivalent circuit is valid for any type of load
Rs
1
I1
I2
hi
2
+
+
IL
+
+
Vs
V1
–
hrv2
–
ho
V2
hfI1
–
ZL
–
1¢
2¢
whether it is pure resistance or impedance or another transistor. It is assumed
that h-parameters remain constant over the operating range. Further, the input
is sinusoidal and I1, V1, I2 and V2 are phasor quantities.
For a transistor amplifier the current gain AI is defined as the ratio of output
current to input current, i.e,
IL – I2
AI = __ = ____
(6.17)
I1
I1
From the circuit of Fig. 6.5,
I2 = hf I1 + hoV2
Substituting
(6.18)
V2 = ILZL = – I2ZL,
I2 = hf I1 – I2ZLho
I2 + I2ZLho = hf I1
I2(1 + ZLho) = hf I1
– hf
– I2
AI = ____ = _________
I1
1 + ho ZL
Therefore,
(6.19)
–hf
AI = ________
1 + hoZL
In the circuit of Fig. 6.5, Rs is the signal source resistance. The impedance seen
when looking into the amplifier terminals (1,1¢) is the amplifier input impedance
Zi, i.e.,
V1
Zi = ___
I1
(6.20)
From the input circuit of Fig. 6.5, V1 = hiI1 + hrV2
Hence,
Substituting
hiI1 + hrV2
Zi = __________
I1
V2
= hi + hr ___
I1
V2 = – I2ZL = AI I1ZL
resulting in
AII1ZL
Zi = hi + hr ______
I1
Zi = hi + hr AI ZL
(6.21)
Substituting for AI,
hf
Zi = hi – ________ hr ZL
1 + hoZL
hf hr
= hi – ___________ ZL
1
ZL ___ + ho
ZL
(
)
1
Taking the load admittance as YL = ___
ZL
hf hr
Zi = hi – _______
YL + ho
(6.22)
Note that the input impedance is a function of load impedance.
The ratio of output voltage V2 to input voltage V1 gives the voltage gain of the
transistor, i.e.
V2
AV = ___
V1
Substituting
(6.23)
V2 = – I2ZL = AI I1ZL
AII1ZL AIZL
AV = ______ = _____
V1
Zi
(6.24)
By definition, Yo is obtained by setting Vs to zero, ZL to infinity and by driving
the output terminals from a generator V2. If the current drawn from V2 is I2,
I2
then Yo ∫ ___ with Vs = 0 and RL = •.
V2
From the circuit of Fig. 6.5,
I2 = hf I1 + hoV2
Dividing by V2,
I2
I1
___
= hf ___ + ho
V2
V2
(6.25)
With Vs = 0, by KVL in input circuit,
RsI1 + hiI1 + hrV2 = 0
(6.26)
I1 (Rs + hi) + hrV2 = 0
Hence,
I1
–hr
___
= ______
V2 Rs + hi
Substituting Eqn. (6.26) in Eqn. (6.25),
(
)
I2
– hr
___
= hf ______ + ho
V2
Rs + hi
hf hr
Yo = ho – ______
hi + Rs
(6.27)
From Eqn. (6.27), the output admittance is a function of source resistance. If the
source impedance is resistive then Yo is real.
This overall voltage gain AVs is given by
V2 V2 V1
V1
AVs = ___ = ___ ___ = AV ___
Vs V1 Vs
Vs
(6.28)
From the equivalent input circuit using Thevenin’s equivalent for the source
shown in Fig. 6.6,
Vs Zi
V1 = _______
Zi + Rs
Zi
V1 _______
___
=
Vs
Zi + Rs
(6.29)
Then,
AV Zi
AVs = _______
Zi + Rs
Substituting
AI ZL
AV = ______
Zi
AIZL
AVs = _______
Zi + Rs
(6.30)
(6.31)
AIZL
Note that if Rs = 0, then AVs = _____ = AV. Hence, AV is the voltage gain
Zi
with an ideal voltage source (with Rs = 0). In practice, AVs is more meaningful than AV because source resistance has an appreciable effect on the overall
amplification.
The modified input circuit using Norton’s equivalent circuit for the source for
the calculation of AIs is shown in Fig. 6.7.
Overall current gain,
–I2 –I2 I1
I1
AIs = ___ = ___ ◊ __ = AI __
Is
I1 Is
Is
Rs
I1 = IS _______
Rs + Zi
From Fig. 6.7,
(6.32)
(6.33)
Rs
I1 _______
__
=
Is Rs + Zi
Rs
AIs = AI _______
(6.34)
Rs + Zi
If Rs = •, then AIs = AI. Hence, AI is the current gain with an ideal current
source (one with infinite source resistance).
and hence,
From Eqn. (6.31),
AIZL Rs
AVs = _______ ___
Zi + Rs Rs
AIS ZL
AVs = ______
Rs
Then,
(6.35)
From Fig. 6.5, average power delivered to the load is P2 = |V2 | |IL | cos q, where
q is the phase angle between V2 and IL. Assume that ZL is resistive i.e. ZL = RL.
Since h-parameters are real at low frequencies, the power delivered to the load
is P2 = V2IL = – V2I2. Since the input power P1 = V1I1, the operating power gain
AP of the transistor is defined as
P2 – V2I2
RL
AP = ___ = ______ = AV AI = AI AI ___
P1
V1 1
Ri
( )
RL
AP = A2I ___
Ri
(6.36)
The important relations derived above are summarised in Table 6.4.
– hf
AI = _________
1 + ho ZL
AI ZL
AV = ______
Zi
hf hr
Zi = hi + hr AI ZL = hi – _______
YL + ho
AV Zi
AI ZL
ZL
AVs = _______ = _______ = AIs ___
Zi + Rs Zi + Rs
Rs
hf hr
1
Yo = ho – ______ = ___
hi + Rs Zo
AI Rs
Rs
AIs = _______ = AVs ___
Zi + Rs
ZL
A CE amplifier has the h-parameters given by hie = 1000 , hre = 2 × 10 – 4, hfe = 50
and hoe = 25 m mho. If both the load and source resistances are 1 k , determine the
(a) current gain and (b) voltage gain.
Solution
Given Rs = 1 kW and rL = 1 kW
(a) Current gain,
hfe
Ai = ___________
1 + hoe × RL
50
= ____________________
= 48.78
1 + 25 × 10–6 × 1 × 103
(b) Voltage gain,
– hfe
AV = ____________
1
hoe + ___ Zin
RL
(
)
hre hfe
Zin = hie – ________
1
hoe + ___
RL
Here,
2 × 10 – 4 × 50
= 1000 – __________________
= 990.24 W
25 × 10 – 6 + 1 × 10 – 3
Therefore,
– 50
AV = ____________________________
–6
(25 × 10 + 1 × 10 – 3) × 990.24
= – 49.26
The output voltage is 180° out of phase to the input signal with a gain
of 49.26.
A transistor amplifier circuit with R1 = 100 kW, R2 = 50 kW, RC = 10 kW and
RL = 40 kW has the h-parameters as follows: hie = 1100 , hfe = 100, hre = 10 ×
10 – 4, hoe = 4 × 10 – 4 mho. Determine the (a) a.c. input impedance of the amplifier
and (b) voltage gain.
Solution
At load resistance of the amplifier,
10 × 103 × 40 × 103
RL¢ = _________________
= 8 kW = 8000 W
10 × 103 + 40 × 103
(a) Input impedance,
hre hfe
Zin = hie – ________
1
hoe + ___
RL¢
4 × 10 – 4 × 100
= 1100 – ______________ = 1024 W
1
4 × 10 – 4 + _____
8000
The a.c. input resistance of the entire stage Ra.c. is
Ra.c. = Zin || R1 || R2 = 1024 || 100 × 1000 || 50 × 1000
(b) Voltage gain,
= 993.4 W
– hfe
AV = _____________
1
hoe + ___ Zin
RL¢
(
)
–100
= ____________________ = –186.34
1
–4
4 × 10 + _____ 1024
8000
(
)
The output is 180° out of phase to the input with a gain of 186.34.
The characteristics of three configurations are summarised in Table 6.5. Here,
the quantities Ai, AV, Ri, Ro and AP are calculated for a typical transistor whose
h-parameters are given in Table 6.2. The values of RL and Rs are taken as 3 kW.
Quantity
CB
CC
CE
AI
0.98
47.5
– 46.5
AV
131
0.989
– 131
AP
128.38
46.98
6091.5
Ri
22.6 W
144 kW
1065 W
Ro
1.72 MW
80.5 W
45.5 kW
The values of current gain, voltage gain, input impedance and output impedance
calculated as a function of load and source impedances can be shown graphically as in Fig. 6.8.
From Table 6.5 and Fig. 6.8, the performance of the CB, CC and CE amplifiers
can be summarised as follows:
(i) Current gain is less than unity and its magnitude decreases with the increase
of load resistance RL,
(ii) Voltage gain AV is high for normal values of RL,
(iii) The input resistance Ri is the lowest of all the three configurations, and
(iv) The output resistance Ro is the highest of all the three configurations.
The CB amplifier is not commonly used for amplification purpose. It is used for
(i) matching a very low impedance source
(ii) as a non-inverting amplifier with voltage gain exceeding unity
(iii) for driving a high impedance load
(iv) as a constant current source
(i) For low value of RL (< 10 kW), the current gain AI is high and almost equal
to that of a CE amplifier,
(ii) The voltage gain AV is less than unity,
(iii) The input resistance is the highest of all the three configurations, and
(iv) The output resistance is the lowest of all the three configurations.
The CC amplifier is widely used as a buffer stage between a high
impedance source and a low impedance load. The CC amplifier is called the
emitter follower.
(i) The current gain AI is high for RL < 10 kW,
(ii) The voltage gain is high for normal values of load resistance RL,
(iii) The input resistance Ri is medium, and
(iv) The output resistance Ro is moderately high.
Of the three configurations, CE amplifier alone is capable of
providing both voltage gain and current gain. Further the input resistance Ri
and the output resistance Ro are moderately high. Hence CE amplifier is widely
used for amplification purpose.
As the h-parameters themselves vary widely for the same type of transistor, it is
justified to make approximations and simplify the expressions for AI, AV, AP,
Ri and Ro. In addition, a better understanding of the behaviour of the transistor
circuit can be obtained by using the simplified hybrid model. Since CE configuration is more useful and general, it is taken for consideration.
The h-parameter equivalent circuit of the transistor in the CE configuration
1
is shown in Fig. 6.9. Here, ___ is in parallel with RL. The parallel combination
hoe
1
of two unequal impedances, i.e. ___ and RL is approx mately equal to the lower
hoe
1
value, i.e. RL. Hence, if ___ >> RL, then the term hoe may be neglected provided
hoe
that hoeRL << 1. Further, if hoe is omitted, the collector current IC is given by
IC = hfeIb.
Under this condition the magnitude of voltage of generator in the emitter circuit
is
hre |VC | = hre IC RL = hre hfe Ib RL
Since hre hfe ª 0.01, this voltage may be neglected in comparison with the voltage
drop across hie = hie Ib provided that RL is not too large.
To conclude, if the load resistance RL is small it is possible to neglect the parameter hre and hoe and obtain the approximate equivalent circuit as shown in
Fig. 6.10. It can be shown that if hoe RL £ 0.1, the error in calculating AI, AV, Ri
and Ro for CE configuration is less than 10%.
Figure 6.11 shows the simplified hybrid circuit that can be used for any configuration by simply grounding the appropriate terminal. The signal is connected between input and ground and the load is connected between output
and ground. The errors introduced in calculating the various parameters using
the approximate hybrid model are to be found out now. This is done for CE
configuration.
B
C
lb
hie
hfe lb
lE
– hfe
AI = _________
1 + hoe RL
If hoe RL < 0.1
AI ª – hfe
(6.37)
This new AI overestimates the magnitude of current gain by less than 10% provided hoe RL < 0.1.
Ri = hie + hre AI RL
It may be put in the form
(
hre hfe |AI| hoe RL
Ri = hie 1 – ______________
hie hoe hfe
)
Using the typical values for the h-parameters,
hre hfe
_____
ª 0.5
hie hoe
Further,
hfe
|AI | = _________ ª hfe
1 + hoe RL
Hence, the equation approximates to
(
0.5 hfe hoe RL
Ri ª hie 1 – ___________
hfe
If hoe RL < 0.1
)
Vb
Ri ª hie = ___
Ib
(6.38)
This overestimates the input resistance by less than 5%.
From Eqn. (6.24),
voltage gain,
hfe RL
RL
AV = AI ___ = – ______
Ri
hie
(6.39)
By taking the logarithm of this equation and then the differential,
dAV ____
dRi
dAI ____
____
=
–
Ri
AV
AI
dRi
and ____ = + 0.05
Ri
with hoe RL < 0.1,
dAI
____
= + 0.1
AI
Therefore,
dAV
____
= 0.1 – 0.05 = 0.05
AV
dAV
____
% = 5%
AV
Hence, the maximum error in voltage gain is 5% and the magnitude of AV is over
estimated by this amount.
It is the ratio of VC to IC with Vs = 0 and RL excluded.
The simplified circuit has infinite output impedance because with Vs = 0 and
external voltage source applied at the output, it is found that Ib = 0 and hence,
IC = 0.
However the actual value of output impedance depends on the source resistance
Rs and lies between 40 kW and 80 kW. With the load resistance RL included, the
output resistance Ro calculated using the approximate model increases, but not
more than 10%.
A CE amplifier is driven by a voltage source of internal resistance Rs = 800 , and
the load impedance is a resistance RL = 1000 . The h-parameters are hie = 1 k ,
hre = 2 × 10 – 4, hfe = 50 and hoe = 25 A/V. Compute the current gain AI, input resistance Ri, voltage again AV and output resistance Ro using exact analysis and using
approximate analysis.
Solution
Exact analysis
Current gain,
– hfe
AI = _________
1 + hoe RL
– 50
= _________________
= – 48.78
1 + 25 × 10 –6 × 103
Input resistance,
hfe hre
Ri = hie – ________
1
hoe + ___
RL
50 × 2 × 10 – 4
= 1000 – ________________ = 990.24 W
1
25 × 10 – 6 + _____
1000
Voltage gain,
RL
AV = AI ___
Ri
1000
= (– 48.78) × ______ = – 49.26
990.24
Output resistance, Ro
hfe hre
Yo = hoe – _______
hie + Rs
50 × 2 × 10 – 4
= 25 × 10 – 6 – ____________
1000 + 800
= 1.94 × 10–5 mho
1
Ro = ___ = 51.42 kW
Yo
Approximate analysis
AI = – hfe = – 50
Ri = hie = 1 kW
hfe RL
50 × 1000
AV = – ______ = – _________ = – 50
1000
hie
Ro = •
Determine Av, AI, Ri, Ro for a CE amplifier using NPN transistor with
hie = 1200 W, hre = 0, hfe = 36 and hoe = 2 × 10– 6 Mhos. RL = 2.5 kW, Rs = 500 W
(neglect the effect of biasing circuit).
Solution
To find current gain (AI):
– hfe
– 36
AI = _________ = _____________________
= – 35.82
1 + hoe RL 1 + 2 × 10– 6 × 2.5 × 103
To find input resistance (Ri):
– hfe hre
Ri = hie – ________ = 1200
1
hoe + ___
RL
To find voltage gain (AV):
RL
2.5 × 103
AV = AI ___ = – 35.82 × ________ = – 74.625
Ri
1200
To find output resistance (Ro):
hfe hre
Yo = hoe – _______
hie + RS
36 × 0
= 2 × 10– 6 – __________ = 2 × 10– 6 mhos
1200 + 500
Therefore,
1
1
Ro = __ = _______
= 500 kW
Yo 2 × 10– 6
The h-parameters of a transistor in the CE amplifier mode are hie = 1100 W,
hre = 2.5 × 10– 4, hfe = 50 and hoe = 25 mmho. Determine the current gain and input
resistance of the amplifier for a load resistance RL = 1 kW.
Solution Given hie = 1100 W, hre = 2.5 × 10– 4, hfe = 50, hoe = 25 m mho and
RL = 1 kW.
(a) The current gain of the amplifier is
– hfe
–50
AI = _________ = _________________
= – 48.78
1 + hoe RL 1 + 25 × 10–6 × 103
(b) The input resistance of the amplifier is
– hre hfe
2.5 × 10– 4 × 50
Zi + hre _______ = 1100 – ______________
= 1087.85 W
1
25 × 10– 6 + 10– 3
hoe + ___
RL
For a CE amplifier, if RL = RS = 1000 W, hie = 1100W, hre = 2.5 × 10– 4, hfe = 50 and
hoe = 25 mA/V, find AI, Ri, AV, AVS and AIS .
Solution Given RL = RS = 1000 W, hie = 1100 W, hre = 2.5 × 10−4, hfe = 50, and
hoe = 25 mA/V
– hfe
– 50
(a) AI = _________ = _________________
1 + hoe RL 1 + 25 × 10–6 × 103
–50
– 50
= ____________
= _____ = – 48.78
–3
1.025
1 + 25 × 10
hie – hfe hre
50 × 2.5 × 10– 4
(b) Ri = _________ = 1100 – _______________
= 1100 – 12.19 = 1088 W
1
25 × 10 –6 + 10 –3
hoe + ___
RL
AI RL
48.78 × 1000
(c) AV = _____ = – ____________ = – 44.83
Ri
1088
AV Ri
– 44.83 × 1088
(d) AVS = _______ = _____________ = – 23.36
Ri + RS
2088
AI RS
48.78 × 1000
(e) AIS = _______ = – ____________ = – 23.36
Ri + RS
2088
The h-parameters of a transistor used in a CE circuit are hie = 1 kW, hre = 10 ×
10– 4, hfe = 50 and hoe = 100 mA/V. The load resistance for the transistor is 1 kW.
Determine Ri, Ro, AV , A1 in the amplifier stage. Assume Rs = 1000 W.
[JNTU 2008]
Solution
(a) Current gain,
hfe
– 50
AI = – _________ = __________________
= – 45.45
1 + hoe RL 1 + 100 × 10– 6 × 103
hfe hre
50 × 10 × 10– 4
(b) Input resistance, RI = hie – ________ = 1 × 103 – _______________
1
1
hoe + ___
100 × 10– 6 + ___3
RL
10
= 954.55 W
RL
103
(c) Voltage gain, AV = AI ___ = – 45.45 × ______ = – 47.61
RI
954.55
(d) Output resistance, Ro:
hfe hre
50 × 10 × 10– 4
Yo = hoe – _______ = 100 × 10– 6 – _____________
= 5 × 10– 5 mho
hie + RS
103 + 103
1
1
Therefore, Ro = ___ = ________
= 20 kW
Yo 5 × 10– 5
Ro × RL 20 × 103 × 1 × 103
(e) Rot = ________ = ________________
= 952.4 W
Ro + RL 20 × 103 + 1 × 103
Approximate Analysis:
(a) AI = – hfe = – 50
(b) Ri = hie = 1 kW
hfe RL
50 × 103
(c) AV = – _____ = – ________
= – 50
hie
1 × 103
(d) Ro = •
(e) Rot = • || RL = RL = 1 kW
Figure 6.12 shows the equivalent circuit of CC amplifier using the approximate
model, with the collector grounded, input signal applied between base and
ground and load connected between emitter and ground.
hie
B
E
(1 + hfe) lb = lL
lE
Ib
Rs
RL
Ve
Vb
+
hfe lb
Vs
–
C
Ri
Current gain,
Ro
Rot
AI = __ = 1 + hfe
Ib
L
(6.40)
From the circuit of Fig. 6.12,
Vb = Ibhie + (1 + hfe) IbRL
Input resistance,
Vb
Ri = ___ = hie + (1 + hfe) RL
Ib
(6.41)
(1 + hfe) Ib RL
Ve
AV = ___ = ____________________
Vb [hie Ib + (1 + hfe) Ib RL]
(1 + hfe) RL
= ________________
[hie + (1 + hfe) RL]
hie + (1 + hfe) RL – hie
= ___________________
[hie + (1 + hfe) RL]
hie
= 1 – _______________
hie + (1 + hfe) RL
Therefore,
hie
AV = 1 – ___
Ri
(6.42)
(6.43)
(6.44)
short circuit current in output terminals
Output admittance (Yo) = _______________________________________
open circuit voltage between output terminals
(1 + hfe) Vs
Short circuit current in output terminals = (1+ hfe) Ib = __________
hie + Rs
Open circuit voltage between output terminals = Vs
1 + hfe
Yo = _______
hie + Rs
and
1 hie + Rs
Zo = __ = _______
1 + hfe
(6.45)
(6.46)
Output impedance including RL, i.e. Ro¢ = Ro || RL.
A voltage source of internal resistance Rs = 900 drives a CC amplifier using load
resistance RL = 2000 W. The CE h-parameters are hie = 1200 , hre = 2 × 10 – 4,
hfe = 60 and hoe = 25 mA/V. Compute the current gain AI the input impedance RI,
voltage gain AV and output resistance Ro using approximate analysis and exact
analysis.
Solution
Conversion formulae:
hic = hie = 1200 W, hfc = – (1 + hfe) = – 61
hrc = 1, hoc = hoe = 25 mA/V
Exact analysis
Current gain,
– hfc
AI = _________
1 + hoc RL
[
]
– (– 61)
= _____________________
= 58.095
1 + 25 × 10–6 × 2 × 103
Input impedance,
Ri = hic + hrc AI RL
= 1200 + (1) (58.095) (2000) = 117.39 kW
Voltage gain,
Output resistance, Ro:
AI RL (58.095) (2 × 103)
AV = ______ = _______________
= 0.9897
Ri
117.39 × 103
hfc hrc
1
Yo = ___ = hoc – _______
Ro
hic + Rs
(– 61) (1)
= 25 × 10–6 – _____________
(1200) + (900)
Ro = 34.396 W
Approximate analysis
Current gain,
AI = 1 + hfe = 1 + 60 = 61
Input impedance,
Ri = hie + (1 + hfe) RL = 1200 + (61) (2000) = 123.2 kW
hie
1200
AV = 1 – ___ = 1 – __________3 = 0.9903
Ri
123.2 × 10
Voltage gain,
1 + hfe
1 + 60
1
Output resistance, Ro: Yo = ___ = _______ = __________ = 0.029 mho
Ro hie + Rs 1200 + 900
Ro = 34.43 W
Figure 6.13 shows the equivalent circuit of CB amplifier using the approximate
model, with the base grounded, input signal applied between emitter and base
and load connected between collector and base.
E
hfeIb
Ie
Ic
C
+
+
Rs
+
Vs
–
Ve
Vc
hie
Ib
–
RL
–
B
B
– hfe Ib
hfe
– Ic –hfe Ib
AI = ___ = ______ = ___________ = ______ = –hfb, from Table 6.3
– (hfe Ib + ) 1 + hfe
Hence, current gain,
hfe
AI = ______ = – hfb
1 + hfe
(6.47)
Ve
–Ib hie
hie
Ri = ___ = ___________ = ______ = hib
Ie – (1 + h )
1 + hfe
(6.48)
fe
Vc – hfe Ib RL hfe RL
AV = ___ = _________ = ______
Ve
– Ib hie
hie
AI, AV and Ri do not differ from exact values by more than 10%.
(6.49)
Vc
Ro = ___ with Vs = 0, RL = •
Ic
With
Vs = 0, Ie = 0 and Ib = 0
Hence,
Ic = 0.
Ro = • using the approximate model.
Therefore,
For a CB transistor amplifier driven by a voltage source of internal resistance
Rs = 1200 , the load impedance is a resistor RL = 1000 . The h-parameters are
hib = 22 , hrb = 3 × 10 – 4, hfb = – 0.98 and hob = 0.5 mA/V. Compute the current
gain AI, the input impedance Ri, voltage gain AV, overall voltage gain AVs, overall
current gain AIs, output impedance Zo, and power gain AP using exact analysis and
approximate analysis.
Solution
Exact analysis
Current gain,
– hfb
– (– 0.98)
AI = _________ = ___________________
= 0.98
1 + hob RL 1 + 0.5 × 10–6 × 1000
Input impedance,
Ri = hib + hrb AI RL
= 22 + (3 × 10 – 4) × 0.98 × 1000 = 22.3 W
Voltage gain,
AIRL 0.98 × 1000
AV = _____ = ___________ = 43.946
Ri
22.3
Overall voltage gain,
AV Ri
43.946 × 22.3
AVs = _______ = ____________ = 0.802
Ri + Rs
22.3 + 1200
Overall current gain,
AI Rs
0.98 × 1200
AIS = _______ = ___________ = 0.962
Ri + Rs 22.3 + 1200
Output admittance,
hfb hrb
(– 0.98) (3 × 10 – 4)
Yo = hob – _______ = 0.5 × 10 – 6 – ________________
22 + 1200
hib + Rs
= 0.7405 × 10– 6 mhos
1
Ro = ___ = 1.35027 MW
Yo
Power gain,
AP = AVAI = 0.98 × 43.946 = 43.06
Approximate analysis
Current gain,
AI = – hfb = 0.98
Input impedance,
Ri = hib = 22 W
Voltage gain,
hfe RL
AV = ______
hie
From Table 6.3,
– hfe
hfb = ______
1 + hfe
Rearranging this equation,
–hfb
hfe = ______
1 + hfb
From the given data,
– (– 0.98)
hfe = ________ = 49
1 – 0.98
From Table 6.3,
hie
hib = ______
1 + hfe
hie = hib (1 + hfe)
= 22 (1 + 49) = 1100 W
49 × 1000
AV = _________ = 44.54
1100
Output impedance,
Ro = •
Overall voltage gain,
AV Ri
44.54 × 22
AVs = _______ = __________ = 0.802
+ Rs 22 + 1200
Overall current gain,
AI Rs
0.98 × 1200
AIs = _______ = ___________ = 0.962
Ri + Rs
22 + 1200
Power gain,
AP = AV AI = 44.54 × 0.98 = 43.65
Calculate the values of input resistance, output resistance, current gain and voltage gain for the common base amplifier circuit shown in Fig. 6.14. The transistor
parameters are hib = 24 , hfb = 0.98, hob = 0.49 mA/V, hrb = 2.9 × 10–4.
Solution
– hfb
AI = _________
1 + hob R¢L
Current gain
where
R¢L = RC || RL = 12 kW || 14 kW = 6.46 kW
– (– 0.98)
AI = _________________________
= 0.977
1 + (0.49 × 10 – 6)(6.46 × 103)
Input lmpedance Ri:
Ri = hib + hrb AIR¢L = 24 + 2.9 × 10–4 × 0.977 × 6.46 × 103 = 25.83 W
Voltage gain AV:
AI R¢L (0.977) × (6.46 × 103)
AV = ______ = ___________________ = 244.34
Ri
25.83
Output resistance Ro:
The output admittance
hfb hrb
1
Yo = ___ = hob – _______ where R¢S = Rs || RE
Ro
hib + R¢S
(– 0.98) (2.9 × 10 – 4)
= 0.49 × 10–6 – _________________ = 0.989 × 10 – 6 mho
24 + 600 || 6000
1
Ro = ___ = 1.011 MW
Yo
R¢s = Ro || R¢L = 1.011 × 10–6 || 6.46 × 103 = 6.42 kW
A circuit that increases the amplitude of the given input signal is an amplifier. A
small a.c. signal fed to the amplifier is obtained as a larger a.c. signal of the same
frequency at the output. Amplifiers constitute an essential part of radio, television
and other communication circuits. In discrete circuits, Bipolar junction transistors
and field effect transistors are commonly used as amplifying elements. Depending
on the nature and level of amplification and the impedance matching requirements, different types of amplifiers can be considered and they are discussed in this
chapter.
Amplifiers can be classified as follows:
1. Based on the transistor configuration
(a) Common emitter amplifier
(b) Common collector amplifier
(c) Common base amplifier
2. Based on the active device
(a) BJT amplifier
(b) FET amplifier
3. Based on the Q-point (operating condition)
(a) Class A amplifier
(b) Class B amplifier
(c) Class AB amplifier
(d) Class C amplifier
4. Based on the number of stages
(a) Single stage amplifier
(b) Multi-stage amplifier
5. Based on the output
(a) Voltage amplifier
(b) Power amplifier
6. Based on the frequency response
(a) Audio frequency (AF) amplifier
(b) Intermediate frequency (IF) amplifier
(c) Radio frequency (RF) amplifier
7. Based on the bandwidth
(a) Narrow band amplifier (normally RF amplifier)
(b) Wide band amplifier (normally video amplifier)
Single stage amplifiers have only one amplifying device, say, BJT in CE, CC or
CB configuration or FET in CS, CD or CG configuration.
Figure 6.15 shows the circuit of a single stage CE amplifier using NPN transistor. The emitter-base junction is forward biased by power supply VBB and collector-base junction is reverse biased by power supply VCC, so that the transistor
remains in the active region throughout its operation. The Quiescent (Q) point
is determined by VCC, RB and RC. Input signal is applied to the base-emitter
circuit and the amplified output signal is taken from the CE circuit. C1 and C2
are coupling capacitors to provide d.c. isolation at the input and output of the
amplifier.
Instead of using two power supplies, the same bias conditions can be set up in
the CE amplifier circuit with a single power supply as shown in Fig. 6.16.
Referring to Fig. 6.16, when no a.c. signal input is given, i.e. under d.c.
conditions,
VCC – VBE VCC
IB = _________ ª ____
(6.50)
RB
RB
IC = b IB
VCE = VCC – ICRC
(6.51)
(6.52)
When a sinusoidal a.c. signal is applied at the input terminals of the circuit, during the positive half cycle the forward bias of the base-emitter junction VBE is
increased, resulting in an increase in IB. The collector IC is increased by b times
the increase in IB. From Eqn. (6.29), VCE is correspondingly decreased, i.e. the
output voltage gets decreased as shown in Fig. 6.17.
Thus, in a CE amplifier, a positive going input signal is converted into a negative
going output signal, i.e. a 180° phase shift is introduced between the output and
input signal and further the output signal is an amplified version of the input
signal.
(i)
(ii)
(iii)
(iv)
(v)
(vi)
Large current gain (AI)
Large voltage gain (AV)
Large power gain (AP = AI ◊ AV)
Voltage phase shift of 180°
Moderate input impedance
Moderate output impedance
Figure 6.18 shows the circuit of a single-stage CC amplifier using an NPN transistor. The emitter-base junction is forward biased by power supply VEE and
collector-base junction is reverse biased by VCC, so that the transistor remains in
the active region throughout its operation.
Input signal is given to the base-collector circuit and the output signal is taken
from the emitter-collector circuit.
Instead of using two power supplies, the required bias condition can be set up in
a CC amplifier circuit with a single power supply as shown in Fig. 6.19.
C1 and C2 are coupling capacitors to provide d.c. isolation at the input and output of the amplifier.
From Fig. 6.19,
Output voltage
Vo = IE RE = bIB RE
(6.53)
When a sinusoidal a.c. signal is applied at the input, during the positive half
cycle of the signal applied, the base potential VB increases, thereby increasing
the base current IB. Hence, emitter current IE = IC + IB increases and voltage
drop across RE, i.e. the output voltage increases.
Thus, a positive going input signal results in a positive going output signal as
shown in Fig. 6.20. Hence, in a CC amplifier, input and output signals are in
phase with each other and further the voltage gain is approximately unity.
As the output signal taken at the emitter terminal almost follows the input signal, the CC amplifier is called as the emitter follower.
(i) High current gain
(ii) Voltage gain of approximately unity
(iii) Power gain approximately equal to current gain
(iv) No current or voltage phase shift
(v) Large input impedance
(vi) Small output impedance.
Figure 6.21 shows the circuit of a single stage CB amplifier using an NPN
transistor. The emitter-base junction is forward biased by power supply VEE,
whereas the collector-base junction is reverse biased by VCC, so that the transistor remains in the active region throughout its operation.
Input signal applied to the emitter-base circuit and output signal is taken from
collector-base circuit. The output voltage (= VCB) is given by the equation
Vo = VCC – ICRC
(6.54)
When a sinusoidal a.c. signal is applied at the input, during the positive half
cycle of the applied signal, the amount of forward bias to base-emitter junction
is decreased, resulting in a decrease in IB. As a result IE (ª bIB) and hence, IC also
decreases.
From Eqn. (6.61), the drop ICRC decreases, hence Vo = VCB correspondingly
increases. Thus, a positive half cycle appears at the output without any phase
reversal as shown in Fig. 6.22.
(i)
(ii)
(iii)
(iv)
(v)
(vi)
Current gain of less than unity
High voltage gain
Power gain approximately equal to voltage gain
No phase shift for current or voltage
Small input impedance
Large output impedance.
The circuit of Fig. 6.23 shows a CE amplifier in fixed bias configuration. The
a.c. equivalent circuit of the amplifier can be drawn by the steps mentioned as
follows:
(i) Remove the d.c. effects of power supply (VCC) by grounding them.
(ii) Replace the capacitors (C1 and C2) by short circuits.
Thus, the circuit of Fig. 6.23 reduces to the a.c. equivalent circuit of Fig. 6.24.
Substituting the approximate hybrid model for the transistor in Fig. 6.24, the
circuit reduces to that shown in Fig. 6.25.
From the circuit of Fig. 6.25, the equations for input impedance, output impedance, voltage gain and current gain can be derived.
Zi = RB || hie
If
(6.55)
RB >> hie,
Zi ª hie
(6.56)
It is the impedance determined with Vi = 0. With Vi = 0,
Ib = 0 and hfe Ib = 0 indicating an open circuit equivalence for the current
source.
Hence,
Zo = RL (= RC)
Voltage gain,
Vo
AV = ___
Vi
li
B
+
lc
lb
C
+
Io
hfelb
Vi
RB
–
hie
E
Vo
RC
E
lL
–
Zo
Zi
Vo = – IoRC
Substituting
Io = hfe Ib
Vo = –hfe IbRC
Assuming that
RB >> hie,
Ii ª Ib and
Therefore,
Vi = Ib hie
– hfeIbRC
AV = ________
Ib hie
– hfeRC
= _______
hie
(6.57)
As hfe and hie are positive, AV is negative. The negative sign indicates a 180°
phase shift between input and output signals.
IL
AI = __
Ii
– Io – hfeIb
= ___ ª ______ = – hfe
Ii
Ib
(6.58)
Note: The sign for AI will be positive if AI is defined as the ratio of Io to Ii.
Determine the input impedance, output impedance, voltage gain and current gain
for the CE amplifier of Fig. 6.26. The h-parameters of the transistor of hfe = 60,
hie = 500 at IC = 3 mA.
Solution
RB = 220 kW >> hie = 500 W
From h-parameter model
Zi = hie = 500 W
12 V
220 kW
5.1 kW
0.1 mF
Vo
0.1 mF
Vi
Zo = RC = 5.1 kW
AV
– hfeRC – 60 (5.1 × 103)
______
=
= _____________
500
hie
= – 612
AI = – hfe = – 60
A simple and effective way to provide voltage gain stabilisation in a CE amplifier is to add an emitter resistor RE which provides feedback as shown in Fig.
6.27. An approximate solution for this arrangement can be obtained by considering the simplified hybrid model equivalent circuit.
Ic – hfe Ib
AI = – __ = ______ = – hfe
Ib
Ib
Thus, the current gain is equal to the short circuit current gain with RE = 0 and
is unaffected by RE.
Vi [ hie + (1 + hfe) RE ]Ib
Ri = __ = __________________
Ib
Ib
(6.59)
Ri = hie + (1 + hfe) RE
Comparing with Eqn. (6.38), the input resistance is augmented by (1 + hfe)
RE and may be very much larger than hie. For example, with RE = 1 kW, hfe = 60,
(1 + hfe) RE = 61 kW >> hie ª 1 kW.
VCC
RL = (RC)
Vo
C
B
E
Rs
RE
+
Vs
–
(a)
B
lC
hie
C
hfe lb
E
Rs
RE
Vi
+
RL
Vc
(1 + hfe) lb
Vs
–
Ri
N
N
(b)
Hence, RE greatly increases the input resistance of the amplifier.
From Eqn. (6.24),
hfe RL
RL
AV = AI ___ = – _______________
Ri
hie + (1 + hfe)
(6.60)
Thus, the addition of emitter resistor RE greatly reduces the voltage amplification as Ri has increased from hie to hie + (1 + hfe)RE. This reduction in gain is
compensated by stability improvement.
If (1 + hfe) RE >> hie and hfe >> 1
hfe RL
– RL
AV ª – __________ ª _____
(1 + hfe) RE
RE
Then
(6.61)
Hence, under these approximations AV is completely stable and independent of
all transistor parameters provided stable resistances are used for RL and RE.
Output resistance Ro with RL excluded is infinite and
with RL included, it is equal to RL and is independent of RE.
A CE amplifier uses load resistor RC = 2 k in the collector circuit and is given
by the voltage source Vs of internal resistance 1000 . The h-parameters of the
transistor are hie = 1300 , hre = 2 × 10–4, hfe = 55 and hoe = 22 mhos. Neglecting
the biasing resistors, compute the current gain AI, input resistance Ri, voltage gain
AV, output resistance Ro and output terminal resistance RoT for the following values of emitter resistor RE inserted in the emitter circuit: (a) 200 , (b) 400 , and
(c) 1000 . Use the approximate model for the transistor if permissible.
Solution
(a) For
RE = 200 W
hoe × (RE + RC) = (2 × 103 + 200) × (22 × 10–6) = 0.0484
Since hoe × (RE + RC) < 0.1, the approximate model is permissible.
AI = – hfe = –55
Ri = hie + (1 + hfe) RE = 12.5 kW
RC
AV = AI ___
2000
= –55 × ______ = – 8.8
12,500
Output resistance,
Ro = •
Output terminal resistance, ROT = Ro | | RC = 2 kW
(b) For
RE = 400 W
hoe × (RE + RC) = (2 × 103 + 400) × (22 × 10–6) = 0.0528
Since hoe × (RE + RC) < 0.1, approximate model is permissible.
AI = – hfe = – 55
Ri = hie + (1 + hfe) RE = 23.7 kW
RC
AV = AI ___
Ri
2000
= – 55 × ______ = – 4.654
23,700
Output resistance,
Ro = •
Output terminal resistance, ROT = Ro | | RC = 2 kW
(c) For
RE = 1000 W
Since hoe × (RE + RC) < 0.1, approximate model is permissible.
Al = –hfe = –55
Ri = hie + (1 + hfe) RE = 57.3 kW
RC
AV = AI ___
Ri
2000
= – 55 × ______ = –1.92
57,300
Output resistance,
Ro = •
Output terminal resistance, ROT = Ro || RC = 2 kW
The a.c. equivalent circuit for this amplifier shown in Fig. 6.28 can be drawn by
following the steps mentioned earlier.
By substituting the hybrid equivalent circuit for the transistor of Fig. 6.29, the
circuit reduces to that shown in Fig. 6.30.
Current through the emitter resistor RE is
Ie = Ib + hfe Ib
= (1 + hfe)Ib
From Fig. 6.30,
Vi = Ibhie + (1 + hfe) IbRE
Vi
Zb = __ = hie + (1 + hfe)RE
Ib
(6.62)
Zb ª hie + hfeRE
(6.63)
As hfe >> 1,
Normally,
hfeRE >> hie leading to
Zb ª hfeRE
(6.64)
Zi = RB || Zb
(6.65)
From the circuit of Fig. 6.30,
With Vi = 0, Ib = 0, hfeIb = 0 indicating open circuit for
current source.
Hence,
Zo = RC
(6.66)
Vo
AV = ___
Vi
From the circuit of Fig. 6.30,
( )
Vi
Vo = –IoRC = – (hfeIb)RC = – hfe ___ RC
Zb
li
B
lb
+
lo
hfelb
hie
Vi
RC
RB
Vo
E
RE
le = (1 + hfe)lb
–
Zi
Zb
Zo
Vo – hfeRC
AV = ___ = ______
Vi
Zb
With
(6.67)
Zb ª hfeRE,
– hfeRC – RC
AV = ______ = _____
RE
hfeRE
(6.68)
– Io
AI = ____
Ii
Io = hfeIb
where
RB
Ib = Ii ________
RB + Zb
Therefore,
RB
Io = hfe Ii ________
RB + Zb
– hfeRB
– Io
AI = ___ = ________
Ii
RB + Zb
(6.69)
For the circuit shown below hfe = 100, hie = 1 kW and other two parameters are
Vo
negligible if Re = 1 kW. Find the value of An = ___
Vi
V
o
AVS = ___, Rif = Rof
Vs
Rc
10 × 103
Solution We know that AV = ___ = – ________
= – 10
Re
1 × 103
Rif = RB || hfe Re = 50 kW
Rif
Vo
50 × 103
AVS = ___ = AV ◊ ________ = (– 10) ◊ ________3 = – 9.8
Vs
RS + Rif
51 × 10
A transistor with hie = 1.1 KW, hfe = 50, hre = 205 × 10– 4, h0e = 25 mA/V is connected
in CE configuration as shown in Fig. 6.32. Calculate AI, AV, RI, RO.
[JNTU April/May 2007]
KW
Solution
As per Miller’s theorem
RF
RF1 = ______
1 – AV
RF
RF2 = ______
1
1 – ___
AV
Assume the gain (AV) is much larger than unity, i.e., AV >> 1.
and
200
RF2 = ______ ª 200 kW
1
1 – ___
AV
Effective load resistance, R¢L = RF 2 || RL = 200 kW || 10 kW = 9.52 kW
We know that
– hfe
AI = _________
1 + hoe R¢L
– 50
= _______________________
= – 40.38
1 + 25 × 10– 6 × 9.52 × 103
Input resistance is
Ri = hie + hre AI R¢L
= 1.1 kW + 2.5 × 10– 4 × (– 40.38) × 9.52 × 103
= 1 kW
Voltage gain,
Output resistance,
AI R¢L – 40.38 × 9.52 × 103
AV = ______ = _________________
= – 384.49
Ri
1 × 103
1
RO = ___________
hfe hre
hoe – _______
hie + Rs
1
= ____________________________
= 4.032 kW
50 × 205 × 10– 4
– 6 __________________
25 × 10 –
1.1 × 103 + 10 × 103
RF
200 × 103
RF1 = ______ = __________ = 520 W
1 – AV 1 + 384.49
R¢I = Ri || RF1 = 1kW || 520 W = 343 W
Consider the CE amplifier of Fig. 6.33 in which the base bias is obtained by two
resistors R1 and R2.
By substituting the h-parameter equivalent for the transistor, the a.c. equivalent
circuit can be obtained directly as shown in Fig. 6.34. As capacitor CE bypasses
RE in the operating frequency range RE is omitted in the equivalent circuit.
Let
R1R2
RB = R1 || R2 = _______
R1 + R2
Zi = RB || hie
(6.70)
Zo = RC
(6.71)
Vo
AV = ___
Vi
Vo = – hfe Ib RC
and Vi = Ib hie
– hfeIb RC
AV = ________
Ib hie
– hfeRC
= ______
hie
(6.72)
– Io
AI = ___
Ii
Substituting
Io = – hfe Ib
where
RB
Ib = Ii _______
RB + hie
Therefore,
RB
Io = – hfe Ii _______
RB + hie
RB
AI = – hfe _______
RB + hie
(6.73)
Determine the input impedance, output impedance, voltage gain and current gain of
the CE amplifier of Fig. 6.35 using h-parameter equivalents for the transistor with
hie = 3.2 k and hfe = 100 at the operating conditions.
VCC = 16 V
RC
40 kW
4 kW
Vo
1 mF
1 mF
Vi
4.7 kW
R2
RE
1.2 kW
CE = 10 mF
Zi = RB || hie
RB = R1 || R2 = 40 kW || 4.7 kW
= 4.2 kW
Zi = 4.2 kW || 3.2 kW = 1.82 kW
Zo = RC = 4 kW
– hfeRC
AV = ______
hie
– 100 × 4 × 103
= _____________
= –125
3.2 × 103
– hfeRB
AI = _______
RB + hie
– 100 × 4.2 × 103
= _______________3 = –56.76
(4.2 + 3.2) × 10
Figure 6.36 shows the circuit of a CB amplifier.
By applying the steps mentioned earlier to draw the a.c. equivalent circuit the
circuit of Fig. 6.36 reduces to the circuit of Fig. 6.37.
Substituting the approximate hybrid model for the transistor in CB connection
the circuit of Fig. 6.48 reduces to the circuit of Fig. 6.38.
Zi = RE || hib
(6.74)
Zo = RC
(6.75)
Vo
AV = ___
Vi
Vo = – Io RC = – hfb Ie RC
Assuming that RE >> hib,
Ie ª Ii and Vi = Iehib
Vo – hfb RC
AV = ___ = _______
Vi
hib
(6.76)
– Io – hfb Ie
AI = ____ ª ______
Ii
Ie
AI = – hfb
Note: As hfb is negative, AV and AI are positive for CB configuration.
(6.77)
Figure 6.39 shows the Emitter Follower circuit in which the output is taken from
the emitter terminal with respect to ground and the collector terminal is directly
connected to VCC. Since VCC is at signal ground in the a.c. equivalent circuit as
shown in Fig. 6.39, the emitter follower circuit is also called common collector
amplifier.
VCC
R1
Rs
CC
Vo
+
–
Vs
R2
RE
The small signal current gain, Ai, is defined as the ratio of output load current IL to input current Ib.
IL – Ie (1 + hfe)Ib
Ai = __ = ___ = _________ = 1 + hfe
Ib
Ib
Ib
where
Ie = – (1 + hfe)Ib
From Fig. 6.40, the input resistance looking into the base is
denoted as Ri, that is,
Ib
Ie
B
E
+
hie
IL
(1 + hfe)lb
Rs
VI
+
Vc
–
R1 || R2
hfe lb
RL
–
C
R ¢i
C
Ri
Ro
R o¢
Vb
Ri = ___ = hie + (1 + hfe)RL
Ib
where
Vb = hie Ib + (1 + hfe)Ib RL
Therefore, the input resistance seen by the signal source R¢i is
R¢i = Ri || R1 || R2
The small signal voltage gain, AV, is defined as the ratio of output voltage, Vo, to input voltage, Vi. That is,
Vo AiRL Ri – hie
hie
AV = ___ = _____ = ______ = 1 – ___
Vi
Ri
Ri
Ri
Therefore, AV ª 1 but always slightly less than one since Ri >> hie.
From Fig. 6.40, the output admittance looking back
into the emitter is denoted as Y0, that is,
hfchrc
Y0 = hoc – _______
hic + R¢S
where
R¢s = Rs || R1 || R2
Neglecting hoc and assuming hrc = 1, hfc = – (1 + hfe), we get
– hfc
Y0 = _______
hic + R¢s
– hic + R¢s hie + R¢s
R0 = _________ = _______
hfc
1 + hfe
Hence, the output resistance looking back into the output terminals, R¢o, is the
load resistance, RL, in parallel with the resistance looking back into the emitter,
Ro, that is,
Therefore,
R¢o = Ro || RL
For the Emitter Follower shown in Fig. 6.39, the circuit parameters are Rs = 500
, R1 = R2 = 50 k , RL = 2 k , hfe = 100 and hie = 1.1 k . Determine the input
resistance, output resistance, current gain and voltage gain.
Solution
(a) To determine input resistance (Ri)
Ri = hie + (1 + hfe)RL = 1.1 × 103 + (1 + 100) × 2 × 103 = 203.1 kW
R¢i = Ri || R1 || R2 = 203.1 × 103 || 50 × 103 || 50 × 103 = 22.26 kW
(b)To determine output resistance (R0)
hie + R¢s 1.1 × 103 + (500 || 50 × 103 || 50 × 103)
R0 = _______ = _________________________________
1 + 100
1 + hfe
1.59 × 103
= _________ = 15.74 W
101
R¢o = Ro || RL = 15.74 || 2 × 103 = 15.62 W
(c) To determine current gain (Ai)
Ai = 1 + hfe = 1 + 100 = 101
(d) To determine voltage gain (AV)
hie
1.1 × 103
AV = 1 – ___ = 1 – __________3 = 0.9946
Ri
203.1 × 10
Calculate the current gain AI, voltage gain AV, input resistance Ri and output resistance Ro for the common collector amplifier shown in Fig. 6.41. The transistor
parameters are hic = 1.4 k , hfc = 100, hrc = 20 A/V and hoc = 20× 10–6.
+ VCC
R1
20 kW
C1
C2
Rs
+
21 kW
R2
20 kW
RE
Vs
10 kW
RL
40 kW
–
Solution
where
– hfc
Current gain AI = _________
1 + hoc R¢L
R¢L = RE || RL = (40 || 10) kW = 8 kW
– (–100)
100
AI = _____________________
= ____ = 86.2
1 + (20) × 10–6 × 8 × 103 1.16
Input resistance
Ri = hic + hrcAIR¢L
= 1.4 × 103 + (1) (86.2) (8 × 103) = 691 kW
AI R¢L (86.2)(8 × 103)
AV = _____ = _____________
= 0.998
RI
691 × 103
Voltage gain
1
Output resistance, Ro = ___
Yo
hfc hrc
Yo = hoc – _______
hic + R¢s
where
R¢s = Rs || R1 || R2 = 1|| 20 || 20 kW = 0.9 kW
(– 100)(1)
Yo = 20 × 10–6 – _____________________
= 43478.26 × 106
3
3
(1.4 × 10 ) + (0.9 × 10 )
Ro = 22.99 W
R¢o = Ro || R¢L
= (22.99) || (8 × 103) = 22.92 W
In the common collector circuit (Fig. 6.42), the transistor parameters are hic = 1.2
kW and hfc = – 101. Calculate input and output resistances, voltage gain and current
gain.
[JNTU May/June 2006]
+ VCC
R1
C1
C2
R3
R2
RL
Vs
˜
Solution
Given
hic = 1.2 kW and hfc = – 101
Current gain,
AI = – hfc = 101
Input impedance
Ri = hie – hfc RL = 1.2 × 103 – (– 101)(20 × 103)
= 2021.2 kW
hic
1.2 × 103
Av = 1 – ___ = 1 – ___________3 = 0.99941
Ri
2021.2 × 10
Voltage gain
hic + Rs 1.2 × 103 + 1 × 103
Output impedance Ro = _______ = _________________ = 21.782 W
101
– hfc
For the given circuit hfe = 100, hie = 1 kW, hre = hoe = 0. Determine with Re = 0, (i)
VS
V0
V0
R¢i = ___ where IS = ___ (ii) AVS = ___ (iii) Ri and (iv) R¢0
IS
RS
VS
[JNTU Dec. 2004]
VCC
10 K W
100 K
V0
Is
Rs = 1 K W
R¢o
R¢i
Solution
The h-parameter equivalent model for the given circuit is shown in
Fig. 7.43(b).
Rs
Is
hie
Z1
Vs
Ic
Ib
RfeIb
Io
Z2
Ri
Vo
E
R¢i
Ri
R¢of
R¢o
Here, the current source is converted into voltage source and resistance
100 kW is split using Millers theorem.
A
Z2 = 100 × 103 × _____ = 100 kW (since A >> 1)
A–1
– IC
Ai = ____ = –hfe = – 100
Ib
Ri = – hie = 1000 W
Vo AiR¢L
Av = ___ = _____
Vi
Ri
Here
R¢L = Z2||RL = 100 kW||10 kW = 9.09 kW
Therefore,
– 100 × 9.09 × 103
Av = ________________ = – 909
1000
R¢i = Z1||Ri
Here
100 × 103 100 × 103
Zi = _________ = _________ = 109.89
1–A
1 + 909
Therefore,
R ¢i = 109.89||1000 = 99 W
Vo Vo Vi
Avs = ___ = ___ × ___
VS Vi VS
Here
Therefore,
Vi
R ¢i
99
___
= ________ = _________ = 0.09
VS R¢i + RS 99 + 1000
AVS = – 909 × 0.09 = – 81.81
Io Io IC Ib
Ais = __ = __ × __ × __
IS IC Ib IS
Here,
Therefore,
Output impedance,
Io ________
– Z2
– 100 × 103
__
=
= __________________
= – 0.909
IC Z2 + RL 100 × 103 + 10 × 103
Ib _______
Z1
109.89
__
=
= _____________ = 0.099
IS Z1 + Ri 109.89 + 1000
Io
Ais = __ = – 0.909 × 100 × 0.099 = –9
IS
Ro = •
R¢o = •||R¢L = 9.09 kW
The h-parameters of a transistor used in a CE circuit are hie = 1.0 kW, hre = 10
× 10– 4, hfe = 50, hoe = 25 × 10–6. The load resistance for the transistor is 1 kW
in the collector circuit. Determine Ri, Ro, AV, Ai in the amplifier stage. Assume
RS = 1000 W.
[JNTU June 2008]
Solution
– hfe
– 50
(a) Current Gain, Ai = _________ = __________________
= – 48.78
1 + hoe RL 1 + 25 × 10– 6 × 1000
(b) Input resistance, Ri = hfe + hre Ai RL = 1000 + 10 × 10– 4 × (– 48.78) × 1000
= 951.22 W
AiRL – 48.78 × 1000
(c) Voltage gain, Av = _____ = _____________ = – 51.28
Ri
951.22
AV Ri
– 51.28 × 951.22
(d) Overall voltage gain, Avs = _______ = ______________ = – 25
Ri + RS
951.22 + 1000
AiRS
– 48.78 × 1000
(e) Overall current gain, Ais = _______ = _____________ = – 25
Ri + RS 951.22 + 1000
hfe hre
50 × 10 × 10– 4
(f) Output admittance, Yo = hoe – _______ = 25 × 10– 6 – _____________ = 0 W
1000 + 1000
hie + RS
1
(g) Output impedance. Ro = 1/Yo = __ = •
0
R¢0 = R0 ||RL = •|| 1 × 103 = 1 kW
A transistor used in CB circuit has the following set of h parameters hib = 20 W, hfb
= – 0.98, hrb = 3 × 10–4, hob = 0.5 × 10– 6. Find the values of Ri, Ro, Ai and AV if RS
= 600 kW and RL = 1.5 kW.
[JNTU June 2008]
Solution
– hfb
(a) Current gain, Ai = _________
1 + hob RL
– (– 0.98)
= ______________________
= 0.979
1 + 0.5 × 10– 6 × 1.5 × 103
(b) Input resistance, Ri = hib + hrb Ai RL
= 20 + 3 × 10– 4 × 0.979 × 1.5 × 103 = 20.44 kW
Ai RL 0.979 × 1.5 × 103
(c) Voltage gain, Ai = _____ = _______________ = 71.844
Ri
20.44
1
(d) Output resistance, Ro = ____________
hfb hrb
hob – _______
hib + RS
1
= __________________________
= 1.0265 MW
–4
(–
0.98)
(3
×
10
)
________________
0.5 × 10– 6 –
20 + 600
R¢0 = Ro ||RL = 1.0265 × 106 || 1.5 × 103 = 1.4978 kW
A transistor used in CE amplifier connection has the following set of h parameters,
hie = 1 kW, hre = 5 × 10– 4, hoe = 2 × 10– 5 mho, Rs = 15 kW, and RL = 5 kW. Determine
input impedance, output impedance, current gain and voltage gain. Assume hfe =
100.
[JNTU June 2008]
Solution
– hfe
– 100
(a) Current gain, Ai = _________ = ________________
= – 90.9
1 + hoe RL 1 + 2 × 10– 5 × 103
(b) Input impedance, Ri = hie + hre AiRL
= 1000 + 5 × 10–4 × (– 90.9) × 5 × 103 = 772.75 kW
Ai RL – 90.9 × 5 × 103
(c) Voltage gain, Av = _____ = ______________ = – 588.16
Ri
772.75
AV R i
– 588.16 × 772.75
(d) Overall voltage gain, Avs = _______ = ________________3 = – 28.8
Ri + RS 772.75 + 15 × 10
AiRS
– 90.9 × 15 × 103
(e) Overall current gain, Ais = _______ = ________________3 = – 86.45
Ri + RS 772.75 + 15 × 10
(f) Output resistance,
1
1
Ro = ____________ = ______________________
= 59.26 kW
hfe hre
100 × 5 × 10–4
–5 _____________
_______
2 × 10 –
hoe –
1000 + 15000
hie + RS
R¢0 = R0 ||RL = 59.26 × 103|| 5 × 103 = 4.61 kW
For a CB configuration, what is the maximum value of RL for which Ri does not
exceed 50 W? Transistor parameters are hib = 21.6 W, hrb = 2.9 × 10–4, hfb = – 0.98
and hob = 0.49 mA/V.
[JNTU June 2008]
Solution
– hfb
Ri = hib + hrb AiRL, where Ai = _________
1 + hob RL
– hfb
Ri = hib = hrb × _________ × RL
1 + hob RL
Hence,
hib – hrb hfb
= _________ = 50 W
1
___
+ hob
RL
– [29 × 10– 4 × (– 0.98)]
(50 – 21.6) = ____________________ = 28.4
1
___
+ 0.49 × 10– 6
RL
284.2 × 10– 6
1
___
= 0.49 × 10– 6 = ___________
RL
28.4
284.2 × 10– 6
1
___
= ___________ = – 0.49 × 10– 6 = 9.517 × 10– 6
RL
28.4
Therefore, RL = 105 W
The maximum value of RL for which Ri does not exceed 50 W is 105 kW
A transistor used in a CC circuit as shown in Fig. 6.44 has the following set of h
parameters.
hic = 2 kW, hfc = – 51, hrc = 1, hrc = 1, hoc = 25 × 10– 6
Find the values of input and output resistances, current and voltage gains of the
amplifier stage. Use the approximate analysis.
[JNTU Sep. 2008]
+VCC
R1
10 kW
R5
1 kW
Vo
Vs
R2
10 kW
5 kW
RE
Solution
The h-parameter equivalent model for the given circuit is shown in
Fig. 6.44(b).
Ib
hic
Ie
IL
Rs
Is
R1
R 2 Vb
hrc Vo
hfc Ib
+
1
hoc
RE
Vs
–
R¢i
Ri
– fc
Ie
(a) Current gain, Ai = __ = ________
Ib 1 + hcc RI
Here, RL = RE = 5 kW
– (– 51)
= ____________________
= 45.33
1 + 25 × 10– 6 × 5 × 103
(b) Input resistance, Ri = hic + hrc Ai RL
= 2000 + 1 × 45.33 × 5000 = 228.65 kW
(c) Overall input resistance, R¢i = Ri || R1 || R2
= 228.65 × 103 || 10 × 103 || 10 × 103 = 4.893 kW
Ro
R¢o
Vo
Ai RL 45.33 × 5000
(d) Voltage gain, Av = _____ = ____________3 = 0.991
Ri
228.65 × 10
Vo Vo Vb
(e) Overall voltage gain, Avs = ___ = ___ = ___
VS Vb VS
R¢i
4.893 × 103
= AV × _______ = 0.991 × _________________
= 0.823
R¢1 + RS
4.893 × 103 + 1000
IL IL Ie Ib
(f) Overall current gain, Ais = __ = __ × __ × __
IS Ie Ib IS
I__
L
Here, = – 1
Ie
Ie
Therefore, __ = – Ai = – 45.33
Ib
Ib _______
RB
R1 || R2
10 || 10
5
__
=
= ___________ = ______________ = __________ = 21.4 × 10– 3
IS RB + Ri R1 || R2 + Ri 10 || 10 + 228.65 5 + 228.65
IL
Therefore, Ai (for circuit) = __ = (– 1) × (– 45.33) × 21.4 × 10– 3 = 0.970
IS
1
(g) Output resistance, Ro = ____________
hfc hrc
hoc – _______
hic + RS
Here, R¢S = RS || R1 || R2
1
Therefore, Ro = ________________________ = 55.478 W
(– 51) × 1
25 × 10– 6 – ______________
(2000 + 833.33)
R¢o = Ro || RL = 55.478 || 5000 = 54.87
A transistor used in a CB amplifier has the following values of h-parameters. hib =
28 W, hfb = – 0.98, hrb = 5 × 10– 4 and hob = 0.34 × 10– 6 S. Calculate the values of Ri,
Ro, Ai and Av, if the load resistance is 1.2 kW. Assume source resistance as zero.
[JNTU Sep. 2008]
Solution
– hfb
– (– 0.98)
(a) Current gain, Ai = _________ = ____________________
= 0.9796
1 + hob RL 1 + 0.34 × 10– 6 × 1200
(b) Input resistance, Ri = hib + hrb + AiRL
= 28 + 5 × 10– 4 × 0.9796 × 1200 = 28.588 W
Ai RL 0.9796 × 1200
(c) Voltage gain, Av = _____ = _____________ = 41.12
Ri
28.588
(d) Overall voltage gain, Avs = Av = 41.12
1
(e) Output resistance, Ro = ____________ (since RS = 0)
hfb hrb
hob – _______
hib + RS
1
= ____________________________
= 56 kW
(– 0.98) (5 × 10– 4)
– 6 ________________
0.34 × 10 –
28
R¢o = Ro || RL = 56 × 103 || 1.2 × 103 = 1.175 kW
The h-parameters of a transistor used as an amplifier in the CE configuration are hie
= 800 W, hfe = 50, hoe = 80 × 10– 6 mho and hre = 5.4 × 10– 4. If the load resistance is
5 kW, determine the current gain, input impedance, output impedance, voltage gain
and power gain.
[JNTU Sep. 2008]
Solution
– hfe
– 50
(a) Current gain, Ai = _________ = ____________________
= – 35.71
1 + hoe RL 1 + 80 × 10– 6 × 5 × 103
(b) Input impedance,
Ri = hie + hre Ai RL = 800 + 5.4 × 10– 4 × (– 35.71) × 5 × 10– 3 = 703.6 W
AiRL – 35.71 × 5 × 103
(c) Voltage gain, Av = _____ = _______________ = – 253.77
Ri
703.6
(d) Output resistance,
1
1
Ro ____________ = ________________________
= 21.62 kW
hfe hre
50 × 5.4 × 10– 4
– 6 _____________
_______
80
×
10
–
hoe –
800 + 0
hie + RS
(e) Power gain = Voltage gain × Current gain = – 253.77 × – 35.71 = 9062
For a CE configuration, what is the maximum value of RS for which Ro differs by
no more than 10 percent of its value for RS = 0? Transistor parameters are hie = 1.2
[JNTU Sep. 2008]
kW, hre = 2.5 × 10– 4, hfe = 50 and hoe = 24 mA/V.
Solution
In CE configuration, if RS increases, then RO decreases slightly. If Ro decreases
1
by 10%, Yo = ___ increases by 11%.
Ro
For RS = 0,
hfe hre
50 × 2.5 × 10– 4
Yo = hoe – ______ = 24 × 10– 6 – _____________ = 12.64 × 10– 6
1100
hie + 0
Thus
Yo(New) = 1.11 × Yo = 1.11 × 12.64 × 10– 6 = 14 × 10– 6
50 × 2.5 × 10– 4
Yo(New) = 14 × 10– 6 = 24 × 10– 6 – _____________
1100 + RS
50 × 2.5 × 10– 4
10 × 10– 6 = _____________
1100 + RS
50 × 2.5 × 10– 4 – 10 × 10– 6 × 1100
RS = ______________________________
= 150 W
10 × 10– 6
RL = 1 kW. The
load impedance is RL = 1 kW. The transistor parameters are hib = 22 W, hfb = – 0.98,
hrb = 2.9 × 10– 4, hob = 0.5 mA/V. Compute current gain, voltage gain, input and
output impedance of the amplifier.
[JNTU June 2009]
Solution
– hfb
– (– 0.98)
(a) Current gain, Ai = _________ = ___________________
= 0.9795
1 + hoe RL 1 + 0.5 × 10– 6 × 1000
(b) Input impedance,
Ri = hib + hrb AiRL = 22 + 2.9 × 10– 4 × 0.9795 × 1000 = 22.284 W
AiRL 0.9795 × 1000
(c) Voltage gain, Av = _____ = _____________ = 43.955
Ri
22.284
(d) Output resistance,
1
1
Ro = ____________ = ____________________________
= 1.285 MW
hfb hrb
(– 0.98) (2.9 × 10– 4)
_______
– 6 _________________
hoe –
0.5 × 10 –
hib + RS
22 + 1000
R¢o = Ro || RL = 1.285 × 106 || 1 × 103 = 999.22 W
A transistor is connected in CC configuration and its h-parameters are hie = 1100 W,
hre = 2.5 × 10– 4, hfe = 50, hoc = 24 mA/V, the circuits use RL = 10 kW, and RS = 1
kW. Calculate gain Ai, input resistance Ri and voltage gain AV of this amplifier.
[JNTU June 2009]
Solution
hic = hie = 100 W
hrc = 1 – hre = 1 – 2.5 × 10– 4 = 999.75 × 10– 3
hfc = – (1 + hfe) = – (1 + 50) = – 51
hoc = hoe = 24 mA/V
– hfc
– (– 51)
(a) Current gain, Ai = _________ = _____________________
= 41.13
1 + hoc RL 1 + 24 × 10– 6 × 10 × 103
(b) Input resistance, Ri = hic + hrc Ai RL
= 1100 + 999.75 × 10– 3 × 41.13 × 10 × 103 = 412.3
AiRL 41.13 × 10 × 103
(c) Voltage gain, Av = _____ = _______________
= 0.9976
Ri
412.3 × 103
Find the values of hfb and hfc, if the value of hfe of a transistor is 50.
[JNTU June. 2009]
Solution
Given,
hfe = 50
hie
22
hib = ______ = ___ = 0.43
1 + hfe 51
where hie = 22 W which is the typical h parameter value of a transistor.
– hfe
– 50
hfb = ______ = ____ = – 0.98
51
1 + hfe
hfc = – (1 + hfe) = – (1 + 50) = – 51
An amplifier should produce an output waveform which does not differ from
the input signal waveform in any respect except amplitude, i.e. the output is an
amplified signal of the input. In practice, it is highly impossible to construct an
ideal amplifier whose output waveform is an exact replica of the input signal
waveform because of the nonlinearity of the characteristic of an active device.
The output differs from the input either in its waveform or frequency content.
The difference between the output waveform and the input waveform in an
amplifier is called distortion.
Harmonic distortion is seen by the nonlinear dynamic
curve for an active device. In this type of distortion, the new frequencies are
produced in the output, which are not present in the input signal. This harmonic
distortion is sometimes called amplitude distortion.
The intermodulation distortion is also a type of nonlinear distortion which occurs
when the input signal consists of more than one frequency. If an input signal
contains two frequencies f1 and f2, then the output will contain their harmonics,
i.e. f1, 2f1, 3f1, etc., and f2, 2f2, 3f2, etc., In addition, there would be components
( f1 + f2) and ( f1 – f2) and also the sum and difference of the harmonics. These
sum and difference frequencies are called intermodulation frequencies which are
undesirable because they subtract from the original intelligence.
The second harmonic distortion is obained from the dynamic transfer curve
using the three-point method for small signals, or the total harmonic distortion
is calculated by the five-point method for large signals.
In this type of distortion, the signal components at different frequencies are amplified by different amounts. This distortion may be
caused by the various frequency dependent reactances associated with the circuit or active device itself. Due to the capacitive and inductive components in
the amplifier circuits, and the active device, there is a loss in gain at the lower
and higher extremes of the frequency range. Hence the gain becomes a complex
number whose magnitude and phase angle depend upon the frequency of the
In this type of distortion, the phase shift between
input and output waveforms depends upon the signals of different frequencies.
Since human ear is not sensitive to phase shift, the phase distortion has no practical significance in audio amplifiers. If the phase shift varies with frequency,
different frequency components of the signal are delayed by different amounts
of time and hence a television picture is smeared.
Miller’s theorem states that if an impedance Z is connected
between the input and output terminals of a network which provides a voltage
gain A, an equivalent circuit that gives the same effect can be drawn by removZ
Z
ing Z and connecting an impedance Zi = _____ across the input and Zo = _____
1–A
1
1 – __
A
ZA
= _____ across the output as shown in Fig. 6.45.
A–1
In inverting amplifiers, the capacitive element, Cf, is connected between input
1
and output terminals of the active device i.e., XC = _____. The large capacitors
f
jw Cf
will control the low-frequency response due to their low reactance levels.
Therefore, the Miller effect input capacitance CMi, is derived as
Z
Zi = ______
(1 – A)
i.e.
Therefore,
1
1
______
= ___________
jw CMi jw Cf (1 – A)
CMi = (1 – A)Cf.
Hence, it is evident that, in any inverting amplifier, the input capacitance will
be increased by a Miller effect capacitance sensitive to the gain of the amplifier
and the interelectrode capacitance, Cf, between the input and output terminals
of the active device.
The Miller output capacitance, CMo is derived as
Z
Zo = _______
1
1 – __
A
(
i.e.
Therefore,
If
)
1
1
______
= ____________
jw CMo
1
jw Cf 1 – __
A
(
(
)
)
1
CMo = 1 – __ Cf
A
A >> 1, CMo = Cf.
Dual of Miller’s theorem states that if an impedance
Z connected as shunt element between input and output terminals, as shown in
Fig. 6.46(a) can be replaced by an impedance Zi = Z(1 – AI) at the input side and
(AI – 1)
1
Z0 = Z 1 – ___ = Z _______ at the output side as shown in Fig. 6.46(b), where
AI
AI
(
)
I2
the current ratio, AI = __. This can be verified by finding that the voltage across
I1
Zi is I1Zi which is equal to the voltage drop (I1 + I2)Z across Z if Zi = Z(1 – AI).
Hence the input voltage Vi is the same in the two circuits in Fig. 6.46(a)
and (b).
Similarly the voltage V2 has the same value in the two circuits if the impedance
[ ]
AI – 1
Zo = ______ Z. Therefore, the two networks are identical. This transformation
AI
is useful in the analysis of electric circuits.
A single-stage RC coupled CE amplifier shown in Fig. 6.47 can be employed as
a small-signal amplifier but a circuit with two cascaded stage gives large amplification. The design of resistor values involves application of Ohm’s law after
selecting suitable voltage and current levels throughout the circuit. The design of
capacitor values are based on the lower cut-off frequency of the circuit and the
resistance which is in series with the capacitor.
In this circuit, the biasing is provided by three resistors R1, R2 and RE. The
resistors R1 and R2 act as a potential divider giving a fixed voltage to the base.
If collector current increases due to change in temperature or change in hfe, then
the emitter current IE also increases, reducing the voltage difference between
base and emitter (VBE). Due to reduction in VBE, base current IB and hence
collector current IC also reduces. Negative feedback acts in emitter bias circuit.
This reduction in collector current IC compensated for the original change in IC.
The frequency response of the single-stage RC coupled BJT amplifier is shown
in Fig. 6.47.
The design of single-stage RC coupled amplifier is based
on the specifications like supply voltage, minimum voltage gain, frequency response, source impedance and load impedance. The circuit shown in Fig. 6.48
has no provision for negative feedback because of the bypass capacitor CE and
hence it is designed to achieve the largest possible gain.
The voltage gain of a CE amplifier circuit is given by
– hfe (RC || RL)
AV = _____________
hie
Since AV is directly proportional to RC || RL, the design for large voltage gain
requires selection of the largest possible collector resistance. But a large value of
RC needs the collector current to be small for satisfactory operation of transistor.
The value of collector resistance RC can be determined by applying Kirchhoff’s
voltage law around the collector-emitter circuit.
i.e.
VCC = ICRC + VCE + VE
VCC – VCE – VE
RC = ______________, where VE = IERE
IC
VCC
VCC
To achieve larger value of RC, let us assume VCE = ____ and VE = ____.
2
10
For good bias stability, the emitter resistor voltage drop, VE, should be greater
than the base emitter voltage VBE i.e., VE >> VBE. Since VE = VB – VBE, the emitter voltage VE will be slightly affected by the variation in VBE due to change in
VE
temperature. Hence, IE and IC remain stable at IC ª IE = ___.
RE
By Ohm’s law, the input resistance at the transistor base is
Vin
Rin(base) = ___
Iin
Here
Vin = VBE + IERE
ª IERE,
since VBE << IERE
ª b IBRE,
and
Therefore,
since IE ª IC = b IB
Iin = IB.
Vin b IBRE
Rin(base) = ___ = ______ ª b RE
Iin
IB
The total resistance from base to ground is
R2 || Rin(base) ª R2 || b RE
A voltage divider is formed by R1 and the resistance from base to ground, b RE,
in parallel with R2. Therefore,
R2 || b RE
VB = _____________ VCC
R1 + R2 || b RE
(
)
If b RE >> R2 (at least 10 times greater), then
R2
VB = _______ VCC.
R1 + R2
(
)
IC
The voltage divider current I2 is selected as ___ which
10
results in good bias stability and high input resistance. Hence, the bias resistors
are calculated as
VB
R2 = ___ and
I2
VCC – VB
R1 = _________
I2
(
)
R2
VB = VE + VBE or VB = _______ VCC.
R1 + R2
where
across the emitter resistor is used to filter out the signal variations at the emitter
with respect to ground. Therefore the reactance offered by this capacitor should
be low for high frequencies but high for d.c. and nearby low frequencies.
1
XC = ______
E
2p fCE
where XC should be high for dc and very low frequency signals and low for high
E
frequencies. Therefore,
1
CE = _______
2p fXC
E
where CE should be high for high frequencies starting from 100 Hz.
Therefore, XC can be fixed at one-tenth of RE.
E
All capacitors should be selected to have the smallest possible capacitance value
mainly to minimize the physical size of the circuit. Each capacitor has its highest impedance at the lowest operating frequency and it is calculated based on
the lower cut-off frequency. The bypass capacitor CE is normally the largest
capacitor in the circuit. We known that the voltage gain for CE circuit with
unbypassed emitter resistance given by
–hfe(RC || RL)
AV = ______________
hie + RE(1 + hfe)
By including the bypass capacitor in parallel with RE the voltage gain is given
by
–hfe(RC || RL)
AV = _______________________
hie + RE(1 + hfe)(RE || XC )
E
Normally RE >> XC so RE can be neglected and also XC is capacitive
E
E
reactance.
–hfe(RC || RL)
__________________
Hence,
AV = ____________________
2
h2ie + [(1 + hfe) (XC )]
÷
When hie = (1 + hfe)XC
E
E
–hfe(RC || RL) Avm
______ = ____
__ ,
|AV| = ____________
÷2
hie ÷12 + 12
where AVm is the mid frequency gain.
Therefore, at lower cut-off frequency fL,
hie = (1 + hfe)XC
E
hie
XC = ______
E
1 + hfe
Hence,
We know that
hie
______
= hib
1 + hfe
1
1
CE = ________ = _______
2p fLXC
2p fLhib
Therefore,
E
The coupling capacitors C1 and C2 have negligible effect on the frequency
response of the amplifier circuit and to minimize the effects of these capacitors,
the reactance of each coupling capacitor is selected to be approximately equal
to one-tenth of the impedance in series with it at the lower cut-off frequency fL.
These capacitances can be determined from the equations given by
Zi (R1 || R2 || hie)
1
C1 = ________, where XC = ___ = ____________
1
10
10
2p fLXC
1
Zo RC || RL
1
C2 = ________, where XC = ___ = _______
2
10
10
2p fLXC
and
2
Design a single stage RC coupled BJT amplifier circuit shown in Fig. 6.63. Assume
that VCC = 10 V, IC = 4 mA, hfe = 100, hie = 1 k , RL = 100 k and fL = 100 Hz.
Solution
Refer to Fig. 6.63.
(a) To determine bias resistors R1 and R2 and RC and RE
We know that
VCC 10
VCC
VE = ____ = ___ = 1V, VCE = ____ = 5V
2
10
10
VCC = ICRC + VCE + VE
Therefore,
ICRC = VCC – VCE – VE = 10 – 5 – 1 = 4V
i.e
4
RC = _______
= 1 kW
4 × 10–3
Here,
VE = IERE ª ICRE
Therefore,
VE
1
RE = ___ = _______
= 250 W
IC 4 × 10–3
VB = VBE + VE = 0.7 + 1 = 1.7
(
)
R2
VB = _______ VCC
R1 + R2
R2
VB
1.7
_______
= ____ = ___ = 0.17
R1 + R2
VCC 10
R2 = 0.17(R1 + R2)
5.88R2 = R1 + R2
4.88R2 = R1
The value of R2 can be selected to satisfy b RE >> R2. Hence, R2 is selected as
2 kW. Therefore, R1 = 9.76 kW ª 10 kW
(b) To determine the bypass capacitor CE
hie
1 × 103
XC = ______ = _______ = 9.9
E
1 + hfe 1 + 100
1
1
1
CE = ________ = _____________ = ______ = 160.8 m F
2p × 100 × 9.9 6217.2
2p fLXC
E
(c) To determine coupling capacitors C1 and C2
Zi (R1 || R2 || hie) (10 × 103 || 2 × 103 || 1 × 103)
XC = ___ = ____________ = _________________________ = 246.154
1
10
10
10
1
1
C1 = ________ = _________________ = 6.47 m F
2p × 100 × 246.154
2p fLXC
1
Zo RC || RL 1 × 103 || 100 × 103
XC = ___ = _______ = _________________ = 99.001
2
10
10
10
1
1
1
C2 = ________ = ________________ = _________ = 0.1608 m F
2p × 100 × 99.001 62172.628
2p fLXC
2
The small signal models for the common source FET can be used for analysing
the three basic FET amplifier configurations: (i) Common source (CS), (ii)
Common drain (CD) or Source-follower, and (iii) Common gate (CG). The CS
amplifier which provides good voltage amplification is most frequently used.
The CD amplifier with high input impedance and near-unity voltage gain is used
as a buffer amplifier and the CG amplifier is used as high frequency amplifier.
The small signal current-source model for the FET in CS configuration is
redrawn in Fig. 6.49(a) and the voltage-source model shown in Fig. 6.49(b)
can be derived by finding the Thevenin’s equivalent for the output part of Fig.
6.49(a). m, rd and gm are the amplification factor, drain resistance and mutual
conductance of the FET.
id
G
+
D
+
rd
G
+
id
D
+
–
Vgs
gmVgs
rd
Vds
Vgs
Vds
mVgs
+
–
–
–
–
S
S
(a)
(b)
the added feature of high input impedance. They have low power consumption
with a good frequency range, and minimal size and weight. The noise output level
is low. This feature makes them very useful in the amplifier circuits meant for
very small signal amplifications. JFETs, depletion MOSFETs and enhancement
MOSFETs are used in the design of amplifiers having comparable voltage gains.
However, the depletion MOSFET circuit realizes much higher input impedance
than the equivalent JFET configuration. Because of the high input impedance
characteristic of FETs, the a.c. equivalent model is somewhat simpler than that
employed for BJTs. The common source configuration is the most popular one,
providing an inverted and amplified signal. However, one also finds the common drain (source follower) circuits providing unity gain with no inversion and
common gate circuits providing gain with no inversion. Due to very high input
impedance, the input current is generally assumed to be negligible, and it is of
the order of few microamperes and the current gain is an undefined quantity.
Output impedance values are comparable for both the BJT and FET circuits
A simple common-source amplifier is shown in Fig. 6.50(a), and the associated
small signal equivalent circuit using the voltage-source model of FET is shown
in Fig. 6.50(b).
Rs) is used to set the Q-point but is bypassed by
S
output voltage,
VDD
RD
+
D
G
S
+
Vi
RG
Rs
–
Vo
CS
–
(a)
– RD
Vo = _______ mVgs
RD + rd
(6.78)
where Vgs = Vi, the input voltage.
Hence, the voltage gain,
Vo – m RD
AV = ___ = _______
Vi RD + rd
From Fig. 6.50(b), Input impedance is given by
Zi = RG
For voltage divider bias as in CE amplifiers of BJT
RG = R1 || R2
(6.79)
Output impedance is the impedance measured at the output terminals with the input voltage Vi = 0.
From Fig. 6.50(b), when Vi = 0, Vgs = 0 and hence
mVgs = 0
Then the equivalent circuit for calculating output impedance is given in Fig.
6.50 (c).
Output impedance
Zo = rd || RD
rd
RD
Zo
(c)
Normally rd will be far greater than RD.
Zo ª RD
Hence,
In the CS amplifier of Fig. 6.50(a), let RD = 5 k , RG = 10 M , = 50, and rd = 35
k . Evaluate the voltage gain AV, input impedance Zi and output impedance Zo.
Solution
The voltage gain,
Vo – m RD
AV = ___ = _______
Vi RD + rd
– 50 × 5 × 103
= ________________
5 × 103 + 35 × 103
– 250 × 103
= __________
= – 6.25
40 × 103
The minus sign indicates a 180° phase shift between Vi and Vo.
Input impedance
Zi = RG
= 10 MW
Output impedance
Zo ª RD
= 5 kW
A FET amplifier in the common-source configuration uses a load resistance of
500 k . The ac drain resistance of the device is 100 k and the transconductance is
0.8 mAV–1. Calculate the voltage gain of the amplifier.
Solution
Given load resistance, RL = RD = 500 kW, rd = 100 W, gm = 0.8 mAV–1
The transconductance m = gmrd = 0.8 × 10 – 3 × 100 × 103 = 80
The voltage gain,
mRD
– 80 × 500 × 103
40 × 106
_________
AV = – _______ = ___________________
=
–
= – 66.67
RD + rd 500 × 103 +100 × 103
600 × 103
A simple common-drain amplifier is shown in Fig. 6.51(a) and the associated
small signal equivalent circuit using the voltage-source model of FET is shown
in Fig. 6.51(b). Since voltage Vgd is more easily determined than Vgs, the voltage
VDD
D
G
Vi
+
S
+
RG
Rs
Vo
–
–
(a)
source in the output circuit is expressed in terms of Vgd using Thevenin’s theorem. The output voltage,
mRs Vgd
Rs
m
_____
_____________
×
V
=
Vo = __________
rd
m + 1 gd (m + 1) Rs + rd
Rs + _____
m+1
(6.80)
where Vgd = Vi, the input voltage.
Hence, the voltage gain,
Vo
mRs
AV = ___ = _____________
Vi (m + 1) Rs + rd
(6.81)
Zi = RG
From Fig. 6.51(b), Output impedance measured at the
output terminals with input voltage Vi = 0 can be simply calculated from the
following equivalent circuit.
m
As
Vi = 0; Vgd = 0; _____ Vgd = 0
m+1
r
d
Output impedance
Zo = _____ || Rs
m+1
when m >> 1 (typical value of m = 50)
rd
1
___
Zo ª __
m || Rs = gm || Rs
rd
m+1
Rs
Zo
In the CD amplifier of Fig. 6.51(b), let Rs = 4 k , RG = 10 M , = 50, and rd = 35
k . Evaluate the voltage gain AV, input impedance Zi and output impedance Zo.
Soution
The voltage gain,
Vo
mRs
AV = ___ = _____________
Vi (m + 1) Rs + rd
50 × 4 × 103
= _________________________
= 0.836
(50 + 1) × 4 × 103 + 35 × 103
The positive value indicates that Vo and Vi are in-phase and further note that
AV < 1 for CD amplifier.
Input impedance
Zi = RG = 10 MW
Output impedance
1
Zo = ___
gm || Rs
rd
= __
m || Rs
( )
35 × 103
Zo = ________ || 4 × 103 = 595.7 W
50
A simple common-gate amplifier is shown in Fig. 6.52(a) and the associated
small signal equivalent circuit using the current-source model of FET is shown
in Fig. 6.52(b).
From the small signal equivalent circuit by applying KCL,
ir = id – gm Vgs
Vo = (id – gmVgs) rd – Vgs
CC
S
CC
D
+
+
RD
G
Vi
R1
Rs
Vo
VDD
R2
–
–
(a)
rd
ir
id
+
Rs
Vi
–
–
Vgs
+
–
G
gmVgs
D
RD
(b)
+
Vo
–
– Vo
and id = ____
RD
But
Vgs = – Vgs = Vi
Thus,
– Vo
Vo = ____ + gmVi rd + Vi
RD
(
)
Hence, the voltage gain,
Vo (gmrd + 1) RD
AV = ___ = ____________
Vi
RD + rd
(6.82)
Figure 6.52(b) is modified for calculation of input impedance as shown in Fig. 6.52(c).
Current through rd is given by
Ird = –Ir = I1 + gmVgs
I1 = Ird – gmVgs
where
Vi – Vo
Ird = _______
r
d
Vi – IRD RD
= __________
r
d
Hence,
Vi – IRD RD
I1 = __________
– gmVgs
r
d
From Fig. 6.52(c),
Vi = –Vgs
Vi – IRD RD
I1 = __________
+ gmVi
r
d
Vi ______
IRDRD
= __
+ gmVi
r – r
d
d
Vi
IRDRD __
I1 + ______
rd = rd + gmVi
From Fig. 6.52(c),
I1 = IRD
Therefore,
[
] [
rd + RD
1
I1 _______
= Vi __
rd
rd + gm
]
Vi ________
rd + RD
__
=
= Zi¢
I1 1 + gm rd
From Fig. 6.52(c),
Zi = Rs || Zi¢
rd + RD
= Rs || ________
1 + gm rd
In practice, rd >>RD and gmrd >> 1.
rd
Therefore,
Zi = Rs || ____
gm rd
1
Zi = Rs || ___
g
Therefore,
m
It is the impedance seen from the output, terminals with
input short circuited.
From Fig. 6.52(c), when Vi = 0, Vsg = 0, the resultant equivalent circuit is shown
in Fig. 6.52(d).
Zo = rd || RD
as
rd >> RD
Zo ª RD
rd
RD
Zo
(d)
In the CG amplifier of Fig. 6.52(b), let RD = 2 k , Rs = 1 k , gm = 1.43 × 10–3
mho, and rd = 35 k . Evaluate the voltage gain AV, input impedance Zi and output
impedance Zo.
Solution
The voltage gain,
Vo (gmrd + 1) RD
AV = ___ = ____________
Vi
RD + rd
(1.43 × 10 – 3 × 35 × 103 + 1) 2 × 103
_______________________________
=
= 2.75
2 × 103 + 35 × 103
Input impedance
1
Zi = Rs || ___
g
m
103
= 1 × 103 || ___
1.4
= 0.41 kW
Output impedance Zo ª RD = 2 kW
From the drain and transfer characteristics of the Field Effect Transistor, we see
that the drain current of an FET is a function of Drain to Source voltage (vDS)
and Gate to Source Voltage (vGS). The linear small signal equivalent circuit for
FET can be drawn analogous to the BJT.
Assuming varying currents and voltages for an FET,
iD = f (vGS, vDS)
(6.83)
If both gate and drain voltages are varied, the change in drain current is given
approximately by first two terms in the Taylor’s series expansion of Eqn.
(6.108),
∂iD
DiD = ____
∂vGS
( )
VDS
∂iD
DVGS + ____
∂vDS
( )
VGS
DvDS
(6.84)
In small signal notation as for BJT,
DiD = id, DvGS = vgs and DvDS = vds
so that Eqn. (6.109) can be written as
1
id = gmvgs + __
r vds
(6.85)
d
where mutual conductance or transconductance of the FET is defined as
∂iD
gm = ____
∂vGS
DiD
ª _____
DvGS
VDS
( ) ( ) ( )
VDS
id
= ___
vgs
VDS
(6.86)
and drain (or output) resistance of the FET is defined as
∂vDS
rd = ____
∂iD
DvDS
ª _____
DiD
VGS
( ) ( ) ( )
vds
= ___
id
VGS
(6.87)
VGS
The reciprocal of rd is the drain conductance gd.
An amplification factor m for an FET may be defined as
∂vDS
m = – ____
∂vGS
(
DvDS
ª – _____
DvGS
ID
) (
) ( )
ID
vds
= – ___
vgs
(6.88)
id = 0
From Eqn. (6.110) by setting id = 0, it can be verified that m, rd and gm are related
by
m = gmrd
(6.89)
A small-signal model for FET in common source configuration can be drawn
satisfying Eqn. (6.110) as shown in Fig. 6.53.
id
Gate G
+
Vgs
gmVgs
rd
D
+ Drain
Vds
–
Source S
–
S
This low frequency model for FET has a Norton’s output circuit with a dependent current generator whose magnitude is proportional to the gate-to-source
voltage. The proportionality factor is the transconductance ‘gm’. The output
resistance is rd. The input resistance between the gate and source is infinite, since
it is assumed that the reverse biased gate draws no current. For the same reason,
the resistance between gate and drain is assumed to be infinite.
The h-parameter model of a BJT in CE configuration is redrawn in Fig. 6.54 for
comparison.
Comparing circuits of Figs. 6.53 and 6.54, the BJT also has a Norton’s output
circuit, but the current generated depends on the input current and not on the
input voltage as in FET. There is no feedback from output to input in the FET,
whereas a feedback exist in the BJT through the parameter hre. The high (almost
infinite) input resistance of the FET is replaced by an input resistance of about
1 kW for a CE amplifier.
Due to the high input impedance and the absence of feedback from output to
input, FET is a much more ideal amplifier than the BJT at low frequencies. This
becomes invalid beyond the audio range as the low frequency model of FET
shown in Fig. 6.53 is not valid in the high frequency range.
The high frequency model of an FET is shown in Fig. 6.55.
G
D
Cgd
Cgs
S
gmVgs
rd
Cds
S
This high frequency model is identical with the low frequency model except that
the capacitances between the various terminals (gate, source and drain) have
been added. The capacitor Cgs represents the barrier capacitance between the
gate and source and Cgd represents the barrier capacitance between the gate
and drain. The capacitor Cds is the drain-to-source capacitance of the channel.
Because of these internal capacitances feedback exists between the output and
input circuits of the FET and the voltage amplification drops drastically with
increase in frequency.
Data sheets published by the semiconductor device manufacturer specify the
electrical characteristics of each type of device. The data sheet establishes the
communication link between the manufacturer and the user. The information
provided by the manufacturer must be recognized and correctly interpreted by
the user. It can avoid device failures and give optimum performance.
Here, the specification sheets of some of the commonly used PN Junction
Diode, Zener Diode, Varactor Diode, Tunnel Diode, Photo Diode, BJT–NPN
Small Signal Transistor, BJT–PNP Small Signal Transistor, N-Channel JFET,
P-Channel JFET, Power MOSFET, Small Signal MOSFET, UJT “and SCR”
are given in the following Tables.
10
75
400
1000
IN4148
IN5404
IN5408
25
1250
650
30
1000
100
5
5
0.025
500
200
10
10
1.5 to 150
50
50
IR
(max)
(mA)
VR
(max)
(V)
DS-10
DR-25
BY127
BY126
OA79
IN4007
IN4002
Type
Parameters
—
—
1
—
—
—
—
1.2 to
3.8
0.9
0.9
3
—
10
—
—
—
—
35
1000
1000
IF
(mA)
Continuous
VF (V)
Peak
1.1
1.1
1
22.5
1000 (mV)
1.5
1.5
1.4 to 4.0
2.3
2.3
VF (V)
3
3
200
20
250
5
5
100
25
25
IF
(A)
Reverse
—
—
4
—
—
—
—
—
5000
3500
recovery
(ns)
—
—
4
—
—
—
—
—
10
15
(10 V)
(pF)
Germanium
Silicon
Silicon
Germanium
Silicon
Indus std;
7-member family
Silicon
Comments
GP rectifier
GP rectifier
Small Signal
Silicon
Silicon
Silicon
Stabilizing element Germanium
Low power
rectifier
Television
receivers
Television
receivers
Detector Circuits
1-amp rect
Capacitance Class
Parameter
Volt VZ @
IZT (Volt)
Watts
Test Current IZT
(mA)
IN4728
3.3
1
—
IN4732
4.7
1
53
IN4734
5.6
1
45
IN4736
6.8
1
37
IN4740
10
1
25
IN4742
12
1
21
IN4744
15
1
17
IN4747
20
1
12.5
IN4749
24
1
10.5
IN4751
30
1
8.5
IN750
4.7
0.4
20
IN752
5.6
0.4
20
IN754
6.8
0.4
18.5
IN755
7.5
0.4
16.5
IN758
10
0.4
14.0
IN759
12
0.4
11.5
IN965
15
0.4
9.5
IN968
20
0.4
7.0
IN970
24
0.4
5.6
IN972
30
0.4
5.3
Type
Parameter
Reverse
breakdown
voltage
(min)
Reverse
leakage
current
(max)
Operating
Nominal Minimum
Tuning
temperature capacitance Q (figure
ratio
range
of
merit)
Min.
Max.
pF
C
Type
(Volts)
(nA)
ZC830B
(SMT)
25
20
SOD 323
30
20 at
(SMT)
TA
SOD 123
30
(SMT)
BB139
30
25 C
10 at
TA
25 C
50
10
300
4.5
60
—
—
—
—
–55 C to
19.5
—
—
—
125 C
–55 C to
150 C
6.3
150
—
—
–55 C to
150 C
–55 C to
125 C
Parameter
9.0
2.0
4.0
MRD 510
MRD 721
mA typ
MRD 500
Type
20
MV1600
(mA)
(Volts)
20
20
20
@ VR Volts
Light Current
250
250
current
12
dissipation
forward
reverse
voltage
2
5.0
5.0
5.0
H W/cm
400
400
(mW)
at 25 C
Maximum
Maximum
Maximum
MV1403
Type
Parameter
100
100
100
V(BR)R
Volts
(min)
100
10
10
2.0
2.0
Q at
20
20
20
@ Volts
—
200
2V dc
Dark Current
4
6
(nH)
inductance
Series
nA (max)
10 V (nA)
current at
leakage
reverse
Maximum
1.0
1.0
1.0
ns Typ
Response Time
AM broadcast band, general A.F.C.
and tuning applications in lower
RF frequencies AFC applications
in Radio, TV and general electronic
tuning.
Applications
200
200
600
700
800
2N2369A
2N3904
2N4401
2N3053
2N2222A
2N916
15A
100
BC549
2N3055
100
BC548
1000
100
BC547
10000
100
BC109
BUY82
100
BC108
BFY50
100
BC107
360
115W
30W
2800
500
5.0W
350
350
360
625
625
625
300
300
300
(mW)
(max)
(max)
(mA)
PD
IC
Type
Parameter
25
60
60
35
40
40
40
40
15
30
30
45
20
20
45
(Volts)
(max)
VCEO
45
70
150
80
75
60
60
60
40
30
30
50
30
30
50
(Volts)
(max)
VCBO
50-200@10
20-70@4A
40(min)@1.5A
30(min)@150
100-300@150
50-250@150
100-300@150
100-300@10
20(min)@100
110-800@2
110-800@2
110-800@2
200-800@2
110-800@2
110-450@2
@ IC(mA)
Hfe (min-max)
0.5
1.1
5
10
10
10
2
1
1
5
5
5
5
5
5
VCE
300
0.8
60
60(min)
300
100
250(max)
300(min)
500(min)
250
300
300
2N2222A
BDY 20
—
—
—
—
2N4403
2N3906
—
BC559
BC558
BC557
BC179
BC178
300
300
BC177
Complement
300
MHz
FT @
(Contd.)
O/P - SW
High power
switch
General Purpose
High speed
switch
General purpose
General purpose
Low level amp.
High speed
switch
Low noise audio
Amplifier
Amplifier
Low noise audio
General purpose
Audio driver
Applications
145
30
30
30
500
2 Amps
1 Amp
30
BF184
BF185
BF195
SL100
PT4
AC176
BF115
145 mW
155 mW
4W
800
250
145
360
(mW)
(mA)
2N3040
(max)
(max)
360
PD
IC
2N2369
Type
Parameter
30
32
20
50
20
20
20
30
(Volts)
(max)
VCEO
50
32
32
60
30
30
30
40
40
(Volts)
(max)
VCBO
45-165
83
80-320
50-280
67
67
75 to 750
40-160@150
40-120@10
@ IC(mA)
Hfe (minmax)
—
—
10 V
7V
10 V
10 V
10 V
0.20
0.35
VCE
230
Mc/S
3
—
200
220
300
50
500
MHz
FT @
—
AC128
PT6
SK100
—
—
—
2N3040
—
Complement
Gen. Broadcast
and television
Radio receivers,
Tape recording
Amplifier and
Radio receivers
AM for receivers
Class B push
pull stage
Low noise AM
and FM
applications
For IF amplifier
Applications
VCE
VCB
–25
–20
–45
–30
–32
–40
–20
–45
BC158
BC159
BC557
BC558
AF115
2N2904
AD162
BC177
–50
–32
–60
–32
–30
–50
–25
–30
–50
(Volts) (Volts)
–45
Parameter
BC157
Type
–100
–2 A
–0.6 A
–10
–100
–100
–100
–100
–100
IC
(mA)
–5 v
–1 v
—
—
—
—
–0.25 10
0.25 10
–0.25 10
Vces@IC
Hfe@
175-500
50-300
20-40
150
75
110-300
125-500
75-500
75-260
IC(mA)
2
2
2
2
2
200
1.5
200
75
150
150
150
150
150
IMHz
FT @
—
—
10
10
10
(mA)
P to t
300
mW
6W
0.6 W
75
500
500
300
300
300
(mW)
Audio driver
Audio matched
pair
Switching &
driving
applications
RF. Amp,
mixer
oscillator in
S.W. receivers
4p. small sig.
4p. small sig.
S.S. Amp
S.S. Amp
S.S. Amp
Use
BC 107
—
—
AF125
AF200
BC158 DS558
BC157 DS557
BC179 BC309
BC175, BC308
BC177, BC212,
BC307
Types
Comparable
Parameter
30
30
E174
2N5018
Type
–30
Gate
Source
voltage VGS
(Volts)
–30
BFW11
–30
Gate
voltage
VDG
(Volts)
Source
voltage
VGS
(Volts)
–30
Drain-
Gate
BFW10
Type
Parameter
30
30
VDG (Volts)
DrainGate voltage
30
30
Source
voltage
VDS
(Volts)
Drain-
300
300
Dissipation
PD(mW)
Device
–65 to 200 C
–65 to 200 C
Temperature
Range ( C ) Tstg
Storage
30
30
10
10
300
350
DrainForward
Device
Source voltage Gate current Dissipation
VDS (Volts)
IGF (mA)
PD (mW)
10
10
Gate
current
IGF (mA)
Forward
–65 C to
200 C
–55 C to
150 C
Digital
switch,
sample
and hold
multiplexers
Analog
switches
choppers
commutators
uses
Common
Low on
resistance,
High speed
switch
Low cost
Low on
resistance
Fast
switching
speed
Features
Low Capacitance High
Transconductor
Low Capacitance High
Transconductor
Features
Storage
Temperature
Range
( C) Tstg
UHF
amplifiers
UHF
amplifiers
uses
Common
200
150
2N6758
2N6757
0.6
0.4
1
1.5
ID
5
6
3.5
3
3
(Amps)
8
9
5.5
4.5
6.0
(Amps) max.
ID
Continuous
Volts mini.
200
200
90
Type
BS107
BS170
2N6661
4
5
14
max.
VDS (ohms)
1
0.2
0.2
(Amps)
ID
TC
2
0.50
0.25
(Amps) max.
ID Continuous
Table A.8(b) Small Signal MOSFET
V(BR) DSS
400
2N6760
Parameter
500
2N6762
max.
Volts
mini.
1.2
VDS
(ohms)
V(BR)
DSS
550
Parameter
MTM6N55
Type
PD
TC
PD
6.25
0.6
0.6
25 C
watts
75
75
75
75
150
25 C watts
150
100
50
C 106A
TY6004
in Amp.
VRRM in Volts
MCR 115
IT (RMS)
Voltage (Max.)
8.0
4.0
0.8
4.0
Current
(RMS)
Reverse
30
Forward
35
35
35
Repetitive
–30
–30
30
emitter
voltage
VBB (v)
two reverse
voltage VEB2 (v)
—
2.55
—
2.55
(AV) in Amp.
(Average) IT
Current
Forward
50
50
50
IE (mA)
current
Continuous
Inter-base
Emitter-Base
MCR l06
Type
Parameter
2N2646
2N2647
MU10
Type
Parameter
—
20
—
25
in Amp.
(Max.) ITSM
Surge Current
NonRepetitive
2
2
1.0
5.0
0.5
0.1
0.5
Watts
PGM in
(Max.)
2.0
0.2
1.0
0.2
IGM in Amp.
(Max.)
Current
—
6.0
5.0
6.0
Volts
VRGM in
Voltage
(Max.)
–40 to
–40 to
–40 to
–40 to
125
110
110
110
Tj in C
Temp.
Junction
Operating
260 C
260 C
–
10 seconds
the case for
1/16 inch from
Lead temperature
Reverse Gate
–65 to 150 C
–65 to 150 C
–65 to 150 C
range
temperature
Storage
Gate Power Forward Gate
300
300
300
25 C (mW)
(or below)
dissipation at
current
IP (A)
Continuous device
Peak-emitter
Probable Values of General Physical Constants
Constant
Symbol
Value
q
1.602 × 10 – 19 C
1 electron volt
eV
1.602 × 10 – 19 Joules
Electronic mass
m
9.109 × 10 – 31 kg
q/m
1.759 × 1011 C/kg
Planck’s constant
h
6.626 × 10 – 34 J-s
Boltzmann constant
k
8.620 × 10–5 eV/°K
Velocity of light
c
2.998 × 108 m/s
Acceleration of gravity
g
9.807 m/s2
Permeability of free space
m0
1.257 × 10 – 6 H/m
Permittivity of free space
e0
8.854 × 10 – 12 F/m
1 joule
J
6.25 × 1018 eV
Electronic charge
Ratio of charge to mass of an electron
Conversion Factors and Prefixes
Constant
Value
1 ampere (A)
1 C/s
1 angstrom unit (Å)
10 – 10 m = 10 – 8 cm
1 coulomb (C)
1 A–s
1 farad (F)
1 C/V
1 henry (H)
1 V–s/A
1 hertz (Hz)
1 cycle/s
1 lumen
0.0016 W (at 0.55 m m)
1 mil
10 – 3 inch = 25 m m
1 micron
1 m m = 10 – 6 m
1 newton (N)
1 kg = m/s2
1 Volt (V)
1 W/A
1 watt (W)
1 J/s
1 weber (Wb)
1 V–s
2
1 weber per square meter (Wb/m )
104 gauss
1 tesla (T)
1 Wb/m2