pubs.acs.org/acsaelm
Letter
Rail-to-Rail MoS2 Inverters
Jinpeng Tian, Yalin Peng, Qinqin Wang, Yanbang Chu, Zhiheng Huang, Na Li, Xiuzhen Li, Jian Tang,
Biying Huang, Rong Yang, Luojun Du, Wei Yang, Dongxia Shi, and Guangyu Zhang*
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sı Supporting Information
*
ABSTRACT: Two-dimensional semiconductors are considered as
promising candidates for future electronic circuits thanks to the
atomic thickness and no dangling bond surface. Additionally, as
one of the most fundamental logic gates, high-performance
inverters are crucial for integrated circuits. Here we design railto-rail MoS2 inverters by using bilayer MoS2 and MoO3 doped
monolayer MoS2 transistors as load and driver transistors,
respectively. The inverters exhibit a good rail-to-rail operation
with a switching threshold voltage VM ≈ 2 V at VDD = 4 V, a high
peak gain of 344 V/V, and a large noise margin NM ≈ 0.98 ×
(VDD/2).
KEYWORDS: 2D semiconductor, MoS2, inverter, rail-to-rail operation, ring oscillator
T
W ratios increase the area per device, which is an important
indicator of devices scaling down.
Here, we propose a strategy to construct rail-to-rail NMOS
MoS2 inverters, without introducing any additional materials to
increase the fabrication complexity. We use a bilayer MoS2 and
a MoO3 doped monolayer MoS2 transistors as the load and the
driver transistors of the inverters, respectively. The bilayermonolayer inverters (BM-inverters) exhibit a rail-to-rail
operation with a switching threshold voltage VM ≈ 2 V at
VDD = 4 V, a high peak gain of 344 V/V, and a large noise
margin NM ≈ 0.98 × (VDD/2), which are the best among the
reported MoS2 inverters.8,9,13−21,23−26 Besides, this method is
also scalable and can be applied to other TMD semiconductors.
Experimentally, we first fabricated the Ti/Au/Ti back gate
and the 10 nm HfO2 dielectric layer on the sapphire substrate
(see Figure S1). Second, a high-quality monolayer MoS213 was
transferred to the dielectric layer by a wet transfer process.
Then, reactive ion etching (RIE) was performed to selectively
oxidize the first layer MoS2 of the driver transistor part with
oxygen plasma at 15 °C for 8 s, leading to a formation of the
MoO3 layer. The AFM data (Figure S2) show the before and
after comparison of oxygen plasma etched MoS2, the height of
MoS2 area increases to ∼1.2 nm from the monolayer MoS2 ∼
wo-dimensional (2D) semiconductors, such as transition
metal dichalcogenides (TMD)1 and black phosphorus,2
have attracted tremendous interest from the academy and
industry. Because the atomically thin channels could facilitate
continued transistor scaling down, 2D materials are considered
as the promising candidates for future generations of electronic
circuits.3−5 In addition, 2D materials are good candidates for
flexible electronics thanks to their high mechanical flexibility
and stability, excellent optical transparency and optoelectronic
properties, which could also be compatible with the standard
semiconductor technology.4,6−10
The inverter, a circuit that outputs a opposite logic-level
(logic “0” of low voltage and logic “1” of high voltage)
corresponding to its input, is the most fundamental logic gate
that performs a Boolean operation on a single-input variable.11
To realize a 2D reliable and high density constructing cascaded
integrated circuit, it is necessary to fabricate a inverter with railmin
max
max
min
min
to-rail output swing (Vmin
in = Vout , Vin = Vout , where Vin , Vout ,
max
,
V
are
the
minimum
and
maximum
of
input
and
output
Vmax
in
out
voltages), high noise margin, narrow transition zone with
minimal number and area of transistors, and one power supply.
There are generally three reported approaches to realize the
MoS2 inverters, including MoS2 NMOS inverters with two
identical transistors,8,9,12−17 or unidentical transistor channel
L/W (L and W are the channel length and width) ratios,18,19
and CMOS inverters with a MoS2 transistor and its p-type
counterpart.20−23 However, it is hard to realize rail-to-rail
operation by using only two identical n-type MoS 2
transistors,18 while the usage of a p-type semiconductor will
introduce fabrication difficulties and compatibility problems.
Moreover, the approaches of unidentical transistor channel L/
© 2022 American Chemical Society
Received: April 5, 2022
Accepted: May 20, 2022
Published: May 24, 2022
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ACS Appl. Electron. Mater. 2022, 4, 2636−2640
ACS Applied Electronic Materials
pubs.acs.org/acsaelm
Letter
Figure 1. Bilayer-monolayer rail-to-rail inverters. (a) The schematic of BM-inverters. The load is the depletion mode transistor, and the driver
transistor is the enhancement mode transistor. (b) The device diagram of BM-inverters. The load and driver transistors are bilayer and MoO3
doped monolayer MoS2 transistors. (c) The IDS−VGS characteristics of doped monolayer and bilayer MoS2 transistors compared with the prime
monolayer MoS2 transistor.
Figure 2. Characteristics of BM-inverters. (a) The load-line plot of the BM-inverter. (b) The voltage transfer curve (VTC) of BM-inverter. The
VDD is 4 V, and VM ≈ 2 V = VDD/2. The gray dash area is the noise margin area. (c) The gain versus input voltage Vin of the BM-inverter at VDD = 4
V, and the peak gain is 344 V/V at VM. The inset is the optical image of the BM-inverter.
monolayer MoS2 transistors show distinct subthreshold voltage
Vth of 1.5 and 0.2 V, respectively, which provides a basis of railto-rail operation. When VGS = 0 V, as shown in the Figure 1c,
the bilayer MoS2 transistor enters the subthreshold region, yet
the doped monolayer MoS2 transistor is still at OFF state. As
such, in the BM-inverters, the output voltage Vout = VDD ×
Rdriver/(Rdriver + Rload) ≈ VDD (Rdriver and Rload are the resistance
of driver and load transistor, respectively) at the input voltage
of Vin = 0 V. As the Vin increases to a value between 1 and 1.5
V, the driver transistor enters the subthreshold area, but Rdriver
is still much larger than Rload, thus the Vout ≈ VDD is still
maintained. When Vin > 1.5 V, Rdriver is comparable to Rload,
and the Vout begins to decrease. Since the load transistor
rapidly enters the saturated regime (VDS > VGS − Vth), Rload
starts to increase (almost linearly with (VDD − Vout)) while
Rdriver decreases, leading to a fast switching of output voltage.
When Rload = Rdriver, one could obtain Vout = VDD/2. Upon
further increasing Vin, with Rload ≫ Rdriver, the Vout is almost
equal to the ground (i.e., 0 V), finishing the rail-to-rail
operation.
Figure 2a shows the load-line plot of the BM-inverter, the
load transistor saturates quickly with source to drain voltage
increases, which ensures fast switching of the inverter and high
noise margin. Additionally, the current of the driver at about
Vin = 2 V is very close to that of the load, which means the
switching point of the BM-inverter is at Vin ≈ 2 V. Figure 2b
shows the voltage transfer curve (VTC) of the BM-inverter. At
0 V < Vin < 2 V, Vout ≈ VDD = 4 V and the inverter switches
quickly at Vin ≈ VDD/2 = 2 V, leading to Vout ≈ 0 at 2 V < Vin <
4 V, exhibiting a good rail-to-rail operation with switching
0.7 nm after oxidation treatment. The XPS spectra in Figure S3
shows the MoS2 was entirely oxidized after RIE treatment.
Next, a second layer MoS2 was transferred to the first layer by
wet transfer, and thus, bilayer and hole doped monolayer
regimes were defined. Finally, Bi/Au was evaporated as a
contact electrode.
Figure 1a shows the schematics of the BM-inverters. The
load is a depletion mode transistor, and the driver transistor is
an enhancement mode transistor. In this circuit, the source and
the gate of load transistor are connected (i.e., VGS = 0 V).
Therefore, the IDS of load transistor will saturate quickly as the
source to drain voltage VDS increases (saturate condition
VDS>VGS-Vth), and this ensures the inverters have a fast
switching speed and a large noise margin.18 In the BMinverters, a bilayer MoS2 transistor serves as depletion mode
load transistor, and a slightly hole doped monolayer MoS2
serves as the enhancement mode driver transistor, as shown in
Figure 1b. While the bilayer MoS2 has a more negative
threshold voltage compared with prime monolayer MoS2
(Figure 1c), the positive threshold voltage of MoO3 doped
monolayer MoS2 is achieved by O2 plasma treatment.27−29 The
channel width and length of the load and driver transistors are
20 and 10 μm, respectively, and the capacitance of 10 nm
HfO2 is ∼1.2 μF cm−2 (Figure S4).
The doped monolayer and bilayer MoS2 transistors exhibit a
good switching performance with ON/OFF ratio over 107 and
subthreshold swing (SS) of 94 and 104 mV/dec, respectively.
The highest carrier density of the doped monolayer and bilayer
MoS2 transistors is ∼1.6 × 1013 cm−2 and ∼2.4 × 1013 cm−2 at
VGS = 4 V respectively. Importantly, bilayer and doped
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Figure 3. Logic gates based on BM-inverters. (a−c) The output characteristics of AND, NOR, and NAND logic gates with input signal level (0,0),
(1,0), (0,1), (1,1). The logic “0” and “1” state represent 0 and 4 V voltage, and VDD = 4 V. The insets are optical images of corresponding logic
gates.
Figure 4. 3-stage ring oscillators. (a) Optical image and schematic of 3-stage ring oscillators. The 3-stage ring oscillators are made of BM-inverters.
The dielectric layer is 20 nm Al2O3. (b) The output characteristics of the 3-stage ring oscillator. The oscillation frequency f is 32.5 kHz at VDD = 10
V. (c) Voltage dependence of the oscillation frequency measured from the 3-stage ring oscillator.
threshold VM ≈ 2 V = VDD/2. Furthermore, the noise margin
of low and high signal level is NML = NMH ≈ 0.98 × (VDD/2)
(dashed boxes in Figure 2b), the high peak gain is 344 V/V at
VM (Figure 2c), which are the best among the reported MoS2
inverters8,9,13−21,23−26 and necessary for constructing cascaded
integrated circuits. Moreover, the hysteresis of the transform
curve of the driver transistor could affect the performance of
the inverters. Because of the quality of HfO2 layer, the driver
transistor exhibits a ∼150 mV hysteresis and induced a ∼110
mV hysteresis in the VTC of inverter (Figure S6). Further
improving the quality of dielectric layer could eliminate the
hysteresis of inverters. Notably, this BM-inverter has a low
direct current (DC) power dissipation of ∼5.5 nW (Figure
S7), which is important for low-power dissipation and flexible
circuits.
We also demonstrate other logic circuits based on BMinverters. The output performance of the logic devices AND,
NOR, and NAND are shown in Figure 3a−c. The schematics
of the electronic circuit for the AND, NOR, and NAND logic
gates are shown in Figure S8. Each of the logic gates exhibits
excellent output stability with input signals (0,0), (1,0), (0,1),
and (1,1). All the logic states “0” and “1” are corresponding to
the voltage 0 and 4 V, respectively, with supply voltage VDD = 4
V. Notably, all the circuits exhibit rail-to-rail outputs with near
perfect high and low logic levels, which are attributed to the
high noise margin of BM-inverters.
The dynamic characteristics and uniformity of the BMinverters can be demonstrated in the performance of the ring
oscillator. We fabricated 3-stage ring oscillators based on BMinverters, as shown in Figure 4a. Additionally, to enhance the
oscillation frequency, we used a 20 nm Al2O3 as the dielectric
layer. Figure 4b shows the output voltage of the 3-stage ring
oscillator with stable oscillation frequency 32.5 kHz at a VDD =
10 V. This result demonstrates the good uniformity characteristic of the present BM-inverters. The delay time of each
inverter is around 5 μs, estimated by 1/2Nf, where N and f are
the number of stages and the oscillation frequency,
respectively. The output oscillation frequency can be adjusted
by varying the VDD. As Figure 4c shows, the ring oscillator
begins to oscillate at VDD ≈ 5 V with a frequency of 16.7 kHz
and can reach an oscillation frequency of 50 kHz at VDD = 12
V. Note that the oscillation frequency could be further
increased by decreasing the parasitic capacitance or the device
size.
In summary, we demonstrate a strategy for rail-to-rail
NMOS MoS2 inverters. A bilayer and MoO3 doped monolayer
MoS2 transistors were used as load and driver transistors in the
inverters. The BM-inverters exhibit a good rail-to-rail operation
with a switching threshold of VM ≈ 2 V = VDD/2 at VDD = 4 V,
high peak gain of 344 V/V, and a large noise margin NM ≈
0.98 × (VDD/2). Notably, the AND, NOR, and NAND logic
gates circuit exhibit rail-to-rail outputs with nearly perfect high
and low logic levels, which are attributed to the high noise
margin of rail-to-rail BM-inverters. The 3-stage ring oscillators
made of BM-inverters begins to oscillate at VDD ≈ 5 V, and
oscillation frequency reaches 50 kHz at a VDD of 12 V. Also,
this method could be transferable to other 2D semiconductors
for rail-to-rail inverters.
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ACS Applied Electronic Materials
■
pubs.acs.org/acsaelm
Jian Tang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Biying Huang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Rong Yang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; Songshan Lake Materials
Laboratory, Dongguan 523808, China; orcid.org/00000001-5936-6849
Luojun Du − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Wei Yang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China; Songshan Lake Materials Laboratory, Dongguan
523808, China; orcid.org/0000-0002-3925-0352
Dongxia Shi − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
ASSOCIATED CONTENT
sı Supporting Information
*
The Supporting Information is available free of charge at
https://pubs.acs.org/doi/10.1021/acsaelm.2c00444.
Details of device fabrication process and measurement;
fabrication process of BM-inverters; optical images and
AFM images of the original and after oxygen plasma
etched MoS2 on the silicon oxide substrate; XPS spectra
of Mo 3d core level of pristine monolayer MoS2 and
after O2 plasma etched (RIE) monolayer MoS2;
capacitance versus bias of 10 nm HfO2; definition of
noise margin and VM; hysteresis of driver transistor and
BM-inverter; power and the current of BM-inverter;
circuit diagrams of the AND, NOR, and NAND logic
gates (PDF)
■
Letter
AUTHOR INFORMATION
Corresponding Author
Guangyu Zhang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China; Songshan Lake Materials Laboratory, Dongguan
523808, China; orcid.org/0000-0002-1833-7598;
Email: gyzhang@iphy.ac.cn
Authors
Jinpeng Tian − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Yalin Peng − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Qinqin Wang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Yanbang Chu − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Zhiheng Huang − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Na Li − Beijing National Laboratory for Condensed Matter
Physics and Institute of Physics, Chinese Academy of Sciences,
Beijing 100190, China; Songshan Lake Materials
Laboratory, Dongguan 523808, China
Xiuzhen Li − Beijing National Laboratory for Condensed
Matter Physics and Institute of Physics, Chinese Academy of
Sciences, Beijing 100190, China; School of Physical Sciences,
University of Chinese Academy of Sciences, Beijing 100190,
China
Complete contact information is available at:
https://pubs.acs.org/10.1021/acsaelm.2c00444
Author Contributions
G.Z. supervised the experiments. J.T. fabricated the devices
and carried out the electrical measurements with the assistance
from Y.P. Q.W. preformed the growth of high quality MoS2
films with large domain sizes. J.T., W.Y., and G.Z. analyzed
data and wrote the manuscript. All authors discussed and
commented on the manuscript.
Notes
The authors declare no competing financial interest.
■
ACKNOWLEDGMENTS
This work was supported by the Key-Area Research and
Development Program of Guangdong Province (grant no.
2020B0101340001), the Strategic Priority Research Program
of Chinese Academy of Sciences (CAS, grant no.
XDB30000000), the National Science Foundation of China
(NSFC, grant nos. 61888102, 11834017, and 61734001). R.Y.
acknowledges the financial supports from the NSFC grant nos.
62122084 and 12074412.
■
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