Received 5 March 2023, accepted 23 March 2023, date of publication 27 March 2023, date of current version 30 March 2023.
Digital Object Identifier 10.1109/ACCESS.2023.3262285
Electrical Characterization by Counter-Doped
Pocket Design in Tunnel FETs
KI RYUNG NAM1 , (Student Member, IEEE), KWANG SOO KIM
WOO YOUNG CHOI 2,3 , (Senior Member, IEEE)
1 Department
2 Department
1,
(Senior Member, IEEE), AND
of Electronic Engineering, Sogang University, Seoul 04107, South Korea
of Electrical and Computer Engineering, Seoul National University, Seoul 08826, South Korea
Semiconductor Research Center (ISRC), Seoul National University, Seoul 08826, South Korea
3 Inter-University
Corresponding authors: Kwang Soo Kim (kimks@sogang.ac.kr) and Woo Young Choi (wooyoung@snu.ac.kr)
This work was supported by the NRF of Korea funded by the Ministry of Science and ICT (MSIT) under Grant
NRF-2021M3F3A2A01037927, NRF-2022M3F3A2A01073944 (Intelligent Semiconductor Technology Development Program),
NRF-2022M3I7A1078544 (Processing in Memory (PIM) Semiconductor Technology Development Program), and
NRF-2021R1A2C1007931 (Mid-Career Researcher Program).
ABSTRACT The effects of low net-doped region on the electrical performance of tunnel field-effect transistors (TFETs) are investigated using a TCAD simulation. Compared with previous studies, it is observed that
the low net-doped region between the source and pocket can enhance TFET electrical characteristics such as
the on-current (Ion ) and subthreshold swing (SS) with fine on-off current ratio (Ion /Ioff ). By optimizing the
length of the low net-doped region, Ion increased 14.6 times and SS is reduced by 34.6 % compared with the
TFET where the low net-doped region was not considered. Furthermore, guidelines for designing counterdoped pocket are proposed considering the low net-doped region. The local minimum in the conduction
band can be used to further improve the on-current and SS performance by adjusting the pocket width and
doping concentration. To avoid pocket-induced SS degradation, the pocket doping concentration must also
considered when determining the optimal value of the pocket width and vice versa.
INDEX TERMS Tunnel field-effect transistor (TFET), counter-doped pocket, low net-doped region, pocket
width, tunneling width.
I. INTRODUCTION
Recently, development of metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have been made up with
aggressive scaling of the gate length. However, as scaling
progresses, the magnitude of the off-current (Ioff ) increases,
degrading the device performances in terms of static power
consumption, on-off current ratio (Ion /Ioff ) and subthreshold swing (SS) [1], [2]. To compensate for this weakness,
tunnel field-effect transistors (TFETs) have been proposed.
TFETs operate via band-to-band tunneling (BTBT), unlike
MOSFETs, which operate by reducing the potential barrier
height with gate voltage [3], [4]. Unlike MOSFETs, because
there is no thermal injection in the subthreshold region,
TFETs can have a very low off-current and SS lower than
60 mV/dec [5]. In addition, because of the CMOS compatible
The associate editor coordinating the review of this manuscript and
approving it for publication was Chaitanya U. Kshirsagar.
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fabrication process, TFETs are attracting attention as nextgeneration devices to replace MOSFETs [6], [7].
However, TFETs are limited by their unacceptably low oncurrent as alternatives to MOSFETs [8]. To obtain a high
BTBT rate, numerous studies have been published, including the use of low bandgap materials such as SiGe or Ge,
L-shaped TFET, U-shaped channel structures, electron-hole
bilayer structures, heterogate structures and pocket layer formation [9], [10], [11], [12], [13], [14], [15], [16], [17], [18],
[19], [20]. Among these, it has been reported that the method
of forming a p-n-p-n structure by inserting a counter-doped
pocket next to the source can improve the on-current and SS
by increasing the lateral electric field [21], [22], [23], [24].
Simulation studies of TFETs with counter-doped pockets
have been conducted in a structure with a pocket and source
attached [21], [25], [26], [27]. However, when an n-type
pocket is formed next to a p-type source by tilt implantation or
epitaxial growth, a region with reduced doping concentration
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
FIGURE 1. Device structure of a planar TFET.
is inevitably created because of counter-doping at the sourcepocket junction [28]. In particular, epitaxy is known to form
a more abrupt junction doping profile than tilt implantation [21]. Because this sharp junction profile improves the
electrical characteristics of vertical PNPN TFET compared to
planar PNPN TFETs, many epitaxy methods are used to form
pocket layer [28], [29], [30]. However, even in vertical TFETs
with epitaxial grown pocket, this region with reduced doping
concentration is observed [28]. This region is defined as a low
net-doped region whose net-doping concentration is less than
the source or pocket doping concentration because of the p-ton transition at the source-pocket junction [28]. If there is a low
net-doped region between the source and pocket, the region
needs to be considered because the tunneling width is affected
by the device geometry [1]. It should be noted that factors that
modify device geometry, such as the state of the SiO2 -channel
junction and the low net-doped region, directly affect the
electrical characteristics of TFETs [31], [32], [33]. However, although the low net-doped region should be carefully
controlled to prevent the degradation of the TFET electrical
performance, no studies have investigated this phenomenon
in detail.
Therefore, in this study, we examine the effects of a low
net-doped region between the source and pocket on the electrical characteristics such as on-current and SS of the TFET.
To this end, simulations were conducted using the Sentaurus
TCAD tool, by changing the width of the low net-doped
region between the source-channel junction and the pocket.
In addition, an optimal design of a low net-doped region to
improve the electrical characteristics such as the on-current
value and SS was proposed. Furthermore, the electrical characteristics of the TFETs were studied based on pocket design
parameters, such as the pocket width and pocket doping concentration, considering the low net-doped region. Therefore,
guidelines for designing counter-doped pocket parameters
to improve the electrical characteristics of TFETs have also
been proposed.
II. SIMULATION SETUP
A basic planar TFET device structure with oppositely doped
source and drain regions and a lightly doped channel is shown
in Fig. 1. Dynamic nonlocal BTBT, Shockley-Read-Hall
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FIGURE 2. Calibration of the transfer curve with experimental data.
FIGURE 3. Simulated device structure of a TFET with a counter-doped
pocket.
recombination, Philips unified mobility model, and Fermi
distribution were used to implement TFET operation [34].
Calibration was performed on the major parameters to
improve the accuracy of the simulation results. For calibration, planar TFET device with the structure shown in Fig. 1
was fabricated. Based on experimental values, calibration of
the A and B parameters of the dynamic nonlocal BTBT model,
which adjusts the BTBT generation rate, was performed [35].
For calibration, the TFET device dimensions were the same
as those of the processed TFET device. Because the simulated
planar TFET has a symmetrical structure except for the source
and drain dopant, source-drain tunneling current (Iturn−on )
and source-drain ambipolar current (Iamb ) appear symmetrically [36]. However, because of the larger diffusivity of boron
compared to arsenic, degradation in the SS and magnitude of
on-current is observed in the experimental data. Therefore,
the calibration was based on Iamb rather than Iturn−on .
As shown in Fig. 2, the transfer curves of the experimental
data and calibrated data are mostly in good agreement.
The simulations were conducted in a structure with a heavily doped n-type pocket inserted next to the source, as shown
in Fig. 3. The pocket width and thickness are defined as Lpo
and Tpo , respectively. Although the gate length is so long in
comparison with the pocket width, the simulation results are
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
TABLE 1. Parameters used in the simulations and their values.
FIGURE 4. Transfer curves of the TFET with counter-doped pocket for
different Lspace .
reasonable because the electrical characteristics of TFETs,
including magnitude of on-current, are largely determined by
BTBT rate in the region near source-channel junction. The
gate length is not a critical parameter when investigating the
effect of the low net-doped region to BTBT rate, as it has little
effect to BTBT in the source region.
To reflect the low net-doped region, there is a space
with a low doping concentration between the pocket and
source-channel junction, and this space is defined as Lspace .
In addition, the drain was doped with a lower doping concentration (1018 cm−3 ) than the source, to suppress the ambipolar
leakage current [37]. Table 1 lists the device and process
parameters of the TFET used in the simulations.
III. LOW NET-DOPED REGION (Lspace ) VARIATION
In this section, the on-current, SS and Ion /Ioff , which are the
most important electrical characteristics of a TFET with a
counter-doped pocket structure, are analyzed.
A. ON-CURRENT PERFORMANCE
First, simulations were performed to confirm the changes in
the electrical characteristics of the TFET according to the
Lspace . In the simulation, the Lpo was fixed at 4 nm, where
the pocket was fully depleted and the best SS property was
achieved, when the pocket doping concentration was 5 ×
19 cm−3 [21]. Simulations were then conducted by dividing
Lspace from 0 nm to 20 nm at 1 nm intervals. Lspace = 0 nm is
when there is no space between the pocket and the source.
Fig. 4 shows the transfer curves for Lspace s of 0, 6, and
20 nm. The figure shows that the on-current is larger when
Lspace is not 0 nm than when Lspace is 0 nm. The on-current is
defined as the drain current at VGS = 1.5 V.
The on-current value increases because of the presence of
Lspace in the energy band. Fig. 5 shows the energy bands
for Lspace = 0 nm and Lspace = 6 nm. Band diagrams
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FIGURE 5. Band diagrams along the channel near the surface at Lspace =
0 nm and 6 nm (a) low VGS state (VGS = 0 V) (b) high VGS state (VGS =
1.5 V).
were obtained 2 nm below the surface. At the low VGS state
(VGS = 0 V) in Fig. 5a, the local minimum is clearly visible
at Lspace = 6 nm compared to Lspace = 0 nm. This local
minimum difference affects the on-current when the TFET
is turned on in the high VGS state (VGS = 1.5 V). In Fig. 5b,
for Lspace = 0 nm, a local minimum does not exist because
the pocket is fully depleted when the TFET is turned on.
However, for Lspace = 6 nm, a local minimum exists because
of the low net-doped region in the high VGS state, which
reduces the tunneling width. As a result, when Lspace = 6 nm,
the BTBT rate increased compared to when Lspace = 0 nm,
and the value of the on-current also increased.
Fig. 6a shows the lateral electric fields for Lspace = 0 nm
and 6 nm. It is observed that when Lspace = 6 nm compared
to when Lspace = 0 nm, the maximum value of the lateral
electric field decreases because the presence of Lspace change
the structure from a p-n junction to a p-i-n junction. However,
from Fig. 6b, when Lspace increases from 0 nm to 6 nm, the
BTBT rate increases. This is contrary to the previously studied counter-doped pocket behavior at Lspace = 0 nm, which
boosts the on-current by sharpening the band and reducing
the tunneling width through an increased lateral electric field
[21]. It can be predicted that the decrease in tunneling width
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
FIGURE 6. (a) Lateral electric field at Lspace = 0 nm and 6 nm (b) BTBT
generation rates at Lspace = 0 nm and 6 nm.
FIGURE 7. (a) On-current values for different Lspace (b) BTBT generation
rate for different Lspace .
FIGURE 8. Band diagrams along the channel near the surface at Lspace =
6 nm and 20 nm (a) low VGS state (VGS = 0 V) (b) high VGS state (VGS =
1.5 V).
by Lspace has a greater effect on the BTBT rate than the lateral
electric field reduction, resulting in an increase in the BTBT
rate.
However, after the peak at Lspace = 6 nm, the on-current
value decreased to Lspace = 20 nm, as shown in Fig. 7a.
This was confirmed by the change in BTBT rate, as shown
in Fig. 7b. The reason for this phenomenon is the change in
tunneling width owing to the increase in Lspace .
Fig. 8 shows the energy bands for Lspace = 6 nm and
20 nm. At the low VGS state in Fig. 8a, local minima are
clearly observed because Lspace is not 0 nm in both cases.
However, the locations of the local minima are different
because of the differences in Lspace . This affects the tunneling
width when the TFET is turned on with a high VGS state.
In Fig. 8b, it can be observed that the tunneling width is larger
for Lspace = 20 nm than for Lspace = 6 nm. This means
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FIGURE 9. (a) Tunneling distances for various energy levels at Lspace =
3 nm and 6 nm (b) band diagrams (VGS = 1.5 V) at Lspace = 3 nm and
6 nm.
FIGURE 10. (a) Lateral electric fields at Lspace = 6 nm and 20 nm (b) BTBT
generation rates at Lspace =6 nm and 20 nm.
that the effect of the increase in the tunneling width by the
increase in the low net-doped region was greater than that of
the band diagram modification by the local minimum. That
is, when Lspace exceeds the optimal value, the tunneling width
increases, in contrast with the previous intention. This is well
represented by the change in tunneling distance with Lspace ,
as shown in Fig. 9a. The tunneling distance is defined as
the distance between the conduction band and valence band
where BTBT occurs. Although the tunneling distance varies
depending on the measured energy level, it can be confirmed
that the tunneling distance increases when Lspace exceeds a
certain value, as expected.
It should be noted that in Fig. 9a, the minimum tunneling
width is the smallest when Lspace = 3 nm, rather than when
Lspace = 6 nm, where the on-current value is the highest.
The minimum tunneling width is defined as the tunneling
distance measured at the source Fermi level (EFS ), where
the tunneling distance between the source conduction band
and channel valence band is minimal [18]. This is because
the measured tunneling distance is highly dependent on the
measured energy level owing to the local minimum. Thus, the
tendency of the minimum tunneling width is different from
that of the minimum tunneling barrier, which should consider
both the tunneling width and tunneling energy window [1].
Fig. 9b shows a comparison of the band diagrams for Lspace =
3 nm and 6 nm. For Lspace = 3 nm, measuring the tunneling
distances at energy levels E1 and E2 which are 0.2 eV and
0.3 eV below EFS , respectively, increases tunneling distances
by 1.89 times and 2.45 times, respectively, compared to the
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
FIGURE 12. (a) Ion /Ioff for different Lspace (b) Ioff for different Lspace .
FIGURE 11. Average SS and on-current for different Lspace .
minimum tunneling width. On the other hand, for Lspace =
6 nm, the increase in tunneling distances compared to the
minimum tunneling width is only 1.03 times and 1.15 times
for E1 and E2 , respectively. Therefore, over the entire range of
energy levels over which BTBT occurs, the average tunneling
distance is shorter, and the tunneling barrier is lower for
Lspace = 6 nm than for Lspace = 3 nm. Therefore, a larger
BTBT rate was observed for Lspace = 6 nm than for Lspace =
3 nm, as shown in Fig. 7b.
Fig. 10a shows the lateral electric fields for Lspace = 6 nm
and 20 nm. For Lspace = 20 nm, it is observed that the value
of the maximum electric field decreases owing to the low netdoped region. From Fig. 10b, it is confirmed that the BTBT
rate also decreases with increasing tunneling width.
B. SUBTHRESHOLD SWING (SS) AND ON-OFF CURRENT
RATIO (Ion /Ioff ) PERFORMANCE
For TFET with counter-doped pockets, SS degradation is
used as the key factor in the performance evaluation along
with on-current boosting. The presence of a counter-doped
pocket causes SS degradation because the pocket behaves
like the source of the n-MOSFET. Therefore, previous studies
have reported that the pocket should be fully-depleted to
prevent SS degradation [21]. Fig. 11 shows the changes in
the on-current and average SS simultaneously with change
in Lspace . The average SS was measured as the gate voltage
required when the drain current increased for over 5 decades.
It should be noted that electron diffusion always contributes
to the drain current because the existence of a local minimum
implies that the pocket is not fully depleted in all ranges
of Lspace . Thus, SS depends on the dominant mechanism
of carrier transport between BTBT and electron diffusion.
In Fig. 11, up to Lspace = 8 nm, BTBT controlled by the gate
voltage dominates over diffusion because the tunneling width
is reduced by the local minimum. However, if Lspace is longer
than a certain value, SS degradation occurs as the effect
of electron diffusion by the pocket on the carrier transport
mechanism increases, as mentioned in previous studies. Thus,
30550
as shown in Fig. 11, when Lspace ≥ 9 nm, SS degradation was
observed.
Fig. 12a and 12b show the Ion /Ioff and Ioff , respectively,
with change in Lspace . From Fig. 12b, it can be observed that
the Ioff value increases as the on-current increases over the
Lspace range. However, even when Ioff is maximum, the value
is 1.05 × 10−17 A and does not change significantly with
change in Lspace . Therefore, the Ion /Ioff has a peak at a certain
Lspace , similar to the on-current tendency. This indicates that
if the counter-doped pocket is formed with an optimal Lspace ,
a high Ion /Ioff can be obtained by boosting the on-current
while maintaining the low off-current advantage of the TFET.
Therefore, when Lspace is not 0 nm, the local minimum in
the conduction band increases the on-current more than when
Lspace = 0 nm. However, if Lspace is larger than a certain
value, on-current degradation occurs; therefore, an optimal
length adjustment is required. From the simulations, it was
confirmed that the on-current was maximized when Lspace =
6 nm. The on-current value was 33.1 times higher than that
of the planar TFET, and 14.6 times higher than that of the
TFET with a counter-doped pocket, but Lspace = 0 nm. At
Lspace =6 nm, no SS degradation was observed, and a high
Ion /Ioff of over 108 and low off-current performance were
obtained.
IV. OPTIMIZATION OF POCKET DESIGN PARAMETER
The on-current and SS, which are the most affected [21] by
both the Lpo and Npo , were analyzed.
A. ON-CURRENT PERFORMANCE
Contrary to previous studies, when Lspace is not 0 nm, the
main reason for the on-current boosting is not the increase
in the lateral electric field by the pocket, but a decrease
in the tunneling width by the local minimum. Therefore,
simulations were performed to confirm the changes in the
on-current and SS of the TFET with changes in Lpo and
Npo when Lspace was not 0 nm. To determine the maximum
on-current value, the pocket design parameters except Lpo
and Npo were fixed to Lspace = 6 nm and Tpo = 3 nm,
which showed the best performance in terms of the on-current
value in Section III. To investigate the effect of Lpo , Npo was
fixed at 5 × 1019 cm−3 , the same value as in Section III. The
simulations were conducted by changing the length of Lpo
from 1 to 10 nm at intervals of 1 nm. Similarly, simulations
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
FIGURE 13. (a) Transfer curves of the TFET with counter-doped pocket for
different Lpo (b) on-current for different Lpo .
FIGURE 14. Band diagrams along the channel near the surface at Lpo =
2 nm, 3 nm, and 4 nm (a) low VGS state (VGS = 0 V) (b) high VGS state
(VGS = 1.5 V).
investigating the effect of Npo were conducted by changing
the value of Npo from 1 × 1019 cm−3 to 9 ×1019 cm−3 at
1 × 1019 cm−3 intervals at Lpo = 4 nm, the same value as in
Section III.
Fig. 13 shows the transfer curve and on-current value
with changes in Lpo . The on-current value increased as Lpo
increased. As shown in Fig. 14a, the local minimum became
wider and deeper as Lpo increased, as noted in a previous
study [38]. When the TFET is turned on, as shown in Fig. 14b,
the local minimum not only decreases the tunneling width,
but also increases the tunneling energy window to lower
the tunneling resistance and increase the BTBT rate. From
Fig. 15a, it can be observed that the value of the lateral electric
field increases as Lpo increases, because the length of Lspace
remains the same. That is, as shown in Fig. 15b, when Lpo =
4 nm, the BTBT rate is at its maximum, and the on-current
value increases.
Fig. 16 shows the transfer curve and on-current values with
changes in Npo . Fig. 16b shows that the on-current value
increased as Npo increased. As shown in Fig. 17, the local
minimum becomes deeper as Npo increases, similar to the
case when Lpo increases. Likewise, the lateral electric field
and BTBT rate increased as Npo increased and the tunneling
width decreased, as shown in Fig. 18.
Both the Lpo and Npo parameters affect to on-current by
adjusting the local minimum width and depth to reduce the
tunneling width. Therefore, the on-current tendencies are
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FIGURE 15. (a) Lateral electric fields at Lpo = 2 nm, 3 nm and 4 nm
(b) BTBT generation rates at Lpo = 2 nm, 3 nm and 4 nm.
FIGURE 16. (a) Transfer curves of the TFET with counter-doped pocket for
different Npo (b) on-current for different Lpo .
FIGURE 17. Band diagrams along the channel near the surface at Npo =
4 × 1019 cm−3 , 5 × 1019 cm−3 , and 6 × 1019 cm−3 (a) low VGS state
(VGS = 0 V) (b) high VGS state (VGS = 1.5 V).
FIGURE 18. (a) Lateral electric fields at Npo = 4 × 1019 cm−3 ,
5 × 1019 cm−3 , and 6 × 1019 cm−3 (b) BTBT generation rates at Npo =
4 × 1019 cm−3 , 5 × 1019 cm−3 , and 6 × 1019 cm−3 .
similar for both Lpo and Npo , as shown in Fig. 13b and
Fig. 16b.
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
FIGURE 19. (a) Average SS for different Lpo (b) minimum tunneling width
for different Lpo .
FIGURE 20. (a) Average SS for different Npo (b) minimum tunneling width
for different Npo .
B. SUBTHRESHOLD SWING (SS) PERFORMANCE
Previous studies have shown that the pocket width has significant effects on SS degradation. As Lpo increases, the local
minimum becomes deeper and wider, resulting in degradation
of SS [38]. Thus, it has been reported that an appropriate Lpo is required to completely deplete the pocket [21].
However, when Lspace is not 0 nm, as shown in Fig. 19a,
the increase in the BTBT rate by the local minimum dominates electron diffusion by the pocket for Lspace = 6 nm
or less. That is, SS degradation does not occur because the
carrier transport is controlled by the gate. However, when Lpo
exceeds 6 nm, SS degradation begins as the electrons diffuse
beyond the potential barrier from the local minimum, similar
to the previously reported subthreshold region operation of
n-MOSFETs [38]. This can be proven by the change in the
minimum tunneling width in Fig. 19b. For a relatively small
Lpo , the tunneling width decreased rapidly as Lpo increased.
However, as Lpo increases, the tunneling width saturates with
the BTBT rate. This indicates that electron diffusion in the
pocket, not BTBT, dominates the carrier transport for the oncurrent. That is, if Lpo is larger than a certain value, the TFET
behaves like a p-n junction and n-MOSFET connected in
series, and loses its advantage of low SS.
According to the simulation results, the optimal value of
Lpo was 6 nm, which maximizes the on-current without SS
degradation when Lspace and Npo were fixed at 6 nm and 5 ×
1019 cm−3 , respectively. The on-current is 2.2 times higher
than the on-current for Lpo = 4 nm, which is the maximum
on-current value in Section III. That is, when Npo and Tpo are
fixed at 5 × 1019 cm−3 and 3 nm, respectively, the optimal
on-current value is 2.2 nA, which is 66.7 times higher than
that of planar TFET. In addition, because there was no SS
degradation, a steep transfer curve could be obtained.
When Lspace is not 0 nm, SS is affected by both tunneling
width and electron diffusion because the pocket is not fully
depleted in most of the Lpo and Npo ranges. This means that
if Lspace is not 0 nm, the effect of Npo contributing to the local
minimum as well as Lpo should be analyzed. Fig. 20a shows
that the SS was minimum at Npo = 6×1019 cm−3 . When Npo
was 6 × 1019 cm−3 or less, BTBT dominated electron diffusion as the carrier transport mechanism. However, when Npo
becomes larger than 6 × 1019 cm−3 , electron diffusion starts
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FIGURE 21. Lpo required for minimum SS at each Npo .
to contribute more to the drain current than BTBT because
of the increased free electron concentration in the pocket.
Fig. 20b shows the minimum tunneling width that saturates as
Npo increases, similar to Fig. 19b. That is, the pocket behaves
as a source of n-MOSFET and causes SS degradation, similar
to TFET operation when Lpo is larger than the optimal value.
The simulation results show that when Lspace = 6 nm and
Lpo = 4 nm, the optimal value of Npo was 6 × 1019 cm−3
with a maximum on-current of 1.7 nA, and no degradation
of SS exists. This on-current is 1.5 times higher than the best
on-current in section III with Npo = 5 × 1019 cm−3 .
Therefore, when Lspace is not 0 nm, the key factor is to
obtain appropriate values of Lpo and Npo , as reported in
previous studies. However, the principle of determining the
optimal Lpo and Npo differs from that of previous studies. For
Lspace = 0 nm, the optimal value of Lpo was defined as the
pocket width when the pocket was just fully-depleted [21].
On the other hand, if Lspace is not 0 nm, the optimum length of
Lpo is the length at which the on-current is maximized without
SS degradation because BTBT is the dominant carrier transport mechanism. The optimal Lpo values with a minimum SS
at a fixed Npo are defined as Lpo,max. Fig. 21 shows Lpo,max
for each Npo value. As Npo increases, more electron diffusion
can occur at the same Lpo because of the increased free
electron concentration in the pocket. This implies that as Npo
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K. R. Nam et al.: Electrical Characterization by Counter-Doped Pocket Design in Tunnel FETs
increases, Lpo,max , which implies the maximum Lpo before
SS degradation occurs, decreases. Therefore, to prevent SS
degradation, Lpo should have a value less than Lpo,max at a
fixed Npo , and vice versa.
V. CONCLUSION
This work confirms the change in TFET performances with
variations in the low net-doped region and provides guidelines for pocket design parameters modified because of the
existence of the low net-doped region. The simulation results
indicate that when Lspace is not 0 nm, the tunneling width
is reduced by the local minimum. When Lpo = 4 nm is
fixed, the on-current increases up to 14.6 times compared
with that when Lspace = 0 nm. In addition, the SS is reduced
to 27.2 mV/dec, which is 34.6 % of the SS for Lspace =
0 nm. As the on-current boosting mechanism changed, the
method for determining the optimal pocket design parameters
Npo and Lpo changed. When Lspace is not 0 nm, the tunneling
width decreases, and the on-current increases as the depth
and width of the local minimum increase with increasing Npo
and Lpo . The results of the simulations show that in the Lpo
range where SS degradation does not occur, the on-current
increases by up to 2.2 times compared to that at Lpo = 4 nm
for the same Lspace and Npo values. In addition, the SS also
decreases to 20.2 mV/dec, which is 74 % of the value at
Lpo = 4 nm. In the Npo range where SS degradation does not
occur, the on-current increases by up to 1.5 times compared
to that at Npo = 5 × 1019 cm−3 for the same Lspace and Lpo .
In addition, SS decreases to 23.9 mV/dec, which is 72 % of
the value at Npo = 5 × 1019 cm−3 . However, as noted in
previous studies on TFETs with counter-doped pocket structures, on-current or SS degradation can occur when Lspace,
Lpo and Npo exceed their optimal values. Therefore, a process
capable of accurately growing Lspace and Lpo with a doping
concentration of Npo is required to prevent degradation of
electrical characteristics. Therefore, to form a highly doped,
ultra-narrow pocket layer, a vertical TFET structure, which
allows the pocket to be formed at a relatively accurate Lpo ,
Npo with low difficulty by using epitaxial growth, is adopted
rather than planar TFET structure using tilt implantation to
form pocket [28], [29], [30]. A process capable of accurately
growing Lspace , such as molecular beam epitaxial growth,
is required to achieve the best PNPN TFET performance [28].
Moreover, when fabricating PNPN TFETs, the presence of
low net-doped region helps PNPN TFETs to operate well,
by sharpening pocket doping profile and preventing dopant
segregation [28].
Hence, this study presents a solution to the low oncurrent problem while maintaining the low-power advantage
of TFETs by optimizing the length of the low net-doped
region that inevitably exists between the source and pocket.
ACKNOWLEDGMENT
The EDA tool was supported by the IC Design Education
Center.
VOLUME 11, 2023
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30554
KI RYUNG NAM (Student Member, IEEE) was
born in Daejeon, in 1998. She received the
B.S. degree from Chungnam National University,
Daejeon, South Korea, in 2021. She is currently
pursuing the M.S. degree with Sogang University,
Seoul, South Korea. Her current research interest includes tunnel field-effect transistor (TFET)
devices.
KWANG SOO KIM (Senior Member, IEEE)
received the B.S., M.S., and Ph.D. degrees
from the Sogang University, Seoul, South Korea,
in 1881, 1983, and 1992, respectively. From 1982
to 1998, he was with the Electronics and Telecommunications Research Institute, working on silicon devices (CMOS, bipolar, and BiCMOS).
From 1988 to 1992, he carried out his Ph.D.
dissertation on high-speed and high-density BiCMOS devices with the Sogang Graduate School.
He was the Principal Research Engineer with IITA, where he planned
new component technology about information and communication technology of South Korea, from 1999 to 2005, and with DGIST, where he
conducted research on IT convergence technology for intelligent vehicles,
from 2005 to 2008. Since 2008, he has been with Sogang University, where
he is currently a Professor with the Department of Electronic Engineering.
His current research interests include technology, modeling, and reliability
analysis of SiC power devices for electric vehicles and nanodevices.
WOO YOUNG CHOI (Senior Member, IEEE)
received the B.S., M.S., and Ph.D. degrees
from the School of Electrical Engineering, Seoul
National University, Seoul, South Korea, in 2000,
2002, and 2006, respectively. From 2006 to 2008,
he held a postdoctoral position with the Department of Electrical Engineering and Computer
Sciences, University of California at Berkeley,
CA, USA. From 2008 to 2022, he was a Faculty
Member and a Professor with the Department
of Electronic Engineering, Sogang University, Seoul. Since 2022, he has
been a Faculty Member with Seoul National University, Seoul, where
he is currently an Associate Professor with the Department of Electrical
and Computer Engineering. He has authored or coauthored more than
300 papers in international journals and conference proceedings. He holds
more than 50 Korean/U.S. patents. His current research interests include
the fabrication, modeling, characterization, and measurement of CMOS
logic/analog devices, emerging devices, memory devices, and brain-inspired
computing devices.
VOLUME 11, 2023