BITS, Pilani- K.K.Birla Goa Campus
First Semester 2023-24
Course Handout (Part-II)
In addition to Part I (General Handout for all the courses appended to the time table), this
portion gives further specific details regarding the course.
Course No.
: ECE/EEE/INSTR F215
Course Title
: Digital Design
Instructor-In-charge : Anita Agrawal
Team of Instructors : Ramesh Vasan ,Arun Raman, Chirayu Amita Dilip Athalye
:
Course Description:
This course covers the topics on logic circuits and
minimization, Digital ICs, Combinational and Sequential logic
circuits,
State
table
and
State
diagrams,
Programmable Logic devices, Arithmetic Operations and
Algorithms, Introduction to Computer Organization,
Algorithmic State Machines.
Scope and Objective:
The objective of the course is to impart knowledge of the
tools for the design of digital circuits and to provide methods
and procedures suitable for a variety of digital design
applications.
The course introduces fundamental concepts of Computer
Organization too. It also includes laboratory practice using
MSI devices.
Text Books:
T1: M.Morris Mano and Michael D.Ciletti, “ Digital Design”, PHI, 4th Edition
Reference Books:
R1 Donald D. Givone , “Digital Principles and Design”, TMH 2003
R2 Samir Palnitkar, “Verilog HDL”, Pearson Education.
Course Plan:
Lect.
No.
Learning Objectives
1
Introduction to Digital
Systems and
Characteristics of Digital
ICs.
2-3
4-5
6-8
9
Topics to be covered
Digital Systems, Digital ICs
Boolean functions, Canonical
Boolean algebra and logic forms, Standard forms,
gates
conversion between different
forms
Codes, Number Systems
Different Number systems such
as binary, octal etc and codes
such as BCD, Excess-3 etc..
K-Maps (2,3,4 & 5 variables),
Simplification of Boolean
Different types & levels of
functions
implementations.
Simulation and Synthesis
basics
Hardware Description
Language (HDL)
Reference to
Text Book
1.1; 1.9; 2.8, 2.9,
10.1,2
2.2-2.7
1.2-7
3.1 to 3.9
3.11
10-11
Combinational Logic,
Arithmetic circuits
Adders, Subtractors Multipliers
12-14
MSI Components
Comparators, Decoders,
Encoders, MUXs, DEMUXs
Simulation of
Combinational Logic
Functions.
HDL for Combinational Logic
15
Latches, Flip-Flops &
Characteristic tables
Analysis of clocked sequential
circuits, state diagram and
reduction
Shift registers, Synchronous &
Asynchronous counters
RAM, ROM, PLA, PAL, FPGA
TTL, MOS Logic families and
their characteristics
16-18
Sequential Logic
19-22
Clocked Sequential
Circuits
23-25
Registers & Counters
26-28
Memory and PLDs
29-31
Digital Integrated
Circuits
32-34
Analysis of arithmetic
units
Multiplication & Division
algorithms
35-37
Design of Asynchronous
Circuits.
Asynchronous Sequential Logic
38-40
Design of Digital
Systems using software
approach
Algorithmic State Machines
4.1 - 4-7
4.8 to 4.11
4.12
5.1 to 5.4
5.5, 5.7, 5.8
6.1 to 6.5
7.1-7.3 7.5 to 7.7
10.3-10.5, 10.7 to
10.9
Class Notes
9.1 – 9.4
R1: Chapter 8
Evaluation Scheme:
Component
Duration
Weightage
Midsem
1.5 hrs.
20%
Quiz
Comprehensive Examination
**
3 Hrs
scheduled
hrs.as per
time-table
**
10%
40%
Laboratory +Verilog eval
Lab Comprehensive
Date & Time
14-10-23
9:00 AM-10:30 AM
**
15-12-23 (FN)
20%
10%
CB/OB
CB
CB
CB
OB
**
CB
** To be announced later
Laboratory
S.No.
Name of Experiment
1.
IMPLEMENTATION OF BOOLEAN FUNCTIONS USING LOGIC GATES
2.
ADDERS AND SUBTRACTORS
3.
BCD ADDER
4.
DECODERS/ DEMULTIPLEXERS, MULTIPLEXERS AND COMPARATORS
5.
LATCHES & FLIP-FLOPS
6.
OPERATION OF 4-BIT COUNTER
7.
COUNTERS
8.
SHIFT REGISTERS
9.
SEQUENCE DETECTORS
Chamber Consultation Hour: To be announced in class
Notices: All notices and announcements will be posted in the course folder on moodle.
Make-up Policy: Make-up in any of the components may be granted only in extremely
genuine cases (admitted to hospital) and with prior permission.
INSTRUCTOR-IN-CHARGE