High-speed CMOS-to-ECL pad driver
in 0.18µm CMOS
F. Centurelli, G. Lulli, P. Marietti, P. Monsurrò, G. Scotti, A. Trifiletti
Dip. di Ingegneria Elettronica - Università di Roma “La Sapienza”
Via Eudossiana 18, I-00184 Roma, ITALY
centurelli@mail.die.uniroma1.it
Abstract—In this paper we present a CMOS-to-ECL converter
and pad driver, to provide true negative ECL outputs to a
positive-supply CMOS ASIC. The circuit exploits negative
feedback loops to precisely set the output voltages
corresponding to 0 and 1 logic ECL levels, and a high speed
current switch to allow a bit rate of hundreds Mb/s.
Simulations using 0.18µm CMOS technology show a bit-rate in
excess of 1Gb/s, with high tolerance to temperature and load
resistance and capacitance values.
I.
INTRODUCTION
To minimize propagation times and achieve higher clock
frequencies, MOSFET feature sizes have been continuously
decreasing, with a consequent reduction of breakdown
voltages. Digital ASIC’s are usually composed of a core, that
uses minimum feature size transistors and low supply
voltages (e.g. 1.8V, 1.2V), and interface circuitry. The latter
depends on the IC application environment, and typically
makes use of thicker oxide devices to allow a larger voltage
swing and thus higher noise margins. For very high speed
I/O, a differential low-swing standard interface, LVDS
(Low-Voltage Differential Signals), has been defined [1].
However digital ASIC’s, in particular for defense and
aerospace systems, have sometimes to be used in existing
and long-defined environments, with strong constraints on
the kind of interfaces to be used, to maintain backward
compatibility with IC’s they have to replace. ASIC’s could
be required to have at the same time low-voltage CMOS /
TTL, high-voltage CMOS (>15V) [2], negative (or positive)
ECL and LVDS interfaces. The availability of all these
interface circuits provides an increased amount of flexibility
to system designers and allows to build standard modules
that can be applied to a broader range of applications.
Designing interface circuits within the constraints of the
technology (maximum voltage across devices) allows the
IC’s to use input levels at the inherited voltage level of the
system they are connected to, while the logic operations are
performed at low voltage levels.
ECL logic family was typically used in the past for very
high speed digital circuits, at the cost of very high power
dissipation. Modern sub-micrometer CMOS technologies
can easily replace ECL circuits with a drastic reduction in
power consumption, but fast ECL-to-CMOS and CMOS-toECL interface circuits are difficult to design if true negativereferenced ECL and positive-supply CMOS are required [3],
due to the constraints imposed by the limited breakdown
voltage of MOSFET devices.
ECL-to-CMOS receiver interfaces can be designed as a
differential amplifier stage followed by CMOS inverters to
achieve full logic swing [4]. Input PMOS source followers
can be used to translate negative input levels above ground.
CMOS-to-ECL pad drivers have to provide precisely defined
voltage levels with the capability to drive 50Ω loads. Line
drive capability is typically provided by an open drain
PMOS device of suitable size, and output level accuracy is
achieved through the use of additional supply voltages or a
negative feedback loop that makes the output level equal to
the external or internal reference voltage [5]-[7]. As an
alternative, ECL pad drivers based on current switching
principle have been proposed [8] to achieve higher bit-rates.
In this paper we present a high-speed CMOS-to-ECL
converter and pad driver, that provides true-ECL output
voltage levels starting from CMOS voltage levels between
ground and VDD (positive supply voltage). ECL interface
specifications are given in Section II; Section III discusses
the design of the pad driver circuit, and simulations are
presented in Section IV.
II.
ECL PAD DRIVER SPECIFICATIONS
A number of different ECL families exists, each with its
own specification. The ECL 100K family is possibly the
most used one, thus we refer here to its characteristics. The
ECL 100K output buffer has to meet the following dc
specifications for the high and low output levels [9]:
-1.025V ≤ VOH ≤ -0.88V
-1.810V ≤ VOL ≤ -1.62V
with
load resistance:
RL = 50Ω
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Accurate output levels can be guaranteed by a feedback
Figure 1. Input and output voltage levels.
load power supply:
VTT = -2V ± 10mV.
The circuit is required to provide output voltages within the
prescribed levels for the whole temperature range
0°C ≤ ambient temperature ≤ 85°C
and for all conditions of load resistance and capacitance,
with:
35Ω ≤ RL ≤ 65Ω
0pF ≤ CL ≤ 10pF.
The ASIC core is designed using a 0.18µm CMOS
technology and uses 1.8V supply voltage; we assume that
3.3V supply devices are also available for interface circuitry.
However we will try to make use of low-voltage devices for
more generality. Fig. 1 shows internal and external voltage
levels to be interfaced.
III.
PAD DRIVER DESIGN
The main issues in the design of the CMOS-to-ECL
converter and pad driver are:
•
the need of shifting voltage levels from positivereferenced CMOS to negative ECL, with the constraint
of the limited breakdown voltage of the devices;
•
the need of an accurate control over ECL logic levels,
that requires closed loop structures;
•
the high-speed requirement, with its trade-off with the
stability of voltage control loop;
•
the high current drive capability needed to have ECL
voltage levels on a 50Ω external load with a –2V supply
voltage.
Figure 2. Voltage-loop ECL pad driver.
loop that sets the voltage drive for the output transistor
(voltage-loop) or the output current (current-loop) to cancel
the difference between the effective output level and the
required reference logic-1 or logic-0 level, provided by a
bandgap voltage reference. The typical structure of a
voltage-loop-based ECL pad driver is shown in Fig. 2: the
reference voltage is switched according to the bit to be
processed, and a fast feedback loop with a settling time
shorter than the bit period is required.
Very fast voltage switches for bit rates of hundreds Mb/s
are difficult to design using this technique. Current switches,
that exploit differential pairs to drive the tail current between
two branches, are typically faster, thus an alternative could
be the use of current-mode loops. As shown in Fig. 3, the
output current can be composed of a static bias current, that
sets the logic-0 ECL voltage (I0), and a current that is
switched on and off, or between two complementary outputs
to achieve the logic-1 level. The values of the currents can be
controlled by low frequency feedback loops that compare the
effective output voltage with reference voltage levels. These
loops behave as sampled-data systems, since the bits to be
transmitted activate the corresponding loop. However this
Moreover power dissipation has to be minimized, to simplify
system integration and packaging.
The high speed current drive capability is usually
provided by an open drain PMOS device; this choice allows
to bias the device with its source terminal connected to
ground, thus minimizing source-drain voltage and power
dissipation.
Figure 3. Current-mode ECL pad driver.
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Figure 4. High-speed ECL pad driver block scheme.
solution leads to a very high power dissipation, since a
positive supply voltage higher than ground is required to
correctly bias the circuit; moreover a current switch for
15-20mA requires very large transistors that have to be
driven by a very low impedance to switch fast. The use of an
NMOS differential pair with a 1:N ratio current mirror does
not solve the problems, due to the limited frequency response
of high-current PMOS current mirrors and the difficulty to
bias the circuit without using additional voltage supplies.
The solution we propose couples aspects from both
approaches to achieve a very high speed ECL pad driver
while trying to minimize power consumption. The voltageloop approach is preferred since high currents are required
only in the output stage, that can be biased with minimum
source-drain voltage, and there is no need of voltage to
current conversion, that could lead to less accurate output
levels. However two loops are used, that separately control
logic-1 and logic-0 output voltage levels: the loops require
fixed voltage references, provided by a bandgap, and are
controlled by switching the bias current to the appropriate
differential pair that compares the output voltage with the
desired level. Therefore only a low-current current switch is
required, that can be designed to be very fast. This solution is
simpler than using MOS transmission gates to switch the
reference voltage (Fig. 2), since full-swing control voltages
Figure 5. ECL pad driver circuit.
between ground and –2V would be required in that case to
drive the switches. The loop amplifiers need to be
compensated, and maximum bit- rate is limited by loop
bandwidth, that has to provide a settling time shorter than the
bit period. Fig. 4 shows a block scheme of the proposed pad
driver topology, and Fig. 5 details the loop selector and
output stage. A positive supply voltage of 1.2V is required to
correctly bias the circuit, whereas the high-current output
transistor uses ground as positive supply level. The level
shifter block in Fig. 4 has to drive the loop selector
differential pair, and is composed of a 1.8V-supply CMOS
inverter, a 1.2V-supply CMOS inverter to reduce the swing
and an NMOS source follower biased between 1.2V and –2V
supply rails, to shift the levels below ground. The reduced
voltage swing allows to design the circuit in Fig. 5 even
without using high-voltage devices, using PMOS cascode
current mirrors to keep the voltage across devices below
breakdown [10]. The 1.2V supply can be easily obtained
from the 1.8V core supply, thus no additional voltage source
is required on the board. Alternatively, the 1.8V supply rail
can be used, with 3.3V-breakdown devices.
The voltage-loop amplifiers have to be designed by
taking into account speed and stability requirements and the
capacitive load in parallel to the 50Ω resistor, if present. The
capacitive load limits the bandwidth of the circuit, either by
setting the dominant pole or by requiring a compensation of
the amplifier.
IV.
CIRCUIT SIMULATIONS
The proposed ECL pad driver has been simulated using
CMOS 0.18µm transistor parameters. The circuit in Fig. 5
has been extended by adding estimated parasitic
capacitances, since their effect cannot be neglected when
very high bit rates are considered. Simulations have been
performed by applying a pseudorandom bit stream to the
cascade of the ECL-to-CMOS receiver in Fig. 6 and the ECL
pad driver. Bond wire inductance and package parasitics
have been taken into account, to connect the external 50Ω
load resistance RL in parallel to a load capacitance CL.
Simulations at different bit-rates and with different
values of the load capacitance have been performed to test
the high-speed capabilities of the proposed circuit. Fig. 7
shows the ECL output signal for a bit-rate of 1Gb/s, when
the load capacitance is 5pF, highlighting a well open eye
Figure 6. ECL-to-CMOS receiver.
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diagram. Bit-rates as high as 1.5Gb/s are possible with a
lower load capacitance, whereas operation at 622Mb/s
(SONET OC-12) is possible for load capacitances in excess
of 15pF. Fig. 8 shows the output eye diagram at 1Gb/s versus
temperature, demonstrating stability of ECL output levels.
Figs. 9 and 10 show the sensitivity of the circuit to the
values of the output resistor and capacitor: the output ECL
signal at 1Gb/s presents an open eye diagram with limited
overshoot for load capacitors as high as 10pF and for load
resistor values in the range 35-65Ω. For smaller resistances
the loop gain is too low to obtain a small error with respect
to the reference voltage, whereas higher resistance values
result in an excessive overshoot. The circuit can be designed
to drive a higher capacitance by using a different
compensation capacitor (not shown in Fig. 4) for the voltageloop.
Figure 7. ECL output signal (1Gb/s, RL=50Ω, CL=5pF)
V.
CONCLUSIONS
This paper has presented a CMOS-only, true-ECL output
buffer, that provides a negative ECL output to a positivesupply CMOS ASIC core. The circuits is based on a lowcurrent current switch and two voltage-loops: no external
components or additional power supplies are required, and
high-voltage devices can be avoided by using cascode
current mirrors. Simulations on a circuit designed for 5pF
load capacitance have shown high-speed capability in excess
of 1Gb/s and good pulse response for a wide range of load
capacitance, with a good tolerance to load resistance and
temperature variations.
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Figure 8. Output signal vs. temperature.
Figure 9. Output signal vs. a) RL (35-65Ω) b) CL (0-10pF).
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