Solid-State Ekctronics Vol. 30, No. 3, pp. 307-319, 1987
0038-I lOI/
Printed in Great Britain
$3.00 + 0.00
Pergamon Journals
CHARACTERIZATION
OF CHARGE INJECTION
TRAPPING IN SCALED SONOS/MONOS
MEMORY DEVICES
Ltd
AND
CHEN-CHUNG C&mot and MARVIN H. WHITE
Lehigh University, Sherman Fairchild Center, Bethlehem, PA 18015, U.S.A.
(Received 1 June 1986; in revised form 20 August 1986)
Abstract-h
this paper we investigate scaled SONOS/MONOS (polysilicon-oxide-nitride-oxidesemiconductor)/(metal-oxide-nitride-oxide-semiconductor)
memory devices, and the characterization of
storage traps in the nitride. The amphoteric and closely-compensating trap models, which describe the
positive and negative charging of the nitride “memory” layer, have been compared. “Scaled” complementary SONOS and MONOS nonvolatile memory transistors with the nitride thickness ranging from
85 to 185 A have been designed and fabricated. The linear voltage-ramp
method, which measures the
flatband voltage shift and separates the charges at the injecting boundary
during the WRITE/ERASE
operations,
has been employed
to study non-steady
state trapping
in the nitride of “scaled” complementary SONOS/MONOS
devices for low voltage E’PROM’s (electrically erasable and programmable
read only memories). We have demonstrated
a differential, saturated flatband voltage shift of 6.5 V with
a k 8 V programming
voltage for scaled-down devices with dimensions of 20 A for the tunnel oxide, 85 A
for the nitride, and 51 A for the blocking oxide. Charge injection and trapping in scaled multi-dielectric
structures
have been modelled with an amphoteric
trap concept. The trap density N,,
N 10”cm-‘,
effective capture cross section of electrons and holes, ?J, 6; = 10-‘3cm2, and effective capture cross
section of neutral charge states, Sz, 8: z lo-l4 cm2, have been determined with an amphoteric trap model.
1. INTRODUCTION
Due to the rapid advances in silicon VLSI (very large
scale integration)
technology,
more research efforts
have been placed on high-density,
long-retentivity
and high-performance
nonvolatile
semiconductor
memories (NVSM) such as EPROM’s
(electrically
programmable
read only memories) or EEPROM’s
(electrically erasable and programmable read only
memories) for program storage in computer systems.
The MNOS
(metal-nitride-oxide-semiconductor)
type memory[l] and floating-gate type memory[2]
represent the state of the art technology for nonvolatile semiconductor memories. The floating-gate
type memories have advantages in long-term charge
retention since the gate oxide is relatively thick (e.g.
100-300 A) with the use of conventional MOS technology for the floating gate. On the other hand, the
MNOS type memories with their very thin tunneling
oxide (10-20 A) have faster write/erase characteristics
for NVRAM’s (nonvolatile random access memoradiation
and
superior
ries)[3] applications
hardness[4]. As the density of the integrated circuits
increases, “scaling” is needed for high-density, lowvoltage operation memories. Here, “scaling” means
the reduction in size of the physical device dimensions
for high-density VLSI chips. One problem in scaled
floating-gate type memories is that the entire memory
charge may be lost through a single defect, since the
floating gate stores charge in the free carrier state (i.e.
tPresent address: Microwave Semiconductor Corporation,
100 School House Road, Somerset, NJ 08873, U.S.A.
307
in the bands). The MNOS type memories represent a
viable alternative to the problems encountered with
the floating-gate type memories; however, the penetration of charge into the nitride under injection and
extended write/erase cycles (endurance) has severely
limited the scalability of MNOS type memories. The
multi-dielectric SONOS/MONOS
structure[5] has
been proposed to solve the scaling problem of dualdielectric structure in MNOS type memories[6].
Traps are electrically active states within the energy
bandgap of a material. Since traps are responsible for
the nonvolatile memory action, the understanding of
charge injection and trapping of carriers in the silicon
nitride film is very important. From the study of the
MONOS devices, the net charge in the nitride film
can be made either positive or negative by suitably
biasing the devices[7]. The net negative charge in the
nitride film is usually due to the electron injection
from the silicon conduction band, while the net
positive charge is created via the hole injection from
the silicon valence band. These observations indicate
two possibilitie@]. (a) The film contains two noninteracting sets of traps. One donor-like trap (N,,)
which can exist in positive or neutral charge states
and the other, an acceptor-like trap (NIA) with
negative and neutral charge states. Or (b) The film
contains an “amphoteric” trap that can exist in
negative (N- ), positive (N+ ), or neutral (No) charge
states. Arnett[9] has analyzed the high field injection
of carriers in the nitride to describe the distribution
of trapped electrons as a function of space and time,
which is the consequence of the assumption being
308
CHEN-CHUNG CHAO and MARVIN H. WHITE
made in this analysis. Initially all donor-like traps are
subsequently,
positively
charged,
and,
empty
whereas, acceptor-like
traps are negatively charged
and their occupancy is not altered during the electron
injection. The extended analysis including two noninteracting
traps and amphoteric
traps has been
derived recently[ IO, I 11.
Agarwal et a/.[121 have developed a non-steady
state. linear voltage-ramp
technique to separate electron and hole injection components.
It is based on the
charge separation concept of Ginovker et a[.[ 131. The
linear voltage-ramp
technique can provide a simultaneous measurement
of the flatband voltage shift
(AV,,) and the injected charge (AQn or AQ,). Previous methods[l3-191
employed to study trapping in
multi-dielectric
structures used the d.c. measurements
to determine the magnitude and sign of the carrier
crossing the injecting boundary;
however,
in the
so-called “steady-state”
there can be no trapping by
definition.
In addition,
d.c. measurements
rely on
charge
transport
across
interfacial
boundaries,
whereas, with a linear voltage ramp method the
displacement current is sensitive to “minute” levels of
charge injection and trapping without the requirement of d.c. conduction.
In fact, several orders of
magnitude
sensitivity improvement
is possible with
such dynamical measurements.
This paper concentrates
on the study of charge
transport and storage in multi-dielectric,
nonvolatile
memory microstructures
with particular emphasis on
scaled SONOS/MONOS
devices. The specific objectives of this work are, firstly, to fabricate and evaluate
the scaled SONOS/MONOS
devices with low programming voltages (5510 V), secondly, to compare an
amphoteric
trap model with a compensating
trap
model, both explain the scaled SONOS/MONOS
operation in terms of the nature and distribution
of
deep-level traps within the nitride memory layer, and
thirdly, to extract the silicon nitride trap modelling
parameters
with computer-aided
data acquisition
techniques and novel device structures.
2. THE SCALED MULTI-DIELECTRIC
MEMORY DEVICE
The conventional
MNOS device with nitride thickness of SOOA and tunnel oxide thickness of 20A
requires relatively high voltages, typically + 25 V, to
write and erase. It is undesirable to program MNOS
devices with such high voltage levels when the peripheral on-chip MOS transistors
are “scaled down”.
Thus, “scaling” must be applied also to the dualdielectric memory structure which implied a reduction in programming
voltage levels. The space charge
distribution,
due to the trapped charge in the nitride
of a MNOS memory device, produces a significant
modulation
of the nitride field outside the space
charge region which affects the “scaling” limit of
MNOS devices[20]. A Ifr 10 V programmable
MNOS
device with a 195 A thick S&N, has been reported by
Yatsuda et al.[21].
An approximate
scaling limit for the nitride thicknes is twice the charge centroid. For a nitride thickness less than this limit, charge trapping does not
occur effectively and such a thin nitride film is
difficult to use in a memory structure. The trapping
length for holes has been reported
to be greater
than
the
corresponding
trapping
length
for
electrons[20,22].
Therefore,
the hole distribution
in
the nitride determines
the scaling limit of MNOS
devices. This limitation is a consequence of the charge
“spreading”
into the nitride of the conventional
MNOS structures
with subsequent
“loss” through
the gate electrode. Lehovec et a!.[231 have observed
significant
hole injection
from the gate electrode
(aluminum) under positive gate bias in the MNOS
structure. To overcome the limitation of the scaleddown MNOS structure, Suzuki et a/.[61 proposed a
scaled-down
MONOS
structure.
The
stacked
SiOz(tunnel oxide)/Si,N,/SiO,(blocking
oxide) structure in Fig. I with bottom oxide thickness less than
20A has been employed as a nonvolatile
semiconductor memory structure[6]. The tunneling oxide acts
as a current injecting film for writing a charge into the
device, but it also prevents the back tunneling of the
charge from the nitride to the silicon. The blocking
oxide acts as a barrier to prevent injection from the
gate electrode. The nitride contains a high density of
traps and serves as a “memory” layer. The flatband
voltage shifts to the positive or negative direction
depending on the electron or hole injection through
the tunnel oxide. The extra layer is formed by the
“blocking” oxide located between the nitride and the
gate electrode. This layer may be formed by thermal
oxidation of the silicon nitride.
When charge is injected from the silicon substrate
through the tunnel oxide, it could be blocked at the
nitride/blocking
oxide interface, which results in an
increase in the trapping
efficiency of the injected
charge and removes the limitation on reduction of the
nitride thickness. The scaled-down
MONOS device
has several advantages for nonvolatile semiconductor
memories: (a) Oxidation of the thin nitride has been
proposed as a technique to create a high density of
electron traps[24]. These traps are attributed to oxyMONOS
Thin
SiO,
N-Si
Fig. I. The scaled MONOS structure
Charge injection and trapping in memories
gen at the nitride/blocking
oxide interface which
serve as the memory sites of scaled MONOS devices.
Therefore, the memory window will be unchanged in
spite of the reduction of the nitride thickness. (b) The
blocking oxide of scaled-down MONOS devices reduces hole and electron injection from the gate
electrode, which is responsible for the loss of charge
in MNOS devices. (c) The programming voltage
levels of scaled MONOS/SONOS devices will be
reduced. Low voltage operation with f6 V has
been demonstrated by the fabricated scaled-down
MONOS transistors with 20 A tunnel oxide, 85 A
silicon nitride and 51 A of blocking oxide[25].
Traps in the nitride are used as memory sites in the
MNOS device. Therefore, the charge storage capability in MNOS devices depends on the nitride thickness. Kapoor et aZ.[24] have found that the amount
of oxygen in the nitride is correlated to the trapped
charge, especially for electron trapping. Large
amount of electron traps have been introduced in the
MONOS structure formed by thermal oxidation of
the thin nitride[5]. MONOS memory devices are
expected to have improved retention characteristics
because the traps created
at the blocking
oxide/nitride interface increase the effective back
tunneling distance. The flatband voltage shift AVFB
includes the information about the charge distribution within the nitride and may be written as[lO]:
AVFB= -
(1)
=-
where X,,is the final nitride thickness after oxidation,
X0, is the blocking oxide thickness, eoe(=3.9) and
tN( =6.5) are dielectric constants of the blocking
oxide and the nitride, respectively, and R is the
centroid of the injected charge.
are assumed in this analysis. The compensating-trap
(two-trap) and amphoteric-trap (one-trap) models
have been reviewed. Both models can successfuly
interpret the charge conversion from positive to
negative (electron injection) or from negative to
positive (hole injection). The importance of an amphoteric trap model concept lies in the implicit assumption that there exists a simple, atomistic model
for the trapping processes[26], rather than the assumption of multiple trapping mechanism which
involve close compensation of positive and negative
charged species[27].
The single-level, amphoteric trap undergoes a transition from an unoccupied state N+ to a neutral state
No and, subsequently, to a doulbe-occupancy state
N-, by means of electron recombination. We neglect
emission processes (detrapping) for these deep-level
traps and write the coupled rate equation as [ll]:
N~~=rr+v,n,(l-j;-f~)N,-~~v,,nfYN,
(3)
NT%
= a;vdn,f
I]N,
(4)
where f z and f; represent the occupational probabilities of the single-charged (neutral) and doublecharged (negative) trap, respective1y.t a,’ and ut are
the capture cross sections of the ionized (nonoccupied) and neutral (single-occupied) traps states,
respectively, n, the free electron carrier density in the
conduction band of the insulator, v,,, the thermal
velocity of electrons, and NT the amphoteric trap
density. In addition, we will write the 1-D continuity
equation for the transport processes as:
dJ,(x, r)
-=--
ax
G%
at
(5)
Pn=qNr(l-f,-f:)-qNTf,-4%
J, = -qncvo
3. TRAPPING
309
(6)
= -g
MODEL
Arnett[9] has shown the occupancy function of the
trapped charge distribution in the nitride at high
fields for donor-like traps is given by
exp(x Ix, 1
ew[~Q(tYql-
1
’
(2)
where N, is the effective trap density (assumed to be
constant), and equal to the maximum density of
trapped carriers, x is the distance measured from the
oxide/nitride interface. x, is the trapping distance
defined as l/N,&, B is the effective capture cross
section of traps, and Q(t) is the total charge injected
into the nitride at time t. The charge conversion from
positive to neutral (electron injection) or from negative to neutral (hole injection) can take place because
the donor-like traps (or acceptor-like traps) processes
tf ,’ +f l +f ; = 1, conserves the total number of charged
trap sites.
where vg is the electron drift velocity. Diffusion
processes are neglected in the formulation of the
problem, since the electric fields are significant
(> lo6 V/cm) in insulator trapping[9,28].
In order to simplify the notation, we will use the
following definitions:
Equations (3H7) may be solved with the initial
conditions, f E(O) = 0 and f; (0) = 0, which implies
the system is initially free of electron occupation (i.e.
all trapping centers are in the N+ state). We have
neglected n, in equation (6) under the high field
condition,
because the upper bound
on the
magnitude of n, is set by J,/(qo,) which is on
the order of 10i2cm-r with J, x 0.1 A/cm3, and
vDx lO’cm/s[29]. This implies rre does not normally
contribute to the space charge compared with the
310
CHEN-CHUNG
CHAO
H. WHITE
and MARVIN
trapped charge. We have the occupancy functions for
the single-charge
(neutral)
and doubled-charged
(negative) trap states for the electron proceses as:
.f2=
(9)
e-;.n _
.f,, =1+
-J.n Rn
R,~
(10)
R/-l
The spatial extent of the trapped
insulator is
charge within the
-1
I
10
I
0
5
x/x,
_“e-“n,Rn
R
1
CR,- 1)
Fig. 3. Charge conversion curves based on the Amphoterictrap model with R, = 10,1, = G,‘Q,iq. and I,, = [li: IV,,] ‘.
where x,, = [B,t N,(x)]-’ is the effective electron trapping length and NT(x) is the spatially varying trap
density in the insulator. And i,,,, = &(O, t) > i.,,(x, 1)
and aQ,,(x, t)/& = 0 at .X = 0 (i.e. no initial free
charge gradient
in the conduction
band) J.,, is
the injection parameter
associated
with the charge
injection Q,,(O, 1) at the electrode boundary
to the
insulator. As R,)--+ r)
fjj+l-em’“=1
.i
II
+
‘i1+
exp(-x/x,,)
(13)
- 1I
exp(&)
0
(14)
The amphoteric
trap model reduces to the single
occupancy model of Arnett[9] [see equation (2)] for
large values of R, as shown in Fig. 2. The charge
conversion
(positive
to negative)
is observed
in
the net charge distribution
for various injection
levels with a uniform trap density N,,
R, = 10,
i,, = r?,~Q,,/q, and x,,, = [di NJ -’ (see Fig. 3).
A charge centroid for the trapped electron distribution consists of electron attached, primarily to neutral
sites, at low level injection levels. At high injection
levels the electrons are attached to doubly occupied,
negatively charged sites. The centroid
charge may be defined as:
X,V/
Ap, (x, t )x d.u
s
R = Ox,~,
of injected
(15)
AP~(x, t) d.w
s0
where AP”(x, t) = -qN,(x)(f’f
+ 2f n ) is the excess
space charge injected into the insulator and X,, is the
insulator thickness, where we have again neglected
the contribution
of n,. Figure 4 illustrates a numerical
integration
of equation
(23) for a uniform
trap
density N,. The centroid for the amphoteric
trap
model deviates strongly from the single occupancy
model[9] for low values of R, and high injection levels.
In summary,
the single occupancy
model of
Arnett’s[9] can be included in the amphoteric-trap
model for large values of R’s, where R is the ratio of
capture cross sections for ionized to neutral trapping
centers. The exact nature of the amphoteric
trap in
the silicon nitride is unknown; however, there has
been considerable
speculation
that silicon dangling
bonds are the origin of the amphoteric
trap[30].
5
4
x,=3
fr10
*
E
t;
Arnett's
results
3
x
\
Ixc 2
1
I
8
-J
I
10
X/X,”
Fig 2. Variation of occupational
probabilities.fjl
and.f,
as
a function of electron trapping length X,, for a constant level
A,, and variable capture cross section ratio R,[l
I].
0
1
I
I
I
I
2
3
4
5
x "0
Fig. 4. Variation
of electron charge centroid
R, __
as a
function of trapping length X,,, charge qectton
.
^
_,..- level A,,,,,
and ratto of capture cross secttons &[I It.
Charge injection and trapping in memories
Fig. 5. A photomicrograph
4. DEVICE
of complementary
FABRICATION
Complementary
MONOS and SONOS devices are
fabricated with a CMOS sequence. The 5-10 R cm,
substrates
are used. The scaled
(IOO), n-type
MONOS device has a tunnel oxide of about 20A
grown in dry oxygen at 730°C. The scaled SONOS
device (Fig. 5) has a thin oxide formed by an initial
preclean and in-situ reaction with the LPCVD chamber and estimated to be less than 10 A. The nitride
thickness ranging from 80 to 215 A is desposited in
a LPCVD reactor. It is performed with SiCl,H,:NH,
ratio of 30: 100 seem at a total reactor pressure of 300
millitorr at about 73O;C. The deposition rate is about
15 A per min. About 50 A of the blocking oxide is
formed when the nitride is oxidized in steam for
50min at 1000°C. The blocking oxide can also be
formed by the reaction of N,O and SiH,CI, in a
LPCVD system[31]. This in-situ method at constant
temperature
avoids the wafer handling which may
lead to particulate
contamination[31],
and also reduces the temperature
after nitride formation which
minimizes the outdiffusion
of hydrogen.
A polysilicon film of 5000 A is deposited with SiH,:N, ratio
of 5OO:lOO seem for 90min at a total pressure of
0.8 torr at 625°C from a LPCVD reactor. A plasma,
produced by gas discharge of SF,, is used to etch the
polysilicon
with these conditions:
gas flow rate30 seem, pressure-300
militorr, and power-250
W.
I. Film thicknesses in the MONOS/SONOS
MONOS, S-SONOS
Initial nitride
thickness (&,)
Final nitride
thickness (X,,)
structure
Blocking
thickness
M7
M2
116A
151 A
85 A
l20A
Ml0
175A
l40A
56 A
s2
173A
l45A
44A
S8
214A
185A
44A
51 A
48 A
M-
oxide
(X0,)
SONOS memory transistors.
The silicon nitride is etched in hot phosphoric acid at
180°C. The etch rate of the silicon nitride is about
100 A per min[32]. The silicon nitride etch rate is
reduced by lowering the temperature,
e.g. 45 A per
min at 165°C. The nitride is removed by a plasma
etch with 4% 0, and 96% CF, gases. The high
hydrogen temperature
annea1[33] with forming gas
(20% hydrogen and 80% nitrogen) at 800°C has been
performed to reduce the Si/SiO, interface states for
better charge retention. This is accomplished
by side
diffusion of the hydrogen from the contact window.
The active
memory
area is estimated
to be
1.6 x 10m3cm*. Table 1 illustrates
the calculated
blocking oxide thickness obtained from electrical and
optical measurements
for different processing conditions. The resulting blocking oxide thickness ranges
from 44 to 56A where a 5-10% variation of the
individual insulator thickness is anticipated
in the
calculation.
Figure 6 depicts a XTEM picture on a
scaled SONOS device with tunnel oxide thickness of
27 A, silicon nitride thickness about 130 A and a
blocking oxide thickness of 45-55 A. This picture was
taken ‘by a conventional
TEM (Philips-400T)
operated at 120 KeV with a magnification
of 360 KX.
5. EXPERIMENTAL
SONOS/MONOS
5.1.
Table
311
RESULTS
MEMORY
ON SCALED
DEVICES
Linear voltage ramp measurement
By combining
the charge centroid technique of
Yun[34] with the charge separation
technique
of
Ginovker et a/.[ 131, Agarwal et al.[ 121 have developed
the linear voltage ramp technique which minimizes
the back tunneling of the injected charge and separates the charge carriers at the injecting boundary
during the write/erase operation.
It also provides a
simultaneous
measurement
of the flatband voltage
CHEWCHUNG
312
CHAO
IN
and N
H. I%'HITI
Poly-
6. The
XTEM
picture
wth
1
oxide 1
Si3 N 4
( Storage
nitride
h
SiO,
( Tunneling
-
Si
(Si
HP-9836
HP-59313A
A/D
7. A
block
diagram
of
the
substrate
dlmenslona
arc
1
oxide)
k,,,
1
= 27 A.
1
I_
converter
c
Fig.
1
diagram of the computer-aided
data acquisition systern used for the mcasurcmcnt.
It is based on the HP
9836 desktop computer with an IEEE 488 Bus. The
linear voltage is supplied by the programmable
function generator
with a triangular
waveform.
The
r
-1
electrode
( Blocking
360 KX magnification. The device
X,, = I30 A. and ,Y,,,, = 45 55 A.
shift, AL’,,, and injected charges, AQ. and AQ,[25].
This technique
has been employed
to study the
non-steady-state
trapping in the thin nitride “storage” layer of the scaled SONOS/MONOS
nonvolatile memory devices. Figure 7 shows the block
(Gate
SiO2
J
Fig.
Si
automated
data-acquisition
measurement.
Jonts
system
supervorltemp
l’or the
linear
voltage-ramp
Charge injection
3-
(a)
_
..‘.’
and trapping
295K
IOOK
I
10
(b)
3-
P-channel
MONOS
WRITE
mode
295K
(A,
-ApI
A% .aP.
I
-3
v,
(VI
I
-3
-10
I
10
0
-10
0
J
10
V,(V)
Fig. 8. Various current components
scaled P-channel
MONOS device.
are area
in the write mode of a
The device dimensions
1.6 x 10m3cm2, X0, = 20 A, X,, = 85 A, and
X0,= 51 A.
source and bulk currents are measured
with the
Keithley 616 digital electrometers.
The analog outputs of the electrometers
and the ramp voltage are
sequentially
sampled by the A/D converter.
The
device is mounted in a TO-5 header and cooled in a
Janis Supervaritemp
Cryostat with liquid nitrogen.
The device is either a gated-diode or a transistor with
drain and source electrodes shorted together.
Consider a scaled P-channel MONOS devices with
the experimental curves shown in Fig. 8. If a positive
bias (+ 8 V) is applied, then electrons will tunnel from
the semiconductor
into the nitride conduction
band
and will be captured by the traps in the nitride film.
in memories
313
In addition, some holes may tunnel from the traps in
the nitride to the semiconductor.
The overall result
would be a net negative charge QN, in the nitride film
corresponding
to a positive flatband
voltage
V,
(+ 3.5 V). Next, the gate bias is swept from accumulation (+8 V) to a large negative bias (-8 V) into
strong inversion
and back to the starting value
(+ 8 V). The electron and hole current components
are shown in Figs 8(b) and (c). As the device is swept
from V,, which corresponds
to the initial flatband
voltage, to strong inversion at large values of the
negative bias, two processes may take place: (1) holes,
which are supplied by the diffused regions via current
IP, tunnel through the thin oxide and are trapped in
the nitride film, resulting in an increase in I, over and
above - aCcB and (2) electrons, which are previously
trapped in the nitride film, tunnel directly into the
silicon conduction
band, drift through the depleted
region, and are collected by the bulk electrode as I,.
This results in an excess “backtunneling”
component
for I, as shown in the band diagram (insert B) of Fig.
9 and a portion of the shaded area A in Fig. 8(b).
During the reverse sweep, holes are removed from the
inversion layer via I, which is positive and flows out
of the source electrode. Finally, the bias is swept past
the new flatband voltage Vz, which now is shifted to
a negative value (- 3 V).
In Figures 8(b) and (c), we only consider the sweep
between the initial and final voltages
V, and V,,
respectively.
Since the gate bias is proportional
to
time, the area under the I-V curve is proportional
to
the charge. The semiconductor
charge is the same
at points V, and Vz, and thus the hatched area
(A,-A,)/aA
under the Z, and IP curve represent
AQ,(C cmm2), the net electron charge released from
the insulator, and AQ, (C cme2), the net hole charge
trapped into the insulator, respectively. A represents
the device area. In addition, AV,, = V2 - V, can be
read directly from the 1, vs V, curve[lO]. The temperature dependence
of the characteristics
is also
shown in Fig. 8(a). The displacement
current at the
gate in the charge injection region is reduced below
that at room temperature.
This can be attributed to
the reduced penetration of the charge centroid due to
an increase in the thermal capture cross section of
attractive traps at a low temperature[l2].
The interface traps are also observed by the shift of the current
components
in the low temperature
measurement
shown in Fig. 8(a). In accumulation,
all the interfacial
traps below the Fermi level are essentially filled by
electrons. As the gate bias is swept to inversion, the
trapped electrons will be emitted from the interface
traps.
Figure 9 illustrates the gate current, I, energy band
diagram, and charge density distribution
in scaled
P-channel
scaled MONOS
structure
at different
points (surface potential) along the voltage sweep, V,.
Region A indicates the displacement
current in the
non-injecting
state, aC,, and back-tunneling
of previously injected electrons. Region B depicts tunneling
CHEN-CHLING CHAO and
314
MARVIN H. WHITE
--
1
-f
3r
I
a=0.2v/s
295 K
. . . . 100 K
-
’
I
G+/
F
,
E
..
a
9
‘9
x
b-4
.a....
f
o-
‘.
..
..
..,. .
.
--
.‘.......
-
. . . . . . . . . . . . ““““9
‘.
; . .
::
C
4
/
. . . . . . .. . . . . .......‘..
..
%k
A
::
z~
Fig. 9. The energy
band diagrams
at various
points in the voltage
device.
from the silicon substrate into the silicon nitride with
a concomitant
movement of the charge centroid into
the nitride. Region C has been observed for hole
injection where the centroid movement
“stops” as
traps appear to saturate. Another interpretation
is
the hole tunneling through the tunneling and blocking oxides is difficult due to increased barrier height
for tunneling but the electron can easily tunnel, i.e.
holes build up in valence band until the field permits
tunneling.
Region
D illustrates
the onset
of
Fowler-Nordheim
tunneling
through the blocking
oxide, which imposes a limit on device operation.
During the reverse sweep, region E and F corresponds to region A and B, respectively, as electrons
are injected into the silicon nitride[25]. Region G
shows Fowler-Nordheim
tunneling of electrons.
The write operation
is defined as a process of
generating a threshold voltage condition for a lowconductance
(LC) state. For a scaled N-channel
devices this pertains to electron injection of carriers
into the nitride (+ VG) from the inversion layer of the
silicon. The erase operation is defined as a process of
generating a threshold voltage condition for a highconductance
(HC) state. This pertains to hole injec-
sweep on a scaled P-channel
MONOS
tion of carriers into the nitride (- VG) from the
silicon surface accumulation
layer. For scaled Pchannel devices, the write operation
is defined as
- V, applied to the gate to create a LC condition,
while the erase operation
being defined as + V(,
applied on the gate to create a HC condition.
The
gate voltage polarity is just opposite in the operation
of a N-channel devices, i.e. - VG for erase operation
and + VG for write operation.
It is reasonable
to
assume the erase mode is equivalent
to the write
mode of the complementary
structure[8]. This permits the study of electron and hole “backtunneling”
[see Fig. 8(a)] since the charge collection efficiency is
high in the case where an inversion layer is formed on
the surface. Thus, electron backtunneling
can be
studied with P-channel
devices while hole backtunneling can be studied with the complementary
structure, the N-channel device. There is a problem
with
charge
separation
in the
erase
mode
operation[8].
For example, in a P-channel
device,
holes that are released from traps in the nitride
tunnel into the valence band of the semiconductor
[Fig. S(b)]. In order to be collected by the source
region, which may be 50-100 pm away, holes have to
Charge injection and trapping in memories
315
Table 2. The extracted charge centroid at low level of charge
injection of scaled MONOS and SONOS devices
M7-P
M2-P
MIO-P
M7-N
M2-N
MIO-N
XNf
zD (300 K)
85 A
120A
140A
XN/
85A
l20A
6A
21 A
27A
rn (300 K)
l4OA
XNJ
v
0
I
I
I
4
2
AQ
I
I
( x 10e6
4A
5A
4A
13A
20A
X, (200 K)
x, (100 K)
20A
8, (200 K)
4A
8A
IOA
K, (IOOK)
IIA
28 A
4A
17A
IA
6A
II A
-
6
1
C cm-*
Fig. 10. AVFB YS AQ. data at different temperatures in
the write mode of the MY’-Ndevice. The device dimensions
are X0,= 20 A, XN,= 85 A, _k& = 51 A, and area is
1.6 x 1O-3cm2.
drift in the space charge region over such long
distances.
There is a very high probability
of recombination
with electrons that are present in high
numbers in the accumulation
layer. Therefore, this
technique
would not detect any significant
hole
charge in the erase mode of P-channel devices. This
technique would not work for the erase operation of
N-channel devices as well. However, we are still able
to obtain a complete picture by using complementary
MONOS or SONOS structures.
5.2. Results and parameter
-
15A
26A
39A
P, (300 K)
145A
185A
S2-N
S8-N
I
x, (100 K)
x, (200 K)
extraction
The fabricated
MONOS devices with the same
tunnel oxide thickness
20 A, have three different
nitride thicknesses.
They are represented
by M7
M2
(X,,= 120A)
and
Ml0
(X,, = 85 A),
(XN/= 140 A). Furthermore,
M7-N or M7-P stands
for N-channel or P-channel MONOS device with the
nitride thickness of 85 A. In SONOS devices, they
are represented
by S2 (X,,= 145 A) and
S8
(X,, = 185 A). Figure 10 shows a typical set of curves
of AVFB vs AQ, of a N-channel
device with temperature
as a parameter.
AQp is neglected
since
AQ,>>AQ,. At low injection levels, the flatband volt-
age shift AV,, increases linearly with -the trapped
charge AQp. At high injection levels, AQp includes the
trapped charge and the free charge in the conduction
band of the silicon nitride. From AVFB vs AQ, data,
we are able to determine the charge centroid x,, as a
function of the injected charge AQp from equation
(1). Figure 11 is a set of R,, vs AQ, curves with
temperature as a parameter. Figure 12 and Figure 13
illustrates AV,, vs AQp and xP vs AQ, curves of a
P-channel
device.
52.1. Charge centroid. From AVFB vs AQ data, we
can extract the charge centroid for electrons and
holes with the equation[8]:
5
Fnn,$
= xN/+
x0, -
(16)
tJq
COB
At high levels of charge injection,
the charge
centroid is approximately
equal to half of the nitride
thickness, R n Z X&2 for a uniform or symmetric
charge distribution.
At low levels of charge injection,
the extracted charge centroid from scaled MONOS
and SONOS devices at different temperatures
are
summarized at Table 2. The accuracy of determining
Fn and rp depends upon the accuracy in determining
X,, and Xos, which has been mentioned in Section 4.
The charge centroid of electrons is slightly larger than
that of holes. The charge centroid tends to decrease
as the temperature
is decreased
during the mea-
10
100
0
295K
.
+
200K
IOOK
iM7-NJ
WRITE
:
V
0
0
2
A0
4
6
( x1o+c cm-’ 1
Fig. II. ,?” vs AQ. curves at different
write mode of the M7-N
temperatures
device.
in the
I
I
I
2
A0 ( xl@C
I
4
I
I
6
cm-*)
Fig. 12. AL’,, vs AQp data at different temperatures in
the write mode of the M2-P device. The device dimensions
are X0,= 20 A, X,,= 120 A, X0, = 48 A, and area is
1.6 x 10-3cm2.
CHEN-CHUNG CHAO and
316
100
_
0
-i
295K
. 2@IK
+ 100 K
(MZ-PI
WRITE
2
-
50
IX”
5r
4
.
cl
I0
.>’
MARVIN H. WHITE
3
-c
X
\
= 2
IX
,/;;’
.y,+,+,
+A+
+.+’
1
/+*
r
0
-_L_LI
2
I
AQ(
E
4
x10m6C cm-’
in the
_ 1 A(AQJ
Therefore, the trapping
lated from the interception
I
I
I
2
3
4
A,,=
surement. This may be attributed to an increase of the
capture cross section of attractive traps in the silicon
nitride at the reduced temperature.
The temperature
dependence
on the capture cross-sections
will be
discussed in Section 5.2.2.
5.2.2. Trapping parameters.
Trapping parameters
like the trap density N,, the capture cross section,
6,: or (if (8~ and 6;) and the capture cross section
ratio R, = (i,‘/c?f (R, = 6,/&E)
for a N-channel
(P-channel)
MONOS device are very important
to
characterize the electron (hole) injection in the silicon
nitride with an amphoteric trap model. The sequence
to extract trapping parameters
for electron injection
will be described as follows:
Figure 10 is the experimental
AVFB vs AQ, data
with different temperature
obtained from the linear
voltage ramp technique.
We begin with the generation of the charge centroid R,, vs AQ, curves as
described
in Section 5.2.1. The assumption
of a
uniform or symmetric trap distribution
in the nitride
is supported by the extraction of the charge centroid
at high injection level (R, z X,w,/2). The trap density
in the nitride N, can be calculated by the following
equation (see Appendix):
‘” - 44
I
1
)
Fig. 13. ,rP vs AQ, curves at different telnperatures
write mode of the M2-P device.
N
0
A8,,
length X,,, can be extrapoof the curves with the R,,
Fig. 14. The extraction
ii,+ A0
--+-
of R, in a N-Channel
(18)
X,, = X,?
Now the capture cross section of ionized trap states
6,: can be determined
by the following equations:
(19)
The normalized
x,/X,, vs I.,3 (= 6: A&/q) curves
can be generated
from 8, vs AQ, curves. If we
compare the theoretical R,jX,,, vs I.,, curve with the
experimental 8,,/X,,, vs i, curve shown in Fig. 14. then
we are able to determine
R,, which is the capture
cross section ratio between the positive charge state
and the neutral charge state. The extraction of R,, for
a P-channel device appears in Fig. 15. The capture
cross section of the neutral state can also be determined by:
-0
CT,,=-.
6,:
R,
For this particular device M7-N, we have obtained
the trap density N, z 2.4 x 10i9cm~‘, the capture
cross
section
of
the
positive
charge
state
”/
on x 2.7 x IO- ” cm’. the capture cross section ratio
R, e IO, and the capture cross-section
of the neutral
charge state 6): z 2.7 x IO I4cm’.
devxes based on an amphoteric trap model
)
Ram of capture
cross seclionb
Charge centrold and
trapping length (A)
Trapping density (cm ‘)
ti p =:(2.X *0.x)
x IO ‘I
6::=(2.X*0.x) x
K,,=n,6” : IO
a
.Y,,7 x,, = 10
A’,,, = I.8 x IOI”
(T = 300 K)
Electron trapping
parameters
Hole trappmg
pXkUIleterS
Capture cross sec,lo”
of neutral ,rap (cm’
device (M7-N).
axis (see Appendix). At small levels of charge injection, the trapping length X,,, is about equal to the
charge centroid R, from Fig. 4:
Table 3. A compamon of the average extracted trappn~ parameters of electrons and holes ,n MONOS
Capture cross Sectlo”
of iomzed trap (cm’)
I
5
IO ‘4
6,; = (2.1 t 0.6) x IO ”
ti”,/ = (‘.
- I -t
0.6)x
riK,,= ;;=
n
IO
R” = x,, =- 24
N, = 2.0 x IO”
IO “I
Charge injection and trapping in memories
0
I
I
I
1
2
.
x
PO
I
I
I
4
5
Bp-fvip
q
Fig. 15. The extraction of R,in a P-Channel
device (M2-P).
A similar sequence can be applied to the extraction
of trapping
parameters
for hole injection.
For
the metal gate device M2-P we have obtained
N m z 1.9 x lOI cm1113,the capture cross section of the
negative
charge
state
c?; x 3.7 x lo-l3 cm*, the
capture cross section ratio R,, z 10, and the capture
cross
section
of
the
neutral
charge
state
(ij z 3.7 x 1O--‘4cm2. For the polysilicon gate device
S2-N,
we have
obtained
N, o 1.5 x 10’9cm-3,
^ + z 6.5 x 10m’3cm2 , R,zz 10, and
811~6.5~
0,
lo-l4 cm*.
The results from scaled MONOS and SONOS
devices are summarized
below.
Hole charge centroid ranges from 6 A in nitride
film thickness of 85-27 A in film thickness of 140 A,
and electron charge centroid ranges from 15 to 39 A
at room temperature
and low level injection.
Effective (measured) hole capture cross section
ranges from 2 to 3.7 x 10~‘3cm2, and effective
(measured) electron capture cross section ranges from
1.4 to 1.8 x 10-‘3cm2.
The capture cross section ratio of electrons and
holes, R, and R,,, is approximately
10 for scaled
MONOS devices.
317
The effective capture cross section of neutral
charged states, 8: or Sf, is about one order of
magnitude
lower than the effective capture cross
section of charged states.
Density
of hole traps ranges from 1.6 to
1.9 x lOI cmm3, and density of electron traps ranges
from 1.7 to 2.3 x lOI cmm3.
The average trapping length of holes, X,, = 20 A,
is slightly less than the average trapping length of
electrons, X,” = 24 A.
The average capture cross section of SONOS
devices is greater than the average capture cross
section of MONOS devices.
In general, effective capture cross sections of
electrons
and
holes
increase
with
decreasing
temperature.
A comparison of extracted trapping parameters of
electrons and holes in MONOS devices based on an
amphoteric
trap model appears in Table 3. We
conclude electrons and holes (for low level injection)
have comparable centroids and trapping lengths. The
effective capture cross sections of electrons and holes,
6: and BP, are approximately
equal and on the order
of lo-l3 cm2, while the effective capture cross section
of the neutral charged states, 611 and 8;, are comparable and on the order of 10-14cm2.
The relationship of the temperature dependence on
the capture cross section can be obtained from a
treatment
similar to that of Lax’s cascade capture
mode1[36]. The energy level for capture can be easily
estimated with the equipartition
of energy for an
electron in a coulombic or non-coulombic
potential
(r-” dependence,
n = 1-4)[371. The capture process
occurs when the carrier (electron) falls 2 kT below the
conduction
band edge. We have the capture cross
section a,(T) z (,-*I”).
The measured or effective
capture cross sections of electrons and holes, 8: and
r?‘;, as a function of temperature
are plotted in Fig.
16. We have found the measured capture cross section of holes and electrons is proportional
to l/T’.S
and l/T*, respectively. However, o,(T) x (T-*.’ I0 --‘)
is related to the measured (effective) capture cross
section by considering the temperature dependence of
the thermal velocity and the drift velocity[lO]. We
may speculate the potential V(r) = l/r” with n zz 1 in
the silicon nitride is the driving force which gives rise
to the temperature dependence on the actual capture
cross section of electrons and holes.
6. CONCLUSIONS
56
0’
100
I
200
I
Temperature
Fig. 16. The average
perature
curves
xx)I
400I
500
1
1 K)
capture
cross section versus
for scaled MONO.5 devices.
tem-
In conclusion,
scaled complementary
SONOS
and MONOS transistors
with the nitride thickness
ranging from 85 to 185 A have been designed and
fabricated for low voltage programming
nonvolatile
semiconductor
memories.
The reduction
of the
nitride thickness is done by oxidizing the silicon
nitride with steam. A differential threshold voltage
shift of 6.5 V with a f8 V programming
voltage is
achieved for scaled-down devices with dimensions of
CHEN-CHUNG CHAO and MARVIN H. WHITE
318
20 A for the tunnel oxide, 85 A for the nitride, and
51 A for the blocking oxide. From the linear voltage
ramp measurements
on scaled SONOS/MONOS
devices, we have observed charge centroid movement
“stops” as traps appear to saturate for hole injection.
We may interpret the saturation
as a difference in
tunneling barrier heights of the blocking oxide for
electrons
and holes. The amphoteric
trap model
reduces to a single occupancy model of Arnett’s for
large values of R, the ratio of capture cross section
for ionized to neutral trapping centers. Important
modelling
parameters
such as the trap density,
IV7. z 10J9cm-‘, effective capture cross sections of
electrons and holes, S,+, 6; z IO-l3 cm2, and effective
capture cross sections of neutral charged states, 6:,
50%
p - 10 -j4cm2, have been determined
with linear
voltage-ramp
measurements
and an amphoteric
trap
model. The charge centroids and trapping lengths of
electrons and holes in the nitride are comparable
at
low injection levels with the average trapping length
of electrons,
X,, = 24 A, and the average trapping
length of holes, X,,, = 20 A. The temperature
dependence of the AV,, vs AQ and & vs VG is attributed to
an increase in the capture cross section of an attractive trap in the nitride layer at a reduced temperature.
Acknowledgements-The
authors would like to thank Dr
J-H. Huang for the XTEM study; and Mr F. C. Miller for
technology
support in device fabrication.
This work was
supported in part by the Sherman Fairchild Foundation,
the
National
Science Foundation,
and the Hewlett-Packard
Design Aids Program.
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APPENDIX
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I.
Trap density determination
At high levels of charge injection, the experimental
charge
centroidllO1 is approximately
equal to half of the nitride
thickness, k n z 2,,/2. which-supports
the assumption
of a
uniform or symmetric trap distribution
in the nitride. The
charge centroid can be rewritten as:
AO(
xlO+C
cm-‘)
Fig. 17. Determination
of the trap density, the trapping
length, and the capture cross section of charged states of a
N-channel
device.
Charge
injection
and trapping
where N, is the trapping density and AQ, = 2qN, A’,,,,is the
maximum
charge change in the nitride from positive to
negative.
At verv low iniection levels:
AQ(X,,z
0) + 0
and
x,(X,,%
0) + X,,.
Thus, the slope of the R, vs AQ. curve is:
J!!T!L=~“,(X,v,P)- R,W,v,=0)
WQ.1
AQ,V’,$)
- AQ.V,,
= 0)
L-
1
WJ,’
(A-2)
in memories
when X,,<<8,(X,,/2),
319
the trap density
N,%--.
1 WQ.1
yields:
(A-3)
4q Ax,
Equation (A-3) is also applicable to P-channel devices. The
determination
of the trap density, the trapping length, and
the capture cross section of charged states will be illustrated
in Fig. 17.