time and frequency
The effects of clock
jitter on data
conversion devices
As high-speed, high-performance
DACs and ADCs come on line,
understanding clock jitter issues
is critical to system design.
By Bar-Giora Goldberg
D
ata conversion devices are now common and
will become even more so as new applications arise. For example, the dream of the digital
software radio, especially for base stations of cellular and PCS, is closer now then ever. A highquality front end is digitized, then processed for
any air interface desired, including the global system for mobile communication (GSM), code-division multiple access (CDMA), and universal
mobile telecommunications system (UMTS).
For such processing, ultra-high dynamic range,
multibits and high-speed A/D (and D/A) converters
are necessary. In such high-quality devices, one must
PLL synthesis technology is generally recognized
as the optimum solution for generations of high-frequency timing sources with ultra low-jitter requirements. This article will review the effect of jitter on
the performance of data conversion devices and the
effect of phase-noise profile on clock jitter.
Background
Data conversion devices (analog-to-digital (A/D),
and digital-to-analog (D/A) digitize analog signals
or convert digitally represented signals to the analog domain. While D/A technology has been running
>1 GHz for a few years now, A/D conversion at
ultra-high speeds (as high as 300 MHz) with high
resolution (as high as 14 to 16 bits) is only now
coming of age. Digitizing involved quantization
causes an inherent error.
Using N bits, quantization error for data conversion devices is very easy to calculate as follows:
Signal energy, assuming a sine, has a peak-topeak of 2 N. Therefore, it has an RMS value of
2N–1/√2, and power level of S=22N/8.
The quantization error can occur equally randomly in the uncertain area, ±0.5. Its probability
density function is flat (p(x) = 1) and its power can
be easily calculated to be:
0.5
N =
q
∫x
−0.5
2
p (x )dx =
1
12
(1)
Therefore, the signal-to-quantization noise ratio
(S/Nq) is given by 1.5 x 22N or 6N+1.78 dB.
This is a well known and fundamental ratio in
DSPs and every extra bit adds theoretical 6 dB
performance.
This noise has a power spectrum of (Sinx/x) 2
where x=πf/Fc . Fc is the sampling (clock) frequency.
To simplify the calculations, assume that the noise
spectrum (see Figure 1) is flat with a single sideband
(SSB) bandwidth (BW) of Fc/2 Hz (fraction of dB error).
It is now easy to calculate the approximated
noise distribution generated by such a device, due
to quantization, based on its sampling frequency.
For example, a 14-bit A/D running at 100 MHz
generates a (SSB) noise floor of about –85.8–10
log(100e6)+3 ≈ –162.8 dBc/Hz. Hence, the theoretical
noise floor generated by quantization is very low.
Sampling and timing
Figure 1. Noise spectrum vs. single side-band bandwidth.
be extra careful when choosing the clocking source.
Excess phase noise (or jitter) can easily degrade the
performance of the data conversion devices.
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To this point, all has been assumed to be ideal.
The focus will now shift to the sampling mechanism.
An analog signal is being sampled by a clock
that has some jitter. A simple relationship
between this jitter and the effect it might have on
quantization error is desired.
All real signals have a phase-noise spectral profile, as shown below (see Figure 2). This noise creates jitter, which will therefore sample the signal
at the “wrong” places and create an amplitude
error, similar to reducing the converter’s accuracy.
The jitter allowed without affecting converter
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N
10
12
14
16
20
S/Nq
61.8
73.8
85.5
97.8
121.8
Table 1. Ideal S/Nq for various data conversion
devices.
Figure 2. Typical spectrum of a real signal.
accuracy will be determined.
Generally, if the signal’s spectrum can
be described by L(fm) (its spectral distribution), then the phase (or time) jitter
can be derived from that spectrum by:
f2
φj = ∫ L ( f ) df rad and
2
2
m
m
f1
φj
T=
2πF
(2)
width (speed) will have a direct effect on
the error. Slower signals are less sensitive to jitter. Therefore, jitter will have
an effect that is related linearly to Fs/Fc.
By sampling the sine at 0 it is easy
to calculate the jitter that causes the
converter to read 1 (or –1) instead. This
affects the converter’s resolution. Such
error will have an effect similar to
using a converter with less bits.
Given that the signal slope is ≈ 2N-1 •
2πFs, and jitter causes an error from 0
to ±1, the time jitter allowed is Tj =
1/2N-1 • 2πFs.
Because time jitter is related to sampling Fc by Tj = φj/2πFc, it can be concluded that the phase jitter allowed in
the clock is given by:
j
0
φ =
j
where Fo is the center frequency, φj is
the phase jitter in radians, f1 and f2 are
the frequency range of integration, Tj is
time jitter.
The signal has a certain bandwidth
and will be represented by a Sin-like
Figure 3. Signal vs. clock pulse waveforms.
(green) wave, sampled as shown by the
rising edge of the clock signal (red). i is
the running time (sample) index. (See
Figure 3.)
Suppose the signal is 2N-1Sin(2πFst)
sampled at Fc rate, then note the following:
• The signal will be most sensitive to
any sampling error around zero crossing. That is where the sine is changing
the fastest (there will be almost no sensitivity if we sample at the peak as
Sine is almost flat there).
• For the same reason, signal band-
28
F
•2
F
c
− (N −1)
(3)
s
In the worst case, signal bandwidth
is ½ of the sampling clock (Nyquist condition). This calculates to φ j = 2 –(N+2)
RMS.
An “arbitrary” assumption is made
that the required jitter is to be at least
four times better (when sampling,
peak-to-peak jitter this number is arbitrary, 4:1 (like 4σ), to be practical and
keep the equations simple).
Hence, in this article the assumed
required phase jitter is φj = 2–N rms.
These are tough numbers. A 14-bit
converter requires a clock that has
61µrad or 0.0035° noise (jitter in
degrees is the same in radians multiplied by 180/π), assuming that the signal BW is close to ½ Fc. For reference,
most cellular synthesizers require 2°
rms, or less, noise.
Figure 4. A PLL block diagram (Laplace domain).
for having low power, accuracy, flexibility and economy. PLL circuits are mature
and achieve excellent performance with
lower voltage and overall power.
PLLs include five basic functions: a
crystal (xtal) reference, a voltage-controlled oscillator (VCO), a phase detector, dividers, and a loop filter.
For generating low jitter signals
above 50 MHz, a PLL in combination
with a clean xtal reference is used.
PLLs offer simplicity, economy and low
noise floor in comparison with direct
multipliers, which are bulkier and significantly more expensive.
Most PLL circuits designed for timing use a third-order loop design (second-order filter).
Fr is the xtal frequency and Fo is the
output. At this stage, the assumption is
made that the reader is familiar with
basic PLL concepts.
PLL noise characteristics
A PLL has its own noise mechanisms. The majority of random noise in
timing devices comes from the PLL’s
phase detector/charge pump (PD/CP)
circuits, and the VCO.
The CP noise is multiplied by the
PLL transfer function, which acts like a
band-pass filter (in the baseband analysis, it looks like a low-pass filter); VCO
noise is multiplied by the loop error
transfer function, which has a “highpass” characteristic.
Therefore, integrated phase noise
depends on the range of integration as
determined by:
105
L = 2 • ∫ sin (f )df + 2 • ∫
PLLs
PLL is the technology of choice for
generating accurate signals, as well as
N (# of Bits)
φj (rms jitter allowed)
10
976 µrad
12
244 µrad
14
61 µrad
16
15.2 µrad
Table 2. Maximum allowable jitter vs. converter bits.
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2.4•108
105
100
sin (f )df ,
L = 3.948 • 10 radian ≈ 395 µrads
−4
0.5
(4)
Note that half of the noise comes from
the wideband floor noise.
105
L = 0 • ∫ sin t (f )df + 2 • ∫
2.4•108
105
100
sin t (f )df,
L = 2.191 • 10 radian ≈ 219 µrads
0.5
−4
(5)
Practical considerations
Everything calculated in regards to
ADCs obviously applies the same way
to DACs. Another way of looking at the
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Figure 5. The PLL’s main closed-loop transfer
function for a third-order loop with 10 kHz bandwidth has –12 dB slope away from loop corner
frequency (open loop is blue, closed loop is red).
These requirements add pressure on
the quality of the xtal used. PLL circuits must exhibit excellent phase
noise and VCOs must possess
demanding qualities.
A solution to the VCO requirements
is to use surface acoustic wave (SAW)
devices. While excellent filter devices,
they are narrowband and apply to single-frequency applications only.
Furthermore, such VCOs require
narrow loop (<500 Hz) with excellent
CP phase noise (see Figure 8). On the
other hand, a quality LC VCO (see
Figure 6. Simulation for 480 MHz signals derived from 10 MHz reference and
using a SAW-based VCO is shown below. Magenta is the VCO’s noise, blue is
the xtal, green is the CP and red is the composite. This simulation assumed a
super -performing, extremely low CP noise PLL chip.
results is to state that the jitter that
can be tolerated is generally given by:
Tj ≈ (2π • 2N • Fs) – 1
Figure 7 shows the jitter one must
require from the clock to meet certain
signal bandwidth and N number of
bits (signal is a 1 to 100 MHz, 8 to 16
bit converter) without violating quantization error (probability is Gaussian
with 4σ).
Jitter and phase noise are similar
representations of the same phenomenon: the random imperfection of timing
devices from the ideal zero-crossing
time location. The signal demonstrated
above is of very high quality. Still its
jitter might not be sufficient for some
demanding applications.
Note that the jitter was correlated
with signal bandwidth. If, instead of a
240 MHz signal spectrum (for a 480
MHz sampling) the bandwidth was down
to 25 MHz (cellular base station bandwidth), jitter could be relaxed by ~ 10:1.
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a commonly available PLL. Its specifications are shown in Figure 10.
Conclusion
To design accurate and functional
high-quality data conversion devices,
ADC and DAC, requires very low jitter clock signals. As ADC’s performance improves and speeds increase,
integrated phase noise of 2-N (for an N
bit converter) requires not only excellent phase noise but also a high-quality noise floor.
When designing these high-quality
Figure 7. As the signal BW and speed increase, the requirement on the clocks
becomes difficult.
Figure 9) at 600 MHz requires a loop in
the 10 to 20 kHz range, again with
excellent CP noise characteristics.
Jitter measures behavior in time and
represents an integrated number, while
the other (spectral phase noise) measures accurate noise profile in the frequency domain and allows the design,
analysis and measurement of the exact
noise profile.
Designer’s choice
Modern digital scopes cannot practically measure below 1 psec jitter. Phase
noise measurement, on the other hand,
can be measured using almost any synthesized spectrum analyzer.
Therefore, many engineers prefer to
use a spectrum analyzer not only for
absolute measurements, but also for
comparative analysis. At least this
offers an option for comparing among
competitors who demonstrate 1 psec jitter (the limit of most digital scopes).
Figure 10 shows a typical graph of
the concepts for a 2500 MHz clock and
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clocks, a quality VCO and a lownoise PLL chip must be used to
achieve the tight requirements for
high-speed circuits.
In addition, many of the converters
require differential emitter-coupled
logic (ECL) clocks, which are derived
from ECL application-specific integrated circuits (ASICs) converting sine to
positive emitter-coupled logic (PECL)
devices. These gates sometimes add
Figure 8. Phase noise profile of SAW VCO at 600
MHz.
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Figure 9. Response of a quality LC VCO at
900 MHz.
phase noise and especially
noise floor. Their use must be
weighted carefully, based on
experience gained, as they are
available from multiple
sources with varied performance characteristics.
Additionally, clock timing
for data conversion can directly
affect the converter accuracy
Figure 10. Jitter at about 0.25 psec.
and effective number of bits. Hence, its
dynamic range and noise floor – parameters of great importance in the applications where wideband signals or multiple signaling (base stations for example) are critical.
The choice of the right PLL circuit is
also critical, as shown by the simulations in this article. Finally, low phase
noise for the phase detector and CP circuits are critical as well, and both
active and passive loops can be used.
References:
[1] Data sheet of PE3335, Peregrine
Semiconductor PLL chip.
[2] W.P Robbins, “Phase noise in
Signal Sources,” Peter Peregrinus,
London, 1982.
[3] Bar Giora Goldberg, “Digital
Frequency Synthesis Demystified,”
LLH publishing, 1999.
[4] Peregrine Semiconductor, AN 13,
“Phase noise Demystified.”
[5] James M. Bryant, “The Effect of
Clock Noise on Sampled Data Systems,
ADI, 2001.
About the author
Bar-Giora Goldberg is President
and CTO of Vitcom Corporation, and
formerly technical director of
Peregrine Semiconductor. He
received his B.S. and M.S. from the
Technion Haifa. Goldberg co-founded
Sciteq, which pioneered DDS and
Fractional-n technology. His expertise is in the areas of Satcom, fast
hopping systems, adaptive antenna,
communications, spread spectrum,
frequency synthesis and system
analysis. Goldberg teaches signal
generation with Besser Associates
and CEI Europe. He can be reached
by e-mail at: giora18@tns.net
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