IC Compiler™
Tool Commands
Version L-2016.03, March 2016
Copyright Notice and Proprietary Information
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www.synopsys.com
IC Compiler™ Tool Commands, Version L-2016.03
ii
Copyright Notice for the Command-Line Editing Feature
© 1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software
contributed to Berkeley by Christos Zoulas of Cornell University.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following
disclaimer.
2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided with the distribution.
3.All advertising materials mentioning features or use of this software must display the following acknowledgement:
This product includes software developed by the University of California, Berkeley and its contributors.
4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Copyright Notice for the Line-Editing Library
© 1992 Simmule Turner and Rich Salz. All rights reserved.
This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of
the University of California.
Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and
redistribute it freely, subject to the following restrictions:
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3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software.
Since few users ever read sources, credits must appear in the documentation.
4.This notice may not be removed or altered.
IC Compiler™ Tool Commands, Version L-2016.03
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IC Compiler™ Tool Commands, Version L-2016.03
iv
Contents
1
add_buffer_on_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
add_clock_drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
add_distributed_hosts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
add_drc_error_detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
add_end_cap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
add_multisource_drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
add_open_drc_error_detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
add_pg_pin_to_db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
add_pg_pin_to_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
add_port_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
add_power_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
add_pst_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
add_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
add_tap_cell_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
add_to_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
add_to_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
adjust_fp_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
adjust_fp_io_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
adjust_premesh_connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
alias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
align_fp_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
align_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
all_active_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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all_ao_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
all_bounds_of_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
all_cells_in_bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
all_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
all_connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
all_connectivity_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
all_connectivity_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
all_critical_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
all_critical_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
all_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
all_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
all_drc_violated_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
all_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
all_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
all_fixed_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
all_high_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
all_ideal_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
all_inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
all_isolation_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
all_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
all_macro_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
all_mtcmos_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
all_objects_in_bounding_box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
all_outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
all_physical_only_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
all_physical_only_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
all_physical_only_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
all_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
all_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
all_rp_hierarchicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
all_rp_inclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
all_rp_instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
all_rp_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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all_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
all_size_only_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
all_spare_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
all_threestate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
all_tieoff_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
allocate_fp_budgets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
analyze_design_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
analyze_displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
analyze_fp_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
analyze_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
analyze_logic_connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
analyze_mv_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
analyze_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
analyze_subcircuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
append_to_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
apply_fast_pba_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
apropos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
archive_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
assign_flip_chip_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
associate_mv_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
associate_supply_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
balance_inter_clock_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
calculate_caa_based_yield2db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
cd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
change_connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
change_fp_soft_macro_to_black_box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
change_link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
change_macro_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
change_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
change_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
change_via_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
change_working_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
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change_working_design_stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
characterize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
check_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
check_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
check_database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
check_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
check_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
check_fp_budget_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
check_fp_pin_alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
check_fp_pin_assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
check_fp_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
check_fp_timing_environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
check_freeze_silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
check_interface_optimization_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
check_isolation_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
check_legality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
check_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
check_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
check_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
check_mpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
check_mv_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
check_noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
check_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
check_physical_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
check_primetime_icc_consistency_settings . . . . . . . . . . . . . . . . . . . . . . . . . . 374
check_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
check_reserved_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
check_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
check_routeability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
check_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
check_scan_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
check_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
check_signoff_correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
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check_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
check_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
check_zrt_routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
clock_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
clock_opt_feasibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
close_distributed_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
close_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
close_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
close_rail_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
commit_fp_group_block_ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
commit_fp_plan_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
commit_fp_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
commit_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
compare_collections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
compare_delay_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
compare_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
compare_rc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
compile_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
compile_fp_clock_plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
compile_power_plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
compile_premesh_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
compress_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
compute_polygons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
connect_logic_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
connect_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
connect_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
connect_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
connect_spare_diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
connect_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
connect_tie_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
continue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
convert_from_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
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Contents
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
convert_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
convert_to_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
convert_wire_ends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
convert_wire_to_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
copy_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
copy_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
copy_mim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
copy_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
copy_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
copy_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
count_drc_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
cputime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
create_auto_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
create_banking_guidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
create_base_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
create_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
create_boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
create_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
create_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
create_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
create_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
create_clock_mesh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
create_command_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
create_connview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
create_custom_wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
create_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
create_differential_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
create_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
create_drc_error_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
create_edit_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
create_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
create_fp_block_shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
create_fp_blockages_for_child_hardmacro . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
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Version L-2016.03
create_fp_group_block_ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
create_fp_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
create_fp_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
create_fp_plan_group_padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
create_fp_virtual_pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
create_freeze_silicon_leq_change_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
create_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
create_lib_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
create_logic_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
create_logic_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
create_macro_fram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
create_mask_constraint_route_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
create_mtcmos_switch_cell_sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
create_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
create_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
create_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
create_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
create_net_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
create_on_demand_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
create_open_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
create_open_locator_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
create_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
create_pad_rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
create_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682
create_pg_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
create_physical_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
create_physical_buses_from_patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
create_pin_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
create_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
create_placement_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
create_plan_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
create_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
create_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
create_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715
create_power_straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
create_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
create_power_switch_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
create_power_switch_ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
create_preroute_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
create_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
create_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
create_qtm_constraint_arc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
create_qtm_delay_arc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
create_qtm_drive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
create_qtm_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
create_qtm_load_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
create_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
create_qtm_path_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
create_qtm_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
create_rail_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
create_rdl_power_extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
create_rdl_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
create_rectangular_rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
create_rectilinear_rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
create_register_bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
create_route_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
create_routing_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
create_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
create_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
create_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
create_short_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
create_signoff_setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
create_site_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
create_spacing_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
create_stack_via_on_pad_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
create_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
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Version L-2016.03
create_supply_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
create_supply_set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
create_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
create_text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
create_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
create_user_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
create_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
create_via_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
create_via_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
create_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
create_voltage_area_feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900
create_zrt_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
current_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
current_design_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
current_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
current_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
current_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
current_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
cut_fp_preroutes_into_plan_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
cut_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
cut_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933
date . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
decrypt_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
define_antenna_accumulation_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
define_antenna_layer_ratio_scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
define_antenna_layer_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
define_antenna_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
define_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
define_io_antenna_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
define_io_diode_protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
define_io_gate_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
define_name_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959
define_proc_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
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IC Compiler™
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Tool Commands
Commands
L-2016.03
Version L-2016.03
define_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
define_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
define_user_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
define_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
define_voltage_area_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
define_zrt_redundant_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
delete_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
derive_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
derive_mpc_macro_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
derive_mpc_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
derive_mpc_port_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
derive_pg_connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
derive_placement_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
derive_reserved_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
disable_double_patterning_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
disconnect_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
display_flip_chip_route_flylines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
display_rdl_route_flylines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
distribute_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
drive_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
eco_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
enable_double_patterning_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
enable_primetime_icc_consistency_settings . . . . . . . . . . . . . . . . . . . . . . . . . 1060
enable_write_lib_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
end_fp_trace_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
error_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
estimate_fp_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
estimate_fp_black_boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
estimate_rc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
evaluate_macro_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
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Version L-2016.03
expand_flip_chip_cell_locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
expand_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
explore_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
export_advanced_technology_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
export_icc2_frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
extend_mw_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
extract_blockage_pin_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
extract_fp_rail_to_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
extract_fp_relative_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
extract_fram_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
extract_hier_antenna_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
extract_rc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
extract_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
extract_zrt_hier_antenna_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
filter_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
find_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
fix_isolated_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
fix_signal_em . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1141
flatten_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1144
flatten_fp_black_boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
flatten_fp_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149
flip_mim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1153
flip_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
focal_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
foreach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
foreach_in_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
get_adjusted_endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
get_alternative_lib_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
get_always_on_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
get_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1180
get_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
get_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
get_buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
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Tool Commands
Commands
L-2016.03
Version L-2016.03
get_cell_sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
get_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
get_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
get_command_option_values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
get_core_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
get_coupling_capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
get_cts_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
get_defined_commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
get_design_lib_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
get_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
get_dominant_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
get_dont_touch_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
get_dont_touch_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
get_drc_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
get_edit_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
get_em_max_toggle_rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
get_error_view_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
get_fill_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
get_flat_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245
get_flat_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
get_flat_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
get_floorplan_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
get_fp_trace_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
get_fp_wirelength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
get_generated_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
get_gui_stroke_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
get_latch_loop_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
get_layer_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
get_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
get_lib_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280
get_lib_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
get_lib_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
get_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
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Version L-2016.03
get_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
get_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1295
get_magnet_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
get_matching_nets_for_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
get_message_ids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
get_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
get_mw_cels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
get_net_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
get_new_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1327
get_object_fixed_edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329
get_object_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1331
get_object_snap_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1333
get_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1336
get_physical_buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1339
get_physical_lib_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
get_physical_lib_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
get_physical_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1351
get_pin_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
get_pin_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
get_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
get_placement_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
get_plan_group_pin_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1374
get_plan_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
get_polygon_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
get_power_domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
get_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
get_power_switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
get_rdl_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
get_related_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
get_route_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
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Contents
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
get_route_mode_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1406
get_route_opt_zrt_crosstalk_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
get_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409
get_route_zrt_detail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
get_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
get_route_zrt_track_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
get_routing_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
get_rp_group_keepouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
get_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
get_rp_groups_net_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1428
get_scan_cells_of_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
get_scan_chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432
get_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1433
get_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
get_si_xtalk_bumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1440
get_site_rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442
get_supply_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1448
get_supply_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1452
get_taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
get_terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1458
get_text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1463
get_timing_paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1468
get_tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
get_user_grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
get_user_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
get_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
get_via_masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
get_via_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1496
get_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
get_voltage_area_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
get_voltage_areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
get_working_design_stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
get_zero_interconnect_delay_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1515
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Version L-2016.03
get_zrt_net_properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
getenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1518
group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
group_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
gui_add_annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1532
gui_add_missing_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
gui_bin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
gui_change_error_highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1547
gui_change_highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1551
gui_check_drc_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1554
gui_clear_error_data_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1558
gui_clear_selected_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
gui_close_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
gui_create_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
gui_create_clock_graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564
gui_create_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
gui_create_pref_category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
gui_create_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572
gui_create_schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
gui_create_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
gui_create_toolbar_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1579
gui_create_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1581
gui_create_vm_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
gui_create_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1586
gui_create_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
gui_delete_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
gui_delete_menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
gui_delete_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
gui_delete_toolbar_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
gui_edit_vmbucket_contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
gui_error_browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
gui_eval_command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
gui_execute_menu_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
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Commands
L-2016.03
Version L-2016.03
gui_exist_pref_category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
gui_exist_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
gui_exist_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
gui_get_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1613
gui_get_bucket_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1615
gui_get_bucket_option_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617
gui_get_current_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1619
gui_get_current_task_item . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
gui_get_current_task_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
gui_get_current_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
gui_get_error_browser_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1625
gui_get_highlight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
gui_get_highlight_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
gui_get_layer_widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
gui_get_loaded_error_views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
gui_get_map_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
gui_get_map_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
gui_get_map_option_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
gui_get_menu_roots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
gui_get_mouse_tool_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
gui_get_pref_keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
gui_get_pref_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
gui_get_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1645
gui_get_routes_between_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
gui_get_setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
gui_get_task_list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
gui_get_task_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
gui_get_toolbar_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
gui_get_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
gui_get_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1657
gui_get_window_ids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1660
gui_get_window_pref_categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
gui_get_window_pref_keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1664
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gui_get_window_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
gui_hide_palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
gui_hide_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1670
gui_inspect_violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
gui_list_attrgroups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
gui_load_area_net_connection_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1676
gui_load_cell_density_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1678
gui_load_cell_slack_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1680
gui_load_clock_delay_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1682
gui_load_clock_tree_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1684
gui_load_delta_delay_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1686
gui_load_error_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1688
gui_load_hierarchy_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1690
gui_load_illegal_cell_placement_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692
gui_load_imported_path_pins_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1693
gui_load_net_capacitance_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695
gui_load_path_slack_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
gui_load_pin_density_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
gui_load_power_density_mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
gui_load_relative_placement_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
gui_load_scan_chain_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
gui_load_static_noise_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
gui_load_voltage_area_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
gui_mouse_tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
gui_overlay_layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1711
gui_query_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1713
gui_remove_all_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
gui_remove_all_rulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
gui_remove_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
gui_remove_pref_key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
gui_remove_ruler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
gui_remove_selected_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
gui_remove_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1726
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Contents
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Commands
L-2016.03
Version L-2016.03
gui_remove_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
gui_report_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
gui_report_hotkeys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1731
gui_schematic_add_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
gui_schematic_remove_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
gui_scroll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
gui_select_by_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
gui_select_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1742
gui_set_active_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744
gui_set_bucket_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746
gui_set_cells_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
gui_set_clock_sources_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
gui_set_connected_cells_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
gui_set_current_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
gui_set_current_task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1756
gui_set_edit_group_children_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
gui_set_error_browser_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
gui_set_error_data_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
gui_set_error_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1765
gui_set_flat_hierarchy_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
gui_set_highlight_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1769
gui_set_hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
gui_set_layer_widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1774
gui_set_layout_layer_visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1776
gui_set_layout_user_command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1778
gui_set_leaf_cells_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1780
gui_set_map_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782
gui_set_mouse_tool_option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1784
gui_set_net_flylines_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
gui_set_nets_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1788
gui_set_netshapes_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
gui_set_physical_buses_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
gui_set_pin_shapes_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1794
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gui_set_plan_group_pin_shapes_of_selected . . . . . . . . . . . . . . . . . . . . . . . . 1796
gui_set_plan_groups_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1798
gui_set_port_and_pins_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800
gui_set_pref_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802
gui_set_rdl_routes_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
gui_set_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
gui_set_routes_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
gui_set_select_menu_adds_to_selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
gui_set_selected_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
gui_set_setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1813
gui_set_terminals_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
gui_set_vias_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
gui_set_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
gui_set_vmbucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822
gui_set_voltage_areas_of_selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
gui_show_form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
gui_show_man_page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
gui_show_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
gui_show_palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833
gui_show_toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836
gui_show_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1838
gui_start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
gui_stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1843
gui_trim_dangling_wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
gui_unload_error_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
gui_unset_flat_hierarchy_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
gui_update_attrgroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
gui_update_pref_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
gui_update_vm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1854
gui_update_vm_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
gui_view_port_history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1861
gui_violation_schematic_add_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1865
gui_wave_add_signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1867
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IC Compiler™
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Tool Commands
Commands
L-2016.03
Version L-2016.03
gui_write_layout_image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1869
gui_write_window_image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1871
gui_zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1873
gui_zoom_all_layouts_to_current_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1876
gui_zoom_to_selected_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1877
help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1881
hookup_retention_register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
identify_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
if . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
ignore_site_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
import_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1895
import_fp_black_boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1898
index_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
initialize_rectilinear_block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
insert_boundary_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
insert_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1915
insert_diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922
insert_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1926
insert_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1930
insert_metal_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1933
insert_mv_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1939
insert_ng_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941
insert_pad_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1945
insert_port_protection_diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
insert_redundant_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
insert_self_gating_dft_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1955
insert_spare_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1958
insert_stdcell_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1962
insert_tap_cells_by_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1969
insert_well_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
insert_zrt_diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
insert_zrt_redundant_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
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is_double_patterning_enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
is_false . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
is_true . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
is_zrt_routed_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
legalize_fp_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
legalize_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
legalize_rp_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1994
lib2saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
license_users . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1998
link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
link_physical_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2007
list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
list_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010
list_dont_touch_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2013
list_drc_error_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2015
list_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017
list_floorplan_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2018
list_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
list_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2024
list_licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
list_mw_cels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
list_partition_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2030
lminus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2035
load_fp_rail_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2037
load_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2040
load_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2047
magnet_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2048
man . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2053
map_freeze_silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2055
map_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057
map_level_shifter_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2059
map_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2061
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
map_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2063
map_unit_tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2066
mark_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2068
mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2072
merge_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074
merge_flip_chip_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2076
merge_fp_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2078
merge_net_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2082
merge_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2084
modify_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
move_mw_cel_origin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2092
move_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2094
move_pins_on_edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097
mw_cel_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2100
name_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2102
open_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104
open_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2107
open_rail_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2109
optimize_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2111
optimize_dft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2116
optimize_flip_chip_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2118
optimize_fp_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2120
optimize_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123
optimize_pre_cts_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126
optimize_rdl_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2129
optimize_wire_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2132
optimize_zrt_wire_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2134
order_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2136
pack_fp_macro_in_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2139
parse_proc_arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
place_eco_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2144
place_flip_chip_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2153
place_flip_chip_drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2156
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Version L-2016.03
place_flip_chip_ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2159
place_fp_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162
place_freeze_silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167
place_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2172
place_opt_feasibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2176
prepare_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2181
preroute_focal_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2183
preroute_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2190
preroute_standard_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2198
preview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2209
print_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211
print_suppressed_messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2213
printenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2215
printvar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2217
process_particle_probability_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2219
propagate_all_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2221
propagate_clock_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2223
propagate_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225
propagate_pin_mask_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232
propagate_pin_mask_to_via_metal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2234
propagate_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2236
psynopt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2239
push_down_fp_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2244
push_flip_chip_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2253
push_rdl_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2257
push_up_fp_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2262
pwd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2267
query_cell_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2268
query_cell_mapped . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2270
query_map_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2272
query_net_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2274
query_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2276
query_on_demand_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2279
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Contents
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
query_port_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2280
query_port_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2282
query_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2284
query_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2286
query_pst_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2288
query_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2290
quit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2312
read_aif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2313
read_antenna_violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2317
read_aocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2319
read_ddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2322
read_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2324
read_drc_error_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2327
read_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2329
read_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333
read_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2335
read_parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2338
read_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2341
read_pin_pad_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2343
read_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2346
read_rail_maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2348
read_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2350
read_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2355
read_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2361
read_signal_em_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2365
read_stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2367
read_tdf_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2369
read_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2371
rebuild_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2374
record_cell_locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2376
recover_tie_connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2378
redirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2380
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redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2384
reduce_fp_rail_stacked_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2386
refine_fp_macro_channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2392
refine_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2394
remove_all_spacing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2397
remove_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2399
remove_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2402
remove_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2405
remove_annotations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2407
remove_antenna_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2409
remove_aocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411
remove_attachment_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2413
remove_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2417
remove_banking_guidance_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2420
remove_base_arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2421
remove_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2423
remove_buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2425
remove_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2428
remove_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2430
remove_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2432
remove_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2434
remove_cell_degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2436
remove_cell_sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2438
remove_cell_vt_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2440
remove_checkpoint_designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2442
remove_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2444
remove_clock_cell_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2446
remove_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2448
remove_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2450
remove_clock_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2452
remove_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2454
remove_clock_mesh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457
remove_clock_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2460
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
remove_clock_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2462
remove_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2464
remove_clock_tree_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2466
remove_clock_tree_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2470
remove_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2472
remove_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2475
remove_cts_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2477
remove_dangling_wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2479
remove_data_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2482
remove_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2485
remove_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2488
remove_diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2489
remove_disable_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2491
remove_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2493
remove_distributed_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2496
remove_dont_touch_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2498
remove_drc_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500
remove_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2502
remove_edit_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2504
remove_fast_pba_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2506
remove_filler_with_violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2507
remove_flip_chip_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2509
remove_floating_pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511
remove_fp_block_shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2513
remove_fp_feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2515
remove_fp_pin_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2519
remove_fp_pin_overlaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2521
remove_fp_plan_group_padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2523
remove_fp_rail_stacked_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2525
remove_fp_rail_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 2526
remove_fp_relative_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2528
remove_fp_virtual_pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2530
remove_fp_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2532
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IC Compiler™ Tool Commands
Version L-2016.03
remove_from_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2534
remove_from_rp_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2536
remove_generated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2538
remove_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2540
remove_ideal_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2542
remove_ideal_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2544
remove_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2546
remove_ideal_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2548
remove_ignore_cell_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2550
remove_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2552
remove_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2554
remove_io_antenna_properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2557
remove_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2558
remove_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2560
remove_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2562
remove_left_right_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2564
remove_level_shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2566
remove_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2568
remove_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2570
remove_map_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2572
remove_mim_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2574
remove_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2576
remove_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2578
remove_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2582
remove_net_routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2584
remove_net_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2586
remove_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2588
remove_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2590
remove_net_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2592
remove_net_timing_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2594
remove_noise_immunity_curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2595
remove_noise_lib_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2597
remove_noise_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2599
Chapter 1: Contents
Contents
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1-xxxi
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
remove_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2601
remove_on_demand_netlist_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2602
remove_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2603
remove_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2606
remove_pg_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2607
remove_physical_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2610
remove_pi_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2612
remove_pin_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2614
remove_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2616
remove_pin_pad_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2619
remove_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2621
remove_placement_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2623
remove_plan_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2625
remove_pnet_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2627
remove_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2629
remove_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2631
remove_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2633
remove_power_plan_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2635
remove_power_ring_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637
remove_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2639
remove_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2641
remove_propagated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2643
remove_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2645
remove_rail_integrity_layout_check_strategy . . . . . . . . . . . . . . . . . . . . . . . . 2647
remove_rail_maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2649
remove_reserved_placement_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2650
remove_route_by_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2652
remove_route_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2655
remove_routing_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2657
remove_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2659
remove_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2661
remove_row_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2663
remove_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2665
Contents
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Version L-2016.03
remove_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2668
remove_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2670
remove_scan_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2672
remove_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2673
remove_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2675
remove_self_gating_logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2677
remove_site_row . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2679
remove_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2681
remove_stdcell_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2682
remove_steady_state_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2684
remove_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2686
remove_supply_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2689
remove_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2691
remove_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2693
remove_text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2695
remove_tie_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2697
remove_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2700
remove_unconnected_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2703
remove_user_budgeted_delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2705
remove_user_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2707
remove_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2709
remove_via_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2711
remove_via_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2713
remove_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2716
remove_voltage_area_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2718
remove_vt_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2720
remove_well_filler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2722
remove_xtalk_prop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2724
remove_zrt_filler_with_violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2725
remove_zrt_redundant_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2728
rename . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2731
rename_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2733
rename_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2735
Chapter 1: Contents
Contents
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1-xxxiii
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
replace_cell_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2737
replace_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739
report_access_preference_route_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2742
report_adjusted_endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2744
report_ahfs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2746
report_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2748
report_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2750
report_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2753
report_antenna_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2755
report_antenna_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2757
report_aocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2759
report_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2764
report_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2766
report_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2771
report_banking_guidance_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2774
report_block_abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2776
report_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2779
report_buffer_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2781
report_buffer_tree_qor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2784
report_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2786
report_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2788
report_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2790
report_cell_em . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2794
report_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2796
report_cell_physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2799
report_cell_vt_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2803
report_channel_capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2805
report_check_library_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2809
report_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811
report_clock_cell_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2816
report_clock_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2818
report_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2830
report_clock_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833
Contents
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Version L-2016.03
report_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2847
report_clock_tree_optimization_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2860
report_clock_tree_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2862
report_clock_tree_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2866
report_concurrent_clock_and_data_strategy . . . . . . . . . . . . . . . . . . . . . . . . . 2873
report_congestion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2875
report_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2879
report_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2881
report_critical_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2890
report_crpr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2893
report_cts_batch_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2898
report_delay_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2900
report_delay_calculation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2907
report_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2909
report_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2911
report_design_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2917
report_design_mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2919
report_design_physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2922
report_direct_power_rail_tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2932
report_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2934
report_displacement_analysis_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2936
report_distributed_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2938
report_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2940
report_dont_touch_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2943
report_drc_error_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2946
report_droute_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2948
report_eco_history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2951
report_eco_physical_changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2954
report_edit_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2958
report_em_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2960
report_error_coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2962
report_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2964
report_fast_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2968
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Version L-2016.03
report_fast_pba_analysis_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2969
report_feasibility_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2971
report_filler_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2973
report_fix_hold_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2975
report_flip_chip_bump_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2977
report_flip_chip_driver_bump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2979
report_flip_chip_flyline_cross . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2981
report_flip_chip_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2984
report_floorplan_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2987
report_fp_clock_plan_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2990
report_fp_feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2991
report_fp_macro_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2999
report_fp_macro_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3001
report_fp_pin_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3003
report_fp_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3005
report_fp_placement_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3007
report_fp_rail_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010
report_fp_rail_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012
report_fp_rail_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3014
report_fp_rail_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3018
report_fp_relative_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3020
report_fp_shaping_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3022
report_fp_trace_mode_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3024
report_fp_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3025
report_fram_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3026
report_groute_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3029
report_gui_stroke_bindings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3031
report_gui_stroke_builtins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3033
report_hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3035
report_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3037
report_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3039
report_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3043
report_instance_based_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3044
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report_inter_clock_delay_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3046
report_interclock_relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3048
report_internal_loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3052
report_io_antenna_properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3054
report_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3056
report_isolated_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3058
report_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3062
report_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3066
report_latch_loop_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3069
report_latency_adjustment_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3072
report_left_right_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3073
report_level_shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3074
report_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3078
report_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3096
report_matching_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3098
report_metal_density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3100
report_milkyway_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3103
report_mim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3106
report_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3108
report_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110
report_mpc_macro_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113
report_mpc_macro_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3115
report_mpc_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3117
report_mpc_pnet_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3119
report_mpc_port_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3121
report_mpc_rectilinear_outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3123
report_mpc_ring_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3125
report_mtcmos_pna_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3127
report_multisource_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3129
report_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3131
report_name_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3133
report_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3136
report_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3139
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L-2016.03
Version L-2016.03
report_net_changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3144
report_net_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3147
report_net_physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3150
report_net_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3155
report_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3157
report_net_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3159
report_net_search_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3163
report_net_search_pattern_delay_estimation_options . . . . . . . . . . . . . . . . . 3165
report_net_search_pattern_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3167
report_noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3169
report_noise_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3173
report_ocvm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3177
report_on_demand_netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3182
report_opcond_inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3184
report_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3186
report_optimization_created_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3188
report_optimization_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3190
report_optimize_dft_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3191
report_optimize_pre_cts_power_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3192
report_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3193
report_path_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3195
report_pg_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3197
report_physical_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3199
report_physical_signoff_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3201
report_pi_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3203
report_pin_guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3205
report_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3207
report_pin_pad_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210
report_pin_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3212
report_place_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3214
report_placement_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3216
report_pnet_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3219
report_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3221
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report_port_protection_diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3227
report_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3229
report_power_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3237
report_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3243
report_power_gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3249
report_power_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3251
report_power_pin_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3253
report_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3257
report_power_plan_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3259
report_power_ring_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3261
report_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3263
report_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3265
report_preroute_advanced_via_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3267
report_preroute_drc_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3271
report_preroute_focal_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3274
report_primetime_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3276
report_pst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3278
report_qor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3282
report_qor_snapshot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3287
report_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3289
report_rail_integrity_layout_check_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . 3292
report_rail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3294
report_rail_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3296
report_read_stream_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3298
report_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3300
report_reference_cell_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3303
report_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3305
report_route_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3308
report_route_opt_zrt_crosstalk_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3310
report_route_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3311
report_route_rdl_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3313
report_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3315
report_route_zrt_detail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3316
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Tool Commands
Commands
L-2016.03
Version L-2016.03
report_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3317
report_route_zrt_track_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318
report_routing_corridors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3319
report_routing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3322
report_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3324
report_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3326
report_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3330
report_scan_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3333
report_scenario_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3335
report_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3338
report_separate_process_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3341
report_si_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3342
report_signal_em . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3344
report_signal_em_calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3347
report_size_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3349
report_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3352
report_spacing_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3354
report_split_clock_gates_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3356
report_starrcxt_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3357
report_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3359
report_supply_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3361
report_taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3363
report_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3365
report_threshold_voltage_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3367
report_tie_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3371
report_tile_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3372
report_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3375
report_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3390
report_timing_histogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3394
report_timing_requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3398
report_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3403
report_top_implementation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3405
report_total_power_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3407
Contents
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Version L-2016.03
report_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3409
report_transitive_fanin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3411
report_transitive_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3413
report_unit_tiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3416
report_units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3418
report_user_budgeted_delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3420
report_via_master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3422
report_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3424
report_voltage_area_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3426
report_vt_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3428
report_write_lib_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3430
report_write_stream_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3431
report_xtalk_route_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3433
report_zrt_net_properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3434
report_zrt_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3436
reset_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3442
reset_clock_tree_optimization_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3444
reset_clock_tree_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3447
reset_clock_tree_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3454
reset_concurrent_clock_and_data_strategy . . . . . . . . . . . . . . . . . . . . . . . . . 3457
reset_cts_batch_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3458
reset_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3460
reset_fast_pba_analysis_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3462
reset_fp_clock_plan_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3464
reset_instance_based_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3466
reset_inter_clock_delay_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3468
reset_latency_adjustment_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3471
reset_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3472
reset_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3474
reset_reference_cell_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3478
reset_split_clock_gates_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3479
reset_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3480
reset_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3482
Chapter 1: Contents
Contents
xli
1-xli
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
reset_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3484
resize_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3486
resize_polygon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3491
restore_design_settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3496
restore_spg_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3498
revert_cell_sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3500
rotate_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3502
route_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3506
route_auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3508
route_detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3510
route_differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3512
route_eco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3514
route_flip_chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3517
route_fp_proto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3520
route_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3522
route_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3524
route_htree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3527
route_mesh_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3531
route_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3534
route_rc_reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3542
route_rdl_differential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3544
route_rdl_flip_chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3547
route_search_repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3551
route_spreadwires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3554
route_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3556
route_widen_wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3557
route_zrt_auto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3559
route_zrt_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3562
route_zrt_detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3563
route_zrt_eco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3566
route_zrt_global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3569
route_zrt_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3572
route_zrt_track . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3576
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Version L-2016.03
rp_group_inclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3578
rp_group_instantiations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3580
rp_group_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3582
run_distributed_tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3585
run_parallel_jobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3587
run_signoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3593
save_design_settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3597
save_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3599
save_qtm_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3603
save_upf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3605
select_block_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3607
select_mim_master_instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3610
send_flow_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3612
set_active_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3615
set_ahfs_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3617
set_always_on_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3621
set_always_on_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3623
set_annotated_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3625
set_annotated_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3629
set_annotated_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3633
set_aocvm_coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3636
set_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3638
set_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3640
set_auto_disable_drc_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3642
set_banking_guidance_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3645
set_budgeted_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3651
set_buffer_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3653
set_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3655
set_cell_degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3657
set_cell_internal_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3659
set_cell_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3662
set_cell_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3664
set_cell_row_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3666
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Contents
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1-xliii
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
set_cell_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3668
set_cell_vt_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3670
set_check_library_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3672
set_checkpoint_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3688
set_child_terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3691
set_clock_cell_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3695
set_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3697
set_clock_gating_registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3701
set_clock_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3704
set_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3708
set_clock_sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3712
set_clock_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715
set_clock_tree_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3718
set_clock_tree_optimization_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3727
set_clock_tree_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3733
set_clock_tree_references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3743
set_clock_uncertainty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3746
set_combinational_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3751
set_command_option_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3753
set_concurrent_clock_and_data_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . 3756
set_congestion_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3760
set_connection_class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3763
set_context_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3766
set_cost_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3768
set_critical_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3770
set_cts_batch_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3772
set_cts_scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3774
set_current_command_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3776
set_data_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3778
set_default_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3781
set_default_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3784
set_default_fanout_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3788
set_default_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3790
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Version L-2016.03
set_default_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3792
set_default_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3794
set_delay_calculation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3796
set_delay_estimation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3799
set_design_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3803
set_die_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3809
set_direct_power_rail_tie . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3810
set_disable_clock_gating_check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3812
set_disable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3814
set_displacement_analysis_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3817
set_distributed_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3819
set_domain_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3823
set_dont_touch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3825
set_dont_touch_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3828
set_dont_touch_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3831
set_dont_use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3832
set_dp_int_round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3834
set_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3838
set_driving_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3841
set_droute_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3846
set_em_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3848
set_equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3852
set_error_view_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3854
set_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3856
set_false_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3863
set_fanout_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3869
set_fast_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3871
set_fast_pba_analysis_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3873
set_fix_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3877
set_fix_hold_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3879
set_fix_multiple_port_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3882
set_flip_chip_bump_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3885
set_flip_chip_cell_site . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3887
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Tool Commands
Commands
L-2016.03
Version L-2016.03
set_flip_chip_driver_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3889
set_flip_chip_driver_island . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3892
set_flip_chip_driver_ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3896
set_flip_chip_driver_strip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3900
set_flip_chip_grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3903
set_flip_chip_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3905
set_fp_base_gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3909
set_fp_black_boxes_estimated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3911
set_fp_black_boxes_unestimated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3912
set_fp_block_ring_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3913
set_fp_clock_plan_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3917
set_fp_flow_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3920
set_fp_macro_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3923
set_fp_macro_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3926
set_fp_pin_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3930
set_fp_placement_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3947
set_fp_power_pad_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3954
set_fp_rail_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3956
set_fp_rail_extraction_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3962
set_fp_rail_region_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3964
set_fp_rail_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3969
set_fp_rail_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3982
set_fp_relative_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3994
set_fp_shaping_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3997
set_fp_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4001
set_fp_trace_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4003
set_fp_voltage_area_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4005
set_groute_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4009
set_gui_stroke_binding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4011
set_gui_stroke_preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4016
set_hierarchy_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4019
set_host_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4021
set_ideal_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4028
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set_ideal_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4031
set_ideal_network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4033
set_ideal_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4036
set_ignore_cell_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4039
set_ignored_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4041
set_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4044
set_input_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4049
set_instance_based_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4052
set_inter_clock_delay_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4054
set_inter_io_ring_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4057
set_isolate_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4059
set_isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4062
set_isolation_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4070
set_isolation_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4072
set_keepout_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4075
set_latch_loop_breakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4079
set_latency_adjustment_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4081
set_left_right_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4083
set_level_shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4085
set_level_shifter_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4091
set_level_shifter_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094
set_level_shifter_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4096
set_lib_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4098
set_lib_cell_spacing_label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4100
set_link_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4103
set_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4106
set_local_link_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4110
set_logic_dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4112
set_logic_one . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4114
set_logic_zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4116
set_macro_cell_bound_spot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4118
set_matching_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4120
set_max_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4122
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
set_max_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4124
set_max_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4127
set_max_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4134
set_max_net_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4136
set_max_time_borrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4138
set_max_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4140
set_mcmm_job_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4143
set_message_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4146
set_min_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4148
set_min_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4150
set_min_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4156
set_min_pulse_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4158
set_minimum_budgeted_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4160
set_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4162
set_mpc_macro_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4164
set_mpc_macro_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4168
set_mpc_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4173
set_mpc_pnet_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4179
set_mpc_port_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4182
set_mpc_rectilinear_outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4186
set_mpc_ring_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4188
set_mtcmos_pna_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4191
set_multi_vth_constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4195
set_multicycle_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4199
set_multisource_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4207
set_mw_lib_reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4209
set_mw_technology_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4211
set_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4213
set_net_aggressors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4215
set_net_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4217
set_net_routing_layer_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4219
set_net_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4223
set_net_search_pattern_delay_estimation_options . . . . . . . . . . . . . . . . . . . . 4226
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set_net_search_pattern_priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4228
set_noise_immunity_curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4230
set_noise_lib_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4233
set_noise_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4235
set_object_boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4237
set_object_fixed_edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4240
set_object_shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4242
set_object_snap_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4247
set_opcond_inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4250
set_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4253
set_opposite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4258
set_optimization_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4260
set_optimize_dft_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4262
set_optimize_pre_cts_power_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4264
set_output_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4267
set_pad_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4273
set_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4278
set_partial_on_translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4280
set_partition_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4282
set_path_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4286
set_pg_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4291
set_physical_signoff_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4294
set_physopt_cpulimit_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4298
set_pi_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4302
set_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4305
set_pin_name_synonym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4307
set_pin_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4309
set_place_opt_cts_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4315
set_place_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4317
set_pnet_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4319
set_port_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4326
set_port_fanout_number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4332
set_port_location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4334
Chapter 1: Contents
Contents
xlix
1-xlix
IC
IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
set_power_clock_scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4336
set_power_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4339
set_power_net_to_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4342
set_power_plan_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4344
set_power_ring_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4350
set_power_switch_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4355
set_power_switch_place_pattern_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . 4357
set_prefer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4360
set_preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4362
set_preroute_advanced_via_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4364
set_preroute_drc_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4369
set_preroute_focal_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4374
set_preroute_special_rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4376
set_primetime_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4387
set_propagated_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4390
set_qtm_global_parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4392
set_qtm_port_drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4395
set_qtm_port_load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4398
set_qtm_technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4400
set_rail_integrity_layout_check_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4404
set_rail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4425
set_read_stream_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4440
set_reference_cell_routing_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4446
set_register_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4448
set_related_supply_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4452
set_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4454
set_retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4456
set_retention_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4460
set_retention_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4462
set_route_flip_chip_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4465
set_route_mode_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4469
set_route_opt_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4470
set_route_opt_zrt_crosstalk_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4474
Contents
l
IC Compiler™ Tool Commands
Version L-2016.03
set_route_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4480
set_route_rdl_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4485
set_route_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4489
set_route_zrt_common_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4491
set_route_zrt_detail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4514
set_route_zrt_global_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4531
set_route_zrt_track_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4536
set_row_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4538
set_rp_group_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4540
set_scaling_lib_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4548
set_scenario_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4550
set_scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4554
set_separate_process_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4556
set_si_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4558
set_size_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4561
set_skew_group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4563
set_spacing_label_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4565
set_split_clock_gates_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4567
set_starrcxt_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4569
set_steady_state_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4572
set_stream_layer_map_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4574
set_switched_net_state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4578
set_switching_activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4580
set_synlib_dont_get_license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4586
set_target_library_subset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4588
set_timing_derate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4592
set_timing_ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4597
set_tlu_plus_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4600
set_top_implementation_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4603
set_total_power_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4609
set_true_delay_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4611
set_unconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4614
set_undoable_attribute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4616
Chapter 1: Contents
Contents
1-lili
IC
IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
set_ungroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4618
set_units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4620
set_user_grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4622
set_via_array_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4625
set_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4627
set_voltage_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4630
set_vt_filler_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4632
set_write_stream_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4634
set_xtalk_route_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4648
set_zero_interconnect_delay_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4650
set_zrt_net_properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4652
sh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4654
shape_fp_blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4656
shell_is_in_upf_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4660
signoff_autofix_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4661
signoff_calculate_hier_antenna_property . . . . . . . . . . . . . . . . . . . . . . . . . . . 4670
signoff_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4674
signoff_metal_fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4684
signoff_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4701
size_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4707
sizeof_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710
skew_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4712
slot_wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4721
snap_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4727
sort_collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4729
sort_fp_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4731
source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4733
split_clock_gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4735
split_clock_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4737
split_multisource_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4739
split_mw_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4748
split_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4751
split_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4754
Contents
lii
IC Compiler™ Tool Commands
Version L-2016.03
split_rdl_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4757
split_register_bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4763
split_zrt_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4765
spread_spare_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4769
spread_zrt_wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4773
sub_instances_of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4776
suppress_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4779
swap_cell_locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4781
synthesize_fp_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4784
synthesize_fp_rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4794
transform_coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4799
trim_fill_eco . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4802
unalias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4805
uncommit_fp_soft_macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4806
uncompress_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4810
undefine_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4812
undo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4814
undo_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4816
undo_mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4818
ungroup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4820
uniquify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4825
uniquify_fp_mw_cel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4828
unset_hierarchy_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4831
unset_power_guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4832
unsetenv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4834
unsuppress_message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4836
update_bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4838
update_clock_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4840
update_dc_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4841
update_flip_chip_pin_locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4843
update_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4845
update_lib_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4848
update_lib_pg_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4850
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update_lib_pin_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4853
update_lib_voltage_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4855
update_physical_bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4857
update_power_plan_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4860
update_routing_corridor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4863
update_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4866
update_voltage_area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4868
upf_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4871
verify_lvs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4873
verify_pg_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4878
verify_rail_integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4881
verify_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4883
verify_zrt_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4886
virtual_ipo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4890
which . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4892
while . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4894
widen_zrt_wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4896
win_select_objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4899
win_set_filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4902
win_set_select_class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4904
window_stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4905
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4908
write_aif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4909
write_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4914
write_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4916
write_design_lib_paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4921
write_design_settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4923
write_environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4926
write_flip_chip_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4929
write_floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4931
write_lib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4938
write_lib_specification_model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4940
write_link_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4942
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write_mw_lib_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4944
write_parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4947
write_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4951
write_physical_script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4953
write_pin_pad_physical_constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4955
write_power_plan_regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4958
write_rail_integrity_strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4960
write_rail_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4962
write_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4964
write_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4966
write_saif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4969
write_sanity_check_point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4972
write_script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4974
write_sdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4978
write_sdf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4982
write_stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4984
write_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4986
write_via_region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4992
Chapter 1: Contents
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add_buffer_on_route
Adds buffers along the route of the specified nets.
SYNTAX
add_buffer_on_route
[-net_prefix prefix]
[-cell_prefix prefix]
[-inverter_pair]
[-location {coordinate_list}]
[-user_specified_buffers {user_specified_buffer_list}]
[-repeater_distance length
| -repeater_distance_length_ratio length_ratio
[-first_distance length
| -first_distance_length_ratio length_ratio]
[-scaled_by_layer {layer_scale_list}]
[-scaled_by_width]
[-max_distance_for_legalized_location length]
[-no_legalize]
[-no_eco_route]
[-only_global_routed_nets]
[-respect_blockages]
[-punch_port]
[-verbose]
list_of_nets
[buffer_lib_cell]
Data Types
prefix
coordinate_list
user_specified_buffer_list
length
layer_scale_list
list_of_nets
buffer_lib_cell
string
list
list
float
list
list
collection
ARGUMENTS
-net_prefix prefix
Specifies the prefix to be used for new nets that are created when buffers are inserted in
the netlist. The prefix must not contain embedded hierarchical separators.
By default, the command uses eco_net as the prefix.
Chapter 1:
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-cell_prefix prefix
Specifies the prefix to be used for new buffers that are inserted in the netlist. The prefix
must not contain embedded hierarchical separators.
By default, the command uses eco_cell as the prefix. This option cannot be used with
-user_specified_buffers.
-inverter_pair
Indicates that a pair of inverting library cells has to be inserted instead of a single
noninverting library cell. If you specify this option, you need to supply a library cell with
an inverting output for the -buffer_lib_cell option. You can use this option when the
library cell (buffer) specified has both inverting and noninverting outputs.
-location {coordinate_list}
Specifies the center point coordinates for the locations of the buffer or inverter pair cells,
in the format {x1 y1 layer1 x2 y2 layer2 ...}. You must specify one location per buffer
when inserting buffers. You must specify two locations per inverter pair when inserting
inverter pairs. These locations can be any valid {x_coordinate y_coordinate layer} triplet
that is inside the placement region of the core area and is relative to the chip origin.
These locations must be within a region from the route. The region radius is specified by
-max_distance_for_legalized_location. Specify the coordinates in units of microns. More
than one routing shape can overlap the specified location. The layer is used to decide
which shape to pick.
•
If you specify a valid value for the layer, the location is matched on a routing shape
on the specified layer.
•
If you specify 0 as the layer value, the tool tries to find the nearest routing shape. If
there are two routing shapes in different metal layers that are the same distance from
the specified location, the tool errors out.
For best results, specify the explicit layer instead of 0.
-user_specified_buffers {user_specified_buffer_list}
Specifies the center point coordinates and layer for the locations of the buffer or inverter
pair cells, as well as their names and library cells, in format of {name1 lib_cell1 x1 y1
layer1 name2 lib_cell2 x2 y2 layer2 ...}. You must specify one five-tuple per buffer when
inserting buffers or two five-tuples per inverter pair when inserting inverter pairs.
They cells must be either all inverters or all buffers. The names should be valid name
strings for the buffers or inverters. The library cells should be name strings or collections.
The locations can be any valid set of coordinates with layers that are inside the
placement region of the core area. These locations must be within the maximum
distance specified, by using -max_distance_for_legalized_location option, from the
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route the buffers or inverters are being added to. Specify the coordinates in units of
microns.
More than one routing shape can overlap the specified location. The layer is used to
decide which shape to pick.
•
If you specify a valid value for the layer, the location is matched on a routing shape
on the specified layer.
•
If you specify 0 as the layer value, the tool tries to find the nearest routing shape. If
there are two routing shapes in different metal layers that are the same distance from
the specified location, the tool errors out.
For best results, specify the explicit layer instead of 0.
-repeater_distance length
Specifies the distance in microns between each buffer to be introduced along the route.
This option always works on the entire physical route underlying the specified nets.
-repeater_distance_length_ratio length_ratio
Specifies the distance between each buffer that is introduced along the route as a ratio
of the total route length. The value range is between 0.0 and 1.0
This option always works on the entire physical route underlying the specified nets.
Only one of the -location, -user_specified_buffers, -repeater_distance, or
-repeater_distance_length_ratio options should be specified.
-first_distance length
Specifies the distance in microns between the driver pin and the first buffer introduced
along the route.
You can use this option only if you also use the -repeater_distance or
-repeater_distance_length_ratio option.
-first_distance_length_ratio length_ratio
Specifies the distance between the driver pin and the first buffer introduced along the
route as a ratio of the total route length. The value range is between 0.0 and 1.0
You can use this option only if you also use the -repeater_distance_length_ratio
option.
-scaled_by_layer {layer_scale_list}
Scales the distance between buffers by the scaling factor specified for the layer. Specify
the scaling factors by using the following format:
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{{layer1 factor1} {layer2 factor2} ...}
The command scales the distance on each layer with the following formula:
D = d*L_M
d:the repeater distance
D:the repeater scaled distance
L_M:layer scaling factor on metal M
Layers that are not in the list use a default factor of 1.
You can use this option only if you also use the -repeater_distance option.
-scaled_by_width
Scales the distance between buffers by the ratio of the default width for the layer and the
actual route width.
The command scales the distance on each layer with the following formula:
D = d*w_M/w_R
d:the repeater distance
D:the repeater scaled distance
w_M:default route width on metal M
w_R:actual route width
By default, the scaling factor is 1 (w_M=w_R).
You can use this option only if you also use the -repeater_distance option.
-max_distance_for_legalized_location length
Specifies the maximum horizontal or vertical distance in microns between the location
found by route tracing and the legalized cell bounding box.
The default for this option is five times the height of reference cell. For example, suppose
the value for this option 100 microns and the location found by route tracing is (x,y). The
legal cell bounding box is then searched within the bounding box with coordinates of
(x-100, y-100) and (x+100, y+100).
If the tool fails to legalize the buffer within the maximum distance specified, the buffer is
not added.
This option and the -no_legalize option are mutually exclusive; you can specify only
one.
add_buffer_on_route
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-no_legalize
Disables legalization of the inserted buffer cells.
This option and the -max_distance_for_legalized_location option are mutually
exclusive; you can specify only one.
-no_eco_route
Disables rerouting of the nets.
-only_global_routed_nets
Enable inserting buffers on global routed nets. When this option is on, the specified nets
must be only global routed without track assigned or detail routed.
-respect_blockages
Indicate that no buffer should be added inside (in layout) a placement blockage , soft
macro or hard macro. But buffers could be added in reserved placement area.
-punch_port
When this option is specified, a buffer can be added on a route segment which has a
topology that is different from the logical hierarchy connection. In such a situation, the
tool punches hierarchical ports to connect the loads of such a buffer.
-verbose
Shows verbose messages.
list_of_nets
Specifies the nets to be buffered. If -user_specified_buffers or -location is specified,
this option must be only one 1 net.
buffer_lib_cell
Specifies the library cell object to be used as a buffer. In this case, the object is either a
named library cell or a library cell collection.
This option cannot be used with -user_specified_buffers. This option must be
specified as well, if -location, -repeater_distance or -repeater_distance_length_ratio
is specified.
DESCRIPTION
This command adds buffers along the route of the specified nets. By default, the new buffers
are placed and legalized and the original net and the newly created nets connecting the
buffers and the original loads are rerouted. To disable legalization of the inserted buffers,
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use the -no_legalize option. If you disable legalization, the original net and the newly
created nets are not rerouted.
The new buffers are placed close to the route of the input net. The new nets follow the
original route as much as possible.
A library cell with a single input and multiple outputs is a buffer, as long as each output has
the same or inverted logic function as the input.
By default, each newly added buffer has a name beginning with the prefix eco_cell and
ending with a numeric suffix. To override the automatic name generation by the tool, use the
-net_prefix and -cell_prefix options.
The add_buffer_on_route command uses the following basic rules to check its arguments
for validity:
•
The net cannot be either a PG net or a tie net.
•
The net must be completely routed (no opens).
•
The library cell cannot be sequential.
•
The library cell must be a buffer, as previously defined.
•
The library cell must have an inverting output if the -inverter_pair option is enabled. The
command uses the first inverting output to insert two cells and to preserve the logic of the
path.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following examples show the usage of command options. The output of the command
is not shown.
The following example shows the command usage to add buffers on net1 using the lib/BUF
library cell. The repeater distance is 100 and the first distance is 80.
prompt> add_buffer_on_route -repeater_distance 100 \
-first_distance 80 net1 lib/BUF
The following example shows the command usage to add buffers on net1 using the lib/BUF
library cell. One location is specified.
prompt> add_buffer_on_route -location {100 200 0} net1 lib/BUF
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The following example shows the command usage to add buffers on net1 by
-user_specifeid_buffers
prompt> add_buffer_on_route n1 -user_specified_buffers {eco1 bufbd2 70 10
0 eco2 bufbd4 140 10 0}
The following example shows the command usage to add buffers on net1 using the lib/BUF
library cell without legalizing them. A repeater distance of 100 is used.
prompt> add_buffer_on_route -no_legalize -repeater_distance 100 \
net1 lib/BUF
The following example shows the command usage to add buffers on net1 using the lib/BUF
library cell without legalizing them. Repeater distance of 40% total route length and first
distance of 20% total route length is also specified.
prompt> add_buffer_on_route -no_legalize \
-repeater_distance_length_ratio 0.4 \
-first_distance_length_ratio 0.2 \
net1 lib/BUF
The following example shows the command usage to add buffers on net1 using the lib/BUF
library cell without legalizing them. A repeater distance of 100 is used. The distance scaling
factor for METAL2 is 0.9 and the distance scaling factor for METAL3 is 0.8. The repeat
distance is scaled by route width on each layer.
prompt> add_buffer_on_route -no_legalize -repeater_distance 100 \
-scaled_by_width -scaled_by_layer { {METAL2 0.9} {METAL3 0.8} } \
net1 lib/BUF
SEE ALSO
legalize_placement(2)
remove_buffer(2)
Chapter 1:
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add_clock_drivers
Adds multiple levels of drivers into your design and connects them together. These drivers
are suitable for driving a clock mesh.
SYNTAX
status add_clock_drivers
-load net_or_pins -prefix prefix_string
| -remove_display
[-configuration list_of_groups
| -external_configuration config_file]
[-driver_type library_cell]
[-avoid cells]
[-max_displacement distance]
[-offset {x_distance y_distance}]
[-use_common_bbox]
[-check_only]
[-verbose]
Data Types
net_or_pins
prefix_string
list_of_groups
config_file
library_cell
cells
x_distance
y_distance
collection
string
list
string
string
collection
float
float
ARGUMENTS
-load net_or_pins
Specifies the overall driver pin and the set of overall load pins. When you specify a net,
it must have one driver pin and typically has many input (load) pins.
If you only want to work on a subset of the pins of a net, use the driving pin of the net and
the pins that you want to process as the value of this option.
This option and the -remove_display option are mutually exclusive. You must specify
one of them.
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-prefix prefix_string
Specifies the prefix for all newly created nets and cells. All newly created nets and cells
also have a suffix that denotes their level and unique ID. You should not use this prefix
for any other nets or cells in the design. This is a global option: it impacts all created
drivers.
There is no default prefix. If you specify the -load option, you must also specify this
option.
-remove_display
Removes the previously annotated tentative mesh drivers from the GUI. This option
works only when the GUI is open.
-configuration list_of_groups
Defines groups of drivers to be added.
This option accepts a list of any length. Each element in the list defines a group of drivers
to be added, and each element must itself be a Tcl list. For details about the
configuration syntax, see the CONFIGURATION STRUCTURE section below.
This option and the -external_configuration option are mutually exclusive; you can
specify only one.
-external_configuration config_file
Specifies the configuration in a Tcl text file.
Each line of text in the file is considered a Tcl command, and must begin with the
add_clock_driver_group command name. The syntax and semantics of this file is
identical to the -configuration option. For details about the configuration syntax, see the
CONFIGURATION STRUCTURE section below.
(Note that the command add_clock_drivers_group is not available unless processed
through the -external_configuration option.)
This option and the -configuration option are mutually exclusive; you can specify only
one.
-driver_type library_cell
Specifies the default driver cell to use. The specified driver cell must have exactly one
input and one output.
The configuration can override the default driver cell for a specific group of drivers. If you
do not specify this option, each group in the configuration must explicitly specify a driver
type.
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-avoid cells
Prevents drivers from being inserted at the top of a large macro block. You can specify
any number of cells as a list or a collection.
-max_displacement distance
Specifies the maximum allowed displacement in the x- and y-directions from the position
specified in the configuration. The distance value is in library units.
When the tool inserts a driver, it starts at the position specified in the configuration and
tries to find an unblocked, legal location within the distance specified by this option. If the
tool cannot find an unblocked location within this distance, it does not insert that driver.
-offset {x_distance y_distance}
Specifies the offset to be added to each driver location after positioning the driver, but
before searching for an unblocked, legal location. The distance values are in library
units.
You can use this option to place drivers on a grid so that they are in the center of each
horizontal wire or in the middle of each gap in a mesh.
If you use both this option and the -offset option for a specific group in the configuration,
the two offsets are added together.
-use_common_bbox
Specifies a single bounding box of load pins for all groups of drivers. Normally each
group of drivers in the configuration uses the geometry of the group below as the
bounding box for placement. The higher the hierarchy level is, the smaller the bounding
box area becomes. For some layouts, it is more convenient to have one common
bounding box. You should use this option for H-tree layouts.
-check_only
Displays a short report of the number of drivers to be created at each level and their
fanouts (without creating drivers). The report is done before the legalization of cell
locations, so the values are approximate. Use this option to test and tune your
configuration without actually inserting drivers.
When the GUI is open, this option displays the locations of tentative mesh drivers in the
GUI. Use the -remove_display option to undo the display.
-verbose
Displays additional information about the way drivers are being created and positioned.
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DESCRIPTION
If you need to drive a large load of many pins with minimum skew, you generally need to
create multiple levels of drivers. You can either manually create such a hierarchy of drivers
by using insert_buffer repeatedly, or let command like compile_clock_tree automatically
create them. However, if the load pins are uniformly distributed, add_clock_drivers
provides some advantages. This command is especially suitable for driving a large clock
mesh net.
This command accepts one net, usually a high-fanout net. The net must have exactly one
driver pin. When the command is done, the clock net is still connected to its original driver
pin, but the original load pins are connected to one or more new nets.
If you use the command to drive a clock mesh (as opposed to a collection of unconnected
input pins), you must use the -short_outputs option at the lowest level. In a mesh, all load
pins are connected by wire straps. To design a mesh, you must add the mesh straps before
running this command. If you do not use -short_outputs, the loads are connected to the
newly created drivers, not to each other. Running this command without this option is
appropriate for generating conventional clock tree circuitry where the driver outputs are not
shorted together.
The specified command options apply globally to the entire hierarchy of drivers. The
configuration lets you specify options in more detail. The two sets of options complement
each other. The global options specify the root and loads of the driver tree to be created and
affect all drivers in the tree, while the configuration specifies how small a group of drivers or
individual drivers should be created.
You must specify a prefix for naming new nets and cells created by this command. The
prefix must not be used by other nets or cells in the design. The names of the newly created
cells have the following format:
<prefix>_L<level_number>_<group_number>_<column>_<row>
For example,
clka_L1_1_2_3
driv_L4_3_7_2
Using a unique prefix enables you to perform operations such as legalizing, routing, or
removing the nets and cells that are created by this command.
You should use a short prefix because the command creates many cells and nets.
When nets are created, they share the same name as the cell that drives them. However, if
you are driving a mesh, you must specify the name of the large mesh net separately.
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You can run this command multiple times with the -check_only option to verify that your
circuitry has valid inputs and a reasonable structure with legal fanouts and balancing before
running the command to insert the drivers and to connect the nets.
You can use this command to insert the cells that drive a mesh net (the mesh drivers) and
then use a separate command to create the cells that drive the mesh drivers (the premesh
tree). For example, use the compile_premesh_tree command after the
add_clock_drivers command inserts the mesh drivers. This two-step approach provides
the advantage of analyzing the mesh driver circuitry and mesh straps before adding the
premesh tree. If the mesh drivers and straps do not meet performance requirement, they
should be redesigned. A premesh tree cannot improve a poorly designed mesh or set of
premesh drivers.
Configuration Structure
The configuration is comprised of one or more driver group specifications.
Each group of drivers has a "level" and is specified by a list of options. The options all have
the form -option_name value, just like a Tcl command. The order of the group
specifications is not important. For example, you can specify the level 2 groupings before or
after the level 1 groupings. Also, the order of the options with each grouping is not important.
For example, you can specify the -boxes option before or after the -driver_type option.
More importantly, you can specify multiple groupings at a single level. For example, you
could have three groupings at level 5 with different geometries to fit unbalanced loads or
avoid obstacles. Each grouping of drivers must be assigned to a level in the driver hierarchy.
Level 0 is the original drive pin or port specified with the -load command option. You must
not try to define any grouping at level 0. The input pins on the first level (level 1) are
connected to the original driving net. The outputs of level 1 drivers are connected to the input
pins on level 2, and so forth. Drivers in the highest numbered level drive the original load
pins. At least one grouping must appear in the configuration, so there must be at least one
grouping at level 1.
The clock tree is built from the bottom (the load pins) up. To add drivers, the tool must know
what the drivers should drive and where to place them. The level number determines the
default set of pins that should be driven. For each level, the default driven pins are all the
pins on the level below, and the default driven region for each group is the bounding box of
the driven pins. You can change the set of load pins for a group on the lowest level by
specifying an explicit -drives option.
The default geometric boundary for placing the new drivers is the same as the driven pin
region. You can override this boundary for a group by using the -boundary option. You
would typically override these specifications only when the design has obstacles or other
complex geometry. If you want all the groups in the configuration to use the same boundary,
use the -use_common_bbox option at the command level.
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When you specify geometries, note that you specify a point as a Tcl list of two distances and
a rectangle as a Tcl list of two points.
An example of a simple configuration is
{
{ -level 1 -boxes {3 2} }
{ -level 2 -boxes {6 4} }
}
This creates two groups of drivers. The first group, on level 1, comprises six drivers (three
columns and two rows) connected to the top-level driver.
The second group, on level 2, comprises 24 drivers, which are driven by the six drivers on
level 1; thus, each of the level 1 drivers has a fanout of 4. The level 2 drivers are arrayed in
six columns and four rows. They are spread uniformly over the region defined by the load
pins specified in the -load command option, because these load pins are implicitly on level
3.
By default, each driver drives those pins that are closest to it.
The configuration file provides various options to help create drivers suitable for a variety of
common situations.
For each driver group, you can specify the following configuration options:
-level level_number
[-boxes {columns rows}
| -auto {columns rows}
| -interior {columns rows}
| -grid {columns rows}
| -single_driver point
| -coincident collection
| -replicate]
[-drives rectangle | -load collection_of_pins]
[-boundary rectangle]
[-driver_type lib_cell]
[-offset {x_offset y_offset}]
[-short_outputs
[-output_net_name string [-transfer_wires_from net]]]
-level level_number
Specifies where in the hierarchy to connect the group of drivers. You must specify this option
for each grouping. Level 1 is the highest level. The input pins of level 1 drivers are driven by
the overall driver pin and are therefore connected directly to the overall clock net. Level 2
drivers with are driven by level 1 drivers. The driver groupings with the highest level number
drive the loads specified by the -load command option.
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There must not be any gaps in the level numbers. Groups must exist for each level from
level 1 to your highest level number. If there is a gap, the configuration is rejected and the
command returns an error.
You can have any number of groups with the same level. This is useful if you have complex
geometry and want to specify particular drivers for particular parts of your design. Note that
it would be very rare, but not illegal, to have a level number more than about 10, because
each level typically has a fanout of approximately 4 to 8, and 10 levels could drive at least
262144 loads.
-boxes {columns rows}
Specifies an array of drivers that are spread across the rectangle that is the boundary of the
group. When you use this option, the drivers are placed at the centers of the boxes that
define the loads they serve.
For example, to place six drivers at {50 50}, {50 150}, {150 50}, {150 150}, {250 50}, and {250
150}, specify the following options:
-level 2 -boundary {{0 0} {300 200}} -boxes {3 2}
To picture the result, draw four vertical and three horizontal lines that form six boxes. The
drivers are placed at the center of each box.
To specify a column of drivers, set the columns argument to 1 and specify the number of
drivers that you want in the rows argument. To specify a row of drivers, set the rows
argument to 1 and specify the number of drivers that you want in the columns argument. To
specify a single driver, set the option argument {1 1}.
-auto {columns rows}
Specifies an array of drivers that are spread across the rectangle that is the boundary of the
group. When you use this option, the tool automatically adjusts the driver positions to even
out the distance from a driver to its loads.
To picture the result, represent the loads by drawing a pattern of 6 dots wide by 4 dots tall,
which are spaced 100 units apart horizontally and vertically, starting at {0 0} and having the
upper-right dot at {500 300}. The -auto {3 2} option adds six drivers centered in the middle
of symmetrical clusters of 4 dots. The drivers are located at {50 50}, {250 50}, {450 50}, {50
250}, {250 250}, and {450 250}. Each driver drives four loads, with an equal distance to each
of them.
To specify a column of drivers, set the columns argument to 1 and specify the number of
drivers that you want in the rows argument. To specify a row of drivers, set the rows
argument to 1 and specify the number of drivers that you want in the columns argument. To
specify a single driver, set the option argument {1 1}.
-grid {columns rows}
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Specifies an array of drivers that are spread on the edges and interior of the rectangle that
is the boundary of the group. When you use this option, the drivers are placed on the
perimeter of the boundary rectangle.
For example, to place six drivers at {0 0}, {150 0}, {300 0}, {0 200}, {150 200}, and {300 200},
specify the following options:
-boundary { {0 0} {300 200}}
-grid {3 2}
To picture the result, draw three vertical and two horizontal lines that form two boxes. Each
box is 150 units wide by 200 units tall. The drivers are placed at the intersections of the
horizontal and vertical lines.
To specify a column of drivers, set the columns argument to 1 and specify the number of
drivers that you want in the rows argument. To specify a row of drivers, set the rows
argument to 1 and specify the number of drivers that you want in the columns argument. To
specify a single driver, set the option argument {1 1}.
This option provides more detailed manual specification than the -boxes or -auto options.
The -grid option might be more convenient than the -boxes option for placing drivers
directly under specific wire segments in the clock wiring mesh. This would be useful for the
lowest level that drives the externally specified load.
-interior {columns rows}
Specifies a regular array of drivers that are spread on the interior of the rectangle that is the
boundary of the group. When you use this option, the drivers are placed only in the interior
and not along the edges.
For example, to place two drivers at {100 100} and {200 100}, enter the following options:
-boundary {{0 0} {300 200}}
-interior {2 1}
To picture the result, draw four vertical lines and three horizontal lines that form six boxes.
Each box is 100 units wide by 100 units tall. The two drivers are placed at the four-way
intersections of the horizontal and vertical lines in the middle.
To specify a column of drivers, set the columns argument to 1 and specify the number of
drivers that you want in the rows argument. To specify a row of drivers, set the rows
argument to 1 and specify the number of drivers that you want in the columns argument. To
specify a single driver, set the option argument {1 1}.
The -interior option can be more convenient than the -grid option for placing drivers directly
under specific wire intersections in the clock wiring mesh.
-single_driver point
Inserts a single driver at the specified point.
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-coincident collection
Specifies that a new set of drivers should be allocated on a one-to-one basis with members
of the specified collection. Typically, this is a collection of vias that are located at the
intersections of the clock mesh. If the clock mesh has already been allocated, you can get
the vias with the following command:
set vias [get_vias -of clock_net]
To specify this configuration to the add_clock_drivers command, enter
add_clock_drivers -load clk \
-driver_type buffd7 -use_common_bbox -verbose -prefix ccc \
-config [list \
{-level 1 -boxes {1 1}} \
{-level 2 -boxes {2 2}} \
{-level 3 -boxes {4 4}} \
[list -level 4 -coincident $vias -short_outputs \
-output_net_name clk_mesh]]
-replicate
Specifies that a new set of drivers should be allocated on a one-to-one basis with the drivers
on the level below the current level. Typically, this is used for allocating pairs of inverters.
-drives rectangle
Specifies that the group drives the loads in the specified rectangle.
By default, the group drives the loads in the entire bounding box of the load pins on the level
below.
-load collection_of_pins
Specifies that the group drives the specified load pins.
You can use this configuration option only for groups at the lowest level that drive a subset
of pins specified in the -load command option.
By default, the group drives all load pins on the level below.
-boundary rectangle
Specifies the boundary for the group of drivers.
By default, the boundary is determined by the set of load pins that the group serves.
For example, if you want to drive loads on the left side of your design with drivers located
near the middle of your design, you can use the -drives configuration option to select the
loads and the -boundary configuration option to specify where to put the drivers.
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The -boundary configuration option directly impacts the operation of the -boxes, -grid, and
-auto configuration options.
-driver_type lib_cell
Specifies the driver cell to use for the group of drivers.
By default, the group uses the driver cell specified by the -driver_type command option. If
you do not specify the -driver_type command option, you must specify this option for each
group in the configuration.
-offset {x_distance y_distance}
Specifies the distance, in library units, to shift each driver from the location calculated by the
tool.
The tool calculates a preferred location for each driver in the group. When you use this
option, the tool first shifts each location by the specified horizontal and vertical offset before
searching for an unblocked location.
You can use this configuration option with the -boxes, -single_driver, -replicate, and -grid
configuration options. For example, you can use this configuration option with the -replicate
configuration option to displace the newly created driver a small distance from the inverter
that it drives.
If you specify both the -offset configuration option and the -offset command option, the
drivers are shifted by the sum of the two offsets.
-short_outputs
Specifies that the outputs of all the drivers in this group are connected to a single net. This
option is typically used when the load pins are joined together by a grid of wires in a mesh.
-output_net_name string
Specifies the name of the net driven by the driver group. This option is typically used when
the load pins are joined together by a grid of wires in a mesh and you want to specify the
name of the mesh net.
This option can be used only in conjunction with the -short_outputs configuration option.
-transfer_wires_from from_net
Specifies that all of the wires and vias on the specified net are transferred to the net
specified on the -output_net_name option.
This option enables you to use the following flow:
create_clock_mesh -load clk -net clk -layers {METAL5 METAL4} \
-num_straps {16 16}
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echo Clock mesh wires are created now
add_clock_drivers -load
-config {
{-level 1 -boxes {1
{-level 2 -boxes {2
-output_net_name
}
clk -driver_type buffd7 -prefix ccc \
1}}
2} -short_outputs \
clk_mesh -transfer_wires_from clk}
This sequence creates the wires on the original clock net, clk, and then creates a 2-level
hierarchy of clock drivers. The second level drives the newly created clk_mesh net and all
of the wires and vias that were once on the clk net are now on the clk_mesh net. Note that
you can save the design and exit the tool at the point marked "Clock mesh wires are created
now". Because the wires are attached to the clk net, which is part of the design with a driver
and load, the wires will not be lost during a save and restore cycle.
This option can be used only in conjunction with the -output_net_name configuration
option.
Limitations
The quality of results is primarily determined by your specification. If your grouping provides
too many or two few drivers or puts the drivers in the wrong location, the tree might be
imbalanced or even illegal.
Although you can specify the driver groups and levels in any order, the actual construction
of the clock tree is bottom up. That is, it starts with the load pins and works toward the root
pin. This command does not optimize the overall geometry.
The placement legalization process is done after the tree is constructed internally, so the
relationship between the drivers and their loads might not be as symmetric as simple
geometry would suggest.
The presence of large obstructions or irregular geometry can limit the utility of this
command.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example generates a hierarchy of drivers connected to a mesh net. You
should run the legalize_placement command after running the add_clock_drivers
command.
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prompt> add_clock_drivers -load clk1 \
-prefix clkd_ -driver_type buf2 \
-configuration {
{-level 1 -boxes {6 4} -driver_type buff2}
{-level 2 -boxes {3 2} -driver_type buff2 \
-short_outputs -output_net_name clk1mesh}
}
1
Report:
Level
Level
Level
Level
1
0
1
2
3
(overall driver) was port "clk"
had 6 cells, max fanout= 4, min fanout=4
had 24 cells, max fanout= 6, min fanout=4
(overall load) had 100 input pins
The following example generates a hierarchy of drivers connected to a large number of input
pins, but only reports the result. In this case, two columns of drivers comprise level 1 and
one column comprises level 2.
The grouping list is created with the Tcl list command, which allows the use of Tcl variables
and other tool functions.
prompt> set loads [get_pins "fflop*/CP"]
prompt> set l2_bound_box [get_bounding_box [get_pins clk2*/CP]
prompt> set config [ list
{ -level 1 -grid { 2 1 } -boundary { 20 400 20 600} }
[list -level 2 -grid { 6 1 } -boundary $l2_bound_box ]
{ -level 2 -boxes { 3 1 } }
]
prompt> add_clock_drivers -load [get_net clkd] -prefix clkd_ \
-driver_type buf2 -check_only -configuration $config
Report:
Level
Level
Level
Level
0
1
2
3
(overall driver) was port "inv2/Y"
had 2 cells, max fanout= 5, min fanout=4
had 9 cells, max fanout= 5, min fanout=3
(overall load) had 34 input pins
1
SEE ALSO
create_clock_mesh(2)
route_mesh_net(2)
compile_premesh_tree(2)
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analyze_subcircuit(2)
compile_clock_tree(2)
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add_distributed_hosts
Adds one or more distributed hosts for distributed jobs.
SYNTAX
status add_distributed_hosts
[-target PrimeTime | StarRCXT | all]
[-32bit]
[-enable_ssh]
-farm lsf | grd | generic | now
[-setup_path setup_path]
[-num_of_hosts count]
[-options string]
[-submission_script submission_script]
[work_station_name]
ARGUMENTS
-target PrimeTime | StarRCXT | all
Specifies the target application for this configuration. Valid values are PrimeTime,
StarRCXT, all. Default is all.
-32bit
This switch is currently not supported in IC Compiler.
-enable_ssh
By default, remote processes are run with rsh. Enable this switch will ask IC Compiler
to use ssh to launch remote processes.
-farm lsf | grd | generic | now
This option is used to specify the type of the farm from which the distributed hosts are to
be acquired.
-setup_path path
This option specifies the path to the submission scripts/executables for farms of type lsf/
grd/generic. The path should contain the following scripts/executables.
-farm lsf the setup_path should contain "qsub", "qdel" -farm grd the setup_path should
contain "bsub", "bkill" -farm generic the setup_path should contain "gsub", "gdel"
The -setup_path option is not valid with -farm now
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-num_of_hosts count
The user can specify the number of hosts to use in an lsf, grd, generic, or now compute
environment. The number must be at least 1. If this option is not specified then the
number of hosts is 1.
-options string
This option is used only in conjunction with -farm lsf | grd | generic. It is a list of
arguments to be passed off to the submission_script used for job submission to a lsf, grd
or generic queue.
-submission_script
The user can explicitly specify the script to call when submitting jobs to farm types grd,
lsf or generic using this option. When both the -setup_path and -submission_script
options are used simultaneously, the path and submission script specification are
combined to define the script used when submit jobs to the compute resource being
specified.
The -submission_script option is not valid with -farm now
work_station_name
Specifies a single UNIX machine. This option is used only in conjunction with -farm now.
DESCRIPTION
The options for add_distributed_hosts depend on whether the user has an on-site load
balancing capability and whether they wish to use it or not.
If on-site load balanced facilities are available these should be specified using the -farm lsf,
-farm grd or -farm generic options, depending on the type of resource available.
If no on-site load balancing capabilities are available or there are other compute resources
available that are not under load balancing control, these should be specified using the -farm
now hostname method.
All combinations of resources are concurrently supported by the command, however, each
separate type must be specified independently with a separate invocation of the
add_distributed_hosts command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
In the following example, two hosts are added for a distributed command. The first host,
platinum1, is specified to have 2 hosts and the second, platinum2, is specified to have 4
hosts. The processes on platinum1 will be 64 bit where as the processes on platinum2 will
be 32 bit. Notice that the actual number of processors in platinum1 and platinum2 is
irrelevant but for optimal performance the number or processes allocated should match the
processors in each machine i.e. 2 processors in platinum1 and 4 processors in platinum2.
prompt> add_distributed_hosts -farm now -num_of_hosts 2 platinum1
1
prompt> add_distributed_hosts -farm now -num_of_hosts 4 platinum2 -32bit
1
To use this command where on-site load balancing capabilities (LSF/GRD/GENERIC) are
in place, use options -farm grd, -farm lsf, or -farm generic. In the example below, the
distributed hosts list is populated by defining four 32 bit hosts from an lsf farm, and two 64
bit hosts from a grd farm.
prompt> add_distributed_hosts -farm lsf -setup_path "/bin/lsf/" \
-options { -R "tmp>300" -q} -num_of_hosts slaves 4 -32bit
1
prompt> add_distributed_hosts -farm grd -setup_path "/bin/grd/" \
-options {-cwd -V -r y -P bnormal -l} -num_of_hosts slaves 2
1
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add_drc_error_detail
Adds additional details to an existing error object that is associated with the default error
type class.
SYNTAX
status add_drc_error_detail
-error_view mw_error_view
-drc_error drc_error
-rectangles rectangles | -polygons polygons
[-net net]
[-layer layer]
Data Types
mw_error_view
drc_error
rectangles
polygons
net
layer
list
list
list
list
list
list
or collection of one item
or collection of one item
or collection of one item
or collection of one item
ARGUMENTS
-error_view mw_error_view
Specifies the error view that contains the error record to which the details are added.
You can specify only a single error view; specifying more than one error view causes an
error.
This is a required option.
-drc_error drc_error
Specifies the error object to which to add these details. You can specify a single error
object; specifying more than one error object causes an error.
You can add error details only to existing error objects. To specify the error object, use
the collection returned by the create_drc_error command or the get_drc_errors
command. The specified error object must be associated with the default error type
class. For more information about error type classes, see the man page for the
create_drc_error_type command.
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This is a required option.
-rectangles rectangles
Specifies the rectangle shapes to add to the error object. You can specify one or more
rectangles as a list of rectangles:
{rectangle+}
where each rectangle is specified as a list of four coordinates:
{llx lly urx ury}
which represent the x- and y-coordinates of the lower-left and upper-right corners of the
rectangle. You can also define a rectangle as a list of two points for the lower-left and
upper-right corners, where a point is a list of two coordinates:
{{llx lly} {urx ury}}
The -rectangles and -polygons options are mutually exclusive; you must specify one of
these options.
-polygons polygons
Specifies the polygon shapes to add to the error object. You can specify one or more
polygons as a list of polygons:
{polygon+}
where each polygon is a list of points
{point+}
and each point is a list that contains an x- and y-coordinate:
{x y}
The list of polygons might look like this:
{{{ax1 ay1} {ax2 ay2} ... {axn ayn}} {{bx1 by1} {bx2 by2} ... {bxn byn}}}
The -rectangles and -polygons options are mutually exclusive; you must specify one of
these options.
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-net net
Specifies the net associated with the shapes. You can specify the net by providing a
collection that contains the net or by specifying the net name. You cannot use wildcards
in the net name.
-layer layer
Specifies the layer associated with the shapes. You can specify the layer by using the
layer name from the technology file or by using the get_layers command.
DESCRIPTION
This command adds shapes and associated details to an existing error object that is
associated with the default error type class.
When an error type is created with the create_drc_error_type command, it is associated
with one of the following error type classes: default, open, openlocator, short, and spacing.
An error object is interpreted based on its error type class. Use this command only for
adding details to error objects associated with the default error type class. To add details to
error objects associated with the open error type class, use the
add_open_drc_error_detail command. For the other error type classes, you specify the
details when you create the error object; you cannot add details to an existing error object.
The command returns 1 if successful; 0 otherwise.
EXAMPLES
The following example creates an error record of the type "Pin made fat" in an error view and
then adds details to it:
prompt> set errId [create_drc_error -error_view "mydesign_mydrc.err" \
-type "Pin made fat"]
{25635}
prompt> add_drc_error_detail -drc_error $errId \
-error_view "mydesign_mydrc.err" \
-net [get_nets myNetName] -layer [get_layers myLayerName] \
-rectangles {{574.0700 430.3600 578.9700 433.4400}}
1
SEE ALSO
create_drc_error(2)
create_drc_error_type(2)
add_drc_error_detail
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IC Compiler™ Tool Commands
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create_open_drc_error(2)
create_open_locator_drc_error(2)
create_short_drc_error(2)
create_spacing_drc_error(2)
add_open_drc_error_detail(2)
list_drc_error_types(2)
report_drc_error_type(2)
get_drc_errors(2)
Chapter 1:
add_drc_error_detail
27
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
add_end_cap
Adds end cap cells to the cell rows in the current design.
SYNTAX
status add_end_cap
-lib_cell lib_cell_name
[-vertical_cells lib_cell_names [-fill_corner]]
[-mode both | bottom_left | upper_right]
[-mirror]
[-respect_padding]
[-respect_blockage]
[-respect_keepout]
[-ignore_soft_blockage]
[-skip_fixed]
[-next_to_fixed]
[-at_va_boundary]
[-at_plan_group_boundary]
Data Types
lib_cell_name
lib_cell_names
collection of one cell
collection of one or more cells
ARGUMENTS
-lib_cell lib_cell_name
Specifies the reference library cell to be used as horizontal end caps. You can specify
only one cell.
This is a required option.
-vertical_cells lib_cell_names
Specifies the reference library cells to be used as vertical end caps.
By default, the tool does not add vertical end cap cells.
-fill_corner
Fills the corners where vertical and horizontal end caps meet with horizontal end cap
cells. You must use this option with the -vertical_cells option.
add_end_cap
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By default, the tool does not fill corners.
-mode both | bottom_left | upper_right
Specifies how to place the end cap cells.
The behavior for each mode is
•
both (the default)
Places an end cap cell at both ends of the row. The left end cap in normal orientation
and the right end cap is flipped. Note that the -mirror option has no effect when using
the both mode.
•
bottom_left
Places an end cap cell at the bottom of a vertical row or to the left of a horizontal row.
•
upper_right
Places an end cap cell at the top of a vertical row or to the right of a horizontal row.
-mirror
Places the end cap cell in a flipped orientation. This option has no effect when you
specify -mode both.
By default, the tool places the cell in its normal orientation.
-respect_padding
Prevents the tool from placing end cap cells in the padding areas around macro cells.
By default, the tool can place end cap cells in the padding areas.
-respect_blockage
Prevents the tool from placing end cap cells inside placement blockages.
By default, the tool can place end cap cells inside placement blockages.
-respect_keepout
Prevents the tool from placing end cap cells inside the keepout margins around macro
cells. This option does not apply to keepout margins on other types of cells.
-ignore_soft_blockage
Ignores soft blockages and honors only hard blockages. You must use this option with
the -respect_blockage option.
-skip_fixed
Prevents the tool from placing end cap cells at locations that are occupied by fixed cells.
If placing a horizontal end cap at either end of a row that overlaps a fixed cell, no
horizontal end cap is placed.
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
You must use this option with the -vertical_cells option. This option is mutually
exclusive with the -next_to_fixed option.
By default, the tool does not respect fixed cells.
-next_to_fixed
Treats fixed cells that are less than one unit tile from a boundary as a macro and places
a horizontal end cap cell next to the fixed cell. Other fixed cells are ignored by this option.
This option is mutually exclusive with the -skip_fixed option.
-at_va_boundary
Places horizontal end cap cells on both sides of the vertical voltage area boundaries.
When you use this option, rows are treated as cut by the vertical voltage area
boundaries. Therefore, horizontal end cap cells are placed on both sides of a vertical
voltage area boundary.
If a voltage area does not have guard bands, its boundary is ignored during end cap
insertion.
By default, voltage area boundaries are ignored during end cap insertion.
-at_plan_group_boundary
Places horizontal end cap cells on both sides of the vertical plan group boundaries.
When you use this option, rows are treated as cut by vertical plan group boundaries.
Therefore, horizontal end cap cells are placed on both sides of a vertical plan group
boundary.
By default, plan group boundaries are ignored during end cap insertion.
DESCRIPTION
This command allows you to add horizontal end cap cells at both ends of a cell row and,
optionally, to add vertical end cap cells along horizontal edges. An end cap cell is typically
not a logic cell and is added before placement to serve a special purpose for the row, such
as a decoupling capacitor. You should specify a proper end cap cell because the tool can
accept any standard cell as an end cap cell.
If you use the -vertical_cells option and the remaining gaps are larger than or equal to the
smallest vertical end cap cells, the tool inserts the vertical end cap cells in the specified
order. If the remaining gaps are smaller than the smallest vertical end cap cells, the tool
inserts the next cell in order. To avoid unfilled gaps, carefully consider the size of the vertical
end cap cells that you specify.
add_end_cap
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example adds horizontal end cap cells named MY_END_CAP to the current
design.
prompt> add_end_cap -lib_cell MY_END_CAP
SEE ALSO
set_keepout_margin(2)
Chapter 1:
add_end_cap
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
add_multisource_drivers
Sets up the tap drivers for a multisource tree. These are typically driven by a clock mesh and
are used by a subsequent split_multisource_clock command.
SYNTAX
status add_multisource_drivers
-mesh_net net
[-driver_type lib_cell]
-tap_markers vias_port_shapes_cells_net_shapes
| -tap_locations list_of_points
[-prefix string]
[-check_only]
[-remove_display]
Data Types
net
lib_cell
vias_port_shapes_cells_net_shapes
port_shapes, cells, or net_shapes.
list_of_points
a list of two distances)
a collection of one net
a collection of one library cell
a collection containing vias,
a Tcl list of points (each point is
ARGUMENTS
-mesh_net net
The clock mesh net that drives the newly created drivers. This is required for all uses of
the command except -remove_display.
-driver_type lib_cell
Specifies the type of cell to be added. If none is specified, the tool picks one based on
heuristics.
-tap_markers vias_port_shapes_cells_net_shapes
Provides a quick way to specify the locations where you want to place the drivers.
Typically this is a collection of all the vias on the mesh net, but other object types can
also be used.
add_multisource_drivers
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-tap_locations list_of_points
If you have the specific XY locations where you would like the cells to go, it can be
accepted as a Tcl list of lists with this option.
-prefix string
Controls the name of newly created cells. The default is "MS_TAP_". The new cells have
this prefix followed by an integer.
-check_only
Does not insert the cells, but puts a white rectangle where they would be placed. Start
the GUI before using this option.
-remove_display
Removes the white rectangles created with the -check_only option from the display.
Running the command without -check_only (to actually create the cells) also removes
the rectangles.
DESCRIPTION
The add_multisource_drivers command adds clock buffer cells that are driven by a
common net, which is typically a clock mesh net. Their output pins can then be used by the
split_multisource_clock command. The split_multisource_clock command need not be run
immediately after the add_multisource_drivers command. Note that the
add_multisource_drivers command can be run first, independently and then the mesh can
be analyzed and characterized electrically. If it is acceptable the split_multisource_clock
command can be run subsequently.
You can specify the locations of drivers with the -tap_markers and -tap_locations options. If
you have specific XY locations in mind, list them explicitly with the -tap_locations options. If
you want the drivers to follow a pattern of preexisting objects, including vias, cells,
port_shapes, and net_shapes (wires), then use the -tap_markers option. If you use both, the
union of these locations is used.
To facilitate this process, you might want to look at the locations of the drivers before
actually adding them. This can be done with the -check_only option. Be sure the GUI is
turned on before running the command this way. After running with -check_only you see
small white rectangles marking the proposed locations of drivers. They might not be exactly
at the locations you specified, since they have to move to legal locations (avoiding
placement blockages, large macros, etc.) To remove these objects from the display, run with
the -remove_display option, or rerun the command without check_only. In either case, the
rectangles are removed from the display.
The new cell names are
Chapter 1:
add_multisource_drivers
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Tool Commands
Commands
L-2016.03
Version L-2016.03
<prefix> <tap number>
such as "MS_TAP_14."
Note that the split_multisource_clock command works best if the names of these driver pins
end in sequential integers. If so, it can then create new nets and cells that follow this pattern.
EXAMPLES
The following example runs the add_multisource_drivers command to create a
multisource tree. The original tree is driven by taps_0/Z.
prompt> add_multisource_drivers -mesh_net I_CLOCK_GEN/net_sys_clk \
-driver_type tsmc_70_max/drv8x -check_only \
-tap_markers [get_vias -of orca/clock_gen/system_clk -filter
{route_type=="Clk Strap"}]
1
SEE ALSO
split_multisource_clock(2)
create_clock_mesh(2)
add_clock_drivers(2)
add_multisource_drivers
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add_open_drc_error_detail
Adds additional details to an existing error object that is associated with the open error type
class.
SYNTAX
status add_open_drc_error_detail
-error_view mw_error_view
-drc_error drc_error
-node node_number
-rectangles rectangles | -polygons polygons
[-layer layer]
Data Types
mw_error_view
drc_error
node_number
rectangles
polygons
layer
list or collection of one item
list or collection of one item
integer
list
list
list or collection of one item
ARGUMENTS
-error_view mw_error_view
Specifies the error view in which to create the error record. You can specify only a single
error view; specifying more than one error view causes an error.
This is a required option.
-drc_error drc_error
Specifies the error object to which to add these details. You can specify only a single
error object; specifying more than one error object causes an error.
You can add error details only to existing error objects. To specify the error object, use
the collection returned by the create_open_drc_error command or the get_drc_errors
command or use the object ID of the error object. The specified error object must be
associated with the open error type class. For more information about error type classes,
see the man page for the create_drc_error_type command.
This is a required option.
Chapter 1:
add_open_drc_error_detail
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Commands
L-2016.03
Version L-2016.03
-node node_number
Identifies the node to which the specified net shapes belong. An open type error is
described by two or more disjoint nodes, where a node is a set of connected net shapes.
This option uniquely identifies the node, while the -rectangles or -polygons option
specifies the net shapes associated with the node.
This is a required option.
-rectangles rectangles
Specifies the rectangle shapes to add to the error object. You can specify one or more
rectangles as a list of rectangles:
{rectangle+}
where each rectangle is specified as a list of four coordinates:
{llx lly urx ury}
which represent the x- and y-coordinates of the lower-left and upper-right corners of the
rectangle. You can also define a rectangle as a list of two points for the lower-left and
upper-right corners, where a point is a list of two coordinates:
{{llx lly} {urx ury}}
The -rectangles and -polygons options are mutually exclusive; you must specify one of
these options.
-polygons polygons
Specifies the polygon shapes to add to the error object. You can specify one or more
polygons as a list of polygons:
{polygon+}
where each polygon is a list of points
{point+}
and each point is a list that contains an x- and y-coordinate:
{x y}
The list of polygons might look like this:
add_open_drc_error_detail
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{{{ax1 ay1} {ax2 ay2} ... {axn ayn}} {{bx1 by1} {bx2 by2} ... {bxn byn}}}
The -rectangles and -polygons options are mutually exclusive; you must specify one of
these options.
-layer layer
Specifies the layer associated with the shapes. You can specify the layer by using the
layer name from the technology file or by using the get_layers command.
DESCRIPTION
This command adds shapes and associated details to an existing error object that is
associated with the open error type class.
The command returns 1 if successful; 0 otherwise.
EXAMPLES
The following example opens an error view named mydesign_mydrc.err, creates an error
type named "Open Net" in the open error type class, creates an error record of the "Open
Net" type, and then adds details to the error record:
prompt> set cellId [open_mw_cel -not_as_current mydesign_mydrc.err]
{mydesign_mydrc}
prompt> set typeId [create_drc_error_type -name "Open Net"
-class "open" \
-info "There are opens in the net" -error_view $cellId]
1024
prompt> set openErrId [create_open_drc_error \
-type $typeId -error_view $cellId]
{1280}
prompt> add_open_drc_error_detail -error_view $cellId \
-drc_err $openErrId -node 1 -layer RV \
-rectangles {{574.0700 430.3600 578.9700 430.3600} \
{574.0700 436.3600 574.0700 453.3600}}
1
SEE ALSO
create_open_drc_error(2)
create_drc_error_type(2)
list_drc_error_types(2)
report_drc_error_type(2)
Chapter 1:
add_open_drc_error_detail
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
get_drc_errors(2)
add_open_drc_error_detail
38
IC Compiler™ Tool Commands
Version L-2016.03
add_pg_pin_to_db
Converts rail or non-pg_pin based logic library (db) into pg_pin based logic library.
SYNTAX
status add_pg_pin_to_db
input_db_filename
[-mw_library_name mw_lib_name]
[-pg_map_file pg.map]
-output pg_db_filename
[-fast]
[-expanded]
[-verbose]
[-pg_map_template pg_pin_map_template_filename]
[-force_update]
ARGUMENTS
input_db_filename
Specifies the name of the input logic library (.db) file, which is in non-pg_pin-based
format. It is mandatory.
-mw_library_name mw_lib_name
Specifies one or more Milkyway library name(s) (FRAM view) that correspond to the
input db file.
-pg_map_file pg.map
Specifies the file name of mapping between non-pg_pin-based data and pg_pin-based
data.
-output pg_db_filename
Specifies the name of new pg_pin-based db file that is generated after the conversion. It
cannot be the same name as the input db file. This option is mandatory.
DESCRIPTION
Command add_pg_pin_to_db converts rail or non-pg_pin based logic library (db) into
pg_pin based logic library. There are three cases:
Chapter 1:
add_pg_pin_to_db
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Tool Commands
Commands
L-2016.03
Version L-2016.03
1) with complete Milkyway library If all cells have single P/G rail (1P1G), -pg_map_file option
is not required but -mw_library_name should be specified to derive the mapping from the
Milkyway Fram view. If some cells have multiple P/G rails, -pg_map_file is required for those
cells.
2) without Milkyway library (db only) If you only specify a logic library (.db), no matter if it is
a single P/G rail library or not, you must specify -pg_map_file to make the conversion.
3) with partial Milkyway library If some cells exists in both logic library and Milkyway library
while others only exist in logic library, -pg_map_file should be specified for the cells that are
missing in the Milkyway library.
EXAMPLES
The following example converts the logic library "old.db" into pg_pin-based "pg.db".
prompt> add_pg_pin_to_db old.db -mw_library_name {mw_lib}
-pg_map_file pg.map -output pg.db
SEE ALSO
add_pg_pin_to_lib(2)
add_pg_pin_to_db
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IC Compiler™ Tool Commands
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add_pg_pin_to_lib
converts rail or non-pg_pin based logic library (.lib) into pg_pin based logic library (.lib).
SYNTAX
status add_pg_pin_to_lib
input_lib_filename
[-mw_library_name mw_lib_name]
[-pg_map_file pg.map]
[-pg_map_template template_filename]
[-expanded]
-output pg_lib_filename
[-common_shell_path common_shell_path]
[-fast]
[-verbose]
[-force_update]
ARGUMENTS
input_lib_filename
Specifies the name of the input logic library (.lib) file, which is in non-pg_pin-based
format. It is mandatory.
-mw_library_name mw_lib_name
Specifies one or more Milkyway library name(s) (FRAM view) that correspond to the
input db file.
-pg_map_file pg.map
Specifies the file name for mapping between non-pg_pin-based data and pg_pin-based
data including PM attributes.
-pg_map_template template_filename
Specifies the file name for map template.
-expanded
Specifies to generate expanded map template with wildcard expanded. By default it is
OFF meaning compressed map template using wildcards will be generated.
Chapter 1:
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Tool Commands
Commands
L-2016.03
Version L-2016.03
-output pg_lib_filename
Specifies the name of new pg_pin-based lib file that is generated after the conversion. It
cannot be the same name as the input lib file. This option is mandatory.
DESCRIPTION
Command add_pg_pin_to_lib converts rail or non-pg_pin based logic library (.lib) into
pg_pin based logic library (.lib). There are three cases:
1) with complete Milkyway library If all cells have single P/G rail (1P1G), -pg_map_file option
is not required but -mw_library_name should be specified to derive the mapping from the
Milkyway Fram view. If some cells have multiple P/G rails, -pg_map_file is required for those
cells.
2) without Milkyway library (.lib only) If you only specify a logic library (.lib )and no Milkyway
library, for a single P/G rail library or multi-rail library, you must specify -pg_map_file to make
the conversion.
3) with partial Milkyway library If some cells exists in both logic library and Milkyway library
while others only exist in logic library, -pg_map_file should be specified for the cells that are
missing in the Milkyway library and for PM cells.
EXAMPLES
The following example converts the logic library "old.lib" into pg_pin-based "pg.lib".
prompt> add_pg_pin_to_lib old.lib -pg_map_file
-output pg.lib
pg.map
SEE ALSO
add_pg_pin_to_db(2)
add_pg_pin_to_lib
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add_port_state
Adds state information to a supply port.
SYNTAX
string add_port_state
supply_port_name
-state {state_name state_value}
Data Types
supply_port_name
state_name
state_value
string
string
string
ARGUMENTS
supply_port_name
Specifies the name of the supply port. Hierarchical names are allowed.
-state {state_name state_value}
Specifies the name and value of a state of the supply port. You can repeat this option.
The state value can be one of the following:
•
A single floating point number that represents the nominal voltage for the specified
state. For example, to define a state called s88 with a nominal voltage of 0.88, use
the following syntax:
-state {s88 0.88}
•
Three floating point numbers that represent the minimum, nominal, and maximum
voltages of the specified state, respectively. For example, to define a state called
active_state with a minimum voltage of 0.88, a nominal voltage of 0.90, and a
maximum voltage of 0.92, use the following syntax:
-state {active_state 0.88 0.90 0.92}
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
•
NOTE: It is an error if minimum voltage is greater than (>) the nominal voltage or the
nominal voltage is greater than (>) the maximum voltage.
•
The keyword off, which indicates an inactive state. For example, to define an inactive
state called off_state, use the following syntax:
-state {off_state off}
DESCRIPTION
This command adds state information to a supply port. The first occurrence of the
supply_port_name option is the default state of the supply port. You can use this to
represent off-chip supply sources that are not driven by the testbench. This option defines
the voltage level supplied to the chip. It provides a convenient shortcut to facilitate
verification and analysis without requiring the creation of a power domain and a supply
network within the verification environment. An error occurs if supply_port_name does not
already exist before executing this command.
This command returns the fully-qualified name from the current scope of the created port or
a null string if the port is not created.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the states and voltages of a supply port named VN1:
prompt> add_port_state VN1 \
-state {active_state 0.88 0.90 0.92} \
-state {off_state off}
SEE ALSO
add_pst_state(2)
create_pst(2)
report_pst(2)
add_port_state
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add_power_state
Adds state information to a supply set or a group.
SYNTAX
status add_power_state
[-supply | -group] object_name
[-simstate {simstate}]
[-update]
[-state state_name {[-supply_expr {supply_expression}]
[-logic_expr {logic_expression}]
[-simstate
{simstate}]
[-illegal]}]*
Data Types
object_name
state_name
supply_expression
logic_expression
simstate
update
illegal
string
string
string
string
string
flag
flag
ARGUMENTS
object_name
Specifies the name of a supply set, or the name of a group created with the
create_power_state_group command. The name should be a simple (nonhierarchical)
name.
-state state_name
Specifies the name of the state of the supply set or the group. The name should be a
simple (nonhierarchical) name. This option can be specified multiple times in the same
command.
-supply_expr {supply_expression}
This option can only be specified when the object_name is a supply set. This option
specifies a Boolean expression in terms of nets and their netstates. The only operator
allowed in the Boolean expression is &&. Each subexpression in the Boolean expression
Chapter 1:
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Tool Commands
Commands
L-2016.03
Version L-2016.03
specifies the net and netstate definitions. Each subexpression must have the following
syntax:
net == netstate
The net can be power or ground and the netstate syntax must be one of the following:
status
`{status}
`{status, nom}
`{status, min, max}
`{status, min, nom, max}
{status}
{status nom}
{status min max}
{status min nom max}
•
status can be OFF or FULL_ON
•
min, nom, and max are floating-point numbers representing the minimum, nominal,
and maximum voltages of the specified state, respectively.
•
NOTE: It is an error if min is greater than (>) nom or if nom is greater than (>) max.
•
If the status is FULL_ON, at least one voltage must be defined.
-logic_expr {logic_expression}
If the object_name is a supply set, then this option specifies a SystemVerilog Boolean
expression in terms of logic nets and supply nets. The -logic_expr option does not affect
implementation and is intended to be used by simulation tools, to read and write
transparently.
If the object_name is a group, then this option specifies a Boolean expression in terms
of supply sets/groups/PSTs and their states. The only operator allowed in the Boolean
expression is &&.
-simstate {simstate}
This option can only be specified when the object_name is a supply set. This option
specifies a simstate for the power states associated with a supply set, valid values are
NORMAL, CORRUPT_ON_ACTIVITY, CORRUPT and NOT_NORMAL. The -simstate
option does not affect implementation and is intended to be used by simulation, so the
tool reads and writes the information specified with this option transparently.
This option can be specified for every state that is defined with the add_power_state
command (as shown below) add_power_state -state state_name {-simstate simstate_value}.
add_power_state
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This option can also be specified globally for the entire add_power_state command (as
shown below) add_power_state -simstate simstate_value -state state_name {...}
However, the latter usage has been discontinued in the UPF standard. This usage has
been retained only for backward compatibility purposes and will be gotten rid of in a
future release.
-update
This option is used to add additional power states (supply set states or group states) to
an object.
In case of supply sets, this option can be used to add incremental information
(-logic_expr, -supply_expr, -simstate) to an existing supply set state. Attempt to add
information that has already been specified before will result in an error.
-illegal
This option is used to indicate that the state defined (for a supply set or a group) is an
illegal state.
DESCRIPTION
This command adds state information to a supply set or a group.
If the object specified is a supply set, then use this command to set power states on the nets
of a supply set and then use them as supplies for the power state table. If the supply set
does not already exist, this command issues an error.
If the object specified is a group, then use this command to create the power state table by
using supply sets, other groups or PSTs in the -logic_expr option. The group should have
been previously created using the create_power_state_group command. If the group does
not already exist, this command issues an error. To add additional group states to a group,
the -update option must be used.
EXAMPLES
The following example shows the states and voltages of a supply set, SS1:
prompt> add_power_state SS1 \
-state HVp {-supply_expr {power == `{FULL_ON, 0.88, 0.90, 0.92}}}
prompt> add_power_state SS1 \
-state HPg {-supply_expr {ground == `{OFF}}}
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The following example defines LV state, but omitting the details on voltages for SS2 supply
set:
prompt> add_power_state SS2 \
-state LV {}
The following example defines a state ON for supply set SS1 where the supply_expression
is a Boolean expression of power and ground.
prompt> add_power_state -supply SS1\
-state ON {-supply_expr {power == {FULL_ON 0.8} && ground ==
{FULL_ON 0}}}
The following example shows how power states can be added to a group. Here 'GROUP1'
is a power state group that has previously been created with the create_power_state_group
command. GS1 and GS2 are the names of the group states created. The system is in state
GS1 when supply set SS1 is in state ON1, and group GROUP2 defined in scope MID1 is in
state ON1, and the PST PST1 defined in scope MID2 is in state ON1.
prompt> add_power_state -group GROUP1 \
-state GS1 {-logic_expr {SS1 == ON1 && MID1/GROUP2 == ON1 &&
MID2/PST1 == ON1}}
-state GS2 {-logic_expr {SS1 == ON2 && MID1/GROUP2 == ON2 &&
MID2/PST1 == ON2}}
SEE ALSO
create_power_state_group(2)
add_pst_state(2)
create_pst(2)
create_supply_set(2)
report_pst(2)
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add_pst_state
Defines the states of each of the supply nets for one possible state of the design.
SYNTAX
status add_pst_state
state_name
-pst table_name
-state supply_states
Data Types
state_name
table_name
supply_states
string
string
list
ARGUMENTS
state_name
Specifies the name of the power state.
-pst table_name
Specifies the power state table (PST) to which this state applies.
-state supply_states
Lists the supply net state names in the corresponding order of the -supplies option
listing in the create_pst command.
DESCRIPTION
The add_pst_state command defines the states of each of the supply nets for one possible
state of the design. It is an error if the number of supply state names is different from the
number of supply nets within the power state table.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example defines the supply net state names for the s1, s2 and s3 power
states:
create_pst pt
add_pst_state
add_pst_state
add_pst_state
-supplies { PN1 PN2
s1 -pst pt -state {
s2 -pst pt -state {
s3 -pst pt -state {
SOC/OTC/PN3
s08 s08 s08
s08 s08 off
s08 s09 off
}
}
}
}
SEE ALSO
add_port_state(2)
create_pst(2)
report_pst(2)
add_pst_state
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add_row
Creates a list of rows in the design.
SYNTAX
status add_row
-within {coordinates}
[-direction horizontal | vertical]
[-flip_first_row]
[-no_double_back]
[-minimal_channel_height channel_height]
[-no_start_from_first_row]
[-tile_name tile_name]
[-snap_to_row_direction {wire_track | tile_width | none}]
[-snap_to_orthogonal_row_direction {existing_row | wire_track |
none}]
[-left_offset left_offset]
[-right_offset right_offset]
[-top_offset top_offset]
[-bottom_offset bottom_offset]
[-allow_overlap]
Data Types
coordinates
channel_height
tile_name
left_offset
right_offset
top_offset
bottom_offset
list
float
string
float
float
float
float
ARGUMENTS
-within {coordinates}
Specifies the boundary within which to create rows. For a rectangular region, specify the
coordinates for the lower-left and upper-right corners as {ll_x ll_y} {ur_x ur_y}}. For a
rectilinear region, specify a list of rectilinear coordinates in either clockwise or
counterclockwise order.
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-direction horizontal | vertical
Specifies the direction of rows to be created. By default, the direction of rows is the same
as the direction of the base array where the rows are added.
-flip_first_row
Flips the bottom row in a horizontal core area or the leftmost row in a vertical core area.
The -flip_first_row and -no_double_back options are mutually exclusive. By default,
the first row is not flipped.
-no_double_back
Creates rows without flipping one row in each pair. The -no_double_back and
-flip_first_row options are mutually exclusive. By default, the area can contain pairs of
rows that are doubled back.
-minimal_channel_height channel_height
Specifies the amount of channel height to allocate for routing between rows. By default,
the minimum channel height is 0.0.
-no_start_from_first_row
Specifies that the bottom row in a horizontal core area or the leftmost row in a vertical
core area is not paired with the second row. By default, the first row can form a row pair
with the second row.
-tile_name tile_name
Specifies the name of the unit tile to use in rows. By default, the tile name is unit.
-snap_to_row_direction {wire_track | tile_width | none}
Specifies the snapping type in the row direction.
If you specify a snapping type of wire_track for a design with horizontal rows, the tool
aligns the vertical-layer wire tracks of the tile and the design. For a design with vertical
rows, the tool aligns the horizontal-layer wire tracks of the tile and the design.
If you specify a snapping type of tile_width for a design with horizontal rows, the tool
separates the left edge of the base array boundary and the starting left edge of the row
by using a multiple of the tile width. For a design with vertical rows, the tool separates
the bottom edge of the base array boundary and the bottom edge of the first row by
using a multiple of the tile width.
If you specify a snapping type of none for a design with horizontal rows, the tool creates
each new row from the left edge as specified by the -within option. For a design with
vertical rows, the tool creates each new row from the bottom edge as specified by the
-within option.
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By default, the snapping type is wire_track.
-snap_to_orthogonal_row_direction {existing_row | wire_track | none}
Specifies the snapping type in the orthogonal row direction.
If you specify an orthogonal snapping type of existing_row, the tool attempts to align
the new row with an existing row that is within one tile height of the specified location.
The existing row must have the same tile pattern and orientation as the first new row. If
the tool cannot find an existing row that meets the criteria, the tool snaps the new row to
a wire track.
If you specify a snapping type of wire_track for a design with horizontal rows, the tool
aligns the horizontal-layer wire track of the tile and the design. For a design with vertical
rows, the tool aligns the vertical-layer wire tracks of the tile and the design.
If you specify a snapping type of none for a design with horizontal rows, the tool creates
the first row at the bottom edge as specified by the -within option. For a design with
vertical rows, the tool creates the first row at the left edge as specified by the -within
option.
By default, the orthogonal row snap type is existing_row.
-left_offset left_offset
Specifies the minimum space between the new rows and the left boundary specified by
the -within option. By default, the left offset is 0.
-right_offset right_offset
Specifies the minimum space between the new rows and the right boundary specified by
the -within option. By default, the right offset is 0.
-top_offset top_offset
Specifies the minimum space between the new rows and the top boundary specified by
the -within option. By default, the top offset is 0.
-bottom_offset bottom_offset
Specifies the minimum space between the new rows and the bottom boundary specified
by the -within option. By default, the bottom offset is 0.
-allow_overlap
Specifies that overlapped rows are allowed. By default, overlapped rows are not
allowed, whether they are same height or not.
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DESCRIPTION
This command adds rows to the specified area.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates rows in a rectangular region.
prompt> add_row -within {{100 100} {300 300}} -tile_name unit1
info: created 6 rows.
1
The following example creates rows in the specified rectilinear region.
prompt> add_row -within {{30.0 30.0} {30.0 50.0} \
{40.0 50.0} {40.0 60.0} {50.0 60.0} {50.0 40.0} \
{60.0 40.0} {60.0 30.0} {30.0 30.0}} -tile_name unit2
Info: 18 rows are added.
1
The following example creates rows and sets left/right offset of 5 units and top/bottom offset
of 10 units.
prompt> add_row -within {{100 100} {300 300}} \
-left_offset 5 -right_offset 5 \
-top_offset 10 -bottom_offset 10 \
Info: 6 rows are added.
1
The following example creates rows with a channel height of 3.69 units between the rows.
prompt> add_row -within {{30 148} {30 159} \
{645 159} {645 166} {817 166} \
{817 159} {1432 159} {1432 148}} \
-minimal_channel_height 3.69
Info: created 4 rows.
1
The following example creates rows that overlap with the existing rows in the region.
add_row
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prompt> add_row -within {{30 148} {30 159} \
{645 159} {645 166} {817 166} \
{817 159} {1432 159} {1432 148}}
-allow_overlap
Warning: Existing row (id = 11279) found in the
creation region. (MWUI-183)
Warning: Existing row (id = 11280) found in the
creation region. (MWUI-183)
Warning: Existing row (id = 11281) found in the
creation region. (MWUI-183)
Warning: Existing row (id = 11282) found in the
creation region. (MWUI-183)
Warning: Existing row (id = 11283) found in the
creation region. (MWUI-183)
Info: created 5 rows.
1
Version L-2016.03
\
specified new row
specified new row
specified new row
specified new row
specified new row
SEE ALSO
cut_row(2)
write_floorplan(2)
Chapter 1:
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add_tap_cell_array
Adds tap cells to the design, forming a two-dimensional array structure.
SYNTAX
status add_tap_cell_array
-master_cell_name cell_name
-distance tap_cell_distance
[-offset distance]
[-pattern normal | every_other_row | stagger_every_other_row]
[-voltage_area {voltage_area_collection}]
[-plan_group plan_group_collection]
[-tap_cell_identifier tap_cell_prefix]
[-tap_cell_separator tap_cell_separator]
[-no_tap_cell_under_layers layer_list]
[-well_port_name port_name]
[-well_net_name net_name]
[-substrate_port_name port_name]
[-substrate_net_name net_name]
[-connect_power_name power_net_name]
[-connect_ground_name ground_net_name]
[-fill_boundary_row true | false]
[-fill_macro_blockage_row true | false]
[-boundary_row_double_density true | false]
[-macro_blockage_row_double_density true | false]
[-left_macro_blockage_extra_tap by_rule | must_insert | no_insert]
[-right_macro_blockage_extra_tap by_rule | must_insert | no_insert]
[-left_boundary_extra_tap by_rule | must_insert | no_insert]
[-right_boundary_extra_tap by_rule | must_insert | no_insert]
[-ignore_soft_blockage true | false]
[-at_distance_only true | false]
[-skip_fixed_cells true | false | tap]
[-respect_keepout]
[-remove_redundant_tap_cells]
[-no_1x]
Data Types
cell_name
tap_cell_distance
distance
voltage_area_collection
plan_group_collection
tap_cell_prefix
tap_cell_separator
layer_list
port_name
net_name
power_net_name
add_tap_cell_array
string
float
float
collection
collection
string
string
list
string
string
string
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ground_net_name
Version L-2016.03
string
ARGUMENTS
-master_cell_name cell_name
Specifies the library reference cell to be used as a tap cell. You can specify only a single
library cell.
This is a required option.
-distance tap_cell_distance
Specifies the distance in microns between two tap cells in a row. This distance is
referred to as the tap distance.
This is a required option.
-offset distance
Specifies the distance in microns that the tap pattern should be shifted to the right.
If the offset distance is a multiple of the tap distance, the effective offset is 0. For
example, if the tap distance is 10 microns and the offset is 32 microns, the effective
offset is 2 (32 - 3x10).
The default is 0.
-pattern normal | every_other_row | stagger_every_other_row
Specifies the tap cell insertion pattern.
The supported patterns are
•
normal (the default)
The tool adds tap cells to every row using the specified tap distance. The tap
distance specified for this pattern should be approximately twice the design rule
distance limit.
•
every_other_row
The tool adds tap cells to every other row for odd rows only. This reduces the number
of required tap cells by approximately half as compared to the normal pattern. The
tap distance specified for this pattern should be approximately twice the design rule
distance limit.
•
stagger_every_other_row
The tool adds tap cells to every row. The tap cells on even rows are offset with half
the tap distance relative to the odd rows, producing a checkerboard-like pattern. This
pattern also reduces the number of required tap cells by approximately half as
Chapter 1:
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compared to the normal pattern. The tap distance specified for this pattern should be
approximately four times the design rule distance limit.
-voltage_area {voltage_area_collection}
Inserts tap cells only in the specified voltage areas.
By default, the tool inserts tap cells in all voltage areas.
If you specify both the -voltage_area and -plan_group options, taps cells are inserted
only in those locations that meet both requirements.
-plan_group plan_group_collection
Inserts tap cells only in the specified plan groups and under the plan group hierarchy.
By default, the tool inserts tap cells in all plan groups.
If you specify both the -voltage_area and -plan_group options, taps cells are inserted
only in those locations that meet both requirements.
-tap_cell_identifier tap_cell_prefix
Specifies the prefix for the inserted tap cells.
By default, no prefix is added.
-tap_cell_separator tap_cell_separator
Specifies the separator character that is used when composing the instance name of the
tap cell.
The tap cell instance name consists of a prefix, the library reference cell name, the tap
layer number, and a rolling number. For example, the instance name
"tapfiller!MY_TAP!98!25" has the tapfiller prefix, the MY_TAP library reference cell
name, the tap layer number 98, the rolling number 25, and the tap cell separator !. This
naming convention allows you to do pattern matching selection of the tap cells.
The default is "!".
-no_tap_cell_under_layers layer_list
Avoids placing tap cells under the preroutes on the specified metal layers.
-well_port_name port_name
Specifies the port name of the well tie.
-well_net_name net_name
Specifies the net name of the well tie.
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-substrate_port_name port_name
Specifies the port name of the substrate tie.
-substrate_net_name net_name
Specifies the net name of the substrate tie.
-connect_power_name power_net_name
Specifies the net to connect the tap cell's power pin if there is more than one power net
in the design,
-connect_ground_name ground_net_name
Specifies the net to connect the tap cell's ground pin if there is more than one ground net
in the design.
-fill_boundary_row true | false
Specifies the density adjustment of the tap cell array.
When you use the -pattern every_other_row option, every other row is empty to
reduce the number of tap cells inserted. When set to true (the default), this option
instructs the tool to fill the section of a row that is adjacent to the chip boundary to avoid
tap rule violations. When set to false, the section of the row adjacent to the chip
boundary might need to rely on tap cells outside the boundary to satisfy the tap distance
rule.
This option is effective only when you also use the -pattern every_other_row option.
-fill_macro_blockage_row true | false
Specifies the density adjustment of the tap cell array.
When you use the -pattern every_other_row option, every other row is empty to
reduce the number of tap cells inserted. When set to true (the default), this option
instructs the tool to fill the section of a row that is adjacent to the macro or blockage
boundary to avoid tap rule violations. When set to false, the section of the row adjacent
to the macro or blockage boundary might need to rely on tap cells outside the boundary
to satisfy the tap distance rule.
This option is effective only when you also use the -pattern every_other_row option.
-boundary_row_double_density true | false
Specifies the density adjustment of the tap cell array.
When you use the -pattern stagger_every_other_row option, every other row is
staggered to reduce the number of tap cells inserted. When set to true (the default), this
option instructs the tool to double the tap density on the section of a row that is adjacent
to the chip boundary to avoid tap rule violations. When set to false, the section of the row
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adjacent to the chip boundary might need to rely on tap cells outside the boundary to
satisfy the tap distance rule.
This option is effective only when you also use the -pattern stagger_every_other_row
option.
-macro_blockage_row_double_density true | false
Specifies the density adjustment of the tap cell array.
When you use the -pattern stagger_every_other_row option, every other row is
staggered to reduce the number of tap cells inserted. When set to true (the default), this
option instructs the tool to double the tap density on the section of a row that is adjacent
to the macro or blockage boundary to avoid tap rule violations. When set to false, the
section of the row adjacent to the macro or blockage boundary might need to rely on tap
cells outside the boundary to satisfy the tap distance rule.
This option is effective only when you also use the -pattern stagger_every_other_row
option.
-left_macro_blockage_extra_tap by_rule | must_insert | no_insert
Specifies the density adjustment of the tap cell array.
Valid values for this option are
•
by_rule (the default)
If the left row edge is more than the minimum tap distance from the closest tap cell
on the same row as the macro or blockage, the tool inserts an extra tap cell at the
minimum tap distance from the left edge. Note that the minimum tap distance is half
of the spacing specified by the -distance option.
•
This setting might insert an extra tap cell, but always ensures that the minimum tap
distance rule is not violated.
•
must_insert
If there is no tap cell within the minimum tap distance from the left row edge, the tool
inserts an extra tap cell at the minimum tap distance from the left edge.
•
If there is a tap cell within the minimum tap distance from the left row edge, the tool
inserts an extra tap cell exactly at the left edge.
•
Note that the minimum tap distance is half of the spacing specified by the -distance
option.
•
no_insert The tool never inserts an extra tap cell at the left edge of the row. When
you use this setting, standard cells near the left side of the row might need to rely on
tap cells inside the macro or blockage to satisfy the tap distance rule.
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-right_macro_blockage_extra_tap by_rule | must_insert | no_insert
Specifies the density adjustment of the tap cell array.
Valid values for this option are
•
by_rule (the default)
If the right row edge is more than the minimum tap distance from the closest tap cell
on the same row as the macro or blockage, the tool inserts an extra tap cell at the
minimum tap distance from the right edge. Note that the minimum tap distance is half
of the spacing specified by the -distance option.
•
This setting might insert an extra tap cell, but always ensures that the minimum tap
distance rule is not violated.
•
must_insert
If there is no tap cell within the minimum tap distance from the right row edge, the tool
inserts an extra tap cell at the minimum tap distance from the right edge.
•
If there is a tap cell within the minimum tap distance from the right row edge, the tool
inserts an extra tap cell exactly at the right edge.
•
no_insert The tool never inserts an extra tap cell at the right edge of the row. When
you use this setting, standard cells near the right side of the row might need to rely
on tap cells inside the macro or blockage to satisfy the tap distance rule.
-left_boundary_extra_tap by_rule | must_insert | no_insert
Specifies the density adjustment of the tap cell array.
Valid values for this option are
•
by_rule (the default)
If the left edge of a row adjacent to the design's boundary is more than the minimum
tap distance from the closest tap cell on the same row, the tool inserts an extra tap
cell at the minimum tap distance from the left edge. Note that the minimum tap
distance is half of the spacing specified by the -distance option.
•
This setting might insert an extra tap cell, but always ensures that the minimum tap
distance rule is not violated.
•
must_insert
If there is no tap cell within the minimum tap distance from the left row edge, the tool
inserts an extra tap cell at the minimum tap distance from the left edge.
•
If there is a tap cell within the minimum tap distance from the left row edge, the tool
inserts an extra tap cell exactly at the left edge.
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no_insert The tool never inserts an extra tap cell at the left edge of the row. When
you use this setting, standard cells near the left side of the row might need to rely on
tap cells outside the design's boundary to satisfy the tap distance rule.
-right_boundary_extra_tap by_rule | must_insert | no_insert
Specifies the density adjustment of the tap cell array.
Valid values for this option are
•
by_rule (the default)
If the right edge of a row adjacent to the design's boundary is more than the minimum
tap distance from the closest tap cell on the same row, the tool inserts an extra tap
cell at the minimum tap distance from the right edge. Note that the minimum tap
distance is half of the spacing specified by the -distance option.
•
This setting might insert an extra tap cell, but always ensures that the minimum tap
distance rule is not violated.
•
must_insert
If there is no tap cell within the minimum tap distance from the right row edge, the tool
inserts an extra tap cell at the minimum tap distance from the right edge.
•
If there is a tap cell within the minimum tap distance from the right row edge, the tool
inserts an extra tap cell exactly at the right edge.
•
no_insert The tool never inserts an extra tap cell at the right edge of the row. When
you use this setting, standard cells near the right side of the row might need to rely
on tap cells outside the design's boundary to satisfy the tap distance rule.
-ignore_soft_blockage true | false
Controls whether soft blockages are ignored during tap cell insertion.
The default is false.
-at_distance_only true | false
Specifies the density adjustment of the tap cell array.
By default (false), extra tap cells can be inserted at locations other than the specified
distance, distance/2, or distance/4 (stagger mode).
When this option is set to true, the tool inserts tap cells only at the specified distance,
distance/2, or distance/4 (stagger mode). This could cause DRC violations.
This option is effective only when the one or more of the following options are set to
by_rule: -left_macro_blockage_extra_tap, -right_macro_blockage_extra_tap,
-left_boundary_extra_tap, and -right_boundary_extra_tap.
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-skip_fixed_cells true | false | tap
Controls whether existing fixed cells are treated as blockages.
When this option is true (the default), existing fixed cells are treated like blockages and
tap cells are not placed on top of fixed cells. Extra tap cells might be placed next to fixed
cells, using the same rules as those applied to blockages.
When this option is set to false, tap cell insertion ignores existing fixed cells and might
cause overlaps by placing tap cells on top of fixed cells. This setting cannot be used with
the -no_1x option.
When this option is set to tap, the tool does not place a tap cell if the location is occupied
by a fixed standard cell. The result is similar to setting this option to false, except that
the tool does not place a tap cell that would cause an overlap.
-respect_keepout
Prevents the placement of tap cells inside the keepout margins around macro cells.
By default, the tool can place tap cells inside the keepout margins.
-remove_redundant_tap_cells
Runs a clean-up operation after placing the well tap cells to remove tap cells with the
specified master cell name that are not strictly necessary to meet the tap distance for the
normal pattern.
The clean-up operation removes redundant tap cells regardless of whether they were
placed during the same command or earlier in the design process.
-no_1x
Does not to allow one-unit-tile fillers in the design. When you specify this option, tap cells
are not placed at locations that would cause one-unit-tile gaps between a tap cell and
fixed cells, macros, blockages, and the chip boundary. The no one-unit-tile spacing rule
takes precedence over all other tap rules. The tool first places tap cells and then checks
for one-unit-tile gaps. Tap cells that cause single one-unit-tile gaps are either moved (to
the left or right) to the next legal location or removed if no legal location is found. Tap
cells that do not cause one-unit-tile gaps are not moved.
Setting this option might cause tap distance and pattern violations. You need to specify
a tighter tap distance to prevent these violations.
This option cannot be used with the -skip_fixed_cells false option.
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DESCRIPTION
This command adds tap cells to the design, forming a two-dimensional array structure. A tap
cell is a special nonlogic cell with a well tie, substrate tie, or both. Tap cells are typically used
when most or all standard cell in the library contain no substrate or well taps. The design
rules typically specify a distance limit from every transistor of a standard cell to a well or
substrate tie.
This command is used to insert tap cells before global placement so that all standard cells
that are subsequently placed can satisfy the distance limit because of the inserted tap cells.
You should specify the tap distance and offset based on your specific design rule's distance
limit. The command has no knowledge of the design rule's distance limit. A visual check is
recommended after running this command to ensure that all standard cell placeable areas
are properly protected by tap cells. You can select several tap cell placement patterns.
The command can connect a substrate or well port of a tap cell to a specified net. It can also
connect a power or ground port of the tap cells to a specified power or ground net.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates a tap cell array in the voltage areas whose names start with
V. The tap cell array contains instances of the Cell1 cell in the normal pattern. The distance
between tap cells is 30 microns. Tap cells are not placed under preroutes on the M1 and M2
metal layers.
prompt> add_tap_cell_array -master_cell_name Cell1 \
-distance 30 -pattern normal \
-voltage_area [get_voltage_areas "V*"] \
-no_tap_cell_under_layers {M1 M2}
SEE ALSO
insert_tap_cells_by_rules(2)
set_keepout_margin(2)
add_tap_cell_array
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add_to_collection
Adds objects to a collection, resulting in a new collection. The base collection remains
unchanged.
SYNTAX
collection add_to_collection
[-unique]
collection1
object_spec
Data Types
collection1
object_spec
collection
list
ARGUMENTS
-unique
Indicates that duplicate objects are to be removed from the resulting collection. By
default, duplicate objects are not removed.
collection1
Specifies the base collection to which objects are to be added. This collection is copied
to the result collection, and objects matching object_spec are added to the result
collection. The collection1 option can be the empty collection (empty string), subject to
some constraints, as explained in the DESCRIPTION section.
object_spec
Specifies a list of named objects or collections to add.
If the base collection is heterogeneous, only collections can be added to it.
If the base collection is homogeneous, the object class of each element in this list must
be the same as in the base collection. If it is not the same class, it is ignored. From
heterogeneous collections in the object_spec, only objects of the same class of the base
collection are added. If the name matches an existing collection, the collection is used.
Otherwise, the objects are searched for in the database using the object class of the
base collection.
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The object_spec has some special rules when the base collection is empty, as explained
in the DESCRIPTION section.
DESCRIPTION
The add_to_collection command allows you to add elements to a collection. The result is
a new collection representing the objects in the object_spec added to the objects in the base
collection.
Elements that exist in both the base collection and the object_spec, are duplicated in the
resulting collection. Duplicates are not removed unless you use the -unique option. If the
object_spec is empty, the result is a copy of the base collection.
If the base collection is homogeneous, the command searches in the database for any
elements of the object_spec that are not collections, using the object class of the base
collection. If the base collection is heterogeneous, all implicit elements of the object_spec
are ignored.
When the collection1 argument is the empty collection, some special rules apply to the
object_spec. If the object_spec is non-empty, there must be at least one homogeneous
collection somewhere in the object_spec list (its position in the list does not matter). The first
homogeneous collection in the object_spec list becomes the base collection and sets the
object class for the function. The examples show the different errors and warnings that can
be generated.
The append_to_collection command has similar semantics as the add_to_collection
command; however, the append_to_collection command can be much more efficient in
some cases. For more information about the command, see the man page.
For background on collections and querying of objects, see the collections man page.
EXAMPLES
The following example from PrimeTime uses the get_ports command to get all of the ports
beginning with 'mode' and then adds the "CLOCK" port.
prompt> set xports [get_ports mode*]
{mode[0] mode[1] mode[2]}
prompt> add_to_collection $xports [get_ports CLOCK]
{mode[0] mode[1] mode[2] CLOCK}
The following example from PrimeTime adds the cell u1 to a collection containing the
SCANOUT port.
prompt> set so [get_ports SCANOUT]
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{SCANOUT}
prompt> set u1 [get_cells u1]
{u1}
prompt> set het [add_to_collection $so $u1]
{u1}
prompt> query_objects -verbose $het
{port:SCANOUT cell:u1}
The following examples show how the add_to_collection command behaves when the
base collection is empty. Adding two empty collections yields the empty collection. Adding
an implicit list of only strings or heterogeneous collections to the empty collection generates
an error message, because no homogeneous collections are present in the object_spec list.
Finally, as long as one homogeneous collection is present in the object_spec list, the
command succeeds, even though a warning message is generated. The example uses the
variable settings from the previous example.
prompt> sizeof_collection [add_to_collection "" ""]
0
prompt> set A [add_to_collection "" [list a $het c]]
Error: At least one homogeneous collection required for argument
'object_spec'
to add_to_collection when the 'collection' argument is empty
(SEL-014)
prompt> add_to_collection "" [list a $het $sp]]
Warning: Ignored all implicit elements in argument 'object_spec'
to add_to_collection because the class of the base collection
could not be determined (SEL-015)
{SCANOUT u1 SCANOUT}
SEE ALSO
append_to_collection(2)
collections(2)
query_objects(2)
remove_from_collection(2)
sizeof_collection(2)
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add_to_rp_group
Adds a cell, hierarchical group, or keepout to an existing relative placement group.
SYNTAX for Leaf Cells
status add_to_rp_group
rp_groups
-leaf cell_names
[-column integer]
[-row integer]
[-pin_align_name pin_name]
[-orientation direction]
[-alignment bottom-left | bottom-right]
[-num_rows integer]
[-num_columns integer]
[-free_placement]
Data Types
rp_groups
cell_names
pin_name
direction
list or collection
cells
string
list of strings
SYNTAX for Hierarchical Groups
status add_to_rp_group
rp_groups
-hierarchy group_name
[-instance instance_name]
[-column integer]
[-row integer]
[-orientation direction]
[-alignment bottom-left | bottom-right]
Data Types
group_name
instance_name
add_to_rp_group
list or collection
cell
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SYNTAX for Keepouts
status add_to_rp_group
rp_groups
-keepout keepout_name
[-column integer]
[-row integer]
[-width integer]
[-height integer]
[-type hard | soft | space]
Data Types
keepout_name
string
ARGUMENTS
rp_groups
Specifies the relative placement groups in which to add an item. The groups must all be
in the same design.
-leaf cell_names
Specifies the name of a cell to add to the relative placement groups in rp_groups. The
specified cell must be in the design that contains the relative placement groups in
rp_groups. Multiple cells are accepted when the -free_placement option is specified.
-column integer
Specifies the column position in which to add the item. If you do not specify the column
position, the default is zero.
-row integer
Specifies the row position in which to add the item. If you do not specify the row position,
the default is zero.
-pin_align_name pin_name
Specifies the name of the pin to use for pin alignment of this cell with other cells in a
group. This overrides the default pin name specified for the relative placement group into
which it is being added. This option can only be used when adding a leaf cell with the
-leaf option.
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-orientation direction
Specifies the placement orientation of the cell or relative placement group being added.
The option functions differently for cells from for relative placement groups. For cells,
specify the orientation with respect to the group to which the cell is being added. You can
specify a list of possible orientations, and the tool chooses the first legal orientation for
the cell. For relative placement groups, the orientation you specify overrides any group
orientation that was specified.
You can specify the direction using DEF syntax:
DEF syntax:
N, W,
S,
E,
FN,
FW,
FS,
FE
This option can only be used to add a leaf cell with the -leaf option or hierarchical
instance with the -hierarchy and -instance options.
-alignment bottom-left | bottom-right
Specifies the alignment to use when placing the cell or group with respect to its parent
group.
If you do not specify this option, IC Compiler uses the alignment method defined for the
parent group. If a relative placement group has the -compress option set, and you add
an element in that group with the -alignment bottom-right option, then the alignment
type of that element is ignored.
-num_rows integer
Specifies the number of rows to which you add the leaf cell. You can specify multiple
rows, ranging from 1 to 255. The default is 1 if you do not specify this option.
-num_columns integer
Specifies the number of columns to which you add the leaf cell. You can specify multiple
columns, ranging from 1 to 255. The default is 1 if you do not specify this option. You
cannot use the bottom-right and bottom-pin alignment settings for a leaf cell that
occupies multiple columns.
-free_placement
Specifies that the cells being provided using -leaf option must be placed randomly, that
is, similar to the cells of a bound. These cells can be added in multiple locations using
the -num_rows and -num_columns options. The width and height of the placement
area is automatically calculated for free placement cells placed inside relative placement
group. You might need to specify the -width option when free placement cells are being
added to boundary columns and the -height option when cells are being added to
boundary rows. The cell being added should not belong to any other bound.
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-hierarchy group_name
Specifies the relative placement group to be added hierarchically to the relative
placement groups in rp_groups.
-instance instance_name
Specifies the hierarchical cell in which to instantiate the relative placement group
specified with the -hierarchy option. The cell must be an instance of the reference
design that contains the relative placement group specified with -hierarchy and must be
in the design containing the relative placement groups specified in rp_groups. This
option can be used only when adding a relative placement group with the -hierarchy
option.
-keepout keepout_name
Specifies the name of the keepout to be added to the relative placement groups in
rp_groups. Although the keepout is not a design object, you name the keepout to refer
to it after it is created.
-width integer
Specifies the width of the keepout being added when used with -keepout. Unit for
keepout width is the width of the site row for a particular library. If you do not specify the
width, the keepout defaults to the width of the column into which the keepout is being
added.
It also specifies the width of the placement area for multiple cells being added with the
-free_placement option. The unit is the width of one site of site row.
-height integer
Specifies the height of the keepout being added when used with the -keepout option.
Unit for keepout height is the height of the site row for a particular library. If you do not
specify the height, the default value is height of the row of relative placement group to
which the keepout is added.
It also specifies the height of the placement area for multiple cells being added with the
-free_placement option. The unit is the height of the site row.
-type hard | soft | space
Specifies whether a keepout is hard, soft, or space.
•
A hard keepout keeps everything out of a location during legalization. This is the
default.
•
A soft keepout allows non-relative-placement cells to come into its location during
the legalization stage.
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A space keepout allows non-relative-placement cells to come into its location during
placement.
DESCRIPTION
This command adds an item to the specified relative placement groups. The relative
placement groups must have been previously defined by using the create_rp_group
command. The item can be either a leaf cell, a relative placement group, or a keepout. The
item is placed in a particular lattice position of the group as specified by a row and column.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses add_to_rp_group to add a cell to an existing relative
placement group and then adds that group hierarchically to another existing group:
prompt> get_rp_groups ripple::grp_ripple
{ripple::grp_ripple}
prompt> add_to_rp_group ripple::grp_ripple -leaf carry_in_1
{ripple::grp_ripple}
prompt> add_to_rp_group example3::top_group -hier grp_ripple -instance U2
{example3::top_group}
prompt> add_to_rp_group example3::top_group -leaf { U1 U2 U3 U4 U5 } \
-row 0 -column 1 -num_rows 2 -num_columns 3 -free_placement
{example3::top_group}
SEE ALSO
create_rp_group(2)
remove_rp_groups(2)
write_rp_groups(2)
add_to_rp_group
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adjust_fp_floorplan
Adjusts an existing floorplan.
SYNTAX
status adjust_fp_floorplan
[-bottom_io2core distance]
[-core_aspect_ratio ratio]
[-core_height height]
[-core_utilization utilization]
[-core_width width]
[-die_height height]
[-die_origin {x y}]
[-die_width width]
[-fc_in_core number | -fc_periphery number]
[-flip_first_row true | false]
[-left_io2core distance]
[-maintain_placement]
[-min_pad_height true | false]
[-no_double_back true | false]
[-number_rows rows]
[-remove_filler_io]
[-right_io2core distance]
[-row_core_ratio ratio]
[-sm_utilization utilization]
[-start_first_row true | false]
[-top_io2core distance]
[-use_vertical_row true | false]
Data Types
distance
ratio
height
utilization
width
x
y
number
rows
Chapter 1:
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float
float
float
float
float
float
float
float
float
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ARGUMENTS
-bottom_io2core distance
Specifies the distance in microns from the core bottom edge to top edge of the largest
bottom pad. If you specify the -min_pad_height true option, the distance is measured
from the smallest bottom pad to the core.
-core_aspect_ratio ratio
Specifies the core aspect ratio. The core aspect ratio is the core height divided by the
core width. If you specify this option, the core is resized to achieve this aspect ratio while
maintaining the current placement area.
-core_height height
Specifies the core height in microns. The core is resized to achieve the specified height
while maintaining the current core width.
This option is usually combined with -core_width or -number_rows (for vertical rows)
options.
-core_utilization utilization
Specifies the core utilization. Core utilization is the core physical area divided by the
core placement area. The core is resized to achieve this new placement area which
maintaining the current aspect ratio.
-core_width width
Specifies the core width in microns. The core is resized to achieve the specified width
while maintaining the current core height.
This option is usually combined with the -core_height or -number_rows (for horizontal
rows) options.
-die_height height
Specifies the die height in microns. The die is resized to achieve the specified height
while maintaining the current die width.
This option is usually combined with -die_width.
-die_origin {x y}
Specifies the die origin. By default, the origin is at (0,0).
-die_width width
Specifies the die width in microns. The die is resized to achieve the specified width while
maintaining the current die height.
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This option is usually combined with -die_height option.
-fc_in_core number
Specifies the number of flip-chip pads or drivers inside the core. Use the string "all" to
capture all flip-chip pads or drivers inside the core.
All flip chip pads in the core affect the utilization calculations.
This option cannot be combined with the -fc_periphery option.
-fc_periphery number
Specifies the number of flip-chip pads or drivers in the periphery, outside the core area.
Use the string "all" to capture all flip-chip pads or drivers in the periphery.
Any flip-chip pads or drivers not in the periphery are assumed to be in the core and affect
the utilization calculations.
This option cannot be combined with the -fc_in_core option.
-flip_first_row true | false
Specifies that the first cell row is flipped. By default, the first row is not flipped.
-left_io2core distance
Specifies the distance in microns from the core left edge to the right edge of the largest
pad on the left side. If you specify the -min_pad_height true option, the distance is
measured from the smallest pad on the left side to the core.
-maintain_placement
Keeps the current standard cell and hard macro placement inside the core. By default,
the command moves standard cells and hard macros outside the core.
-min_pad_height true | false
Specifies whether the core to pad distances are to the smallest pad on the
corresponding side instead of the largest pad. If you do not specify this option, the tool
calculates distances to the largest pad.
-no_double_back true | false
Specifies that cell rows are not double backed. Double backed rows only have gaps
between each flipped and non-flipped row pair. Non-double backed rows have gaps
between each row.
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-number_rows rows
Specifies the required number of rows. The core is resized to achieve the specified
number of rows. The current core width is maintained for horizontal rows. The current
core height is maintained for vertical rows.
-remove_filler_io
Removes filler I/O pads.
-right_io2core distance
Specifies the distance in microns from the core right edge to the left edge of the largest
right pad. If you specify the -min_pad_height true option, the distance is measured
from the smallest pad on the right to the core.
-row_core_ratio ratio
Specifies row core ratio. The ratio is the ratio of row height to core height for horizontal
rows, or row width to core width for vertical rows.
-sm_utilization utilization
Specifies individual soft macro utilizations as a list of strings. Each string in the list uses
the following syntax.
sm_name sm_utilization [fc_area_factor]
You can supply the optional flip chip pad and driver area factor only if the design
contains flip chip pads and drivers.
-start_first_row true | false
Specifies that cell rows begin with a complete row pair containing flipped and non-flipped
rows.
-top_io2core distance
Specifies the distance in microns from core top edge to bottom edge of the largest top
pad. If you specify the -min_pad_height true option, the distance is measured from the
smallest top pad to the core.
-use_vertical_row true | false
Specifies that the command places cell rows vertically.
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DESCRIPTION
This command modifies the current die and core sizes by changing one or more values
while maintaining as much of the current settings as closely possible to their original
settings.
You can change the following characteristics by using the specified option:
. absolute die size (-die_width or -die_height)
. absolute core size (-core_width or -core_height)
. core size based on number of rows (-number_rows, -core_width,
or -core_height depending on row direction
. core utilization (-core_utilization or -core_aspect_ratio)
. row geometry (direction, double_back, start_first_row,
flip_first_row,
row_core_ratio)
. core to pads distances (-bottom_io2core, -left_io2core,
-right_io2core, and -top_io2core)
. die origin (-die_origin)
. core to pad distance based on minimum pad height (-min_pad_height)
For all core resizes the die is resized to maintain the core to pad spacing. For all die resizes
the core is resized to maintain the core to pad spacing.
By default, changing the die or core size invalidates the placement. As a result, all standard
cells and macros are unplaced and moved out of the core area. Use the -keep_placement
option to retain the current cell and macro placement.
After placement blockages and filler pads might be invalid after resizing the core. The tool
automatically removes blockages. You can remove filler pads by using the
-remove_filler_io option.
By default, the total physical area of all standard cells and hard macros is used to calculate
the placement area. If the design contains soft macros or flip-chip pads and drivers, you can
adjust the utilization calculation to also consider these cells.
You can specify the utilization of each soft macro. This increases the physical size of the soft
macro from just the total physical size of all its child standard cells and hard macros to the
physical size divided by the utilization. For example, a utilization of 0.5 doubles the physical
area of the soft macro.
Some flip-chip drivers and pads might be within the core area, while others are outside the
core area. Flip-chip drivers and pads in the core decrease the placement area and must be
taken into account in the utilization calculation. You can set the number by specifying either
the number within the core or the number within the periphery. You can use the string "all"
to specify all flip-chip pads and drivers. By default, the tool considers that all flip-chip drivers
and pads are in the core.
A number of flip-chip pads and drivers might overlap soft macros. This number is
automatically estimated for each soft macro based on the soft macro size and number of
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flip-chip drivers and pads in the core. You can apply an extra scale factor to the area to
adjust the number.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following command resize the core to 1000 x 1000 microns and maintains the core to
pad spacing.
prompt> adjust_fp_floorplan -core_width 1000 -core_height 1000
The following command changes rows to vertical orientation with a row core ratio of 0.9.
prompt> adjust_fp_floorplan -use_vertical_row true -row_core_ratio 0.9
The following example changes the core utilization to 0.9 with soft macro alu1 utilization of
0.5.
prompt> adjust_fp_floorplan -core_util 0.9 -sm_utilization { "alu1 0.5" }
SEE ALSO
adjust_fp_floorplan
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adjust_fp_io_placement
Adjusts I/O pad placement.
SYNTAX
int adjust_fp_io_placement
[-side l | r | t | b]
[-spacing spacing]
[-pitch pitch]
[-offset offset]
[-undo]
[list_of_IO_cells]
Data Types
spacing
pitch
offset
list_of_IO_cells
float
float
float
list
ARGUMENTS
-side l | r | t | b
Indicates the of the chip where I/O cells are to be adjusted. This option is mutually
exclusive with the list_of_IO_cells argument.
-spacing spacing
Specifies the spacing in microns between adjacent I/Os. This option is mutually
exclusive with -pitch.
-pitch pitch
Specifies the distance from the center of an I/O cell to the center of the adjacent I/O cell
in microns. This option is mutually exclusive with -spacing.
-offset offset
The distance (in microns) between the bottom-most (for left and right I/Os) or the
left-most (for top and bottom I/Os) point of all the adjusted I/O cells and the bottom edge
or left edge of the chip. If no -offset is specified, the command packs the I/O cells in the
center of the appropriate side.
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-undo
Undoes the movements made by the previous adjust_fp_io_placement command.
This option is mutually exclusive with all other options. Only one level of undo is
supported.
list_of_IO_cells
The I/O cells whose placement are to be adjusted. All the selected I/Os must be on the
same side of the chip. This is mutually exclusive with the -side option.
DESCRIPTION
This command adjusts the spacing and location of I/O cells. The adjust_fp_io_placement
command moves cells only with the I/O pad type. The I/O cells that are moved are marked
as FIXED. Any cell-to-cell overlaps for I/O cells after the adjustment are reported.
EXAMPLES
The following command adjusts the I/O placement on the left side of the chip with a spacing
of 1 micron between adjacent I/Os.
prompt> adjust_fp_io_placement -side l -spacing 1
SEE ALSO
set_pad_physical_constraints(2)
adjust_fp_io_placement
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adjust_premesh_connection
Connects the load pins in the specified clock tree or subtree either as mesh loads or as part
of the premesh tree. If you specify the -premesh option, it balances the first-level loads of the
premesh tree.
SYNTAX
status adjust_premesh_connection
-root root_name
[-premesh | -exclude_pins list_of_pins]
[-operating_condition min | max | min_max]
Data Types
root_name
list_of_pins
net, port, or pin
list
ARGUMENTS
-root root_name
Specifies the name of the root of the clock tree or subtree. You can specify a clock net,
clock port, or pin that drives a clock tree or subtree.
If you specify a clock net, the command considers all the load pins of that net. If you
specify a pin or a port, the command considers the load pins in the fanout of the
specified port or pin. A pin is a load pin if it is either a macro pin or has a nonzero phase
delay.
This is a required option.
-premesh
Balances the first-level load pins of the specified clock tree or subtree with the isolation
buffers that drive the load pins below the mesh.
Use this option only after running the analyze_subcircuit command.
This option and the -exclude_pins option are mutually exclusive.
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-exclude_pins list_of_pins
Excludes the specified pins from consideration. The specified pins are connected above
the mesh. By default, all load pins in the fanout of the specified clock root are
considered.
This option and the -premesh option are mutually exclusive.
-operating_condition min | max | min_max
Specifies the operating condition to be used by the clock tree synthesis engine. If you do
not specify this option, the maximum operating condition is used.
DESCRIPTION
This command either adjusts the specified load pins (default behavior) or balances the
first-level loads of the specified clock tree or subtree (-premesh option).
In default mode, the set of load pins is determined by removing the pins specified in the
-exclude_pins option from the set of pins derived from the -root option. The command
connects these load pins either below the mesh or to the premesh tree. If the load pin is a
flip-flop clock pin, drives a flip-flop clock pin, or is a macro pin with a large capacitance, the
pin is connected below the mesh. If the load pin has a nonzero phase delay, the phase delay
is compared to the maximum delay of all branches associated with flip-flops. If the phase
delay is greater than the maximum branch delay, the pin is connected to the premesh tree.
If the clock tree has a macro pin with nonzero phase delay and split_clock_net
-isolate_float_pins is used. The command decides whether to connect the pin to the
premesh tree or below the mesh based on the capacitance value and phase delay of the pin.
If the macro pin has high capacitance value, the pin is connected below the mesh because
the mesh has high drive strength. If the pin has nominal capacitance value and nonzero
phase delay, the pin is connected to the premesh tree. If you need to set the phase delay of
the macro pin, use the set_clock_tree_exceptions command.
When connecting load pins after the mesh, the command inserts an isolation buffer after the
specified clock root and inserts the load pins after the isolation buffer, so that the clock root
drives the isolation buffer and the isolation buffer drives the load pins below the mesh.
When connecting load pins to the premesh tree, the command connects the pins to the
specified clock root.
In premesh mode, the command uses the compile_clock_tree and optimize_clock_tree
commands to balance the first-level load pins of the specified clock tree.
adjust_premesh_connection
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EXAMPLE
The following command analyzes the load pins connected to the clknet1 net and either
connects them to the premesh tree or below the mesh.
prompt> adjust_premesh_connection -root clknet1
SEE ALSO
optimize_clock_tree(2)
split_clock_net(2)
analyze_subcircuit(2)
Chapter 1:
adjust_premesh_connection
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alias
Creates a pseudo-command that expands to one or more words, or lists current alias
definitions.
SYNTAX
string alias
[name]
[def]
Data Types
name
def
string
string
ARGUMENTS
name
Specifies a name of the alias to define or display. The name must begin with a letter, and
can contain letters, underscores, and numbers.
def
Expands the alias. That is, the replacement text for the alias name.
DESCRIPTION
The alias command defines or displays command aliases. With no arguments, the alias
command displays all currently defined aliases and their expansions. With a single
argument, the alias command displays the expansion for the given alias name. With more
than one argument, an alias is created that is named by the first argument and expanding to
the remaining arguments.
You cannot create an alias using the name of any existing command or procedure. Thus,
you cannot use alias to redefine existing commands.
Aliases can refer to other aliases.
Aliases are only expanded when they are the first word in a command.
alias
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EXAMPLES
Although commands can be abbreviated, sometimes there is a conflict with another
command. The following example shows how to use alias to get around the conflict:
prompt> alias q quit
The following example shows how to use alias to create a shortcut for commonly-used
command invocations:
prompt> alias include {source -echo -verbose}
prompt> alias rt100 {report_timing -max_paths 100}
After the previous commands, the command include script.tcl is replaced with source
-echo -verbose script.tcl before the command is interpreted.
The following examples show how to display aliases using alias. Note that when displaying
all aliases, they are in alphabetical order.
prompt> alias rt100
rt100report_timing -max_paths 100
prompt> alias
includesource -echo -verbose
qquit
rt100report_timing -max_paths 100
SEE ALSO
unalias(2)
Chapter 1:
alias
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align_fp_pins
Aligns a set of soft macro, black box, or plan group pins with a set of reference pin objects.
These can be terminals or pins on hard macros, I/O pad cells, standard cells, internal child
hard macros, or another soft macro, black box or plan group.
SYNTAX
status align_fp_pins
[-align_with_child_hm_pins]
[-change_layer_width]
[-direction {center | left | right | top | bottom}]
[-fixed]
[-order_type {low_to_high | high_to_low | net_connection}]
[-propagate_single_pins]
[-reference object]
objects
Data Types
object
objects
collection of one item
collection
ARGUMENTS
-align_with_child_hm_pins
Aligns pins with child hard macro pins. The reference pins are hard macro pins inside a
soft macro.
-change_layer_width
Changes pin metal layer to match the reference pin. The final width of the aligned pin is
the default width of the target layer, not the width of the reference pin. By default, the
aligned pin retains its original layer and width.
-direction {center | left | right | top | bottom}
Specifies the direction for pin alignment.
The center keyword aligns pins to the horizontal or vertical central axis passing through
the bounding box of the reference pin object. If the pin to be aligned is located on a
horizontal edge, the center of the aligned pin is aligned to the vertical central axis. The
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horizontal central axis is used instead if the aligned pin sits on a vertical edge. By
default, center alignment is used to align pins.
If the reference pin object is a terminal, or a pin on an I/O cell or standard cell, a central
axis (horizontal or vertical) of the reference pin object is used regardless of the
-direction value you specify.
The left, right, top, and bottom keywords indicate the reference pin edges to be used
as the axis of alignment. For example, if the reference pin sits on the bottom edge of a
hard macro and you specify the -direction left option, the left edge of the pin to be
aligned is made flush with the left edge of the reference pin.
The difference in placement results between the -direction left option and the
-direction right option depends on the width of the reference pin and aligned pin. The
results are different only if the reference pin and the aligned pin have different widths.
Furthermore, the central axis (horizontal or vertical) of the reference pin is used if the
-direction option value is incompatible with the location of the aligned pin. Using the
previous example, the center of the aligned pin is aligned with the vertical central axis of
the reference pin if you specify either the -direction top option or the -direction bottom
option.
-fixed
Fixes pins in place after alignment. By default pins are marked "movable" after
alignment.
-order_type {low_to_high | high_to_low | net_connection}
Specifies the method used to align pins with reference pins. You can specify the
following values: net_connection, low_to_high, and high_to_low. By default, the
command uses the net_connection keyword.
The net_connection keyword specifies that an aligned pin is moved into alignment with
the reference pin that is logically connected to it by a net. The command uses net
connectivity to automatically determine the reference pins. In many cases, this can
eliminate the need to specify the reference pins in the argument collection. For example,
if the pin to be aligned is connected to a net, and the only other connection for the net is
to another soft macro or plan group pin, then the latter pin is assumed to be the
reference pin if you provide the first (but not the second) pin in the argument collection.
If a reference pin object cannot be uniquely determined because the net connected to
the pin to be aligned is connected to multiple other objects, a multilevel priority scheme
determines the reference pin object:
1.
Pin in the argument list
2.Pin on the reference object specified with -reference
3.Fixed soft macro, black box or plan group pin
Chapter 1:
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4.Other soft macro, black box or plan group pin
5.Hard macro pin
6.I/O pad cell pin
7.Terminal
8.Other standard cell pin
When multiple pin objects exist within the same level, preference is given to the closest pin
object. If the net is not connected to any other soft macro, black box or plan groups but is
connected to two hard macro pins and an I/O pad pin, the reference pin is assumed to be
the hard macro pin closer to the pin to be aligned. However, the I/O pad pin is used as the
reference if you explicitly include the I/O pad pin in the argument collection or specifies the
I/O pad cell as the argument for the -reference argument.
The low_to_high keyword aligns pins in pairs starting from pins that have the lowest
original horizontal coordinate. For example, in the case where alignment is done on a
horizontal edge with four reference pins and three pins on the other macro to be aligned, the
fourth reference pin with the largest horizontal coordinate is not used in the alignment. Pins
on vertical edges are placed according to their vertical coordinates.
The high_to_low keyword aligns pins in pairs starting from pins that have the highest
original horizontal coordinate. In a case where alignment is done on a horizontal edge with
four reference pins and three pins on the other macro to be aligned, the fourth reference pin
with the smallest horizontal coordinate is not used in the alignment.
If the number of reference and aligned pins is the same, there is no difference in results
between the -order_type low_to_high option and the -order_type high_to_low option.
Note that the tool preserves the original pin order of the aligned pins when using either
option. The aligned pin with the lowest original coordinate still has the lowest coordinate
among the aligned pins.
NOTE: This option is not used if you use the -align_with_child_hm_pins option, or if the
reference pin object is a terminal or a pin of an I/O cell or standard cell. In these cases the
net_connection keyword is the only available alignment method.
-propagate_single_pins
Corrects single-pin violations in abutted designs if possible. When this option is used,
the objects list must contain pins only, or an empty object list. If the object list is empty
(the only option in which an empty object list is allowed) then all pins are checked for
single pin violation and fixed if possible.
The -propagate_single_pins option is mutually exclusive with all other options. This
option is intended only to be used in an abutted design. When you use this option, the
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command identifies single-pin violations in an abutted design, and checks the abutted
soft macro or plan group and adds a pin to that abutted soft macro or plan group if a
logical connection exists to that soft macro or plan group instance. The command also
checks if single-pin violations exist which result from misaligned pins along a macro
edge. If violations exist, the command moves the pins on non-MIM instances to correct
the single-pin violation.
When this option is used, the "objects" argument should be a collection of pins.
As suggested above, in the context of single pin violations resulting from mis-aligned
pins, where one of the blocks is a MIM instance and the other block is not a MIM
instance, the pin on the MIM instance acts as a reference pin, and the other pin acts as
a slave pin that gets moved to align with the MIM pin. The moved non-reference pin
inherits the layer and width and height properties of the reference pin.
In the context of single pin violations on abutted edges of 2 MIM instances, the
command will not attempt to modify either MIM pin placement because this can cause
new violations on other instances of either MIM.
-reference object
Specifies a reference object. The object is used to resolve ambiguity in cases where the
command is unable to determine the reference pin. For example, a specified net
connected to a soft macro pin to be aligned is connected to more than one hard macro.
In this case the hard macro whose pin is to be used as a reference can be used as the
argument to this option. You can omit this option if the reference macro can be uniquely
determined from the arguments supplied without resorting to the multilevel reference pin
selection process. See the -order_type net_connection argument description for
details.
Note that the command uses the object provided by this option only as a source of
information of last resort. Information provided by this option is silently ignored if the
command can uniquely determine the reference pin or terminal, whether or not the
argument given is relevant or specified incorrectly. The argument can be any one of the
following: soft macro, black box, plan group, hard macro, I/O pad cell, terminal, or
standard cell.
objects
Specifies the collection of pins, nets, or reference terminals.
At a minimum, the collection consists of the set of soft macro, black box or plan group
pins to be aligned. Reference pins or terminals can be added if they are needed to
resolve any ambiguity regarding designation of reference pins. If you specify the
-order_type net_connection option, or do not specify -order_type, the command
attempts to determine the reference pins via net connection. See the -order_type
argument description for details. You must supply reference pins or terminals as
arguments only when absolutely necessary, or when using the -order_type
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low_to_high or the -order_type high_to_low option, since a net connection is not
used as the basis for alignment and reference pins can not be determined from net
connectivities.
Net arguments are also acceptable but they can not be mixed with pins or reference
terminals; the collection should be a homogeneous set of nets. Also note that any
terminal supplied is used as a reference. This command does NOT align terminals;
terminals are considered fixed.
DESCRIPTION
The align_fp_pins command aligns a set of unfixed soft macro, black box or plan group
pins with a set of reference terminals or pins on soft macros, hard macros, plan groups, I/O
pad cells, or standard cells. Fixed pins are not aligned.
Aligned pins are automatically snapped to the closest current snap type. Use the
get_object_snap_type -type port_shape command to report the current snap type. The
default snap type is wiretrack. For this reason, pins might not be perfectly aligned if the
reference pins and aligned pins are of different sizes, or if they are on different layers and
the wiretrack grids of these layers are not aligned. To create a perfect alignment, set the
current snap type to the minimum grid by using the set_object_snap_type -type
port_shape -snap litho command. Perfect alignment is impossible if the reference pins are
not snapped to the minimum grid.
NOTE: The command aligns pins even if the alignment creates a short between the aligned
pin and another pin. A warning is issued by the command if a short is created. No other pin
position legality check is performed.
Note that aligning terminals or off-edge pins is not supported.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
Suppose "mac1" and "mac2" are to soft macros (or black boxes, plan groups), the following
example aligns the specified pins using "mac1" as the reference.
prompt> align_fp_pins -reference mac1 \
[get_pins "mac1/A mac1/B mac1/C mac2/A mac2/B mac2/C"]
align_fp_pins
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SEE ALSO
set_object_snap_type(2)
get_object_snap_type(2)
Chapter 1:
align_fp_pins
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align_objects
Aligns one or more objects to an anchor object or position.
SYNTAX
status align_objects
[{-anchor object | -parent |
-to value_point_rect}]
[-side alignment_side]
[-offset float]
[-resize]
[-keep_area]
[-ignore_fixed]
objects
Data Types
alignment_side
objects
string
collection
ARGUMENTS
-anchor object
Specifies the object to which other objects are aligned.
-parent
Specifies that objects are aligned to the parent edge.
For terminals and io pads the parent object will be the die. For soft macro pins the parent
object will be the soft macro. For all other objects the parent will be the core.
-to value_point_rect
Specifies that objects are aligned to the position specified by value_point_rect.
This position can be a single value (x for left/right, y for top/bottom), a point, or a
rectangle.
-side alignment_side
Specifies the side of the object and anchor object to be aligned.
align_objects
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The valid value is one of left, right, top, bottom, hcenter, and vcenter.
The description of the valid values are as follows:
left
right
top
bottom
hcenter
vcenter
-
indicates
indicates
indicates
indicates
indicates
indicates
to
to
to
to
to
to
use
use
use
use
use
use
the
the
the
the
the
the
left side
right side
top side
bottom side
horizontal center
vertical center
The default depends on the aspect ratio (height/width) of the object's surrounding bbox.
If the aspect ratio is less than or equal to 1, then left is the default, otherwise, bottom is
the default.
-offset float
Specifies the offset from the specified anchor object's side.
The default value is 0.0.
-resize
Specifies to resize the object when aligning.
-keep_area
Specifies to keep the original object's area when resizing.
By default, the command does not keep the object's area.
-ignore_fixed
Specifies to align fixed objects as well as unfixed objects.
By default, the command does not align fixed objects.
objects
Specifies a list of objects to align.
DESCRIPTION
This command aligns a list of unfixed objects so that their left, right, top, or bottom edges are
coincident with, or at a specified offset from, an anchor object or anchor position.
The user can specify an anchor object or anchor position, or allow the command to
automatically determine the anchor object from the supplied list of objects by using the
following algorithm:
Chapter 1:
align_objects
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•
If any objects are marked as fixed then the anchor object is selected from the set of fixed
objects. The rightmost, leftmost, bottommost, or topmost fixed object for alignment of
left, right, top, and bottom, respectively.
•
If no objects are marked as fixed, then the anchor object is taken as the leftmost,
rightmost, topmost, or bottommost object for alignment of left, right, top, and bottom,
respectively.
When aligning an object, the position of the opposite edge can be retained so that the object
is resized rather than moved e.g. when left aligning the position of the right edge of the
object can be retained while the left edge is moved as normal.
The position of the other sides of the object is also retained unless you specify that the area
is to be kept, in which case the other sides are moved to achieve the original object area.
When you do not specify the -resize option, any movable object can be aligned. If you do
specify it, only resizable objects can be aligned.
The tool automatically performs snapping of the origin, bounding box, or points using global
snap settings unless you specify the -no_snap option.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example moves the currently selected objects so that their left edges are 20
units from the left edge of the core.
prompt> align_objects [get_selection] -parent -offset 20
SEE ALSO
distribute_objects(2)
expand_objects(2)
flip_objects(2)
get_object_snap_type(2)
move_objects(2)
remove_objects(2)
resize_objects(2)
rotate_objects(2)
set_object_snap_type(2)
align_objects
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all_active_scenarios
Lists the active scenarios available in memory.
SYNTAX
string all_active_scenarios
ARGUMENTS
This command has no arguments.
DESCRIPTION
This command displays all active scenarios currently in memory. This list excludes
scenarios that are inactive.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example uses the all_active_scenarios command to list the active scenarios.
prompt> create_scenario MODE1
prompt> create_scenario MODE2
prompt> create_scenario MODE3
prompt> set_active_scenarios {MODE1 MODE3}
prompt> all_active_scenarios
MODE1 MODE3
SEE ALSO
all_scenarios(2)
create_scenario(2)
current_scenario(2)
Chapter 1:
all_active_scenarios
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remove_scenario(2)
set_active_scenarios(2)
all_active_scenarios
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all_ao_cells
Returns a collection of always-on cells available in the design.
SYNTAX
collection all_ao_cells
ARGUMENTS
The all_ao_cells command has no arguments.
DESCRIPTION
The all_ao_cells command returns a collection of existing always-on cells in the design. If
the design has dual-powered marked always-on cells, they are returned by this command.
However, if the design has always-on power guides that contain regular cells, those cells are
also returned by this command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
get_always_on_logic(2)
Chapter 1:
all_ao_cells
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all_bounds_of_cell
Returns the collection of all bounds in the specified list of cells from the design.
SYNTAX
collection all_bounds_of_cell
cell_list
Data Types
cell_list
list
ARGUMENTS
cell_list
Specifies the list of all cells for which to determine the bounds. This can be a simple list
or it can be an entire collection manipulation command, enclosed in square brackets [],
that returns a collection of cells.
DESCRIPTION
This command returns the collection of all the group or move bounds of a specified cell list.
You can use wild cards, such as an asterisk (*) or question mark (?), when specifying the
input cell list.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_bounds_of_cell
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EXAMPLES
The following example shows the returned collection of all bounds of cells named cell1,
cell2, and cell3.
prompt> all_bounds_of_cell {cell1 cell2 cell3}
{cell_bound1 cell_bound2 cell_bound3}
The following example shows the returned collection of all bounds of cells in the u* cell list.
In this case, the command returns the collection specified by the get_cells command
operating on u*.
prompt> all_bounds_of_cell [get_cells u*]
{my_bound1 my_bound2}
Following example shows the returned collection of all the bounds of cells in the SBLK
subdesign. In this case, the command returns the collection specified by the get_cells
command operating on SBLK.
prompt> all_bounds_of_cell [get_cells SBLK/*]
{bound1 bound2}
SEE ALSO
create_bounds(2)
foreach_in_collection(2)
get_cells(2)
remove_bounds(2)
report_bounds(2)
sizeof_collection(2)
Chapter 1:
all_bounds_of_cell
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all_cells_in_bound
Returns the collection of all cells in the specified list of group bounds and move bounds from
the design.
SYNTAX
collection all_cells_in_bound
{bound_list}
Data Types
bound_list
list
ARGUMENTS
{bound_list}
Specifies all the lists of bounds for which to determine cells. The tool returns the
collection of the bounds.
DESCRIPTION
This command returns the collection of all the cells from the specified group and move
bounds. These bounds are created by using the create_bound command. This command
inputs a list of multiple bounds and returns a collection of cells from all of them. The tool
searches the entire design hierarchy. It returns cells from the entire design, not just from the
top level.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_cells_in_bound
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EXAMPLES
The following example shows the returned collection of all cells in the my_bound1 bound,
which was created by using the create_bound command.
prompt> all_cells_in_bound {my_bound1]
{cell1 top/cell2 top/cell4 cell10}
The following example shows the returned collection of all cells from multiple bounds given
as a list. The list is composed of my_bound1 and my_bound2.
prompt> all_cells_in_bound {my_bound1 my_bound2}
{cell1 cell2 cell3 cell4 cell5}
SEE ALSO
all_bounds_of_cell(2)
create_bounds(2)
foreach_in_collection(2)
remove_bounds(2)
report_bounds(2)
sizeof_collection(2)
Chapter 1:
all_cells_in_bound
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all_clocks
Returns a collection of all clocks in the current design.
SYNTAX
collection all_clocks
ARGUMENTS
This command has no arguments.
DESCRIPTION
Returns a collection containing all clocks in the current design. The clocks must be defined
in the design before running this command.
To create clocks, use the create_clock command. To remove clocks, use the
remove_clock command. To list detailed information about all clocks in the design, use the
report_clock command.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example applies the set_dont_touch_network command to all clocks in the
current design:
prompt> set_dont_touch_network [all_clocks]
SEE ALSO
create_clock(2)
remove_clock(2)
all_clocks
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report_clock(2)
set_dont_touch_network(2)
Chapter 1:
all_clocks
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all_connected
Returns the objects connected to a net, port, pin, net instance, or pin instance.
SYNTAX
collection all_connected
[-leaf]
object
Data Types
object
string
ARGUMENTS
-leaf
Specifies that only leaf pins are returned for a hierarchical net. For nonhierarchical nets,
there is no difference in output.
object
Specifies the object whose connections are returned. The object must be a net, port, pin,
net instance, or pin instance.
DESCRIPTION
The all_connected command returns a collection of objects connected to the specified net,
port, pin, net instance, or pin instance. A net instance is a net in the hierarchy of the design.
A pin instance is a pin on a cell in the hierarchy of a design.
If the -leaf option is used, a list of leaf pins of the net is returned.
To connect nets to ports or pins, use the connect_net command. To break connections,
use the disconnect_net command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_connected
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EXAMPLES
The following example uses all_connected to return the objects connected to MY_NET:
prompt> all_connected MY_NET
prompt> connect_net MY_NET OUT3
Connecting net 'MY_NET' to port 'OUT3'.
prompt> connect_net MY_NET U65/Z
Connecting net 'MY_NET' to pin 'U65/Z'.
prompt> all_connected MY_NET
{OUT3 U65/Z}
prompt> all_connected OUT3
{MY_NET}
prompt> all_connected U65/Z
{MY_NET}
This example uses all_connected to associate net load capacitance with the net n47, which
is connected to the pin instance C/Z:
prompt> set_load 0.147 [all_connected [get_pins U0/U1/C/Z]]
Set "load" attribute to 0.147 for net "U0/U1/n47"
SEE ALSO
all_inputs(2)
all_outputs(2)
connect_net(2)
create_net(2)
current_design(2)
disconnect_net(2)
remove_net(2)
Chapter 1:
all_connected
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all_connectivity_fanin
Reports pins, ports, or cells in the fanin of specified sinks.
SYNTAX
list all_connectivity_fanin
-to sink_list
[-startpoints_only]
[-only_cells]
[-flat]
[-levels count]
Data Types
sink_list
count
list
int
ARGUMENTS
-to sink_list
Reports a list of sink pins, ports, or nets in the design and connectivity based fanin of
each sink in the sink_list. If you specify a net, the effect is the same as listing all driver
pins on the net.
-startpoints_only
Returns only the connectivity startpoints.
-only_cells
Results in a set of all the cells in the connectivity fanin of the sink_list.
-flat
Specifies to function in the flat mode of operation. The two major modes in which
all_connectivity_fanin functions are hierarchical (default) and flat. When in hierarchical
mode, only objects from the same hierarchy level as the current sink are returned. Thus,
pins within a level of hierarchy lower than that of the sink are used for traversal but they
will not be reported.
all_connectivity_fanin
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-levels count
Stops traversal when reaching the perimeter of the search of count hops, where
counting is performed over the layers of cells that are of equidistant from the sink.
DESCRIPTION
This command reports the connectivity fanin of specified sink pins, ports, or nets in the
design. A pin is considered to be in the connectivity fanin of a sink if there is a path through
combinational logic from the pin to that sink. The fanin report stops at the clock pins of
registers (sequential cells).
NOTE: This command reports same results as all_fanin except the cases
1. false paths are not considered in this commands
2. manually created clocks are not treated as paths start points
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following examples show the connectivity fanin of a port in the design. The design
comprises three inverters in a chain named iv1, iv2, and iv3. The iv1 and iv2 inverters are
hierarchically combined in a larger cell named ii2.
prompt> all_connectivity_fanin -to tout
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
prompt>
all_connectivity_fanin -to tout -flat
{"ii2/iv1/U1/a", "ii2/iv2/U1/z", "tin", "iv3/U1/a", "ii2/iv1/U1/z",
"ii2/iv2/U1/a", "iv3/U1/z", "tout"}
SEE ALSO
all_fanin(2)
all_fanout(2)
report_transitive_fanin(2)
Chapter 1:
all_connectivity_fanin
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_connectivity_fanout
Returns a set of pins, ports, or cells in the fanout of the specified sources.
SYNTAX
list all_connectivity_fanout
-from source_list
[-endpoints_only]
[-only_cells]
[-flat]
[-levels count]
Data Types
source_list
count
list
int
ARGUMENTS
-from source_list
Specifies a list of source pins, ports, or nets in the design. The connectivity fanout of
each source in source_list is reported. If a net is specified, the effect is the same as
listing all load pins on the net.
-endpoints_only
Returns only connectivity endpoints as a result.
-only_cells
Results in a set of all cells in the connectivity fanout of the source_list, rather than a set
of pins or ports.
-flat
Specifies to function in the flat mode of operation. The two major modes in which
all_connectivity_fanout functions are hierarchical (default) and flat. When in
hierarchical mode, only objects from the same hierarchy level as the current source are
returned. Thus, pins within a level of hierarchy lower than that of the source are used for
traversal but are not reported.
all_connectivity_fanout
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-levels count
Stops traversal when reaching the perimeter of the search of count hops, where
counting is performed over the layers of cells that are of equidistant from the source.
DESCRIPTION
This command reports the connectivity fanout of specified source pins, ports, or nets in the
design. A pin is considered to be in the connectivity fanout of a sink if there is a path through
combinational logic from that source to the pin. The fanout report stops at the inputs to
registers (sequential cells).
NOTE: This command reports same results as all_fanout except the cases
1. false paths are not considered in this commands
2. manually created clocks are not treated as paths start points
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the connectivity fanout of a port in the design. The design
comprises three inverters in a chain named iv1, iv2, and iv3. The iv1 and iv2 inverters are
hierarchically combined in a larger cell named ii2.
prompt> all_connectivity_fanout -from tin
{iv3/out tout iv3/in ii2/hin ii2/hout tin}
prompt> all_connectivity_fanout -from tin -flat
{"tout", "ii2/iv2/U1/z", "ii2/iv1/U1/a", "iv3/U1/z", "iv3/U1/a",
"ii2/iv2/U1/a", "ii2/iv1/U1/z", "tin"}
prompt> all_connectivity_fanout -from tin -levels 1 -only_cells
{iv3 ii2}
SEE ALSO
all_fanout(2)
all_fanin(2)
all_connectivity_fanin(2)
report_transitive_fanout(2)
Chapter 1:
all_connectivity_fanout
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Commands
all_connectivity_fanout
L-2016.03
Version L-2016.03
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all_critical_cells
Returns a collection of critical leaf cells in the top hierarchy of the current design.
SYNTAX
collection all_critical_cells
[-slack_range range_value]
Data Types
range_value
float
ARGUMENTS
-slack_range range_value
Specifies a margin of slack for searching top-hierarchy leaf cells in paths whose slacks
are in the specified range_value relative to the worst slack of the current design. A
top-hierarchy leaf cell is a cell in the top hierarchy and with no hierarchy underneath.
The range_value must be expressed in the same units as the technology library used
during optimization. In addition, the range_value must be positive or 0.0. If no
range_value is specified, the default is 0.0. A range_value of 0.0 means that
top-hierarchy leaf cells in the most critical paths (those with the worst violations) are
returned. If a positive range_value is specified, all top-hierarchy leaf cells are returned if
they are in near-critical paths with slacks in the range_value relative to the worst slack
of the current design.
DESCRIPTION
The all_critical_cells command returns a collection of leaf cells that are in the top hierarchy
and in some path with a slack in the range_value relative to the worst slack of the current
design. This command returns only those cells with no hierarchy underneath.
If all timing paths passing through a cell are unconstrained, the cell is assumed to be
non-critical, and is not returned. You can use this command, along with the group
command, to group together into a new subhierarchy those cells in the most critical paths.
Then you can try various optimization techniques on the new subhierarchy.
Chapter 1:
all_critical_cells
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IC Compiler™
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Tool Commands
Commands
L-2016.03
Version L-2016.03
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example lists all top-hierarchy leaf cells in the worst critical paths of the current
design:
prompt> all_critical_cells
The following example lists all top-hierarchy leaf cells in those paths within range 5.0 relative
to the worst slack of the current design:
prompt> all_critical_cells -slack_range 5.0
The following example groups all top-hierarchy leaf cells in the worst critical paths into a new
hierarchy, called CRIT, under the top hierarchy of the current design:
prompt> group [all_critical_cells] -design_name CRIT
The following example reports cell connections of all top-hierarchy leaf cells in the worst
critical paths of the current design.
prompt> report_cell -connections [all_critical_cells]
SEE ALSO
all_critical_pins(2)
current_design(2)
group(2)
report_cell(2)
all_critical_cells
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all_critical_pins
Returns a collection of critical endpoints or startpoints in the current design.
SYNTAX
collection all_critical_pins
[-type endpoint | startpoint]
[-slack_range range_value]
Data Types
range_value
float
ARGUMENTS
-type endpoint | startpoint
Specifies that the pins or ports to be searched are either timing endpoints or timing
startpoints. The default is endpoint.
-slack_range range_value
Specifies a margin of slack for searching timing endpoints (or startpoints) in paths whose
slacks are in the specified range_value relative to the worst slack of the current design.
The range_value must be expressed in the same units as the technology library used
during optimization. In addition, the range_value must be positive or 0.0. If no
range_value is specified, the default is 0.0. A range_value of 0.0 means that endpoints
(or startpoints) in the most critical paths (those with the worst violations) will be returned.
If a positive range_value is specified, endpoints (or startpoints) in near-critical paths with
slacks in the range_value relative to the worst slack of the current design will be
returned.
DESCRIPTION
The all_critical_pins command returns a collection of endpoints (or startpoints) that are in
some timing path with a slack in the range_value relative to the worst slack of the current
design. For a pin, if all timing paths passing through it are unconstrained, it is assumed to be
non-critical, and it will not be returned.
Chapter 1:
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Tool Commands
Commands
L-2016.03
Version L-2016.03
This command may be used together with the all_fanin or all_fanout command to report
useful information; for example, cells in the transitive timing fanin cone of the most critical
endpoints.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example lists all endpoints in the worst critical paths of the current design:
prompt> all_critical_pins
The following example lists all startpoints in those paths within range 5.0 relative to the worst
slack of the current design:
prompt> all_critical_pins -type startpoint -slack_range 5.0
The following example reports cells in the 3-level transitive fanin timing cone of endpoints in
the worst critical paths:
prompt> report_cell [all_fanin -to [all_critical_pins] \
-only_cells -levels 3 -flat]
The following example reports the logic in the transitive fanin of endpoints in the worst
critical paths of the current design:
prompt> report_transitive_fanin -to [all_critical_pins]
SEE ALSO
all_critical_cells(2)
all_fanin(2)
current_design(2)
group(2)
report_cell(2)
report_transitive_fanin(2)
report_transitive_fanout(2)
all_critical_pins
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all_designs
Returns a collection containing all designs in the current design.
SYNTAX
collection all_designs
ARGUMENTS
There are no arguments to this command.
DESCRIPTION
The all_designs command returns a collection containing the designs in the current design
hierarchy in bottom-up order. You must set the current design using the current_design
command before using all_designs.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
current_design(2)
Chapter 1:
all_designs
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Tool Commands
Commands
L-2016.03
Version L-2016.03
all_dont_touch
Returns a collection of dont_touch cells or nets from the current design or from the
specified input collection.
SYNTAX
collection all_dont_touch
-cells | -nets
[input_coll]
Data Types
input_coll
string
ARGUMENTS
-cells
Specifies that all cells with the dont_touch attribute are to be returned. The -cells and
-nets options are mutually exclusive.
-nets
Specifies that all nets with the dont_touch attribute are to be returned. The -cells and
-nets options are mutually exclusive.
input_coll
Searches the specified input collection and returns the collection of cells or nets having
the dont_touch attribute. Objects are to be searched only from the content of input_coll
rather than from the entire design. By default, this option is off.
DESCRIPTION
This command returns the collection of cells or nets that have the dont_touch attribute from
the design or from a list that you specify. You can use wildcard characters, such as an
asterisk (*) or question mark (?), when specifying the input cell list.
all_dont_touch
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The command returns a standard Tcl collection. You can perform all of the generic
collection-manipulating commands, such as foreach_in_collection, sizeof_collection,
and so on, on this collection handle.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example shows the collection of all cells with the dont_touch attribute in the
design:
prompt> all_dont_touch -cells
{U20 U21 U23 SBLK/U1 SBLK/U2}
The following example shows the collection of all nets with the dont_touch attribute from an
existing collection where COLL is its handle:
prompt> all_dont_touch -nets $COLL
{n2 n5 SBLK/n2}
SEE ALSO
foreach_in_collection(2)
get_attribute(2)
get_cells(2)
get_nets(2)
report_attribute(2)
set_attribute(2)
set_dont_touch(2)
set_dont_touch_network(2)
set_dont_touch_placement(2)
sizeof_collection(2)
Chapter 1:
all_dont_touch
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_drc_violated_nets
Returns a collection of DRC-violated nets from the current design or from the specified input
collection.
SYNTAX
collection all_drc_violated_nets
-max_capacitance | -max_transition | -max_fanout
[input_coll]
[-bound upper]
[-threshold threshold]
Data Types
input_coll
upper
threshold
collection
float
float
ARGUMENTS
-max_capacitance
Returns the collection of maximum capacity nets that violate design rule checking
(DRC), as designated by drc_violated_nets.
-max_transition
Returns the collection of maximum transition nets that violate DRC, as designated by
drc_violated_nets.
-max_fanout
Returns the collection of maximum fanout nets that violate DRC, as designated by
drc_violated_nets.
input_coll
Searches the specified input collection and returns the requested collection of nets that
violate DRC constraints. Objects are searched only from the contents of the specified
input collection, rather than from the design.
all_drc_violated_nets
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-bound upper
Captures all DRC-violated nets that have values less than or equal to the bound
specified by upper. By default, this option is off.
-threshold threshold
Captures all DRC-violated nets that have values greater than or equal to the threshold
specified by threshold. By default, this option is off.
DESCRIPTION
The all_drc_violated_nets command returns a collection of DRC-violated nets from the
current design or from the specified input collection. The tool can search the entire design
hierarchy. It returns DRC-violated nets from the entire design, not just from the top level.
This command returns the 3 most common types of DRC violations: max_capacitance,
max_transition, and max_fanout. You can specify each of the violations separately in this
command. If you do not specify an option, a collection of all three types of DRC-violated nets
is returned.
The command returns a standard Tcl collection. You can perform all of the generic collection
manipulating commands, such as foreach_in_collection, sizeof_collection, and so on, on
this collection handle.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example shows the collection of all maximum capacity DRC-violated nets from
the design:
prompt> all_drc_violated_nets -max_cap
{n1 n2 n3 abc/n14}
The following example shows the collection of all -max_fanout DRC-violated nets from an
existing collection stored in $COLL:
prompt> all_drc_violated_nets -max_fanout $COLL
{n1 n3 abc/n14}
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)
all_drc_violated_nets
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all_fanin
Reports pins, ports, or cells in the fanin of specified sinks.
SYNTAX
collection all_fanin
-to sink_list
[-startpoints_only]
[-exclude_bboxes]
[-break_on_bboxes]
[-only_cells]
[-flat]
[-levels count]
[-trace_arcs arc_type]
Data Types
sink_list
count
list
int
ARGUMENTS
-to sink_list
Reports a list of sink pins, ports, or nets in the design and a timing fanin of each sink in
the sink_list. If you specify a net, the effect is the same as listing all driver pins on the net.
-startpoints_only
Returns only the timing startpoints.
-exclude_bboxes
Excludes black boxes from the final result.
-break_on_bboxes
Stops timing fanin traversal on black boxes.
-only_cells
Results in a set of all cells in the timing fanin of the sink_list.
Chapter 1:
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Commands
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Version L-2016.03
-flat
Specifies to function in the flat mode of operation. The two major modes in which
all_fanin functions are hierarchical (the default) and flat. When in hierarchical mode,
only objects from the same hierarchy level as the current sink are returned. Thus, pins
within a level of hierarchy lower than that of the sink are used for traversal but are not
reported.
-levels count
Stops traversal when reaching the perimeter of the search of count hops, where
counting is performed over the layers of cells that are equidistant from the sink.
-trace_arcs arc_type
Specifies the type of combinational arcs to trace during the traversal. Allowed values are
timing, which permits the tracing only of valid timing arcs (arcs that are neither disabled
nor invalid due to case analysis), and all, which permits tracing of all combinational arcs
regardless of either case analysis or arc disabling. The default is timing. You can
change the default by setting the fanin_fanout_trace_arcs variable to the desired
value.
DESCRIPTION
The all_fanin command reports the timing fanin of specified sink pins, ports, or nets in the
design. A pin is considered to be in the timing fanin of a sink if there is a timing path through
combinational logic from the pin to that sink. The fanin report stops at the clock pins of
registers (sequential cells).
Multicorner-Multimode Support
Depending on the options used, this command either uses the current scenario or has no
dependency on scenario-specific information.
EXAMPLES
The following examples show the timing fanin of a port in the design. The design comprises
three inverters in a chain named iv1, iv2, and iv3. The iv1 and iv2 inverters are hierarchically
combined in a larger cell named ii2.
prompt> all_fanin -to tout
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
prompt> all_fanin -to tout -flat
{ii2/iv1/U1/a ii2/iv2/U1/z tin iv3/U1/a ii2/iv1/U1/z
all_fanin
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ii2/iv2/U1/a iv3/U1/z tout}
SEE ALSO
all_fanout(2)
report_transitive_fanin(2)
Chapter 1:
all_fanin
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Tool Commands
Commands
L-2016.03
Version L-2016.03
all_fanout
Returns a set of pins, ports, or cells in the fanout of the specified sources.
SYNTAX
collection all_fanout
-clock_tree
-from source_list
[-endpoints_only]
[-exclude_bboxes]
[-break_on_bboxes]
[-only_cells]
[-flat]
[-levels count]
[-trace_arcs arc_type]
Data Types
source_list
count
list
int
ARGUMENTS
-clock_tree
Uses all clock source pins and/or ports in the design as the list of sources. Clock sources
are specified by using the create_clock command. If there are no clocks, or if the clocks
have no sources, the report is empty. Use the report_clock command to list the sources
for all clocks in the design. The -clock_tree option generates a report that displays the
clock trees or networks in the design. The -clock_tree and -from options are mutually
exclusive.
-from source_list
Specifies a list of source pins, ports, or nets in the design. The timing fanout of each
source in the source_list is reported. If a net is specified, the effect is the same as listing
all load pins on the net. The -clock_tree and -from options are mutually exclusive.
-endpoints_only
Returns only timing endpoints as a result.
all_fanout
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-exclude_bboxes
Excludes black boxes from the final result.
-break_on_bboxes
Stops timing fanout traversal on black boxes.
-only_cells
Results in a set of all cells in the timing fanout of the source_list, rather than a set of pins
or ports.
-flat
Specifies to function in the flat mode of operation. The two major modes in which
all_fanout functions are hierarchical (the default) and flat. When in hierarchical mode,
only objects from the same hierarchy level as the current source are returned. Thus, pins
within a level of hierarchy lower than that of the source are used for traversal but are not
reported.
-levels count
Stops traversal when reaching the perimeter of the search of count hops, where
counting is performed over the layers of cells that are equidistant from the source.
-trace_arcs arc_type
Specifies the type of combinational arcs to trace during the traversal. Allowed values are
timing, which permits the tracing only of valid timing arcs (arcs that are neither disabled
nor invalid due to case analysis), and all, which permits tracing of all combinational arcs
regardless of either case analysis or arc disabling. The default in IC Compiler and
Design Compiler (both in topographical mode and non-topographical mode) is timing.
The default in DC Explorer is all. The default can be changed by setting the
fanin_fanout_trace_arcs variable to the desired value.
DESCRIPTION
The all_fanout command reports the timing fanout of specified source pins, ports, or nets in
the design. A pin is considered to be in the timing fanout of a sink if there is a timing path
through combinational logic from that source to the pin. The fanout report stops at the inputs
to registers (sequential cells). The source pins or ports are specified by using the
-clock_tree or -from source_list option.
Multicorner-Multimode Support
Depending on the options used, this command either uses the current scenario or has no
dependency on scenario-specific information.
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
EXAMPLES
The following example shows the timing fanout of a port in the design. The design comprises
the following three inverters in a chain named iv1, iv2, and iv3. The iv1 and iv2 inverters are
hierarchically combined in a larger cell named ii2.
prompt> all_fanout -from tin
{iv3/out tout iv3/in ii2/hin ii2/hout tin}
prompt> all_fanout -from tin -flat
{tout ii2/iv2/U1/z ii2/iv1/U1/a iv3/U1/z iv3/U1/a
ii2/iv2/U1/a ii2/iv1/U1/z tin}
prompt> all_fanout -from tin -levels 1 -only_cells
{iv3 ii2}
SEE ALSO
all_fanin(2)
create_clock(2)
report_clock(2)
report_transitive_fanout(2)
all_fanout
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all_fixed_placement
Returns the collection of all fixed-placement cells or ports in the design or from a list of
objects in the input collection.
SYNTAX
collection all_fixed_placement
-cells | -ports
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
-cells
Specifies that the collection of fixed-placement cells is to be returned. If you specify this
option, you must not specify the -ports option: They are mutually exclusive.
-ports
Specifies that the collection of fixed-placement ports is to be returned. If you specify this
option, you must not specify the -cells option: They are mutually exclusive. All the ports
which are either having implicit is_fixed attribute or valid location are treated as
fixed-placement ports
input_coll
Specifies the input collection to search and return the collection of fixed-placement
objects. Objects are to be searched only from the content of the specified input collection
rather than from the design.
DESCRIPTION
This command can return the collection of all fixed-placement objects in the design. The tool
searches the entire design hierarchy. It returns fixed-placement objects from the entire
design, not just from the top level.
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
If you specify a value for input_coll, the command searches for fixed-placement objects only
from the specified collection, rather than from the entire design.
If you do not specify either the -cells or -ports option, the all_fixed_placement command
returns an error.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the collection of all fixed-placement cells from the design.
prompt> all_fixed_placement -cells
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
The following example shows the collection of all fixed-placement ports from the design.
prompt> all_fixed_placement -ports
{hin in out tin hout tout}
The following example shows the collection of all fixed-placement cells from an existing
collection stored in $COLL.
prompt> all_fixed_placement -cells $COLL
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
SEE ALSO
foreach_in_collection(2)
remove_dont_touch_placement(2)
set_dont_touch_placement(2)
sizeof_collection(2)
all_fixed_placement
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all_high_fanout
Returns a collection of high-fanout nets from the current design or from the specified input
collection.
SYNTAX
collection all_high_fanout
-nets
[-threshold value]
[input_coll]
[-through_buf_inv]
Data Types
value
input_coll
float
collection
ARGUMENTS
-nets
Returns the collection of high-fanout nets.
-threshold value
Specifies a threshold value used to determine if a net is a high-fanout net. The value is
a user-specified value. By default, the high_fanout_net_threshold variable value is
used to determine if a net is a high-fanout net.
input_coll
Searches the specified input collection for high-fanout nets. Objects are to be searched
only from the contents of the specified input collection, rather than from the design.
-through_buf_inv
Indicates to treat a buffer tree as transparent. The leaf loads of the buffer tree are treated
as the fanouts of the net.
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
DESCRIPTION
The all_high_fanout command returns a collection of all high-fanout nets in the design. The
tool searches the entire design hierarchy. It returns nets from the entire design, not just from
the top level.
To determine if a net is a high-fanout net, use the high_fanout_net_threshold variable
value as the threshold value. The command returns all nets with a fanout count higher than
this threshold as high-fanout nets. You can also specify the threshold by using the
-threshold option.
If you specify a value for input_coll, the command searches for high-fanout objects only from
the specified collection, rather than from the entire design.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection handle.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the collection of all high-fanout nets from the design:
prompt> all_high_fanout -nets
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
The following example shows the collection of all high-fanout nets from an existing collection
stored in $COLL:
prompt> all_high_fanout -nets $COLL
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
The following example shows the collection of all high-fanout nets from the design having a
fanout count of more than 100:
prompt> all_high_fanout -nets -threshold 100
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
all_high_fanout
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SEE ALSO
all_fanin(2)
all_fanout(2)
foreach_in_collection(2)
report_net_fanout(2)
sizeof_collection(2)
Chapter 1:
all_high_fanout
131
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_ideal_nets
Returns a collection of ideal nets from the current design or from the specified input
collection.
SYNTAX
collection all_ideal_nets
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
input_coll
Specifies the input collection to search for ideal nets.
If you do not specify this argument, the command searches for ideal nets in the current
design.
DESCRIPTION
The all_ideal_nets command returns a collection of ideal nets.
If you specify a value for input_coll, the command searches for ideal nets only in the
specified collection.
If you do not specify a collection, the command searches for ideal nets in the current design.
The tool searches the entire design hierarchy. The command returns ideal nets from the
entire design, not just from the top level.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection handle.
all_ideal_nets
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example returns a collection of all ideal nets from the design:
prompt> all_ideal_nets
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
The following example returns a collection of all ideal nets from an existing collection stored
in $COLL:
prompt> all_ideal_nets $COLL
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
SEE ALSO
all_fanout(2)
foreach_in_collection(2)
sizeof_collection(2)
Chapter 1:
all_ideal_nets
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_inputs
Returns a collection of input or inout ports in the current design.
SYNTAX
collection all_inputs
[-clock clock_name]
[-edge_triggered | -level_sensitive]
Data Types
clock_name
string
ARGUMENTS
-clock clock_name
Limits the search to ports that have input delay relative to clock_name.
-edge_triggered
Limits the search to ports that have edge-triggered input delay as specified by the
set_input_delay command with the -clock option.
-level_sensitive
Limits the search to ports that have level-sensitive input delay as specified by the
set_input_delay command with the -level_sensitive option.
DESCRIPTION
The all_inputs command returns a collection of all input or inout ports in the current design,
unless one of the options limits the search. The all_inputs command is usually used with a
command that places attributes on input ports. To get detailed information on ports in the
current design, use the report_port command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_inputs
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EXAMPLES
The following example lists all input ports in the current design:
prompt> all_inputs
{A1 A2 BIDIR1}
The following example sets the drive value of all the input ports on the current design to 10:
prompt> set_drive 10.0 [all_inputs]
The following example marks with a multicycle value of 0 all paths from inputs having
level-sensitive input delay relative to PHI1 to level-sensitive registers clocked by PHI1:
prompt> set_multicycle_path 0 \
-from [all_inputs -clock PHI1 -level_sensitive] \
-to [all_registers -data_pins -clock PHI1]
SEE ALSO
all_outputs(2)
current_design(2)
report_port(2)
set_drive(2)
set_input_delay(2)
set_multicycle_path(2)
Chapter 1:
all_inputs
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_isolation_cells
Returns a collection of isolation cells available in the design.
SYNTAX
collection all_isolation_cells
ARGUMENTS
The all_isolation_cells command has no arguments.
DESCRIPTION
The all_isolation_cells command returns a collection of the existing isolation cells in the
design. The enabled level shifters also work as isolation cells, but that type of cell is not
returned by this command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
all_level_shifters(2)
check_mv_design(2)
all_isolation_cells
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all_level_shifters
Returns a collection of level-shifter cells available in the design.
SYNTAX
collection all_level_shifters
[-type els | simple]
ARGUMENTS
-type els | simple
Specifies the type of level-shifter cells to include in the collection. If you specify -type
els, the command returns only the enabled level-shifter cells. If you specify -type
simple, the command returns only regular level-shifter cells. If you do not specify this
option, the command returns all level-shifter cells.
DESCRIPTION
The all_level_shifters command returns a collection of existing level-shifter cells in the
design. You can restrict the types of level-shifter cells returned in the collection by using the
-type option.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
check_level_shifters(2)
Chapter 1:
all_level_shifters
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_macro_cells
Returns a collection of all macro cells in the design or from a list of objects in the input
collection.
SYNTAX
collection all_macro_cells
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
input_coll
Specifies the input collection to search and return the collection of macro cells. Objects
are to be searched only from the content of the specified input collection rather than from
the design.
DESCRIPTION
This command can return the collection of all macro cells from the design. The tool searches
the entire design hierarchy. It returns cells from the entire design, not just from the top level.
This command uses the same definition as used in the legalizing process to determine if a
cell is a macro cell.
If you specify a value for input_coll, the command searches for macro cells only from the
specified collection, rather than from the entire design.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_macro_cells
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EXAMPLES
The following example shows the collection of all macro cells from the design.
prompt> all_macro_cells
{macro1 top/macro2 top/macro4 macro10}
The following example shows the collection of all macro_cells from an existing collection
stored in $COLL.
prompt> all_macro_cells $COLL
{macro1 macro2}
SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)
set_cell_type(2)
Chapter 1:
all_macro_cells
139
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_mtcmos_cells
Returns a collection of MTCMOS cells available in the design.
SYNTAX
collection all_mtcmos_cells
[-type coarse | fine]
ARGUMENTS
-type coarse | fine
Specifies the type of the MTCMOS cell to include in the collection.
If you specify -type coarse, the command returns only the coarse-grained MTCMOS
cells. If you specify -type fine, the command returns only the fine-grained MTCMOS
cells. If you do not specify this option, the command returns all MTCMOS cells.
DESCRIPTION
The all_mtcmos_cells command returns a collection of existing MTCMOS cells in the
design. You can restrict the types of MTCMOS cells returned in the collection by using the
-type option.
all_mtcmos_cells
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all_objects_in_bounding_box
Returns the collection of all cells and nets in the specified bounding box in the design or from
a list of objects in the input collection.
SYNTAX
collection all_objects_in_bounding_box
-cells | -nets
[-phys_cells]
-coordinates {llx lly urx ury}
[-flat]
[input_coll]
Data Types
llx
lly
urx
ury
input_coll
integer
integer
integer
integer
collection
ARGUMENTS
-cells
Specifies that all the cells from the bounding box are to be returned. The -cells and
-nets options are mutually exclusive; you can use only one.
-nets
Specifies that all the nets from the bounding box are to be returned. The -cells and -nets
options are mutually exclusive; you can use only one.
-phys_cells
Returns only physical-only cells.
-coordinates {llx lly urx ury}
Specifies the coordinates of the area from which the objects are to be returned.
-flat
Gets cells or nets inside physically hierarchical blocks.
Chapter 1:
all_objects_in_bounding_box
141
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
input_coll
Specifies the input collection to search and from which to return the collection of cells or
nets from the specified bounding box. Objects are to be searched only from the content
of the specified input collection, rather than from the design.
DESCRIPTION
This command can return the collection of all objects from the rectangular area (bounding
box) specified by the coordinates described by the -coordinates option. The tool searches
the entire design hierarchy. It returns objects from the entire design, not just from the top
level.
If you do not specify the -cell or -nets option, the command returns a collection of both
objects together from the specified bounding box.
If you specify a value for input_coll, the command searches for objects only from the
specified collection, rather than from the entire design. You must specify bounding box
coordinates; this command does not provide a default.
A standard Tcl collection is returned. All of the generic collection-manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the collection of all cells in the bounding box described by the
10 10 90 90 coordinates from the design.
prompt> all_objects_in_bounding_box -cells \
-coordinate {10 10 90 90}
{u1 u2 u3 abc/u14}
The following example shows the collection of all nets in the bounding box described by the
10 10 90 90 coordinates from the design.
prompt> all_objects_in_bounding_box -nets \
-coordinate {10 10 90 90}
{n1 n2 n3 abc/n14}
all_objects_in_bounding_box
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SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)
Chapter 1:
all_objects_in_bounding_box
143
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IC Compiler™
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Tool Commands
Commands
L-2016.03
Version L-2016.03
all_outputs
Returns a collection of output or inout ports in the current design.
SYNTAX
collection all_outputs
[-clock clock_name]
[-edge_triggered | -level_sensitive]
Data Types
clock_name
string
ARGUMENTS
-clock clock_name
Limits the search to ports that have output delay relative to clock_name.
-edge_triggered
Limits the search to ports that have edge-triggered output delay as specified by the
set_output_delay command with the -clock option.
-level_sensitive
Limits the search to ports that have level-sensitive output delay as specified by the
set_output_delay command with the -level_sensitive option.
DESCRIPTION
The all_outputs command returns a collection of all output or inout ports in the current
design, unless one of the options limits the search. This command is usually used with a
command that places attributes on output ports. To get detailed information on ports in the
current design, use the report_port command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_outputs
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EXAMPLES
The following example lists all output ports:
prompt> all_outputs
{OUT1 OUT2 BIDIR1}
The following example sets a capacitive load of 3.5 on each output port:
prompt> set_load 3.5 [all_outputs]
The following example sets paths leading to output ports clocked by TSTCLK to be false.
prompt> set_false_path -to [all_outputs -clock TSTCLK]
SEE ALSO
all_inputs(2)
current_design(2)
report_port(2)
set_false_path(2)
set_load(2)
set_output_delay(2)
Chapter 1:
all_outputs
145
1-145
IC
IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_physical_only_cells
Returns a collection of all the physical-only cells from a design or from a list of objects in an
input collection.
SYNTAX
collection all_physical_only_cells
[-lib_cells lib_list | -cell_name list]
[-coordinates {llx lly urx ury}]
[input_coll_handle]
Data Types
lib_list
list
llx
lly
urx
ury
input_coll_handle
list
list
float
float
float
float
collection
ARGUMENTS
-lib_cells lib_list
Specifies a list of library cells. The tool searches for physical-only cells in the specified
library cell list. The default behavior returns all physical-only cells from the entire design.
-cell_name list
Specifies the base instance name of the filler cells to be searched for in the design. The
default behavior returns all physical-only cells from the entire design.
-coordinates {llx lly urx ury}
Specifies the coordinates of the area to search for physical-only cells. Returns a
collection of the physical-only cells contained within the specified area. The default
behavior returns all physical-only cells from the entire design.
all_physical_only_cells
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input_coll_handle
Specifies the name of a collection from which to search for physical-only cells. Returns
a collection of physical-only cells that are contained within the specified input collection.
The default behavior returns all physical-only cells from the entire design.
DESCRIPTION
This command returns a collection of all the physical-only cells in the design. The tool
searches the entire design hierarchy. It returns physical-only cells from the entire design, not
just from the top level.
You can use wild cards, such as an asterisk (*) or question mark (?), when specifying cell
instance names.
A standard Tcl collection is returned. All of the collection-manipulating commands, such as
the foreach_in_collection and sizeof_collection commands, can be performed on the
collection of physical-only cells.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example collects all the physical-only cells from the design.
prompt> all_physical_only_cells
{fill1 fill2 fill3 abc/fill4}
The following example collects all the physical-only cells from the design that have a library
cell of type OKOAFILLER.
prompt> all_physical_only_cells -lib_cell OKOAFILLER
{hin in out tin hout tout}
The following example collects all the physical-only cells from an existing collection stored
in $COLL.
prompt> all_physical_only_cells $COLL
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
Chapter 1:
all_physical_only_cells
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Tool Commands
Commands
L-2016.03
Version L-2016.03
The following example collects all the physical-only cells from the design that have an
instance name starting with fill.
prompt> all_physical_only_cells -cell_name fill*
{fill1 fill2 fill3}
SEE ALSO
all_physical_only_nets(2)
all_physical_only_ports(2)
foreach_in_collection(2)
sizeof_collection(2)
all_physical_only_cells
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all_physical_only_nets
Returns a collection of all physical-only nets in the design or from a list of objects in the input
collection.
SYNTAX
collection all_physical_only_nets
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
input_coll
Specifies the input collection to search and return the collection of physical-only nets.
Objects are to be searched only from the content of the specified input collection rather
than from the design.
DESCRIPTION
This command can return the collection of physical-only nets from the design. The tool
searches the entire design hierarchy. It returns physical-only nets from the entire design, not
just from the top level. It returns power and ground nets together: They are not returned
separately.
If you specify a value for input_coll, the command searches for physical-only nets only from
the specified collection, rather than from the entire design.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
Chapter 1:
all_physical_only_nets
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
EXAMPLES
The following example returns a collection of all physical-only nets from the design.
prompt> all_physical_only_nets
{pnet1 pnet2 gnd vcc}
The following example returns a collection of all the physical-only nets from an existing
collection stored in $COLL.
prompt> all_physical_only_nets $COLL
{vcc vdd gnd vcc5}
SEE ALSO
all_physical_only_cells(2)
all_physical_only_nets(2)
foreach_in_collection(2)
sizeof_collection(2)
all_physical_only_nets
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all_physical_only_ports
Returns a collection of all physical-only ports in the design or from a list of objects in the
input collection.
SYNTAX
collection all_physical_only_ports
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
input_coll
Specifies the input collection to search and return the collection of physical-only ports.
Objects are to be searched only from the content of the specified input collection rather
than from the design.
DESCRIPTION
This command can return the collection of all physical-only ports from the design. The tool
searches the entire design hierarchy. It returns physical-only ports from the entire design,
not just from the top level.
If you specify a value for input_coll, the command searches for physical-only ports only from
the specified collection, rather than from the entire design.
A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
Chapter 1:
all_physical_only_ports
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
EXAMPLES
The following example returns a collection of all physical-only ports from the design.
prompt> all_physical_only_ports
{port1 port2 port3}
The following example returns a collection of all the physical-only ports from an existing
collection stored in $COLL.
prompt> all_physical_only_ports $COLL
{pport portp1 pport2}
SEE ALSO
all_physical_only_cells(2)
all_physical_only_nets(2)
foreach_in_collection(2)
sizeof_collection(2)
all_physical_only_ports
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all_registers
Returns a collection of sequential cells or pins in the current design.
SYNTAX
collection all_registers
[-no_hierarchy]
[-clock clock_name]
[-rise_clock rise_clock_name]
[-fall_clock fall_clock_name]
[-cells]
[-data_pins]
[-clock_pins]
[-slave_clock_pins]
[-output_pins]
[-level_sensitive | -edge_triggered]
[-master_slave]
Data Types
clock_name
rise_clock_name
fall_clock_name
string
string
string
ARGUMENTS
-no_hierarchy
Limits the search to only the current level of hierarchy. Subdesigns are not searched.
By default, the entire hierarchy is searched.
-clock clock_name
Considers only sequential cells clocked by the specified clock.
By default, all sequential cells in the current design are considered.
-rise_clock rise_clock_name
Considers only sequential cells triggered by the rising edge of the specified clock.
By default, all sequential cells in the current design are considered.
Chapter 1:
all_registers
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
-fall_clock fall_clock_name
Considers only sequential cells triggered by the falling edge of the specified clock.
By default, all sequential cells in the current design are considered.
-cells
Returns a collection of sequential cells that meet the search criteria.
If you do not specify any of the object type options, the command returns a collection of
sequential cells.
-data_pins
Returns a collection of data pins of the sequential cells that meet the search criteria.
-clock_pins
Returns a collection of clock pins of the sequential cells that meet the search criteria.
-slave_clock_pins
Returns a collection of slave clock pins of master-slave registers that meet the search
criteria. Slave clock pins are specified as clocked_on_also in the library.
-output_pins
Returns a collection of output pins of the sequential cells that meet the search criteria.
-level_sensitive
Limits the search to level-sensitive cells.
-edge_triggered
Limits the search to edge-triggered cells.
-master_slave
Limits search to master_slave cells.
DESCRIPTION
The all_registers command returns a collection of sequential cells or pins in the current
design, filtered as specified by the options. By default, the command returns a collection of
all sequential cells in the design. If you specify clock_name, it considers only the sequential
cells in the transitive fanout of the sources of the clock.
You can use one or more of the -cells, -data_pins, -clock_pins, -slave_clock_pins, and
-output_pins options to return a collection containing the respective types of objects. For
all_registers
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example, if you use -data_pins, the command returns a collection containing the only the
data pins of the sequential cells that meet the search criteria. If you use both -cells and
-data_pins, the command returns a collection containing both the sequential cells and their
data pins.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example sets max_delay targets for timing paths leading to data pins of all
registers clocked by PHI2:
prompt> set_max_delay 10.0 -to [all_registers -clock PHI2 -data_pins]
The following example returns a list of data pins for all master-slave registers clocked by
clockB:
prompt> all_registers -master_slave -data_pins -clock clockB
The following example returns a list of all level-sensitive cells and their clock (enable) pins:
prompt> all_registers -level_sensitive -cells -clock_pins
The following example shows how to push into an instance named U1 and find
level-sensitive cells without searching subdesigns of that instance:
prompt> current_instance U1
prompt> all_registers -no_hierarchy
SEE ALSO
create_clock(2)
current_design(2)
current_instance(2)
remove_clock(2)
set_max_delay(2)
Chapter 1:
all_registers
155
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_rp_groups
Returns a collection of specified relative placement groups and all groups in their hierarchy.
SYNTAX
collection all_rp_groups
[rp_groups]
Data Types
rp_groups
list or collection
ARGUMENTS
rp_groups
Specifies the relative placement groups for which to search.
If you do not specify this argument, the command returns a collection that contains all
relative placement groups currently loaded in memory.
DESCRIPTION
The all_rp_groups command returns a collection of the specified groups and all subgroups
in their hierarchy.
If you do not specify the rp_groups argument, the command returns all relative placement
groups currently loaded in memory.
If no relative placement groups are found, the command returns an empty string.
This command is supported only for designs that do not contain multiply-instantiated
designs.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
all_rp_groups
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EXAMPLES
The following example uses the all_rp_groups command:
prompt> get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}
prompt> all_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}
prompt> all_rp_groups ripple::grp_ripple
{ripple::grp_ripple mul::grp_mul}
prompt> remove_rp_groups -all -quiet
1
prompt> all_rp_groups
SEE ALSO
add_to_rp_group(2)
all_rp_hierarchicals(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)
Chapter 1:
all_rp_groups
157
1-157
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_rp_hierarchicals
Returns a collection of hierarchical relative placement groups that contain the specified
groups in their hierarchy. The specified groups can be either included or instantiated in their
parent group.
SYNTAX
collection all_rp_hierarchicals
[rp_groups]
Data Types
rp_groups
list or collection
ARGUMENTS
rp_groups
Specifies the relative placement groups whose ancestor groups are to be in the
collection returned by this command. The specified groups can be either included or
instantiated in their parent group.
If you do not specify this argument, this command returns a collection that contains all
hierarchical relative placement groups currently loaded in memory.
DESCRIPTION
The all_rp_hierarchicals command returns a collection of hierarchical groups that are
ancestors of the relative placement groups specified in the rp_groups argument.
If you do not specify the rp_groups argument, the command returns a collection that
contains all hierarchical relative placement groups currently loaded in memory.
If no relative placement groups are found, the command returns an empty string.
This command is supported only for designs that do not contain multiply-instantiated
designs.
all_rp_hierarchicals
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the all_rp_hierarchicals command:
prompt> get_rp_groups
{b::top a0::a0_group b::u_top/a1_group
b::u_top/a1_group_include b::u_nxt/a1_group
b::a1_group_include a1::a1_group}
prompt> all_rp_hierarchicals
{b::a1_group_include b::u_nxt/a1_group
b::u_top/a1_group_include b::u_top/a1_group b::top}
prompt> all_rp_hierarchicals b::u_top/a1_group_include
{b::u_top/a1_group}
prompt> remove_rp_groups -all -quiet
1
prompt> all_rp_hierarchicals
SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)
Chapter 1:
all_rp_hierarchicals
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_rp_inclusions
Returns a collection that contains the hierarchical relative placement groups that include the
specified groups.
SYNTAX
collection all_rp_inclusions
[rp_groups]
Data Types
rp_groups
list or collection
ARGUMENTS
rp_groups
Specifies the included relative placement groups whose parent groups are to be
included in the collection returned by this command.
If you do not specify this argument, this command returns a collection that contains all
hierarchical relative placement groups in the design that contain included groups.
DESCRIPTION
The all_rp_inclusions command returns a collection that contains the hierarchical groups
that include the relative placement groups specified in the rp_groups argument.
If you do not specify the rp_groups argument, the command returns a collection that
contains all hierarchical relative placement groups currently in memory that include other
relative placement groups.
If no relative placement groups are found, the command returns an empty string.
This command is supported only for designs that do not contain multiply-instantiated
designs.
all_rp_inclusions
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the all_rp_inclusions command:
prompt> get_rp_groups
{mul::grp_mul mul::big_grp ripple::grp_ripple
example3::g2 example3::top_group}
prompt> all_rp_inclusions
{mul::big_grp example3::g2}
prompt> all_rp_inclusions mul::grp_mul
{mul::big_grp}
prompt> remove_rp_groups -all -quiet
1
prompt> all_rp_inclusions
SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_hierarchicals(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)
Chapter 1:
all_rp_inclusions
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_rp_instantiations
Returns a collection of hierarchical relative placement groups that instantiate the specified
groups.
SYNTAX
collection all_rp_instantiations
[rp_groups]
Data Types
rp_groups
list or collection
ARGUMENTS
rp_groups
Specifies the instantiated relative placement groups whose parent groups are to be
included in the collection returned by this command.
If you do not specify this argument, this command returns a collection that contains all
hierarchical relative placement groups in the design that contain instantiated groups.
DESCRIPTION
The all_rp_instantiations command returns a collection of hierarchical relative placement
groups that instantiate the groups specified in the rp_groups argument.
If you do not specify the rp_groups argument, the command returns a collection that
contains all hierarchical relative placement groups currently in memory that instantiate other
relative placement groups.
If no relative placement groups are found, the command returns an empty string.
This command is supported only for designs that do not contain multiply-instantiated
designs.
all_rp_instantiations
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the all_rp_instantiations command:
prompt> get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::top_group}
prompt> all_rp_instantiations
{ripple::grp_ripple example3::top_group}
prompt> all_rp_instantiations ripple::grp_ripple
{example3::top_group}
prompt> remove_rp_groups -all -quiet
1
prompt> all_rp_instantiations
SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_hierarchicals(2)
all_rp_instantiations(2)
all_rp_references(2)
create_rp_group(2)
remove_rp_groups(2)
Chapter 1:
all_rp_instantiations
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IC Compiler™
Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_rp_references
Returns a collection of relative placement groups that directly contain the specified cells,
which are either leaf cells or hierarchical cells that contain instantiated relative placement
groups.
SYNTAX
collection all_rp_references
[cell_list]
[-design design_name]
Data Types
cell_list
design_name
list
string
ARGUMENTS
cell_list
Specifies the cells (either leaf cells or hierarchical cells that contain instantiated relative
placement groups) whose parent groups are to be included in the collection returned by
this command.
If you do not specify this argument, the command returns a collection that contains all
relative placement groups that directly contain any leaf cells in the specified design.
-design design_name
Specifies the design in which to locate the specified cells.
If you do not specify this option, the tool looks for the cells in the current design.
DESCRIPTION
The all_rp_references command returns a collection of relative placement groups that
directly contain the cells (either leaf cells or hierarchical cells that contain instantiated
relative placement groups) specified in the cell_list argument.
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If you do not specify the cell_list argument, the command returns a collection that contains
all relative placement groups that directly contain any leaf cells in the specified design.
A group directly contains a leaf cell if the cell was added to the group by using the -leaf
option of the add_to_rp_group command.
A group directly contains a hierarchical cell if the cell was used to hierarchically instantiate
another group by using the -instance option of the add_to_rp_group command.
This command is supported only for designs that do not contain multiply-instantiated
designs.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the all_rp_references command:
prompt> get_rp_groups
{mul::grp_mul ripple::grp_ripple example3::ripple
example3::top_group}
prompt> all_rp_references
{mul::grp_mul ripple::grp_ripple example3::ripple}
prompt> all_rp_references U1 -design mul
{mul::grp_mul}
prompt> remove_rp_groups -all -quiet
1
prompt> all_rp_references
SEE ALSO
add_to_rp_group(2)
all_rp_groups(2)
all_rp_inclusions(2)
all_rp_instantiations(2)
create_rp_group(2)
remove_rp_groups(2)
Chapter 1:
all_rp_references
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_scenarios
Lists all defined scenarios available in memory.
SYNTAX
string all_scenarios
ARGUMENTS
The all_scenarios command has no arguments.
DESCRIPTION
The all_scenarios command displays the scenarios currently defined in memory. This list
includes both active and inactive scenarios.
Multicorner-Multimode Support
This command uses information from both active and inactive scenarios.
EXAMPLES
The following example uses all_scenarios to list the available scenarios:
prompt> create_scenario MODE1
prompt> create_scenario MODE2
prompt> all_scenarios
MODE1 MODE2
SEE ALSO
all_active_scenarios(2)
create_scenario(2)
current_scenario(2)
all_scenarios
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remove_scenario(2)
set_active_scenarios(2)
Chapter 1:
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_size_only_cells
Returns a collection of cells that have the size_only attribute on them.
SYNTAX
collection all_size_only_cells
[cell_list]
Data Types
cell_list
collection
ARGUMENTS
cell_list
Specifies the cells from which the size-only cells are returned.
By default, all cells in the design are considered.
DESCRIPTION
This command returns the collection of size-only cells from the specified cells. You can use
wild cards, such as an asterisk (*) or question mark (?), when specifying the input cells.
A standard Tcl collection is returned. You can use all of the generic collection manipulating
commands, such as foreach_in_collection and sizeof_collection, on this collection.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following command returns a collection that contains all of the size-only cells in the
current design.
prompt>
all_size_only_cells
all_size_only_cells
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{U20 U21 U23 SBLK/U1 SBLK/U2}
The following command returns a collection that contains the size-only cells in the SBLK
subdesign.
prompt> all_size_only_cells [get_cells SBLK/*]
{SBLK/U1 SBLK/U2}
SEE ALSO
set_size_only(2)
get_attribute(2)
foreach_in_collection(2)
get_cells(2)
set_attribute(2)
report_attribute(2)
sizeof_collection(2)
Chapter 1:
all_size_only_cells
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Compiler™ Tool
Tool Commands
Commands
L-2016.03
Version L-2016.03
all_spare_cells
Returns a collection of all spare cells in the design or from a list of objects in the input
collection.
SYNTAX
collection all_spare_cells
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
input_coll
Specifies the input collection to search and return the collection of spare cells. Objects
are to be searched only from the content of the specified input collection, rather than
from the design.
DESCRIPTION
The all_spare_cells command returns the collection of all spare cells in the entire design
hierarchy (not just those in the top level of the design).
If you specify a value for the input_coll option, the tool searches for spare cells only in the
collection this option identifies, rather than in the entire design.
The all_spare_cells command looks for an internal attribute placed earlier on existing cells
during physical optimization or on additional cells at the end of physical optimization. (For
more information, see the man page for the insert_spare_cell command.)
The tool returns a standard Tcl-language collection. You can perform all of the
generic-collection manipulating commands, such as foreach_in_collection,
sizeof_collection, and so on, on this collection.
all_spare_cells
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example returns a collection of all spare cells in the design.
prompt> all_spare_cells
{spare1 top/spare2 top/spare4 spare10}
The following example returns a collection of all spare cells from an existing collection stored
in $COLL.
prompt> all_spare_cells $COLL
{spare1 spare2}
SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)
Chapter 1:
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Commands
L-2016.03
Version L-2016.03
all_threestate
Returns a collection of three-state cells or nets.
SYNTAX
collection all_threestate
-nets
[input_coll]
Data Types
input_coll
collection
ARGUMENTS
-nets
Specifies that the collection of three-state nets is to be returned.
input_coll
Searches the specified input collection and returns a collection of three-state nets.
Objects are to be searched only from the content of the specified input collection, rather
than from the design.
DESCRIPTION
The all_threestate command returns a collection of all three-state nets from the design. The
tool searches the entire design hierarchy. It returns three-state nets from the entire design,
not just from the top level.
If you specify a value for input_coll, the command searches for three-state nets only from the
specified collection, rather than from the entire design.
Only the nets that are driven by a pin that is tristate or bidirectional are returned as
three-state nets.
If you do not specify the -nets option, the all_threestate command returns an error.
all_threestate
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A standard Tcl collection is returned. All of the generic collection manipulating commands,
such as foreach_in_collection, sizeof_collection, and so on, can be performed on this
collection handle.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example returns a collection of all three-state nets from the design:
prompt> all_threestate -nets
{ii2/hin iv3/in iv3/out tin ii2/hout tout}
SEE ALSO
all_fanout(2)
foreach_in_collection(2)
sizeof_collection(2)
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Commands
L-2016.03
Version L-2016.03
all_tieoff_cells
Returns a collection of all tie-off cells in the current design or in the input collection.
SYNTAX
collection all_tieoff_cells
ARGUMENTS
The all_tieoff_cells command has no arguments.
DESCRIPTION
The all_tieoff_cells command returns a collection of all tie-off cells from the current design.
The tool searches the entire design hierarchy. It returns tie-off cells from the entire design,
not just from the top level.
Tie-off cells are the constant cells that the tool introduced in the design. To find the value of
a tie-off cell, the tool examines the corresponding lib_cell of each cell to determine if it is
logic-0 or logic-1.
If you specify a value for input_coll, the command searches for tie-off cells or nets only from
the specified collection, rather than from the entire design.
This command returns a standard Tcl collection. All of the generic collection manipulating
commands, such as foreach_in_collection, sizeof_collection, and so on, can be
performed on this collection.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example returns a collection of all tie-off cells from the design:
prompt> all_tieoff_cells
{logic1 logic0}
all_tieoff_cells
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The following example returns a collection of all tie-off cells from an existing collection stored
in $COLL:
prompt> all_tieoff_cells $COLL
{logic1}
SEE ALSO
foreach_in_collection(2)
sizeof_collection(2)
Chapter 1:
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Tool Commands
Commands
L-2016.03
Version L-2016.03
allocate_fp_budgets
Performs proportional timing budgeting.
SYNTAX
status allocate_fp_budgets
[-cells budget_cell_names]
[-black_box_cells bb_cells_list]
[-fixed_delay_objects objects]
[-file_format_spec file_format_string]
[-no_interblock_logic]
[-exploration]
[-incremental]
[-no_split]
[-print_partial_constraints]
[-create_qtm_models [-qtm_model_path output_directory]]
[-add_scenarios]
[-host_options host_options_name]
[-work_directory dir_name]
[-pre_open_cell_script pre_open_cell_script_name]
[-post_open_cell_script post_open_cell_script_name]
Data Types
budget_cell_names
bb_cells_list
objects
file_format_string
output_directory
host_options_name
dir_name
pre_open_cell_script_name
list
list
collection
string
string
string
string
string
ARGUMENTS
-cells budget_cell_names
Specifies a list of cells to budget. By default, the command budgets all plan groups and
soft macros in the current design.
-black_box_cells bb_cells_list
Specifies a list of black box cells to budget. Each black box cell in the list should have a
timing model. By default, black box are not rebudgeted.
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-fixed_delay_objects objects
Specifies a collection of objects that are implemented and their related delays do not
change. The objects can include one or more soft macro cells, hard macro cells, black
box cells, hierarchical cells for plan groups, pins of soft macros with ILMs, and pins of
hierarchical cells for plan groups. The budgets allocated to them are equal to the current
delay. By default, there are no fixed delay objects.
-file_format_spec file_format_string
Specifies the directory and naming style of the resulting Synopsys Design Constraints
(SDC) files. The file_format_string indicates the directory to write the output SDC files
and specifies whether to use the budgeting block instance names or reference names
as the file names. Specify output_directory/i.sdc to use the instance name, where
output_directory is the name of the output directory. Specify output_directory/m.sdc to
use the reference name. For designs with multiply instantiated modules (MIMs), the
command generates one SDC file for each module if you use instance name for file
name. If you use the reference name for file names, the command generates one master
SDC file for each MIM set.
-no_interblock_logic
Specifies that the top-level delays are considered fixed. There is no proportional budget
allocation at the top level.
-exploration
Specifies that budgeting is called inside the design planning exploration flow. By default,
the command operates in the normal design planning flow.
-incremental
Performs budgeting in incremental mode. In this mode, the budgeter retrieves certain
block-level implementation information from the ILMs of the soft macros and budgets the
delays using this information.
-no_split
Retains long command lines in the output file without splitting. By default, the budgeter
splits long lines when creating the SDC files and uses a backslash (\) symbol at the end
of each line to indicate continuation.
-print_partial_constraints
Generates partial constraint files for blocks containing partial netlists. This option is valid
only in partial netlist flows such as the on-demand-loading flow, re-budgeting with ILM
flow, and the trace mode flow. By default, budgeting does not write out partial constraint
files.
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Commands
L-2016.03
Version L-2016.03
-create_qtm_models
Creates quick timing models (QTM) for the budgeted plan groups or soft macros. The
delay arcs and constraint arcs in the generated QTM represent the budgets on the plan
groups or soft macros. You can load the QTMs for the soft macros or plan groups after
they are committed to soft macros, and check the timing at the top level and verify the
budgets. By default, the command does not create quick timing models.
-qtm_model_path output_directory
Specifies the directory path to write the quick timing model (QTM) files that the tool
generates. By default, the files are written to the current work directory. You must also
specify the -create_qtm_models option when you specify the -qtm_model_path
option.
-add_scenarios
Adds constraints generated by the current budgeting command to the constraints
generated previously for different scenarios. You can use this option only if you
previously ran budgeting at least one time without the -add_scenarios option.
-host_options host_options_name
Specifies the distributed processing configuration to use when running this command.
You use the set_host_options command to define the distributed processing
configuration. By default, the command does not use distributed processing.
-work_directory dir_name
Specifies the name of the working directory used to write the files produced by
distributed budgeting. The default directory name is TB_work_dir. This directory must be
accessible by all the distributed processing workers and should not be on a local disk
accessible only to the master process. This option takes effect only when the
-host_options option is also specified.
-pre_open_cell_script pre_open_cell_script_name
Specifies the name of a file containing a script that will be sourced by the distributed
processes before opening the design.It can be used to set up some design specific
information. This option takes effect only when the -host_options is also specified.
-post_open_cell_script post_open_cell_script_name
Specifies the name of a file containing a script that will be sourced by the distributed
processes immediately after opening the design. It can be used to set up non-default
timer behavior or to read parasitic files. This option takes effect only when the
-host_options option is also specified.
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DESCRIPTION
This command performs proportional timing budgeting for all plan groups or soft macros in
the design. It writes out the Synopsys Design Constraints (SDC) files which contain timing
constraints describing the budgets.
By default, the allocate_fp_budgets command disables recovery and removal arcs, similar
to the report_timing and timing optimization commands. To enable recovery and removal
arcs, set the enable_recovery_removal_arcs variable to true. This variable setting is
honored by the allocate_fp_budgets command, the report_timing command, and timing
optimization commands such as place_opt.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example performs timing budgeting for a design with three blocks: BlockA,
BlockB, and BlockC. It creates three SDC files in the current directory: BlockA.sdc,
BlockB.sdc, and BlockC.sdc. These files contain the timing constraints for the
corresponding block.
prompt> allocate_fp_budgets
The following example creates three files named BlockA.sdc, BlockB.sdc, and BlockC.sdc.
In this example, the delays internal to the file named BlockA.sdc are considered fixed. This
potentially affects all three generated files.
prompt> allocate_fp_budgets -fixed_delay_objects [get_cells BlockA]
The following example runs distributed budgeting using LSF. The script post.tcl will be
sourced in the distributed processes after the design is opened.
prompt> set_host_options -name my_host_options -pool lsf \
-submit_options "-q cpu64"
prompt> allocate_fp_budgets -host_options my_host_options \
-post_open_cell_script post.tcl
SEE ALSO
Chapter 1:
allocate_fp_budgets
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Commands
L-2016.03
Version L-2016.03
check_fp_budget_result(2)
check_fp_timing_environment(2)
place_opt(2)
report_timing(2)
set_host_options(2)
allocate_fp_budgets
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analyze_design_violations
Analyzes the current design, identifies unfixable violations, and generates a summary
report.
SYNTAX
status analyze_design_violations
-type max_trans | hold
[-fanout hfn_threshold]
[-slack small_violation_threshold]
[-output output_dir]
[-effort medium | high]
[-stage preroute | postroute]
[-input input_file]
Data Types
hfn_threshold
small_violation_threshold
output_dir
input_file
integer
float
string
string
ARGUMENTS
-type max_trans | hold
Specifies the type of violation to analyze, either maximum transition (max_trans) or hold
time (hold).
This is a required option.
-fanout hfn_threshold
Specifies the high-fanout threshold; nets with a fanout larger than this value are
considered high-fanout nets.
By default, the high-fanout threshold is 30.
-slack small_violation_threshold
Specifies the slack threshold in picoseconds for violations to be considered small. Other
analysis will not be performed on small violations.
By default, any slack violation less than 5 ps (-slack 5.0) is considered small.
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Commands
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Version L-2016.03
-output output_dir
Specifies the output directory name.
Before starting analysis, the analyze_design_violations command runs the
report_constraint command and writes the violating endpoints or nets to a file in the
specified directory. A detailed report file and all category files are written to the same
directory. If the specified directory exists, the command overwrites the files in that
directory.
By default, the output directory name is analyze_design_violations.
-effort medium | high
Specifies the analysis effort.
The default is medium.
If you set this option to high, the command performs setup conflict checking, which
significantly increases the runtime. You should use this option with the -input option to
focus on a few violations instead of the whole design.
-stage preroute | postroute
Specifies the routing stage used for analysis.
The default is postroute and the command uses the route_length attribute to
determine the wire lengths.
If you set this option to preroute, the command uses the x_length and y_length
attributes to determine the wire lengths.
-input input_file
Specifies the name of the input file used to specify the endpoints or nets to analyze.
By default, the command analyzes all violations in the design.
To reduce the runtime or to focus on specific violations, you can provide a file that
contains the endpoints or nets to analyze. The file must be generated by the
report_constraint command with required options.
To generate a file used to analyze maximum transition violations, use the following
command:
report_constraint -max_transition -all_violators \
-nosplit -significant_digits 5
If this is a multicorner-multimode design, you must also use the -scenarios
[all_active_scenarios] option.
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To generate a file used to analyze hold time violations, use the following command:
report_constraint -min_delay -all_violators \
-nosplit -significant_digits 5
If this is a multicorner-multimode design, you must also use the -scenarios
[all_active_scenarios] option.
After you have generated the output file, you can copy and paste the violations of
interest into the input file. Do not modify the contents for a violation, such as changing
lines or spacing, as this command analyzes the file based on syntax.
For maximum transition violations, the input should include the violated net with the
complete pin or port lines. You cannot provide an input file with only violated pin or port
lines.
DESCRIPTION
This command analyzes maximum transition or hold time violations in the current design
and generates a summary report for the unfixed violations.
Multicorner-Multimode Support
This command supports multicorner-multimode designs.
EXAMPLES
The following example analyzes the maximum transition violations in the current design:
prompt> analyze_design_violations -type max_trans
The following example analyzes the hold time violations in the current design. It considers
any net with more than 10 fanouts as a high-fanout net and any violation with slack less than
50 ps as a small violation. It writes the output to a directory named my_report.
prompt> analyze_design_violations \
-type hold -fanout 10 -slack 50 \
-output my_report
Assume that you want to generate a maximum transition report only for the worst maximum
transition violation in the design. You could edit the report generated by the
report_constraint command so that it contains only that violation and use that report as
input to the analyze_design_violations command. Note that you do not need to remove
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Version L-2016.03
the header and title, as the analyze_design_violations command automatically filters
these out.
The following is the edited maximum transition report used as input to the
analyze_design_violations command:
****************************************
Report : constraint
-all_violators
-max_transition
Design : demo
Version: G-2012.06-ICC
Date
: Wed May 2 13:48:53 2012
****************************************
Parasitic source
Parasitic mode
Extraction mode
Extraction derating
:
:
:
:
LPE
RealRC
MIN_MAX
0/0/0
max_transition
Required
Actual
Net
Transition
Transition
Slack
----------------------------------------------------------------LA_LINK0[16]
0.50000
552.96002
-552.46002
(VIOLATED)
PORT : LA_LINK0[16] 0.50000
552.96002
-552.46002
(VIOLATED)
When you run the analyze_design_violations command using this file as the input, it
generates the following maximum transition report.
WNS: 11.74 TNS: 13456.76 Number of Violating Paths: 43745
(with Crosstalk delta delays)
Nets with DRC Violations: 3382
Total moveable cell area: 736083.9
Total fixed cell area: 213675072.0
Total physical cell area: 214411152.0
Core area: (30000 30000 17169980 17169200)
(Hold) WNS: 0.57 TNS: 110.48 Number of Violating Paths: 773
(with Crosstalk delta delays)
*************************************************************************
**
Product version: G-2012.06-ICC
Product root: /product/synopsys/tool/ICC
Current design: demo
Script version: 2.5
Options:
verbose: off, 0
type: max_trans
fanout: 30
analyze_design_violations
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slack: 5 ps
effort: medium, setup conflict check will be excluded
stage: postroute
input: ./my_input
output: analyze_design_violations
*************************************************************************
**
Phase 1: Analyzing optimization setup and current log......Thu Jun 14
13:40:02 2012
--> using default set_cost_priority
--> using user's critical_range { 0.200000 }
--> found RCEX-060 in icc_output.txt
--> variable "physopt_cpu_limit" is 0
--> variable "routeopt_disable_cpulimit" is false
--> variable "focalopt_endpoint_margin" is true
--> variable "compile_no_new_cells_at_top_level" is false
--> checking report_route_opt_strategy
--> checking report_route_opt_zrt_crosstalk_options
--> found 320 placement blockage(s)
--> no routing blockage
Phase 2: Generating all temporary files......Thu Jun 14 13:40:03 2012
Phase 3: Analyzing max_trans violations left in the design......Thu Jun
14 13:40:03 2012
--> real time progress is at "/testcase/project/
analyze_design_violations/max_trans.summary"......
Analyzing specific violated max trans net LA_LINK0[16] ......
****** Category Of Violated Nets ******
* Category 1 : Entire net is dont_touch *
* Category 2 : Nets connect to pad cell *
LA_LINK0[16]
0.50000
552.96002
(VIOLATED)
PORT : LA_LINK0[16] 0.50000
552.96002
(VIOLATED)
-552.46002
-552.46002
* Category 3 : Clock nets *
* Category 4 : Constant nets *
* Category 5 : Nets have within_ilm attribute *
* Category 6 : Nets have within_block_abstraction attribute *
* Category 7 : Multi-driven nets *
* Category 8 : High fanout *
* Category 9 : Driver cell is {dont_touch or macro or is_fixed} AND
driver pin is violating AND net is < 100u *
* Category 10 : Nets with small violated slack *
* Category 11 : Nets are highly blocked *
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* Category 12 : Violated nets are not included in above catelogy, or may
be fixable (small violated slack or high fanout) *
* Category 13 : Setup conflict with driver on violated net or endpoint *
****** End Of Category of Violated Nets ******
Phase 4: Generating summary report......Thu Jun 14 13:40:08 2012
*************************************************************************
**
Total violated max transition nets: 1, 1 are unfixable
Within 0 violated nets not found in unfixable categories, 0 are less
than 5.0 ps
Unfixable categories:
---------------------------------------------------Entire net is dont_touch: 0
Nets connect to pad cell: 1
Clock nets: 0
Constant nets: 0
Nets have within_ilm attribute: 0
Nets have within_block_abstraction attribute: 0
Multi-driven nets: 0
Driver cell is {dont_touch or macro or is_fixed} AND driver pin is
violating AND net is < 100u: 0
Nets are highly blocked: 0
Information:
---------------------------------------------------High fanout (>= 30 load pins): 0
Nets with small violated slack (<= 5.0 ps): 0
Found RCEX-060 warning in log and optimization will not fix those
nets
Setup conflict with driver or endpoint: No check with effort medium
Violated
Violated
Violated
Violated
slack
slack
slack
slack
(<= 5.0 ps): 0
(> 5.0 AND <= 10.0 ps): 0
(> 10.0 AND <= 20.0 ps): 0
(> 20.0 ps): 0
*************************************************************************
**
Information: check "/slowfs/disk/user/demo/analyze_design_violations/
max_trans.summary" for all details
SEE ALSO
report_constraint(2)
report_timing(2)
analyze_design_violations
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analyze_displacement
Reports and analyzes the displacement information for the feasibility flow.
SYNTAX
status analyze_displacement
-input filename
[-checkpoints checkpoint_list]
[-displacement_threshold distance]
[-cells cell_collection]
[-timing_path filename]
[-slack_threshold slack]
[-move_back checkpoint_index]
[-compare_timing]
[-commit_change]
Data Types
filename
checkpoint_list
distance
cell_collection
slack
checkpoint_index
string
list
integer
collection
float
integer
ARGUMENTS
-input filename
Reads the cell location history report file, and reports the displacement in the GUI if the
GUI is open. It also displays the displacement list from each checkpoint accordingly. This
is a required option.
-checkpoints checkpoint_list
You can specify two or more checkpoints from the flow. By default, the
analyze_displacement command looks at all the checkpoints in the input file.
Checkpoints specified will be the starting and end compare points. For example, if you
specify -checkpoints {2 3}, the analyze_displacement command compares cell
positions between checkpoints 2 and 3 and reports the cells with displacement greater
than the displacement threshold. Some commands, such as the optimization command,
can remove cells from the design. Only cells that are in both start and end checkpoints
will be reported.
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This option cannot be used with the -move_back option.
-displacement_threshold distance
Specifies the displacement threshold in unit of cell row height. This option filters any
cells that have displacement less than the specified threshold value. The displacement
distance is calculated by Euclidean distance; that is, sqrt(deltaX**2 + deltaY**2). The
default value is 10.
-cells cell_collection
Specifies a collection of cells to filter the reporting of large displacement. You use this
option to restrict reporting and the -move_back option to focus on a specific set of cells.
When this option is used together with the -timing_path option, the -cells option selects
the cells that are present in both the timing paths and cell list.
-timing_path filename
Specifies the critical timing paths where the command finds cells with large
displacement. The filename is a timing report file from the report_timing command. You
can specify the -slack_threshold option for the command to find the timing paths. You
can use the -timing_path option with the -cell option to further restrict the cells to the
specified lists of both options.
-slack_threshold slack
Specifies the minimum negative slack threshold value of the timing paths where the
command finds cell displacement. For example, a -1.0 value means that the paths with
slack worse than -1.0 are considered in the analysis. The default is 0.0. Use this option
with the -timing_path option to filter most of the timing paths.
-move_back checkpoint_index
Moves the cells with large displacement to the specified checkpoint. This option must be
followed by the -compare_timing option, the -commit_change option, or both options.
This option cannot be used with the -checkpoints.
By default, the process of the -move_back option is temporary, and it does not change
the placement of the design. The RC data can be unsynchronized.
-compare_timing
Specifies a timing report file associated with cell displacement. Use this option with the
-move_back option. If you specify the -timing_path option, the command generates
another timing report for the specified timing paths with large cell displacement. You can
compare the timing of the two reports and examine the timing impact on the same timing
paths.
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-commit_change
This option only takes effect when used with the -move_back option, and keeps the
cells at the locations after the move back. By default, all the move back actions of the
cells are reversed after the analysis.
DESCRIPTION
The place_opt_feasibility flow records the cell movement history by using specific
checkpoints, such as before and after the legalization step, and a new report is generated.
By default, this feature is enabled during the place_opt_feasibility and
clock_opt_feasibility flow. The resulting output file is named feas_cell_history. If this file is
not available, a new file name is used instead. The tool uses the naming convention
feas_cell_history.<n>, where <n> is the index number.
You need to specify a report file for the command to determine how many checkpoints have
been executed, and the command displays the cells with the associated displacement
information. If the appropriate GUI window is open, the command plots the displacement as
an overlay by using different color for each checkpoint.
To analyze large displacement cells in critical timing paths, you can provide an up-to-date
timing report file as the input. The command analyzes the timing report and finds the cells
with large displacement. The command reports the cell displacement and displays the cell
displacement in the GUI if the appropriate window is open.
You can use the -move_back option to analyze the timing impact. The command moves the
cells back to the original locations before the specified checkpoint, estimates RC data,
updates timing, and regenerates the timing report file for the specified timing paths. To
preserve the results, you can use the -commit_change option. By default, the timing
analysis after the moving back is not preserved, but the RC data is left as is and you should
update the data.
You can also specify the cell names for the tool to report cells that have large displacement.
It provides flexibility compared to the time_report format input that is supported by this
feature.
The following example uses the -timing_path option. It is a timing report file. You can
provide your timing report file for the tool to analyze. You can then specify the
-slack_threshold option for the tool to skip the non-critical paths.
Startpoint: mi_wrap/ms_top_inst/u_MS_TOP/u_CLKGEN4/
u_CLKGEN_SUB_ODEN_ub_clk/u_CLK_DIV_ODEN/clk_even_reg
(rising edge-triggered flip-flop clocked by PLL_CLK4)
Endpoint: mi_wrap/ms_top_inst/u_MS_TOP/u_CLKGEN4/
u_CLKGEN_SUB_ODEN_ub_clk/u_CLK_DIV_ODEN/clk_shift_reg
(rising edge-triggered flip-flop clocked by CLK3')
Scenario: sys_main
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Path Group: CLK3
Path Type: max
Attributes:
d - dont_touch
u - dont_use
mo - map_only
so - size_only
i - ideal_net or ideal_network
Point
Path
Trans
Delta
Incr
Location / Load
--------------------------------------------------------------------------------------------------------------clock PLL_CLK4 (rise edge)
140.000
140.000
clock network delay (ideal)
0.000
140.000
...
data arrival time
140.279
clock CLK3' (rise edge)
140.400
140.400
clock network delay (ideal)
0.000
140.400
clock reconvergence pessimism
0.000
140.400
clock uncertainty
-0.300
140.100
library setup time
-0.231
139.869
data required time
139.869
-------------------------------------------------------------------------------------------------------------data required time
139.869
data arrival time
-140.279
------------------------------------------------------------------------------------------------------------slack (VIOLATED)
-0.410
EXAMPLES
The following example shows the typical output.
prompt> analyze_displacement -input feas_cell_history
****************************************
Report : analyze_displacement
analyze_displacement
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Design : TOP
-input feas_cell_history
-displacement_threshold 10
Version: D-2010.03-ICC
****************************************
Minimal cell row height: 5.040.
Summary of analysis Result
--------------------------------------------------Checkpoint 1: Start_legalizer
39 new large displacement to next checkpoint
Checkpoint 2: End_legalizer
0 new large displacement to next checkpoint
Checkpoint 3: Start_legalizer
42 new large displacement to next checkpoint
Checkpoint 4:End_legalizer
0 new large displacement to next checkpoint
Checkpoint 5: Current
1
The following example reports the displacement of cells between checkpoints 1 and 4.
Notice that the value is not the sum of displacement of checkpoint 1-2 and 3-4 from the
previous example. The discrepancy is due to cells that were removed from the design during
optimization. Only cells existing in both checkpoints are reported.
prompt> analyze_displacement -input feas_cell_history
-checkpoints {1 4}
****************************************
Report : analyze_displacement
Design : TOP
-input feas_cell_history
-displacement_threshold 10
Version: D-2010.03-ICC
****************************************
Minimal cell row height: 5.040.
Summary of analysis Result
--------------------------------------------------Checkpoint 1: Start_legalizer
39 new large displacement to next checkpoint
Checkpoint 2: End_legalizer
1
The following example uses the -move_back and -compare_timing options.
prompt>analyze_displacement -input feas_cell_history \
-move_back 3 -compare_timing -timing_path report.tim
****************************************
Report : analyze_displacement
Design : TOP
-input feas_cell_history
-displacement_threshold 10
Version: D-2010.03-ICC
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****************************************
Minimal cell row height: 5.040.
Summary of analysis Result
--------------------------------------------------Checkpoint 1: Start_legalizer
4 new large displacement to next checkpoint
Checkpoint 5: Current
Summary of Cell Movement
--------------------------------------------------Move cell U740 back from {374.880 519.120} to {372.900 423.360}
Move cell U719 back from {349.800 327.600} to {350.638 420.901}
Move cell U407 back from {347.820 327.600} to {350.029 420.837}
Move cell U728 back from {331.980 327.600} to {333.912 421.000}
Total 4 cells moved.
Summary of timing analysis after cells moving back
--------------------------------------------------Estimate RC ....
Update timing ....
Report timing ....
Saved timing report file after moving cells back as ./timing_report_27199
Saved timing paths impacted by cell displacement as ./timing_path_27199
Startpoint: INSTANCE_2/CK
Endpoint:
REG/D
Slack change 0.85: from -1.940 to -1.09
Info: Cancelled the cell move_back action.
1
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analyze_fp_rail
Analyzes a complete or partial power network for voltage (IR) drop and electromigration
(EM) on the specified power and ground nets.
SYNTAX
status analyze_fp_rail
-nets nets
[-power_budget power]
[-analyze_power]
[-voltage_supply voltage]
[-pad_masters pad_masters]
[-read_pad_instance_file file_name]
[-read_pad_master_file file_name]
[-use_pins_as_pads]
[-top_level_only]
[-create_virtual_rails layer]
[-ignore_blockages]
[-ignore_conn_view_layers layer]
[-read_power_compiler_file file_name]
[-read_prime_power_file file_name]
[-read_default_power_file file_name]
[-output_directory directory_name]
Data Types
nets
power
voltage
pad_masters
file_name
layer
directory_name
collection or list
float
float
string
string
collection or list
string
ARGUMENTS
-nets nets
Specifies the names of the power or ground nets on which to perform power network
analysis. The default is to perform it on all power and ground nets.
-power_budget power
Specifies a total power budget for the analyzed design on which to perform
constraint-driven power network analysis. The power budget is divided among the
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instances according to their sizes. For hard macros or standard cells, the power budget
is computed based on the percentage of the total area. For a hierarchical block, the it is
computed based on the sum of all cells and blocks inside it. The power unit is in
milliwatts. The default is 1000.
For example, if the power budget for the entire design is 500 milliwatts, the total area of
the top-level blocks is 500,000 square microns, and one of the blocks has an area of
25,000 square microns, power network analysis allocates the power for that
25,000-square-micron block as follows:
500mW * (25,000/50,000) = 25mW
-analyze_power
Specifies the power network analysis|synthesis (PNA|PNS) engine to analyze power for
each instance from ICC. Before using this tcl option for power analysis, the default
toggle rate (default as 0.1) and default static probability (default 0.5) for primary inputs
and black box outputs can be set using set power_default_toggle_rate and set
power_default_static_probability commands. The toggle rate and/or static probability
for a specified object, e.g. a net, pin or port can be set using set_switching_activity.
The switching activity interchange format (SAIF) file may also be read using read_saif
command. set_cell_internal_power can be used to set the power value of a pin per
toggle. Please refer to report_power command for more detailed information.
report_power -cell -flat -nosplit is recommended to be run first prior to PNA with
-analyze_power.
-analyze_power can be used concurrently with option -power_budget. If a power
budget is specified using -power_budget together with -analyze_power and the power
budget is larger than the sum of instance power calculated by -analyze_power, the
difference between power budget and the total power by -analyze_power will be
assigned to those instances that are not assigned in -analyze_power if there is any
such instances. Otherwise, the power budget is ignored. Power budget is set to 0 by
default with "-analyze_power".
-analyze_power can also be used concurrently with -read_default_power_file. The
power specified in the default power file has a higher priority than that calculated by
-analyze_power option, i.e. if the power value is calculated and read from the default
power file for one instance, the instance will be assigned with the power from the default
power file.
"-analyze_power" is mutually exclusive with "-read_power_compiler_file" and
"-read_prime_power_file".
By default, power is NOT calculated from ICC unless this option is explicitly used.
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-voltage_supply voltage
Specifies at the power pad the voltage of the net to be analyzed. The voltage unit is
volts. The default is 1.5.
-pad_masters pad_masters
Specifies the pad masters and the associated net as follows
net_name:pad_master_name
If net name is not specified, the pad master is used for both power and ground nets. By
default, PNA will assume all the pads logically connected to signal 1 or 0 as power pads.
-read_pad_instance_file file_name
Specifies the pad instance file name and (optionally) the net name. If you do not specify
the net name, the command assumes that the specified pad instance is used for both
power and ground nets.
The instance_and_net format is as follows:
instance_name [net_name]
For example, a valid instance_and_net value might be VDD1 VDD. By default, this
option is off.
-read_pad_master_file file_name
Specifies the pad master file name and (optionally) the net name. If you do not specify
the net name, the command assumes that the specified pad master is used for both
power and ground nets. The master_name_and_net format is as follows:
master_name [net_name]
For example, a valid master_name_and net value might be VDD.FRAM VDD. By
default, this option is off.
-use_pins_as_pads
Specifies to regard pins as pads in block level simulation.
-top_level_only
Specifies for the power network analysis (PNA) engine to ignore cells inside soft macros,
but to consider all the power and ground net wires and vias in the design. By default, the
PNA engine analyzes the design as if it were flat.
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-create_virtual_rails layer
Allows Power network analysis to create virtual pseudo straps that represent the metal
1 straps for the standard cell pin connections because, during floorplanning stages,
metal 1 straps for the standard cell pin connections usually are not available. During
power planning, Power network analysis then analyzes the IR (voltage) drop and
electromigration to predict what the effects might be when the metal 1 straps are
available. This option creates pseudo horizontal straps with specified layers for standard
cell pin connections based on the row information in the database. By default, this option
is off.
-ignore_blockages
Ignores blockages for virtual pads.
By default, this option is off.
-ignore_conn_view_layers layer
Ignores all metal layers (select the All option) or the specified metal layer(s) (select the
Specified option) in connectivity (.CONN) views. By default, this option is off and none of
metal layers are ignored.
-read_power_compiler_file file_name
Obtains the power calculation source from a Power Compiler report file. By default, this
option is off.
-read_prime_power_file file_name
Obtains the power calculation source from a Prime Power/Prime Time PX report file. By
default, this option is off.
-read_default_power_file file_name
Uses the PNA default format to obtain a power calculation. The
power_name_and_value format is as follows, where power_value is given in mW:
instance_or_master_name [power_value]
For example, a valid power_name_and_value value might be as follows:
instance X1 0.2
master abc.FRAM 0.1
By default, the command also reads a power information file generated from AstroRail
by using the poDumpPowerInfo command.
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-output_directory directory_name
The specified directory stores the IR/EM results with the file name design_name.
net_name.pw_hl.pna and the power allocation results with the file name design_name.
net_name.power. The default is pna_output.
DESCRIPTION
This command allows user to perform a power network analysis (PNA) in a complete or
partially built power/ground network at design planning stage. If the power ports in standard
cells and/or hard macros are yet to be connected to the P/G network, the PNA will make
virtual connection to those unconnected power ports and analyze the IR drop and EM in the
power network based on user provided power budget and voltage supply.
Multicorner-Multimode Support
This command is not supported in a multi-scenario design flow.
EXAMPLES
The following example shows how to analyze the voltage drop on net VDD and VSS in the
power network. The total power budget in the design is 1000mW, the voltage supply is 1.2V,
and the pad master is pvdi.FRAM for net VDD and pvdo.FRAM for net VSS.
prompt> analyze_fp_rail\
-nets {VDD VSS}\
-power_budget 1000\
-voltage_supply 1.2\
-pad_masters "VDD:pvdi.FRAM VSS:pvdo.FRAM"
The following example shows how to analyze the voltage drop on net VDD in the power
network. The power is analyzed by ICC and the voltage supply is 1.2V.
prompt> analyze_fp_rail\
-nets VDD\
-analyze_power\
-voltage_supply 1.2
SEE ALSO
create_fp_virtual_pad(2)
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load_fp_rail_map(2)
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analyze_library
Provides library cell analysis according to the specified parameters.
SYNTAX
analyze_library
[-multi_vth]
[-ignore_dont_use_attribute]
[-graph filename]
[list_of_libraries]
Data Types
filename
list_of_libraries
file
list
ARGUMENTS
-multi_vth
Specifies that the analysis should report the multiple-threshold-voltage characteristics of
the libraries.
-ignore_dont_use_attribute
Specifies that the library analysis should ignore the don't-use attributes when excluding
the cells for analysis.
-graph filename
Specifies the file name for the graph which represent the library analysis. The graph is
written in SVG format.
list_of_libraries
Specifies a list of .db files of libraries to be analyzed. The command assumes that each
library is completely setup, which means the .db file location is included in the
search_path variable setting, the don't-use cells are identified, the threshold voltage
groups are labeled, etc. If a list of libraries is not specified, all target libraries, specified
by using the target_library variable, are used by default.
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DESCRIPTION
This command allows you to compare the characteristics of different libraries.
The -multi_vth option generates a report which compares the leakage per area versus
timing characteristics of the cells of each threshold-voltage group in the specified libraries,
excluding macros, black box cells, ICG cells, library cells flagged as don't-use, library cells
with unknown LEF IDs, and library cells with a LEF ID that is not supported by all the main
threshold-voltage groups among the libraries.
If a cell does not have a threshold-voltage group label and it belongs to a library without a
default threshold-voltage group label, the cell is classified by its parent library name.
The command analyzes all the libraries that are loaded from the list of libraries provided with
the command. If this list is empty, it loads the libraries specified by the target_library
variable. The command reports the geometric average of the leakage power per area and
timing of the valid cells in each threshold-voltage group, normalized by the values obtained
for the threshold-voltage group with the smallest leakage power per area (flagged as
Baseline). At the same time, for each threshold-voltage group, it reports the number of
library cells flagged as don't-use cells, together with the total number of library cells
classified as part of the threshold-voltage group.
If a threshold-voltage group has all its cells flagged as don't-use cells, the command reports
only its name. All the library cells are excluded from the report. If there is no or only one VT
group defined each library file will be treated as a single VT group.If the command is not able
to identify more than one VT groups,it will exit without reporting anything. :
EXAMPLES
The following example shows an analysis report generated by the analyze_library -multi_vth
command:
prompt> analyze_library -multi_vth
*******************************************************************
Multi-VT Library Analysis Report
Vth Group/Library Name
Avg.
Avg.
(dont_use cells/total cells)
Leakage
Timing
*******************************************************************
LVT31 (0/998)
1.83
1.57
SVT31 (0/998)
1.00
1.00 (Baseline)
ULVT31 (0/998)
4.88
3.75
*******************************************************************
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SEE ALSO
set_dont_use(2)
remove_attribute(2)
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analyze_logic_connectivity
Invokes the Design Planning Data Flow Analyzer to assist in improving macro placement
through connectivity tracing and analysis.
SYNTAX
status analyze_logic_connectivity
ARGUMENTS
This command has no arguments.
DESCRIPTION
This command launches the Design Planning Data Flow Analyzer, a macro-to-macro and
macro-to-I/O connectivity analysis tool. The tool helps you determine the strength of
connection between macros and between macros and I/Os as you navigate through the
design with the GUI. For instance, you can run the "Macro or IO Weight Virtual Flyline
Analysis" utility under the Display menu to open the tracing initialization window. After
tracing is complete, you can select macros or I/Os in the layout window and display flylines
with weight values. Flylines with the largest weight have the strongest connection between
the objects.
The Design Planning Data Flow Analyzer supports manual modification of the macro
placement. You can perform a connectivity analysis and use the macro tool box or macro
array editor to create a better macro placement.
Before using the Design Planning Data Flow Analyzer, you should run the link,
initialize_floorplan, and create_fp_placement commands on your design.
Use the connectivity analysis results from the Design Planning Data Flow Analyzer to
determine the macro-to-macro and macro-to-I/O connection strength. Refining the macro
placement can produce a better standard cell placement, resulting in improved design
timing and congestion.
EXAMPLES
The following command invokes the Design Planning Data Flow Analyzer:
analyze_logic_connectivity
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prompt> analyze_logic_connectivity
SEE ALSO
create_fp_placement(2)
Chapter 1:
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Commands
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Version L-2016.03
analyze_mv_design
Analyzes multivoltage design connections.
SYNTAX
status analyze_mv_design
[-level_shifter | -always_on]
[-from_pin from_pin_list]
[-to_pin to_pin_list]
[-net target_net]
[-verbose]
Data Types
from_pin_list
to_pin_list
target_net
list
list
list
ARGUMENTS
-level_shifter
Enables level-shifter analysis, which is based on load-to-driver pin arguments.
-always_on
Enables always-on analysis, which is based on the target net argument.
-from_pin from_pin_list
Specifies the driver (leaf cell pin or top-level port) for level-shifter analysis.
-to_pin to_pin_list
Specifies the loads (leaf cell pins or top-level ports) for level-shifter analysis.
-net target_net
Specifies the net for always-on analysis.
-verbose
Generates detailed information in the report.
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DESCRIPTION
The analyze_mv_design command performs multivoltage analysis and reports design
details that can help you understand multivoltage-related issues. You can perform either
level-shifter or always-on analysis by using the -level_shifter or -always_on option.
The level-shifter analysis lists variable settings, power state table information, signal
connections, and library availability information. The input for the level-shifter analysis is a
pin-to-pin connection, which can be derived easily from the output of the check_mv_design
command.
The following variable settings are reported in the level-shifter analysis output:
•
Level Shifters on clock nets:
•
This setting is controlled by the auto_insert_level_shifters_on_clocks variable. It
specifies the list of clock nets considered for automatic level shifter insertion. If the value
is "all", every clock net it considered. The default is "all".
•
Level shifter on top nets:
•
This setting is controlled by the compile_no_new_cells_at_top_level variable. It
controls the capability of the tool to insert level-shifter cells at top level. When the
variable value is set to true, no new level-shifter cells are accepted. The default is false.
•
Level shifters allowed on leaf pin boundary:
•
This setting is controlled by mv_allow_ls_on_leaf_pin_boundary variable. When the
setting is true, the tool is allowed to insert level shifters at any driver or load pins of a net,
even if the pins are not on a power domain boundary. The default is false.
The always-on analysis reports details about always-on constraints, related supply nets,
relevant power state table settings, and library cell availability for the target net.
EXAMPLES
The following command analyzes a specified level-shifter connection:
prompt> analyze_mv_design -level_shifter \
-from_pin gprs_nrestore -to_pin GPRs/A_reg_reg[0]/NRESTORE
...
Level Shifter Analysis (1/1)
from driver pin 'gprs_nrestore', to load pin 'GPRs/A_reg_reg[31]/
NRESTORE'
*************************************
Level Shifter Analysis - Settings
*************************************
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Level Shifters on clock nets:
Level Shifters on top nets:
Level Shifters allowed leaf pin boundary:
all
TRUE
FALSE
********************************************************
Level Shifter Analysis - Driver and Load Related PST
********************************************************
Current Scope: ChipTop
Supply Names: VDD, VSS, VDDG,
Resulting Power States in this Scope:
VDD| VSS|VDDG|
drv: HV| GND| HV|
drv: HV| GND| LV|
********************************************************
Level Shifter Analysis - Drive to Load Pins and Nets
********************************************************
From Pin:
gprs_nrestore
Related Supplies: VDD; VSS;
To Pin:
GPRs/A_reg_reg[31]/NRESTORE
Related Supplies: VDDG; VSS;
-------------------------------------------------------Pin: =domain boundary=
Type:
Constraint:
gprs_nrestore;
Design Port; Domain Boundary;
not defined
Net:
gprs_nrestore;
Domain:
TOP;
Local Fanout:
1;
Primary Supply Nets:
VDD, VSS,
Available Supply Nets: VDD, VSS, VDDI, VDDIS, VDDG, VDDM,
- Driver pin related supply nets (VDD, VSS) and load pin related supply
nets
(VDDG, VSS) are available in the domain 'TOP'
- Driver pin related supply nets (VDD, VSS) are the primary supplies in
the
domain 'TOP'
Pin: =domain boundary=
Type:
Constraint:
GPRs/gprs_ret1;
Hierarchical Port; Domain Boundary;
not defined
Net:
GPRs/gprs_ret1;
Domain:
GPRS;
Local Fanout:
608;
Primary Supply Nets:
VDDGS, VSS,
Available Supply Nets: VSS, VDDG, VDDGS,
- Neither driver pin related supply nets (VDD, VSS) nor load pin
related
supply nets (VDDG, VSS) are primary supplies in the domain 'GPRS'
Pin:
Type:
GPRs/A_reg_reg[31]/NRESTORE;
Cell Input Pin; Lib Cell: RSDFCSRHD2BWP;
*********************************************
Level Shifter Analysis - Target Libraries
*********************************************
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Required pin-to-pin level shifter type: H2L
All level shifters cells found in the target libraries: 12
Usable level shifter cells: 12
Usable level shifter cells of type H2L: 4
Lib Cell 'mylib_wc09072/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_wc0909/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_bc11088/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
Lib Cell 'mylib_bc1111/LVHL' works in the required voltage range:
Input voltage range [0.700 - 1.300]
Output voltage range [0.700 - 1.300]
1
SEE ALSO
check_mv_design(2)
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analyze_rail
Performs the targeted rail analysis on the specified nets using the PrimeRail tool.
SYNTAX
status analyze_rail
nets
[-integrity]
[-voltage_drop]
[-electromigration]
[-inrush]
[-min_path_resistance]
[-primerail_script_file primerail_script
| -script_only]
[-result result_name]
[-replace_result]
[-decap]
Data Types
nets
primerail_script
result_name
collection or list
string
string
ARGUMENTS
nets
Specifies the power and ground nets to be analyzed.
The tool considers all the switched or internal power nets of the specified power nets in
the analysis. You do not need to explicitly specify the internal power nets.
-integrity
Performs connectivity checking on the specified power and ground nets.
When enabled, the tool checks for missing vias, floating shapes, dangling vias, and
floating pin shapes. It reports power and ground network integrity violations in a
Milkyway error view.
-voltage_drop
Performs voltage drop analysis on the specified power and ground nets.
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When enabled, the tool checks for voltage drop violations. It generates a voltage drop
map, parasitics map, and power map. In addition, it reports the voltage drop violations in
a text file and in a Milkyway error view.
-electromigration
Performs electromigration analysis on the specified power and ground nets.
When enabled, the tool analyzes the current density on the specified nets and identifies
the segments with potential electromigration issues. It also calculates the
electromigration violations based on the default rules that are loaded in the Milkyway
design library. It generates an electromigration map and reports the electromigration
violations in a Milkyway error view.
-inrush
Performs inrush current analysis on the specified power and ground nets.
When enabled, the tool generates a Fast Signal Database (FSDB) file, voltage drop
map, and parasitics map.
-min_path_resistance
Performs minimum path resistance analysis on the specified power and ground nets.
When enabled, the tool generates a minimum path resistance map.
-primerail_script_file primerail_script
Specifies and uses an existing PrimeRail script to perform the PrimeRail run.
This script is usually generated from an earlier analyze_rail run.
When you use this option, all other options are ignored. For example, if you run the
analyze_rail -voltage_drop -primerail_script_file myscript.tcl command, the tool
ignores the -voltage_drop option.
This option and the -script_only option are mutually exclusive.
-script_only
Generates the PrimeRail script and the input data for the target analysis, such as
integrity, voltage drop, or electromigration, without actually executing the analysis run.
This allows you to modify and reuse the run script as desired.
This option and the -primerail_script_file option are mutually exclusive.
-result result_name
Specifies the name for the generated rail results cache.
The default is RAIL_RESULT.
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-replace_result
Enables the tool to overwrite an existing rail results cache.
If the specified rail results cache exists and you do not use this option, the command
fails.
DESCRIPTION
This command prepares the data needed for PrimeRail rail analyses, and then calls
PrimeRail to perform the specified rail analysis run. The supported rail analyses are voltage
drop analysis, electromigration analysis, inrush current analysis, minimum path resistance
analysis, and integrity checking. You can also use a previously generated PrimeRail
command script to perform the analyses.
The PrimeRail tool generates results data that can be queried in the IC Compiler tool, as well
as map data that can be viewed in the IC Compiler GUI. The map files are saved to the
output_dir/rail_map_data directory at the end of the run.
PrimeRail also generates error views that capture violations found during the analysis. You
can display the errors in the error browser, depending on the analysis options you chose.
You can perform multiple analyses, such as voltage drop and electromigration, in a single
run.
When the -analysis_mode option is set to static with the set_rail_options command, the
analyze_rail command performs static voltage drop and electromigration analyses and
generates the following information:
•
Average voltage drop values in a map file
•
Average electromigration values in a map file
•
An error cell with average electromigration values
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example performs static voltage drop analysis:
prompt> set_rail_options -default
prompt> analyze_rail {VDD VDDV}
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The following example performs power and ground network integrity analysis:
prompt> set_rail_options -user_defined_taps VDD_tap.txt
prompt> analyze_rail VDD -integrity
The following example performs power and ground network integrity analysis and voltage
drop analysis:
prompt> analyze_rail {VDD VSS} -integrity -voltage_drop
The following example performs minimum path resistance analysis:
prompt> set_rail_options -user_defined_taps VDD_tap.txt
prompt> analyze_rail VDD -min_path_resistance
EXAMPLES
The following example performs static voltage drop analysis and stores the results in a rail
result cache named static.
prompt> analyze_rail {VDD VSS} -voltage_drop -result static
The following example performs static voltage drop analysis and stores the results in a rail
result cache named static. If there is an existing rail result cache named static, the tool
replaces the results with the new results.
prompt> analyze_rail {VDD VSS} -voltage_drop \
-result static -replace_result
SEE ALSO
report_rail_options(2)
set_rail_options(2)
remove_rail_integrity_layout_check_strategy(2)
report_rail_integrity_layout_check_strategy(2)
set_rail_integrity_layout_check_strategy(2)
verify_rail_integrity(2)
write_rail_options(2)
open_rail_result(2)
close_rail_result(2)
rail_indesign_shell_mode(3)
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analyze_subcircuit
Invokes circuit simulation on a subcircuit of the current design. This command is suitable for
analyzing clock meshes.
SYNTAX
status analyze_subcircuit
[-name string]
[-to net_or_pins]
[-analysis_mode max | min | max_then_min]
[-effort low | medium | high]
[-simulator name_of_simulator]
[-spice_header_files list_of_files]
[-driver_subckt_files list_of_files]
[-starrcxt_map_file file_name]
[-configuration list_of_scenario_configurations]
[-output_directory directory]
[-input_rise_transition transition_time]
[-input_fall_transition transition_time]
[-period pulse_duration]
[-clock clock_name]
[-no_extraction]
[-from pins]
[-tie_high pins_or_nets]
[-tie_low pins_or_nets]
[-zero_resistance nets]
[-reset_annotation]
[-purge_all_annotations]
[-projected_loads load_configuration]
[-projected_drivers driver_configuration]
[-projected_input_skew input_skew_configuration]
[-probe_wires net]
[-verbose]
[-starrcxt_nxtgrd_file ]
Data Types
string
net_or_pins
pins
name_of_simulator
list_of_files
list_of_scenario_configurations
directory
transition_time
clock_name
pins
pins_or_nets
nets
analyze_subcircuit
name_of_simulator
collection of one net or multiple
string
list
list
path
float > 0.0
string
collection
collection
collection
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driver_configuration
input_skew_configuration
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list
list
list
ARGUMENTS
-name string
Specifies the name of this subcircuit, which is used to distinguish it from other subcircuits
in the same design. The string is used to construct both circuit elements and file names,
so it must only contain alphanumeric characters and underscores. With that restriction,
you can use any name, but if a clock is being analyzed you should use the name of the
clock (if this is unique). Many files are generated based on this name.
-to net_or_pins
Specifies a collection of input pins that are driven by the circuit. If you specify a single
net, the input pins associated with the net are included as load pins. (In earlier releases,
the option was known as -load.)
-analysis_mode max | min | max_then_min
Specifies how buffer delays are calculated. If set to max, the delays for the buffers are
calculated using their maximum delay value. If set to min, their minimum delay value is
used. If set to max_then_min, maximum analysis is performed, followed by minimum
analysis. You can use this option only if the TLUPlus specifies two corners.
-effort low | medium | high
Specifies the precision of the analysis done by the simulator. The effort setting is
reformatted to suit the input syntax of the circuit simulator and sent as a parameter to the
circuit simulation engine to control the precision of its analysis. The default is low.
-simulator name_of_simulator
Specifies which simulator to use. Only hsim, hspice, hspice64, and nanosim simulators
are supported. The default is nanosim. The simulator you want to use must be available
as a working, and properly licensed Linux command in your shell path. You may need to
adjust the path in your .cshrc or .login file.
-spice_header_files list_of_files
Specifies the locations of the spice device models of the transistors. Spice device
models are needed for all the transistors. You specify the device models with the file
path, and the file paths are copied into the simulator input. If you specify multiple files,
they are included in the order specified. Note that file locations are relative to the current
working directory (not relative to the temporary working directory, as was done in some
earlier versions of mesh analysis).
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-driver_subckt_files list_of_files
Specifies the locations of the subcircuit models of the buffers in the clock mesh tree. The
circuit simulator requires a subcircuit model for all the buffers in the clock mesh tree. You
specify the subcircuit models with the file path, and the file paths are copied into the
simulator input. If you specify multiple files, they are included in the order specified. Note
that file locations are relative to the current working directory.
-starrcxt_map_file file_name
Specifies the file name that contains the physical layer mapping information between the
input database and the nxtgrd file. This file maps every TCAD process layer to a
corresponding layer of layout database. This is a mandatory option if you want to use
StarRC for extraction.
-configuration list_of_scenario_configurations
Specifies the SPICE settings for each scenario to be analyzed. The list can be of any
length.
The format of the list_of_scenario_configurations argument is
-configuration {
{-scenario_name scenario
[-max_driver_subckt_files max_files]
[-max_spice_header_files header_max]
[-min_driver_subckt_files min_files]
[-min_spice_header_files header_min]
} ...
}
The -scenario_name option is a required option and the specified name must be the
same as the name used in the create_scenario command that created the scenario.
If you do not specify the -max_driver_subckt_files or -min_driver_subckt_files
option for a scenario, that scenario uses the files specified in the -driver_subckt_files
command option. If you do not specify the -max_spice_header_files or
-min_spice_header_files option for a scenario, that scenario uses the files specified in
the -spice_header_files command option.
-output_directory directory
Specifies the directory used to contain the simulation driving files and the results of the
simulation. If you do not specify this option, the -name option is used for the name of the
output directory. If no directory by this name exists, one is created. Because many files
are created in this directory, you must specify a directory with write permissions and
sufficient disk space.
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-input_rise_transition transition_time
Specifies the rise transition time for the root of the subcircuit. This value must be greater
than zero. The parameter overrides any rise transition time otherwise observable in the
circuit.
If you do not specify this option, the tool considers all the clocks found at the root of the
subcircuit, and uses the slowest rise transition time.
-input_fall_transition transition_time
Specifies the fall transition time for the root of the subcircuit. This value must be greater
than zero. The parameter overrides any fall transition time otherwise observable in the
circuit.
If you do not specify this option, the tool considers all the clocks found at the root of the
subcircuit, and uses the slowest fall transition time.
-period pulse_duration
Controls the waveform (width of the pulse) applied at the root node. This value must be
greater than zero.
If you do not specify this option, the tool uses a pulse with half the width of the relevant
clock period. In general, you should not have to change this option.
-clock clock_name
Specifies for which clock domain the analysis should be done. This especially helps to
select the appropriate clock path when multiple clocks arrive at pins of a cell in the clock
mesh circuitry.
-no_extraction
Controls whether the tool runs the extract_rc command to extract parasitics before
writing the simulation driving files.
By default, the tool runs the extract_rc command. If your design already has current
parasitic information written in the output directory from a previous run, you can
suppress extraction to save time.
-from pins
Specifies the startpoint to analyze a circuit.
If you do not specify this option, the command automatically determines a single driving
point of a clock tree based on the load of the clock tree. If you design the tree from the
loads up, specify the pins to be driven for timing purposes. You must specify this option
if you are analyzing circuits with complex cells such as AND gates, multiplexers, and
integrated clock-gating (ICG) cells. (In earlier releases, This option was known as
-inputs.)
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-tie_high pins_or_nets
Holds the specified nets (or the nets attached to the specified pins) at logic 1 during
simulation. If you specify a net, it is equivalent to specifying all the pins on that net.
This option is for advanced users only and might be useful for enable pins.
-tie_low pins_or_nets
Holds the specified nets (or the nets attached to the specified pins) at logic 0 during
simulation. If you specify a net, it is equivalent to specifying all the pins on that net.
This option is for advanced users only and might be useful for disable pins.
-zero_resistance nets
Sets the wire resistance for the specified nets to zero to perform "what if" analysis.
This option is for advanced users and can be used to estimate the amount of skew that
has been introduced by wire resistance.
-reset_annotation
Removes the mesh timing annotation data from the previous analyze_subcircuit
session from a single net.
You must use this option together with the -to option.
-purge_all_annotations
Removes the mesh timing annotation data from the previous analyze_subcircuit
session from the entire design.
-projected_loads load_configuration
Specifies additional loads that are to be included in the simulation in accordance with the
configuration list. The configuration list defines projected load groups that are included
in the simulation. You can define any number of projected load groups in the
configuration list.
The format of the projected loads configuration list is
-projected_loads {
{-within rectangle
[-capacitance capacitance_value]
[-load_pin library_pin -number_of_loads positive_integer]
[-load_wire_capacitance capacitance_value]
}...
}
The -within option is required for each projected load group. It defines the mesh
elements to which additional capacitance is added. Only mesh elements within the
specified rectangle are in the load group.
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You can specify the additional capacitance in the following ways:
* Use the -capacitance option to specify a capacitance value.
This value is added to all mesh elements in the load group.
* Use the -load_pin option to specify a load pin.
This is typically the name of a buffer or an integrated clock-gating
cell (ICG). The tool multiplies the capacitance attribute of the
specified pin by the value of the -number_of_loads option
and adds this value to all mesh elements in the load group. The
-number_of_loads option estimates the number of integrated
clock-gating cells (ICGs) and buffer loads found within the
specified region.
* Use the -load_wire_capacitance option to specify a small
capacitance value that is added to the value associated with each
load pin to model the comb routing to the pin.
The specified capacitance is added to the load pin capacitance, which is calculated by
adding the load pin capacitance to the wire capacitance times the number of loads. This
capacitance is modeled as being distributed uniformly over the mesh straps in the
specified region.
If you specify multiple projected load region statements, their effect is cumulative. That
is, the capacitance at a point is impacted by the sum of all the projected load statements
that overlap it.
When constructing the projected groups configuration for a hierarchical design, you can
get the bounding box of a cell or soft macro from its bbox attribute. You can get the
capacitance of a library pin, for your own reference, from its capacitance attribute.
For example, you can define two projected load regions with this syntax:
analyze_subcircuit -name testc ... -projected_loads {
{-within {{100.0 300.5} {800.0 440.6}}
-capacitance 0.3e-12
-load_pin tcbn90ghphvtwc/BUFFHVTD24
-load_wire_cap 0.001e-12
-number_of_loads 1000}
{-within {{l900.0 2300.5} {3800.0 2440.6}}
-load_pin tcbn90ghphvtwc/BUFFHVTD24
-number_of_loads 1000}
}
-projected_drivers driver_configuration
Specifies additional drivers that are to be included in the simulation in accordance with
the configuration list. The configuration list defines projected drivers that are included in
the simulation. You can define any number of projected drivers in the configuration list.
To run analyze_subcircuit, your design must first have a mesh driver at each location
where a driver might be needed. With this option, you can change the number and type
of drivers seen by the simulation. This allows you to experiment with various drivers to
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get the set of drivers that is sufficient to drive your design reliably without overdriving the
mesh and wasting power and area.
The configuration list defines the projected drivers that are included in the simulation.
You can define any number of projected drivers in the configuration list.
The format of the projected drivers configuration list is
-projected_drivers {
{-within rectangle | -nearest point
[-replicate integer]
[-projected_lib_cell lib_cell]
}...
}
To identify the affected mesh drivers, you must specify either the -within option or
-nearest option for each driver group. When you use the -within option, the
specification affects the mesh drivers within the specified rectangle. When you use the
-nearest option, the specification affects the mesh driver that is nearest to the specified
point. The -nearest option might be effective for tuning the design based on the results
of a previous analysis.
You can use the following options to specify additional drivers:
* -replicate
When you use this option, the simulation model includes the specified
number of drivers in parallel for each affected mesh driver.
For example, if you specify -replicate 4, the SPICE simulation
sees your original mesh driver plus three new ones in parallel. Note
that these driver cells are not actually added to the design and they
do not have locations or routing associated with them.
The only tool that sees them is the SPICE simulation.
You should not specify a value of 0. If you do, the SPICE simulation
does not see the original cell; that is, part of the mesh that is not
driven.
However, any routing parasitics associated with the comb route from
its output pin are retained regardless of the value of this parameter.
Because mesh drivers are typically close to the mesh and are
therefore short and of low capacitance, this should not be a major
inaccuracy.
* -projected_lib_cell lib_cell
When you use this option, the simulation uses the specified library
cell instead of the actual mesh driver.
If you specify multiple projected driver groups and their geometric regions overlap on a
driver, they are processed in the order they appear, and only the final one impacts the
driver. This can be used to specify a projected driver for the entire design in one large
region and to specify additional driver sizing in a series of small regions.
For example, you can define two projected driver groups with this syntax:
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analyze_subcircuit -name testc ... -projected_drivers {
{-within {{100.0 300.5} {800.0 440.6}} -replicate 4}
{-within {{l900.0 2300.5} {3800.0 2440.6}}
-projected_lib_cell tcbn90ghphvtwc/BUFFHVTD24}
}
-projected_input_skew input_skew_configuration
Specifies that simulation is to model skew on the input pins of the mesh drivers.
One of the major motivations for using a clock mesh is to reduce skew in the presence
of on-chip variation (OCV) or other imperfections in a standard clock tree. Because the
premesh tree design flow generally produces a low-skew tree, to determine how
effective the mesh would be at skew reduction is difficult. Because skew reduction is
determined mainly by the width and pitch of the mesh, you are likely to create excess
mesh straps unless you perform OCV analysis. You can use the
-projected_input_skew option to calibrate the effectiveness of the mesh by simulating
the effect of delay on the mesh driver inputs in one or more regions.
The worst case OCV probably occurs when a clock tree driver is close to the root of the
premesh tree that has a very large additional delay, which might make half of what the
chip sees as a large mesh driver input delay. If you consider this case too pessimistic,
you might want to take only one quarter of the chip; that is, probably the quadrant with
the largest load. Add delays to the mesh driver inputs in that quadrant by one typical
gate delay.
The skew configuration list defines the delay to simulate on the mesh driver inputs in a
region. You can define any number of input skew groups in the configuration list.
The format of the skew configuration list is
-projected_input_skew {
{-within rectangle
-rise_delay time
-fall_delay time
[-rise_transition time]
[-fall_transition time]
}...
}
The -within option is required for each input skew group. It defines the mesh drivers for
which to model skew. Only mesh drivers within the specified rectangle are in the input
skew group. If you specify multiple input skew groups, the specified geometric regions
must not overlap.
You can specify the following delay values for each input skew group:
* -rise_delay
Delays the input waveform for the rising edge by the specified time.
You must specify this value for each input skew group.
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* -fall_delay
Delays the input waveform for the falling edge by the specified time.
You must specify this value for each input skew group.
* -rise_transition
Specifies the rising transition time for the input waveform.
If you do not specify this option, the simulation uses the rising
transition time of the root of the tree.
* -fall_transition
Specifies the falling transition time for the input waveform.
If you do not specify this option, the simulation uses the falling
transition time of the root of the tree.
For example, if the mesh has an active area of 3000 by 4000 microns with the largest
loads in the lower right quadrant and a gate delay is 0.025 ns, define the input skew
group as follows:
analyze_subcircuit -name testc ... -projected_input_skew {
{-within {{1500.0 0.0} {3000.0 2000}}
-rise_delay 0.025 -fall_delay 0.020
-rise_transition 0.1 -fall_transition 0.08}
}
-probe_wires net
Specifies that extraction is to insert probe points at regular intervals along the wires of
the specified net, which is typically a clock mesh net. You can specify only a single net.
These probe points allow analysis to separate the skew on the mesh from the skew on
the loads, which is typically larger and more random, so each can be addressed and
minimized appropriately.
Circuit performance in a clock mesh is determined by the efficacy of the drivers, mesh
straps, and the routing from the mesh straps to the loads. Sometimes it is useful to
distinguish between the delays and skew on the mesh straps and the skew induced by
the comb routing to the load pins. The -probe_wires option causes the extraction to
insert probe points along the long wires associated with the specified net. Short wires do
not have probe points added. The spacing between probe points is determined by the
tool. After simulation, the tool prints out a summary of the maximum, minimum, and
average latency and transition times observed on these probe points. This summary
might be useful for tuning the distribution of mesh drivers and adjusting the widths of the
mesh straps. Only one net might be so instrumented.
You can use this option only when you use StarRC for extraction.
-verbose
Displays the extraction and circuit simulation messages to the console.
By default, these messages are redirected into log files in the output directory.
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-starrcxt_nxtgrd_file
Specifies the tcad grd file that contains conductor sheet resistance and models for 3-D
parasitic capacitance calculation for StarRC. This is a mandatory option if you want to
use StarRC for extraction. You need to specify one file for every scenario corner in the
proper order in the list.
DESCRIPTION
Within IC Compiler, timing prediction is generally done with static timing analysis. But for
some purposes, such as clock meshes, it is necessary or desirable to use circuit simulation.
This command generates the necessary files to run a circuit simulator, invokes the simulator,
and reads the output of simulation back into your design as annotations for delay and
transition times.
By default, the analyze_subcircuit command extracts and simulates the circuit as it stands.
You can also use this command to perform "what if" analysis to see how the mesh would
behave with additional loads or different drivers. This is especially important in large
hierarchical designs where the turnaround time of physical synthesis can be long and the
need for upfront analysis is greater. For details about specifying additional loads, see the
description for the -projected_loads option. For details about specifying additional drivers,
see the description for the -projected_drivers option. For details about modeling input
skew, see the description for the -projected_input_skew option.
Files
Inputs required:
You must have a circuit-level model for each of the buffer gates in your clock tree, and a
transistor model for each of the transistors in the circuit models.
Files generated:
This command creates the output directory if it is not already present, and populates it with
files for simulation and annotation. These include the circuit files, command files, and
measurement files. One of these files is a shell script that is used to invoke the circuit
simulator. Simulation produces many output and log files, which also populates the
directory. This command then processes those output files and generates an annotation file.
This file can be sourced into your design, to update the delays and transition times of your
subcircuit to match the circuit simulation results.
Limitations
The subcircuit to be is analyzed is modeled as being by a single signal. That signal is applied
at the unique point, determined automatically by traversing the circuit from the load pins,
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through any buffers, and stopping at an input port or a multiple input gate. The circuit to be
simulated must not have any "side inputs." It does timing from one point to many.
If you want to analyze a set of mesh drivers whose inputs are not yet connected, you can do
this by using the -from option and listing all the mesh driver input pins. For the purpose of
simulation, these are all driven in parallel, with no skew among them. This type of simulation
is only for early exploration, before the clock tree "above" the mesh drivers has been
designed.
Buffers that are "shorted together" in a mesh or other structure are supported. The
resistance and capacitance of the mesh is determined by extraction, and is expressed in a
parasitic input file with values obtained the IC Compiler extractor or StarRC.
The entire subcircuit must be in the top level of the current Milkyway design. It must not
extend into a block or subdesign.
The underlying circuit simulator is not case-sensitive, so elements "buff_27" and "BUFF_27"
are indistinguishable, and the design must not contain both names. For similar reasons,
circuit elements should not contain the dot character ".".
NanoSim simulator generally models coupling among the elements of the clock tree itself.
The simulation of the tree accepts a transition time for the root gate. If the tree is driven by
multiple clocks and the input signal has widely divergent transition times when operating in
the various modes, this effect are not modeled. The loads of the flip-flops are modeled by
lump capacitance, not by active transistor models. If this operation is done before the signal
nets have been routed, which would normally be the case, the final gate placement, routing
geometry and detailed placement might not match the geometry in the final chip. There is no
modeling of IR drop in the power or ground wires. The actual VSS and VDD used for each
buffer gate is assumed to be static and is determined before simulation starts.
For more information on simulation see the NanoSim User Guide the HSIM User Guide, or
HSPICE documentation.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
In the following example, a clock tree called clk1 has been implemented with a set of
specified library references to be used as buffers, driving a clock mesh net called mesh_net.
After this command has been run, the report_timing and report_clock_tree commands
reflects the delays and transitions observed in the circuit simulation.
prompt> analyze_subcircuit -name clk1 -to mesh_net \
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-output_directory clk_working \
-spice_header_file original/models.sp \
-driver_subckt_file {original/drivers.sp extra_cells.sp}
The following command uses the HSIM simulator for analysis.
prompt> analyze_subcircuit -name clk1 -to mesh_net \
-output_directory clk_working \
-spice_header_file original/models.sp \
-simulator hsim \
-driver_subckt_file {original/drivers.sp extra_cells.sp}
In the following example, a clock tree called clk2 has been implemented with a set of
specified library references used as buffers driving a set of pins, but not using a mesh net.
prompt> set load_pins \
[get_pins {addr_reg[27]/CP S45_reg[6]/CP S47_reg[13]/CP \
S37_reg[10]/CP}]
prompt> analyze_subcircuit -name addr -to $load_pins \
-spice_header_file original/models.sp \
-driver_subckt_file original/drivers.sp -effort high
If each scenario has a different SPICE file or header file, you should use the -configuration
option to specify these files, as shown in the following example.
prompt> analyze_subcircuit -to clk \
-driver_subckt_files max_spice_model \
-spice_header_files header_file \
-config {
{-scenario_name scenario1
-max_driver_subckt_files max_spice_model_1
-max_spice_header_file max_header_file_1}
{-scenario_name scenario2
-max_spice_header_file max_header_file_2}
}
SEE ALSO
create_clock_mesh(2)
add_clock_drivers(2)
compile_premesh_tree(2)
route_mesh_net(2)
create_scenario(2)
compile_clock_tree(2)
set_extraction_options(2)
report_clock_tree(2)
set_annotated_delay(2)
set_annotated_transition(2)
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append_to_collection
Adds objects to a collection and modifies a variable.
SYNTAX
collection append_to_collection
[-unique]
var_name
object_spec
Data Types
var_name
object_spec
collection
list
ARGUMENTS
-unique
Indicates that duplicate objects are to be removed from the resulting collection. By
default, duplicate objects are not removed.
var_name
Specifies a variable name. The objects matching object_spec are added into the
collection referenced by this variable.
object_spec
Specifies a list of named objects or collections to add.
DESCRIPTION
The append_to_collection command allows you to add elements to a collection. This
command treats the variable name given by the var_name option as a collection, and it
appends all of the elements in object_spec to that collection. If the variable does not exist, it
is created as a collection with elements from the object_spec as its value. If the variable
does exist and it does not contain a collection, it is an error.
The result of the command is the collection that was initially referenced by the var_name
option, or the collection created if the variable did not exist.
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The append_to_collection command provides the same semantics as the common use of
the add_to_collection command; however, this command shows significant improvements
in performance.
An example of replacing the add_to_collection command with the append_to_collection
command is provided below. For example,
set var_name [add_to_collection $var_name $objs]
Using the append_to_collection command, the command becomes:
append_to_collection var_name $objs
The append_to_collection command can be much more efficient than the
add_to_collection command if you are building up a collection in a loop. The arguments of
the command have the same restrictions as the add_to_collection command. For more
information about these restrictions, see the add_to_collection man page.
EXAMPLES
The following example from PrimeTime shows how a collection can be built up using the
append_to_collection command:
prompt> set xports
Error: can't read "xports": no such variable
Use error_info for more info. (CMD-013)
prompt> append_to_collection xports [get_ports in*]
{in0 in1 in2}
prompt> append_to_collection xports CLOCK
{in0 in1 in2 CLOCK}
SEE ALSO
add_to_collection(2)
foreach_in_collection(2)
index_collection(2)
remove_from_collection(2)
sizeof_collection(2)
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apply_fast_pba_analysis
Performs fast path-based slack adjustment to reduce pessimism during timing analysis
using advanced on-chip variation (AOCV) analysis.
SYNTAX
status apply_fast_pba_analysis
[-check_only file_name]
Data Types
file_name
string
ARGUMENTS
-check_only file_name
Writes the set_path_margin timing exceptions to the specified file without executing the
command or applying any timing adjustments to the design. You can source the
generated file to actually apply the timing adjustments.
DESCRIPTION
This command performs fast path-based advanced on-chip variation (AOCV) analysis to
reduce pessimism of the timing analysis.
Advanced on-chip variation (AOCV) analysis is an optional method of pessimism reduction
that applies varying timing derating factors for different paths. It applies higher derating
values to short paths and lower derating values to long paths. To invoke AOCV, you set the
timing_aocvm_enable_analysis variable to true and read in a set of derating tables with
the read_aocvm command. By default, AOCV considers the shortest path leading up to
each endpoint to determine the derating value for that endpoint. It applies that same
derating value to all paths leading up to that endpoint, including longer paths, giving
pessimistic results for those paths.
When you use AOCV, you can further reduce pessimism by invoking the fast path-based
option of AOCV after you have used the route_opt command. This option selects a limited
number of worst paths leading up to each endpoint for analysis, and calculates a separate
(less pessimistic) derating value for each path in isolation from other paths, based on the
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actual number of stages in the path. The resulting slack from this calculation is larger (or less
negative) than for the default AOCV calculation. The fast path-based option then executes
a set_path_margin on each path, which adjusts the slack to a less pessimistic value for the
analyzed path.
You can apply the fast path-based option of AOCV by executing the
apply_fast_pba_analysis command. By default, the command applies the
set_path_margin commands immediately. Alternatively, you can use -check_only
file_name option to write the set_path_margin commands to a file, without applying them.
You can then examine the file and possibly execute it as a script using the source
command.
The generated margin values, if applied to the design, are reported by the report_timing
command. You can see the path_margin values in the timing report if they have been
applied.
Another way to invoke fast path-based AOCV analysis is to enable it with the
set_route_opt_strategy -fast_pba_analysis true command. In that case, the analysis and
timing adjustment occur during execution of the route_opt -incremental or focal_opt
command.
The reduced pessimism comes at a cost of runtime and memory. You can control the
tradeoff between accuracy and runtime/memory by setting the analysis options using the
set_fast_pba_analysis_options command.
To remove all the generated margin values, you can use remove_fast_pba_analysis
command.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example performs fast path-based AOCV analysis on the 20 worst paths for
each of the 5000 worst violating endpoints.
prompt> set_fast_pba_analysis_options -num_endpoints 5000
-paths_per_endpoint 20
prompt> apply_fast_pba_analysis
The following example performs fast path-based analysis and writes the resulting
set_path_margin commands to a file, without applying them to the design.
prompt> apply_fast_pba_analysis -check_only my_margin_setings.tcl
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SEE ALSO
remove_fast_pba_analysis(2)
set_fast_pba_analysis_options(2)
set_path_margin(2)
read_aocvm(2)
timing_aocvm_enable_analysis(3)
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apropos
Searches the command database for a pattern.
SYNTAX
string apropos
[-symbols_only]
pattern
Data Types
pattern
string
ARGUMENTS
-symbols_only
Searches only command and option names.
pattern
Searches for the specified pattern.
DESCRIPTION
The apropos command searches the command and option database for all commands that
contain the specified pattern. The pattern argument can include the wildcard characters
asterisk (*) and question mark (?). The search is case-sensitive. For each command that
matches the search criteria, the command help is printed as though help -verbose was
used with the command.
Whereas help looks only at command names, apropos looks at command names, the
command one-line description, option names, and option value-help strings. The search can
be restricted to only command and option names with the -symbols_only option.
When searching for dash options, do not include the leading dash. Search only for the
name.
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EXAMPLES
In the following example, assume that the get_cells and get_designs commands have the
-exact option. Note that without the -symbols_only option, the first search picks up
commands which have the string "exact" in the one-line description.
prompt> apropos exact
get_cells
# Create a collection of cells
[-exact]
(Wildcards are considered as plain characters)
patterns
(Match cell names against patterns)
get_designs
[-exact]
patterns
# Create a collection of designs
(Wildcards are considered as plain characters)
(Match design names against patterns)
real_time
# Return the exact time of day
prompt> apropos exact -symbols_only
get_cells
# Create a collection of cells
[-exact]
(Wildcards are considered as plain characters)
patterns
(Match cell names against patterns)
get_designs
[-exact]
patterns
# Create a collection of designs
(Wildcards are considered as plain characters)
(Match design names against patterns)
SEE ALSO
help(2)
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archive_design
Archives the specified designs to a new location.
SYNTAX
status archive_design
-source library_path
-design design_names
-archive archive_directory
[-complete]
[-overwrite]
[-include views | -exclude views]
[-include_ref_lib paths
| -exclude_ref_lib paths]
[-update_archive]
Data Types
library_path
design_names
archive_directory
views
paths
string
string
string
string
string
ARGUMENTS
-source library_path
Specifies the path to the Milkyway library that contains the specified designs.
This is a required option.
-design design_names
Specifies the Milkyway designs to archive.
To archive multiple designs, enclose the list of design names in quotation marks and
separate the names with space characters. To archive all designs in the main library, use
the asterisk character (*).
This is a required option.
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By default, the latest version of the design is archived, but you can specify a specific
version. For example, to archive version 3 of the top_design Milkyway design, use the
following option:
-design top_design;3
-archive archive_directory
Specifies the path to the new archive directory.
This is a required option.
-complete
Archives all designs in the reference libraries, even if they are not used in the specified
designs. Using this option allows the archived design to be further optimized later, if
needed, using the additional cells saved in the archive.
By default, the command archives cells in the reference libraries only if they are used by
the designs being archived.
This option cannot be used with the -include, -exclude, or -update_archive options.
-overwrite
Overwrites the existing archive destination.
This option cannot be used with the -update_archive option.
-include views
Specifies the views of the design to archive. You can use this option to reduce the
runtime and disk usage for archiving when you do not need all the views.
For example, to save only the FRAM view, use the following option:
-include FRAM
By default, all views of a design are archived.
This option cannot be used with the -complete or -exclude options.
-exclude views
Specifies the views of the design not to archive (all other views are archived). You can
use this option to reduce the runtime and disk usage for archiving when you do not need
all the views.
For example, to save all views except the err view, use the following option:
-exclude err
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By default, all views of a design are archived.
This option cannot be used with the -complete or -include options.
-include_ref_lib paths
Specifies the reference libraries to be included in the archive. All others are excluded.
You specify the references libraries as a list of paths separated by either commas or
spaces. Paths that do not exist or that do not point to directories trigger a warning
message and are ignored. Reference libraries that are located in or under one of the
valid paths are included in the archive directory. All other reference libraries are
excluded. You can use this option to reduce runtime and disk usage of this command
when not all reference libraries need to be copied.
If you do not specify this option or the -exclude_ref_lib option, all reference libraries that
contain designs used by the top-level design being archived are copied.
This option is mutually exclusive with the -exclude_ref_lib option.
-exclude_ref_lib paths
Specifies the reference libraries to be excluded from the archive.
You specify the references libraries as a list of paths separated by either commas or
spaces. Paths that do not exist or that do not point to directories trigger a warning
message and are ignored. Reference libraries that are located in or under one of the
valid paths are excluded from the archive directory. All other reference libraries that
contain designs used by the top-level design being archived are included.
If you do not specify this option or the -include_ref_lib option, all reference libraries that
contain designs used by the top-level design being archived are copied.
This option is mutually exclusive with the -include_ref_lib option.
-update_archive
Updates an existing archive. When you specify this option, new or modified cells since
the previous archive operation are copied over to the existing archive, while cells that
have not been modified remain unchanged.
This option cannot be used with the -complete or -overwrite options.
DESCRIPTION
This command copies the specified Milkyway design, logic libraries, and TLUPlus files and
creates a design_setup.tcl file in the specified archive directory. The purpose is to extract
one or more designs of interest from a library that contains many designs, leaving you with
a smaller, self-contained set of files for that design.
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Unless otherwise specified, the archive_design command copies the latest version of all
views of the designs being archived, and any subdesigns that are referenced directly or
indirectly by these designs. Note that the LM view is not archived. If you specify the
-complete option, all designs contained in the archived reference libraries are copied. The
main library and all needed reference libraries are placed in separate directories under the
design subdirectory. The library references maintained in the archived libraries are updated
to reflect the new locations of the reference libraries in the archive location.
The archive_design command uses the search_path, target_library, and link_library
variables to determine the logic .db libraries. The command also copies the minimum
libraries that are set by using the set_min_library command. If the variables are not set or
the files are not found, the logic libraries are not copied to the archive location. The logic
libraries are stored in the logic_db subdirectory.
The archive_design command archives the TLUPlus files that are defined with the
set_tlu_plus_files command. If no values have been specified or the files are not found, the
TLUPlus files are not copied. The TLUPlus files are stored in the tlu_plus subdirectory.
The design_setup.tcl file contains variable initializations that you can be sourced by the
user. It contains the values of the application variables from the current session, similar to
the output of the write_app_var command. The variable settings in the design_setup.tcl file
can be modified from the current session values to reflect the new archive location. This file
is stored in the root directory of the archive location.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows a typical usage of the archive_design command:
prompt> source ~/my_designs/ORCA/orig_data/design_setup.tcl
prompt> archive_design -source ~/my_designs/ORCA/design \
-design "icc_top_route icc_top_place" -archive my_archive \
-include "FRAM"
The following example includes any reference libraries under the /work/ref_libs/
macro_cell_libraries directory and the A.ref.mw reference library if they define cells used in
the design being archived. All other reference libraries are not included in the archive
directory.
Because the -complete option is specified, the included reference libraries are copied with
all of their cells.
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prompt> archive_design -source ~/my_designs/ORCA/design \
-design "icc_top_route icc_top_place" \
-archive my_archive -complete \
-include_ref_lib "/work/ref_libs/macro_cell_libraries \
../ref_libs/A.ref.mw"
SEE ALSO
set_tlu_plus_files(2)
search_path(3)
target_library(3)
link_library(3)
set_min_library(2)
write_app_var(2)
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assign_flip_chip_nets
Creates or reconnects nets between flip-chip drivers to bumps.
SYNTAX
status assign_flip_chip_nets
[-matching_type matching_type_list]
[-prefix prefix]
[-uniquify num_to_uniquify]
[-multiple_terminal_pins pin_name_or_collection]
[-terminal_layers layer_name_or_collection]
[-terminal_names terminal_name_list]
[-eco]
Data Types
matching_type_list
prefix
num_to_uniquify
pin_name_or_collection
layer_name_or_collection
terminal_name_list
list
string
integer
collection
collection
list
ARGUMENTS
-matching_type matching_type_list
Specifies a list of matching types for matching the flip-chip driver and bump pins. Only
driver and bump pins with identical personalities are matched. Each matching type is a
string name. By default, the tool processes all matching types.
-prefix prefix
Specifies a prefix string name. Use this option when a new net must be generated to
connect a flip-chip driver and a bump. The default prefix is "fcNet".
-uniquify num_to_uniquify
Specifies whether to and how to uniquify the driver nets inside a driver group. A driver
group contains multiple drivers with flip-chip ports that are connected to the same net.
The num_to_uniquify argument accepts integers from -n to 0 to n.
n means n-to-1 uniquify and to assign one bump for every n flip-chip driver ports.
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1 means one-to-one uniquify and to assign one bump for each flip-chip driver port. The
tool creates new nets by using the original net name followed by "_#". For example, VDD
net will be uniquely named to VDD, VDD_1, VDD_2, and so on.
0 means "do not uniquify" and to assign only one bump for the multiple flip-chip driver
ports. The original driver net is reused.
-n means 1-to-n connection and to assign n bumps for each flip-chip driver port.
The default behavior is one-to-one uniquify.
To form a 1-to-n connection, first specify the assign_flip_chip_nets -uniquify 1
command, followed by the assign_flip_chip_nets -uniquify -n command.
-multiple_terminal_pins pin_name_or_collection
Specifies the pins that have multiple terminals. The tool assigns one bump to each
terminal of the specified pins. Specify the pins either by using an object access
command, such as get_pins, or by specifying the pin name patterns in a Tcl list.
-terminal_layers layer_name_or_collection
Specifies the layers to use in the multiple terminal pin assignment. Only the terminals on
the given layers will be assigned a bump, the rest will not be assigned. This option is only
effective when used together with the -multiple_terminal_pins option. By default, all
terminals of the multiple terminal pins are assigned a bump. Specify the layer by using
either the get_layers command or by specifying the name of the layer.
-terminal_names terminal_name_list
Specifies specific terminals of flip-chip driver pins to be assigned. This option cannot be
used together with the -multiple_terminal_pins or -terminal_layers options. Each
terminal name must be specified by using the following syntax: "cell_instance_name/
pin_name:terminal_name". Pattern matching with wildcards is not supported. If you use
this option, each specified terminal is counted as an individual driver pin. The flip-chip
driver pins that do not occur in the list are assigned as usual.
-eco
Assigns flip-chip nets only for unconnected drivers or bumps or both, and keeps the
existing flip-chip connections.
DESCRIPTION
Based on the current placement results, you can use this command to locate the nearest
unassigned bumps, match them to flip-chip drivers using the shortest wire length method,
and automatically assign new logical nets or reconnect the nets between the flip-chip bumps
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and drivers. According to the -uniquify style you specify, the matching can be one-to-one or
n-to-one (n drivers to 1 bump) or one-to-n (1 driver to n bumps).
A flip-chip driver pin can have multiple terminals. If each of the terminals needs one bump to
be assigned, use the -multiple_terminal_pins option to specify the pin list. If only some of
the terminals on specific layers need to be assigned, use the -terminal_layers option to
specify which layers to use. If only some specific terminals need to be assigned, use the
-terminal_names option. By default, one bump will be assigned to each pin.
For bumps with an existing logical connection, the previous connection to the bump is
removed and a new bump is assigned. The newly matched bump is reconnected to the
matching flip-chip driver. The new bump net inherits the net name from the flip-chip driver
pad to which the bump is now connected. A new net is created only if the flip-chip driver pad
has no existing net connection.
The driver-to-bump matching is processed by matching types previously defined by the
set_flip_chip_type command. Only drivers and bumps with identical matching types are
matched. The tool does not process unspecified matching types if you use the
-matching_type option.
Prerequisites
Use the set_attribute command to specify a port of the flip-chip driver cell as the designated
flip-chip port. This identifies the port that is used to connect to a bump.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example performs driver-to-bump matching of the matching types red and
yellow.
prompt> assign_flip_chip_nets -matching_type {"red" "yellow"}
The following example performs 3-to-1 driver-to-bump matching
prompt> assign_flip_chip_nets -uniquify 3
Matching 8 POWER flip chip driver ports to 3 bumps using Munkres
algorithm...
Initializing Munkres Matrix...
Solving Munkres Matrix...
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
Storing the matching result...
Clearing up Munkres...
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Uniquified net vdd_1 being created from original net vdd
Uniquified net vdd_2 being created from original net vdd
Total 8 drivers-bumps match of all
prompt> report_flip_chip_driver_bump
BUMP_CELL NET DRIVER_CELL(S)
"BUMP1" "vdd_1" "VDDPST_1" "VDDPST_2" "VDDPST_3"
"BUMP2" "vdd_2" "VDDPST_4" "VDDPST_5" "VDDPST_6"
"BUMP3" "vdd"
"VDDPST_7" "VDDPST_8"
The following example performs multiple-terminal-aware assignment
prompt> assign_flip_chip_nets -matching_type "A" -multiple_terminal_pins
DI/*
Matching 4 A flip chip driver ports to 16 bumps using Munkres
algorithm...
Initializing Munkres Matrix...
Solving Munkres Matrix...
>>>>>>>>>>>>>>>>>>>>>>>>>
Storing the matching result...
Clearing up Munkres...
Reporting the multiple terminal pin matching property on bump cell
AREAPAD_S_120
[0]
pin name: DI/VSS_TEST
terminal name: VSS_TEST 3
Reporting the multiple terminal pin matching property on bump cell
AREAPAD_S_121
[0]
pin name: DI/VSS_TEST
terminal name: VSS_TEST 2
Reporting the multiple terminal pin matching property on bump cell
AREAPAD_S_63
[0]
pin name: DI/VSS_TEST
terminal name: VSS_TEST
Reporting the multiple terminal pin matching property on bump cell
AREAPAD_S_64
[0]
pin name: DI/VSS_TEST
terminal name: VSS_TEST 1
Total 4 drivers-bumps match of A
1
The following example performs multiple-terminal-aware assignment by specifying terminal
names
prompt> assign_flip_chip_nets -matching_type "A" -terminal_names \
{DI/VSS_TEST:VSS_TEST "DI/VSS_TEST:VSS_TEST 2"}
Matching 2 A flip chip driver ports to 16 bumps using Munkres
algorithm...
Solving Munkres Matrix...
>>>>>>>>>>>>>>>>>>>>>>>>>
Storing the matching result...
Clearing up Munkres...
Reporting the multiple terminal pin matching property on bump cell
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AREAPAD_S_121
[0]
pin name: DI/VSS_TEST
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terminal name: VSS_TEST 2
Reporting the multiple terminal pin matching property on bump cell
AREAPAD_S_64
[0]
pin name: DI/VSS_TEST
terminal name: VSS_TEST
Total 2 drivers-bumps match of A
SEE ALSO
set_matching_type(2)
merge_flip_chip_nets(2)
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associate_mv_cells
Associates the UPF strategies to the power management cells in the current design, and
reports the correlation between power management cells in the netlist and the UPF
strategies.
SYNTAX
status associate_mv_cells
[-level_shifters]
[-isolation_cells]
[-retention_registers]
[-power_switches]
[-verbose]
ARGUMENTS
-level_shifters
Reports the correlation and discrepancies between level-shifter cells and level-shifting
strategies.
-isolation_cells
Reports the correlation and discrepancies between isolation cells and isolation
strategies.
-retention_registers
Reports the correlation and discrepancies between retention cells and retention
strategies.
-power_switches
Reports the correlation and discrepancies between power switches and UPF
power-switch strategies.
-verbose
Reports the association information in the design in detail.
associate_mv_cells
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DESCRIPTION
The associate_mv_cells command analyzes the current design and associates existing
power-management cells according to the UPF strategies. It also checks and reports the
correlation between the power-management cells in the netlist and the corresponding UPF
strategies. The checking is based only on the UPF strategies. This command does not
check for electrical violations. The associate_mv_cells command does not support the
post-optimization flow in which optimization has been applied to the power-management
cells and their related connections.
If none of the power-management cell types are specified, this command reports all types of
the power-management cells in the design. If the -verbose option is specified, details of all
association information is reported.
EXAMPLES
The following example shows the report from the associate_mv_cells command when you
do not specify any argument. All types of power-management cells are reported.
prompt> associate_mv_cells \
------------------------------------------------------------------------------Retention Cells
------------------------------------------------------------------------------Information: Retention strategy retention_inst in power domain
InstDecode/PD
is associated with 1 retention cell(s). (UPF-511)
------------------------------------------------------------------------------Isolation Cells
------------------------------------------------------------------------------Information: Isolation strategy iso_stra_2 in power domain InstDecode/PD
is
associated with 1 isolation cell(s). (UPF-512)
------------------------------------------------------------------------------Power Switches
------------------------------------------------------------------------------Information: Power switch InstDecode/inst_sw is associated with 3 power
switch
instance(s). (UPF-513)
Information: Power switch Multiplier/mult_sw is associated with 2 power
switch
instance(s). (UPF-513)
------------------------------------------------------------------------------Level Shifters
-------------------------------------------------------------------------
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------1
SEE ALSO
check_mv_design(2)
report_isolation_cell(2)
report_level_shifter(2)
report_power_switch(2)
report_retention_cell(2)
associate_mv_cells
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associate_supply_set
Associates a supply set handle to another supply set handle or supply set reference.
SYNTAX
status associate_supply_set
supply_set_name
-handle supply_set_handle
Data Types
supply_set_name
supply_set_handle
string
string
ARGUMENTS
supply_set_name
Specifies the name of the supply set to which the supply set handle is associated. The
name can be the name of a supply set or a supply set handle.
This is a required argument.
-handle supply_set_handle
Specifies the supply set handle on which the action is performed.
This is a required argument.
DESCRIPTION
The associate_supply_set command associates the supply set handle specified with the
-handle option to the specified supply set. After the association, the tool treats
corresponding functions in each supply set to be virtually connected. So, the supply sets
inherit common switching behavior and must eventually be resolved to the same physical
supply net.
A supply set supports the following functions:
Power
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Ground
Multicorner-Multimode Support
This command has no dependency on scenario specific information.
EXAMPLES
The following example associates primary supply handle of domain PD1 to a supply set SS1
prompt> associate_supply_set SS1 \
-handle PD1.primary
1
SEE ALSO
create_power_domain(2)
create_supply_set(2)
associate_supply_set
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balance_inter_clock_delay
Performs interclock delay balancing.
SYNTAX
status balance_inter_clock_delay
[-clock_trees list_of_clocks]
[-max_target_delay float_value]
[-operating_condition min | max | min_max]
Data Types
list_of_clocks
float_value
list
float
ARGUMENTS
-clock_trees list_of_clocks
Performs interclock delay balance on the clocks specified in the list_of_clocks. When
this option is omitted and no balance group defined, the balancing is performed on all
clocks in the design. When this option is omitted and any balance group defined through
set_inter_clock_delay_options, the balancing is performed on clocks defined in balance
groups. When this option is specified and one or more balance groups defined through
set_inter_clock_delay_options, the balancing is performed on clocks specified in this
option.
-max_target_delay float_value
Specifies the maximum target delay using a positive float value. The tool balances all of
the clocks' longest paths up to the -max_target_delay value if no other higher priority
options are specified. -max_target_delay is not supported by MCMM ICDB engine.
-operating_condition min | max | min_max
Sets the operating condition to reflect the worst case (such as long delays, low voltage,
or high temperatures). This option can be combined with another operating condition. If
no operating condition option is specified (min, max or min_max) is set, the default is
-max.
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DESCRIPTION
The balance_inter_clock_delay command performs interclock delay balance by inserting
delay cells at the root of the clock to meet the clock insertion delay requirements. If timing
violations occur due to an unbalanced clock insertion delay in a different clock domain, set
a clock delay requirement with a small longest path delay value and run the
balance_inter_clock_delay command. This minimizes the differences between the longest
paths among the clocks.
Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios. All scenarios
enabled as clock tree synthesis scenarios are activated for clock tree synthesis and are
returned to their current state (active or inactive) after clock tree synthesis.
The clocks that need to be balanced need to be specified as scenario_name@clock_name
in -clock_trees option to correctly perform the balancing where,
scenario_name: Scenario with cts_mode set to true.
clock_name: Clock present in that scenario.
EXAMPLES
The following command performs interclock delay balancing using the maximum target
delay options:
prompt> balance_inter_clock_delay \
-max_target_delay 0.5
The following command performs interclock delay balancing for the CLK1 clock tree to 0.5ns
and the CLK2 clock tree to 0.8ns by using the set_inter_clock_delay_options command
and the balance_inter_clock_delay command:
prompt> set_inter_clock_delay_options \
-target_delay_clock CLK1 \
-target_delay_value 0.5
prompt> set_inter_clock_delay_options \
-target_delay_clock CLK2 \
-target_delay_value 0.8
prompt> balance_inter_clock_delay
The following command performs interclock delay balancing for the CLK1 clock tree, which
lags the CLK2 clock tree by 0.5ns, by using the set_inter_clock_delay_options command
and the balance_inter_clock_delay command:
balance_inter_clock_delay
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prompt> set_inter_clock_delay_options \
-delay_offset 0.5 \
-offset_to CLK1 -offset_from CLK2
prompt> balance_inter_clock_delay
The following command performs interclock delay balancing only on the CLK4 and CLK5
clocks under the worst and the best operating conditions, even though the design might
have additional clocks:
prompt> balance_inter_clock_delay \
-clock_trees [get_clocks {CLK4 CLK5}] \
-operating_condition min_max
The following command performs interclock delay balancing on the CLK6 and CLK7 clocks
for the scenario scene01
prompt> balance_inter_clock_delay \
-clock_trees [get_clocks {scene01@CLK6 scene01@CLK7}]
SEE ALSO
set_inter_clock_delay_options(2)
Chapter 1:
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break
Immediately exits a loop structure.
SYNTAX
int break
ARGUMENTS
None
DESCRIPTION
The break command immediately exits the innermost loop structure. Use the break
command to terminate a while loop, rather than waiting until the loop evaluates to zero.
The break command returns the integer 1, indicating successful operation. A syntax error is
reported if break is used outside a loop structure.
EXAMPLES
In the following example, a list of file names is scanned until the first file name that is a
directory is encountered. The break command is used to terminate the foreach loop when
the first directory name is encountered.
foreach f [which {VDD.ave GND.tech p4mvn2mb.idm}] {
echo -n "File $f is "
if { [file isdirectory $f] == 0 } {
echo "NOT a directory"
} else {
echo "a directory"
break
}
}
break
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SEE ALSO
continue(2)
while(2)
Chapter 1:
break
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calculate_caa_based_yield2db
Calculates critical-area-analysis-based yield and adds it to the .db library.
SYNTAX
status calculate_caa_based_yield2db
library_name_or_db_file_name
-particle_distr_func_file file_name]
[-data_kit_type tsmc | tsmc_encr]
[-layer_alias_dsd_format {x y z r t}]
[-output db_file_name]
ARGUMENTS
library_name_or_db_file_name
Specifies the input library using either the library name or the .db file name.
If you specify the library name, it must be a library that is already loaded in memory. To
see the libraries loaded in memory, use the get_libs command. If you specify that .db
file name, ensure that it is a valid file name.
This is a required argument.
-particle_distr_func_file file_name
Specifies the particle distribution function file.
You can define the shrinkage factor in this file for half-node support. The shrinkage
factor impacts the total critical area in the Poisson equation, and therefore impacts the
cell yield. If the shrinkage factor is not specified, the default is 1.
This is a required option.
-data_kit_type tsmc | tsmc_encr
Specifies the data kit type.
The valid values are tsmc and tsmc_encr (the default).
Use tsmc if the particle distribution function file from TSMC is in plain text format. Use
tsmc_encr if the particle distribution function file from TSMC is in encrypted format.
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-layer_alias_dsd_format {x y z r t}
Specifies the metal scheme that will be used for the tapeout. The order is {Mx My Mz Mt
Mr}. For example, {5 2 1 0 0} means that M2, M3, M4, M5, and M6 are Mx layers; M7
and M8 are My; and M9 is Mz.
Use this option when there are multiple routing layers defined in the library and the
critical area analysis tables.
For more details about the metal scheme, consult the TSMC manual.
-output db_file_name
Specifies the name of the generated .db file that contains the
critical-area-analysis-based yield data if the calculation finished successfully.
This option is not required when you specify a library name as the input library because
you can use the write_lib command to write out the critical-area-analysis yield .db file.
This option is required if you specify a .db file name as the input library.
DESCRIPTION
The calculate_caa_based_yield2db command calculates critical-area-analysis-based
yield using the critical area table defined in the input library, the particle distribution function,
the routing layer alias dsd format, and then adds the cell yield model to the library .db file.
This data can be used to improve yield in many stages of the design flow by various
methods, such as yield-based cell swapping and optimization.
The cell yield data is stored as a cell attribute in the format of a failure rate. You can
determine the relationship from the Poisson equation:
Cell_CA_Yield = exp (-Cell_FR);
If the library is generated from a .lib file, you can report the cell failure rate by using the
report_lib -yield command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example calculates CAA-based yield for the library read from test.lib and
writes out the yield.db file, which contains the yield data.
Chapter 1:
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prompt> read_lib test.lib
prompt> calculate_caa_based_yield2db test \
-particle_distr_func_file ddk_1.txt \
-data_kit_type tsmc caa_yield -layer_alias_dsd_format {1 2 1 2 1}
prompt> write_lib test -output yield.db
prompt> report_lib -yield test
SEE ALSO
report_critical_area(2)
calculate_caa_based_yield2db
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cd
Changes the current directory.
SYNTAX
status cd
[directory]
Data Types
directory
string
ARGUMENTS
directory
Specifies an existing directory name.
DESCRIPTION
The cd command changes the current directory to the specified directory. If you do not
specify directory, your login or home directory becomes the new current directory. By
default, the current directory is the directory where the shell is invoked.
A file specification of dot (.) is shorthand for the current directory. Dot is commonly included
in the search_path variable. Changing the current directory changes the interpretation of "."
in the search_path variable.
Note that the sh command cannot be used to change directories.
EXAMPLES
The following are examples of using the cd command:
prompt> cd /usr/designer
prompt> pwd
/usr/designer
prompt> cd joe
Chapter 1:
cd
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prompt> pwd
/usr/designer/joe
prompt> cd ../bob
prompt> pwd
/usr/designer/bob
prompt> cd ~
prompt> pwd
/usr/designer/joe
prompt> cd ~doug
prompt> pwd
/usr/designer/doug
prompt> cd
prompt> pwd
/usr/designer/joe
prompt> cd /usr/designer
prompt> ls
bob
designs
doug
joe
one.ddc
two.ddc
prompt> cd designs
prompt> ls
one.ddc
other.ddc
prompt> set_app_var search_path ". ~"
prompt> read_ddc {one.ddc two.ddc}
Loading ddc file '/usr/designer/designs/one.ddc'
Loading ddc file '/usr/designer/joe/two.ddc'
prompt> cd /tmp
prompt> read_ddc one.ddc
Loading ddc file '/usr/designer/joe/one.ddc'
SEE ALSO
ls(2)
pwd(2)
cd
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change_connection
Disconnects the nets on the specified pins and connects these pins to the desired network
that is determined by the specified net.
SYNTAX
status change_connection
[-net netName]
pin_list
Data Types
pin_list
collection of pins
ARGUMENTS
-net netName
Specifies the net to be connected. If this option is not specified, the specified pins will be
disconnected.
pin_list
Specifies a list of pins to be connected by the desired network that is defined by the
specified net. The net segment of the network must exist in the same hierarchical level
of each target pin.
DESCRIPTION
This command first disconnects the target pins and then connects these pins to the desired
network. A network is the set of nets connected across hierarchy. The specified input net is
on the segment of the network.
EXAMPLES
The following example uses the change_connection command to connect net new_net to
pin U1/SE, net A/new_net to pin A/U2/SE and net A/B/new_net to pin A/B/U3/SE. The nets
Chapter 1:
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U1/new_net, A/new_net and A/B/net_net share the same network through the hierarchical
port.
prompt> change_connection -net new_net {U1/SE A/U2/SE A/B/U3/SE}
The following example uses the change_connection command to disconnect net old_net
from pin U1/SE, net A/old_net from pin A/U2/SE and net A/B/old_net from pin A/B/U3/SE.
The command then connects net new_net to pin U1/SE, net A/new_net to pin A/U2/SE and
net A/B/new_net to pin A/B/U3/SE.
prompt> change_connection -net new_net {U1/SE A/U2/SE A/B/U3/SE}
SEE ALSO
all_connected(2)
connect_net(2)
disconnect_net(2)
change_connection
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change_fp_soft_macro_to_black_box
Converts the specified soft macros to black boxes.
SYNTAX
status change_fp_soft_macro_to_black_box
black_boxes
ARGUMENTS
black_boxes
Specifies the soft macros to convert.
DESCRIPTION
Converts the specified soft macros to black boxes (the original soft macro is removed and
replaced with an empty one).
All instantiated subdesigns and leaf cells in the specified soft macro are removed from the
logical (hierarchy preservation) information in the database.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example converts the soft macro alu1 to a black box.
prompt> change_fp_soft_macro_to_black_box [get_cell alu1]
SEE ALSO
estimate_fp_black_boxes(2)
get_cells(2)
Chapter 1:
change_fp_soft_macro_to_black_box
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change_link
Changes the design to which a cell is linked.
SYNTAX
status change_link
object_list
design_name
[-view view_name]
[-freeze_silicon]
Data Types
object_list
design_name
view_name
list
string
string
ARGUMENTS
object_list
Specifies the cells or references in the current design for which to change the link.
design_name
Specifies the name of the design to which to link the cells or references in the object list.
-view view_name
Specifies the Milkyway view of the reference design to which to link the cells or
references in the object list.
-freeze_silicon
Used for the ECO freeze silicon flow.
After you run this command, the cell instances are in the transitional state. You must run
the place_freeze_silicon or map_freeze_silicon command to swap the cell instances
with the available spare cells of the specified reference library cell.
change_link
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DESCRIPTION
The change_link command specifies a design for which to change the link for a cell or
reference.
If you specify a cell in the object list, the command changes it to one occurrence of the
specified design. If you specify a reference in the object list, the command changes all cells
of the specified reference type to occurances of the design.
You can change the cell or reference link only to a compatible design. For example, the
design must have the same number of ports with the same name and direction as the cell or
reference.
You can also use this command to change the reference of a physical-only cell to another
physical-only library cell.
Physical-only cells and standard cells are not compatible, so you can only change a
physical-only cell's reference to another physical-only library cell. Similarly, references of
standard cells can only be changed to logical library cells.
The -view option allows the reference to be changed to a Milkyway view other than the
FRAM view. Be careful when using this option, as the tool performs only minimal checking
when it is used. This option also triggers a complete link of the design, even if it is already
linked.
Although the design_name argument accepts names in the format library/library_cell, it
does not imply that the actual library cell used for the new cell will be from the specified
library. The actual library cell used is determined by the current link library settings.
After running the change_link command, link the design with the link -force command.
EXAMPLES
The following example shows an improper use of the change_link command. The specified
cell does not have the same number of ports as the design to which it is being linked.
prompt> change_link U3 HALF_ADDER
Error: Number of pins on cell 'U3' don't equal design 'HALF_ADDER'
The following example shows the use of change_link to change the reference of the U1 cell
from INVX3 to BUFX3:
prompt> get_attribute [get_cells U1] ref_name
INVX3
1
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prompt> change_link [get_cells U1] BUFX3
1
prompt> get_attribute [get_cells U1] ref_name
BUFX3
1
SEE ALSO
current_design(2)
link(2)
map_freeze_silicon(2)
place_freeze_silicon(2)
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change_macro_view
Changes the view of the macro that is used.
SYNTAX
status change_macro_view
-reference cell_reference_name
-view view_name
[-quiet]
Data Types
cell_reference_name
view_name
string
string
ARGUMENTS
-reference cell_reference_name
Specifies the cell reference name for which to change the reference view.
All instances of the cell reference will use the view specified by the -view option with the
view_name value.
-view view_name
Specifies the view name to be used.
Valid values for view_name are FRAM and CEL.
-quiet
Suppresses the messages.
DESCRIPTION
The change_macro_view command changes the macro's view. All instances of the cell
reference are affected by this command.
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example replaces the existing CEL view with the FRAM view for the mem_ctrl
macro:
prompt> change_macro_view -reference mem_ctrl -view FRAM
The following example specifies that the CEL view is to be used for the mem256x16
reference cell:
prompt> change_macro_view -reference mem256x16 -view CEL
SEE ALSO
create_macro_fram(2)
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change_names
Changes the names of ports, cells, and nets in a design.
SYNTAX
status change_names
[-rules name_rules]
[-hierarchy]
[-verbose]
[-names_file names_file]
[-log_changes log_file]
[-restore]
[-dont_touch object_list]
[-instance instance]
[-new_name new_name]
[-skip_inactive_constraints]
Data Types
name_rules
names_file
log_file
object_list
instance
new_name
string
string
string
list
string or instance object
string
ARGUMENTS
-rules name_rules
Specifies a name rule set that details the rules to which the object names must conform.
The name_rules file is defined by using the define_name_rules command.
By default, this value is the name_rules file specified by the default_name_rules
variable.
The tool ignores the -rules option if you specify the -names_file option.
-hierarchy
Modifies all names in the design hierarchy.
By default, the tool changes only objects in the current design.
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-verbose
Reports every name change.
By default, the tool provides only a summary of the number of name changes in the
design.
-names_file names_file
Specifies a file of manual name changes. These name changes are not subject to any
name rules, but an error is reported if any name changes are not unique.
By default, the command automatically makes name changes based on the naming
rules.
If you specify this option, the tool ignores the -rules option.
-log_changes log_file
Specifies the log file in which to record all name changes.
If you run multiple change_names commands, the log_file must be empty before
running the first change_names command.
-restore
Reverses the changes recorded in the names_file during the current session and
restores the contents of the file to the state it was in when opened.
-dont_touch object_list
Specifies the designs on which the change_names command is not to be applied. You
can specify any design under the hierarchy of the current design in the object list to
ensure that the change_names command does not apply any changes to them. The dot
(.) character represents the current design.
By default, there are no designs in the list.
-instance instance
Specifies the instance on which to apply the change_names command.
This option must be used with the -new_name option to specify a new instance name.
This option is mutually exclusive with all other options except -new_name and
-verbose.
-new_name new_name
Specifies the new instance name when the -instance option is used. The new name
must consist of only alphanumeric characters and the underscore (_) and must start with
an alphabetical character. The new name cannot be a reserved word used by Verilog,
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SystemVerilog, or VHDL. The new name must not conflict with an existing instance, port,
and net name within the same design. The leading backslash will be removed from the
new name.
-skip_inactive_constraints
When you specify this option, the inactive constraints (that are part of the non-current
design or part of inactive scenarios) are not preserved when you use the -instance
option with change_names. This option has no impact when you do not specify the
-instance option.
DESCRIPTION
The change_names command changes the names of ports, cells (including physical-only
cells), and nets in a design to conform to specified name rules.
This command cannot be used to change the name of library cells or bus ports.
To change the name of bus ports, you must first use the undefine_bus command to remove
the bus property from the port.
If an object name does not conform to the specified rules, the tool changes the name and
ensures that the new name is unique within the design.
By default, the tool changes the names of bus members to force them to use the same base
name as their owning bus. If you do not want the names of bus members, set the
change_names_dont_change_bus_members variable to true before running the
change_names command.
To show the effects of running this command without actually making the changes, use the
report_names command.
There are two primary reasons for using the change_names command:
•
It enables you to modify design object names in the tool so that the names match those
that are ultimately created for a saved design. The names the tool displays in reports and
in other information match those used in your target system.
•
It enables you to define naming rules specific to your target system. For example, you
might be using VHDL as a design transfer mechanism, but the naming rules of your
system might be more restrictive than those supported by the true VHDL format.
To obtain a list of available name rules, use the report_name_rules command. For
information about naming rules that can be affected during the execution of the
change_names file, see the define_name_rules man page.
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When you run the change_names command with no options, it operates on the ports, cells,
and nets in the current design. When you specify the -hierarchy option, changes are
expanded to include all design objects within the current design hierarchy.
For runtime reasons, it's best to use the -instance option only when you have a small list of
instances to be renamed. If you have a big list of instances to be renamed, you must use the
-rule option with change_names or use the -skip_inactive_constraints option and apply
the constraints after running change_names -instance.
Names File Format
To specify a name change, you must specify the following four fields:
design_name
object_type
object_name
new_name
The design_name field is a design currently read into the tool. The object_type field is port,
cell, or net. The object_name field is the name of an object within the specified design. The
new_name field is the name that replaces the existing name.
If the file contains a report bar formed by a dashed line (--------), the tool ignores all
information above the report bar. The tool parses all lines after the report bar (or all lines, if
the file does not contain a report bar).
By default, the tool parses each line into four fields, which are separated by whitespace
characters, such as blanks, tabs, or new lines.
This format matches the format of the report_names command output, which allows you to
redirect the output of the report_names command to a file, edit it, and then use it as input
to the change_names command.
The tool also supports the use of a semicolon (;) as a delimiter to separate the name change
specifications in the file. If you use a delimiter, you must add the following line above the
report bar formed by the dashed line (--------):
use delimiter:true
The following example shows a names file without a delimiter:
****************************************
Report : names
-rules MY_RULES
Design : TOP
Version: v3.0
Date
: Tue Aug 13 14:24:23 2007
****************************************
Design
Type
Object
New Name
-------------------------------------------------------------
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TOP
cell
net
TOP
net
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U$1
U_1
NET_NAME_IS_WAY_TOO_LONG
NET_NAME_IS_WAY_TOO
12345
N12345
The following example shows a names file with a delimiter:
use delimiter:true
Design
Type
Object
New Name
------------------------------------------------------------TOP
cell
U$1
U_1 ;
TOP
net
NET_NAME_IS_WAY_TOO_LONG
NET_NAME_IS_WAY_TOO ;
TOP
net
12345
N12345 ;
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows how to change the names in the current design to conform to
the rules defined by the default_name_rules variable:
prompt> list default_name_rules
default_name_rules = "EXAMPLE"
prompt> change_names
Information: Using name rules 'EXAMPLE'.
Information: 4 names changed in design 'TOP'.
The following example shows how to use the -verbose option to show each name changed
by the change_names command.
prompt> change_names -verbose
Information: Using name rules 'EXAMPLE'.
Design
Type
Object
New Name
------------------------------------------------------------TOP
port
A1
a_
TOP
port
A2
a_a
TOP
port
A3
a_b
TOP
port
A4
a_c
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The following example shows how to use the -hierarchy option to change names
throughout the design hierarchy. Typically, you want to change the names of all designs in
the hierarchy to conform to your name rules.
prompt> change_names -hierarchy
Information: Using name rules 'EXAMPLE'.
Information: 12 names changed in design 'HALF_ADDER'.
Information: 35 names changed in design 'SUBTRACTOR'.
Information: No names changed in design 'TOP'.
The following example shows how to use the define_name_rules command to create a set
of simple name rules. In this example, the name rules require that all names use uppercase
characters or numerals.
prompt> define_name_rules CAPS_ONLY -allow "A-Z 0-9"
prompt> change_names -rules CAPS_ONLY -verbose
Information: Using name rules 'CAPS_ONLY'.
Design
Type
Object
New Name
------------------------------------------------------------MY_BUFFER
port
a1
A1
MY_BUFFER
port
a2
A2
MY_BUFFER
port
b1
B1
MY_BUFFER
port
b2
B2
MY_BUFFER
cell
u1
U1
MY_BUFFER
cell
u2
U2
The following example shows how to make manual name changes to design objects by
using the report_names and change_names commands. First, redirect a report of all the
original design objects to a file and edit the file to make manual changes. Use the edited
names file to direct the name changes made by the change_names command. In this case,
the tool ignores the name rules and makes only the specified changes.
prompt> report_names -original > TOP.names
/* Edit the TOP.names names file */
prompt> change_names -names_file TOP.names
Information: 15 names changed using names file 'TOP.names'
The following example shows how to use the -instance option to change one instance
name:
prompt> change_names -instance a1 -new_name a2
The following example shows how to rename a bus port by first removing the bus property
and then using the change_names command to change the name.
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prompt> undefine_bus -type port -name my_bus
prompt> change_names -names_file name.change -verbose
SEE ALSO
define_name_rules(2)
report_name_rules(2)
report_names(2)
default_name_rules(3)
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change_selection
Changes the selection in the GUI, taking a collection of objects and changing the selection
according to the type of change specified.
SYNTAX
status change_selection
[-name slct_bus]
[-replace]
[-add]
[-remove]
[-toggle]
[-type object_type]
[-clock_trees clock_tree_list]
collection
Data Types
slct_bus
object_type
clock_tree_list
collection
string
list
list
list
ARGUMENTS
-name slct_bus
Specifies to change the selection bus by using the value of slct_bus. By default, the
command changes the selection bus by using the name global.
-replace
Replaces the current selection with the objects in the collection. This is the default
behavior when no options are specified.
-add
Adds the objects in the collection to the current selection. By default, this option is off.
-remove
Removes the objects that are specified in the collection from the current selection. By
default, this option is off.
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-toggle
Adds each item that is specified in the collection to the selection bus if it is not currently
contained in the selection bus. If it is currently contained in the selection bus, it is
removed. By default, this option is off.
-type object_type
Specifies the type to change. Only those items from the collection that are of the type
specified by object_type are used to change the selection. The valid values are design,
port, net, cell, pin, and path (timing path). By default, the command uses the entire
collection.
-clock_trees clock_tree_list
Specifies a list of clock trees for changing the selection. By default, this option is off.
collection
Specifies the collection of objects to use to change the selection. The type of change
that is applied to the current selection with the collection is specified by the options listed
above. By default, this option is off.
DESCRIPTION
The change_selection command changes the selection in the GUI. When selections are
changed, the GUI updates all relevant windows to reflect it.
A collection of objects and the type of change are given as input to the command. The
collection of objects might be returned as the result of another command, such as the
get_designs command. If the collection is empty and you use the -replace option (or let the
command default by specifying no option), the current selection is cleared.
If you use the -type option, only the type of objects specified are used to change the current
selection. For example, if you use -type design, the command uses only the design objects
in the collection to change the current selection. If you do not use the -type option, all
objects in the collection are used to change the current selection. For example, if you use
the -add option without using the -type option, all objects, regardless of their type, are
added to the current selection.
For information about collections, see the collections man page.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example replaces the current selection with the collection of design objects,
regardless of type:
prompt> change_selection [get_designs]
The following example adds a cell named U5 to the selection made in the example above:
prompt> change_selection -add [get_cells U5]
The following example removes all pin objects from the current selection:
prompt> change_selection -remove -type pin [get_selection]
The following example clears the selection:
prompt> change_selection ""
The following example creates a new selection bus and adds a net named n1 to the
selection:
prompt> set slct [create_selection_bus]
prompt> change_selection
-name $slct [get_nets 1]
SEE ALSO
collections(2)
filter_collection(2)
get_selection(2)
query_objects(2)
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change_via_master
Changes the via master of via objects in a collection.
SYNTAX
collection change_via_master
via_objects
-via_master via_master_name
Data Types
via_objects
via_master_name
collection
string
ARGUMENTS
via_objects
Specifies the via objects in the design to be assigned a new via master. This is a
required argument.
-via_master via_master_name
Specifies the name of the via master for the specified via objects. This is a required
option.
DESCRIPTION
This command changes the via master for one or more specified via objects in the design to
a new via master and returns a collection of the specified vias, including both the vias whose
master has changed and those that are unchanged.
If the via_objects argument is a collection variable and the tool issues an MWUI-1018
message during the change, the original via collection is invalidated. You must use the
returned via collection instead of the original via collection if any further processing is
needed on the vias.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example changes the via master according to the specified collection of
objects and via master name.
prompt> change_via_master [get_vias VIA#512*] \
-via_master [get_via_masters VIA12B]
Information: Changed the via master from VIA12A to VIA12B
for via VIA#5121. (MWUI-1017)
Information: Changed the via master from VIA12C to VIA12B
for via VIA#5122. (MWUI-1017)
{VIA#5121 VIA#5122}
In following example, the tool issues MWUI-1018 warning messages during the change,
which indicates that the object ID of vias has changed and therefore the via_col_1 input
collection is invalid. The via_col_2 collection must be used instead of the via_col_1
collection in the foreach_in_collection command.
prompt> set via_col_1 [get_vias {VIA#235012 VIA#235013 VIA#235014}]
prompt> set via_col_2 [change_via_master -via_master VIA1 $via_col_1]
Warning: Change the object ID of the via from 235012 to 173568.
(MWUI-1018)
Information: Changed the via master from via1 to VIA1 for via
VIA#173568. (MWUI-1017)
Warning: Changed the object ID of the via from 235013 to 173568.
(MWUI-1018)
Information: Changed the via master from via1 to VIA1 for via
VIA#173569. (MWUI-1017)
Warning: Changed the object ID of the via from 235014 to 173568.
(MWUI-1018)
Information: Changed the via master from via1 to VIA1 for via
VIA#173570. (MWUI-1017)
{VIA#173568 VIA#173569 VIA#173570}
prompt> foreach_in_collection via $via_col_2 \
{puts "Via master for [get_attribute $via] is [get_attribute $via
via_master]"}
Via master for VIA#173568 is VIA1
Via master for VIA#173569 is VIA1
Via master for VIA#173570 is VIA1
The following example causes an MWUI-1019 error, which indicates that the via master
cannot be changed.
prompt> change_via_master [get_vias VIA_ARRAY#5377] -via_master VIA15A
Error: Cannot change via master to VIA15A for via VIA_ARRAY#5377.
(MWUI-1019)
{VIA_ARRAY#5377}
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SEE ALSO
get_vias(2)
create_via_master(2)
get_via_masters(2)
create_via(2)
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change_working_design
Changes the working design in a cell hierarchy by moving down or up a hierarchy of soft
macro cells.
SYNTAX
status change_working_design
-push cell [-readonly] | -pop [-discard]
Data Types
cell
collection of one cell
ARGUMENTS
-push cell
Specifies a soft macro cell in the current design. You can specify the cell by name or as
a collection containing one cell object. The command makes the specified cell the
current working design and displays the design in the context of the higher-level design.
The cell name is pushed onto a stack.
-readonly
Opens the lower-level design in read-only mode. This option works only with the -push
option.
-pop
Reverses the effects of the most recent usage of the change_working_design -push
command. It pops the most recent cell pushed onto the stack and restores the previous
higher-level cell as the current working design.
You must use either the -push or -pop option in the command.
-discard
Discards the recent modifications on the current working design when popping the
design off of the stack. This option works only with the -pop option.
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DESCRIPTION
This command changes the working design in a cell hierarchy by moving down or up a
hierarchy of soft macro cells. Use the -push option to move down the hierarchy or the -pop
option to move up the hierarchy. When you move down the hierarchy, the GUI displays the
new lower-level working design in the context of the higher-level design.
This command is similar to opening the child design with the open_mw_cel command.
However, the GUI shows the lower-level soft macro in the context of the parent design, with
the surrounding uneditable higher-level layout information dimmed.
The change_working_design command works only in a design organized as a hierarchy
of soft macros. You can "push" the view down to a soft macro implemented as a CEL view,
but not down to a logical hierarchical block that has been implemented as "flat" along with
other lower-level blocks.
When you use the change_working_design command, the tool maintains a stack of
working designs. The -push option saves the current working design on the stack before it
changes the working design to the specified cell, whereas the -pop option restores the most
recent working design stored on the stack and removes it from the stack.
You can use the get_working_design_stack command to check the stack and the
change_working_design_stack command to switch between different stacks.
The current_mw_cel command also changes the working design, but it ignores and clears
out the stack. For more information, see the current_mw_cel man page.
When pushing into a child design, this command implicitly opens the child Milkyway design
if it is not already open. For a reference to a CEL view, you can use the -readonly option to
open the cell in read-only mode if the tool would otherwise allow read-write access. If the
child design is already open, its current read/write accessibility is not affected.
After you finish editing the child Milkyway design, you can run the change_working_design
-pop command to pop the child Milkyway design from the stack and return to its parent
Milkyway design. The changes to the child design are automatically reflected in its ancestor
designs. If you do not want to save the changes to the child design, you can use the
-discard option with the -pop option.
To save all changes to the top-level Milkyway design and its child Milkyway designs, you
must use the save_mw_cel -hierarchy command. To close all Milkyway designs in the
stack, use the close_mw_cel -hierarchy command.
EXAMPLES
The following example sets the current working design to a child Milkyway design,
BLENDER_2, which is instantiated by the I_ORCA_TOP/I_BLENDER_4 soft macro cell.
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After performing some operations, the example pops the child Milkyway design from the
stack and returns to the parent Milkyway design, ORCA.
prompt> change_working_design -push I_ORCA_TOP/I_BLENDER_4
1
prompt> current_mw_cel
{BLENDER_2}
(some operations performed ...)
prompt> change_working_design -pop
1
prompt> current_mw_cel
{ORCA}
SEE ALSO
change_working_design_stack(2)
close_mw_cel(2)
current_mw_cel(2)
get_working_design_stack(2)
open_mw_cel(2)
save_mw_cel(2)
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change_working_design_stack
Changes the current working design stack.
SYNTAX
collection change_working_design_stack
design
Data Types
design
collection
ARGUMENTS
design
Specifies the Milkyway design whose stack is set as the current design stack. You can
specify the design by name, name pattern, or a collection. If you specify a collection, the
collection must contain only one design.
This is a required argument.
DESCRIPTION
This command changes the current working design stack by specifying a top-level Milkyway
design. The command returns a collection that contains the current working design stack.
The current working design is changed to the top of target stack, which is the latest design
pushed onto that stack. If the stack contains more than one design, the current working
design is not the top-level design.
See the current_mw_cel man page for information about how to switch to the target
top-level design and clear the stack.
EXAMPLES
The following example shows that the change_working_design_stack command changes
the working design stack without clearing it.
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prompt> current_mw_cel
{TOP}
prompt> change_working_design_stack ORCA
{ORCA BLENDER_2}
prompt> current_mw_cel
{BLENDER_2}
SEE ALSO
change_working_design(2)
get_working_design_stack(2)
current_mw_cel(2)
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characterize
Captures information about the environment of specific cell instances and assigns the
information as attributes on the design to which the cells are linked.
SYNTAX
status characterize
cell_list
[-no_timing]
[-constraints]
[-connections]
[-power]
[-verbose]
Data Types
cell_list
list
ARGUMENTS
cell_list
Specifies the cells in the current design whose designs are to be characterized.
-no_timing
Indicates not to characterize the timing characteristics of the design. Attributes
representing the timing environment or requirements are not placed on the subdesigns.
-constraints
Places area, power, connection class, and design rule constraint information on the
subdesigns.
-connections
Characterizes the connection attributes of the design.
-power
Uses the switching activity information of the specified cells to annotate the
corresponding subdesigns.
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-verbose
Echoes the equivalent commands that are applied to the subdesign being characterized.
DESCRIPTION
The characterize command places on a design the information and attributes that
characterize its environment in the context of a specified instantiation in another design.
The primary purpose of the characterize command is to capture the timing environment of
the subdesign. This occurs if the characterize command is run without the -no_timing
option.
The command derives and asserts the following on the design to which the instance is
linked:
•
Unless the -no_timing option is used, the characterize command places on the
subdesigns any timing characteristics previously set by the following commands:
create_clock
group_path
read_sdf
read_clusters
set_annotated_check
set_annotated_delay
set_auto_ideal_net
set_disable_timing
set_drive
set_driving_cell
set_false_path
set_ideal_latency
set_ideal_net
set_ideal_transition
set_input_delay
set_load
set_max_delay
set_min_delay
set_multicycle_path
set_operating_conditions
set_output_delay
set_resistance
set_timing_ranges
set_wire_load_model
set_wire_load_mode
set_wire_load_selection_group
set_wire_load_min_block_size
•
If the -constraint option is used, the characterize command places on the subdesigns
any area, power, connection class, and design rule constraints previously set by the
following commands:
characterize
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set_cell_degradation
set_connection_class
set_dont_touch_network
set_fanout_load
set_fix_multiple_port_nets
set_ideal_network
set_ideal_net
set_max_area
set_max_capacitance
set_max_fanout
set_max_power
set_max_transition
set_min_capacitance
set_min_porosity
•
If the -connections option is used, the characterize command places on the
subdesigns any connection attributes previously set by the following commands:
set_equal
set_logic_one
set_logic_zero
set_logic_dc
set_opposite
set_unconnected
•
Note that connection class information is applied only if the -constraint option is used.
•
If the -power option is used, the characterize command places on the subdesigns any
switching activity information, toggle rates, and static probability previously set,
calculated, or saved by the following commands:
report_power
set_switching_activity
•
In most cases, characterizing a design removes the effects of any previous
characterization and replaces all relevant information. However, in the case of
back-annotation (the set_load, set_resistance, read_sdf, set_annotated_delay, an
set_annotated_check commands), the annotations are moved during the characterize
step, and cannot overwrite existing annotations made on the subdesign. In this case,
annotations must be explicitly removed from the subdesign by using the reset_design
command before running the characterize command the next time.
Multicorner-Multimode Support
This command uses information from the current scenario only.
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EXAMPLES
The following example characterizes the top-level design.
prompt> characterize TOP
SEE ALSO
create_clock(2)
current_design(2)
group_path(2)
link(2)
read_sdf(2)
remove_annotated_check(2)
remove_annotated_delay(2)
reset_design(2)
set_annotated_check(2)
set_annotated_delay(2)
set_cell_degradation(2)
set_connection_class(2)
set_disable_timing(2)
set_dont_touch(2)
set_dont_touch_network(2)
set_drive(2)
set_driving_cell(2)
set_equal(2)
set_false_path(2)
set_fanout_load(2)
set_fix_multiple_port_nets(2)
set_ideal_latency(2)
set_ideal_net(2)
set_ideal_network(2)
set_ideal_transition(2)
set_input_delay(2)
set_load(2)
set_logic_one(2)
set_logic_zero(2)
set_logic_dc(2)
set_min_capacitance(2)
set_max_area(2)
set_max_capacitance(2)
set_max_delay(2)
set_max_fanout(2)
set_max_transition(2)
set_min_delay(2)
set_multicycle_path(2)
set_operating_conditions(2)
set_opposite(2)
set_output_delay(2)
set_resistance(2)
set_target_library_subset(2)
set_timing_ranges(2)
characterize
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set_unconnected(2)
uniquify(2)
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check_block_abstraction
Checks the readiness of a block abstraction for usage in a top-level design at various stages
of the flow.
SYNTAX
status check_block_abstraction
[-stage stage_value]
Data Types
stage_value
string
ARGUMENTS
-stage stage_value
Specifies the stage for which the readiness of the blocks is checked. The checks
performed by thecheck_block_abstraction command depend on the specified stage.
Ensure that the block contents are relevant to the specified stage.
You can specify one of the following values:
•
pre_place_opt
Use this stage when the top-level design is ready for placement.
•
pre_clock_opt
Use this stage when the top-level design is ready for clock tree synthesis.
•
pre_route_opt
Use this stage when the top-level design is ready for routing.
If this option is not specified, the command runs some general checks.
DESCRIPTION
The check_block_abstraction command checks if the blocks linked to the top-level design
are ready for various stages of the top-level flow such as placement, clock tree synthesis,
and routing. If you do not specify a stage, the following general checks are performed:
check_block_abstraction
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•
Block leaf-cell location check
•
Multicorner-multimode checks
•
CEL and FRAM view consistency check
•
PG boundary pin consistency check
•
dont_touch attribute check
Version L-2016.03
The pre_place_opt checks include the general checks and a block location check.
The pre_clock_opt checks include the general checks, the pre_place_opt checks, and a
clock tree synthesis check.
The pre_route_opt checks include the general checks, the pre_place_opt checks, the
pre_clock_opt checks, a parasitic data check, and a signal integrity aggressor data check.
If any error messages are reported by this command, you should resolve them before
proceeding further. If any warning messages are reported by this command, you should
review them before proceeding further.
Multicorner-Multimode Support
This command uses information from active scenarios only.
EXAMPLES
The following example checks the blocks in the current design in the pre_route_opt stage.
prompt> check_block_abstraction -stage pre_route_opt
Warning: Master cell of macro blk is not blk.FRAM. (TL-35)
Error: Net 'blk/net1' is not clock tree synthesized. (TL-125)
Error: Block 'blk' does not have required (SI aggressor info) file.
(TL-32)
0
SEE ALSO
create_block_abstraction(2)
set_top_implementation_options(2)
report_block_abstraction(2)
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check_physical_design(2)
check_block_abstraction
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check_clock_tree
Checks the clock trees of the current design for common problems that can adversely
impact clock tree synthesis.
SYNTAX
status check_clock_tree
[-clocks clock_list]
[-solution_template file_name
[-solution_for option_list]]
Data Types
clock_list
file_name
option_list
list
string
list
ARGUMENTS
-clocks clock_list
Checks only those clock trees that appear in the clock_list. By default, the command
checks all clocks in the design.
-solution_template file_name
Writes out a file containing commands that resolve clock tree issues identified by the
command. You can source the file to resolve the warnings. The file is saved in the
current working directory.
Some violations might contain multiple solutions. For these cases, the solution file
contains more than one solution for a given violation. The default solution is the
suggested solution. Alternative solutions have a comment character (#) before each
command line. Before sourcing the file, you must remove the comment to enable that
solution.
-solution_for option_list
Limits the solution template output file to only the specified violation types. You can also
select the default solution or alternate solution in the option list. You must also specify
the -solution_template option when you specify -solution_for.
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For example, the command creates two solutions for a CTS-823 warning: create a
generated clock (default solution), or set an exclude pin. If you specify
check_clock_tree -solution_template -solution_for {cts-823-1}, the command writes
out the default solution to resolve the warning. If you specify check_clock_tree
-solution_template -solution_for {cts-823-2} the command writes out the alternate
solution.
You can also specify multiple violation types in the option list. For example, specify the
following command to write out a solution file for the specified violations.
check_clock_tree -solution_template solution.tcl
-solution_for {cts-823-1 cts-861-1 cts-835-2}
By default, the solution file contains all violation types.
DESCRIPTION
Use the check_clock_tree command before clock tree synthesis to check for common
problems that might impact clock tree synthesis. The command performs the following
checks:
*: The command writes a solution to the solution template file
CTS-821
A master clock does not propagate to a generated
clock
CTS-822
Improperly specified master clock
CTS-823*
A master clock terminates at a multiclock pin
CTS-831
A clock has no synchronous pins
CTS-832
A clock loops to itself
CTS-834*
Multiple clocks per register
CTS-835*
Exceptions defined on output pins
CTS-837*
Dont_touch nets/cells not defined by
set_clock_tree_exceptions
CTS-838
Clock nets are routed prior to clock tree
synthesis
CTS-841*
Ignored exceptions
CTS-850*
No buffer available for clock tree synthesis
CTS-851
Multiple arc between input and out pins
CTS-852
Case analysis set on a pin
CTS-853
Disable timing set at a pin
CTS-855
No reference can be used
CTS-858*
Clock tree exception defined on a clock source
CTS-859*
max_fanout is smaller than its default value
CTS-860*
NonMCMM conflicting balancing requirement check
CTS-861*
MCMM master clock terminates at a multi_clock pin
CTS-862*
MCMM conflicting balancing requirement check
CTS-866*
Different offset values defined for ICDB
CTS-867*
Different target_delay value set for ICDB
CTS-868*
Conflicting requirement set for clocks for ICDB
CTS-869*
Cyclic offset values specified for ICDB
CTS-871*
Phase delay skew of etm/ilm entrance pin larger
than threshold
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CTS-875*
CTS-876
data pin
CTS-877
CTS-878
issue
CTS-982
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Possible cap/fanout violation on dont_touch net
Generated clock defined in the output cone of a
Cell has output_output arcs
A possible balance conflict at pin due to unknown
A clock root is in fanin cone of another root
Some checks are specific to overlapping clock domains; these require that you set the
timing_enable_multiple_clocks_per_reg shell variable to true to enable the timing engine
to propagate multiple clocks per register. If the variable is set to false, the command
performs an extra check to detect and warn about overlapping clocks (CTS-834).
When check_clock_tree encounters a problem, the command prints a warning or
informational message. The message might by followed by additional information to aid
debugging and repair. There is a man page available for each message type; the page
explains the problem in detail and what you can do to solve it.
Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios. All scenarios
enabled as clock tree synthesis scenarios are activated for clock tree checking and are
returned to their current state (active or inactive) after checking.
The check_clock_tree command performs the following checks for all clock tree synthesis
scenarios:
Per-clock exception conflicts for each scenario:
CTS-860 Conflicting exceptions for different clocks on same pin
The conflicts covered are :
Stop(sink)
Float value (vice versa)
Float value
Different float value (vice versa)
Stop(sink)
nonstop (vice versa)
Float value
nonstop (vice versa)
Cross-scenario checks :
CTS-861 Missing gen clock definitions across scenarios
CTS-862 Conflicting float/stop nonstop exception across scenarios
Interclock delay balancing settings:
CTS-866 Conflicting offset values for same root across scenarios
CTS-867 Different target_delay setting for same root across
scenarios
CTS-868 Roots in balance group in one scenario have offset
values in another scenario
CTS-869 Cyclic offset setting checking across scenarios
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EXAMPLES
In the following example, the check_clock_tree command is used to check all of the clocks
in the current design:
prompt> check_clock_tree
In the following example, the check_clock_tree command is used to check a specific list of
clocks in the current design:
prompt> check_clock_tree -clocks [list clock1 clock2]
When using the solution_template option, the command writes a file with a suggestion on
how to resolve the warning. For example, the CTS-871 warning, which warns about poor
skew at ETM/ILM entrance pin, can be resolved by either setting a float_pin or by setting an
exclude exception. The command writes both solutions to the file by commenting the second
solution as follows:
prompt> check_clock_tree -solution_template suggestion.txt
The file suggestions.txt has:
###############CTS-871 Solution File###############
set_clock_tree_exception -float_pins [get_pins u_ETM/CLK]
-float_pin_max_delay_rise 0.2
-float_pin_min_delay_rise 0.2
-float_pin_max_delay_fall 0.2
-float_pin_min_delay_fall 0.2
#--------------------#set_clock_tree_exceptions -exclude_pins [get_pins u_ETM/CLK]
#----------------------
Using solution_for option, you can select which of the two suggestions provided to the
solution file without "#".
The following command:
prompt> check_clock_tree -solution_template
-solution_for {CTS-871-2}
suggestion.txt \
produces:
###############CTS-871-2 Solution File###############
set_clock_tree_exceptions -exclude_pins [get_pins u_ETM/CLK]
#----------------------
If you specify an incorrect solution id, the command issues a warning as follows:
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prompt> check_clock_tree -solution_template solution.out -option
{cts-860-3}
Warning: your input of check cts-860-3 is incorrect: either wrong input
format or wrong option ID
Please enter your solution option list as {cts-823-1 cts-835-2 cts-871-1
cts-862-1 ...}
No solution is provided for this check
The complete list of supported values and solutions for the -solution_for option is as
follows:
Cts-823-1
Define a missing generate clock to resolve the
warning by default
CTS-823-2
Define an exclude pin on the conflict pin to
resolve the warning by default
CTS-834-1
Set multiple clocks per register by default
CTS-835-1
Remove exception from output pin by default
CTS-835-2
Move exception from output pin to input pin by
default
CTS-837-1
set_clock_tree_exceptions on those clock tree
synthesis ignored dont_touch/size_only by default
CTS-841-1
Remove blocked exceptions by default
CTS-850-1
Add cells to reference list by default
CTS-858-1
Remove exception from clock source by default
CTS-859-1
Remove max_buffer_level/max_fanout setting by
default
CTS-860-1
Reset conflict floating value with larger one
by default
CTS-860-2
Reset conflict floating value with smaller one
by default
CTS-861-1
Define a missing generate clock to resolve the
warning by default
CTS-861-2
Define an exclude pin on the balance conflict
pin to resolve the warning by default
CTS-862-1
Set clock tree exception on balance conflict
sinks by default
CTS-862-2
Remove the exception which causes the balance
conflict by default
CTS-866-1
Remove ICDB conflict offset with bigger value
by default
CTS-867-1
Remove ICDB option with smaller target delay
value by default
CTS-868-1
Remove ICDB conflict offset option by default
CTS-869-1
Remove ICDB root with bigger conflict offset
value by default
CTS-869-2
Remove ICDB root with smaller conflict offset
value by default
CTS-871-1
Define a float_pin value on entrance pin of
ILM/ETM with skew issue by default
CTS-871-2
Define an exclude pin on entrance pin of ILM/
ETM with skew issue by default
CTS-875-1
Remove the exception to allow clock tree
synthesis to buffer the nets.
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SEE ALSO
compile_clock_tree(2)
report_clock_timing(2)
report_clock_tree(2)
set_clock_tree_exceptions(2)
check_clock_tree
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check_database
Checks the integrity of the design database to ensure that the design information has been
correctly stored.
SYNTAX
status check_database
[library_name]
[-verbosity low | medium | high]
[-physical]
[-netlist]
Data Types
library_name
string
ARGUMENTS
library_name
Specifies the name of a Milkyway design library to check; the command checks all cells
in the library. By default, the command checks only the currently open cell.
-verbosity low | medium | high
Specifies the level of detail in the report. The default is low. Set this option to medium
or high to get more detailed messages.
-physical
Specifies checking of physical information, which includes (but is not limited to) the
floorplan, physical wiring, and UPF data. If neither -physical nor -netlist is specified, all
information is checked.
-netlist
Specifies checking of logical netlist information, which includes (but is not limited to)
netlist connectivity data. If neither -physical nor -netlist is specified, all information is
checked.
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DESCRIPTION
This command checks the database integrity and reports any database problems found. It
evaluates how the data is stored and whether this meets the database rules of construction.
However, it does not determine whether the design information is correct or whether a legal,
valid design can be constructed.
EXAMPLES
The following commands check the database consistency for the currently open cell.
prompt> open_mw_lib orca_lib.mw
{orca_lib.mw}
prompt> open_mw_cel signal_route1
{signal_route1}
prompt> check_database
******************************************************
CHECK_DATABASE RESULTS FOR CELL : signal_route1.CEL
******************************************************
Warning: The hierarchical net 'VDD' is inconsistent with the flat net
'VDD'.
Warning: The via "via12Fat_3_4" data is corrupted.
prompt> check_database -verbosity high
...
Warning: The hierarchical net 'VDD' is inconsistent with the flat net
'VDD'.
The hierarchical net 'VDD' is power, while the flat net 'VDD' is signal.
The hierarchical net 'VDD' is connected to leaf pin 'U1/A', but the flat
net 'VDD' is not.
The hierarchical net 'VDD' is connected to leaf pin 'U2/A', but the flat
net 'VDD' is not.
Warning: The via "via12Fat_3_4" data is corrupted.
Via instance 0xF0 has a lower enclosure wire 0xC0 that does not match the
via master enclosure size.
Via instance 0xF8 has a lower enclosure wire 0xC8 that does not match the
via master enclosure size.
prompt> check_database -verbosity high -physical
...
Warning: The via "via12Fat_3_4" data is corrupted.
Via instance 0xF0 has a lower enclosure wire 0xC0 that does not match the
via master enclosure size.
Via instance 0xF8 has a lower enclosure wire 0xC8 that does not match the
via master enclosure size.
prompt> check_database -verbosity high -netlist
...
Warning: The hierarchical net 'VDD' is inconsistent with the flat net
'VDD'.
The hierarchical net 'VDD' is power, while the flat net 'VDD' is signal.
The hierarchical net 'VDD' is connected to leaf pin 'U1/A', but the flat
net 'VDD' is not.
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The hierarchical net 'VDD' is connected to leaf pin 'U2/A', but the flat
net 'VDD' is not.
SEE ALSO
open_mw_cel(2)
check_design(2)
check_physical_design(2)
report_design(2)
Chapter 1:
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check_design
Checks the current design for consistency.
SYNTAX
status check_design
[-summary]
[-no_warnings]
[-one_level]
[-multiple_designs]
[-no_connection_class]
[-post_layout | -only_post_layout]
[-nosplit]
[-unmapped]
[-cells]
[-ports]
[-designs]
[-nets]
[-tristates]
[error-ids]
[-html_file_name html_file]
ARGUMENTS
-summary
Displays a summary of the warning messages instead of one message per warning.
This does not affect the way error messages are issued. The -summary option used
along with the -post_layout or the -only_post_layout option only displays a summary
of the missing back-annotation information.
-no_warnings
Suppresses warning messages, so only error messages are printed.
-one_level
Performs checks at only the current level of hierarchy. By default, check_design checks
the current level and all designs below the current level.
-multiple_designs
Reports warning messages related to multiply-instantiated designs. With this option, the
tool lists all multiply-instantiated designs along with instance names and associated
attributes, such as dont_touch, black_box, and ungroup. By default, these messages
are suppressed.
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-no_connection_class
Suppresses connection class warning messages. This switch is useful while working on
GTECH designs and netlists on which connection class violations are expected. By
default, these messages are reported.
-post_layout
Checks the design for annotated information in a links-to-layout flow. The information is
annotated on the design after the design has been placed and routed by the backend
tool. This includes delay back-annotation, resistance back-annotation, capacitance
back-annotation, and PDEF back-annotation; for example, clusters, cell locations, and
so on. The -post_layout option lists designs or instances that have any of these
annotations missing. This option must be used at least once for a design flow to validate
the back-annotation part of the links-to-layout flow.
-only_post_layout
Checks only the annotated information in a links-to-layout flow. The information includes
delay back-annotation, resistance back-annotation, capacitance back-annotation, and
PDEF back-annotation; for example, clusters, cell locations, and so forth. This option
lists designs or instances that have any of these annotations missing. The
-only_post_layout option can be used instead of the -post_layout option to validate
the back-annotation part of the links-to-layout flow.
-nosplit
Prevents lines from being split when column fields overflow. Most of the design
information is listed in fixed-width columns. If the information for a given field exceeds
the column width, the next field begins on a new line in the correct column.
-unmapped
Reports warning messages for unmapped cells when the cells are being checked. By
default, these messages are suppressed.
-cells
Reports the following warning messages for cells: LINT-0, LINT-1, LINT-10, LINT-32,
LINT-33, LINT-58, LINT-59, LINT-60, and LINT-61 (if the -unmapped option is used).
-ports
Reports the following warning messages for ports: LINT-5, LINT-6, LINT-8, LINT-28,
LINT-29, LINT-31, and LINT-52.
-designs
Reports the following warning messages for designs: LINT-25, LINT-46, and LINT-55.
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-nets
Reports the following warning messages for nets: LINT-2, LINT-3, LINT-4, LINT-35,
LINT-38, LINT-47, and LINT-54.
-tristates
Reports the following warning messages for tristates: LINT-34 and LINT-63.
error-ids
Reports warning messages for specified error IDs, such as LINT-2.
-html_file_name html_file
Generates a report for the check_design command in HTML format. By default, the
check_design command writes reports in standard output. The -html_file_name
option redirects the output to a specified HTML file.
DESCRIPTION
The check_design command checks the internal representation of the current design for
consistency, and issues error and warning messages as appropriate.
Error messages indicate design problems of such severity that the compile command does
not accept the design; for example, recursive hierarchy in a design (when a design
references itself) is an error. Warning messages are informational and do not necessarily
indicate design problems. However, these messages should be investigated.
The check_design command flags multiple instances of a design within a system. If a
design is instantiated in two different designs, a warning message is issued. For information
on how to respond to error messages dealing with multiple instances, see the uniquify
command man page.
The check_design -summary command automatically runs on every design that is
compiled. However, you can use the check_design command explicitly to see warning
messages.
Potential problems detected by this command include unloaded input ports or undriven
output ports, nets without loads or drivers or with multiple drivers, cells or designs without
inputs or outputs, mismatched pin counts between an instance and its reference, tristate
buses with non-tristate drivers, wire loops (timing loops with no cells in them) across
hierarchies, and so forth.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following command checks the current design for problems and issues error and
warning messages:
prompt> check_design
The following command checks only the current level of the design:
prompt> check_design -one_level
SEE ALSO
check_library(2)
check_timing(2)
current_design(2)
set_dont_touch(2)
uniquify(2)
check_design_allow_non_tri_drivers_on_tri_bus(3)
check_design_check_for_wire_loop(3)
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check_error
Reports extended information on message IDs from the last command.
SYNTAX
status check_error
[-verbose]
[-reset]
ARGUMENTS
-verbose
Displays the list of message IDs found during previous commands.
By default, the command only returns the error status.
-reset
Resets the list of previously found message IDs. After resetting the error list, the
check_error -verbose command returns an empty list.
By default, the command does not modify the message list.
DESCRIPTION
The check_error command is used to compare error, warning, or informational messages
issued by previous commands to the list of message IDs specified by the check_error_list
variable. While it is most commonly used for error messages, the variable may contain error,
warning, or informational message IDs.
If the check_error command finds message IDs that are specified in the check_error_list
variable, the command returns 1. If the check_error command does not find any messages
that are specified by the check_error_list variable, the command returns 0.
Messages that are suppressed by the suppress_message command are reported by
check_error. If you want suppressed messages to be ignored by check_error then you
must remove their message IDs from the check_error_list variable.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example shows how to use the check_error command to check if execution
errors are specified by the check_error_list variable:
prompt> printvar check_error_list
check_error_list
= "UID-3 UID-4 EQN-18 EQN-19"
prompt> check_error
0
prompt> link
Error: Current design is not defined. (UID-4)
0
prompt> check_error
1
prompt> check_error -verbose
{UID-4}
1
The following command resets the error list:
prompt> check_error -reset -verbose
{UID-4}
1
prompt> check_error -verbose
0
To use the check_error command in a script to see if specified errors occurred in the
previous commands, use the following command:
prompt> if { [check_error] } {
echo failure_message
exit
} else {
echo success_message
}
SEE ALSO
check_error_list(3)
suppress_message(2)
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check_fp_budget_result
Performs post-budgeting timing analysis.
SYNTAX
status check_fp_budget_result
-file_name output_design_report
[-blocks block]
[-pins pin]
[-html]
[-html_dir dir_name]
Data Types
output_design_report
block
pin
dir_name
string
string
string
string
ARGUMENTS
-file_name output_design_report
Specifies the name of the ASCII format output timing budgeting report file to write. Use
the -html and -html_dir options to write an HTML format report. This option is required.
-blocks block
Specifies name of the plan groups to include in the timing budgeting report. You can
specify the block argument by specifying a collection generated by the get_cells
command. By default, the command generates the budgeting analysis report for all pins
on all plan groups.
-pins pin
Specifies name of a pin on a plan group to include in the timing budgeting report. You
can specify the value of pin by using a collection generated by the get_pins command.
By default, the command generates the budgeting analysis report for all pins on all plan
groups.
-html
Generates an HTML-format report in addition to the ASCII-format report.
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-html_dir dir_name
Specifies the name of the directory in which to generate the HTML-format report. If you
do not specify this option, the tool writes the HTML-format report to the
check_budget_result_html directory.
DESCRIPTION
This command generates a report containing budgeted and actual delays through a
hierarchical block. A timing path starts at a startpoint and ends at an endpoint. For this
report, hierarchical pins separate timing paths into timing path segments. This report
contains the actual and budgeted delay for each of timing path segment. You can use this
report to analyze the timing budgeting process.
For each pin on the block, the report lists the worst-case timing paths per clock domain
passing through the pin. The report shows the budgeted and actual delays for each path
segment on the timing path.
This command can be run only after running the IC Compiler Timing Budgeter.
If you do not specify the -blocks or -pins options, the command writes out the information
for the entire design. You can specify the -blocks or -pins option to restrict the information
written.
The information in the report file is divided by soft macro or plan group. All the timing path
information related to one soft macro or plan group is grouped together.
If you specify the -html option, the command generates an HTML-format report in addition
to the ASCII-format report file.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example creates a report file named Ib1.rpt that contains timing budgeting
information about the B1 block.
prompt> check_fp_budget_result -blocks B1 -file_name b1.rpt
The following example creates a report file named all.rpt that contains timing budgeting
information about the entire design.
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prompt> check_fp_budget_result -file_name all.rpt
SEE ALSO
allocate_fp_budgets(2)
check_fp_timing_environment(2)
get_cells(2)
get_pins(2)
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check_fp_pin_alignment
Checks the soft macro or plan group pin alignment QoR.
SYNTAX
status check_fp_pin_alignment
[-detour]
[-tolerance real]
[-report_nets]
[-nets collection]
ARGUMENTS
-detour
Generates a detour report for soft macro or plan group pins.
Note that unlike pin alignment checking, pin detour checking is performed on all two-pin
and multi-pin nets connected to soft macros or plan groups.
The detour measure of a net is calculated as dividing the estimated routing length of the
whole net by the estimated routing length of the standard cell pins on this net.
If you specify this option, the tool computes a count of the number of nets in which such
a detour exists. When used in conjunction with the -report_nets option, the tool
generates an actual list of nets with detours. To suppress reporting of nets that are
slightly detoured, use the -tolerance option.
-tolerance real
Specifies the percentage tolerance for the detour report.
This option allows you to specify the percentage in which the perimeter of the first
bounding box is allowed to be larger than the perimeter of the second bounding box,
before the net is flagged as having a detour. It is useful for suppressing reporting of
slightly detoured nets by supplying it with a small tolerance value, such as 0.1.
The valid range for tolerance is from 0 through 100 percent. A tolerance value greater
than 100 is reset to 100. A tolerance value less than 0 is reset to 0.
The default value for tolerance is 0.
-report_nets
Prints out the individual net names in the pin detour and pin alignment report.
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By default, the tool outputs only the detoured net count.
-nets collection
Specifies the nets for which soft macro or plan group pin alignment and pin detour
checks are performed.
DESCRIPTION
This command checks the soft macro or plan group pin alignment QoR.
If you do not specify the -detour option, the tool performs normal alignment checking.
Alignment checking is limited to two-pin nets with at least one connection to a soft macro or
a plan group. Nets not connected to a soft macro nor a plan group or those with more than
two connections of any kind are not checked. In particular, a net connected to a top-level pin
(that is, a terminal) is not checked unless it is connected to a soft macro or a plan group on
the other end. A text report like the following is produced at the end of the alignment
checking:
******************************************************************
Report: check_fp_pin_alignment pin alignment check
Design: RISC_CORE
Version: F-2011.09
Date:
Thu Oct 27 20:10:35 2011
******************************************************************
All numbers cited pertain only to two-connection nets with at least one
soft macro connection
186 total two-connection nets
176 alignable two-connection nets (176 non-blocked)
23 unaligned alignable two-connection nets (23 non-blocked)
66 aligned two-connection nets on different metal layers
0 aligned two-connection nets on different metal layers (soft macro ->
soft macro connections)
The definitions for terms used in this report are as follows:
alignable nets
A two-pin net with only a single soft macro or a plan group pin is considered alignable if the
non-soft-macro non-plan-group pin (a terminal, a standard cell pin, or a hard macro pin) is
located within the projection of the soft macro or plan group edge on which the soft macro
or plan group pin is located. A two-pin net connected to soft macros or plan groups at both
ends is considered alignable if the projections of the soft macro or plan group edges on
which the soft macro or plan group pins sit overlap.
non-blocked
A two-pin net is considered "non-blocked" if the flyline connecting the two pins is not
interrupted by any soft macro, plan group or hard macro not connected to the net.
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If you specify the -report_nets option, the names of all nets that are alignable but are
unaligned are printed out.
If you specify the -detour option, a detour report is generated. A detour is caused by an
invalid soft macro or plan group pin placement, which causes routing from the source to
targets to be longer than is necessary. The detour report consists of a simple count of the
number of nets with a detour measure exceeding the tolerance specified by the -tolerance
option. Detour measures of interconnected feedthrough nets created by IC Compiler during
pin cutting or top-down pin placement are computed as a single net.
If you specify both the -report_nets option and the -detour option, the individual nets that
fail the detour test are listed in the detour report.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example checks the soft macro pin alignment using a detour report.
prompt> check_fp_pin_alignment -detour
******************************************************************
Report: check_fp_pin_alignment detour check
Design: TOP
Version: F-2011.09
Date:
Thu Oct 27 20:10:35 2011
******************************************************************
106 pin detours.
prompt> check_fp_pin_alignment -report_nets -detour
******************************************************************
Report: check_fp_pin_alignment detour check
Design: RISC_CORE
Version: F-2011.09
Date:
Thu Oct 27 20:10:36 2011
******************************************************************
2 pin detours.
/****************** Nets with pin detour, tolerance = 0.000000
***************
OUT_VALID
Oprnd_A[11]
*******************************************************************
SEE ALSO
check_fp_pin_assignment(2)
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check_fp_pin_assignment
Performs pin placement checks.
SYNTAX
status check_fp_pin_assignment
[-block_level [-net_routing_constraints]]
[-layers]
[-macro_type soft_macros | hard_macros | all]
[-match_pin_shapes]
[-missing]
[-nets net_collection]
[-no_stacking]
[-off_edge]
[-outside_pin_guide]
[-pin_mask_constraint]
[-pin_size]
[-pin_preroute_spacing]
[-pin_spacing]
[-pin_type signal_pins | pg_pins | all]
[-shorts]
[-single_pin connected | unconnected | all]
[-wiretrack [-preferred_wiretrack_only] [-allow_half_wiretrack]]
[objects]
Data Types
net_collection
objects
collection
collection
ARGUMENTS
-block_level
Checks block-level pin placement. The tool performs the tests you specify on top-level
pins. By default, the command checks soft macro pins.
-net_routing_constraints
Checks if the soft macro pins, plan group pins, or top-level terminals comply with the
constraints set by using the set_net_routing_rule command or the
set_net_routing_layer_constraints command. The tool checks the pin layer, pin
width, and pin spacing against the specified constraints. You must use this option with
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the -block_level option; otherwise, it is ignored. By default, the command does not
check net routing constraints.
-layers
Determines if pins are placed on legal metal layers as specified by the -allowed_layers
option of the set_fp_pin_constraints command. For information about the default
minimum and maximum metal layers used for pin placement, see the
set_fp_pin_constraints man page. By default, the command does not perform this
check.
-macro_type soft_macros | hard_macros | all
Specifies the types of macros for pin checking. Accepted values are
•
soft_macros
Checks soft macro pins.
•
hard_macros
Checks hard macro pins. Hard macro pin checks are limited to the
-match_pin_shapes, -single_pin, -shorts, -missing, and -off_edge options. All
other checks specified with the -macro_type hard_macros option are silently
ignored.
•
all
Checks both soft and hard macro pins.
By default, the tool checks only soft macro pins and pins specified by the -single_pin
option. The pins checked by the -single_pin option depend on the setting of the
-pin_type option.
-match_pin_shapes
Checks if the macro pins or plan group pins on overlapping or abutted edges match. This
option applies to pins placed on or straddling an abutted edge. Only pins that touch each
other without shorting are tested. In the case of abutting pins, every abutting edge of a
pin must be fully abutted with an abutting edge of one or more pins. That is, an abutting
edge should not have any part of the edge that is not covered by an edge of the abutting
pin. In the case of overlapping pins, their boundaries must match exactly. The command
checks macro or plan group pins that overlap terminals. Pins that fail to satisfy either one
of the two criteria are flagged. The command ignores this option if you use the
-block_level option. By default, the command does not perform this check.
-missing
Determines if any pins are missing. By default, the command does not perform this
check.
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-nets net_collection
Specifies the collection of nets for pin placement checking. If you specify this option, the
command checks pin placement only on the soft macro pins and relevant hard macro
pins connected to the specified nets. If your design contains plan groups, the command
checks pin placement only on plan group pins connected to the specified nets if plan
groups are given in the objects argument.
If you do not specify this option, but specify macros for the objects argument, the
command checks all relevant pins on the specified soft and hard macros. Similarly, if you
do not specify this option, but specify plan groups for the objects argument, the
command checks all relevant pins on the specified plan groups. If you do not specify
either this option or the objects argument, the command checks all relevant soft and
hard macro pins.
-no_stacking
Checks for stacking constraint violations set by the -no_stacking option of the
set_fp_pin_constraints command. The stacking constraints specify the proper
conditions for overlapping pins on different layers. Valid values for this constraint are
stacking_allowed, pg_pins_only, signal_pins_only, or all. For more information
about these constraints, see the set_fp_pin_constraints man page. By default, the
command does not perform this check.
The command does not check stacking constraints if you did not set them by using the
set_fp_pin_constraints command. If you did set stacking constraints, each macro or
specified plan group is checked based on the assigned stacking constraint. For
example, if a design contains macros A, B, and C with the following stacking constraints:
•
Macro A: Pin stacking is allowed for both power and ground (PG) pins and signal
pins.
•
Macro B: Pin stacking is not allowed on either PG pins or signal pins.
•
Macro C: Pin stacking is allowed only for signal pins.
The command performs the following tests by using the check_fp_pin_assignment
-no_stacking command:
•
Macro A: The command does not check for pin stacking and allows both types of
stacking for this macro.
•
Macro B: The command checks stacking on both PG and signal pins.
•
Macro C: The command checks stacking only on PG pins.
The -no_stacking option also turns on the -shorts option.
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If you use the -block_level option, the command performs terminal checks based on the
stacking setting assigned in an earlier call to the set_fp_pin_constraints -block_level
command.
-off_edge
Determines if part of a pin outline coincides with an edge. A soft macro pin or plan group
pin is flagged if none of the pin edges coincide with its block edges. If you use the
-block_level option, the command flags a terminal if none of its edges coincide with an
edge of the top-level cell. By default, the command does not perform this check.
-outside_pin_guide
Checks if the center of a pin is outside the associated pin guide. By default, the
command does not perform this check.
-pin_mask_constraint
Checks if abutted pins have conflicting mult pattern mask constraints. The mult pattern
mask constraint for the pin is set by the user or the tool. The constraint allows the mask
to be decomposed easily during manufacturing using mult patterning technology.
The following combinations of double pattern mask constraints values for abutted pins
are considered illegal:
•
mask1_hard vs. mask2_hard
•
mask1_hard vs. mask2_soft
•
mask1_soft vs. mask2_hard
•
mask1_soft vs. mask2_soft
•
Any nonzero double pattern mask constraint vs. zero
-pin_size
Checks if pins honor their width and depth constraints. If the pins do not have width or
depth constraints, but are on the double patterning layers, this option checks if the pins
honor the default double patterning pin depth requirement. If pins have width and depth
constraints and are also on double patterning layers, this option checks only if the width
and depth constraints are honored.
-pin_preroute_spacing
Determines if any signal pin is closer to a preroute than the number of wire tracks
specified by the -pin_preroute_spacing option of the set_fp_pin_constraints
command. By default, the command does not perform this check.
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-pin_spacing
Determines if any two signal pins are closer than the number of wire tracks specified by
the -pin_spacing option of the set_fp_pin_constraints command. By default, the
command does not perform this check.
-pin_type signal_pins | pg_pins | all
Specifies the types of pins to be checked. Valid values are
•
signal_pins
Checks signal pins.
•
pg_pins
Checks power and ground pins. Power and ground pin checks are limited to the
-match_pin_shapes, -single_pin, -shorts, -layer, -missing, and -off_edge
options. All other checks specified with the -pin_type pg_pins option are silently
ignored.
•
all
Checks both signal pins and power and ground pins.
If you do not specify this option, only signal pins are checked.
-shorts
Checks for shorts that are caused by two pins on the same layer that touch or overlap
each other. By default, the command does not perform this check.
-single_pin connected | unconnected | all
Checks for unroutable pins on abutted edges. Valid values for this option are:
•
connected
A macro or plan group pin is flagged as a single (unroutable) pin if any one of the
following are true:
The macro or plan group pin is placed on a block edge that abuts another
block
•
❍
edge and the macro or plan group pin does not abut the other block pin on the
same metal layer.
The macro or plan group pin is placed on a block edge that coincides with the •
❍
top-level cell boundary and connects to anything other than a terminal (top-level
pin), unless the pin connects only to other pins on the same block and those pins
are stacked on top of the pin.
The macro or plan group pin is placed on a block edge that coincides with the •
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top-level cell boundary and the macro or plan group pin is connected only to a
terminal, but the terminal is not stacked on top of the macro or plan group pin on
the same metal layer.
unconnected
A macro or plan group pin is flagged as a single (unroutable) pin if either one of the
following is true:
The macro or plan group pin is logically unconnected to any pin or terminal
and is
•
❍
placed on a part of the block edge that abuts another block edge.
The macro or plan group pin is logically unconnected to any pin or terminal
and is
•
❍
placed on a part of the block edge that coincides with the top-level cell boundary.
•
When you specify -single_pin unconnected, the command also checks terminals.
A terminal is flagged if it is logically unconnected and is located on a top-level cell
boundary that abuts a macro edge.
•
all
A macro or plan group pin is flagged as a single (unroutable) pin if any of the
scenarios described for connected or unconnected occur.
This option performs routability checks on soft macro and hard macro pins. No other
checks are performed on hard macro pins unless you use the -macro_type
hard_macro option. For more details, see the descriptions for the -macro_type and
-single_pin options.
If hard macro pins are detected which are off of the hard macro boundary, it is interpreted
as a "center" pin, and it is reported as a single pin if there is not a top-level terminal
stacked on top of the pin.
This option is ignored if you specify the -block_level option. By default, the command
does not perform this check.
-wiretrack
Determines if pins are centered on wire tracks. A vertical wire track on the same layer as
the pin must coincide with the vertical central axis of the pin for pins on a horizontal
edge. A horizontal wire track must coincide with the horizontal central axis of a pin on a
vertical edge. For an off-edge pin, the pin's vertical and horizontal central axes must
coincide with a horizontal and a vertical wire track, respectively, unless you use the
-preferred_wiretrack_only option. By default, the command does not perform this
check.
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-preferred_wiretrack_only
Determines if off-edge pins are centered on preferred wire tracks only. Use this option
with the -wiretrack option for verification of off-edge pins. When this option is used, the
command verifies that off-edge pins are centered on wire tracks in the preferred
direction of the metal layer of the pins. The pins are not checked against the wire tracks
in the nonpreferred direction. You must use this option together with the -wiretrack
option; otherwise the -preferred_wiretrack_only option is silently ignored.
-allow_half_wiretrack
Allow pins to be centered on half wire tracks. A pin on a vertical half wire track is defined
as a pin where the vertical central axis of the pin coincides with a center line halfway
between adjacent vertical wire tracks of the same layer. Similarly, a pin on a horizontal
half wire track is defined as a pin where the horizontal central axis of the pin coincides
with a center line halfway between adjacent horizontal wire tracks of the same layer.
This option must be used in conjunction with the -wiretrack option. If you specify both
the -wiretrack -allow_half_wiretrack options, the command does not flag pins that are
on the half wire track and only reports pins that are not centered on wire track and half
wire track. By default, this option is off.
objects
Specifies the collection of macros or plan groups for pin placement checking. Either soft
macros or plan groups, or a mixture of both can be in the objects argument.
The command checks pin placement only on the macros or plan groups you specify. By
default, if no macros or plan groups are specified, the command checks the pins on all
soft and relevant hard macros.
DESCRIPTION
This command performs the selected pin placement checks using the constraint values set
by the set_fp_pin_constraints command. The command uses default pin constraints if you
have not set pin constraints. You can review the pin constraints with the
report_fp_pin_constraints command.
If you use the -block_level option, the command performs checks on terminals (top-level
pins).
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example checks a soft macro named blockA for shorted and missing pins. It
also determines if any two signal pins are closer than the number of wire tracks previously
specified by the -pin_spacing option of the set_fp_pin_constraints command.
prompt> check_fp_pin_assignment -shorts -missing \
-pin_spacing [get_cells blockA]
The following example checks that soft macro pins are placed on wire tracks.
prompt> check_fp_pin_assignment -block_level -wiretrack
SEE ALSO
check_fp_pin_alignment(2)
report_fp_pin_constraints(2)
set_fp_pin_constraints(2)
set_net_routing_rule(2)
set_net_routing_layer_constraints(2)
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check_fp_rail
Checks the integrity of the power network created by power network synthesis, early in the
design planning stage.
SYNTAX
status check_fp_rail
-nets nets
[-ring]
[-floating_segment]
[-power_switch_connection]
Data Types
nets
collection or list
ARGUMENTS
-nets nets
Specifies the net name(or names) of the power network for integrity checking. If no
power straps exist with the specified net name, the command fails and issues an error
message. You can specify a single net name or multiple net names separated by a
comma or a space.
-ring
Checks only the core rings of the power network. If a core ring segment is broken, a
warning message is issued. By default this option is off.
-floating_segment
Checks only the floating segments in the power network. If a floating segment is
detected, a warning message is issued. By default, this option is off.
-power_switch_connection
Checks only the connection between power switch cell input pin and the permanent
power/ground straps. If there are unconnected power switch input pins, a warning
message is issued. Use this option in a multivoltage design with power-down voltage
areas. By default, this option is off.
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DESCRIPTION
This command allows you to check the integrity of the power network created by the
synthesize_fp_rail and the commit_fp_rail commands early in the design stage. If there
are broken core rings, floating segments, or unconnected power switch input pins in the
power mesh, a warning message is issued.
EXAMPLES
The following example shows how to check the VDD ring of a power plan.
prompt> check_fp_rail -net {VDD} -ring
WARNING: Core ring is broken at (123.400 227.900)
SEE ALSO
synthesize_fp_rail(2)
commit_fp_rail(2)
check_fp_rail
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check_fp_timing_environment
Performs timing environment analysis.
SYNTAX
int check_fp_timing_environment
[-block_pin_stats]
[-unbudgetable_pins]
[-unconstrained_pins]
[-exception_pins]
[-static_logic_pins]
[-delay_violators percent]
[-num_pin_connections connections]
[-block_name block_name]
[-pin_name pin_name]
[-zero_wire_delay negative_slack_percent]
[-bottleneck slack_limit]
[-bottleneck_max_cell num_cells]
[-bottleneck_no_vipo]
[-vipo_timing slack_percent]
[-format_report]
Data Types
connections
block_name
pin_name
negative_slack_percent
slack_limit
num_cells
slack_percent
integer
string
string
float
float
integer
float
ARGUMENTS
-block_pin_stats
Specifies whether to print block pin statistics. It prints the number of budgetable pins, the
number of unbudgetable pins, and the total number of pins on the block.
-unbudgetable_pins
Specifies whether to print block pins that cannot be budgeted. It prints the reason each
pin cannot be budgeted:
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* Pin is not connected to net* Pin is not connected to a top-level
net, but is connected to an internal net* Pin is not connected to
an internal net, but is connected to a top-level net* Only fixed
delay exists on one side of the pin* Timing paths through the pins
are not constrained* Pin is an input or output clock port* Pin is
connected to power or ground net, or has set_case_analysis on it
-unconstrained_pins
Specifies whether to print unconstrained block pins. A pin is unconstrained if it has no
timing paths through it.
-exception_pins
Specifies whether to print block pins touched by an exception. The exception can be
set_false_path, set_multicycle_path, set_min_delay, or set_max_delay.
-static_logic_pins
Specifies whether to print block pins that are set to static logic state. It prints whether a
block pin is tied to high or low by a power or ground net in the input netlist. It also reports
if a block pin is set to specific state by set_case_analysis, set_logic_one, or
set_logic_zero.
-delay_violators percent
Specifies whether to print cells with delays greater than the specified percentage of the
capture clock period. The percent argument must be greater than or equal to zero. The
command traverses all critical paths per clock domain through a block pin.
-num_pin_connections connections
Specifies whether to print the number of net connections from this block to other blocks,
top-level standard cells, pad cells, or to top-level ports. The connections argument must
be greater than zero. This option also specifies the number of connections to be
displayed in the GUI for each type of net connection.
-block_name block_name
Specifies whether to print a budgeting report for a particular block only. The name of
block could be a plan group, instance name, or master name.
-pin_name pin_name
Specifies whether to print a budgeting report for a particular pin only. The name of pin
must exactly match a pin on the plan group.
-zero_wire_delay negative_slack_percent
Specifies whether to perform timing analysis with zero wire delays and print the paths
that have slack less than the negative percentage of the capture clock period. The
check_fp_timing_environment
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negative_slack_percent argument must be less than zero. Both the path and the number
of logic levels on the path are printed.
-bottleneck slack_limit
Specifies whether to report bottleneck cells. It prints the leaf cells that contribute to
multiple timing violations. It lists the leaf cell, its reference, and the number of paths
through the leaf cell that have timing violations. Based on this report, you can check the
fanin and fanout logic to determine the possible cause of the timing bottleneck.
It also specifies the slack limit for reporting bottleneck cells. Only timing paths having
slack less than slack_limit are explored for finding bottleneck cells.
-bottleneck_max_cell num_cells
Specifies the number of bottleneck cells to report. The num_cells argument must be
greater than zero. If this option is not specified, a maximum of 20 bottleneck cells are
reported.
-bottleneck_no_vipo
Specifies whether to perform virtual in-place optimization (VIPO) before reporting
bottleneck cells. The default is to run virtual in-place optimization.
-vipo_timing slack_percent
Specifies whether to report timing analysis results based on virtual in-place optimization
(VIPO). This report can help visualize the timing analysis report after the actual in-place
optimization has been run.
It also specifies the slack limit for timing paths in the virtual in-place optimization timing
report. Only the paths having slack less than slack_percent of the capture clock period
are reported.
-format_report
Specifies whether to format the report in table form. If this option is not specified, the
report is printed in a single line format. The report in table form is easier to look at, but
might be difficult to parse using automated tools.
DESCRIPTION
This command generates a report that contains additional design information that helps you
analyze the budgets assigned to each block. The block can be a plan group or a soft macro.
The report can be used to debug the budgets generated by the IC Compiler design planning
timing budgeter.
Chapter 1:
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The additional design information includes, but is not limited to, timing constraints in the
design, timing exceptions in the design, delay distribution on the worst timing path through
a block port, pins tied to high or low, high negative slack on a timing path, and so on.
This command can be run before or after calling the IC Compiler design planning timing
budgeter.
All of the command options are optional. The options determine the type of information put
in the output report.
If no options are specified, no information is written out. You must provide at least one option
to have something in the output report.
In the output, the following information is printed for the whole design:
* zero wire delay based negative slack paths
* bottleneck cells
* virtual in-place optimization timing report
The rest of the report is divided by soft macro or plan group. All the timing environment
information related to one soft macro or plan group is printed together.
The -bottleneck_max_cell and -bottleneck_no_vipo options are ignored if the
-bottleneck option is not specified.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following command creates a report file, stat.rpt, that contains summary information
about budgetable, unbudgetable and total block pins in the design.
prompt> check_fp_timing_environment -block_pin_stats > stat.rpt
The following command creates a report file, violators.rpt, that contains cell delay violators.
The cells are printed if they have a delay of more than 50 percent of the related clock period.
prompt> check_fp_timing_environment -delay_violators 50 > violators.rpt
The following example reports block pins that are unconstrained or have timing exceptions
on them.
prompt> check_fp_timing_environment -unconstrained_pins \
-exception_pins
check_fp_timing_environment
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The output has the following format:
=====================================================
Plan Group Name: <PG Name>, Master Name: <Reference Name>
=====================================================
##### Information regarding block pins without constraint or delay
information
Plan Group Port = <port name1>: is not constrained.
Plan Group Port = <port name2>: is not constrained.
##### Information regarding blocks pins that are touched by an exception
Plan Group Port = <port name3>: Port touched by set_false_path exception.
Plan Group Port = <port name4>: Port touched by set_multicycle_path
exception.
SEE ALSO
allocate_fp_budgets(2)
check_fp_budget_result(2)
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check_freeze_silicon
Performs an eco cell to spare cell mapping feasibility analysis on the design. This command
is typically used in a freeze silicon ECO flow.
SYNTAX
status check_freeze_silicon
ARGUMENTS
The check_freeze_silicon command has no arguments.
DESCRIPTION
The check_freeze_silicon command performs an eco cell to spare cell mapping feasibility
analysis on the design.
The report includes the number of eco cells and spare cells in the design, and the eco cells
mapping feasibility analysis, and other useful information about the lib cell, such as
threshold voltage group, drive strength and power leakage.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows feasibility check report.
prompt> check_freeze_silicon
****************************************
Report : feasibility check
Design : CORE
Version: G-2012.06-SP4
Date
: Mon Sep 24 20:45:23 2012
****************************************
// Check freeze silicon report summary
=======================================================
check_freeze_silicon
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Type
Eco Number
Spare Number
Total:
13
60
=======================================================
// ECO CELLs mapping feasibility:
=======================================================
// These references don't have spare cells:
OAI31X1
DLY4X4
INVX3
AND4XL
OAI2BB2X1
// These references don't have enough spare cells:
Type
Eco Number
Spare Number
NAND4XL
3
2
INVXL
3
1
=======================================================
// Eco vs Spare detail report
=========================================================================
===============================
Type
Eco Number
Spare Number
Vth_group
Drive_strength
Power_leakage
INVX8
-4
-0.859444
8823.709961
BUFX6
1
2
--
1
2
--
1
--
--
3
1
--
NOR3X8
-13190.655273
3
--
AND3XL
-8040.989746
2
--
XOR2X1
-17071.150391
2
--
BUFX8
-19169.406250
2
--
AND4X2
-7329.886719
2
--
OR2XL
-15510.257812
3
--
XOR3XL
-27894.359375
3
--
0.839473
16106.979492
AND3X8
0.940156
16749.720703
OAI31X1
0.077852
2839.916260
INVXL
0.059397
557.142517
0.553695
0.052200
0.087977
1.112450
0.216134
0.063906
0.038241
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XOR2XL
-20550.919922
2
--
AND2XL
-7234.810059
3
--
0.042525
0.059008
1
--
--
0.253915
DLY4X4
10905.224609
CLKMX2X6
0.564671
-40903.886719
3
--
NAND4XL
0.063678
3
2
--
2177.355713
-56905.968750
3
--
1
--
--
-28681.214844
3
--
1
--
--
1
--
--
AND2X8
-17233.214844
3
--
1.030519
XNOR3XL
0.038401
-27853.902344
2
--
OR3X1
-20829.560547
3
--
OR3X2
-14829.480469
2
--
NOR3XL
-884.248291
3
--
AND4X1
-5172.642578
2
--
CLKMX2X8
0.836803
-33615.250000
3
--
XOR3X4
0.355980
OAI2BB2X1
0.085834
OR2X8
1.001016
6651.741699
AND4XL
0.047527
8035.480957
INVX3
0.317955
3221.233887
0.107236
0.233281
0.035706
0.094153
Type
Eco Number
Spare Number
Vth_group
Drive_strength
Power_leakage
=========================================================================
===============================
Feasibility check completed.
check_freeze_silicon
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1
SEE ALSO
place_freeze_silicon(2)
map_freeze_silicon(2)
create_freeze_silicon_leq_change_list(2)
Chapter 1:
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check_interface_optimization_setup
Checks the setup for performing interface optimization by using the route_opt command.
SYNTAX
status check_interface_optimization_setup
[-distributed_hosts]
[-initialization]
ARGUMENTS
-distributed_hosts
Checks only the distributed processing setup specified for parallel execution of block
update during interface optimization by using the route_opt command.
When you specify this option, the tool:
1) Identifies the blocks and host options specified by using the
set_top_implementation_options command
2) Checks the directory and file permissions
3) Tests distributed processing using options that are specified by using the
set_host_options and set_top_implementation_options commands.
If you do not specify either the -distributed_hosts or -initialization option, the tool
performs both the distribution host and initialization checks.
-initialization
Checks only the consistency of the blocks floorplan data, which is loaded during
interface optimization with the top-level floorplan data. This check is done for each of the
blocks opened for interface optimization. The consistency checks are performed for site
arrays, VA, bounds, routing layers loaded from the blocks.
If you do not specify either the -distributed_hosts or -initialization option, the tool
performs both the distribution host and initialization checks.
DESCRIPTION
The check_interface_optimization_setup command checks whether the setup for
interface optimization is correct. It is recommended to run this command after using the
check_interface_optimization_setup
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set_hosts_options and set_top_implementation_options commands and before
running the route_opt command with interface optimization. This helps you find any issues
with the set up for interface optimization without actually running the route_opt command.
If the command reports any error or warning messages, review these messages and resolve
them before proceeding.
Multicorner-Multimode Support
This command uses information from active scenarios only.
EXAMPLES
The following example checks the interface optimization related setup:
prompt> set_host_options -pool lsf -name LSF_hosts
prompt> set_top_implementation_options -optimize_block_interface true \
-block_references {ALU} \
-host_options LSF_hosts
prompt> check_interface_optimization_setup
# Resolve errors/warnings reported by above commands and run route_opt
with interface optimization.
prompt> route_opt
SEE ALSO
set_host_options(2)
set_top_implementation_options(2)
check_block_abstraction(2)
check_physical_design(2)
route_opt(2)
Chapter 1:
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check_isolation_cells
Reports the existing isolation cells in the current design. It also reports if any isolation cell is
redundant or might be required.
SYNTAX
status check_isolation_cells
[-input]
[-output]
[-inside]
[-outside]
[objects]
Data Types
objects
list
ARGUMENTS
-input
Checks the isolation cells only on the input nets of the top-level logical hierarchies or
voltage areas.
-output
Checks the isolation cells only on the output nets of the top-level logical hierarchies or
voltage areas.
-inside
Checks the isolation cells that are inside the top-level logical hierarchies or voltage
areas.
-outside
Checks the isolation cells that are outside the top-level logical hierarchies or voltage
areas.
objects
Specifies a list of voltage areas (in physical context) or top-level logical hierarchies (in
logical context) that are for which the query is run.
check_isolation_cells
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DESCRIPTION
The check_isolation_cells command reports the isolation cells that are associated with the
top-level logical hierarchies or voltage areas in the design. The top-level logical hierarchies
can be given as inputs only from dc_shell and voltage areas can be given as inputs only
from psyn_shell.
This command also reports if there are possible redundant isolation cells in the design.
When in dc_shell, this command reports about the possible requirement of an isolation cell
on a net if that nets crosses two logical hierarchies without any isolation cell. In psyn_shell,
if a net is sourced in a voltage area and sinked into another, the command reports that there
might be a requirement of an isolation cell on that net.
If no logical hierarchies are given in this command in dc_shell, the command looks all of the
top-level logical hierarchies and reports on the isolation cells based upon the given
switches.
In psyn_shell, if no voltage areas are specified, the command looks at all existing voltage
areas, except the default voltage area, and reports about the isolation cells according to the
given switches. The command does not accept default voltage area as an input from
psyn_shell.
This command works both for multisupply and multivoltage designs. In the case of a
multivoltage design, this command treats enabled level-shifter cells also as isolation cells.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following is an example report from the check_isolation_cells command:
prompt> check_isolation_cells
*********************************************
Information : Output vdd_region_2/state_out[31]
state_out_iso31 outside vdd_region_2
Information : Output vdd_region_2/state_out[30]
state_out_iso30 outside vdd_region_2
Information : Output vdd_region_2/state_out[29]
state_out_iso29 outside vdd_region_2
Information : Output vdd_region_2/state_out[28]
state_out_iso28 outside vdd_region_2
Information : Output vdd_region_2/state_out[27]
state_out_iso27 outside vdd_region_2
Information : Output vdd_region_2/state_out[26]
state_out_iso26 outside vdd_region_2
Chapter 1:
check_isolation_cells
has an isolation cell
has an isolation cell
has an isolation cell
has an isolation cell
has an isolation cell
has an isolation cell
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Information : Output vdd_region_2/state_out[25] has an isolation cell
state_out_iso25 outside vdd_region_2
Information : Output vdd_region_2/state_out[24] has an isolation cell
state_out_iso24 outside vdd_region_2
Information : Output vdd_region_2/state_out[23] has an isolation cell
state_out_iso23 outside vdd_region_2
Total number of isolation cell(s) : 9
*********************************************
1
SEE ALSO
check_level_shifters(2)
check_library(2)
check_isolation_cells
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check_legality
Checks the legality of the current placement.
SYNTAX
int check_legality
[-verbose]
ARGUMENTS
-verbose
Prints a detailed report of all possible violations. By default, the command reports only a
summary of all violations.
DESCRIPTION
The check_legality command checks the legality of the current placement and prints out a
report of violation statistics. The violations can be classified as:
1. Cells that are not on rows
2. Cells overlapping each other
3. Cells overlapping with blockages in the design
4. Cells with orientation that is not allowed for the row on which a cell
is placed
5. Cells with a core site type not equal to that of the row on which
cells are placed
6. Cells overlapping with power straps in the design
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the command for printing out a summary of all violations.
prompt> check_legality
Chapter 1:
check_legality
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SEE ALSO
create_placement(2)
legalize_placement(2)
check_legality
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check_level_shifters
Checks the design for all existing level shifters and nets against the specified level-shifter
strategy and threshold.
SYNTAX
status check_level_shifters
[-verbose]
ARGUMENTS
-verbose
Prints a detailed report of all possible violations. By default, only a summary of all
violations is printed.
DESCRIPTION
This command checks the design for all existing level shifters and nets against the specified
level-shifter strategy and threshold. It prints out complete statistics of the design regarding
existing and required voltage adjustments containing the following information:
•
Level shifter strategy and threshold
•
Nets that need level shifters
•
Nets that need level shifters but are dont_touched
•
Nets that have multiple driver pins at different operating voltages
•
Total number of level shifters in the design
•
Total number of violating level shifters in the design
•
Total number of violating nets in the design.
Multicorner-Multimode Support
This command uses information from the current scenario only.
Chapter 1:
check_level_shifters
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EXAMPLES
The following example prints out a summary of all violations:
prompt> check_level_shifters
****************************************************
Check Level Shifters and Nets Summary
****************************************************
Level shifter strategy
:low_to_high
Level shifter threshold voltage
:0
Level shifter threshold percent
:0
Number of violating nets (dont_touch)
:2
Number of violating nets (multiple driver)
:0
Number of violating nets (total)
:2
Number of violating level shifters
:32
****************************************************
The following example shows the command using the -verbose option:
prompt> check_level_shifters -v
---------------------------------------------------------------------Net
Driver Pin
Input Volt Load Pin
Output Volt
---------------------------------------------------------------------n1
U1/out1
0.9
LS1/A
1.08
=========================================================================
==
Level Shifter
Reference
Input Output Violation Reason
Opcond
Volt
Volt
=========================================================================
==
LS1
LVL2
0.9
0.7
TRUE
Lib Cell
max_v9
=========================================================================
==
SEE ALSO
check_library(2)
insert_level_shifters(2)
remove_level_shifters(2)
set_level_shifter_strategy(2)
set_level_shifter_threshold(2)
check_level_shifters
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check_library
Performs consistency checks between logic and physical libraries, across logic libraries,
and within physical libraries.
SYNTAX
status check_library
[-mw_library_name phys_library_name_list]
[-logic_library_name logic_library_name_list]
[-cells cell_list]
Data Types
phys_library_name_list
logic_library_name_list
cell_list
list
list
list
ARGUMENTS
-mw_library_name phys_library_name_list
Specifies the Milkyway reference libraries to be checked.
If you do not specify this option, the command uses the reference libraries from the open
Milkyway design library. If there is no open Milkyway design library, the command uses
the reference libraries specified in the mw_reference_library variable.
-logic_library_name logic_library_name_list
Specifies the logic libraries (.db) to be checked. Other types of libraries such as .ILM are
not supported.
For logic versus logic library checking, specify two or more libraries, such as the
minimum and maximum libraries. If you have set the -compare or -validate options of
the set_check_library_options command, specify only two libraries.
If you do not specify this option, the command determines the logic libraries in the
following order:
•
Chapter 1:
check_library
The minimum and maximum libraries that were set with the set_min_library
command.
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•
If you have set the -scaling option of the set_check_library_options command, the
scaling libraries that were set with the define_scaling_lib_group command.
•
The link libraries that were set with the link_library and search_path variables.
For logic versus logic library checking, the command first groups the link libraries by
cell set, and within each group or family the command checks consistencies across
all libraries in the same group. The grouping is by majority (> 50%) of same name
cells. For example, if lib1 has 9 cells and lib2 has 6, and 5 of them are the same, then
they are grouped together.
This option is ignored for physical library checking.
-cells cell_list
Specifies a list of cell names to be checked. If not specified, all cells in the libraries are
checked.
DESCRIPTION
The check_library command checks and reports the items described below, based on the
settings of the set_check_library_options command.
If you do not run the set_check_library_options command and do not specify any options
with the check_library command, the check_library command checks logic versus
physical library consistency for the libraries that are set up for the current design. If there are
no libraries set up for the current design, the command does not perform any checks.
During logic library checking, to report the delay, power, and noise characterization values
in the libraries, the Liberty-format description of the libraries must have the library_features
attribute set to the respective values: report_delay_calculation,
report_power_calculation, and report_noise_calculation.
Use the check_library command to verify the libraries before reading in a design.
This command checks library qualities in three main areas:
•
Physical library quality
•
Logic versus physical library consistency
•
Logic versus logic library consistency
Physical Library Quality Checking
Physical library qualities are checked as follows:
•
Technology data consistency between the specified main library and each linked
reference library
check_library
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•
CEL view versus FRAM view in the library for missing views and mismatched views
•
Cells with identical names in different reference libraries and the specified main library
•
Signal electromigration rules
•
Antenna rules and missing antenna properties
•
Rectilinear cells
•
Physical-only cells
•
Physical properties for place and route including unit tiles for the libraries
•
Pin routability
•
Technology data quality
•
DRC for each cell in the library
Logic Versus Physical Library Consistency Checking
The command performs the following consistency checks between logic and physical
libraries:
•
Missing cells in the logic or physical library
If you specify multiple logic libraries and no cells are found in any of the libraries that
match the physical library, the cells are counted as missing in the logic library unless they
are physical-only cells. Otherwise, if the cells are found in any of the logic libraries, such
as the first library, they are counted as consistent in cell names.
•
•
Missing or mismatched pins (pin names, directions, and types) in the logic and physical
library.
Note that the input pin direction keyword in a logic cell versus the Input keyword in a
physical cell is not a mismatch.
•
Area values of each standard cell between the logic (.lib or .db) model and FRAM view
(PRBoundary and CellBoundary)
•
Cell footprint (cell_footprint attribute)
•
Bus character naming style in logic and physical libraries.
By default, missing cells and pins and mismatched pins are checked.
For logic versus physical library checking, at the end of checking the command reports a
cross-check summary that includes the following information:
•
Number of cells missing in the logic library (excluding physical-only cells)
Chapter 1:
check_library
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•
Number of cells missing in the physical library
•
Number of cells with missing or mismatched pins in libraries, if any
•
The logic versus physical library quality checking PASSED or the logic library is
INCONSISTENT with the physical library
Logic Versus Logic Library Consistency Checking
Logic versus logic library consistency checks include:
•
General checking at library, cell, pin, and timing group levels for missing cells, missing
and mismatched pins or pg_pins, and timing arcs.
•
Special checking for timing, noise, and power scaling
•
Special checking for the UPF or multivoltage flow, such as pg_pins, power management
cells, and power data
•
Special checking for the multicorner-multimode flow, such as operating conditions and
power-down functions
•
Library characterization and validation
For logic versus logic library checking, at the end of checking the command reports a
summary for each specified option. For example, for the -mcmm option, it reports:
Logic library consistency check FAILED for MCMM.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
In the following example, the lib1.db and lib2.db logic libraries are checked against the
phys_lib physical libraries for missing cells and pins, mismatched pins, the cell footprint, and
the bus delimiter:
prompt> set_check_library_options -cell_footprint -bus_delimiter
1
prompt> check_library -mw_library_name {phys_lib} \
-logic_library_name {lib1.db lib2.db}
#BEGIN_XCHECK_LIBRARY
Logic Library:
check_library
lib1
lib2
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Physical Library: phys_lib
check_library options: -cell_footprint -bus_delimiter
Version:
E-2010.12
Check date and time:
Tue Sep 28 20:34:26 2010
List of logic library and file names
-------------------------------------------------------------------Logic library name
Logic library file name
-------------------------------------------------------------------lib1
/usr/lib/lib1.db
lib2
/usr/lib/lib2.db
-------------------------------------------------------------------#BEGIN_XCHECK_LOGICCELLS
Number of cells missing in logic library:
3 (out of 3348)
Information: List of cells missing in logic library (LIBCHK-210)
-------------------------------------------------------------------Cell name
Cell type
Physical library
-------------------------------------------------------------------AND2
Core
phys_lib
NOR1
Core
phys_lib
XOR3
Core
phys_lib
-------------------------------------------------------------------List of physical only cells
-------------------------------------------------------------------Cell name
Cell type
Physical library
-------------------------------------------------------------------GFILL
Filler
phys_lib
GFILL10
Filler
phys_lib
FILL8
Filler
phys_lib
-------------------------------------------------------------------#END_XCHECK_LOGICCELLS
#BEGIN_XCHECK_PHYSICALCELLS
Number of cells missing in physical library:
0 (out of 846)
#END_XCHECK_PHYSICALCELLS
#BEGIN_XCHECK_PINS
Number of cells with missing or mismatched pins in libraries:
1
Error: List of pins mismatched in logic and physical libraries
(LIBCHK-213)
Logic library:
lib1
Physical library: phys_lib
------------------------------------------------------------------Pin direction
Pin type
Cell name
Pin name
Logic
Physical
Logic
Physical
------------------------------------------------------------------pnl123
VSSO
output Output
signal ground
SGND
input
Input
signal ground
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------------------------------------------------------------------#END_XCHECK_PINS
#BEGIN_XCHECK_BUS
Information: List of bus naming styles (LIBCHK-214)
----------------------------------------------------------------Library name
Library type
Bus naming style
----------------------------------------------------------------phys_lib
Physical library
_<%d>
lib1
Logic library
----------------------------------------------------------------#END_XCHECK_BUS
#BEGIN_XCHECK_FOOTPRINT
Number of footprints:
1
Warning: List of cells with cell_footprint attribute (LIBCHK-215)
------------------------------------------------------------------Footprint Logic library name
Cell name
PR boundary
------------------------------------------------------------------TIEH
lib1
GTIEH
(0,0)(0.8,1.8)
lib1
TIEH
(0,0)(0.6,1.8)
------------------------------------------------------------------#END_XCHECK_FOOTPRINT
Logic vs. physical library check summary:
Number of cells missing in logic library:
3
Number of cells with missing or mismatched pins in libraries:
1
Information: Logic library is INCONSISTENT with physical library.
(LIBCHK-220)
#END_XCHECK_LIBRARY
0
SEE ALSO
open_mw_lib(2)
report_check_library_options(2)
set_check_library_options(2)
link_library(3)
mw_reference_library(3)
check_library
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check_license
Checks the availability of a license for a feature.
SYNTAX
status check_license
feature_list
Data Types
feature_list
list
ARGUMENTS
feature_list
Specifies the list of features to be checked. If more than one feature is specified, they
must be enclosed in curly braces ({}). By looking at your key file, you can determine all
of the features licensed at your site.
DESCRIPTION
The check_license command checks on a license for the named features. It does not check
out the license.
The list_licenses command provides a list of the features that you are currently using.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
This example checks on the license for the multivoltage feature:
prompt> check_license {Galaxy-MV}
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SEE ALSO
get_license(2)
license_users(2)
list_licenses(2)
remove_license(2)
check_license
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check_mpc
Checks the result of the minimum physical constraints options on the design after running
the design through the minimum physical constraints flow.
SYNTAX
int check_mpc
[-macros]
[-ports]
[-conflicting]
[-verbose]
[object_list]
Data Types
object_list
collection or list
ARGUMENTS
-macros
Checks the constraints for macro objects only. Set the constraints with the
set_mpc_macro_options command and the set_mpc_macro_array command.
-ports
Checks the constraints for port objects only. Set the constraints with the
set_mpc_port_options command.
-conflicting
Reports only the conflicting constraints, such as constraints that are failing.
-verbose
Includes the values used to check the minimum physical constraints against the final
placement in the report. This option produces a more detailed than without the switch.
object_list
Specifies a list of designs, macros, ports, or group_names that are specified in the
design.
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DESCRIPTION
The check_mpc command verifies the design level physical constraints against the actual
floorplan created after the minimum physical constraints flow, which consists of the
create_placement -mpc, compile_physical -mpc, and the physopt -mpc flows. Use
check_mpc to verify and debug the constraints, and to determine if any constraints were or
were not met and the reason why.
The constraints and the actual floorplan are read in from the .db file.
Multicorner-Multimode Support
This command is not supported in a multi-scenario design flow.
EXAMPLES
After reading in a .db file that contains the constraints and placement information, you can
check the constraints on the current_design, as shown in the following example:
prompt> check_mpc [current_design]
Current design is 'MRISC'.
set_mpc_options
-aspect_ratio
1.500
-left_port_limit
10
-right_port_limit
10
-top_port_limit
10
-bottom_port_limit
100
-min_port_pitch
1
1
1.510
10
10
10
67
560
Not Met
Met
Met
Met
Met
Met
The following example checks the constraints on port objects only:
prompt> check_mpc -port
set_mpc_port_options
-side
set_mpc_port_options
-side
set_mpc_port_options
-side
1
Instrn[8]
top
Instrn[7]
top
Instrn[6]
top
top
Met
top
Met
top
Met
The following example checks constraints on macro objects only:
prompt> check_mpc -macro
set_mpc_macro_options
I_MBOX_QTM_core1
-legal_orientations N S FN FS
-anchor_bound
r
276.360) Met
check_mpc
N
Met
(215.520 176.360 315.520
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-x_offset
-align_pins
set_mpc_macro_options
-legal_orientations
-anchor_bound
476.360) Met
-y_offset
1
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2.000
{PSW[10] Y[0]}
I_MBOX_QTM_core2
N S FN FS
t
2.000
3.000
3.000
Met
Met
N
Met
(3.170 376.360 103.170
Met
The following example includes the values used to check the minimum physical constraints
of the I_MBOX_QRT_core1 object against the final placement in the report:
prompt> check_mpc -verbose I_MBOX_QTM_core1
set_mpc_macro_options
I_MBOX_QTM_core1
-legal_orientations N S FN FS
N
Met
-anchor_bound
r
(215.520 176.360 315.520
276.360) Met
The Bound for this region 'r' is [215.520 0.000 315.520 479.360]
-x_offset
2.000
2.000
Met
-align_pins
{PSW[10] Y[0]}
Met
The location of the pin Y[0] on macro I_MBOX_QTM_core1 is {315.020
196.860}
The location of the port PSW[10] is {317.380 196.840}
1
The following examples show how run check_mpc on specific object lists:
prompt> check_mpc [all_macro_cells]
prompt> check_mpc [get_ports ALL_OUTS*]
prompt> check_mpc -verbose
prompt> check_mpc [list [current_design] [get_ports In*]] \
[all_macro_cells]
SEE ALSO
create_placement(2)
report_mpc_macro_options(2)
report_mpc_options(2)
report_mpc_port_options(2)
set_mpc_macro_array(2)
set_mpc_macro_options(2)
set_mpc_port_options(2)
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Commands
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Version L-2016.03
check_mv_design
Checks for violations in a multivoltage design.
SYNTAX
status check_mv_design
[-verbose]
[-isolation]
[-target_library_subset]
[-opcond_mismatches]
[-connection_rules]
[-level_shifters]
[-power_nets]
[-clock_gating_style]
[-diode_cells]
[-max_messages message_count]
[-output output_file_name]
Data Types
message_count
output_file_name
unsigned integer
string
ARGUMENTS
-verbose
Reports the violations in detail. When this option is not used, only a summary of the
violations is reported in the log file.
-isolation
Reports electrical isolation issues:
•
Nets that require isolation, but the isolation cell is missing
•
Nets that do not require isolation, but an isolation cell is present
•
Isolation cells that do not cross a power domain boundary
-target_library_subset
Checks for inconsistent settings between the target library, target library subset, and
operating conditions. This option reports the following conditions:
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•
Conflicts between the target library subset and the global target_library variable
setting. The target library subset must be a subset of the library set specified by the
target_library variable.
•
Conflicts between the operating condition and target library subset. There must be at
the least one library from the target library subset that has the same process, voltage,
and temperature as the operating condition being used on a block.
•
Conflicts between a cell and the target library subset specification on the parent
design of the cell. This check ensures that the cells from the specified target library
subset are used.
-opcond_mismatches
Reports the technology cells instantiated in the design with incompatible operating
conditions. The option checks for conflicts between a cell and the operating condition
specified on the parent design of the cell. This check ensures that the operating
condition at which the cell is characterized matches the operating condition specified on
the design.
-connection_rules
Reports violations in the always-on synthesis and pass-gate connections:
•
Always-on net driven by a normal cell
•
Always-on net or a net from an always-on domain driving a pass gate
•
Always-on cell driving a normal net
•
Two pass gates connected to each other
-level_shifters
Reports level shifter violations:
•
Net requiring level-shifting with no level-shifter cell
•
Net on which a level-shifter cell cannot be added because either the net is marked as
dont_touch or the net is driven by a pin operating at a different voltage
•
Level-shifter cell shifting an incorrect voltage difference
•
Input pin of a level-shifter cell driven by a pin operating at a different voltage
•
Output pin of a level-shifter cell driving pins operating at a different voltage
•
Level-shifter cell that violates level-shifter strategy settings
-power_nets
Reports power and ground pin connections, including the following information:
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•
PG pin mismatch between the logical library and FRAM library
•
Power and ground connection summary
•
Power and ground pins whose connections cannot be derived and the reason that
the derivation fails
•
Power and ground pins whose existing connections do not match with the derived
connection from the power domains.
A mismatch between an existing PG connection and the connection derived from the
power domains can occur for any of the following reasons:
•
"Unknown power pin type" indicates either the power pin does not have a type or the
pin has a type without connection semantics. Automatic power connection supports
the following power pin types: primary_power_pin, primary_ground_pin,
backup_power_pin, backup_ground_pin, internal_power_pin, and
internal_ground_pin.
•
"Invalid pin type for the cell or the cell's power domain" indicates that the cell's power
domain does not have a power net connection with the matching type for the power
pin type. For example, this situation occurs when a regular cell has a backup ground
pin, but the cell's power domain does not have a backup ground net connection.
•
"No signal pin that uses this PG pin as the related_power_pin/related_ground_pin."
This issue occurs only on level-shifter and isolation cells. The power connection of a
power pin on a level-shifter or isolation cell is obtained through tracing cells
connected to related signal pins of the power pin. The power connection fails if a
power pin has no related signal pin, for example, when no signal pin uses the power
pin as the related_power_pin or related_ground_pin in the logical library cell
definition.
•
"Cells connected to the related signal pins of the level shifter or isolation cell requiring
different PG nets." This issue occurs only on level-shifter and isolation cells. The tool
cannot derive a proper power net for a specific pin because different nets are needed
for the same pin, based on cells connected to the related signal pins.
•
"Back-to-back connection of level-shifter and isolation cell" occurs when a
level-shifter or isolation cell is directly connected to another level-shifter or isolation
cell. The automatic connection of a power pin on such level-shifter or isolation cells
might fail if the tracing of related signal connections reaches only other level-shifter
or isolation cells.
This option also reports bias pin connections, when a supply net and its connected
supply nets through supply ports or power switches are used as the power/nwell/
deepnwell net, and also as the ground/pwell/deeppwell net.
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-clock_gating_style
Reports hierarchical blocks for which there is no library cell that meets its operating
condition and specified clock-gating style. Clock-gate insertion cannot be performed.
-diode_cells
Checks for and reports multivoltage violations related to diodes cells.
-max_messages message_count
Sets a maximum limit on the number of messages written into the log file and output file.
-output output_file_name
Writes the output of the check_mv_design command to a file specified by the file name
argument. If a file of the specified name already exists, it is over-written.
This file can be opened in the MV Advisor browser in the Design Vision GUI.
Alternatively, the same file can be opened in an HTML browser by using the absolute
path of the file.
The output file contains the details of all violations reported, even when the -verbose
option is not used.
DESCRIPTION
The check_mv_design command checks the design, multivoltage constraints, electrical
isolation requirements, and connection rules. It issues error and warning messages as
appropriate.
The checker options can be combined to adjust the level of detail in the final report. If the
command is used without any checker options, it reports only a summary of all violations
found.
If the -verbose option is used, the command reports details of all violations in the log file.
The -max_messages option limits the number of violations reported. When other checker
options are specified, the message count specified by the -max_messages option applies
to each type of check performed. If no specific checker is specified, the message count
applies to the total number of messages generated by all types of checks performed. If
-max_messages is not specified, the command writes out all messages without limit.
Multicorner-Multimode Support
This command uses information from the current scenario only.
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EXAMPLES
The following command reports all multivoltage violations in the design:
prompt> check_mv_design -verbose
-----------------------------------------------------------------------Target Library Subset Checks
-----------------------------------------------------------------------No Errors/Warnings Found.
-----------------------------------------------------------------------Power Domain Checks
-----------------------------------------------------------------------Warning: Isolation cell is required on net A_INST/OUTPUT connecting
A_INST and B_INST. (MV-042)
Warning: Isolation cell is required on net B_INST/OUTPUT connecting
B_INST and top. (MV-042)
Warning: Isolation cell A_INST/iso1 is used to isolate a net that is
not crossing power domain boundary. (MV-044)
-----------------------------------------------------------------------Power Domain Checks Summary
-----------------------------------------------------------------------Warning: Found 2 net(s) without isolation. (MV-046)
Warning: Found 1 isolation cell(s) on net(s) not crossing power
domain boundaries. (MV-048)
-----------------------------------------------------------------------Cell Operating Condition Checks
-----------------------------------------------------------------------No Errors/Warnings Found.
-----------------------------------------------------------------------Power Domain and Operating Condition Consistency Checks
-----------------------------------------------------------------------No Errors/Warnings Found.
The following command generates a summary of all violations in the design:
prompt> check_mv_design
-----------------------------------------------------------------------Target Library Subset Checks
------------------------------------------------------------------------
check_mv_design
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No Errors/Warnings Found.
-----------------------------------------------------------------------Power Domain Checks
-----------------------------------------------------------------------Warning: Found 2 net(s) without isolation. (MV-046)
Warning: Found 1 isolation cell(s) on net(s) not crossing power domain
boundaries. (MV-048)
-----------------------------------------------------------------------Cell Operating Condition Checks
-----------------------------------------------------------------------No Errors/Warnings Found.
-----------------------------------------------------------------------Power Domain and Operating Condition Consistency Checks
-----------------------------------------------------------------------No Errors/Warnings Found.
The following example reports violations related to electrical isolation:
prompt> check_mv_design -verbose -isolation
-----------------------------------------------------------------------Power Domain Checks
-----------------------------------------------------------------------Warning: Isolation cell is required on net A_INST/OUTPUT connecting
A_INST and B_INST. (MV-042)
Warning: Isolation cell is required on net B_INST/OUTPUT connecting
B_INST and top. (MV-042)
Warning: Isolation cell A_INST/iso1 is used to isolate a net that is not
crossing power domain boundary. (MV-044)
-----------------------------------------------------------------------Power Domain Checks Summary
-----------------------------------------------------------------------Warning: Found 2 net(s) without isolation. (MV-046)
Warning: Found 1 isolation cell(s) on net(s) not crossing power domain
boundaries. (MV-048)
The following example reports violations related to power nets:
prompt> check_mv_design -verbose -power_nets
-------------------------------------------------------------------------------
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Power/Ground Pin Connection Checks
------------------------------------------------------------------------------Error: Supply net sn1 and its connected supply net(s) are used as both
power/nwell/deepnwell net and ground/pwell/deepnwell net. (MV-601)
Error: Supply net sn2 and its connected supply net(s) are used as both
power/nwell/deepnwell net and ground/pwell/deepnwell net. (MV-601)
Error: Power net hookup for power domains is not specified properly.
(MV-503)
-------------------------------------------------------------------------------
The following example shows how to use the -output option of the check_mv_design
command.
prompt> check_mv_design -verbose -output my_file.cmvd
SEE ALSO
check_library(2)
insert_level_shifters(2)
remove_target_library_subset(2)
set_operating_conditions(2)
set_target_library_subset(2)
check_mv_design
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check_noise
Checks whether there are necessary data available to run noise analysis in the current
design.
SYNTAX
status check_noise
[-verbose]
[-nosplit]
[-include check_list]
Data Types
check_list
list
ARGUMENTS
-verbose
Enables verbose mode showing detailed information and pin names.
-nosplit
Most of the design information is listed in fixed-width columns. If the information in a
given field exceeds the column width, the next field begins on a new line, starting in the
correct column. The -nosplit option prevents line-splitting and facilitates writing software
to extract information from the report output.
-include check_list
Specifies the types of checking. Available values are noise_driver and noise_immunity.
The default is noise_immunity.
DESCRIPTION
It is possible to have invalid noise models in a library and run noise analysis without
detecting them. This may result in inaccurate results. If the design is large, and it takes long
time to finish the noise analysis, it will also cause longer turn around time. Moreover, it is
very important that all pins in the design have correct noise immunity information.
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Otherwise, when the noise analysis is over, violations wouldn't be reported even if noise
bumps are large enough to create violations.
The check_noise command can be executed before the noise analysis to validate the
correctness of a design with respect to noise analysis. It checks for the presence of any
invalid noise model, and any pin without a model from the library and from the design. It
verifies that all pins in the design are 'noise constrained', i.e., their noise immunity can be
calculated.
In a verbose mode, the command shows the names of cells and pins that have no model or
an invalid model.
EXAMPLES
The following example shows a noise immunity check:
prompt> check_noise
Information: Checking noise immunity on load pins...
Noise immunity type above_low below_high -------------------------------------------------------library immunity table 0 0 library immunity curve 0 0 library CCS noise immunity 3245 3245
global threshold 0 0
The following example shows a noise driver check:
prompt> check_noise -include {noise_driver}
Information: Checking noise models on driver pins...
Noise driver type above_low below_high -------------------------------------------------------- library
set iv curve 0 0 library set CCS noise 520 520 estimation set value 0 0
SEE ALSO
report_noise(2)
check_noise
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check_physical_constraints
Checks the physical constraints and provides feedback about possible errors in input.
SYNTAX
int check_physical_constraints
[-narrow_placement_area no_of_sites]
[-rc_check rc_variation_margin]
[-verbose]
[-analyze_legality [-nworst no_of_worst_cells]
[-design]
[-lib_cell lib_cell_name]]
Data Types
no_of_sites
rc_variation_margin
no_of_worst_cells
lib_cell_name
integer
float
integer
string
ARGUMENTS
-narrow_placement_area no_of_sites
Issues warnings about narrow placement areas in the floorplan. It is defined in terms of
base site widths. The default is the maximum width of the cells in the library. Using a
value of 0 for this switch causes the narrow placement area check to be skipped. The
narrow placement area threshold width is same for both the vertical and the horizontal
direction.
-rc_check rc_variation_margin
Issues warnings if the resistance or capacitance varies by more than the
rc_variation_margin across different metal layers. This option detects invalid layers,
such as POLY. However, such a variation is possible because of differing metal widths in
different layers. Also checks for width, pitch, and spacing for all route metal layers.
Default is 5.0. Note that rc_variation_margin value is a multiplier and not an absolute
value.
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-verbose
Prints more information. When used with the -analyze_legality switch, it prints the legal
site rates for each library cell and the reason for non-legal sites.
-analyze_legality
Analyzes each cell of a physical library against a floorplan (with power structures) and
reports the success rate for legalization on all sites. The legal rate printed prints the legal
sites for the library cell after evaluating them against the power straps. It shows the total
number of available sites for the library cell so you can determine whether or not you
want to use that cell. Default is off.
-nworst no_of_worst_cells
Prints no_of_worst_cells for all cells in the physical library in terms of legal site rates.
This is the default mode of the -analyze_legality switch. If it is used with -verbose or
-lib_cell, it is ignored. This option is only used with -analyze_legality. Default is 10.
-design
Performs -analyze_legality on the library cells that are in design only. Default is false.
-lib_cell lib_cell_name
Specifies a particular library cell for -analyze_legality.
DESCRIPTION
The check_physical_constraints command checks several physical constraints and
provide information about possible errors in input. It checks for cell areas in hard bound,
correct layers in the library against those in the floorplan, resistance and capacitance for
different route layers, narrow placement areas in the floorplan, legal sites for library cells in
floorplan, etc. Check all of the warnings and error messages to avoid erroneous input to the
tool. Use this command early in the flow to detect errors in input.
Refer to the -check_only option to the physopt for further information.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example checks the physical constraints. The rc_variation_margin is 2.1.
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prompt> check_physical_constraints -verbose -rc_check 2.1
SEE ALSO
PSYN-469(n)
report_placement_utilization(2)
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check_physical_design
This command checks the readiness of the current design for IC Compiler.
SYNTAX
status check_physical_design
-stage stage_value
| -input_log log_file
| -design_statistics [-include_clock_tree_report]
[-check_timing]
[-analyze_legality]
[-continue_on_missing_scandef]
[-placement_constraints_min_distance distance]
[-placement_constraints_solution_file filename]
[-output directory]
[-display]
Data Types
stage_value
log_file
distance
filename
directory
string
string
float
string
string
ARGUMENTS
-stage stage_value
Specifies which stage to check. The checks performed by the check_physical_design
command depend on the specified stage. Make sure the design contents make sense
for the specified stage; otherwise, the report might be meaningless.
You can specify one of the following values:
•
pre_place_opt
This stage requires that the floorplan and netlist data are ready and the design
constraints are set.
•
post_initial_placement
This stage meant to run placement constraints checks and requires that the design
is placed, but not buffered, and the placement design constraints are set.
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•
pre_clock_opt
This stage requires the same items as pre_place_opt. In addition, the design must be
placed and the clock constraints must be set.
•
pre_route_opt
This stage should be called when the design is ready for routing.
You must specify one of the following options: -stage, -input_log, or
-design_statistics.
-input_log log_file
Specifies the log file to analyze. When you specify this option, the command analyzes
the specified log file; it does not perform any checks.
You must specify one of the following options: -stage, -input_log, or
-design_statistics.
-design_statistics
Performs statistical analysis on various aspects of the design, such as cells, nets, and
area and generates ASCII and HTML report files.
The report files are written to a directory named
cpd_design_statistics_<year><month><day><hour><minutes><seconds>, which is
created in the current working directory. You can view the individual report files, or view
the HTML report by opening the index.html file in a browser.
This analysis can be done at any stage in the design cycle. When you specify this option,
the command does only analysis and does not perform any checks.
If you specify the -include_clock_tree_report option with the -design_statistics
option, the design statistics include a clock-tree report.
If you specify the -stage option with the -design_statistics option, the tool issues an
error message.
You must specify one of the following options: -stage, -input_log, or
-design_statistics.
-include_clock_tree_report
Includes a clock-tree report with the design statistics.
You can use this option only with the -design_statistics option.
-check_timing
Performs timing checks, including timing checks related to abstracted blocks.
If you do not specify this option, the check_physical_design command determines
whether to perform timing checks based on the value of the cpd_skip_timing_check
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variable, whose default is true. Skipping the timing checks reduces runtime, especially
for large, complex designs.
-analyze_legality
Performs more detailed cell analysis for all the library cells used in the current design.
By default, only brief analysis is done. This option is most useful when one or more
reference libraries are used by IC Compiler for the first time. This option has a runtime
penalty.
-continue_on_missing_scandef
Continues with placement checks when the design contains scan chains but no
SCANDEF data.
By default, missing SCANDEF data causes the command to exit with an error message.
If you specify this option, the command issues a warning but continues the placement
checks and considers the scan chains without the missing SCANDEF.
-placement_constraints_min_distance distance
This option valid only while using -stage post_initial_placement. When we run
placement constraints checking, this option allows user to control what is the minimal
distance of a constraint cell to be checked. If this option is not used, the check uses
default value of 200 micron.
-placement_constraints_solution_file filename
This option valid only while using -stage post_initial_placement. When we run
placement constraints checking, the check creates placement constraints solution
statements, which are Tcl commands that adjust the placement constraints that could
cause suboptimal placement. This option allows user decide if these statements will be
written out as solution script into a file, and to specify the output file name. If this option
is not used, the placement constraints checking prints out the solution statements on the
screen and no file are generated.
-output directory
Specifies the directory in which to save the report.
By default, the report is saved in a directory called cpd_<stage>_<time>_<pid>. The
generated HTML report is called index.html.
If the specified directory already exists, a unique directory named directory.n is created
and used.
-display
Displays the result in the Web browser defined by the gui_online_browser variable.
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DESCRIPTION
The check_physical_design command performs one of the following checks:
•
When you use the -stage option, the tool checks the readiness of the current design for
IC Compiler by performing specific checks and analysis based on the options you
specify.
•
When you use the check_physical_design -stage post_initial_placement, the tool
performs a check for problematic placement constraints. The constraints set on certain
cells in the design can force wrong locations for cells which can cause later for run time
and QOR issues. Please note, this check could take some runtime especially for large
design, but it's important to find any bad placement constraints to avoid wrong cell
placement and sub optimal QoR.
•
Problematic Cell placement constraints are:
•
When a Cell is member of bound, while none of its connected cells is member of the
bound, and they are located far away from the cell in the bound.
•
When a cell in one bound connected to a cell in another bound that is far away.
•
When a cell in one bound connected to a fixed cell that is far away.
•
When a Cell is member of bound and connected to a port which located far away from
the cell in the bound.
•
When a cell is fixed, and all of the cells connected to located far away from the fixed cell.
•
When a fixed cell connected to a fixed cell that is far away.
•
When the checker identifies cells with Problematic placement constraints, it reports them
out, and suggest corrective action, based on the specific constraints. These corrective
statements could use to solve the problems.
•
This new stage can come with default run. But we allow user to control 2 aspects of this
check with 2 options: -placement_constraints_min_distance This option allows user to
control what is the minimal distance of a constraint cell to be checked. If this option is not
used, the check uses default value of 200 microns.
•
-placement_constraints_solution_file This option allows user decide if these statements
will be written out as solution script into a file, and the output file name for this. The
solution script contains Tcl commands that adjust the placement constraints that could
cause suboptimal placement. If this option is not used, the placement constraints
checking prints out the solution statements on the screen and no file is generated.
•
These two options are relevant only with check_physical_design -stage
post_initial_placement, other ways tool issues error.
Expected usage flow:
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•
remove_buffer_tree all
•
create_placement [options] | create_fp_placement [options] | place_opt_feasibility stage
initial_placement [options]
•
check_physical_design -stage post_initial_placement
•
When you use the -input_log option, the tool checks the readiness of the current design
for IC Compiler by analyzing the specified log file.
•
When you use the -design_statistics option, the tool performs statistical analysis on
various aspects of the design, such as cells, nets, DRC violations, and area. If you also
specify the -include_clock_tree_report option, the tool includes a clock-tree report with
the design statistics.
If you specify the -design_statistics or -stage option, you must load the floorplan and open
the Milkyway design before running the command; otherwise, the checking will not work. In
addition, some of the checks require the CEL view to be writable.
If you specify the -stage or -input_log option, the command analyzes and reports all the
error messages and other customizable messages from the checking results or the input log
file and provides the final report in an easy-to-use HTML format. The HTML file contains
information about what to do next, hyperlinks to man pages, and the line number in the log
file for each message. The command supports Web browsers such as Internet Explorer and
Firefox. By default, this command tries to open the result in the Web browser.
Configuration File
You can customize the behavior of the check_physical_design command by using a
configuration file, which is called .icc_report_config. The tool looks for this file in your home
directory and the current working directory. Settings in the configuration file in the current
working directory override those in the configuration file in your home directory.
The configuration file can contain the following commands:
set maxMessageCount integer
This variable controls how many detailed messages are displayed for the same message ID
in the HTML file. The default is 10.
set linkToLogMode integer
This variable controls the algorithm used to link the log file in the HTML file. If set to 0, the
HTML file uses JavaScript to automatically generate the partial log file and highlights the
desired message line when you click on the hyperlink to the log file. If set to 1, multiple
partial log files are generated during command execution and the links point directly to the
saved files. A setting of 1 has a small runtime and disk space penalty, due to saving extra
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files on disk, but the speed of opening the links should be better than with a setting of 0. If
your browser does not support JavaScript inside the HTML, use a setting of 1. The default
is 0.
add_keyword keyword
This command allows you to specify keywords that you want the tool to be aware of. The tool
creates an HTML table with the results of "grepping" for this keyword. When you use this
setting, your operating system path must be set up so that it can directly find the grep
command.
config_message options
This command defines how the check_physical_design command treats messages during
analysis. Note that error messages are always considered important messages.
The supported options for the config_message command are:
•
-id message id
Specifies the message ID to be reconfigured.
•
-title message_id_title
Specifies the title of the message, which is displayed in the HTML table.
•
-ignore
Specifies that the check_physical_design command should treat this message ID as
an unimportant message.
•
-stage stage_name
Specifies the stage to which this configuration applies. If not specified, the configuration
applies to all stages. This option allows you to treat the same message differently at
different stages. For example, you can define the messages from checking ideal clock
nets as unimportant at the pre_clock_opt stage, but define them as important at the
pre_route_opt stage.
config_check options
This command adds user-defined checks to the check_physical_design command. The
checks are executed one-by-one after the embedded checks.
The supported options for the config_check command are
•
-cmd tcl_procedure_name
Specifies the Tcl procedure that contains the user-defined check.
•
-stage stage_name
Specifies the stage to which this configuration applies. If not specified, the configuration
applies to all stages. This option allows you to add the same check at different stages.
config_drive options
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This command defines the values that influence the size categories in the drive strength
reports in the design statistics report generated by the check_physical_design
-design_statistics command.
The supported options for the config_drive command are:
•
-id label_string
Specifies the label given to the size categories, which describe the specified drive
strength to which the new values belong. Supported values are XS, S, M, L, and XL. You
must specify one of these labels. The label XXL defaults to net length and fanout values
greater than the XL values.
•
-fanout pin_count
Specifies the maximum number of pins that can be driven by the library cell. You must
specify an integer value. The default value varies for each label and is defined below.
•
-net net_length
Specifies the total wire length associated with the pins that are driven by the library cell.
The unit is the length unit of the design library. The default value varies for each label and
is defined below.
To produce a meaningful drive strength report, the values for the -net and -fanout options
should increase for each label from XS to XL. If one or both values do not incrementally
increase in value from XS to XL, a warning is issued when creating the drive strength table.
If you do not specify values for a label, the tool uses the following default values:
config_drive
config_drive
config_drive
config_drive
config_drive
-id
-id
-id
-id
-id
XL -fanout 150 -net 700
L -fanout 100 -net 500
M -fanout 50 -net 300
S -fanout 10 -net 100
XS -fanout 5 -net 50
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example checks the design readiness for placement and saves the result in
the cpd_result directory. The log file lists the checks that were performed and the result
summary. An HTML file is also generated, which you can read by using the Web browser.
prompt> check_physical_design -stage pre_place_opt -output cpd_result
checking tluplus...
checking link...
checking logic objects...
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checking physical objects...
checking timing...
checking HFN/ideal/dont_touch nets...
checking placement constraints...
**************************************************
Report : check_physical_design
Design : RISC_CHIP
Version: B-2008.09-ICC-SP
Date
: Wed Oct 8 10:55:22 2008
**************************************************
Total messages: 0 errors, 270 warnings
----------------------------------------------Other Warning Summary for check_physical_design
-----------------------------------------------------------------------------------------------------------------------ID
Occurrences
Title
-------------------------------------------------------------------------FEAS-002
1
High Fanout Synthesis has not been
performed
LINT-1
3
cell does not drive any nets
LINT-2
129
Net driven by pin has no loads
LINT-3
4
Net has no drivers.
LINT-5
4
In design '%s', output port '%s' is not
driven.
LINT-8
88
Input port unloaded
LINT-32
5
In design '%s', a pin on submodule '%s'
is conn...
LINT-33
1
In design '%s', the same net is connected
to mo...
LINT-63
32
Net '%s' has a single tri-state driver.
PNR-156
2
macro cell has no keepout margin defined
PSYN-261
1
Capacitance of layer %s varies more than
the sp...
-------------------------------------------------------------------------dump check_physical_design result to file cpd_result/index.html
1
prompt> sh firefox cpd_result/index.html
The following example analyzes the results in the pre_place_log log file. It does not perform
any checks on the design.
prompt> check_physical_design -input_log pre_place_log
The following example checks the design readiness for placement, including timing checks,
which are disabled by default. This might cause longer runtime. The log file lists the checks
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that were performed and the result summary. An HTML file is also generated, which you can
read by using the Web browser.
prompt> check_physical_design -stage pre_place_opt \
-check_timing
The following example runs placement constraints checks when minimal distance to be
checked is 300u and if any violation found, the corrective actions will be written into file
solution.tcl.
prompt> fBcheck_physical_design -stage post_initial_placement \
-placement_constraints_min_distance 300.0\
-placement_constraints_solution_file ./solutions.tcl
The following example generates a design statistics report. It does not perform any checks
on the design.
prompt> check_physical_design -design_statistics
The following example generates a design statistics report with clock-tree reporting. It does
not perform any checks on the design.
prompt> check_physical_design -design_statistics \
-include_clock_tree_report
The following example shows a sample configuration file:
% cat ~/.icc_report_config
add_keyword drc
config_message -stage pre_clock_opt -id CTS-810 -ignore
config_check -stage pre_clock_opt -cmd "report_design -physical"
set maxMessageCount 5
config_drive -id S -fanout 5 -net 50
SEE ALSO
check_design(2)
check_physical_constraints(2)
check_error(2)
check_timing(2)
get_message_info(2)
print_message_info(2)
print_suppressed_messages(2)
suppress_message(2)
unsuppress_message(2)
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gui_online_browser(3)
cpd_skip_timing_check(3)
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check_primetime_icc_consistency_settings
SYNTAX
int check_primetime_icc_consistency_settings
[-html_output_path path_name]
Data Types
path_name
string
ARGUMENTS
-html_output_path path_name
Writes out the consistency report in HTML format in the specified directory path. Without
this option, the command writes the report to the console in plain text format.
DESCRIPTION
The check_primetime_icc_consistency_settings command checks IC Compiler and
PrimeTime settings for good timing correlation between the two tools. It reports an error for
each setting that is different from recommended and tells you the proper setting in the
applicable tool.
Before you can use this command, you must run the set_primetime_options command to
set up the PrimeTime executable location and setup script. You can query the PrimeTime
option settings by using the report_primetime_options command.
Multicorner-Multimode Support
This command applies to current scenario only.
EXAMPLES
The following example demonstrates usage of the
check_primetime_icc_consistency_settings command. Before running this command,
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the set_primetime_options command sets up the PrimeTime executable location and
PrimeTime setup script, pt.tcl.
prompt> set_primetime_options \
-exec_dir $install_dir/bin -common_file pt.tcl
prompt> check_primetime_icc_consistency_settings
Error: The timing_remove_clock_reconvergence_pessimism setting is
inconsistent between IC Compiler and PrimeTime. The IC Compiler value is
TRUE; the PrimeTime value is "false". (CORR-803)
Error: The timing_remove_clock_reconvergence_pessimism PrimeTime variable
should be set to TRUE. (CORR-800)
SEE ALSO
report_primetime_options(2)
set_primetime_options(2)
Chapter 1:
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check_rail
Checks the integrity of the power network in preparation for running the analyze_rail
command.
SYNTAX
status check_rail
[-report_file file_name]
Data Types
file_name
string
ARGUMENTS
-report_file file_name
Specifies the report file name. The set_rail_options -output_dir command sets the
output directory for the report file. The command report_rail_options reports the
current output directory setting. The default report file name is check_rail_report.txt.
DESCRIPTION
This command checks the integrity of the power network. Use the check_rail command
prior to running the analyze_rail command. The check_rail command checks all power and
ground nets in the Milkyway design. If there are floating power pins, supply nets which do
not have instance connection, or supply nets without supply voltage assigned, the command
outputs warning messages to the report file and a writes a brief summary to the log file.
By default, the check_rail command purges and rebuilds the RAIL view to ensure
consistency between the Milkyway design and the RAIL view. To use the existing RAIL view
generated by the analyze_rail command without purging, use the command
set_rail_options -reuse setup_variable. See the set_rail_options man page for more
information.
The check_rail command creates a new Milkyway session to avoid interfering with the
current session. If the power or ground network has changed, save the cell before invoking
the check_rail command to ensure the new Milkyway session uses the most recent data.
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EXAMPLES
The following example checks the integrity of the power network and saves the report to the
file report.txt:
prompt> check_rail -report_file report.txt
SEE ALSO
set_rail_options(2)
report_rail_options(2)
analyze_rail(2)
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check_reserved_placement_area
Checks the consistency of the reserved placement areas between the top and child levels.
SYNTAX
status check_reserved_placement_area
[-objects rows_or_placement_blockages]
[soft_macros]
Data Types
rows_or_placement_blockages
soft_macros
collection
collection
ARGUMENTS
-objects rows_or_placement_blockages
Specifies one or more reserved placement site rows or placement blockages for
checking. The check_reserved_placement_area command runs at the top level of the
design, but you can check the child-level reserved placement blockages by selecting the
appropriate reserved placement blockages inside the block, assigning the selection to a
variable, and executing the command at the top level on the selected objects defined by
the variable.
By default, the command checks the consistency of all the top-level reserved placement
site rows and child-level reserved placement blockages.
soft_macros
Specifies the soft macros to be checked for reserved placement areas. By default, the
tool processes all soft macros in the current design.
DESCRIPTION
This command checks the reserved placement area in both the top design and the child
design levels. The reserved placement areas are the site rows or placement blockages with
the "is_reserved_placement_area" attribute. For each top-level reserved placement site
row, the command checks whether there are child-level reserved placement blockages
whose bounding box fully covers the bounding box of the site row. The command reports
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inconsistencies if no such child-level reserved placement blockage exists. For each
child-level reserved placement blockage, the command checks whether there are reserved
placement site rows at the top level that are fully inside the bounding box of the child-level
reserved placement blockage. The command reports an inconsistency if there are no
reserved top-level site rows fully inside the bounding box.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example checks all reserved placement areas in the current design.
prompt> check_reserved_placement_area
SEE ALSO
derive_reserved_placement_area(2)
remove_reserved_placement_area(2)
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check_route
Checks and reports the violations of a routed design.
SYNTAX
status check_route
[-drc]
[-opens]
[-antenna]
[-top_layer_probe_constraints]
[-num_cpus num]
ARGUMENTS
-drc
Check DRC Violations.
-opens
Check Opens.
-antenna
Check Charge-Collecting Antenna violations.
-top_layer_probe_constraints
Check Top-Layer Probe Constraints.
-num_cpus num
Number of cpus for DRC checking. Number must be >= 1.
DESCRIPTION
This command checks and reports the following about a routed design: DRC Violations,
Opens, Charge-Collecting Antenna violations and Top-Layer Probe Constraints. Design rule
checking can also be done using the Distributed Routing option.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
prompt> check_route -drc
SEE ALSO
Chapter 1:
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check_routeability
Verifies that the current design is routable.
SYNTAX
int check_routeability
[-error_cell cell_name]
Data Types
cell_name
string
ARGUMENTS
-error_cell cell_name
Enter the error cell you want or use the default name provided. The default name is
<top_cell_name>.err. When there are errors in the design, an error cell is generated with
this given name. An error cell is not be generated unless errors exist.
DESCRIPTION
Checks pin access points, cell instance wire tracks, pin out of boundaries, min-grid and pin
design rules and blockages to ensure they meet the design requirements. It performs a
check of the design for optimization in order to substantiate any errors in the design that
might need to be fixed or what could help to improve the design. This must currently be run
on a placed design.
You can use this command at every stage between placement and detail routing. Verify
errors in the generated error cell or log file.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example dump out the design error to a specified file, dumpErr.err.
prompt> check_routeability -error_cell dumpErr.err
The following example dump out the design error to a default cell.
prompt> check_routeability
SEE ALSO
create_route_guide(2)
Chapter 1:
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check_rp_groups
Checks the relative placement constraints and reports any failures.
SYNTAX
collection check_rp_groups
{rp_groups | -all}
[-output filename]
[-critical]
[-verbose]
Data Types
rp_groups
filename
list or collection
string
ARGUMENTS
rp_groups
Specifies the relative placement groups that will be checked for failures. This option and
the -all option are mutually exclusive.
-all
Specifies that all relative placement groups will be checked. This option and the
rp_groups argument are mutually exclusive.
-output filename
Specifies the name of the output file for the report.
If you do not specify this option, the report is written to the standard output.
-critical
Specifies to report the specified relative placement groups that cannot be placed.
-verbose
Reports relative placement cell orientation failures that are not reported otherwise. It
also returns more detailed alignment and utilization failure messages that include the
exact location details of the failures.
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DESCRIPTION
The check_rp_groups command checks any violations of relative placement constraints
for the specified relative placement groups. The violations include failing to place the
specified relative placement groups and the placed relative placement groups not meeting
relative placement constraints.
The command returns a collection containing the relative placement groups that are
checked. If no groups are checked, an empty string is returned.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following examples use check_rp_groups to check for relative placement failures:
prompt> get_rp_groups
{compare::g1 compare::g2 compare::g4 compare::g7}
prompt> check_rp_groups -all -out failures
{compare::g7 compare::g4 compare::g2 compare::g1}
prompt> check_rp_groups compare::g4 -out g4_failures
{compare::g4}
prompt> check_rp_groups compare::g4
********************************************
Report: The relative placement groups not meeting all constraints but
placed.
Version: B-2008.09
Date: Mon Sep 11 04:44:34 2008
Number of relative placement groups: 1
********************************************
relative placement GROUP: compare::g4
--------------------------------------Warning: Possible placement failure of relative placement group
'compare::g4'
(RPGP-027)
{compare::g4}
prompt> check_rp_groups compare::g1
****************************************
Report: The relative placement groups that could not be placed.
Version: B-2008.09
Date: Mon Sep 11 04:47:25 2008
Number of relative placement groups: 1
****************************************
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relative placement GROUP: compare::g1
--------------------------------------Warning: Possible placement failure of relative placement group
'compare::g1'
(RPGP-027)
{compare::g14}
SEE ALSO
add_to_rp_group(2)
create_rp_group(2)
remove_rp_groups(2)
check_rp_groups
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check_scan_chain
Allows scan chain structural consistency checking based on the scan chain information
stored in the current design.
SYNTAX
status check_scan_chain
[-chain_name chain_name]
Data Types
chain_name
string
ARGUMENTS
-chain_name chain_name
Displays detailed information about the structural checking of the specified scan chain,
including location of inconsistency.
DESCRIPTION
This command performs a scan chain structural checking based on the scan chain
information stored in the current CEL. If the scan chain passes all the structural checks, then
the scan chain status is "VALIDATED"/V and the chain can be physically design-for-test
(DFT) optimized. If the scan chain fails the structural checks then the scan chain status is
"FAILED"/F and the chain cannot be physically optimized.
By default, the command generates a summary report. To generate a detailed report for a
specific scan chain, use the -chain_name option.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example checks for scan chain structural consistency.
prompt> check_scan_chain
Checking SCANDEF...
Checking scan cell correspondence between SCANDEF and netlist...
Start scan chain checking...
All checks completed.
Warning: There are 2 scan chains with no PARTITION label which can result
in lower QoR. (PSYN-1019)
****************************************
Report :
Design :
Version:
Date
:
Scan DEF check
E2080_cpu
I-2013.12-DEV
Mon Jul 22 21:56:52 2013
****************************************
Information from SCANDEF file:
Number of SCANCHAINS: 2
Checking between SCANDEF file and design:
Total SCANCHAINS checked: 2
VALIDATED : 2
FAILED
: 0
Chain name
---------1
U381/A
2
Status
-----V
#cells
-----98
#bits
----62
PARTITION
--------no_partition
Scan IN
------U10/C
Scan OUT
-------alu1/
V
74
61
no_partition
U11/C
U9/B
1
The following example checks for the scan chain structural consistency of scan chain 2.
prompt> check_scan_chain -chain 2
Checking SCANDEF...
Checking scan cell correspondence between SCANDEF and netlist...
Checking scan chain checking...
All checks completed.
****************************************
Report :
Design :
Version:
Date
:
Scan DEF check
E2080_cpu
Z-2007.03-ICC-BETA1
Tue Jan 9 14:38:37 2007
****************************************
check_scan_chain
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Information from SCANDEF file:
Number of SCANCHAINS: 2
Checking between SCANDEF file and design:
Total SCANCHAINS checked: 2
VALIDATED : 2
FAILED
: 0
Information on SCANCHAIN 2:
STATUS: V
Examining design SCANCHAIN 2:
STOP: U9/B
thru: statemachine1/counter_reg_3_/SI
thru: statemachine1/counter_reg_2_/SI
thru: statemachine1/counter_reg_1_/SI
thru: statemachine1/counter_reg_0_/SI
START: U11/C
1
SEE ALSO
read_def(2)
optimize_dft(2)
report_scan_chain(2)
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check_scenarios
Performs consistency checks between the scenarios, for scenario specific information such
as TLUplus files, operating conditions on the libraries, clocks and so on.
SYNTAX
status check_scenarios
[-output ]
[-display]
ARGUMENTS
-output
Specifies the directory to store the output. By default output is stored in HTML format in
the directory, design_dir/check_scenarios_mmddyyyy_pid
-display
Opens a HTML browser to display the data. The browser to be used is defined by the Tcl
variable, gui_online_browser.
DESCRIPTION
The check_scenarios command checks and reports issues with the scenarios. The
command performs the following checks: TLUplus, clock related information such as clock
periods, default versus nominal PVT on libraries, PVT from blocks versus parent, and PVT
of library cells.
Multicorner-Multimode Support
This command uses information from all active scenarios. This command also supports
designs that are not multicorner-multimode designs.
EXAMPLES
The following is an example of the check_scenarios command:
prompt> check_scenarios
check_scenarios
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check_scenarios
Warning: The complexity of the scenario (s1) might cause long runtime and
high
memory usage. (MCMM-212)
Warning: Scenario (s1) has instances which referenced library cells that
are
marked as "dont_use". (MCMM-225)
Warning: Scenario (s2) has a library setup issue with regard to the PVT
values
and the operating condition. (MCMM-213)
Information: HTML report can be found at
/WORKING_DIRECTORY/run/check_scenarios_7132009_21451/
check_scenarios_0.html
SEE ALSO
gui_online_browser(3)
Chapter 1:
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check_signoff_correlation
Performs correlation checking in IC Compiler, PrimeTime, and StarRC.
SYNTAX
status check_signoff_correlation
[-setup]
[-spef_out]
[-pt_only]
[-star_only]
[-preroute]
[-keep_signoff_mode]
[-output directory]
[-html]
Data Types
directory
string
ARGUMENTS
-setup
Performs setup correlation checks between IC Compiler and PrimeTime and between IC
Compiler and StarRC.
This is the default option if you do not specify any options.
-spef_out
Writes out an SPEF file from both IC Compiler and StarRC and a compare script. The
compare script is used to perform parasitic correlation from the two SPEF files.
-pt_only
Performs only the correlation check between IC Compiler and PrimeTime. The parasitic
correlation check between IC Compiler and StarRC is not performed.
-star_only
Performs only the correlation check between IC Compiler and StarRC. The timing
correlation check between IC Compiler and PrimeTime is not performed.
check_signoff_correlation
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-preroute
Assumes that the design is a preroute design and performs only the preroute correlation
checks.
By default, the check_signoff_correlation command assumes that the design is a
postroute design
You cannot use this option with the -spef_out option.
-keep_signoff_mode
Keeps the tool in sign-off mode after running the correlation.
By default, the check_signoff_correlation command exits sign-off mode after the
command is finished.
You can use this option with the -spef_out option, but you should not use it with the
-preroute option or when only setup correlation checks are performed.
-output directory
Specifies the name of the output directory for the saved scripts and files. If the specified
directory does not exist, the command creates it.
By default, the check_signoff_correlation command saves the scripts and files in a
directory whose name is based on the timestamp of the run.
-html
Generates an HTML correlation report in addition to the scripts. You can use a Web
browser to review the reports, to get a summary of all warnings and errors, and to get
additional information by clicking on the message ID values.
The -html option supports multicorner-multimode designs.
By default, the check_signoff_correlation command generates only the
recommended script for setup.
DESCRIPTION
The check_signoff_correlation command performs sign-off correlation checks between IC
Compiler and PrimeTime and between IC Compiler and StarRC. It generates correlation
reports and IC Compiler script files for correlation improvement. In a multicorner-multimode
design, you can source the script files to fix all correlation issues in all scenarios once and
then run the update_timing command at the end. If you use the -spef_out option, the
command also generates SPEF files from IC Compiler and StarRC.
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Before running this command, you need to provide PrimeTime settings with the
set_primetime_options command and StarRC settings with the set_starrcxt_options
command.
Multicorner-Multimode Support
This command uses information from all active scenarios.
SEE ALSO
run_signoff(2)
set_primetime_options(2)
set_starrcxt_options(2)
report_primetime_options(2)
report_starrcxt_options(2)
check_signoff_correlation
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check_timing
Checks for possible timing problems in the current design.
SYNTAX
status check_timing
[-overlap_tolerance minimum_distance]
[-override_defaults check_list]
[-multiple_clock]
[-retain]
[-include check_list]
[-exclude check_list]
Data Types
minimum_distance
check_list
float
list
ARGUMENTS
-overlap_tolerance minimum_distance
Specifies the minimum distance allowed between the master close edge and the slave
open edge. If the distance is less than this value, the tool issues a warning. Use this
option to check for the master-slave clock overlap. By default, this option is off.
-override_defaults check_list
Overrides the checks in timing_check_defaults by using the argument specified in
check_list. If the -override_defaults option is used with a check list, the final list of
checks to be performed is the one in the check_list argument of the -override_defaults
option.
-multiple_clock
Issues a warning when multiple clocks reach a register clock pin. If more than one clock
signal reaches a register clock pin, and the timing_enable_multiple_clocks_per_reg
variable is set to false, then the clock to use for analysis is undefined, and the tool
generates a warning message. In this case, use either the set_case_analysis or
set_disable_timing command so that only one clock can propagate from the sources
to the register clock pin. By default, this option is off.
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-retain
Provides a warning if any of the RETAIN values is larger than its corresponding delay
value. The RETAIN values should be less than their corresponding delay values so that
they can be considered for hold violations. Otherwise, the RETAIN values might be
considered for setup violations. By default, this option is off.
-include check_list
Adds the checks listed in check_list to the checks defined by the
timing_check_defaults variable.
-exclude check_list
Subtracts the checks listed in check_list from the checks defined by the
timing_check_defaults variable.
DESCRIPTION
This command checks the timing attributes placed on the current design and issues warning
messages as needed. The messages provide information that identifies and corrects
potential errors. The warnings do not necessarily indicate design problems.
This command without any options performs the checks defined by the
timing_check_defaults variable. Redefine this variable to change the value. If the
-override_defaults option is not used, the final list of checks to be performed is the list of
checks specified by the timing_check_defaults variable, plus the list of checks given by
the -include option, minus the list of checks given by the -exclude option. If the
-override_defaults option is used with a check_list, the final list of checks to be performed
is the checks in the check_list given by the option.
The alphabetically ordered list below shows the meaning of each check:
clock_crossing
Checks clock interactions when there are multiple clock domains. If a clock launches one or
more paths that are captured by other clocks, it will have an entry in the clock crossing
report. If all paths between two clocks are false paths or they are exclusive or asynchronous
clocks, the path is marked with an asterisk (*). If only some of the paths are set as false
paths, the path is marked by a number sign (#).
clock_no_period
Warns if clocks with no period are specified.
data_check_multiple_clock
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Warns if multiple clocked signals reach a data check register reference pin. The analysis is
done separately for each of the clocked domains. If the
timing_enable_multiple_clock_per_reg variable is set to false, only one of the clocked
signals is analyzed.
data_check_no_clock
Warns if no clocked signal reaches a data check register reference pin. In this case, no
setup or hold checks are performed on the constrained pin.
gated_clock
Warns about the gated clocks. Disable the gating timing arcs only if the propagated_clock
attribute is set on that clock.
generated_clock
Checks the generated clock network. Three types of issues are reported:
•
The source pin (master point) is not the clock source.
•
The definition point of the generated clock has no path to the source point.
•
The generated clocks form a loop.
generic
Warns about generic (unmapped) cells in the design. The timing of paths through generic
cells is inaccurate because generic cells have zero delay.
ideal_clocks
Warns about any clock networks that are ideal. Generally, all clocks should be propagated
so that the clock network timing is accurately calculated. Especially in the presence of
crosstalk, the delay changes induced by other nets on the clock network will not reflected in
the calculated slacks in the design.
ideal_timing
Warns that user_defined ideal transition or latency is set on a normal pin (not ideal).
loops
Warns of combinational feedback loops. If the feedback loop is not broken by the
set_disable_timing command, it is automatically broken by disabling one or more timing
arcs.
multiple_clock
This item should also be specified by the -multiple_clock option.
net_no_driving_info
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Warns about any net that does not have driving pins or that there are no timing arcs on the
driver pins. The warning is issued only when the net has coupled parasitic.
no_driving_cell
Warns about any port that does not have a driving cell. The warning is issued only when the
net connected to the port has parasitic. When no driving cell is specified, that net is assigned
a strong driver for modeling aggressor effects, which can be pessimistic. Also, a port with no
driving cell could act as a strong victim, which could underestimate the crosstalk effect.
no_input_delay
Warns if no clock-related delay is specified on an input port, where it propagates to a
clocked latch or output port. If the timing_input_port_default_clock variable is set to true,
a default clock is assumed for the input port. Otherwise, it will not be clocked, and the paths
are unconstrained. In this case, if there is no input delay specified, check_timing does not
generate warnings.
partial_input_delay
Warns about any ports have partially defined input delay; only the minimum or only the
maximum delay defined with set_input_delay. As a result, some paths starting from the
port with partially defined input delay may become unconstrained and some potential
violations could be missed.
pulse_clock_cell_type
Warns if an instance cell has a mismatched pulse type defined from its library cell.
retain
This check item should also be specified by the -retain option.
unconstrained_endpoints
Warns about unconstrained timing endpoints. This warning identifies timing endpoints that
are not constrained for maximum delay (setup) checks. If the paths to the endpoint are all
false paths, endpoints are not reported as unconstrained endpoints.
The warning messages that can occur when using this command are described below.
•
The warning message shown below occurs when the waveforms applied to a
master-slave register are overlapping or have different periods. Use the create_clock
command to modify one of the waveforms.
•
The overlap check first determines the intended master-slave waveform relationships
based on the ideal clock waveforms. Then the clock network delay and uncertainty is
applied to the waveforms and if the distance between the related edges is less than the
overlap tolerance, the tool issues a warning.
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WARNING: The following master-slave registers have overlapping clock violations. The
waveforms or periods may be invalid.
•
The warning message shown below identifies timing endpoints (output ports and register
data pins) that are not constrained. If the endpoint is a register data pin, use the
create_clock command for the appropriate clock source to constrain the pin. Use the
set_output_delay or set_max_delay command to constrain output ports. The
set_output_delay command constrains only the path when the delay is relative to a
clock.
WARNING: The following endpoints are not constrained for maximum delay.
•
The warning message shown below identifies gated clocks. Disable the gating timing
arcs only if the propagated_clock attribute is set on that clock.
WARNING: The clock network starting at "clk" is gated by the following input pins. The
gating timing arcs might need to be disabled for clocks with the "propagated_clock" attribute.
•
The warning message shown below occurs when the design contains unmapped cells
(generic logic), which causes the timing of the paths through the generic cells to be
inaccurate because generic cells have zero delay.
WARNING: Design "design_name" contains unmapped cells.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example checks the timing of the current design and issues warnings as
needed:
prompt> check_timing
Information: Checking
Information: Checking
Information: Checking
Information: Checking
Information: Checking
'unexpandable_clocks'...
'generic'...
'latch_fanout'...
'loops'...
'generated_clocks'...
SEE ALSO
check_design(2)
check_library(2)
create_clock(2)
Chapter 1:
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current_design(2)
set_case_analysis(2)
set_disable_timing(2)
set_max_delay(2)
set_output_delay(2)
timing_enable_multiple_clocks_per_reg(3)
check_timing
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check_tlu_plus_files
Checks the files used for TLUPlus extraction.
SYNTAX
status check_tlu_plus_files
ARGUMENTS
This command has no arguments.
DESCRIPTION
The check_tlu_plus_files command performs consistency checks on the TLUPlus files
used for virtual route and postroute extraction, which are specified by using the
set_tlu_plus_files command. If the TLUPlus files are from a Milkyway design library
attachment, this command does not do any checking because the attachment was already
checked when it was attached.
The following items are checked for consistency:
•
Layer names
The consistency check ensures that the conductor and via layer names are consistent
across the Milkyway, ITF, and mapping files. The tool also checks that the number of
layers are consistent between the ITF files and the Milkyway technology files. The tool
issues error messages if there are inconsistencies.
•
Etch values
The tool checks that the etch values in the ITF files are consistent with the delta width
values in the Milkyway technology files under minimum, nominal, and maximum
conditions. The signs used to indicate expand and shrink are opposite in the ITF files and
the Milkyway technology files. The tool issues warning messages if there are
inconsistencies.
•
Minimum width and minimum spacing
The tool checks that the minimum width and minimum spacing are consistent between
the ITF files and the Milkyway technology files, and among different minimum, nominal,
and maximum ITF files. The tool issues warning messages if there are inconsistencies.
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Conductor thickness
The tool checks that the conductor thicknesses are consistent between the ITF files and
the Milkyway technology files. The tool issues warning messages if there are
inconsistencies.
Multicorner-Multimode Support
This command uses information from all scenarios.
EXAMPLES
The following example runs the consistency checks:
prompt> check_tlu_plus_files
SEE ALSO
check_library(2)
set_tlu_plus_files(2)
check_tlu_plus_files
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check_zrt_routability
Locates and reports design obstructions that can prevent clean routing. The main function
of this command is to identify blocked ports. It also performs out-of-boundary checks and
minimum-grid checks.
SYNTAX
status check_zrt_routability
[-error_view view_name]
[-check_standard_cell_blocked_ports true | false]
[-check_non_standard_cell_blocked_ports true | false]
[-check_pg_blocked_ports true | false]
[-check_frozen_net_blocked_ports true | false]
[-check_min_grid true | false]
[-check_out_of_boundary true | false]
[-obey_access_edges true | false]
[-access_edge_whole_side true | false]
[-report_no_access_edge true | false]
[-obey_direction_preference true | false]
[-blocked_range integer]
[-blocked_range_via_side integer]
[-standard_cell_search_range integer]
[-allow_via_rotation true | false]
[-connect_standard_cells_within_pins true | false]
[-check_no_net_pins true | false]
[-honor_layer_constraints true | false]
Data Types
view_name
integer
string
integer
ARGUMENTS
-error_view view_name
Specifies the name of the generated error view.
The default is top_cell_name.err.
If there is an existing error view with the specified (or default) name, the tool overwrites
it.
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-check_standard_cell_blocked_ports true | false
Controls whether the command checks for blocked standard cell ports.
By default (true), the standard cell ports are checked.
-check_non_standard_cell_blocked_ports true | false
Controls whether the command checks for blocked macro, top-level, and
non-standard-cell ports.
By default (true), the macro, top-level, and non-standard-cell ports are checked.
-check_pg_blocked_ports true | false
Controls whether the command checks for blocked power and ground ports.
By default (false), the power and ground ports are not checked.
-check_frozen_net_blocked_ports true | false
Controls whether the command checks for blocked frozen net ports.
By default (false), the frozen net ports are not checked.
-check_min_grid true | false
Controls whether the command checks and reports design objects that are not on the
user (manufacturing) minimum grid.
By default (true), the minimum-grid checks are performed.
-check_out_of_boundary true | false
Controls whether the command checks and reports the pins that are outside of the
design boundary. The design boundary is the same as the "die size."
By default (true), the out-of-boundary checks are performed.
-obey_access_edges true | false
Controls whether pins can be connected only at their access edges.
By default (false), pins can be connected at any point.
-access_edge_whole_side true | false
Controls the access points when access edges are obeyed (-obey_access_edges
true).
An access edge is marked by a narrow rectangle, a short line, or even by a single point.
The access edge mark either fully or partially overlaps one of the port edges. When the
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overlap is not full, such as when the access edge mark is a single point, there are two
possible interpretation of the connection rule.
By default (true), the connection can be made to any point on the marked port edge. If
set to false, only the exact access edge mark can be used.
-report_no_access_edge true | false
Controls whether the command reports the unconnected pins without predefined access
edges.
By default (false), pins without access edges are not reported.
-obey_direction_preference true | false
Controls whether only preferred direction access is allowed.
By default (false), access is allowed in both the horizontal and vertical directions. When
set to true, access is allowed only in the preferred direction.
This option applies only to non-standard-cell ports. (Standard-cell ports are usually
accessed only by vias. When a wire on the port layer is needed, it can be in any
direction.)
-blocked_range integer
Specifies the number of pitches for the same-layer accessibility check for macro and
top-level ports.
The default is 10.
-blocked_range_via_side integer
Specifies the number of pitches for the accessibility check on the other side of an access
via.
The default is 10.
This check applies only to macro and top-level ports.
-standard_cell_search_range integer
Specifies the number of pitches for the same-layer accessibility search of standard cell
pins.
The default is 2.
-allow_via_rotation true | false
Controls whether pin connections can use rotated vias.
By default (true), pin connections can use rotated vias.
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-connect_standard_cells_within_pins true | false
Controls whether via connections to standard cell pins must be fully inside the pins.
By default (false), the via connections do not need to be fully inside the pins.
-check_no_net_pins true | false
Controls whether the command checks the accessibility for pins without an assigned
net.
By default (false), the command does not check pins without nets.
-honor_layer_constraints true | false
Controls whether the command considers the layer constraints when checking the
accessibility of ports and the connectivity of nets.
The layer constraints include the global minimum and maximum routing layer
constraints set by the -min_routing_layer and -max_routing_layer options of the
set_ignored_layers command; the net-specific minimum and maximum routing layer
constraints set by the -min_layer_name and -max_layer_name options of the
set_net_routing_layer_constraints command; and the freeze layer constraints set by
the -freeze_layer_by_layer_name and
-freeze_via_to_frozen_layer_by_layer_name options of the
set_route_zrt_common_optiona command.
By default (true), the command considers the layer constraints when checking for
blocked ports and nets.
DESCRIPTION
The check_zrt_routabilty command identifies blocked ports, out-of-boundary ports, and
minimum-grid violations for all design objects. The results are reported as part of the
standard output and in an error view. The error view can be accessed by the GUI error
browser.
A logical port can have several physical pins. A port is considered blocked if none of its pins
is accessible.
A top-level or macro pin is considered accessible if a legal path can be extended from the
pin to a certain distance around it. This path can be only on the pin layer or can extend to a
neighboring layer by a single via. The required distance on the pin layer and on the layer at
the other side of the via are set by the -blocked_range and -blocked_range_via_side
options.
A standard cell pin is considered accessible if there is a legal path that extends to the next
layer or a path on the pin layer that extends to the distance set by the
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-standard_cell_search_range option or a shorter path on the pin layer ended by a via to a
neighboring layer.
To get DRC-clean routing, you must fix all reported violations.
•
You can fix blocked ports by removing or modifying the blockages, by moving or
modifying the ports, or by modifying the netlist.
•
You can fix out-of-boundary ports by moving them or, if appropriate, by fully removing
them.
•
You can either fix minimum-grid violations or intentionally accept them.
You can run the check_zrt_routability command at any stage of the routing flow. However,
it is most useful when run before global routing. It can be useful to run the command after
routing to identify the root cause of certain routing failures.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following command performs accessibility checks, out-of-boundary checks, and
minimum-grid checks. You should run it before global routing and, if needed, modify the
design according to the generated report.
prompt> check_zrt_routability
The command writes a report to the standard output. The report includes either "no
violation" messages or a detailed list of the violations. The following example shows a report
for a design with violations:
=======================================
==
Check for min-grid violations
==
==
(At data load stage)
==
=======================================
>>> X MinGrid Violation in via cell instance inst_name at (85.432 62.100)
>>> Y MinGrid Violation in via center at (43.500 60.137)
>>>>>> Found 2 min-grid violations
=======================================
== Check for out-of-boundary ports ==
=======================================
>>> Port (chip4 clkin) at [-0.40, 50.500...0.20, 50.700] M3,M4 out of
boundary
>>>>>> Found 1 out-of-bound ports
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=======================================
==
Check for blocked ports
==
=======================================
>>>>>> Port blocked by layer constraints- min/max and freeze layer
settings
>>> Port at [328.095,34.485..328.270,35.915] M1 is blocked by layer
constraints.
Inst=driveB Master=ADR1 Port=Out2 Net=net123
>>>>>> Port blocked by check port access
>>> Port at [20.400,40.750..20.450,40.850] M1 is blocked. Inst=driveA
Master=BufAA2 Port=Out1 Net=setoo
>>>>>> The design cannot be cleanly routed because it has 2 completely
blocked ports
>>>>>> Net blocked by layer constraints- min/max and freeze layer
settings
>>> Net netA at [328.095,34.205..339.300,35.915] is blocked with its
ports
isolated by layer constraints.
>>> Net netB at [328.095,34.205..339.300,35.915] is blocked with its
ports
isolated by layer constraints and the shapes on freeze layer can't be
accessed.
>>>>>> The design cannot be cleanly routed because it has 2 blocked Nets
The following command performs only out-of-boundary and minimum-grid checks:
prompt> check_zrt_routability \
-check_standard_cell_blocked_ports false \
-check_non_standard_cell_blocked_ports false
The following command does not report minimum-grid violations:
prompt> check_zrt_routability -check_min_grid false
SEE ALSO
route_zrt_global(2)
route_zrt_detail(2)
route_zrt_auto(2)
set_ignored_layers(2)
set_route_zrt_common_options(2)
set_net_routing_layer_constraints(2)
check_zrt_routability
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clock_opt
Performs clock tree synthesis, routing of clock nets, extraction, optimization, and hold time
violation fixing on the design. There is also an option to perform interclock delay balancing.
SYNTAX
status clock_opt
[-only_psyn]
[-fix_hold_all_clocks]
[-inter_clock_balance]
[-update_clock_latency]
[-operating_condition
min | max | min_max]
[-only_cts]
[-clock_trees name_of_clocks]
[-optimize_dft]
[-continue_on_missing_scandef]
[-no_clock_route]
[-only_hold_time]
[-area_recovery]
[-size_only | -in_place_size_only]
[-power]
[-insert_self_gating]
[-congestion]
[-concurrent_clock_and_data]
[-incremental_concurrent_clock_and_data]
ARGUMENTS
-only_psyn
Performs optimization only.
-fix_hold_all_clocks
Performs hold time violation fixing for all clocks during incremental optimization.
By default, the clock_opt command does not perform hold fixing.
-inter_clock_balance
Performs interclock delay balancing.
By default, the clock_opt command does not perform interclock delay balancing.
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-update_clock_latency
Updates the latencies on real and virtual clock objects after clock tree synthesis, clock
tree optimization, interclock delay balancing (if enabled), and clock tree detail routing.
This option effectively executes the set_clock_latency command internally for the clock
objects and uses the insertion delay of the clock tree as the latency value. If you run the
set_latency_adjustment_options command before the clock_opt command, the
directives are obeyed. If you do not specify any directives, only the latencies of real clock
objects are updated. The update mechanism uses the insertion delay of the clock tree
as the latency value.
-operating_condition min | max | min_max
Specifies the operating condition. The default is max.
-only_cts
Performs only clock tree synthesis, clock tree optimization, and clock tree routing.
-clock_trees name_of_clocks
Performs clock tree synthesis and optimization on the clocks specified in the order
specified.
-optimize_dft
Enables clock-aware scan reordering.
The reordering tries to minimize the number of buffer crossings in the scan chains.
Minimizing the number of buffer crossings can reduce hold time violations in the scan
chains.
When you specify this option, you must load the SCANDEF data that defines the scan
chains before running the clock_opt command. You can use the get_scan_chains
command to check if the SCANDEF data is available.
For best results, first use the place_opt -optimize_dft command to perform
placement-aware scan reordering.
By default, the clock_opt command does not perform scan reordering.
-continue_on_missing_scandef
Continues placement when the design contains scan chains but no SCANDEF data.
By default, missing SCANDEF data causes the command to exit with an error message.
If you specify this option, the command continues with a warning and results in reduced
quality-of-results.
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-no_clock_route
Disables routing of clock nets.
-only_hold_time
Performs only hold time fixing after clock tree synthesis.
If you specify the -fix_hold_all_clocks option, the tool fixes hold time violations for all
clocks. Otherwise, the tool fixes hold time violations only for the clocks specified with the
set_fix_hold command.
-area_recovery
Enables area recovery for the cells not on the timing critical paths.
-size_only
Restricts post clock tree synthesis optimization to sizing changes only. Optimization
procedures that insert new cells and remove cells are disabled.
See the description for the -in_place_size_only option for information about how to
further constrain sizing changes.
The -size_only and -in_place_size_only options are mutually exclusive.
-in_place_size_only
Restricts post clock tree synthesis optimization to in-place sizing changes only.
Optimization procedures that insert new cells and remove cells are disabled.
With the -in_place_size_only option, sizing changes are further constrained for minimal
engineering change order (ECO) placement changes. For example, a cell is sized to
improve timing or design rule costs only if the newly-sized cell can fit into any available
space adjacent to the original cell location. The resulting transformation is verified to
ensure that it is legal.
The -size_only and -in_place_size_only options are mutually exclusive.
-power
Performs the enabled clock tree power optimizations before clock tree synthesis, as well
as power-aware timing optimization and leakage-power optimization after clock tree
synthesis.
The supported clock tree power optimizations are power-aware placement and clock
gate restructuring. To enable power-aware placement, use the
set_optimize_pre_cts_power_options command to set the -low_power_placement
option to true. When you enable power-aware placement, the tool performs incremental
switching-activity-based power-aware placement. For the best results from
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power-aware placement, you should specify the same coarse placement setup, such as
the placer_max_cell_density_threshold variable, used in the place_opt command
before running the clock_opt command.
To enable clock gate restructuring, use the set_optimize_pre_cts_power_options
command to set the -merge_clock_gates option to true.
The clock_opt command can perform leakage-power optimization based on either the
multiple-threshold-voltage constraint or the leakage values of the library cells. To
perform leakage-power optimization based on the multiple-threshold-voltage constraint,
use the set_multi_vth_constraint command to define this constraint before running the
clock_opt command. If this constraint is not defined, the tool bases the leakage-power
optimization on the leakage values of the library cells.
When you specify this option for a multicorner-multimode design, you must use the
set_scenario_options command to select the leakage scenarios before running the
clock_opt command.
When you use the -power option with the -only_cts option, the enabled clock tree
power optimizations are performed before clock tree synthesis; leakage-power
optimization is not performed.
When you use the -power option with the -only_psyn option, power-aware timing
optimization and leakage-power optimization are performed but the clock tree power
optimizations are not performed.
To perform only power-aware-timing optimization and not clock-tree-power or
leakage-power optimization, do not use the -power option. Instead, set the
icc_preroute_power_aware_optimization variable to true before running the
clock_opt command.
-insert_self_gating
Inserts XOR self-gating logic during clock tree synthesis before clock tree construction.
For best results, you should provide the clock activity information by reading a SAIF file
with the read_saif command before running the clock_opt command.
-congestion
Performs congestion-driven incremental placement during the post clock tree synthesis
optimization stage.
By default, the clock_opt command does not consider congestion during incremental
placement.
-concurrent_clock_and_data
When -only_cts option is used along with -concurrent_clock_and_data option, the tool
synthesizes the clock trees, performs data-path optimization, and computes useful skew
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for improving the setup WNS and TNS, and rebuilds the clock trees to implement the
useful skew. When -concurrent_clock_and_data is used along with only_cts option,
clock_opt command accepts other data-path optimization options such as
area_recovery, congestion, etc to guide the data-path optimization that is performed
inside.
When -only_psyn option is used along with -concurrent_clock_and_data option, the
tool performs data-path optimization, WNS improvement driven clock tree optimization,
and finally performs an additional data-path optimization.
When -concurrent_clock_and_datai is used without only_cts or only_psyn, it is
equivalent to clock_opt -only_cts -concurrent_clock_and_data followed by clock_opt
-only_psyn -concurrent_clock_and_data.
-incremental_concurrent_clock_and_data
Performs incremental data-path optimization and timing improvement driven clock tree
optimization. The optimization at this stage improves timing in all active scenarios.
Options -area_recovery and -continue_on_missing_scandef can be used with
-incremental_concurrent_clock_and_data.
When this option is given, no clock detail route is called even there is no -no_clock_route
given.
It is recommended to use -incremental_concurrent_clock_and_data only after clock_opt
-only_cts -concurrent_clock_and_data and clock_opt -only_psyn
-concurrent_clock_and_data have already been run.
DESCRIPTION
The clock_opt command performs clock tree synthesis, routing of clock nets, extraction,
optimization, and optionally hold time violation fixing on the current design.
If clock tree synthesis or the routing of the clock nets fails, the command returns with a value
of 0.
If you specify the -only_psyn option, the tool performs only extraction and optimization on
a clock-routed design. This option can be used in a customized clock tree synthesis flow
where clock tree synthesis is performed outside of the clock_opt command.
Before running the clock_opt command, use the set_clock_tree_options command to
control the compile_clock_tree command. Use the set_latency_adjustment_options
command to issue directives to control the adjustment of latency on clock objects that
belong to virtual and real clocks. If no directives are given, the default clock_opt command
flow updates the latencies of real clocks with their insertion delays obtained after the
compile_clock_tree, optimize_clock_tree, and optionally balance_inter_clock_delay
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commands. Use the set_inter_clock_delay_options command to control the behavior of
interclock delay balancing within the clock_opt command.
Briefly, the clock_opt command
•
Runs the optimize_pre_cts_power command, if enabled
•
Runs the compile_clock_tree command
•
Runs the optimize_clock_tree command
•
Runs the set_propagated_clock command for all clocks from the root pin, but keeps
the clock object as ideal
•
Performs interclock delay balancing, if enabled
•
Performs detail routing of the clock nets
•
Performs RC extraction of the clock nets and computes accurate clock arrival times
•
Updates the latency on clock objects, if enabled
•
Reduces congestion, if enabled
•
Optimizes the scan chains, if enabled
•
Fixes the placement of the clock tree buffers and inverters
•
Runs the psynopt command
•
Fixes hold time violations, if enabled
Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios. All scenarios
enabled as clock tree synthesis scenarios are activated for clock tree synthesis and are
returned to their current state (active or inactive) after clock tree synthesis. If you enable
clock_opt
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power optimization, you must select the leakage scenarios before running the clock_opt
command.
EXAMPLES
The following command performs clock tree synthesis, routing of all clock nets, extraction,
and optimization:
prompt> clock_opt
SEE ALSO
extract_rc(2)
psynopt(2)
place_opt(2)
read_saif(2)
route_opt(2)
set_clock_tree_options(2)
set_inter_clock_delay_options(2)
set_latency_adjustment_options(2)
set_multi_vth_constraint(2)
set_scenario_options(2)
icc_preroute_power_aware_optimization(3)
skew_opt(2)
set_concurrent_clock_and_data_strategy(2)
reset_concurrent_clock_and_data_strategy(2)
report_concurrent_clock_and_data_strategy(2)
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clock_opt_feasibility
Performs optimization feasibility analysis on the design after clock tree synthesis.
SYNTAX
status clock_opt_feasibility
[-congestion]
[-clock_route]
[-only_psyn]
[-fix_hold_all_clocks]
[-inter_clock_balance]
[-update_clock_latency]
[-operating_condition
min | max | min_max]
[-only_cts]
[-optimize_dft]
[-continue_on_missing_scandef]
[-no_clock_route]
[-only_hold_time]
[-area_recovery]
[-size_only]
[-in_place_size_only]
[-power]
[-no_legalize_large_displacement]
[-large_displacement_threshold number_of_cell_rows]
Data Types
number_of_cell_rows
int
ARGUMENTS
-congestion
Performs congestion removal during the optimization feasibility flow.
By default, the command does not perform congestion removal.
-clock_route
Performs clock net routing after optimization.
By default, the command does not perform clock routing.
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-only_psyn
Performs optimization only.
-fix_hold_all_clocks
Performs hold time violation fixing for all clocks during incremental optimization.
By default, the command does not perform hold fixing.
-inter_clock_balance
Performs interclock delay balancing.
By default, the command does not perform interclock delay balancing.
-update_clock_latency
Updates the latencies on real and virtual clock objects after clock tree synthesis, clock
tree optimization, interclock delay balancing (if enabled), and clock tree detail routing.
This effectively executes the set_clock_latency command internally for the clock
objects and uses the insertion delay of the clock tree as the latency value. If you run the
set_latency_adjustment_options command before the clock_opt_feasibility
command, the directives are obeyed. If you do not specify any directives, only the
latencies of real clock objects are updated. The update mechanism uses the insertion
delay of the clock tree as the latency value.
-operating_condition min | max | min_max
Specifies the operating condition.
The default is max.
-only_cts
Performs only clock tree synthesis and clock tree optimization.
-optimize_dft
Enables clock-aware scan reordering.
The reordering tries to minimize the number of buffer crossings in the scan chains.
Minimizing the number of buffer crossings can reduce hold time violations in the scan
chains.
When you specify this option, you must load the SCANDEF data that defines the scan
chains before running the clock_opt command. You can use the get_scan_chains
command to check if the SCANDEF data is available.
For best results, first use the place_opt -optimize_dft command to perform
placement-aware scan reordering.
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-continue_on_missing_scandef
Continues placement when the design contains scan chains but no SCANDEF data.
By default, missing SCANDEF data causes the command to exit with an error message.
If you specify this option, the command continues with a warning and results in reduced
quality-of-results (QoR).
-no_clock_route
Disables routing of clock nets. This is the default behavior.
-only_hold_time
Performs only hold time fixing after clock tree synthesis.
If you specify the -fix_hold_all_clocks option, the tool fixes hold time violations for all
clocks. Otherwise, the tool fixes hold time violations only for the clocks specified with the
set_fix_hold command.
-area_recovery
Enables area recovery for the cells not on the timing critical paths.
-size_only
Restricts post clock tree synthesis optimization to sizing changes only. Optimization
procedures that insert new cells and remove cells are disabled.
The -size_only and -in_place_size_only options are mutually exclusive. See the
description for the -in_place_size_only option for additional information about how to
further constrain sizing changes.
-in_place_size_only
Restricts post clock tree synthesis optimization to in-place sizing changes only.
Optimization procedures that insert new cells and remove cells are disabled.
With the -in_place_size_only option, sizing changes are further constrained for minimal
engineering change order (ECO) placement changes. For example, a cell is sized to
improve timing or design rule costs only if the newly-sized cell can fit into any available
space adjacent to the original cell location. The resulting transformation is verified to
ensure that it is legal.
-power
Performs the enabled clock tree power optimizations before clock tree synthesis, as well
as leakage-power optimization after clock tree synthesis.
The supported clock tree power optimizations are power-aware placement and clock
gate restructuring. To enable power-aware placement, use the
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set_optimize_pre_cts_power_options command to set the -low_power_placement
option to true. When you enable power-aware placement, the tool performs incremental
switching-activity-based power-aware placement. For the best results from
power-aware placement, you should specify the same coarse placement setup, such as
the placer_max_cell_density_threshold variable, used in the place_opt command
before running the clock_opt_feasibility command.
To enable clock gate restructuring, use the set_optimize_pre_cts_power_options
command to set the -merge_clock_gates option to true.
The clock_opt_feasibility command can perform leakage-power optimization based
on either the multiple-threshold-voltage constraint or the leakage values of the library
cells. To perform leakage-power optimization based on the multiple-threshold-voltage
constraint, use the set_multi_vth_constraint command to define this constraint before
running the clock_opt_feasibility command. If this constraint is not defined, the tool
bases the leakage-power optimization on the leakage values of the library cells.
When you specify this option for a multicorner-multimode design, you must use the
set_scenario_options command to select the leakage scenarios before running the
clock_opt_feasibility command.
When you use the -power option with the -only_cts option, the enabled clock tree
power optimizations are performed before clock tree synthesis; leakage-power
optimization is not performed.
When you use the -power option with the -only_psyn option, leakage-power
optimization is performed but the clock tree power optimizations are not performed.
-no_legalize_large_displacement
Does not move cells beyond the distance threshold specified by the
-large_displacement_threshold option during legalization.
Those cells that are not legalized are kept at their illegal location. You can run the
legalize_placement command after feasibility analysis to legalize these illegal cells.
-large_displacement_threshold number_of_cell_rows
Specifies the displacement threshold for the -no_legalize_large_displacement option.
The unit for this option is the cell row height.
By default, the displacement threshold is the height of 10 cell rows.
DESCRIPTION
The clock_opt_feasibility command performs optimization feasibility analysis after clock
tree synthesis. You should run the feasibility flow during the early stages of the design flow
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to debug the design constraints. Both the setup and hold timing optimization engines are
designed for fast runtimes and are less exhaustive.
Run this command on a design with initial constraints, such as latency settings, and
cross-clock-domain-related timing issues. The clock_opt_feasibility flow runs faster than
the comparable clock_opt flow and produces reasonable QoR correlation.
By default, the clock_opt_feasibility command does not perform congestion removal to
save runtime. You can specify the -congestion option to perform the congestion removal
step or you can run the psynopt -congestion command separately.
By default, the clock_opt_feasibility command does not perform clock routing to save
runtime. You can specify the -clock_route option to perform clock routing or you can run the
route_zrt_group -all_clock_nets command separately.
By default, the clock_opt_feasibility command does not change the
placer_max_cell_density_threshold variable if it is already set. If it is not set, the
clock_opt_feasibility command uses a value of 0.8 for the variable when you use the
-congestion option. Set the placer_max_cell_density_threshold variable to its default of
-1 if you do not want to use the variable.
Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios. All scenarios
enabled as clock tree synthesis scenarios are activated for clock tree synthesis and are
returned to their current state (active or inactive) after clock tree synthesis. If you enable
power optimization, you must select the leakage scenarios before running the
clock_opt_feasibility command.
EXAMPLES
The following command performs optimization for feasibility analysis:
prompt> clock_opt_feasibility -only_psyn
SEE ALSO
clock_opt(2)
read_saif(2)
set_clock_tree_options(2)
set_inter_clock_delay_options(2)
set_latency_adjustment_options(2)
set_multi_vth_constraint(2)
set_scenario_options(2)
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close_distributed_route
Closes all of the sockets and shuts down the daemons.
SYNTAX
integer close_distributed_route
DESCRIPTION
Closes all of the sockets and shuts down the daemons on the slave machines.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
set_distributed_route(2)
report_distributed_route(2)
remove_distributed_route(2)
close_distributed_route
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close_mw_cel
Closes the specified Milkyway designs.
SYNTAX
status close_mw_cel
[-save]
[-hierarchy]
[-all_views]
[-all_versions]
[mw_cel_list]
Data Types
mw_cel_list
list
ARGUMENTS
-save
Indicates that the specified Milkyway designs are to be saved before closing. By default,
the command discards any changes made to the Milkyway design and closes the
specified Milkyway design.
-hierarchy
Closes the specified top design and all opened child designs. By default, the command
closes only the specified Milkyway designs.
When -hierarchy is specified, mw_cel_list can only specify the top design.
The -hierarchy argument cannot be used with -all_views and -all_versions.
-all_views
Closes all opened views of specified Milkyway designs. By default, the command closes
only the specified Milkyway designs. If this option is used with -save, only views
supported by save_mw_cel will be saved first and then all opened views will be closed.
If specifying this option without -all_versions, only the latest versions of all views will be
closed.
The -all_views argument cannot be used with -hierarchy.
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-all_versions
Closes all versions of specified Milkyway designs. If specifying this option with
-all_views, all views and all versions of the specified Milkway designs will be closed, or
else only all versions of the specified views will be closed.
The -all_versions argument cannot be used with -hierarchy.
mw_cel_list
Specifies Milkyway designs to be closed. You can specify Milkyway designs by name,
name pattern, or by the Milkyway design collection's name. For example, specifying top
matches a Milkyway design named top in the current library. Specifying top* matches all
Milkyway designs having names beginning with top. The command close_mw_cel
[get_mw_cels *] closes all Milkyway designs in the current library. By default, the
command uses the current Milkyway design.
DESCRIPTION
This command saves or discards specified Milkyway designs or the current Milkyway design
and then closes them.
If the closed Milkyway design appears in any design stack, it will be poped out from those
stacks first.
If the current working design is poped out of stack or is closed, we will switch current working
design to the top of most recently used stack.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example discards and closes the current Milkyway design.
prompt> close_mw_cel
1
The following example saves and closes a list of Milkyway designs.
prompt> close_mw_cel -save {test1 test2}
Information: Saved design named test1.CEL;1.
Information: Saved design named test2.CEL;1.
1
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The following example discards and closes a list of Milkyway designs.
prompt> close_mw_cel {test1 test2}
1
The following example saves and closes all views of the specified Milkyway design.
prompt> close_mw_cel -save -all_views test1
Information: Saved design named test1.CEL;1.
Information: Saved design named test1.FILL;2.
1
The following example saves and closes all versions of the specified Milkyway design.
prompt> close_mw_cel -save -all_versions {test1.FILL}
Information: Saved design named test1.FILL;1.
Information: Saved design named test1.FILL;2.
1
The following example saves and closes all views and all versions of the specified Milkyway
design.
prompt> close_mw_cel -save -all_views -all_versions test1
Information: Saved design named test1.CEL;1.
Information: Saved design named test1.FILL;1.
Information: Saved design named test1.FILL;2.
1
The following example saves and closes the specified top design and its opened child
designs.
prompt> close_mw_cel -hierarchy
Information: Saved design named
Information: Saved design named
Information: Saved design named
1
-save RISC_CORE
ALU.CEL;1. (UIG-5)
DATA_PATH.CEL;1. (UIG-5)
RISC_CORE.CEL;1. (UIG-5)
SEE ALSO
copy_mw_cel(2)
create_mw_cel(2)
current_mw_cel(2)
get_mw_cels(2)
open_mw_cel(2)
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remove_mw_cel(2)
rename_mw_cel(2)
mw_cel_collection(2)
list_mw_cels(2)
close_mw_cel
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close_mw_lib
Closes the current Milkyway library.
SYNTAX
status close_mw_lib
[-save]
ARGUMENTS
-save
Saves all Milkyway CEL views opened in this library. By default, the command discards
changes of Milkyway CEL views in this library.
DESCRIPTION
This command closes the current Milkyway library. It returns a status indicating success or
failure.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example closes the current Milkyway library:
prompt> close_mw_lib
1
SEE ALSO
open_mw_lib(2)
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close_rail_result
Closes the current rail result.
SYNTAX
status close_rail_result
DESCRIPTION
This command closes the current rail result.
After the rail result is closed, you cannot access any rail analysis result information such as
taps, voltage drop attributes, and power attributes.
EXAMPLE
The following example closes the current rail result.
prompt> open_rail_result static
prompt> get_attribute [ get_cell U35 ] total_power
1.0876e-06
prompt> close_rail_result
1
SEE ALSO
analyze_rail(2)
open_rail_result(2)
close_rail_result
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collections
Describes the methodology for creating collections of objects and querying objects in the
database.
DESCRIPTION
Synopsys applications build an internal database of objects and attributes applied to them.
These databases consist of several classes of objects, including designs, libraries, ports,
cells, nets, pins, clocks, and so on. Most commands operate on these objects.
By definition:
A collection is a group of objects exported to the Tcl user interface.
Collections have an internal representation (the objects) and, sometimes, a string
representation. The string representation is generally used only for error messages.
A set of commands to create and manipulate collections is provided as an integral part of the
user interface. The collection commands encompass two categories: those that create
collections of objects for use by another command, and one that queries objects for viewing.
The result of a command that creates a collection is a Tcl object that can be passed along
to another command. For a query command, although the visible output looks like a list of
objects (a list of object names is displayed), the result is an empty string.
An empty string "" is equivalent to the empty collection, that is, a collection with zero
elements.
To illustrate the usage of the common collection commands, the man pages have examples.
Most of the examples use PrimeTime as the application. In all cases, the application from
which the example is derived is indicated.
Homogeneous and Heterogeneous Collections
A homogeneous collection contains only one type of object. A heterogeneous collection can
contain more than one type of object. Commands that accept collections as arguments can
accept either type of collection.
Lifetime of a Collection
Collections are active only as long as they are referenced. Typically, a collection is
referenced when a variable is set to the result of a command that creates it or when it is
passed as an argument to a command or a procedure. For example, in PrimeTime, you can
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save a collection of design ports by setting a variable to the result of the get_ports
command:
pt_shell> set ports [get_ports *]
Next, either of the following two commands deletes the collection referenced by the ports
variable:
pt_shell> unset ports
pt_shell> set ports "value"
Collections can be implicitly deleted when they go out of scope. Collections go out of scope
for various reasons. An example would be when the parent (or other antecedent) of the
objects within the collection is deleted. For example, if our collection of ports is owned by a
design, it is implicitly deleted when the design that owns the ports is deleted. When a
collection is implicitly deleted, the variable that referenced the collection still holds a string
representation of the collection. However, this value is useless because the collection is
gone, as illustrated in the following PrimeTime example:
pt_shell> current_design
{"TOP"}
pt_shell> set ports [get_ports in*]
{"in0", "in1"}
pt_shell> remove_design TOP
Removing design 'TOP'...
pt_shell> query_objects $ports
Error: No such collection '_sel26' (SEL-001)
Iteration
To iterate over the objects in a collection, use the foreach_in_collection command. You
cannot use the Tcl-supplied foreach iterator to iterate over the objects in a collection,
because the foreach command requires a list, and a collection is not a list. In fact, if you use
the foreach command on a collection, it destroys the collection.
The arguments of the foreach_in_collection command are similar to those of foreach: an
iterator variable, the collection over which to iterate, and the script to apply at each iteration.
Note that unlike the foreach command, the foreach_in_collection command does not
accept a list of iterator variables.
The following example is an iterative way to perform a query in PrimeTime. For more
information, see the foreach_in_collection man page.
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pt_shell> \
foreach_in_collection s1 $collection {
echo [get_object_name $s1]
}
Manipulating Collections
A variety of commands are provided to manipulate collections. In some cases, a particular
command might not operate on a collection of a specific type. This is application-specific.
Consult the man pages from your application.
•
add_to_collection - This command creates a new collection by adding a list of element
names or collections to a base collection. The base collection can be the empty
collection. The result is a new collection. In addition, the add_to_collection command
allows you to remove duplicate objects from the collection by using the -unique option.
•
append_to_collection - This command appends a set of objects (specified by name or
collection) to an existing collection. The base collection is passed in through a variable
name, and the base collection is modified directly. It is similar in function to the
add_to_collection command, except that it modifies the collection in place; therefore, it
is much faster than the add_to_collection command when appending.
•
remove_from_collection - This command removes a list of element names or
collections from an existing collection. The second argument is the specification of the
objects to remove and the first argument is the collection to have them removed from.
The result of the command is a new collection. For example, in PrimeTime:
pt_shell> set dports \
[remove_from_collection [all_inputs] CLK]
{"in1", "in2", "in3"}
•
compare_collections - This command verifies that two collections contain the same
objects (optionally, in the same order). The result is "0" on success.
•
copy_collection - This command creates a new collection containing the same objects
in the same order as a given collection. Not all collections can be copied.
•
index_collection - This command extracts a single object from a collection and creates
a new collection containing that object. The index operation is done in constant time - it
is independent of the number of elements in the collection, or the specific index. Not all
collections can be indexed.
•
sizeof_collection - This command returns the number of objects in a collection.
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Filtering
In some applications, you can filter any collection by using the filter_collection command.
This command takes a base collection and creates a new collection that includes only those
objects that match an expression.
Some applications provide a -filter option for their commands that create collections. This
allows objects to be filtered out before they are ever included in the collection. Frequently
this is more efficient than filtering after the they are included in the collection. The following
examples from PrimeTime filters out all leaf cells:
pt_shell> filter_collection \
[get_cells *] "is_hierarchical == true"]
{"i1", "i2"}
pt_shell> get_cells * -filter "is_hierarchical == true"
{"i1", "i2"}
The basic form of a filter expression is a series of relations joined together with AND and OR
operators. Parentheses are also supported. The basic relation contrasts an attribute name
with a value through a relational operator. In the previous example, is_hierarchical is the
attribute, == is the relational operator, and true is the value.
The relational operators are
==
!=
>
<
>=
<=
=~
!~
Equal
Not equal
Greater than
Less than
Greater than or equal to
Less than or equal to
Matches pattern
Does not match pattern
The basic relational rules are
•
String attributes can be compared with any operator.
•
Numeric attributes cannot be compared with pattern match operators.
•
Boolean attributes can be compared only with == and !=. The value can be only true or
false.
Additionally, existence relations determine if an attribute is defined or not defined, for the
object. For example,
(sense == setup_clk_rise) and defined(sdf_cond)
The existence operators are
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defined
undefined
These operators apply to any attribute as long as it is valid for the object class. See the
appropriate man pages for complete details.
Sorting Collections
In some applications, you can sort a collection by using the sort_collection command. It
takes a base collection and a list of attributes as sort keys. The result is a copy of the base
collection sorted by the given keys. Sorting is ascending, by default, or descending when
you specify the -descending option. In the following example from PrimeTime, the command
sorts the ports by direction and then by full name.
pt_shell> sort_collection [get_ports *] \
{direction full_name}
{"in1", "in2", "out1", "out2"}
Implicit Query of Collections
In many applications, commands that create collections implicitly query the collection when
the command is used at the command line. Consider the following examples from
PrimeTime:
pt_shell> set_input_delay 3.0 [get_ports in*]
1
pt_shell> get_ports in*
{"in0", "in1", "in2"}
pt_shell> query_objects -verbose [get_ports in*]
{"port:in0", "port:in1", "port:in2"}
pt_shell> set iports [get_ports in*]
{"in0", "in1", "in2"}
In the first example, the get_ports command creates a collection of ports that is passed to
the set_input_delay command. This collection is not the result of the primary command
(set_input_delay), and as soon as the primary command completes, the collection is
destroyed. The second example shows how a command that creates a collection
automatically queries the collection when that command is used as a primary command.
The third example shows the verbose feature of the query_objects command, which is not
available with an implicit query. Finally, the fourth example sets the variable iports to the
result of the get_ports command. Only in the final example does the collection persist to
future commands until iports is overwritten, unset, or goes out of scope.
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SEE ALSO
add_to_collection(2)
append_to_collection(2)
compare_collections(2)
copy_collection(2)
filter_collection(2)
foreach_in_collection(2)
index_collection(2)
query_objects(2)
remove_from_collection(2)
sizeof_collection(2)
sort_collection(2)
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commit_fp_group_block_ring
Commits the power ground group block ring and/or straps based on the results from the
create_fp_group_block_ring command.
SYNTAX
status commit_fp_group_block_ring
ARGUMENTS
none
DESCRIPTION
Generates a real power ground group block ring and/or straps based on group block ring
creation results from the create_fp_group_block_ring command. Vias along with wires
are also created at each intersection of two wires (For example, a ring or strap) in opposite
directions.
EXAMPLES
The following example commits the group block ring.
prompt> commit_fp_group_block_ring
SEE ALSO
create_fp_group_block_ring(2)
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commit_fp_plan_groups
Transforms the specified plan groups into soft macros.
SYNTAX
status commit_fp_plan_groups
[-push_down_power_and_ground_straps]
[-new_top_cell new_cell_name]
[plan_groups]
Data Types
new_cell_name
plan_groups
string
collection
ARGUMENTS
-push_down_power_and_ground_straps
Specifies that the command pushes down global power and ground preroutes into the
soft macro and removes them from the top level. This option only pertains to power and
ground nets that are outside the scope of the plan group. Any routing associated with a
power or ground net that is defined within the plan group will be pushed down
automatically along with any other net route objects that are owned by the plan group.
The use of this option is equivalent to the combination of running
commit_fp_plan_groups (without this option) and subsequently running
push_down_fp_objects and specifying routing as the type and specifying a collection of
power and ground nets.
-new_top_cell new_cell_name
Specifies that the command creates a new top cell where the top-level changes occur.
When this option is used, a new top cell is created and the current cell is changed to the
new top cell and plan groups within this new top cell are committed. This is equivalent to
internally calling "current_mw_cel new_cell_name". When the user calls "save_mw_cell
-hier" after commit when using this option, then the new top cell is saved and all soft
macros created by commit are saved also.
plan_groups
Specifies the plan groups that are committed to soft macros.
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If you do not specify this option, all plan groups are committed to soft macros.
DESCRIPTION
This command transforms the specified plan groups into soft macros. For each plan group
processed, the tool creates a soft macro to replace the plan group. The soft macro uses the
plan group's placement. The soft macro's port instances are connected to their
corresponding nets. The plan group's cells are disconnected and deleted, along with the
plan group. On the soft macro level, the cells that correspond to the plan group's
master-level cells are created in the child, placed relative to their master-level placement,
and connected to the corresponding macro-level nets. When used with the "-new_top_cell"
option, the user has the benefit of the changes made to a new top layout cell without
modifying the currently open cell. If a UPF power domain is detected which is defined
completely within the plan group's hierarchical cell instance, and the power domain lists the
hierarchical cell instance as an element of that power domain, all UPF objects related to that
power domain will be pushed into the soft macro and removed from the top cell. Any
embedded UPF power domain and voltage area whose scope is a child of the plan group's
hierarchical cell instance will also be pushed down into the soft macro and removed from the
top cell. All routing associated with plangroup-owned nets (nets in the top cell that are
internal to the plan groups) is automatically removed from the top cell and instantiated in the
soft macro cell, both signal and power/ground (as long as they are owned by the plan
group). Global power and ground nets do not get pushed down automatically, as they are
not "owned" uniquely by the plan group. Such global power and ground nets must be
pushed down after commit using push_down_fp_objects.
Hard move bounds and relative placement groups which overlap the plan group or which
logically are members of the plan group are pushed down to the soft macro and removed
from the top cell.
Multiply-instantiated modules (MIMs) are supported in commit_fp_plan_groups. For plan
groups which represent MIM modules, it is necessary to have uniquified the design prior to
running commit_fp_plan_groups. This should be done using uniquify_fp_mw_cel and the
-store_mim_property option. It is also advisable to run select_mim_master_instance before
running commit_fp_plan_groups in order to identify to commit just which plan group to treat
as the physical master plan group. If this is done, then commit_fp_plan_groups will properly
process the master of the MIM groups of plan groups.
If your design contains scan chains and SCANDEF, please issue check_scan_chain after all
design planning steps and before commit_fp_plan_group.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example commits the specified plan groups to soft macros.
prompt> commit_fp_plan_groups $PG_List
The following example commits all plan groups to soft macros and makes the changes in a
new cell named TOP_NEW.
prompt> commit_fp_plan_groups -new_top_cell TOP_NEW
The following example commits all plan groups in the current design to soft macros and
pushes down the global power and ground net straps.
prompt> commit_fp_plan_groups -push_down_power_and_ground_straps
SEE ALSO
uncommit_fp_soft_macros(2)
push_down_fp_objects(2)
uniquify_fp_mw_cel(2)
select_mim_master_instance(2)
commit_fp_plan_groups
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commit_fp_rail
Commits the power network (power/ground wires and vias) based on power network
synthesis (PNS) results.
SYNTAX
int commit_fp_rail
ARGUMENTS
none
DESCRIPTION
Generates a real power network (power/ground wires and vias) based on PNS results, when
the IR (voltage) drop map meets target IR drop constraints. Power/ground pins might also
be created on the chip boundary.
Multicorner-Multimode Support
This command is not supported in a multi-scenario design flow.
EXAMPLES
The following example commits a real power network after PNS is done.
prompt> commit_fp_rail
SEE ALSO
synthesize_fp_rail(2)
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commit_skew_group
Checks the skew groups defined in the design for common problems that can adversely
impact clock tree synthesis. If no problem is found, the command modifies clock tree
structure to isolate skew groups.
SYNTAX
status commit_skew_group
[-check_only]
ARGUMENTS
-check_only
Causes the command only to check skew groups for common problems but not modifies
the clock tree structure to isolate skew groups.
DESCRIPTION
Use the commit_skew_group command after defining skew groups for a linked design to
check for common problems that adversely impact clock tree synthesis. The following
classes of checks are performed:
CTS-924
CTS-925
CTS-926
CTS-927
CTS-928
CTS-929
CTS-930
CTS-931
pins in a skew group from different master clocks
pins in a skew group with upstream/downstream relation
looping dependencies between skew groups
more than one level of dependency between skew groups
pins in a skew group with no clocks reaching them
skew group spreading across more than one sub-tree
incompatible options
pins beyond exceptions
When commit_skew_group encounters a problem, the tool displays a warning or
information message, which is sometimes followed by additional information to help solve
the problem. Refer to the man page for each message that explains the problem in detail
and shows how to solve it. When no problem is found, the command modifies clock tree
structure to isolate skew groups.
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EXAMPLES
In the following example, the commit_skew_group command checks all skew groups in
the currently linked design and isolates skew groups if no problem is found:
prompt> commit_skew_group
In the following example, the commit_skew_group command checks all skew groups in
the currently linked design. Clock tree structure is not modified to isolate skew groups:
prompt> commit_skew_group -check_only
SEE ALSO
set_skew_group(2)
remove_skew_group(2)
report_skew_group(2)
compile_clock_tree(2)
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compare_collections
Compares the contents of two collections. If the same objects are in both collections, the
result is "0" (like string compare). If they are different, the result is nonzero. The order of the
objects can optionally be considered.
SYNTAX
int compare_collections
[-order_dependent]
collection1
collection2
Data Types
collection1
collection2
collection
collection
ARGUMENTS
-order_dependent
Indicates that the order of the objects is to be considered; that is, the collections are
considered to be different if the objects are ordered differently.
collection1
Specifies the base collection for the comparison. The empty string (the empty collection)
is a legal value for the collection1 argument.
collection2
Specifies the collection with which to compare to collection1. The empty string (the
empty collection) is a legal value for the collection2 argument.
DESCRIPTION
The compare_collections command is used to compare the contents of two collections. By
default, the order of the objects does not matter, so that a collection of cells u1 and u2 is the
same as a collection of the cells u2 and u1. By using the -order_dependent option, the
order of the objects is considered.
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Either or both of the collections can be the empty string (the empty collection). If two empty
collections are compared, the comparison succeeds (that is, compare_collections
considers them identical), and the result is "0".
EXAMPLES
The following example from PrimeTime shows a variety of comparisons. Note that a result
of "0" from compare_collections indicates success. Any other result indicates failure.
prompt> compare_collections [get_cells *] [get_cells *]
0
prompt> set c1 [get_cells {u1 u2}]
{u1 u2}
prompt> set c2 [get_cells {u2 u1}]
{u2 u1}
prompt> set c3 [get_cells {u2 u4 u6}]
{u2 u4 u6}
prompt> compare_collections $c1 $c2
0
prompt> compare_collections $c1 $c2 -order_dependent
-1
prompt> compare_collections $c1 $c3
-1
The following example builds on the previous example by showing how empty collections
are compared.
prompt> set c4 ""
prompt> compare_collections $c1 $c4
-1
prompt> compare_collections $c4 $c4
0
SEE ALSO
collections(2)
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compare_delay_calculation
Compares the Arnoldi-based delays with the Elmore delays in the current design.
SYNTAX
status compare_delay_calculation
[-verbose]
[-ccs]
ARGUMENTS
-verbose
Creates histogram-style reports showing the distribution of the delay differences when
using the Arnoldi-based and Elmore delay models.
-ccs
Creates histogram-style reports showing the delay differences when using Composite
Current Source (CCS) models and nonlinear delay models (NLDM).
DESCRIPTION
The compare_delay_calculation command calculates and compares the timing results of
the current design using the Arnoldi-based and Elmore delay models. This command
reports pin-to-pin delays, max transition, several DRC violations and the worst slack within
each path group for both delay models. In the verbose mode this command creates
histogram-style reports showing the distribution of the Arnoldi-based and Elmore delay
differences on the paths with negative slacks. The distribution of the differences is
represented by the two histograms showing the delay differences in the library units and in
the percentage.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following is an example of an Arnoldi-based and Elmore delay calculation report:
compare_delay_calculation
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prompt> compare_delay_calculation -verbose
Percent of Arnoldi-based delays = 66.67%
+====================+=======================+=======================+
|
|
Elmore
|
Arnoldi
|
|--------------------|-----------------------|-----------------------|
|Max Transition
|
0.195
|
0.521
|
|DRC Violations
|
1
|
1
|
|--------------------|-----------+-----------|-----------+-----------|
|Group
|
WNS
|
TNS
|
WNS
|
TNS
|
|--------------------|-----------|-----------|-----------|-----------|
|CLK1
|
1.71
|
3.96
|
1.46
|
2.64
|
|default
|
0.00
|
0.00
|
0.00
|
0.00
|
+--------------------+-----------+-----------+-----------+-----------+
Histograms for Delays with Negative Slack
+======================+=====================+=====================+
|Difference (%)
|
Count
|
%
|
|----------------------|---------------------|---------------------|
| 0 - 1
|
2
|
8.33
|
| 1 - 5
|
5
|
20.83
|
| 5 - 10
|
3
|
12.50
|
| 10 - 50
|
10
|
41.67
|
| 50 - 100
|
4
|
16.67
|
| 100+
|
0
|
0.00
|
+======================+=====================+=====================+
|Difference(lib_units) |
Count
|
%
|
|----------------------+---------------------+---------------------|
| 0.0 - 0.001
|
0
|
0.00
|
| 0.001- 0.01
|
3
|
12.50
|
| 0.01 - 0.05
|
7
|
29.17
|
| 0.05 - 0.1
|
0
|
0.00
|
| 0.1 - 1.0
|
14
|
58.33
|
| 1.0+
|
0
|
0.00
|
+----------------------+---------------------+---------------------+
Histograms for Slews with Negative Slack
+======================+=====================+=====================+
|Difference (%)
|
Count
|
%
|
|----------------------|---------------------|---------------------|
| 0 - 1
|
0
|
0.00
|
| 1 - 5
|
8
|
33.33
|
| 5 - 10
|
9
|
37.50
|
| 10 - 50
|
3
|
12.50
|
| 50 - 100
|
4
|
16.67
|
| 100+
|
0
|
0.00
|
+======================+=====================+=====================+
|Difference(lib_units) |
Count
|
%
|
|----------------------+---------------------+---------------------|
| 0.0 - 0.001
|
0
|
0.00
|
| 0.001- 0.01
|
12
|
50.00
|
| 0.01 - 0.05
|
0
|
0.00
|
| 0.05 - 0.1
|
0
|
0.00
|
| 0.1 - 1.0
|
12
|
50.00
|
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| 1.0+
|
0
|
0.00
|
+----------------------+---------------------+---------------------+
SEE ALSO
read_parasitics(2)
report_delay_calculation(2)
report_timing(2)
compare_delay_calculation
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compare_lib
Performs a cross-reference check between a technology library and a symbol library or
between a technology library and a physical library.
SYNTAX
status compare_lib
library1
library2
Data Types
library1
library2
string
string
ARGUMENTS
library1
Specifies the name of a technology library.
library2
Specifies the name of a symbol library or physical library to be compared with the
technology library.
DESCRIPTION
The compare_lib command compares the specified libraries consistency. The first library is
a technology library and the second library is a symbol or physical library. For this command
to run successfully, the libraries to be compared must be in the Synopsys internal database
format and must also exist in memory. To compile a library, use the read_lib command. To
load a compiled library, use the read_file command.
The compare_lib command performs the following checks:
•
First, it ensures that each component in the technology library has a corresponding
definition in the symbol or physical library.
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•
Second, it crosschecks the pin names of each component in the technology library
against the pin names defined for its corresponding symbol or physical representation.
•
Third, it ensures that each component in the symbol or physical library has a
corresponding definition in the technology library.
•
Fourth, it crosschecks the pin names of each component in the symbol or physical library
against the pin names defined for its corresponding technology cell.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example compares a technology library and a symbol library:
prompt> compare_lib tech_lib.db sym_lib.sdb
SEE ALSO
read_file(2)
read_lib(2)
report_lib(2)
write_lib(2)
compare_lib
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compare_rc
Compares annotated net capacitance with estimated net capacitance and reports the
percentage differences in a table.
SYNTAX
int compare_rc
[-worst_nets integer_nets]
[-threshold min_float_capacitance]
[-bound max_float_capacitance]
[-min]
[-net net_list]
Data Types
integer_nets
min_float_capacitance
max_float_capacitance
net_list
integer
float
float
list
ARGUMENTS
-worst_nets integer_nets
Specifies the number of worst nets to report based on the difference between the
estimated capacitance and the back-annotated capacitance. The default is 10. If the
specified number is higher than 500 or a negative number, all nets are reported, without
ordering.
-threshold min_float_capacitance
Specifies the minimum back-annotated capacitance considered. Only nets having this
capacitance value or more are reported.
-bound max_float_capacitance
Specifies the maximum back-annotated capacitance considered. Only nets having this
capacitance value or less are reported.
-min
Reports the net capacitance at the minimum condition. By default, the command reports
the net capacitance at the maximum condition.
Chapter 1:
compare_rc
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-net net_list
Compares only those nets in net_list. If you also use either the -threshold or -bound
option, only those nets that meet the criteria in the current instance are used. When you
use the -net option, the command ignores the -worst_nets option.
DESCRIPTION
This command compares the back-annotated capacitance with the estimated capacitance
for nets in the design and reports the percentage difference between the two values for each
net, sorted from most to least difference. It also generates a histogram plot of the
percentage differences.
The worst deviation reported is 200 percent; any deviation above that is truncated to 200
percent.
Before running this command, you must back-annotate the design with capacitance data,
either by running one or more set_load scripts or by reading in a postroute database with
capacitance values set on the nets in the design.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example shows the results of the compare_rc command.
prompt> compare_rc -threshold 0.0001 -worst_nets 25
Loading target library 'ssc_core'
Loading design 'address'
Information: The distance unit in Capacitance and Resistance is 1 micron.
(GR-7)
Information: Library Derived Horizontal Cap : 0.0001 (GR-10)
Information: Library Derived Vertical Cap : 0.00011 (GR-10)
Information: Library Derived Horizontal Res : 0.00016 (GR-10)
Information: Library Derived Vertical Res : 0.00014 (GR-10)
Information: Using region-based R and C coefficients. (GR-13)
----------------------------------------------------------------Net
Estimated
Back-annotated %age-diff
fanout
Cap
Cap
----------------------------------------------------------------n3331 0.00123256
0.00049
151.543
2
n3325 0.000762279
0.00031
145.896
2
N87AC 0.000726195
0.00031
134.256
2
N37AH 0.000726195
0.00031
134.256
2
n5490 0.000822903
0.00036
128.584
2
n4532 0.000701367
0.00031
126.247
2
n4187 0.00105752
0.00049
115.82
2
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n6545
N111AI
N86AH
N63AE
n2000
N125A
N2AD
n6933
n1849
N49AF
n6051
n6718
n3222
n3119
n4704
n3628
n2597
n3191
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0.000873081
0.000820671
0.000812273
0.000812273
0.000814395
0.000812273
0.000812273
0.000983985
0.00115294
0.000781043
0.000797972
0.000957085
0.000949579
0.000775716
0.000777002
0.000777554
0.000775716
0.000777554
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0.00041
0.0004
0.0004
0.0004
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0.0004
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0.00049
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0.00041
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0.0005
0.00041
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105.168
103.068
103.068
103.599
103.068
103.068
100.813
98.7828
95.2607
94.6273
91.4169
89.9158
89.1991
89.5128
89.6473
89.1991
89.6473
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2
2
2
2
2
2
2
2
2
2
2
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2
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--------------****--+----***********----|
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-200 -150 -100 -50
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SEE ALSO
set_load(2)
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compile_clock_tree
Builds a clock tree based on the clock tree definition.
SYNTAX
status compile_clock_tree
[-clock_trees name_or_source_pin_list]
[-config_file_read read_filename]
[-config_file_write write_filename]
[-operating_condition min | max | min_max]
[-high_fanout_net net_or_pin_list
[-sync_phase rise | fall | both]]
[-insert_self_gating]
Data Types
name_or_source_pin_list
net_or_pin_list
list
list
ARGUMENTS
-clock_trees name_or_source_pin_list
Specifies the clock trees to compile.
To specify the clock trees, use either the user-assigned symbolic name or the name of
the source (port or pin) of each clock tree. If you use the source to specify a clock tree,
it must match the full name of the clock tree root pin or port passed to the
set_clock_tree_options command with the -clock_trees option.
By default, the command is applied to all currently-defined clock trees.
-config_file_read read_filename
Specifies the name of the configuration file used to build the clock tree.
To learn the format of the clock tree configuration, build the clock tree, and then write out
the configuration file. You can edit the file to obtain the desired configuration.
If you are already familiar with the format of the clock tree configuration file, you can run
clock tree synthesis with a specified configuration file.
compile_clock_tree
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The configuration can be soft, meaning that only the number of levels is specified, and
the clock tree synthesis engine honors the specification. The number of buffers at each
level is determined by clock tree synthesis.
The configuration can also be hard, meaning that the number of levels and number of
buffers at each level are specified. You can also specify the buffer types.
The clock tree synthesis engine honors all configuration specifications.
-config_file_write write_filename
Writes out the clock tree configuration levels and number of buffers at each level after
clock tree synthesis has been completed.
-operating_condition min | max | min_max
Specifies the operating condition.
The default is max.
-high_fanout_net net_or_pin_list
Inserts a balanced buffer tree for the specified high-fanout signal nets using the same
techniques as in clock tree synthesis. You can specify either the net or the nets' driving
pins in the net_or_pin_list argument.
A common use of this option is to buffer set or reset nets.
-sync_phase rise | fall | both
Balances skew at rise, fall, or both edges.
By default, the tool uses rise in skew calculation.
You can use this option only with the -high_fanout_net option.
-insert_self_gating
Inserts XOR self-gating logic on all clocks during clock tree synthesis prior to clock tree
construction.
For best results, you should provide the clock activity information by reading a SAIF file
with the read_saif command before running the compile_clock_tree command.
If per clock synthesis is required, you should use the -insert_self_gating option only
during the first run of this command.
DESCRIPTION
This command synthesizes a clock tree and updates the design database with the compiled
clock trees.
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Before running the compile_clock_tree command,
•
Use the set_clock_tree_options command to specify clock trees to be synthesized.
•
Use the set_clock_tree_references command to define which clock tree buffers or
inverters can be used for those clocks during clock tree synthesis.
By default, design rule checking (DRC) violations beyond exception pins are fixed at the end
of clock tree synthesis.
Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios. All scenarios
enabled as clock tree synthesis scenarios are activated for clock tree synthesis and are
returned to their current state (active or inactive) after clock tree synthesis.
The clocks that need to be compiled need to be specified as scenario_name@clock_name
in -clock_trees option where,
scenario_name: Scenario with cts_mode set to true.
clock_name: Clock present in that scenario.
EXAMPLES
The following example shows a clock tree with root CLK1 implemented with a set of
specified library references to be used as buffers. Clock CLK1 is compiled and updated in
the design netlist.
prompt> set_clock_tree_options -clock_trees [get_ports CLK1]
prompt> set_clock_tree_references -references {buffer1x buffer2x}
The following example shows a command that performs clock tree synthesis for clock CLK1:
prompt> compile_clock_tree -clock_trees CLK1
The following example shows a command that reports the structural and timing
characteristics of the compiled clock tree:
prompt> report_clock_tree -clock_trees CLK1
The following example shows a command that performs clock tree synthesis for clock CLK1
under scenario scene1:
prompt> compile_clock_tree -clock_trees scene1@CLK1
compile_clock_tree
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SEE ALSO
report_clock_tree(2)
set_clock_tree_options(2)
set_clock_tree_references(2)
read_saif(2)
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compile_clock_tree
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compile_fp_clock_plan
Compiles clock trees inside a plan group and builds clock trees at the top level based on the
plan group clock trees.
SYNTAX
status compile_fp_clock_plan
[-operation_cond min | max | min_max]
[-anchor_only]
[-parallel]
ARGUMENTS
-operation_cond min | max | min_max
Specifies the operating condition for clock tree compilation. By default, the operating
condition is max.
-anchor_only
Inserts anchor cells on the plan group input ports, but does not synthesize the clock
plan. By default, the tool inserts anchor cells on the plan group input ports and
synthesizes the clock plan.
-parallel
Specifies that the tool generates clock trees inside plan groups by using multiple parallel
processes. Multiple parallel processes speed-up the runtime for clock planning.
DESCRIPTION
The compile_fp_clock_plan command performs the following tasks:
1. Inserts anchor cells on the plan group input ports.
2. Generates the clock trees inside each plan group.
3. Defines the input pin of each anchor cell to be a floating pin.
compile_fp_clock_plan
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4. Generates the top-level clock tree.
5. Performs detail routing on the clock interface nets.
The log-files and reports are generated in the clock-planning output directory.
The plan groups to be synthesized must be defined with the set_fp_clock_plan_options
command before using the compile_fp_clock_plan command.
The -parallel option provides an increase in performance in large designs that meet the
following criteria:
1. The design includes more than 3 plan group
2. The design has most of the clock sinks located within the plan groups
3. The design has limited clock dependency between plan groups; only a small number of
clock nets exit the plan group and drive subtrees at the top level or in other plan groups.
The -parallel option is not compatible with designs that contain fully abutted floorplans.
Because parallel generation of a plan group clock tree does not save the plan group clock
trees, the -parallel option is ignored when you specify set_fp_clock_plan_options
-keep_block_tree true.
Multicorner-Multimode Support
This command is not supported in a multi-scenario design flow.
EXAMPLES
In the following example, the CLKBUF12 anchor cell is inserted in all plan groups and the
CLK1 clock net is implemented in all plan groups.
prompt> set_fp_clock_plan_options -clock_nets CLK1
-anchor_cell CLKBUF12
prompt> compile_fp_clock_plan
\
In the following example, the CLKBUF12 anchor cell is inserted in all plan groups and the
CLK1 clock net is implemented in all plan groups by using parallel processing.
prompt> set_fp_clock_plan_options -clock_nets CLK1
-anchor_cell CLKBUF12
prompt> compile_fp_clock_plan -parallel
Chapter 1:
compile_fp_clock_plan
\
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The following command inserts anchor cells for each plan group, but does not perform clock
tree synthesis.
prompt> set_fp_clock_plan_options -clock_nets CLK1 \
-anchor_cell CLKBUF12
prompt> compile_fp_clock_plan -anchor_only
SEE ALSO
set_fp_clock_plan_options(2)
compile_fp_clock_plan
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compile_power_plan
Creates a power and ground network based on the specified power planning strategy and
template.
SYNTAX
status compile_power_plan
[-strategy strategy_name]
[-undo]
[-verbose]
[-write_default_template template_file_name]
[-ignore_design_rules]
[-ring]
Data Types
strategy_name
template_file_name
string
string
ARGUMENTS
-strategy strategy_name
Creates a power network based on the specified strategy only. By default, the tool
creates a power plan using all specified strategies. The -strategy and
-write_default_template options are mutually exclusive.
-undo
Removes the power and ground straps created by the compile_power_plan command.
The compile_power_plan -undo command does not remove the straps created by
other commands. The compile_power_plan -undo command also clears the undo
command stack.
-verbose
Writes out additional debugging information regarding where and why some straps are
cut. This option also prints out additional design and technology related information.
-write_default_template template_file_name
Writes out the default template to the specified file in the current working directory. The
command overwrites the template_file_name file if it exists. The template contains the
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default values used to create a power plan when no power plan template is specified.
You can use this template file as a skeleton to create a new power plan template. No
power plan is generated when you specify the -write_default_template option. The
-write_default_template is mutually exclusive with -strategy options.
-ignore_design_rules
Ignores design rule violations during power plan creation. The command prints error
messages for any shorted or floating wires. You must correct the violations before
creating the power plan. By default, this option is off.
-ring
Creates the power ring for the specified strategy as defined by the
set_power_ring_strategy command. If you specify the compile_power_plan -ring
-write_default_template template.tpl command, the tool writes an example power ring
template to the template.tpl file and does not implement the power rings.
DESCRIPTION
This command creates the power network based on the specified strategy and template.
EXAMPLES
The following example creates a power plan using the strategy example1 only.
prompt> compile_power_plan -strategy example1
SEE ALSO
remove_power_plan_strategy(2)
set_power_plan_strategy(2)
report_power_plan_strategy(2)
compile_power_plan
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compile_premesh_tree
Invokes clock tree synthesis on a net that is driving a clock mesh.
SYNTAX
status compile_premesh_tree
-clock_tree name_or_root_pin
Data Types
name_or_root_pin
string
ARGUMENTS
-clock_tree name_or_root_pin
Specifies the name of the clock tree or the name of the root (a pin, port or net) of the
clock mesh. This is a required option.
DESCRIPTION
This command invokes the compile_clock_tree command to generate a buffer tree with
drivers connecting to a clock mesh. Before running compile_premesh_tree, you must first
create clock mesh wiring grid and add drivers that are connected to the wiring grid. The
inputs of the buffer tree that drives the clock mesh wiring grid are typically connected to the
clock root. The outputs of the buffer tree that drives the clock mesh wiring grid are connected
to the mesh net. These connections must be set up before the command invokes
compile_clock_tree.
The root net might be associated with one or more clocks, but this command processes the
root net as a single electrical signal. Any multiplexing of clocks must be done in the circuitry
that drives the driver pin or port of the root net. This command only generates a buffer tree
and does not generate any multi-input gates for gated clocks or integrated clock gating
(ICG) cells.
See create_clock_mesh for more information on clock net, root net, and mesh net.
Chapter 1:
compile_premesh_tree
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Multicorner-Multimode Support
This command uses information from the clock tree synthesis scenarios.
EXAMPLE
The following command invokes clock tree synthesis on an ideal clock net that was
previously connected to the ideal net clk1.
prompt> compile_premesh_tree -clock_tree [get_pins clk1top/Z]
1
SEE ALSO
create_clock_mesh(2)
add_clock_drivers(2)
route_mesh_net(2)
analyze_subcircuit(2)
compile_clock_tree(2)
compile_premesh_tree
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compress_scenarios
Compresses the original set of scenarios into a smaller subset of scenarios. The constraints
of the smaller subset of scenarios (setup, hold, maximum transition, and leakage) are then
modified to capture violations from scenarios that are not in the subset.
SYNTAX
status compress_scenarios
[-max_compression num_scenarios]
Data Types
num_scenarios
int
ARGUMENTS
-max_compression num_scenarios
Specifies the maximum number of scenarios into which the command compresses the
original set of active scenarios.
If you do not specify this option, at most one setup and one hold scenario is activated for
each mode.
DESCRIPTION
This command compresses the original set of scenarios into a dominant subset. Constraints
of these dominant scenarios are modified to account for violations (as seen by optimization)
unique to the scenarios not in the dominant set. The command deactivates all scenarios that
are not in the compressed subset. It also renames the surviving scenarios to indicate they
have been compressed by modifying their constraints. For example, the FUNC_WC
scenario is renamed to FUNC_WC__z__ by appending the suffix '__z__'.
The command first performs a dominance analysis on the active set of scenarios. For the
dominant set, it identifies the unique timing graph (modes). For each mode, one setup and
one hold scenario is chosen and their constraints are modified to capture the violations from
other scenarios. The compressed scenarios remain active while the others are deactivated.
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To undo the effects of the compression and reactivate the original set of scenarios along
with their original names and constraints, run the uncompress_scenarios command.
This command is supported only by the route_opt core command. Running other core
commands, such as place_opt and clock_opt on compressed scenarios can produce
undesired QoR.
The command returns 1 if it performs compression successfully, and 0 otherwise.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example illustrates how to use scenario compression in the postroute flow.
prompt>
prompt>
prompt>
prompt>
prompt>
prompt>
route_opt -initial_route_only
compress_scenarios -max_compression 4
route_opt -skip_initial_route -power
route_opt -incremental
uncompress_scenarios
report_timing
SEE ALSO
uncompress_scenarios(2)
route_opt(2)
compress_scenarios
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compute_polygons
Returns a list or collection of polygons that exactly cover the region computed by performing
a Boolean operation on the input polygons.
SYNTAX
list compute_polygons
-boolean and | or | not | xor
poly_list1
poly_list2
Data Types
poly_list1
poly_list2
list or collection
list or collection
ARGUMENTS
-boolean and | or | not | xor
Specifies the Boolean operation to perform on the two input polygon lists or collections
to produce the output polygon list or collection.
"and" finds the area occupied by both the first and second input polygon list or collection.
"or" finds the area occupied by either the first or second input polygon list or collection,
or occupied by both.
"not" finds the area occupied by the first input polygon list or collection and not occupied
by the second polygon list or collection.
"xor" finds the area occupied by either the first or second input polygon list or collection,
but not both.
poly_list1
Specifies the first list or collection of input polygons. You can specify a single polygon or
multiple polygons, representing the first argument for the geometric Boolean operation.
To specify a polygon as a list, enter a sequence of X-Y coordinate pairs that represent
the successive vertices of the polygon, using the following format:
{{x1 y1} {x2 y2} ... {xN yN} {x1 y1}}
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The coordinate unit size is specified in the technology file; typically it is microns.
Polygons must be rectilinear, so the X coordinate of each data point must match the X
coordinate of a neighboring data point, and the Y coordinate must match the Y
coordinate of the other neighboring data point. The last point in the list must be the same
as the first.
Instead of specifying lists of coordinates, you can specify a polygon collection. In that
case, the output of the command is also a collection.
poly_list2
Specifies the second list or collection of input polygons. The command performs a
Boolean operation between the first and the second list or collection of polygons.
DESCRIPTION
This command performs a Boolean operation (OR, AND, NOT, or XOR) between two
polygons or between two sets of polygons, specified as lists of vertices or as polygon
collections. It returns the result in the same form as the input polygons, either a list or a
polygon collection. The result can be a single polygon or a set of multiple, disjoint polygons.
Before using this command, the Milkyway design library containing the input polygons must
be open. The input polygons must be rectilinear, consisting of only vertical and horizontal
line segments that meet at right angles.
You can directly pass the output of this command as a parameter directly to another
compute_polygons command, but not to the other polygon commands,
convert_from_polygon, resize_polygon, or get_polygon_area. This is because the
other polygon commands can only take a single polygon as input. Instead, you must use a
Tcl list command such as the foreach or lindex command to extract each polygon from the
returned list, and then pass each polygon to the other polygon command.
To view the coordinates of a polygon collection stored in a variable, use the following
command:
prompt> get_attribute $variable_name coordinate
EXAMPLES
Assume that you have two polygons, A-B-C-D-A and A1-B1-C1-D1-A1, as shown in the
following figure:
A
B
+---------------------+
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The following example performs the Boolean OR operation on these input polygons. The
result is the B-E-B1-C1-D1-F-D-A-B polygon.
prompt> compute_polygons -boolean or \
{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {40.000 20.000} {40.000 0.000} {10.000
0.000}
{10.000 10.000} {0.000 10.000} {0.000 30.000} {30.000 30.000}}
The following figure shows the resulting polygon.
A
B
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C1
The following example performs the Boolean AND operation on the same input polygons.
The result is the A1-E-C-F-A1 polygon.
prompt> compute_polygons -boolean and \
{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{10.000 20.000} {30.000 20.000} {30.000 10.000}
{10.000 10.000} {10.000 20.000}}
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The following figure shows the resulting polygon.
A1
E
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F
C
The following example performs the Boolean NOT operation on these input polygons. The
result is the B-E-A1-F-D-A-B polygon, which is the region covered by the first polygon,
A-B-C-D-A, but not covered by the second polygon, A1-B1-C1-D1-A1.
prompt> compute_polygons -boolean not \
{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {10.000 20.000} {10.000 10.000}
{0.000 10.000} {0.000 30.000} {30.000 30.000}}
The following figure shows the resulting polygon.
A
B
+---------------------+
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A1
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E
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D
F
The following example performs the Boolean XOR operation on these input polygons. The
result is two polygons, B-E-A1-F-D-A-B and B1-C1-D1-F-C-E-B1, which are the areas
covered by either input polygon, but not both.
prompt> compute_polygons -boolean xor \
{{0 30} {30 30} {30 10} {0 10} {0 30}} \
{{10 20} {40 20} {40 0} {10 0} {10 20}}
{{30.000 30.000} {30.000 20.000} {10.000 20.000} {10.000 10.000} {0.000
10.000}
{0.000 30.000} {30.000 30.000}} {{40.000 20.000} {40.000 0.000} {10.000
0.000}
{10.000 10.000} {30.000 10.000} {30.000 20.000} {40.000 20.000}}
compute_polygons
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The following figure shows the resulting polygons, moved apart slightly to clearly show the
disjoint regions.
A
B
+---------------------+
|
|
|
|
|
A1
| E
B1
|
+--------------+ +------+
|
|
E |
|
|
|
|
|
|
|
F
|
|
+------+
+-------------+
|
D
F
|
C
|
|
|
|
|
+--------------------+
D1
C1
The following script demonstrates how to use the output of the compute_polygons
command as input for other polygon commands.
set p1 [convert_to_polygon [get_net_shapes RECTANGLE#123]]
set p2 [convert_to_polygon [get_net_shapes RECTANGLE#456]]
set my_polys [compute_polygons -boolean xor $p1 $p2]
foreach poly $my_polys {
set my_xor_rect [convert_from_polygon $poly]
echo $my_xor_rect
}
The following example shows how to use a polygon collection as input for the
compute_polygons command.
prompt> set p1 [convert_to_polygon [get_net_shapes RECTANGLE#123]
-collection]
prompt> set p2 [convert_to_polygon [get_net_shapes RECTANGLE#456]
-collection]
prompt> set p3 compute_polygons -boolean or $p1 $p2
{Poly1 Poly2}
The following example shows how compute_polygons can accept list of polygons as input.
prompt> compute_polygons -boolean or {{{0 0} {10 0} {10 10} \
{0 10} {0 0}} {{20 0} {30 0} {30 10} {20 10} {20 0}}} \
{{10 0} {20 0} {20 10} {10 10} {10 0}}
{{0.000 10.000} {30.000 10.000} {30.000 0.000} {0.000 0.000} {0.000
10.000}}
Chapter 1:
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SEE ALSO
convert_to_polygon(2)
convert_from_polygon(2)
resize_polygon(2)
compute_polygons
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connect_logic_net
IC Compiler parses, but ignores, this command.
SYNTAX
status connect_logic_net
net_name
[-ports port_list]
Data Types
net_name
port_list
string
list
ARGUMENTS
net_name
Specifies the net name. You must use a simple name.
-ports port_list
Specifies the ports connected to the net. The ports must be on the interface of the active
scope or on the design elements that are located in the active scope and its
descendants.
DESCRIPTION
This command has no function in IC Compiler. It is parsed in the UPF file, but ignored.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
connect_net(2)
create_logic_port(2)
Chapter 1:
connect_logic_net
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create_logic_net(2)
connect_logic_net
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connect_net
Connects the specified net to the specified pins or ports.
SYNTAX
status connect_net
net
object_list
Data Types
net
object_list
string
list
ARGUMENTS
net
Specifies the net to connect. The net must be a scalar (single bit) net, and must exist in
the current design.
object_list
Specifies a list of pins and ports to which the net is to be connected. Pins and ports must
be at the same hierarchical level as the specified net, and must exist in the current
design. If a specified pin or port is already connected, the tool issues an error message.
DESCRIPTION
This command connects a net to the specified pins or ports at the same hierarchical level.
The net can be at any level of hierarchy but the pins or ports must be at the same level. A
net can be connected to many pins or ports; however, you cannot connect a pin or port to
more than one net.
You can use connect_net to connect PG and Tie nets to pins or ports. Only PG nets can be
connected to leaf-level PG pins. PG nets can not be connected to leaf-level signal pins. Tie
nets can not be connected to leaf-level signal output pins. Tie or PG nets can not be
connected to a hierarchical pin that is already connected to a Tie or PG net on the other
hierarchical side.
Chapter 1:
connect_net
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To disconnect objects on a net, use the disconnect_net command.
To display pins and ports on a net, use either the all_connected or get_nets -of $net
command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses connect_net to connect net NET0 to ports A1 and A2 and pin
U1/A. The all_connected command returns the objects connected to net NET0.
prompt> connect_net NET0 [get_ports {A1 A2}]
prompt> connect_net NET0 [get_pins U1/A]
prompt> all_connected NET0
{A1 A2 U1/A}
The following example shows the error message generated when you attempt to connect a
pin or port to more than one net:
prompt> connect_net MY_NET_1 PORT1
Connecting net 'MY_NET_1' to port 'PORT1'.
prompt> connect_net MY_NET_2 PORT1
Error: Object 'PORT1' is already connected to net 'MY_NET_1'.
The following example shows how connect_net is used to connect the U1/MY_NET net to
the U1/MY_PORT port:
prompt> connect_net U1/MY_NET U1/MY_PORT
SEE ALSO
all_connected(2)
create_net(2)
current_design(2)
disconnect_net(2)
remove_net(2)
connect_net
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connect_pin
Connects pins or ports at any level of hierarchy.
SYNTAX
status connect_pin
-from from_object
-to to_list
[-port_name port_name]
[-verbose]
Data Types
from_object
to_list
port_name
collection
collection
string
ARGUMENTS
-from from_object
Specifies the pin or port from which to make the connection. The direction of the pin or
port cannot be inout.
-to to_list
Specifies the pins and ports to which to make the connection. The pins and ports can be
at any level of the hierarchy. The direction of the pins or ports cannot be inout.
-port_name port_name
Specifies the base name to use as the names of ports that are created on subdesigns to
make the connection.
-verbose
Specifies that the tool displays individual netlist operations while making the global
connections.
Chapter 1:
connect_pin
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DESCRIPTION
This command performs global connections between the source object specified in the
-from option and the objects specified in the -to option. The specified pins and ports can be
at any level of hierarchy. The parent design of the pins and ports must be unique.
Leaf-level power and ground pins or hierarchical pins connected to power, ground, or tie
nets on one side of the hierarchy cannot be connected by using the connect_pin command.
While making the global connections, ports and nets are created in the subdesigns, if
needed. Ports in the subdesigns are reused regardless of their names, when the from pin is
already connected to a net. Also, a port in a subdesign is reused if it is unconnected and the
name is as specified by the -port_name option.
Wherever applicable, the name of the net that is created is the name of the connecting port,
as long as there is no net with the same name in that design. If there is an existing net with
the name, the name of the net is generated.
The connect_pin command ensures that multiply-driven nets are not created. The
command does not allow a connection from an output pin to an output pin.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the connect_pin command to connect the U1/Z output pin to
the mid1/bot1/U3/A input pin.
Use the report_net -connections or report_cell -connections command to view the
connections.
prompt> connect_pin -from [get_pins U1/Z] \
-to [get_pins mid1/bot1/U3/A]
prompt> report_net -connections [get_net -of [get_pins U1/Z]]
SEE ALSO
all_connected(2)
connect_net(2)
create_port(2)
report_cell(2)
connect_pin
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report_net(2)
Chapter 1:
connect_pin
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connect_power_switch
Connects the pins of the power switch cells in the design.
SYNTAX
int connect_power_switch
-source object
-port_name port_name
-mode hfn | daisy | fishbone
[-ack_out object]
[-ack_port_name port_name]
[-direction horizontal | vertical]
[-start_point lower_left | upper_left | lower_right | upper_right]
[-verbose]
[-auto]
[-pattern_name pattern_name]
[-pattern_list list_of_patterns]
[-voltage_area list_of_voltage_areas]
[-object_list objects]
[-lib_pin library_pin_names]
Data Types
object
port_name
pattern_name
list_of_patterns
list_of_voltage_areas
objects
library_pin_names
collection
string
string
list
list
collection
string
ARGUMENTS
-source object
Specifies the pin, port or net from which to connect the power switch. The direction of the
pin or port cannot be inout. For pin and net with same name situation, pin takes
precedence over net.
-port_name port_name
Specifies the base name to use as names of switch ports when a new port is created on
the subdesigns to make the connection. It is a required option.
connect_power_switch
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-mode hfn | daisy | fishbone
Specifies the type of switch connections: daisy chain, high fanout or fishbone. This
option is required.
To avoid creating route connections in the orthogonal direction over hard macros during
fishbone mode routing, set the mv_mtcmos_detour_obstruction application variable
to true. When this variable is true, the tool creates additional connection lines in the
primary direction on either side of the hard macro to reduce the routing over the hard
macro and create better quality of results.
-ack_out object
Specifies the pin, port or net that is to be used as acknowledge-out signal. It is optional
and is only allowed with -mode daisy or -mode fishbone. For pin and net with same
name situation, pin takes precedence over net.
-ack_port_name port_name
Specifies the base name to use as names of acknowledge ports when a new port is
created. This is required with the -ack_out option in -mode daisy or -mode fishbone.
-direction horizontal | vertical
Specifies the direction for the daisy mode connections. Requires -mode daisy or -mode
fishbone. It is used only when the tool tries to infer the daisy chained connections based
on the instantiated switch cells. The option can only be used with -mode daisy or -mode
fishbone. This option can also be used to specify the direction of connections for
branches connected to the main trunk in -mode fishbone.
-start_point lower_left | upper_left | lower_right | upper_right
Specifies the starting point for the daisy mode connections. Requires -mode daisy or
-mode fishbone. It is used to infer the startpoint for daisy or fishbone connections. This
is helpful in connecting the source pin to the nearest starting switch cell. For fishbone
connections, this option determines the starting point for the trunk of fishbone
connections. This option can only be used with -direction. This is not a required option.
-verbose
Specifies that the tool displays individual netlist operations while making the global
connections.
-auto
Specifies whether the list of power switch cell specified by -object_list objects is to be
sorted by the tool. You must also specify the -direction option when you use the -auto
option. You can use -start_point to specify more connection options, but it is not
required. For -mode fishbone, the -auto option is not needed and the tool sorts the list
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of power switches specified by -object_list into a fishbone structure. By default, the
ordering is based on the order you specify in objects.
-pattern_name pattern_name
Specifies the user-defined pattern name. pattern_name is used to specify a handle for
connections being done using connect_power_switch. A pattern_name refers to a
collection of switch cells and the mode (hfn or daisy) in which these cells are connected.
These pattern_name handles are used as building blocks for later stage connections.
You can create a connection configuration using the connect_power_switch command
and specify a pattern_name for these connections. At a later stage, you can create
complex connections using these patterns or handles as blocks without referring to
anything inside these patterns. This gives you the flexibility to make second level
connections with these handles. This option can be used for both first-time and
second-level connections. The pattern_name must be unique and is saved in the
database.
-pattern_list list_of_patterns
This option provides an input list of patterns or objects to be connected using the
connect_power_switch command. This list specifies the handles or patterns that are
already created by the user or the tool. These handles or patterns are then connected
again using the connect_power_switch command. The tool internally collects the
associated cells at the head and tail of the pattern specified by list_of_patterns. These
patterns are connected in mode specified by -mode option.
-voltage_area list_of_voltage_areas
Specifies the voltage areas in which to connect power switch cells. The patterns can be
a collection handle of voltage areas or name patterns. The command tries to collect the
switches in the specified voltage area and connect them. If you specify the -object_list
option, the command ignores the switches in the object_list that are not in the specified
voltage areas. Switches are connected in the order the voltage areas are specified by
this option.
-object_list objects
Specifies the ordered list of cells on which to perform the connections. In -mode daisy,
the connections are made in the order in which they are specified. To ignore the ordering
of the objects list and sort the list, use the -auto and -direction options.
-lib_pin library_pin_names
Specifies the list of library input and output pins that should be used in both -mode daisy
and -mode hfn. This is a required option for switch cells that have multiple switch and
acknowledge pins. The command issues an error message if a switch cell with multiple
input or output is used but does not have its library pins specified in this option. This can
be used with both -mode daisy and -mode hfn. For a fine grain macro, you must specify
connect_power_switch
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the library pin name of switch and acknowledge pins even if you have only one switch
pin and one acknowledge pin.
DESCRIPTION
The connect_power_switch command connects power switch cells that are instantiated
and placed in the design. Connection mode and ordering for the switches are specified by
options. The command can identify the switch cells in the design based on Liberty syntax
and can connect them in either high-fanout style or daisy-chain style.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example connects the switches in the daisy-chain mode.
prompt> connect_power_switch \
-source enable \
-port_name enable_va_0 \
-mode daisy \
-direction horizontal \
-voltage_area voltage_area_2
-verbose
1
prompt> connect_power_switch \
-source [get_nets enable] \
-port_name enable_va_0 \
-mode daisy \
-direction horizontal \
-object_list $switch_list1 \
-auto \
-start_point lower_right \
-verbose
1
prompt> connect_power_switch \
-source enable \
-port_name enable_va_0 \
-mode fishbone \
-direction horizontal \
-object_list $switch_list1 \
-auto \
-verbose
1
prompt> connect_power_switch \
-source enable \
-pattern_name HFN1 \
-port_name enable_va_0 \
-mode daisy \
Chapter 1:
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-direction horizontal \
-object_list {Header_switch1 Header_switch100} \
-verbose
1
prompt> connect_power_switch \
-source enable \
-pattern_name HFN2 \
-port_name enable_va_0 \
-mode daisy \
-direction horizontal \
-object_list {Header_switch101 Header_switch200} \
-verbose
1
prompt> connect_power_switch \
-source enable \
-pattern_name DAISY1 \
-port_name enable_va_0 \
-mode daisy \
-direction horizontal \
-pattern_list {HFN1 HFN2} \
-verbose
1
SEE ALSO
create_power_domain(2)
create_voltage_area(2)
mv_mtcmos_detour_obstruction(3)
connect_power_switch
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connect_spare_diode
Uses the spare diode ports found in the design to fix antenna violations.
SYNTAX
status connect_spare_diode
[-exclude_nets collection_of_nets]
[-antenna_check_engine internal | hercules]
[-internal_check_option all | top_layer_only]
[-routing skip | route]
[-distance distance_number]
[-signal_route_options ignore_lower_layers | include_lower_layers |
include_all_lower_layers | advanced]
[-max_ratio max_ratio_number]
Data Types
collection_of_nets
distance_number
max_ratio_number
collection
integer
integer
ARGUMENTS
-exclude_nets collection_of_nets
Specifies a collection of nets that should not be connected to diodes. If you do not
specify this option, all nets will be connected to diodes.
-antenna_check_engine internal | hercules
Specifies either the internal antenna checker or Hercules. The default is internal.
-internal_check_option all | top_layer_only
Specifies to report either all antenna rule violations or only the top-layer antenna
violations. The default is all. This option applies only when -antenna_check_engine
internal is specified.
-routing skip | route
Specifies the extent of the routing process. Using skip stops routing. Using route
invokes the detail router in ECO mode to route diode ports. The default is route.
Chapter 1:
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-distance distance_number
Specifies the maximum distance to search for spare diodes. The default value is 10
times the global route cell size.
-signal_route_options ignore_lower_layers | include_lower_layers |
include_all_lower_layers | advanced
Specifies the HPO signal route options for checking a charge-collecting antenna. The
default is the value of the doAntennaConx detail routing option.
-max_ratio max_ratio_number
Specifies the maximum allowable ratio of wiring area and gate area for checking a
charge-collecting antenna.
DESCRIPTION
This command uses spare diodes in the design to fix antenna violations. First, the tool runs
the internal antenna checker or uses Hercules output to identify antenna violations. For each
antenna violation, this command searches the neighborhood of the antenna for spare
diodes. The number of required diode ports is determined by define_antenna_rule and
define_antenna_layer_rule.
When enough diode ports are found to fix an antenna violation, it sets the net ID of all the
selected diode ports to be the same as the net ID of the antenna to establish the net
connectivity. Finally, you might choose to complete the routing of the connected diode ports.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following is an example of the connect_spare_diode command.
prompt> connect_spare_diode -antenna_check_engine
-internal_check_option top_layer_only\
-signal_route_options include_all_lower_layer\
-max_ratio 1000
internal\
The following is an example of the connect_spare_diode command.
prompt> connect_spare_diode -route skip -distance 10
connect_spare_diode
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SEE ALSO
insert_diode(2)
define_antenna_rule(2)
define_antenna_layer_rule(2)
Chapter 1:
connect_spare_diode
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connect_supply_net
Connects the supply net to specified supply ports and pins.
SYNTAX
status connect_supply_net
supply_net_name
-ports list
[-vct vct_name]
Data Types
supply_net_name
list
vct_name
string
list
string
ARGUMENTS
supply_net_name
Specifies the name of the supply net to be connected, which must be an existing simple
(nonhierarchical) supply net name.
-ports list
Specifies the supply ports or pins that are to be connected with the supply net. Each item
in the list is the hierarchical name of a supply port or pin.
-vct vct_name
Specifies the value conversion table (VCT) to be used in this connection.
The tool supports only the following 14 predefined VCT names: UPF2VHDL_SL ;
UPF_GNDZERO2VHDL_SL ; UPF2SV_LOGIC ; UPF_GNDZERO2SV_LOGIC ;
VHDL_TIED_HI ; SV_TIED_HI ; VHDL_TIED_LO ; SV_TIED_LO ; VHDL_SL2UPF ;
VHDL_SL2UPF_GNDZERO ; SV_LOGIC2UPF ; SV_LOGIC2UPF_GNDZERO ;
SV_LOGIC2UPF_MD ; SV_LOGIC2UPF_GNDZERO_MD.
connect_supply_net
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DESCRIPTION
The connect_supply_net command makes an explicit connection of a supply net to
specified supply ports or pins. It overrides (has higher precedence than) the automatic
connection semantics that might otherwise apply.
If a design element is not connected explicitly to any supply net using the
connect_supply_net command, it shares the primary power or ground supply net with the
power domain to which it belongs.
Before they can be connected, the supply net must be created in the same power domain
as the supply port. The instance that contains the pin must also be in the extent of the same
power domain.
The command can be used to connect a supply net to bias pins. Bias pins that meet
following conditions are supported:
•
The bias pin is from a macro cell
•
The bias pin direction is "input" or "inout"
•
The bias pin physical_connection is "routing_pin"
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example connects a supply net named VSS with the supply port VSS:
prompt>
PD1
prompt>
VSS
prompt>
VSS
prompt>
1
create_power_domain PD1 -elements INST_1
create_supply_net VSS -domain PD1
create_supply_port VSS -domain PD1
connect_supply_net VSS -ports VSS
The following example shows how to connect a supply set with a supply port:
prompt> connect_supply_net sset.power -ports VDD
1
prompt> connect_supply_net sset.ground -ports VSS
1
Chapter 1:
connect_supply_net
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Version L-2016.03
SEE ALSO
create_supply_net(2)
report_supply_net(2)
connect_supply_net
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connect_tie_cells
Instantiates tie-high and tie-low cells and connects them to the specified cell ports.
SYNTAX
status connect_tie_cells
-objects {object_coll}
-obj_type port_inst | cell_inst | lib_cell
[-tie_high_lib_cell lib_cell -tie_low_lib_cell lib_cell]
[-tie_highlow_lib_cell lib_cell
-tie_high_port_name port -tie_low_port_name port]
[-max_fanout number]
[-max_wirelength number]
[-incremental true | false]
Data Types
object_coll
lib_cell
port
number
collection
string
string
integer
ARGUMENTS
-objects {object_coll}
Specifies the objects from which the tool infers the ports to which the tie-high and tie-low
cells are connected. The objects can be cell instances, port instances, or reference cells.
This is a required option.
-obj_type port_inst | cell_inst | lib_cell
Identifies the type of object specified in the -objects option.
This is a required option.
-tie_high_lib_cell lib_cell
Specifies the reference cell used to instantiate the tie-high cells. The tool determines the
number of tie-high cells to instantiate.
If you use this option, you must also use the -tie_low_lib_cell option.
Chapter 1:
connect_tie_cells
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-tie_low_lib_cell lib_cell
Specifies the reference cell used to instantiate the tie-low cells. The tool determines the
number of tie-low cells to instantiate.
If you use this option, you must also use the -tie_high_lib_cell option.
-tie_highlow_lib_cell lib_cell
Specifies the reference cell used to instantiate the tie-highlow cells. The tool determines
the number of tie-highlow cells to instantiate.
If you use this option, you must also use the -tie_high_port_name and
-tie_low_port_name options.
-tie_high_port_name port
Specifies the name of the port that is logic high on the tie-highlow cell.
This option is required if you use the -tie_highlow_lib_cell option.
-tie_low_port_name port
Specifies the name of the port that is logic low on the tie-highlow cell.
This option is required if you use the -tie_highlow_lib_cell option.
-max_fanout number
Specifies the maximum number of ports that can be driven by a single tie-high or tie-low
cell.
If you do not specify this option, the maximum fanout is 8.
-max_wirelength number
Specifies the maximum Manhattan wire length in microns from a tie-high or tie-low cell
to each driven cell port.
If you do not specify this option, the maximum wire length is 100.
-incremental true | false
Specifies whether to run in incremental mode.
By default (false), the command removes all existing tie cells of the specified ports. In
incremental mode, existing tie cells that satisfy the wire length and fanout constraints are
not removed. This provides minimum disruption to the existing placement and routing.
connect_tie_cells
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DESCRIPTION
This command specifies the cell ports to which to connect to tie-high and tie-low cells. It
instantiates the tie-high and tie-low cells and makes the necessary connections. Before you
run this command, the design must be fully placed and connected to power and ground.
A tie-high cell is a special standard cell whose output pin is always at logic high. A tie-low
cell is a special standard cell whose output pin is always at logic low. A tie-highlow cell is a
combination cell with two output pins, one at logic high and the other at logic low. In some
designs, unused input pins cannot be tied directly to the power or ground net and tie-high,
tie-low, or tie-highlow cells must be used.
You can specify the library reference cells for the tie-off cells in the following ways:
•
You can specify the library reference cells associated with the tie-high and tie-low cells.
In this case, the ports that are tied off to power or ground are connected to the specified
tie cells. Note that you must specify both the tie-high and tie-low library reference cells.
•
You can specify the library reference cell of a tie-highlow cell.
If you specify a two-pin tie-highlow cell, you must also specify the port names of the pins
that are logic high and low. In this case, the ports tied off to power or ground are
connected to the high or low port, respectively, of the tie-highlow cell.
•
You can specify both one output tie-high and tie-low library reference cells and a two
output tie-highlow library reference cell.
In this case, in regions of the chip where ports are tied off to both power and ground, the
tool uses tie-highlow cells; otherwise, the tool uses tie-high or tie-low cells.
The cell ports to connect to the tie-high and tie-low cells are inferred from the specified list
of cell instances, port instances, or reference cells.
You can specify maximum fanout (the maximum number of ports that can be driven by a
single tie-high or tie-low cell) and maximum wire length (the maximum Manhattan wire
length between a tie-high or tie-low cell and a driven port) constraints.
The command can also be run in incremental mode.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLE
In the following example, all input ports of the BONUS_SET_*/* cells that are tied off to
power or ground are connected to new tie-high and tie-low cells.
Chapter 1:
connect_tie_cells
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prompt> connect_tie_cells -objects [get_cells "BONUS_SET_*/*"] \
-obj_type cell_inst \
-tie_high_lib_cell TIEH -tie_low_lib_cell TIEL
In the following example, all input ports named A of the BONUS_SET_*/* cells that are tied
off to power or ground are connected to new or existing tie-high and tie-low cells that are at
most 64 microns of Manhattan distance away.
prompt> connect_tie_cells -objects {"BONUS_SET_*/*/A"} \
-obj_type port_inst \
-tie_high_lib_cell TIEH -tie_low_lib_cell TIEL \
-max_wirelength 64 -incremental true
In the following example, all input ports of the BONUS_SET_*/* cells that are tied off to
power or ground are connected to new tie-highlow cells. Ports that are tied off to power are
connected to the OUT1 port on the TIEHL cell. Ports that are connected to ground are
connected to the OUT0 port on the TIEHL cell.
prompt> connect_tie_cells -objects [get_cells "BONUS_SET_*/*"] \
-obj_type cell_inst \
-tie_highlow_lib_cell TIEHL \
-tie_high_port_name OUT1 \
-tie_low_port_name OUT0
connect_tie_cells
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continue
Begins the next loop iteration.
SYNTAX
int continue
ARGUMENTS
None
DESCRIPTION
This command begins the next iteration of the innermost loop. To immediately reevaluate
the condition of a while loop, use the continue command, rather than executing the
remaining statements to the end.
The continue command always returns the integer 1, indicating successful operation. A
syntax error is reported if the continue command is used outside a loop structure.
EXAMPLES
The following example plots the first 10 sheets of the current design, except for sheet 5:
set p 0
while {$p <= 10} {
if {$p % 2} {
incr p
continue
}
echo "$p squared is: [expr $p * $p]"; incr p
SEE ALSO
break(2)
while(2)
Chapter 1:
continue
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convert_from_polygon
Converts each polygon into a list or collection of mutually exclusive rectangles.
SYNTAX
list convert_from_polygon
polygons
[-format polygon | rectangle]
Data Types
polygons
polygon list or collection
ARGUMENTS
polygons
Specifies the list or collection of input polygons to be decomposed into rectangles. You
can specify a single polygon or multiple polygons.
To specify a polygon as a list, enter a sequence of X-Y coordinate pairs that represent
the successive vertices of the polygon, using the following format:
{{x1 y1} {x2 y2} ... {xN yN} {x1 y1}}
The coordinate unit size is specified in the technology file; typically it is microns.
Polygons must be rectilinear, so the X coordinate of each data point must match the X
coordinate of a neighboring data point, and the Y coordinate must match the Y
coordinate of the other neighboring data point. The last point in the list must be the same
as the first.
Instead of specifying lists of coordinates, you can specify a polygon collection. In that
case, the output of the command is also a collection.
-format polygon | rectangle
Specifies the output format of the resulting rectangles.
By default, each resulting rectangle is represented as two data points at opposite
corners of the rectangle:
{x1 y1} {x2 y2}
convert_from_polygon
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If you specify -format polygon, each resulting rectangle is represented in polygon
format, using five data points for the round trip around the perimeter of the rectangle:
{{x1 y1} {x2 y1} {x2 y2} {x1 y2} {x1 y1}}
DESCRIPTION
This command converts a polygon into a list of mutually exclusive rectangles. The returned
rectangles are represented as a list of coordinates or a collection. Before using this
command, the Milkyway design library must be open.
Note that this command might return a list of disjoint polygons. Because the polygon
commands take a single polygon as input, you cannot directly pass the result as a
parameter to another polygon command. Instead, you must use a Tcl list command, such as
the foreach or lindex command, to extract each polygon from the returned list, and then
pass each polygon to the polygon command.
EXAMPLES
The following example converts the A-B-C-D-E-F-G-H-A polygon to three rectangles,
K-F-G-H, E-I-C-D, and A-B-I-K.
A
B
+---------------------+
|
|
|
|
|
|
K+- - - +-------+ - - -+I
|
|F
E|
|
|
|
|
|
|
|
|
|
+------+
+------+
H
G
D
C
prompt> convert_from_polygon {{0 20} {30 20} {30 0} \
{20 0} {20 10} {10 10} {10 0} {0 0} {0 20}}
{{0.000 0.000} {10.000 10.000}} {{20.000 0.000}
{30.000 10.000}} {{0.000 10.000} {30.000 20.000}}
The following example shows how to use a polygon collection as input.
prompt> set p1 [convert_to_polygon [get_net_shapes RECTANGLE#*]
-collection]
{Poly1}
prompt> convert_from_polygon $p1 -format polygon
{Poly2 Poly3 Poly4}
Chapter 1:
convert_from_polygon
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SEE ALSO
convert_to_polygon(2)
compute_polygons(2)
resize_polygon(2)
convert_from_polygon
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convert_mw_lib
Converts a Milkyway library's cell data.
SYNTAX
status convert_mw_lib
mw_lib
[-cell_name cell_name]
[-all]
[-check_only]
Data Types
mw_lib
cell_name
string
string
ARGUMENTS
mw_lib
Specifies the library containing the cells to be converted.
-cell_name cell_name
Specifies the name of cell to be converted. If the option is specified, all child soft macro
cells referred by the current cell will be converted along with the current cell.
-all
If the option is specified, all cells under the design lib will be converted.
-check_only
This option lists the names of the cells that need to be converted, together with their
library names, without actually performing the conversion. This option can be used only
with the -cell_name or -all option. The list generated by the -check_only option includes
cells that belong to reference libraries. To convert such cells, you need to apply the
convert_mw_lib command directly to the library containing the cells, because the
convert_mw_lib command only converts cells contained in the specified library, not cells
in reference libraries.
Chapter 1:
convert_mw_lib
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DESCRIPTION
This command converts cells of the specified library. It does not convert cells in the
reference libraries.
If a cell was created by a prior release, it is old and must be updated before it is opened by
the current release. Once updated, the cells may be used by any tool from the current
release.
It is recommended to convert all cells once using this convert_mw_lib command. This
minimizes run-time and memory consumption for conversion and would have less impact to
the ICC flow. If an old cell is not converted, the open_mw_cel command will open the old cell
and automatically convert it in memory. If the user does not save the cell, the cell will be
automatically converted again during the next open_mw_cel command call.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
convert_mw_lib foo_library -cell_name top
1
SEE ALSO
open_mw_cel(2)
save_mw_cel(2)
convert_mw_lib
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convert_to_polygon
Returns a polygon list or collection for the specified objects.
SYNTAX
list convert_to_polygon
[-quiet]
[-collection]
object_spec
Data Types
object_spec
object collection or polygon list
ARGUMENTS
-quiet
Suppresses the reporting of error and warning messages.
-collection
Returns a polygon collection.
By default, the command returns a list.
object_spec
Specifies the input object collection or polygon list. If you specify an object collection, the
object class must be cell, shape, placement blockage, or route guide. If you specify a list
of polygon vertex coordinate pairs, the command converts the list to a polygon
collection.
DESCRIPTION
This command returns polygons calculated from the input objects. By default, the returned
polygon is represented as a list of polygon vertex coordinates. To return a polygon collection
instead, use the -collection option. polygon collection
Chapter 1:
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EXAMPLES
The following example returns a polygon list from the RECTANGLE#123 net shape.
prompt> convert_to_polygon [get_net_shapes RECTANGLE#123]
{{99.490 111.340} {117.590 111.340} {117.590 112.620} {99.490 112.62}
{99.490 111.340}}
The following example returns a polygon collection from all the net shapes in the current
design.
prompt> convert_to_polygon [get_net_shapes] -collection
{Poly1 Poly2 Poly3 Poly4 Poly5 Poly6 Poly7 Poly8}
The following example converts a polygon list into a polygon collection.
prompt> convert_to_polygon {{16 26} {198 26} {198 16} {16 16} {16 26}}
{Poly9}
SEE ALSO
convert_from_polygon(2)
compute_polygons(2)
resize_polygon(2)
convert_to_polygon
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convert_wire_ends
Converts the currently opened cell's signal wire ends.
SYNTAX
status_value convert_wire_ends
ARGUMENTS
no arguments
DESCRIPTION
This command searches the currently opened cell for signal wires having zero length
extensions. Each of these wires is converted into a wire having half width extensions. If the
wire is not convertible (i.e., the wire length is less than the width), the wire is deleted.
This command only modifies wires having a signal route type.
The command returns a status indicating success or failure.
EXAMPLES
The following example converts the "top" cell's zero length extension wires into half width
extension wires.
prompt > open_mw_lib myLib
{myLib}
prompt > open_mw_cel top
{top}
prompt > convert_wire_ends
Warning: Removed net shape (VWIRE#1796726). (MWUI-140)
Warning: Removed net shape (VWIRE#1687148). (MWUI-140)
Warning: Removed net shape (VWIRE#1687150). (MWUI-140)
1
prompt > save_mw_cel
Information: Saved design named top.CEL;1. (UIG-5)
1
prompt > close_mw_cel
1
prompt > close_mw_lib
Chapter 1:
convert_wire_ends
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convert_wire_ends
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convert_wire_to_pin
Converts wires to pins for either all nets or specified nets in the selected wire set.
SYNTAX
status convert_wire_to_pin
[-net_names net_names]
objects
Data Types
net_names
objects
collection
collection
ARGUMENTS
-net_names net_names
Specifies net names to filter selected wires. The net_names argument is a collection of
net names.
objects
Specifies a selected wire set as a collection of wires.
DESCRIPTION
This command searches the specified nets and converts the selected wires of the nets into
pins. You must manually select the wires by GUI first.
The successive command create_macro_fram can extract those detailed pins converted
from wires in the FRAM view. If the net_names argument is NULL, all selected wires are
converted to their corresponding pins. Otherwise, only the selected wires that belong to the
specified net_names are converted to pins.
NOTES
Only the wire section connecting to a pin is converted to a pin. If no corresponding pin of
selected wires exists in the top cell, nothing is converted. That is, no new pin is created in
the top cell (no net list changes).
Chapter 1:
convert_wire_to_pin
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example converts user-selected wires of the nets named OR and SCEN) to
pins.
prompt> convert_wire_to_pin -net_names {OR SCEN} [get_selection]
SEE ALSO
create_macro_fram(2)
get_selection(2)
convert_wire_to_pin
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copy_collection
Duplicates the contents of a collection, resulting in a new collection. The base collection
remains unchanged.
SYNTAX
collection copy_collection
collection1
Data Types
collection1
collection
ARGUMENTS
collection1
Specifies the collection to be copied. If an empty string is used for the collection1
argument, the command returns the empty string (a copy of the empty collection is an
empty collection).
DESCRIPTION
This command is no longer needed and is provided only to make old scripts work without
modification.
EXAMPLES
The following example from PrimeTime shows the result of copying a collection.
Functionally, it is not much different that having multiple references to the same collection,
except it is slower.
prompt>
{U1 U10
prompt>
{U1 U10
prompt>
prompt>
Chapter 1:
copy_collection
set c1 [get_cells "U1*"]
U11 U12}
set c2 [copy_collection $c1]
U11 U12}
unset c1
query_objects $c2
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{U1 U10 U11 U12}
SEE ALSO
collections(2)
copy_collection
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copy_floorplan
Copies floorplan data from a specified design to the current design in a Milkyway design
library.
SYNTAX
status copy_floorplan
[-library design_library_name]
-from design_name
[-macro]
[-filler]
[-pad]
[-power_plan]
[-verbose]
[-incremental]
Data Types
design_library_name
design_name
string
string
ARGUMENTS
-library design_library_name
Specifies the name of the Milkyway design library for the source and destination
designs. If this option is not specified, the current open library is used. If no library is
currently open, this option is required.
-from design_name
Specifies the name of the source design. The source design must be specified,
otherwise, the copy_floorplan command will not execute.
-macro
Copy placement of macros. Placement here includes position, orientation, fixed or
placed status and so on.
-filler
Copy placement of filler cells. Placement here includes position, orientation, fixed or
placed status and so on.
Chapter 1:
copy_floorplan
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-pad
Copy placement of I/O pads, corner pads and flip chip pads. Placement here includes
position, orientation, fixed or placed status and so on.
-power_plan
Copy power net connections and routing.
-verbose
Print detailed message and statistics on data copied and not copied.
-incremental
Do not update the existing named objects in the destination design. Can be combined
with all other options.
DESCRIPTION
The copy_floorplan command copies floorplan data from a specified design to the current
design in a Milkyway design library, and the current design must be opened before the
command is executed. Floorplan data includes die area, core area, rows, wire tracks,
placement and routing obstructions, bounds, groups and regions, power domains and
voltage areas, the XY coordinates of cell instances and top level pins, routes, and power net
connections.
Use this command after floorplanning is done, but before standard cell placement and
routing is done, which is an early stage in an implementation flow.
The source design and the current design are Milkyway cells and must exist in the same
design library. And you must specify the -from option to indicate the source design. If you do
not specify the type of data to copy (-macro, -filler, -pad, or -power), the command copies
all existing floorplan data from the source design to the current design. Otherwise, only the
data specified by the options is copied.
The command does not do a complete netlist comparison. It goes through the netlist of the
source design and looks for the objects by name in the destination design. By default, if a
cell instance or net does not exist in the destination design, it is skipped.
The command returns 1 on success, 0 on failure.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
copy_floorplan
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EXAMPLES
The following example copies the macro and pad placement information from design A to
the current design in design library mwlib.
prompt> copy_floorplan -library mwlib -from A -macro -pad
The following example copies all floorplan information from design A to the current open
design, printing detailed information about the copy process.
prompt> copy_floorplan -from A -verbose
SEE ALSO
write_floorplan(2)
Chapter 1:
copy_floorplan
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copy_mim
Copies cell placement, blockages, or shape from one multiply instantiated module (MIM)
plan group to others in same group.
SYNTAX
status copy_mim
[-type placement | blockage]
[-restore_placement]
collection
Data Types
collection
list containing one plan group
ARGUMENTS
-type placement | blockage
Identifies the type of copy to perform. The placement argument copies the cell
placement of the given MIM to all other MIMs in the same group. The blockage
argument copies all types of placement blockages overlapping the given MIM to all other
MIMs in the same group. The default is placement.
-restore_placement
Restores the placement of cells in the MIM group of the MIM specified by placement.
This option undoes the result of the previously-executed copy_mim -type placement
command. This option restores the placement, even if you exit and restart the tool,
because the original placement before the copy_mim -type placement is saved to the
database.
collection
Specifies a collection containing one MIM plan group. This is the source MIM to copy to
all other MIMs in the same group.
copy_mim
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DESCRIPTION
This command performs various manipulations on MIMs. MIMs are modules that have the
same reference cell. A set of these modules is called an MIM group. A design can have
more than one MIM group. For example, if modules A1 and A2 have reference A and
modules B1 and B2 have reference B, they form two MIM groups.
The command performs manipulations during the virtual flat stage. This is the period when
MIMs are physically represented in the design as plan groups. You can use this command
to create MIMs with the same cell placement, blockages, and shapes.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example copies the placement of a MIM plan group, M1, to MIM plan groups
M2 and M3.
prompt> copy_mim -type placement M1
The following example copies placement blockages in M1 to M2 and M3.
prompt> copy_mim -type blockage M1
The following example undoes the placement of M1, M2, and M3. Placement is restored to
the state before the copy_mim -type placement M1 command.
prompt> copy_mim -restore_placement M1
Note that this command undoes only the placement, not the blockage copy.
SEE ALSO
flip_mim(2)
report_mim(2)
Chapter 1:
copy_mim
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copy_mw_cel
Copies Milkyway designs from a source design library to a target design library.
SYNTAX
status copy_mw_cel
-from source_mw_cel_name
[-to target_mw_cel_name]
[-from_library source_library_name]
[-to_library target_library_name]
[-hierarchy]
[-check_only]
[-overwrite]
Data Types
source_mw_cel_name
target_mw_cel_name
source_library_name
target_library_name
collection
string
string
string
ARGUMENTS
-from source_mw_cel_name
Specifies the Milkyway designs to be copied. If you use the -hierarchy option, you can
specify only a single design. If you do not use the -hierarchy option, you can specify a
single design or multiple designs.
You can specify a Milkyway design by name, pattern, or collection. For example, "top"
matches a Milkyway design named "top" in the current design library; "top*" matches all
Milkyway designs whose names start with "top"; and "*" specifies all Milkyway designs
in the current design library.
If you specify a version number in the source file name, only that version of the Milkyway
design is copied. If you do not specify a version number in the source file name, the
latest version of the Milkyway design is copied.
-to target_mw_cel_name
Specifies a new name for the target Milkyway design. By default, the command copies
the design to the target library without changing its name.
copy_mw_cel
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If you specify multiple source Milkyway designs in the -from option, the tool assumes
that you want to copy them without changing the names, so it ignores this option.
The -to and -hierarchy options are mutually exclusive.
-from_library source_library_name
Specifies the design library that contains the source Milkyway designs. If you do not
specify this option, the tool uses the current design library as the source library.
-to_library target_library_name
Specifies the target library to which the Milkyway designs are copied. Generally, you do
not need to open the target library before running this command. If you do not specify
this option, the tool uses the current design library as the target library.
If you use both the -to_library option and the -hierarchy option, and the specified target
design library does not exist, the tool creates a new library and copies the hierarchical
design into it.
-hierarchy
Copies the source Milkyway design and its subdesigns to the target design library.
Without this option, the command copies only the specified design, not its subdesigns.
-check_only
Reports the list of Milkyway designs, views, and versions but does not copy the designs.
This option is valid only when used with the -hierarchy option.
-overwrite
Overwrites the target Milkyway design when copying. This option cannot be used with
the -hierarchy option.
DESCRIPTION
This command copies the specified Milkyway designs from the source design library to the
target design library. You must have write permission for the target design library. Only read
permission is required for the source design library.
You can use the -hierarchy option to copy both the top-level design and its subdesigns.
Subdesigns that are instantiated from the reference library stay in the reference library and
are not copied to the target design library. The target library sets the reference path to those
reference libraries. The latest version of any open and unsaved Milkyway design in the
hierarchical tree is saved from memory into the target design library. If the open Milkyway
design is not the latest version, the Milkyway design is copied from disk instead of memory.
If the Milkyway design is not open, the Milkyway design on disk is copied.
Chapter 1:
copy_mw_cel
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The copied Milkyway designs include all information from the original Milkyway design. The
copied Milkyway designs have their versions set to 1 if the target library is a new library. If
the target library is not a new library, the version of the copied Milkyway design is
incremented by 1 from the latest version before the copy, unless you use the -overwrite
option.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example copies all Milkyway designs from the current library to another library
named new_lib.
prompt> copy_mw_cel -from * -to_library new_lib
1
The following example copies the design named ORCA and all of its subdesigns from the
current library to a library named lib1.
prompt> copy_mw_cel -hierarchy -to_library lib1 -from ORCA
Copied Library Files
From: /orca/orca_lib
To: lib1
Copied Cells
From: /orca/orca_lib
To: lib1
Copying cell: ORCA.CEL;1
Copying cell: BLENDER_2;
1
SEE ALSO
close_mw_cel(2)
create_mw_cel(2)
current_mw_cel(2)
get_mw_cels(2)
open_mw_cel(2)
remove_mw_cel(2)
rename_mw_cel(2)
mw_support_hier_fill_view(3)
copy_mw_cel
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copy_mw_lib
Copies a Milkyway library to another location.
SYNTAX
status copy_mw_lib
[-from mw_lib]
-to lib_name
Data Types
mw_lib
lib_name
string
string
ARGUMENTS
-from mw_lib
Specifies the name of the source Milkyway library to be copied. The mw_lib value can
be a library name or a collection of libraries. By default, the command uses the current
Milkyway library.
-to lib_name
Specifies the destination Milkyway library name.
DESCRIPTION
The copy_mw_lib command copies a Milkyway library to another location. It returns a
status indicating success or failure.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example copies a Milkyway library design to another location:
Chapter 1:
copy_mw_lib
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prompt> copy_mw_lib -from design -to design.bak
1
SEE ALSO
rename_mw_lib(2)
copy_mw_lib
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copy_objects
Copies one or more objects.
SYNTAX
collection copy_objects
[{-delta vector | -to point}]
[-x_times integer]
[-y_times integer]
[-x_pitch float]
[-y_pitch float]
[-use_same_net]
objects
Data Types
objects
collection
ARGUMENTS
-delta vector
Specifies the horizontal and vertical displacement, in database units, from the locations
of the original (specified) objects to the locations of their copies.
This option cannot be combined with the -to option.
If neither the -delta option nor the -to option is specified then a delta of (0,0) is assumed
i.e. the first copied object will be coincident to the original.
Units are in microns.
-to point
Specifies the location, in absolute coordinates, for the copies of the specified objects.
This option cannot be combined with the -delta option.
Units are in microns.
-x_times integer
Creates multiple copies of each specified object, and specifies the number of copies in
the x-direction.
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Use the -x_pitch option to optionally specify the distance between each copied object. If
the -x_pitch option is not specified then the pitch is assumed to be the width of the
object.
If this is not specified then one copy is assumed.
-y_times integer
Creates multiple copies of each specified object, and specifies the number of copies in
the y-direction.
Use the -y_pitch option to optionally specify the distance between each copied object. If
the -y_pitch option is not specified then the pitch is assumed to be the height of the
object.
If this is not specified then one copy is assumed.
-x_pitch float
Specifies the distance in the x-direction between adjacent copies of the same object.
This option must only be specified in conjunction with the -x_times option.
Units are in microns.
-y_pitch float
Specifies the distance in the y-direction between adjacent copies of the same object.
This option must only be specified in conjunction with the -y_times option.
Units are in microns.
-use_same_net
Controls whether the copies are assigned the same net connections as the original
objects.
If this option is not specified, the copies are unconnected.
This option applies only to objects that can have net connections.
objects
Specifies the objects to be copied.
DESCRIPTION
This command copies one or more objects and returns a collection of the copies.
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You can place the copies at a specific location or specify a delta from the location of the
original object.
You can create multiple copies of each specified object, and you can specify the pitch
between adjacent copies of the same object.
All the attributes of an original object are applied to its copies, with the following exceptions:
•
The database ID for a copy is different from the ID for the original object because each
object must have a unique database ID.
•
The copy of an object is not connected to a net by default. If you specify the
-use_same_net option, the copy is connected to the same net as the original object.
•
The copy of an object is placed at a different location from the location of the original
object if you specify either the -delta option or the -to option.
Note that if object snapping is enabled, each copy is snapped to its new location
automatically based on the global snap settings.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example copies the selected object and places the copy 100 database units
to the right and 200 database units above the original object:
prompt> copy_objects -delta {100 200} [get_selection]
The following example creates 8 copies of the selected object placed in a 2 by 4 grid with
origin at (100,100) with no space between the objects.
prompt> copy_objects -to {100 100} [get_selection] -x_times 2 -y_times 4
SEE ALSO
move_objects(2)
remove_objects(2)
resize_objects(2)
rotate_objects(2)
align_objects(2)
distribute_objects(2)
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expand_objects(2)
flip_objects(2)
set_object_snap_type(2)
get_object_snap_type(2)
copy_objects
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count_drc_violations
Returns the number of design rule constraint (DRC) violations.
SYNTAX
int count_drc_violations
[-intersect bbox]
[-ignoring bbox]
[-include_types types]
[-ignore_types types]
[-include_layers layers]
[-ignore_layers layers]
[-use_new_drc]
[-drc_cell_name drc_cell_name]
[-return_error_type]
[-verbose]
Data Types
bbox
types
layers
drc_cell_name
bounding box
string or list of strings
string or list of strings
string
ARGUMENTS
-intersect bbox
Include DRC violations within or touching this bounding box.
-ignoring bbox
Ignore DRC violations completely within this bounding box.
-include_types types
Include DRC violations of these types. Use -verbose to find type names.
-ignore_types types
Ignore DRC violations of these types. Use -verbose to find type names.
-include_layers layers
Include DRC violations on these layers. Use -verbose to find layer names.
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-ignore_layers layers
Ignore DRC violations on these layers. Use -verbose to find layer names.
-use_new_drc
Use the geNewdrc DRC error cell. This is already the default.
-drc_cell_name drc_cell_name
Specify a particular DRC error cell name. Use topCellName for the verify_route results.
Use topCellName_aDRC.err for the verify_drc results.
-return_error_type
Returns the name of the error type found (if there are multiple errors , it returns the first
one).
-verbose
Report all the DRC violations in full form.
DESCRIPTION
This command reports the number of DRC errors of the specified types, on the specified
layers, within the given domain. It also lists the DRC error if -verbose is selected.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
prompt> count_drc_violation -verbose
SEE ALSO
verify_route(2)
count_drc_violations
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cputime
Reports the CPU time in seconds.
SYNTAX
status cputime
[-all]
[-verbose]
ARGUMENTS
-all
Reports the total CPU time of the main process and its child processes. This is the
default; this option is kept for backward compatibility.
-verbose
Reports in detail the CPU time and elapsed (wall-clock) time of the main process and
each child process, including placement, extraction, and routing.
DESCRIPTION
The cputime command reports the CPU time in seconds. If you specify -verbose, it reports
the CPU time and elapsed (wall-clock) time for the main process and each child process.
The runtime numbers are collected from the operating system.
When you use the set_host_options command, the tool runs multiple threads. Currently
the operating system measures the CPU time by adding the usage for all threads. It does
not take into account parallelization of the threads. This means that the report might show a
larger CPU time than elapsed time when you use set_host_options. The elapsed time
(wall-clock time) is more appropriate for measuring multicore runtime.
The elapsed time depends on many external factors and can vary for every session. It
depends on factors such as the I/O traffic, the network traffic, RAM and swap usage, and the
other processes running on the same machine. When the elapsed time is much longer than
the CPU time, it might point out an inefficiency of the computing environment, such as
insufficient memory, too many processes running on the same machine, or a slow network.
The only way to make the elapsed time close to the CPU time is to run only one session on
a machine with enough RAM and using the local disk.
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EXAMPLES
The following example shows the default command output:
prompt> cputime
1202
The following example shows the output when using the -verbose option:
prompt> cputime -verbose
Main process CPU: 1202 s (0.33 hr) Elapse: 1800 s (0.50 hr)
Child "placement" called 3 times, total CPU: 200 s (0.06 hr)
Elapse: 250 s (0.07 hr)
Child "extraction" called 2 times, total CPU: 100 s (0.03 hr)
Elapse: 150 s (0.04 hr)
Total CPU: 1502 s ( 0.42 hr) Elapse: 1800 s ( 0.50 hr)
1523
SEE ALSO
mem(2)
set_host_options(2)
monitor_cpu_memory(3)
PSYN-508(n)
cputime
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create_auto_shield
Performs automatic shield routing using the classic router.
SYNTAX
status create_auto_shield
[-with_ground net_name]
[-nets collection_of_nets]
[-ignore_shielding_net_pins]
[-ignore_shielding_net_rails]
[-coaxial_below]
[-coaxial_above]
Data Types
net_name
collection_of_nets
string
collection
ARGUMENTS
-with_ground net_name
Specifies which power or ground net to tie the shielding wires to.
By default, the shielding wires are tied to the ground net. If the design contains multiple
ground nets, you must use this option to specify the ground net.
-nets collection_of_nets
Specifies the nets to be shielded. If the specified nets do not have shielding rules
defined, the tool uses the default width and minimum spacing for the layer as defined in
the technology file.
By default, this command performs shielding on all nets with defined shielding rules. To
define the shielding rules, use the define_routing_rule and set_net_routing_rule
commands.
-ignore_shielding_net_pins
Prevents connection of the shielding wires to the standard cell power or ground (PG)
pins.
By default, the shielding wires are connected to the standard cell PG pins.
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-ignore_shielding_net_rails
Prevents connection of the shielding wires to the standard cell rails.
By default, the shielding wires are connected to the standard cell rails.
-coaxial_below
Creates coaxial shielding below the shielded net segment layer.
By default, this command does not perform coaxial shielding below the shielded net
segment layer.
-coaxial_above
Creates coaxial shielding above the shielded net segment layer.
By default, this command does not perform coaxial shielding above the shielded net
segment layer.
DESCRIPTION
The create_auto_shield command uses the classic router to shield nets based on the
associated shielding rules.
By default, the command performs same-layer shielding on all nets with predefined
shielding rules. The router routes shielding wires based on the shielding widths and spacing
defined in the shielding rules. The shielding wires are tied to the ground net, standard cell
ground pins, and standard cell rails.
To explicitly specify the nets on which to perform shielding, use the -nets option. To tie the
shielding wires to a named power or ground net, use the -with_ground option. To prevent
connections to the standard cell PG pins, use the -ignore_shielding_net_pins option. To
prevent connections to the standard cell rails, use the -ignore_shielding_net_rails option.
By default, the command does not perform coaxial shielding. To perform coaxial shielding
above the shielded net segment layer, use the -coaxial_above option. To perform coaxial
shielding below the shielded net segment layer, use the -coaxial_below option. When the
tool performs coaxial shielding, the coaxial shielding segments
•
Are routed in the preferred layer direction
•
Use the defaultWidth layer attribute from the technology file
•
Are spaced such that they leave at least one signal routing resource on each layer
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Prerequisites
Before you run this command, you must first define the shielding rules with the
define_routing_rule command and assign these rules to the nets to be shielded with the
set_net_routing_rule command.
This requirement applies when you do not specify the -nets option, you want to use a
nondefault width or minimum spacing, or you want to snap the shielding segments to the
grid.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example defines the shielding rules; assigns these shielding rules to all clock
nets; and then uses the classic router to shield the CLK_B1 clock net with the VSS ground
net, the CLK_B2 clock net with the GND ground net, and the CLK_B3 and CLK_B4 clock
nets with the VDD power net. The shielding wires are not connected to the standard cell PG
pins.
prompt> define_routing_rule clock_net_shielding \
-default_reference_rule -taper_level 0 -snap_to_track \
-widths { METAL1 0.16 METAL2 0.2 METAL3 0.2 METAL4 0.2 } \
-spacing { METAL1 0.18 METAL2 0.21 METAL3 0.21 METAL4 0.21 } \
-shield_width { METAL1 0.16 METAL2 0.2 METAL3 0.2 METAL4 0.2 } \
-shield_spacing { METAL1 0.18 METAL2 0.21 METAL3 0.21 METAL4 0.21 } \
-via_cuts { via1 1X1 via2 1X1 via3 1X1 }
prompt> set clock_nets [get_nets -filter "net_type == Clock" -hier]
prompt> set_net_routing_rule -rule clock_net_shielding $clock_nets
prompt> create_auto_shield -with_ground VSS -nets {CLK_B1} \
-ignore_shielding_net_pins
prompt> create_auto_shield -with_ground GND -nets {CLK_B2} \
-ignore_shielding_net_pins
prompt> create_auto_shield -with_ground VDD -nets {CLK_B3 CLK_B4} \
-ignore_shielding_net_pins
SEE ALSO
define_routing_rule(2)
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set_net_routing_rule(2)
create_auto_shield
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create_banking_guidance
Generates output file having create_register_bank commands to replace single-bit registers
with multibit register.
SYNTAX
status create_banking_guidance
DESCRIPTION
The command create_banking_guidance uses the strategy set by
set_banking_guidance_strategy to identify groups of single-bit registers which can be
replaced by multibit registers and generates an output file having create_register_bank
commands. You can source the output file back into the tool to replace single-bit registers
with multibit register.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example uses the create_banking_guidance command to generate the
output file having create_register_bank commands.
prompt> create_banking_guidance
SEE ALSO
set_banking_guidance_strategy(2)
remove_banking_guidance_strategy(2)
report_banking_guidance_strategy(2)
create_register_bank(2)
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create_base_array
Creates a base array record in the design.
SYNTAX
status create_base_array
[-tile_name tile_name]
-coordinate rectangle
[-direction direction]
Data Types
tile_name
rectangle
direction
string
list
string
ARGUMENTS
-tile_name tile_name
Specifies the name of unit tile used in the base array record.
If -tile_name is not specifies, by default it creates a base array using "unit" as its unit tile.
-coordinate rectangle
Specifies the lower left corner and the upper right corner of the base array. The values
are specified in microns relative to the chip origin.
-direction direction
Specifies the direction of the base array record.
The validated values of direction can be: horizontal and vertical.
By default, the direction is set to horizontal.
DESCRIPTION
The create_base_array command allows you to create a base array record into database.
This command returns 1 if succeeds.
create_base_array
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates a base array record.
prompt> create_base_array -coordinate {{200 200} {1800 1800}} \
-direction horizontal -tile_name unit
1
SEE ALSO
remove_base_arrays(2)
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create_block_abstraction
Generates a block abstraction for the current design. The command identifies the interface
logic of the current design and annotates the design in memory with the interface logic.
SYNTAX
status create_block_abstraction
[-include objects]
Data Types
objects
collection
ARGUMENTS
-include objects
Specifies the additional leaf cells and nets that are to be included in the block
abstraction.
Logical hierarchical cells and pins are ignored.
If either one of the following conditions exist, the entire block is included in the block
abstraction:
•
The number of leaf cells included exceeds 95 percent of the total leaf cells in the
block.
•
The number of nets included exceeds 95 percent of the total nets in the block.
DESCRIPTION
This command creates a block abstraction of the current design and annotates the design
in memory with the interface logic.
You must save the block abstraction on disk by using the save_mw_cel command.
Creating a block abstraction by using the create_block_abstraction command allows you
to perform transparent interface optimization on the block in the top-level flow.
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At the top level, use the set_top_implementation_options command to specify which
blocks should be integrated with the top-level design as block abstractions.
The create_block_abstraction command first determines the interface logic.
The following netlist objects are part of the interface logic:
•
All cells, pins, and nets in timing paths from input ports to registers or output ports.
•
All cells, pins, and nets in timing paths to output ports from registers or input ports.
•
The following clock-gating circuitry:
•
❍
Any logic in the connection from the master clock to the generated clocks.
❍
The clock trees that drive interface registers, including any logic in the clock tree.
❍
The longest and shortest clock paths from the clock ports.
The side-load cells of all nonideal and non-DRC disabled nets.
By default, the create_block_abstraction command ignores an input or inout port during
interface logic identification, if the percentage of the total registers in the transitive fanout of
the port is greater than or equal to the threshold percentage specified in the
abstraction_ignore_percentage variable. (The default is 25.) The ports that are ignored
are then connected to already-identified interface logic. Also, minimum and maximum
critical timing paths are retained for these ignored ports.
This default helps to identify the test enable and reset ports of your design. Examine the
current value of the abstraction_ignore_percentage variable and change it, if needed. The
default might potentially ignore ports you do not want to ignore or fail to ignore ports that you
do want to ignore. Carefully read the messages that the create_block_abstraction
command issues when you use the default to see which ports have been ignored and to
what percentage of registers they fanned out.
The create_block_abstraction command implicitly performs an update_timing on the
design, if required.
The create_block_abstraction command ignores case analysis settings, if any, during
interface logic identification. You must specify the appropriate case analysis settings at the
top level. This is done to make the block abstraction more context independent.
The create_block_abstraction command assumes all latches found in the interface logic
are potential borrowers; thus, all logic from I/O ports to flip-flops or output ports are identified
as belonging to the interface logic.
Multicorner-Multimode Support
This command uses information from all scenarios.
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For a multicorner-multimode design,
•
The create_block_abstraction command automatically detects the presence of
multiple scenarios (multiple modes or corners) and determines the interface logic for
each scenario. The interface logic identified for each scenario is retained as the interface
logic of the block abstraction. If an interface timing path is disabled in one scenario but
enabled in another, the path is included in the interface logic.
•
Detailed parasitics are extracted and stored as part of abstraction information for each
specified TLUPlus file and temperature.
•
Signal integrity and coupling capacitance information are stored for each scenario when
the design is track assigned or detail routed.
•
Power consumption of the design is calculated for each scenario. The calculated power
data is stored in attributes in the design and can be used by the report_power command
during the final assembly step of the entire chip.
EXAMPLES
The following example shows how to create and save a block abstraction:
prompt> open_mw_cel MY_DES
prompt> create_block_abstraction
prompt> save_mw_cel
SEE ALSO
open_mw_cel(2)
save_mw_cel(2)
abstraction_ignore_percentage(3)
abstraction_max_active_scenarios(3)
check_block_abstraction(2)
report_block_abstraction(2)
set_top_implementation_options(2)
create_block_abstraction
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create_boundary
Creates a boundary for a design or library cell.
SYNTAX
status create_boundary
[-coordinate rectangle
| -poly {point point ...}
| -by_terminal]
[-core]
[-left_offset l_offset]
[-right_offset r_offset]
[-top_offset t_offset]
[-bottom_offset b_offset]
[design | -lib_cell_type type]
ARGUMENTS
-coordinate rectangle
Creates a boundary using the specified bounding box. This option is mutually exclusive
with -poly and -by_terminal; you can only use one of them. If you do not specify any of
these options, the boundary is created according to current boundary. You cannot
specify this argument with the -lib_cell_type option.
-poly {point point ...}
Creates a rectilinear boundary with n points. This option is mutually exclusive with
-coordinate and -by_terminal; you can only use one of them. If you do not specify any
of these options, the boundary is created according to current boundary. You cannot
specify this argument with the -lib_cell_type option.
-by_terminal
Creates a boundary based on the bounding box of all the terminals in the design (if you
specify design) or the library cells (if you specify -lib_cell_type).
-core
Indicates that -coordinate also defines the core area for design planning.
-left_offset l_offset
Specifies the distance to adjust the left side of the boundary.
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-right_offset r_offset
Specifies the distance to adjust the right side of the boundary.
-top_offset t_offset
Specifies the distance to adjust the top of the boundary.
-bottom_offset b_offset
Specifies the distance to adjust the bottom of the boundary.
design
Specifies the design for which to create a boundary.
This option and the -lib_cell_type option are mutually exclusive. If you do not specify
either design or -lib_cell_type, the boundary is created for the current design.
-lib_cell_type type
Specifies the type of library cell for which to create boundaries. If you also specify
-by_terminal, the boundary is created based on the terminal locations; otherwise the
boundary is created based on the current boundary.
This option and the design argument are mutually exclusive. You cannot use this option
when you specify the -coordinate or -poly options.
DESCRIPTION
The create_boundary command allows you to create a boundary for a design or library
cells. If you specify -lib_cell_type, a boundary is created for all library cells of the specified
type. If you specify design, a boundary is created for the specified design. If you do not
specify either -lib_cell_type or design, a boundary is created for the current design.
For a design, you can specify the boundary by using the -coordinate, -poly, or
-by_terminal option. If you do not specify how to create the boundary, the boundary is
created based on the current boundary.
For library cells, you can specify the boundary only by using the -by_terminal option.
You can also adjust the boundary by using the -left_offset, -right_offset, -top_offset, and
-bottom_offset options. However, these four options cannot be used with -poly.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following command creates a boundary for the current design by specifying a bounding
box.
prompt> create_boundary -coordinate {{0 0} {100 100}}
1
The following command creates a boundary for the current design by specifying a point
array.
prompt> create_boundary -poly {{0 0} {100 0} \
{100 100} {50 100} {50 50} {0 50}}
1
The following command creates a boundary for the current design based on its terminal
locations and adjusts the left side of the boundary.
prompt> create_boundary -by_terminal -left_offset 10
1
The following command creates a boundary for all io_pad cells in the reference library.
prompt> create_boundary -lib_cell_type io_pad
1
SEE ALSO
Chapter 1:
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create_bounds
Creates a fixed move bound or floating group bound in the design.
SYNTAX
status create_bounds
[-name bound_name]
[-coordinate {llx1 lly1 urx1 ury1 ...}]
[-dimension bound_dimension]
[-diamond central_object]
[-effort low | medium | high | ultra]
[-type soft | hard]
[-exclusive]
[-color color]
[-cycle_color]
object_list
Data Types
bound_name
llx1
lly1
urx1
ury1
bound_dimension
central_object
color
object_list
string
float
float
float
float
list
object
integer or string
list
ARGUMENTS
-name bound_name
Specifies the name of the bound.
-coordinate {llx1 lly1 urx1 ury1 ...}
Specifies rectangular move bounds by specifying the coordinates of the lower-left and
upper-right corners for each rectangle. The coordinates are in microns relative to the
chip origin.
Each combination of {llx lly urx ury} defines a target placement area for the objects. The
coarse placement engine can place cells in any of the rectangles. These placeable
areas can overlap or be disjoint.
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You can specify rectilinear move bounds by dividing the rectilinear region into individual
rectangular bounds and specifying the rectangles in the coordinate list.
-dimension bound_dimension
Specifies the dimension of a group bound or diamond bound in microns. The dimension
of a group bound is specified as {width height}, while the dimension of a diamond bound
is specified as extent.
-diamond central_object
Creates a diamond bound centered on the specified object, which can be a port, cell, or
pin.
The objects in the bound are constrained to lie within the distance specified by the
-dimension option (measured as a Manhattan distance) of the specified object. A
diamond bound is always a soft bound.
If you specify this option, you must also specify the -dimension option.
-effort low | medium | high | ultra
Specifies the effort to bring cells closer inside a group bound.
The default is medium.
This option is mutually exclusive with the -coordinate and -dimension options.
-type soft | hard
Specifies the type of the bound to be either hard or soft.
To use this option, you must also specify either the -coordinate or -dimension option.
The bound type cannot be set for automatically generated group bounds or diamond
bounds.
The default is soft.
-exclusive
Creates an exclusive move bound.
Exclusive move bounds require all of their cells to be placed inside them and prohibit the
placement of other cells in the same area. Exclusive move bounds are respected by
both coarse placement and legalization.
-color color
Specifies the move bound color. You can specify the color either by specifying an integer
value between 0 and 63 or by specifying one of the following keywords: black, blue,
green, cyan, brown, purple, red, magenta, salmon, orange, yellow, or white.
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The default is no_color, meaning that no color is specified.
-cycle_color
Allows the tool to automatically assign a move bound color.
By default, this option is off.
object_list
Specifies a list of cells, ports, and pins to be included in the bound.
If a cell is a hierarchical cell, the bound applies to all cells in the subdesign. If a port is a
hierarchical port, the corresponding port is attached to the bound instead. If a pin is a
leaf pin, the lower-left point of the first geometry of the pin is marked on the cell of the
pin, and the cell is added to the bound. If a pin is a hierarchical pin, it is ignored.
A cell can be assigned to only one move bound; an error occurs if a specified cell already
belongs to another move bound.
This argument is optional; you can create an empty move bound and later associate
cells with it by using the update_bounds command.
DESCRIPTION
The create_bounds command allows you to define region-based placement constraints for
coarse placement.
There are three types of bounds: move bounds, group bounds, and diamond bounds.
•
Move bounds restrict the placement of cells to a specific region of the core area.
•
To create a move bound, use the -coordinate option.
•
Group bounds are floating region constraints. Cells in the same group bound are placed
within a specified bound but the absolute coordinates are not fixed. Instead, they are
optimized by the placer.
•
To create a group bound, use the -dimension option.
•
Diamond bounds are region constraints centered on a specific object, which can be fixed
or floating. Other objects in the same diamond bound are placed within the specified
Manhattan distance from the central object but their absolute coordinates are not fixed.
Instead, they are optimized by the placer.
•
To create a diamond bound, use the -diamond option together with the -dimension
option.
If you do not use any of these options, the tool creates a group bound with a bounding box
computed internally by the tool. In this case, you can use the -effort option to specify the
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effort level used to bring the cells closer. All automatically generated bounds are soft
bounds; you cannot use the -type option to change the bound type for these group bounds.
Generally, there is no guarantee that cells are placed completely within the bounds. For
instance, coarse placement can violate the bounds if the quality of its primary placement
objectives would otherwise be destroyed.
In these situations, you should revisit the bounds and floorplan to ensure that the design is
not overconstrained. Alternatively, you can use the -type hard option to specify the bound
type to be hard (the default is soft). The coarse placer tries to honor the hard bound as hard
constraints while sacrificing other objectives, such as timing and routability. You should not
use many hard bounds because this can lead to inferior placement solutions.
The bounds created by the create_bounds command are persistent and do not need to be
re-created when the design is reloaded.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example constrains the placement of the INST_1 instance to lie within the
rectangle with its lower-left corner at (100, 100) and its upper-right corner at (200, 200):
prompt> create_bounds -name "temp" -coordinate {100 100 200 200} INST_1
The following example creates a hard rectilinear move bound on a hierarchical instance
named INST2. The rectilinear move bound is created as a set of two rectangles: one with its
lower-left corner at (10, 10) and its upper-right corner at (30, 20), and one with its lower-left
corner at (20, 20) and its upper-right corner at (30, 30).
prompt> create_bounds -name "temp2" \
-coordinate {10 10 30 20 20 20 30 30} \
-type hard INST_2
The following example creates a diamond bound centered on the pin MOD/U1/A. The cells
MOD/INST1 and MOD/INST2 are constrained to lie at most 64 microns of Manhattan
distance away from MOD/U1/A.
prompt> create_bounds -name "temp3" \
-dimension 64 \
-diamond MOD/U1/A \
{MOD/INST1 MOD/INST2}
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SEE ALSO
create_placement(2)
remove_bounds(2)
report_bounds(2)
set_cell_location(2)
set_dont_touch_placement(2)
update_bounds(2)
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create_buffer_tree
Creates a buffer tree for the specified driver pins and nets.
SYNTAX
status create_buffer_tree
[-from pin_net_list]
[-incremental]
[-no_legalize]
[-on_route [-skip_detail_route]]
[-align_hierarchy_for_long_nets]
Data Types
pin_net_list
collection
ARGUMENTS
-from pin_net_list
Specifies the driver pins and nets for which the tool creates buffer trees. When the -from
option is not specified, the create_buffer_tree command works on all drivers with a
transitive fanout of 5 or more. The -from option can be used with the -on_route option.
If they are used together, the nets are required to be routed. The create_buffer_tree
command runs post route based optimization only when the -on_route and -from
options are used together. You have to run subsequent routing to make sure that all nets
are fully routed for the next operation.
-incremental
Sets the scope of creating the buffer tree for the specified nets rather than the entire
buffer tree driven by the specified nets. When this option is specified, the
create_buffer_tree command constructs a buffer tree, if needed, on each net specified
by the -from option to reduce the high fanout of each net, but it does not remove any
existing buffers or inverters. So, the scope of creating buffer trees is a single specified
net.
-no_legalize
Disables placement legalization at the end of buffering.
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-on_route
Perform the postroute optimization flow, where it fixes DRC violations by using the
route_opt command and then the focal_opt command. It focuses mainly on fixing
maximum net length, so you need to specify the max_net_length constraint by using the
set_max_net_length command, before using this option. The final database is a detail
routed database.
It is recommended to use the -align_hierarchy_for_long_nets option with the
-on_route option to ensure that optimization occurs for long nets crossing logical
hierarchies.
You can use the -from option with this option to fix DRC violations for the concentrated
nets. However, if you use the -from option, the design must be detail routed and you
cannot use the -skip_detail_route or -align_hierarchy_for_long_nets options.
-skip_detail_route
Skips detail routing when used with the -on_route option. By default the -on_route
option triggers full detail routing after topology-based DRC optimization. This option can
reduce runtime of the on_route option by skipping the final detail route.
This option can only be used with the -on_route option. This option cannot be combined
with the -from option.
-align_hierarchy_for_long_nets
Enables additional optimizations and port punching for long nets that crosses multiple
hierarchies. Long nets are those nets that violate the maximum net length constraint for
the design. You can specify max_net_length constraint via command
set_max_net_length before using this option. If you use this option and the design does
not have a maximum net length constraint, the command fails with an error message.
When you use this option, the tool first performs high-fanout net fixing and also fixing
DRC violations, such as maximum transition and capacitance, for low fanout nets. It then
performs preroute topology-based buffering and port punching for the nets that violate
the maximum net length constraint and crosses multiple hierarchies. If both of these
conditions are not met, this additional optimization is not performed.
This option does not fix all maximum net length constraint. You have to rely on the
-on_route option to fix the remaining violations.
This option can be used alone or with the -on_route option, but it cannot be used with
the -from options.
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DESCRIPTION
The create_buffer_tree command creates a buffer tree for each specified driver pin and for
the driver pin of each specified net.
The create_buffer_tree command generates a hierarchical buffer tree, and buffers are
inserted across hierarchical boundaries. The command is location-based. Therefore, the
specified driver pin should not be a hierarchical pin because a hierarchical pin does not have
a location.
Use this command on a placed design only. The command requires the following libraries
and information:
•
The physical libraries that correspond to the specified logic libraries.
•
The capacitance and resistance per unit length derived from the physical library or
user-specified.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example creates a buffer tree that is implemented at driver a/O:
prompt> create_buffer_tree -from [get_pins a/O]
The following example creates buffer trees for driver a/O and net n1:
prompt> create_buffer_tree -from {[get_pins a/O] [get_nets n1]}
SEE ALSO
remove_buffer_tree(2)
report_buffer_tree(2)
report_ahfs_options(2)
report_net_fanout(2)
set_ahfs_options(2)
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create_cell
Creates leaf or hierarchical cells in the current design or its subdesigns.
SYNTAX
status create_cell
cell_list
[reference_name]
[-hierarchical]
[-view view_name]
[-freeze_silicon]
Data Types
cell_list
reference_name
view_name
list
string
string
ARGUMENTS
cell_list
Specifies the names of cells created in the current design. Each cell name must be
unique within the current design.
reference_name
Specifies the design or library cell that new cells reference. Ports on the reference
determine the name, number, and direction of pins on the new cell.
-hierarchical
Creates hierarchical cell instances and designs with the name given by cell_list if the
reference_name is not specified.
If you specify the reference_name, the cell_list must have a single element. The
command creates the hierarchical cell instance with the name given by the single
cell_list and also creates the design with the name given by reference_name.
This option is mutually exclusive with the -view option.
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-view view_name
Specifies the Milkyway view of the reference design used for creating the new cell. Using
this option triggers a link of the design and can increase runtime.
When creating the cell, the tool verifies that the specified view exists for the reference
cell.
Do not use this option for creating standard cells, which always use the FRAM view of
the reference cell.
Note that all cells in the design must have a FRAM view in the reference library,
regardless of the view used when creating a new cell. The create_cell command
currently verifies only the existence of the specified view. If you specify -view CEL and
a FRAM view does not exist for the reference design, you might receive errors later in
the design flow. To create a FRAM view for a reference design, use the
create_macro_fram command.
-freeze_silicon
Creates cell instances in a transitional state to support the ECO freeze silicon flow. The
place_freeze_silicon or map_freeze_silicon command deletes the instances and
replaces them with existing spare cells of the same reference library cell. This option has
no impact on cell creation for hierarchical cells.
DESCRIPTION
This command creates new leaf or hierarchical cells in the current design or its subdesigns
based on the cell_list argument. New leaf cells are the instantiation of an existing design or
library cell. New hierarchical cells are the instantiation of a new design.
The created cells are placed just outside the core area on the lower right corner, if the core
area is defined. The attribute "is_placed", is still FALSE, as this is not a legal location.
To remove cells from the current design, use the remove_cell command.
Although the reference_name argument accepts names in the format library/library_cell, the
command might not instantiate the actual library cell from the specified library. The actual
library cell to be used is determined by the current link library settings.
EXAMPLES
The following example creates a cell named cell1 under the subdesign corresponding to the
mid1 cell:
prompt> create_cell {mid1/cell1} my_lib/AND2
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Creating cell 'cell1' in design 'mid'.
The following example creates leaf cells using library cells as references.
prompt> create_cell {U3 U4} my_lib/NAND2
prompt> create_cell "U5" my_lib/NOR2
The following example creates hierarchical cell H1 with the new design name DESIGN1,
and creates leaf cell U2 under the new hierarchical cell using library cells as references:
prompt> create_cell -hierarchical H1 DESIGN1
prompt> create_cell H1/U2 my_lib/NAND2
The following example creates hierarchical cells H2 and H3 with the design name H2 and
H3 separately. Also, it creates leaf cell U3 under the new hierarchical cell H2 using library
cells as references.
prompt> create_cell -hierarchical {H2 H3}
prompt> create_cell H2/U3 my_lib/NAND2
In IC Compiler, reference cells in the physical library can be used without the need for a
logical library reference if the physical cell reference has only power and ground pins. This
allows you to create some cells (such as filler, power pad, tap, and cap cells) without having
logical library references for them. The following example creates a power pad using a
physical library reference. No slash is used to designate a library, since there is only one
physical library.
prompt> create_cell my_power_pad pvdd
The following example creates a FRAM view before using the -view option:
prompt> create_macro_fram -library_name logo -cell_name cell_logo \
-identify_macro_pin_by_pin_text
prompt> close_mw_library logo
prompt> open_mw_library design
prompt> open_mw_cell routed
prompt> create_cell -view FRAM cell_logo my_logo
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SEE ALSO
create_macro_fram(2)
map_freeze_silicon(2)
place_freeze_silicon(2)
remove_cell(2)
report_cell(2)
set_cell_location(2)
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create_clock
Creates a clock object and defines its waveform in the current design.
SYNTAX
status create_clock
[-name clock_name]
[-add]
[source_objects]
[-period period_value]
[-waveform edge_list]
[-comment comment_string]
Data Types
clock_name
source_objects
period_value
edge_list
comment_string
string
list
float
list
string
ARGUMENTS
-name clock_name
Specifies the name of the clock being created. If you do not use this option, the clock is
given the same name as the first clock source specified in source_objects. If you do not
use source_objects, you must use this option, which creates a virtual clock not
associated with a port or pin. Use this option along with source_objects to give the clock
a more descriptive name than that of the pin or port where it is applied.
If you specify the -add option, you must use the -name option and the clocks with the
same source must have different names.
-add
Specifies whether to add this clock to the existing clock or to overwrite the existing clock.
Use this option to capture the case where multiple clocks must be specified on the same
source for simultaneous analysis with different clock waveforms. When you specify this
option, you must also use the -name option. Defining multiple clocks on the same
source pin or port causes longer runtime and higher memory usage than a single clock,
because the synthesis timing engine must explore all possible combinations of launch
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and capture clocks. Use the set_false_path command to disable unwanted clock
combinations. This option is ignored (the default), unless multiple clocks analysis is
enabled by setting the timing_enable_multiple_clocks_per_reg variable to true.
source_objects
Specifies a list of pins or ports on which to apply this clock. If you do not use this option,
you must use -name clock_name, which creates a virtual clock not associated with a
port or pin. If you specify a clock on a pin that already has a clock, the new clock
replaces the old clock unless you use the -add option.
-period period_value
Specifies the period of the clock waveform in library time units.
-waveform edge_list
Specifies the rise and fall edge times, in library time units, of the clock over an entire
clock period. The first time in the list is a rising transition, typically the first rising
transition after time zero. There must be an even number of increasing times, and they
are assumed to be alternating rise and fall times. The numbers must represent one full
clock period. If -waveform edge_list is not specified, but -period period_value is, a
default waveform with a rise edge of 0.0 and a fall edge of period_value/2 is assumed.
-comment comment_string
Allows the command to accept a comment string. The tool honors the annotation and
preserves it with the SDC object so that the exact string is written out when the
constraint is written out when you use the write_sdc or write_script command. The
comment remains intact through the synthesis, place-and-route, and timing-analysis
flows.
DESCRIPTION
The create_clock command creates a clock object in the current design. The command
defines the specified source_objects as clock sources in the current design. A pin or port
can be a source for a single clock. If source_objects is not specified, but a clock_name is
given, a virtual clock is created. A virtual clock can be created to represent an off-chip clock
for input or output delay specification. For more information about input and output delay,
refer to the set_input_delay and set_output_delay command man pages.
Clock objects hold attributes that affect the clock network, such as dont_touch_network,
fix_hold, and propagated_clock. Using create_clock on an existing clock object
overwrites the attributes previously set on the clock object. The create_clock command
also defines the waveform for the clock. The clock can have multiple pulses per period.
Setup and hold path delays are automatically derived from the clock waveforms of the path
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startpoint and endpoint. The fix_hold attribute (set by the set_fix_hold command) directs
compile to fix hold violations for a clock.
By default, a new path group is created for the clock. This groups together the endpoints
related to this clock for cost function calculation. To remove the clock from its assigned
group, use the group_path command to reassign the clock to another group or to the
default path group. For more information, refer to the group_path command man page.
The new clock has ideal timing, so no propagation delay through the clock network is
assumed. To enable propagation delay through the clock network, use the
set_propagated_clock command. To add skew or uncertainty to the ideal waveform, use
the set_clock_latency or set_clock_uncertainty command.
To show information about all clock sources in a design, use the report_clock command.
To get a list of clock sources, use the get_clocks command. To return sequential cells
related to a given clock, use the all_registers command. To undo create_clock, use the
remove_clock command.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example creates a clock on port PHI1 with a period of 10.0, rise at 5.0, and fall
at 9.5:
prompt> create_clock "PHI1" -period 10 -waveform {5.0 9.5}
In the following example, the clock has a falling edge at 5 and a rising edge at 10, with a
period of 10. Because the -waveform option expects the edges to be ordered first rise then
fall, and to increase in value, the fall edge can be given as 15; that is, the next falling edge
after the first rise edge at 10.
prompt> create_clock "PHI2" -period 10 -waveform {10 15}
The following example creates a clock named CLK on pin u13/Z, with a period of 25, fall at
0.0, rise at 5.0, fall at 10.0, rise at 15.0, and so forth:
prompt> create_clock "u13/Z" -name "CLK" -period 25 -waveform {5 10 15
25}
The following example creates a virtual clock named HI2 with a period of 10.0, rise at 0.0,
and fall at 5.0:
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prompt> create_clock -name "PHI2" -period 10 -waveform {0.0 5.0}
The following example creates a clock with multiple sources and a complex waveform:
prompt> create_clock -name "clk2" -period 10 -waveform {0.0 2.0 4.0 6.0}
\
{clkgen1/Z clkgen2/Z clkgen3/Z}
SEE ALSO
all_clocks(2)
all_registers(2)
check_timing(2)
current_design(2)
get_clocks(2)
group_path(2)
remove_clock(2)
report_clock(2)
reset_design(2)
set_clock_latency(2)
set_clock_uncertainty(2)
set_dont_touch_network(2)
set_fix_hold(2)
set_max_delay(2)
set_min_delay(2)
set_output_delay(2)
set_propagated_clock(2)
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create_clock_mesh
Creates a grid of horizontal and vertical straps that are joined by vias for clock mesh
implementation.
SYNTAX
status create_clock_mesh
[-net net]
[-layers {horizontal_layer vertical_layer}]
[-num_straps {horizontal_count vertical_count}
| -pitches {horizontal_pitch vertical_pitch}
| -max_pitches {horizontal_pitch vertical_pitch}
| -relative_pitches {horizontal_pitch vertical_pitch}]
[-widths {horizontal_width vertical_width}
| -relative_widths {horizontal_width vertical_width}]
[-keepouts list_of_points]
[-ring]
[-bounding_box rectangle]
[-lower_left {llx lly}]
[-upper_right {urx ury}]
[-max_displacement {horizontal_disp vertical_disp}]
[-load net_or_pins]
[-avoid instances]
[-no_snap]
[-check_only]
[-remove_display]
[-verbose]
[-offset {horizontal_offset vertical_offset}]
[-full_pitch_perimeter]
Data Types
net
horizontal_layer
vertical_layer
horizontal_count
vertical_count
horizontal_pitch
vertical_pitch
horizontal_width
vertical_width
list_of_points
rectangle
llx
lly
urx
ury
horizontal_disp
vertical_disp
create_clock_mesh
list or collection of one item
string
string
integer
integer
float
float
float
float
list
float
float
float
float
float
float
float
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collection
collection of instances
float
float
ARGUMENTS
-net net
Connects new straps to the existing net that you specify. Use the create_net command
if necessary.
-layers {horizontal_layer vertical_layer}
Specifies the horizontal and vertical layers to use for the mesh.
-num_straps {horizontal_count vertical_count}
Specifies the number of horizontal and vertical straps to create. Both numbers should be
positive integers. A mesh created by using the -num_straps {2 2} option has an outer
ring only if the -ring option is specified. The mesh has a hash shape (#) if the -ring
option is not specified. High strap numbers result in a dense mesh. If you to not specify
the -pitches or a -num_straps option, the command synthesizes a mesh based on
internal experimental values.
-pitches {horizontal_pitch vertical_pitch}
Specifies the horizontal and vertical pitches of the mesh. The first distance is the vertical
distance between horizontal straps, and the second is the horizontal distance between
vertical straps. This option is mutually exclusive with the -num_straps option. This is a
hard constraint.
-max_pitches {horizontal_pitch vertical_pitch}
Specifies the maximum horizontal and vertical pitches of the mesh. The first distance is
the maximum vertical distance between horizontal straps, and the second is the
horizontal distance between vertical straps. This option is mutually exclusive with the
-num_straps option. This is a soft constraint. If the pitch does not divide the effective
bounding box evenly, the command adds additional straps to create an even distribution
of straps. You can use the electrical or physical limits as a base for the settings of this
option.
-relative_pitches {horizontal_pitch vertical_pitch}
Specifies the relative horizontal and vertical pitches of the mesh. The pitches are
represented as multiples of the default minimum wire spacing for the chosen layers. The
first distance controls the minimum vertical distance between horizontal straps, and the
second controls the horizontal distance between vertical straps. This option is mutually
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exclusive with the -num_straps option. This is a soft constraint. If the pitch does not
divide the effective bounding box evenly, the command adds additional straps to create
an even distribution of straps. You can use the electrical or physical limits as a base for
the settings of this option.
-widths {horizontal_width vertical_width}
Specifies the widths of horizontal and vertical straps. If you do not specify this option, the
command selects widths based on internal experimental values.
-relative_widths {horizontal_width vertical_width}
Specifies the widths of horizontal and vertical straps that are multiples of the default
minimum wire width for the specified layers.
-keepouts list_of_points
Specifies a list of explicit locations of placement blockages or cells rather than design
objects. The tool does not generate straps and vias that intersect these blocks.
-ring
Encloses the mesh with a rectangular ring that connects the ends of horizontal and
vertical straps. This option adds routing overhead, capacitance, and power, but the ring
might be more effective for reducing impedance among drivers and loads near the
perimeter of the mesh. Note that the ring cannot be completed if the mesh is blocked.
-bounding_box rectangle
Specifies the bounding fox for the mesh. If you specify both the -load and
-bounding_box options, the -bounding_box option takes precedence.
-lower_left {llx lly}
Specifies the X location of the leftmost vertical strap and the Y location of the lowest
horizontal strap. Use this option to specify the point where the lowest horizontal strap
crosses the leftmost vertical strap. The horizontal straps are limited on the left by the left
edge of the implied or specified bounding box. The vertical straps is limited on the
bottom edge by the bottom edge of the implied or specified bounding box.
-upper_right {urx ury}
Specifies the point where the highest horizontal strap crosses the rightmost vertical
strap. This option can only be used with the -lower_left option. No vertical strap is
allowed to the right of urx, and no horizontal strap is allowed above ury.
-max_displacement {horizontal_disp vertical_disp}
Sets the maximum allowed horizontal displacement of vertical straps and the maximum
allowed vertical displacement of horizontal straps. Normally, the command places straps
at the exact geometric location according to the specified options, but the command can
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displace straps within the maximum allowable values to avoid obstructions. The default
value of displacement is determined internally by the tool, you can override the internal
displacement calculation by using the -max_displacement option. A large
horizontal_disp value allows vertical straps to move greater distances horizontally. A
zero value eliminates any vertical straps that encounter a obstruction. See also the
-no_snap option.
-load net_or_pins
Uses the bounding box of the specified pins as the bounding box for the mesh. If a net
is present, the command considers all pins on that net.
-avoid instances
Specifies a collection of instances, typically large blocks. The command does not
generate straps and vias that intersect these blocks.
-no_snap
Disables snapping to available routing tracks. Normally, the command adjusts the
position and spacing of the straps to coincide with available routing tracks. Use the
-no_snap option to avoid snapping to available routing tracks. The -no_snap option is
useful early in the design process to help verify the -bounding_box, -offset, or other
options. The option allows you to see where the straps are placed without adjustment.
-check_only
Prevents straps from being inserted. Use this option to report the number of straps
created and their properties. If the GUI is active, the GUI displays the horizontal and
vertical strap positions, without inserting the straps, after removing any previously
annotated temporary straps.
-remove_display
Removes from the GUI the temporary mesh straps added by the -check_only option.
This option is valid only if the GUI is active.
-verbose
Generates additional debugging messages during strap creation. This option is off by
default.
-offset {horizontal_offset vertical_offset}
Moves the newly created vertical straps to the right by the specified horizontal offset, and
moves the vertical straps up by the specified vertical offset. Use this option to align with
power and ground straps, but avoid intersections.
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-full_pitch_perimeter
Adjusts spacing so that the four straps on the right, left, top, and bottom sides are away
from the perimeter by a full grid pitch. The default is half a pitch.
DESCRIPTION
This command builds a grid of horizontal and vertical straps suitable for a clock mesh. Use
this command as one of the first steps in clock mesh tree creation. Alternatively, you can
create a clock mesh by using create_net_shape and create_via commands. However, the
create_clock_mesh command is specifically designed for creating the clock mesh.
The mesh covers a rectangular area which can be specified directly with the
-bounding_box option, or indirectly with the -load option. If you specify the -load option,
the mesh covers all of the pins specified in the load. Typically, it is easiest to specify the ideal
clock net by using the -load option. If neither -bounding_box nor -load is specified, the
command chooses an area based on the site arrays in the current design.
The layers of the straps are specified as a list with the -layers option, with the first element
in the list being the horizontal layer and the second being the layer to used for vertical straps.
The widths can be omitted, in which case heuristic width straps are used. If -widths are
used, the first element is the width for horizontal straps and the second for vertical straps.
Alternatively, widths can be specified relative to the minimum width for the layer with the
-relative_widths options.
Note that for the options that accept lists, the order of the elements in the list is important.
For the following command skeleton:
create_clock_mesh -layers {M7 M8} -num_straps {7 8}
The first element in the -layers list is the horizontal layer, M7, and corresponds to the first
element in the -num_straps options, 7. The command generates 7 horizontal straps on
layer M7. The second element in the -layers list is M8 and the second element in the
-num_straps option is 8, the command generates 8 straps on layer M8.
The mesh covers the entire rectangle defined by the bounding box, unless you use -avoid
or -keepouts to specify one or more blocks where the mesh should not be created. Use this
option with care: it is possible to construct meshes with poor electrical connectivity, or even
disconnected straps by using this option.
To create a ring around the perimeter of your mesh, use the -ring option. A mesh created
with the -ring option using the following options:
-ring -num_straps {2 2}
has a square shape. A mesh created without the -ring option using the following option:
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-num_straps {2 2}
has a hash shape ("#"). The number of straps can be any nonnegative number. The
following option:
-num_straps {1 1}
creates two straps shaped like a cross "+". The following option
-num_straps {8 0}
adds 8 horizontal straps and no vertical straps. Note that when 0 straps are specified in one
dimension, the calculations are done internally as if two or more straps were specified in the
other dimension, and then those straps are suppressed. This is important because the
length of the horizontal straps, for example, is dependent on the vertical straps. The
following option:
-num_straps {2 0}
places two horizontal straps directly on top of the two horizontal straps created by the
following option:
-num_straps {2 7}
This allows you to create complex meshes by running the create_clock_mesh command
multiple times.
By default, the spacing between straps are equal in the interior of the mesh, but only half as
wide around the perimeter. This is done so that each strap horizontal-vertical crossing is
surrounded by the same area.
To create evenly spaced straps, use the -full_pitch_perimeter option. For example, if you
specify a bounding box of {{0 0} {120.0 240.0}} and specify the following options:
-num_straps {2 4} -full_pitch_perimeter
to generate 2 horizontal straps and 4 vertical straps, the vertical straps are 48 microns apart
and 48 microns from the right and left sides. (240 divided by 5). Without the
-full_pitch_perimeter option, the interior pitch would be adjusted to 60 microns, and the
leftmost mesh strap is placed 30 microns (one half pitch) away from the bounding box, and
the rightmost mesh strap is 30 microns (one half pitch) away from the right side of the
bounding box. Similar calculations apply for the top and bottom straps. This style is
preferred if you intend to place a driver at each interior intersection (in this case, 8 drivers),
because then each driver is in the center of a rectangle with the same dimensions, and all
drivers would serve similar loads.
If you know exactly where you want to place the wires, you might want to use the -lower_left
and -pitch options. The argument to the -lower_left option is the exact position of the center
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of the crossing of the leftmost vertical wire with the bottommost horizontal wire. Using the
-pitch option lets you specify the precise distance between wires. If you do this, you cannot
specify the -num_straps option, the number of straps is determined for you. To create fewer
straps, you can limit the grid by specifying the -upper_right option. No vertical wires are
added to the right of this point, nor any horizontal wires above this point.
The following command:
create_clock_mesh -layers {M5 M6} -lower_left {15.125 76.015} -pitches
{100 200}
creates vertical wires with X coordinates 15.125, 215.125, 415.125, etc and horizontal wires
with Y coordinates of 76.015, 176.015, 276.015, etc.
Note the following terminology used to define nets relevant to all the clock mesh commands:
The commands that deal with clock meshes distinguish among three types of important
nets. The term "clock net" refers to a net normally associated with the original ideal clock.
Typically it is connected to an input port, or it can be marked in SDC as a derived clock.
Generally, a clock starts out as an ideal net connected to a port or a clock driver and many
loads.
The "root net" is the net at the apex of the tree of buffers that drive the mesh. The "root net"
is often the same net as the "clock net", but this is not required. If several clocks are
distributed by the same mesh, the root net is a common point for their distribution, but the
root net is not required to be uniquely associated with one clock.
The "mesh net" is the net of the wiring grid. In the methodology illustrated here, the mesh
net is created using the create_net command before creating the mesh itself.
Because each of these nets is important in understanding and analyzing the circuit, it is
advisable to assign them evocative names. If there is only one clock involved, perhaps
called "clk" connected to a port called "clk", then the net associated with the mesh might be
called "clk_mesh." and the root net is also net "clk." The create_clock_mesh command
could use -load clk and -net clk_mesh. Later, the add_clock_drivers command would take
the pins that are on the net called clk, disconnect them from net "clk" and connect them to
net clk_mesh, and add drivers that start from the net clk and drive clk_mesh. If you chose to
use the analyze_subcircuit command, it would model the circuit starting from net "clk"
through all the pins connected to net "clk_mesh".
If there are two distinct clocks, "clk1" and "clk2" that are gated together into the root of the
tree, the root might be called "clk1_clk2_root", and the mesh that is driven might be
"clk1_clk2_mesh". The create_clock_mesh command could use -load clk1_clk2_root and
-net clk1_clk2_mesh. Later, the add_clock_drivers command would take the pins that are
on the net called clk1_clk2_root, disconnect them from clk1_clk2_root and connect them to
net clk1_clk2_mesh, and add drivers that start from the net clk1_clk2_root and drive
clk1_clk2_mesh. The add_clock_drivers command would not deal with the nets "clk1" or
"clk2". The analyze_subcircuit command would model the circuit starting from net
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"clk1_clk2_root" through all the pins connected to net "clk1_clk2_mesh". The
analyze_subcircuit command would not begin its analysis at net clk1 or clk2, because the
analyze_subcircuit command requires a single net at its root.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
This example creates a grid with horizontal straps on M7 and vertical straps on M8. It
includes the top and bottom straps that form a ring around the mesh, and it connects the
load pins to the net of the mesh, which is called "clk1_mesh". The command inserts just
enough horizontal straps so that the distance between them is not more than 100 times the
minimum pitch for layer M7. It adds just enough vertical straps so that the pitch between
them is not be more than 150 times the minimum pitch for layer M8. Since the widths of the
straps are not specified, the command chooses the widths internally.
prompt> create_net clk1_mesh
1
prompt> set_attribute [get_net clk_mesh] net_type "Clock"
1
prompt> create_clock_mesh -net [get_net clk1_mesh] \
-load [get_pins -of clk] -ring \
-relative_pitches {100 150} -layers {M7 M8}
1
SEE ALSO
add_clock_drivers(2)
analyze_subcircuit(2)
compile_clock_tree(2)
compile_premesh_tree(2)
route_mesh_net(2)
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create_command_group
Creates a new command group.
SYNTAX
string create_command_group
[-info info_text]
group_name
ARGUMENTS
-info info_text
Help string for the group
group_name
Specifies the name of the new group.
DESCRIPTION
The create_command_group command is used to create a new command group, which
you can use to separate related user-defined procedures into functional units for the online
help facility. When a procedure is created, it is placed in the "Procedures" command group.
With the define_proc_attributes command, you can move the procedure into the group
you created.
The group_name can contain any characters, including spaces, as long as it is appropriately
quoted. If group_name already exists, create_command_group quietly ignores the
command. The result of create_command_group is always an empty string.
EXAMPLES
The following example demonstrates the use of the create_command_group command:
prompt> create_command_group {My Procedures} -info "Useful utilities"
prompt> proc plus {a b} { return [expr $a + $b] }
prompt> define_proc_attributes plus -command_group "My Procedures"
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prompt> help
My Procedures:
plus
...
SEE ALSO
define_proc_attributes(2)
help(2)
proc(2)
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create_connview
Invokes the Hercules connectivity engine to generate a connectivity (CONN) view and
current source files for nonstandard cells. The generated CONN view and current source
files can be used during IR drop analysis.
SYNTAX
status create_connview
-library library_name
-design design_name
[-power_nets net_names]
[-ground_nets net_names]
[-generate_csf]
[-skip_via mask_names]
[-connview_skip_cell cell_names]
[-csf_skip_cell cell_names]
[-layer_text mask_names_text]
Data Types
library_name
design_name
net_names
mask_names
cell_names
mask_names_text
string
string
string
string
string
string
ARGUMENTS
-library library_name
Specifies the name of the library. The library is the one in the Milkyway database.
This is a required option. There is no default for this option.
-design design_name
Specifies the name of the single cell in the specified Milkyway library for which you want
to generate a CONN view.
This is a required option. There is no default for this option.
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-power_nets net_names
Specifies the names of the top-level power nets to be extracted.
You must specify at least one of the following options: -power_nets or -ground_nets.
-ground_nets net_names
Specifies the names of the top-level ground nets to be extracted.
You must specify at least one of the following options: -power_nets or -ground_nets.
-generate_csf
Generates current source files for the specified design and then attaches them to the
CONN view during CONN view generation. The files are used during rail analysis
functions such as power network analysis or PrimeRail to improve accuracy by placing
current sinks of hard macros into the locations described in the current source files.
By default, this command does not generate current source files.
-skip_via mask_names
Does not extract the connectivity through the specified vias.
By default, the command extracts the connectivity through via1 to via11 (metal1 to
metal12).
-connview_skip_cell cell_names
Specifies the child cells to be excluded from CONN view generation.
By default, all child cells are included.
-csf_skip_cell cell_names
Specifies the child cells to be excluded from current source file generation.
By default, all child cells are included.
-layer_text mask_names_text
Specifies the metal mask names with the name or number of the layers used for text that
identify the corresponding metal layer geometries. If all text layers match the geometry
layers, this option is not needed.
The format of the layer text is
mask_name:layer_name_or_number
For example, to use layer 32 to identify metal2 geometries and layer 31 to identify metal3
geometries, use the following option:
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-layer_text {metal2:32 metal3:31}
DESCRIPTION
This command invokes the Hercules connectivity engine to generate the connectivity
(CONN) view and current source files for nonstandard cells.
Nonstandard cells, such as hard macros, can have significant effects on voltage drop and
electromigration at the full-chip level. The power consumption of these cells or the power
and ground routing that exists inside these cells could allow voltage to flow through the cells
to other regions of the chip. It is therefore necessary to be able to consider the internal
power and ground network and power consumption of these types of cells during IR drop
analysis.
This command combines the values of the routing and power usage into a single construct
that rail analysis tools such as power network analysis or PrimeRail can access. The
construct consists of the following two parts:
•
Connectivity (CONN) view
The CONN view represents the power and ground networks inside the cell.
•
Current source file
The current source file is an ASCII file that records where current (and therefore power)
is drawn inside the cell.
Note:
You should close the library and cell of interest before running this command. The number
of cells printed in each Hercules command is limited to 300 to prevent the Hercules parser
from breaking.
Multicorner-Multimode Support
This command is not supported in a multi-scenario design flow.
EXAMPLES
The following example generates a CONN view and current source files for the
TS1GE256X16M4 design in the ts1ge256x16m4_lib library, using the VDD power net and
the VSS ground net.
prompt> create_connview -library ts1ge256x16m4_lib \
-design TS1GE256X16M4 -power_nets VDD -ground_nets VSS \
-generate_csf
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The following example shows generates a CONN view and current source files for the
TS1GE256X16M4 in the ts1ge256x16m4_lib library, using the VDD power net. During
CONN view generation, the tool skips vias via2 and via3, skips child cells S1B100W10_V4
and S1B100W10_V1_5, and uses layer 5 as metal1 and layer 12 as metal2.
prompt> create_connview -library ts1ge256x16m4_lib \
-design TS1GE256X16M4 -power_nets VDD -skip_via {via2 via3} \
-connview_skip_cell {S1B100W10_V4 S1B100W10_V1_5} \
-layer_text {metal1:5 metal2:12}
SEE ALSO
analyze_fp_rail(2)
synthesize_fp_rail(2)
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create_custom_wire
Creates custom wires for the specified nets.
SYNTAX
status create_custom_wire
[-start_command |
-add_point point | -delete_point | -end_points |
-end_command | -undo]
[-nets collection_of_nets]
[-horizontal_layer layer]
[-horizontal_width distance]
[-horizontal_pitch distance]
[-vertical_layer layer]
[-vertical_width distance]
[-vertical_pitch distance]
[-set_of_layers list_of_layers_with_options]
[-override filename]
[-mark_as strap | ring]
[-start_at low_end | high_end]
[-switch_end_at_turning true | false]
[-skip_count int]
[-multi_via_size int]
[-extend_first true | false]
[-extend_last true | false]
[-snap_to_track true | false]
[-look_inside_std_cell true | false]
[-reverse_net_order true | false]
[-draw_bbox_vias true | false]
[-show_detailed_info true | false]
[-honor_route_guides true | false]
[-extend_first_to_boundaries true | false]
[-extend_last_to_boundaries true | false]
Data Types
collection_of_nets
mark_type
start_type
list_of_layers_with_options
layer
file_name
distance
create_custom_wire
collection
string
string
list
string
string
distance
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ARGUMENTS
-start_command
Starts the mouse interaction mode.
-add_point point
Adds a mouse point to process.
-delete_point
Deletes the last mouse point.
-end_points
Commits the point input and enables the undo operation.
-end_command
Ends the command.
-undo
Removes the last committed wires and vias.
-nets collection_of_nets
Specifies the nets. You can specify a maximum of 2 nets.
-horizontal_layer layer
Specifies the name or number of the horizontal metal layer.
If you do not specify this option, the tool uses first horizontal metal layer in the
technology file.
-horizontal_width distance
Specifies the minimum width for the horizontal layer.
-horizontal_pitch distance
Specifies the pitch of the horizontal layer.
-vertical_layer layer
Specifies the name or number of the vertical metal layer.
If you do not specify this option, the tool uses first vertical metal layer in the technology
file.
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-vertical_width distance
Specifies the minimum width for the vertical layer.
-vertical_pitch distance
Specifies the pitch of the vertical layer.
-mark_as strap | ring
Marks the created wires and vias as the specified type.
The default is ring.
-set_of_layers list_of_layers_with_options
Specifies the layers on which to create wires.
You specify the list of layers with options in the following format:
{layer horizontal|vertical width true|false ...}
The parameter is a list of layer, horizontal or vertical flags, width, and boolean flags,
which tell the tool to search targets on the specified layers.
You specify the layer either with the layerNumber or maskName from the technology file.
-override file_name
Specifies the name of the file that defines override values for the width and pitch values
specified by other options.
An override must be specified on one single line and has one of the following formats:
net_number width pitch
(net_number1 netnumber2 ...) width pitch
-start_at low_end | high_end
Specifies whether to start at the low or high end of the net when creating a wire.
The default is low_end.
-switch_end_at_turning true | false
Specifies whether to switch ends when turning.
The default is false.
-skip_count int
Specifies the number of nets that are skipped during a direction change.
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-multi_via_count int
Specifies the minimum number of via cuts.
The default is 1.
-extend_first true | false
Specifies whether to extend the wire from the first point entered.
The default is false.
-extend_last true | false
Specifies whether to extend the last bit of a bus.
The default is false.
-snap_to_track true | false
Specifies whether to create the wire on the wire track.
The default is false.
-look_inside_std_cell true | false
Specifies whether to create vias to connect wires to pins inside standard cells.
The default is false.
-reverse_net_order true | false
Specifies whether to reverse the order of the bus bits.
The default is false.
-draw_bbox_vias true | false
Specifies whether to draw only the bounding box of the via.
The default is true.
-show_detailed_info true | false
Specifies whether to show the width and increasing length number dynamically for each
net.
The default is false.
-honor_route_guides true | false
Specifies whether to consider the variable routing rule defined for the nets.
The default is false.
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-extend_first_to_boundaries true | false
Specifies whether to extend the first created wire and generate a pin at the boundary.
The default is false.
-extend_last_to_boundaries true | false
Specifies whether to extend the last created wire and generate a pin at the boundary.
The default is false.
DESCRIPTION
Creates a wire between the specified points. Because this is an interactive command, you
must start the GUI before using it. To start the GUI, use the gui_start command.
You can change the internal application of DRC rules by using the
set_preroute_drc_strategy command.
To remove wire segments, use the create_custom_wire -undo command.
EXAMPLES
The following example creates a custom wire shape and then uses the undo operation to
remove it.
prompt> gui_start
prompt> create_custom_wire -start_command
prompt> set_preroute_drc_strategy -drc_off \
-min_layer METAL -max_layer METAL5
prompt> create_custom_wire -add_point {100.00 100.100}
prompt> create_custom_wire -add_point {200.00 100.100}
prompt> create_custom_wire -end_points
prompt> create_custom_wire -undo
prompt> create_custom_wire -end_command
SEE ALSO
set_preroute_drc_strategy(2)
gui_start(2)
create_custom_wire
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create_die_area
Creates the die area for the current design.
SYNTAX
status create_die_area
-boundary {boundary_points_list}
Data Types
boundary_points_list
list
ARGUMENTS
-boundary {boundary_points_list}
Specifies the boundary of the die area.
If the points list is two elements, the points define the lower-left and upper-right
coordinates of a rectangular die area. The format is {{llx lly} {urx ury}}.
If there are more than two points, the points define a polygon. The format is {{x_0 y_0}
{x_1 y_1} ... {x_0 y_0}}
The coordinate unit size is specified in the technology file.
DESCRIPTION
The create_die_area command creates the die area for the current design.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates the die area with an L-shape by defining a polygon:
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prompt> create_die_area -boundary {{0 0} {0 400} {200 400} {200 200} \
{400 200} {400 0} {0 0}}
SEE ALSO
get_die_area(2)
remove_die_area(2)
create_die_area
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create_differential_group
Defines a differential group of nets.
SYNTAX
status create_differential_group
-group group_name
-nets nets
Data Types
group_name
nets
string
collection
ARGUMENTS
-group group_name
Specifies the name of the differential group.
-nets nets
Specifies the nets to associate with the differential group.
DESCRIPTION
Defines a differential group with the specified name that contains the specified nets. Each
group can have two or more nets. After you define the differential groups, you can route
them by using the route_differential or route_rdl_differential command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates a differential group named "dgroup" that contains nets that
begin with the prefix "net_diff".
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prompt> create_differential_group -group dgroup -nets
[get_nets net_diff*]
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\
SEE ALSO
route_differential(2)
route_rdl_differential(2)
create_differential_group
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create_drc_error
Creates an error record for an error type in the default error type class, for the purpose of
creating an error view.
SYNTAX
collection create_drc_error
-error_view error_view
-type error_type
[-status error | fixed | ignored | waived]
[-info description]
-rectangles rectangles | -polygons polygons
[-net net]
[-layer layer]
[-required required]
[-actual actual]
[-route_types route_types]
Data Types
error_view
error_type
description
rectangles
polygons
net
layer
required
actual
route_types
list or collection of one item
string
string
list
list
list or collection of one item
list or collection of one item
float
float
list
ARGUMENTS
-error_view error_view
Specifies the error view in which to create the error record. You must specify exactly one
error view.
-type error_type
Specifies the error type for the new error object. This is a required argument.
You can specify the error type by using the ID or name of the error type. Although the
command accepts error types from any error type class, you should use this command
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only for error types in the default error type class. For error types in nondefault error type
classes, you should use the class-specific error object creation commands. For more
information, see the DESCRIPTION section.
-status error | fixed | ignored | waived
Sets the current status of this error. If you do not specify this option, the status is set to
error.
-info description
Provides a full description of this error. The description string must have a length of less
than 1024. If the description contains space characters, enclose it in quotation marks. If
you do not specify this option, the description is left empty.
-rectangles rectangles
Specifies the rectangle shapes to add to the error object. The coordinates for the
rectangle shapes are in microns. You can specify one or more rectangles as a list of
rectangles:
{rectangle rectangle rectangle ...}
where each rectangle is specified as a list of four coordinates:
{llx lly urx ury}
which represent the x- and y-coordinates of the lower-left and upper-right corners of the
rectangle.
You can also define a rectangle as a list of two points for the lower-left and upper-right
corners, where a point is a list of two coordinates:
{{llx lly} {urx ury}}
The -rectangles and -polygons options are mutually exclusive; you must specify
exactly one of these options.
-polygons polygons
Specifies the polygon shapes to add to the error object. The coordinates for the polygon
shapes are in microns. You can specify one or more polygons as a list of polygons:
{polygon polygon polygon ...}
where each polygon is a list of points
{point point point ...}
and each point is a list that contains the x and y coordinates:
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{x y}
The list of polygons might look like this:
{{{ax1 ay1} {ax2 ay2} ... {axn ayn}} {{bx1 by1} {bx2 by2} ... {bxn byn}}}
The -rectangles and -polygons options are mutually exclusive; you must specify
exactly one of these options.
-net net
Specifies the net associated with the shapes. You can specify the net by providing a
collection that contains the net or by specifying the net name. You cannot use wildcards
in the net name.
If you do not specify this option, the error has no associated net.
-layer layer
Specifies the layer associated with the shapes. You can specify the layer by using the
layer name from the technology file or by using the get_layers command.
If you do not specify this option, the error has no associated layer.
-required required
Specifies the required value in microns, if applicable. The required value is the value
expected by DRC checker, but violated in the error. For example, for a minimum spacing
violation, the required value is DRC required spacing value that is violated.
The argument is ignored if it is less than or equal to 0.0.
If you do not specify this option, it is undefined.
-actual actual
Specifies the actual value in microns, if applicable. The actual value is the real value that
violates the required value in the error. For example, for a minimum spacing violation,
the actual value is the real spacing value that violates the DRC required spacing.
The argument is ignored if it is less than 0.0.
If you do not specify this option, it is undefined.
-route_types route_types
Specifies the route types associated with the error.
You can specify one or more of the following route type keywords: user_enter,
signal_route, signal_route_global, pg_ring, clk_ring, pg_strap, clk_strap,
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pg_macro_io_pin_conn, pg_std_cell_pin_conn, clk_zero_skew_route, bus,
shield, shield_dynamic, and clk_fill_track.
If you do not specify this option, the route type is undefined for the error.
DESCRIPTION
This command creates a new error object of the specified error type, for the purpose of
creating an error view. Every error object must be associated with exactly on error type. The
error type association is made when the error object is created and cannot be changed.
Therefore, you must create an error type before you can create error objects of that type.
When an error type is created with the create_drc_error_type command, it is associated
with one of the following error type classes: default, open, openlocator, short, or spacing.
An error object is interpreted based on its error type class.
In addition to the create_drc_error command, the tool also provides the following error
object creation commands, which are specific to the nondefault error type classes:
create_open_drc_error, create_open_locator_drc_error, create_short_drc_error, and
create_spacing_drc_error.
To ensure that the error objects are correct-by-construction, you should use the
create_drc_error command only to create error objects with the default error type class. To
create error objects with a nondefault error type class, use the appropriate class-specific
error object creation command.
If successful, the create_drc_error command returns a collection that contains the new
error object.
EXAMPLES
The following example opens an error view named mydesign_mydrc.err, creates an error
type named Overlap, and then creates an error record of the Overlap type, which is
associated with one shape on the RV layer:
prompt> set cellId [open_mw_cel -not_as_current mydesign_mydrc.err]
{mydesign_mydrc}
prompt> set typeId [create_drc_error_type -name Overlap \
-info "Metal and blockage overlap" -error_view $cellId]
1024
prompt> create_drc_error -type $typeId -error_view $cellId \
-layer RV -rectangles {{574.0700 430.3600 578.9700 433.4400}}
{1280}
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SEE ALSO
add_drc_error_detail(2)
create_drc_error_type(2)
create_open_drc_error(2)
create_open_locator_drc_error(2)
create_short_drc_error(2)
create_spacing_drc_error(2)
get_drc_errors(2)
list_drc_error_types(2)
remove_drc_error(2)
report_drc_error_type(2)
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create_drc_error_type
Creates an error type record for custom error reporting, in preparation for error object
creation with the create_drc_error or similar command.
SYNTAX
integer create_drc_error_type
-name type_name
-error_view mw_error_view
[-class default | open | openlocator | short | spacing]
[-info description]
[-status error | fixed | ignored | waived]
[-level err_type_level]
Data Types
type_name
mw_error_view
description
err_type_level
string
list or collection
string
string
ARGUMENTS
-name type_name
Specifies the name of the error type. The specified name must be unique in a
case-insensitive comparison with existing names. This is a required argument.
-error_view mw_error_view
Specifies the error view in which to create the error type record. You must specify
exactly one error view.
-class default | open | openlocator | short | spacing
Specifies the error class for the created error type. The class name keywords are
case-insensitive.
The open error type class is for violations where routed shapes for a net are not fully
connected and is described as two or more disjoint nodes of connected net shapes.
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The openlocator error type class is for violations that describe opens in nets, not as
disjoint nodes of connected net shapes, but as the potential connection flyline for an
open.
The short error type class is for violations where routed shapes overlap in the same
area in a layer.
The spacing error type class is for violations where two routed shapes in the same layer
violate a spacing rule.
If you specify this option, error objects of this type receive the data interpretation specific
to the error class.
If you do not specify this option or if you specify default, error objects of this type receive
the default data interpretation.
-info description
Provides a full text description of the created error type. If the description string contains
space characters, enclose it in quotation marks. If you do not specify this option, the
description is left empty.
-status error | fixed | ignored | waived
Sets the default status for errors of the created error type. If you do not specify this
option, the default status is error.
-level err_type_level
Specifies the severity level of the created error type. The value must be one of Error,
"Critical Error", "Major Error", "Moderate Error", "Minor Error", or
Recommendation. If you do not specify this option, the severity level is Error.
DESCRIPTION
This command creates a new error type with the specified type name. Every error object
must be associated with exactly one error type. The error type association is made when the
error object is created and cannot be changed. Therefore, you must create an error type
before you create error objects of that type.
If successful, the command returns the data object ID of the new error type record.
Otherwise, the command returns 0. You can use the returned ID for the error type record in
the -type option that identifies the type when you create an error object of that type. You can
also identify the error type by using the type name specified as the argument to the -name
option.
The IC Compiler error browser allows you to display error objects grouped by type. Error
objects can also be sorted or filtered by type. Error types can be declared to be in a type
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class. Error objects of a type in a type class receive the data interpretation that is specific to
that type class. The nondefault type classes are open, openlocator, short, and spacing.
To create an error type in a nondefault type class, use the -class option. The error type
association with a type class is made when the error type is created, and cannot be
changed.
EXAMPLES
The following example opens an error view named mydesign_mydrc.err and creates an
error type named Overlap in the default type class:
prompt> set cellId [open_mw_cel -not_as_current mydesign_mydrc.err]
{mydesign_mydrc}
prompt> create_drc_error_type -name Overlap \
-info "Metal and blockage overlap" -error_view $cellId
1024
The following example adds a type named "Via Spacing" that is in the spacing type class to
an error view named mydesign_err.err:
prompt> create_drc_error_type -name "Via Spacing" -class "spacing" \
-error_view "mydesign_err.err" \
-info "Via corner spacing" -error_view $cellId
1025
SEE ALSO
list_drc_error_types(2)
report_drc_error_type(2)
create_drc_error(2)
create_open_drc_error(2)
create_open_locator_drc_error(2)
create_short_drc_error(2)
create_spacing_drc_error(2)
get_drc_errors(2)
create_drc_error_type
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create_edit_group
Creates a new edit group from the specified objects.
SYNTAX
collection create_edit_group
[-name string]
objects
ARGUMENTS
-name string
Specifies the optional name of the edit group.
The name must be unique if specified. If you do not specify a name, the tool generates
a unique name for the edit group.
objects
Specifies the collection of objects to be placed in the edit group.
Objects are limited to those objects that are movable and do not already belong to
another edit group.
If any specified object is invalid, no edit group is created.
DESCRIPTION
Creates a new edit group from the specified objects.
If the command completes successfully, a collection containing the created edit group is
returned.
EXAMPLES
The following example creates an edit group from the current selection.
prompt> set gr [create_edit_group [get_selection]]
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SEE ALSO
get_edit_groups(2)
remove_edit_groups(2)
report_edit_groups(2)
create_edit_group
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create_floorplan
Creates a floorplan with a chip boundary, core, rows, and wire tracks.
SYNTAX
status create_floorplan
[-control_type aspect_ratio | width_and_height | boundary]
[-core_aspect_ratio ratio]
[-core_utilization ratio]
[-core_width width]
[-core_height height]
[-use_vertical_row]
[-no_double_back]
[-start_first_row]
[-flip_first_row]
[-left_io2core distance]
[-right_io2core distance]
[-bottom_io2core distance]
[-top_io2core distance]
[-keep_macro_place]
[-keep_std_cell_place]
[-min_pad_height]
[-pad_limit]
[-keep_io_place]
Data Types
ratio
width
height
distance
float
float
float
float
ARGUMENTS
-control_type aspect_ratio | width_and_height | boundary
Specifies how the command sizes the core area of the floorplan. The aspect_ratio
control type specifies the area based on the ratio of the core height divided by the core
width. The width_and_height control type specifies the area based on the true
dimensions of the core. The boundary control type specifies the area based on the
place and route boundary of the current design. The default control type is aspect_ratio.
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-core_aspect_ratio ratio
Specifies the aspect ratio for the floorplan. The aspect ratio is the height divided by the
width. For example, an aspect ratio of 1.00 specifies a square core area with equal width
and height. An aspect ratio of 3.00 specifies a height that is three times the width. An
aspect ratio of 0.50 specifies a width that is two times the height. Note that the specified
aspect ratio is only a target. The tool creates the floorplan with the actual core area
perimeter as close as possible to the specified aspect ratio.
-core_utilization ratio
Specifies the utilization for the core area. The utilization is the total area of the core
occupied by all standard cells and macro cells divided by the total core area. You can
specify a utilization value between 0 and 1. The cell area includes all standard and
macro cells. For example, a core utilization of 0.8 specifies that 80 percent of the core
area is used for cell placement and 20 percent is available for routing. This option is only
valid when you specify the -control_type option.
-core_width width
Specifies the width of the core area. The unit is in microns. This option is only valid when
you specify the -control_type width_and_height option.
-core_height height
Specifies the height of the core area. The unit is in microns. This option is only valid
when you specify the -control_type width_and_height option.
-use_vertical_row
Specifies that the command places cell rows vertically in the core area. If you do not
specify this option, the command places cell rows horizontally in the core area.
-no_double_back
Specifies that the command places pairs of cell rows without flipping one row in each
pair. By default, the command flips one cell row in each cell row pair.
-start_first_row
Specifies that cell row pairing begins at the bottom of the core area for horizontally
placed cell rows or the left side of the core area for vertically placed cell rows. This option
is mutually exclusive with the -no_double_back option. If this option is not used, cell
row pairing might or might not begin at the very first row. The cell row pairing does not
begin at the very first row when the wire track creation forces to have gaps between row
pairs.
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-flip_first_row
Specifies that the command flips the first row at the bottom of the core area for
horizontally placed cell rows, or the leftmost row for vertically placed cell rows. This
option is mutually exclusive with the -no_double_back option.
-left_io2core distance
Specifies the distance between the left side of the core area and the right side of the
closest terminal or pad. The unit is in microns.
-right_io2core distance
Specifies the distance between the right side of the core area and the left side of the
closest terminal or pad. The unit is in microns.
-bottom_io2core distance
Specifies the distance between the bottom side of the core area and the top side of the
closest terminal or pad. The unit is in microns.
-top_io2core distance
Specifies the distance between the top side of the core area and the bottom side of the
closest terminal or pad. The unit is in microns.
-keep_macro_place
Specifies that the command keeps the placement of macro cells and does not move
them.
-keep_std_cell_place
Specifies that the command keeps the placement of standard cells and does not move
them.
-min_pad_height
Specifies that the die area is based on the minimum pad height. Generally speaking, die
area becomes smaller because bigger pads will overlap the core.
-pad_limit
Specifies that the command places pads with no space between pads.
-keep_io_place
Specifies that the command keeps the location of terminals and pads, even if you
previously specified I/O constraints by using theread_io_constraints command.
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DESCRIPTION
The create_floorplan command performs floorplanning on the current design. Before
running this command, you must open a physical design by using the open_mw_cel
command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates a floorplan using the default settings:
prompt> open_mw_cel top -lib design
{top}
prompt> create_floorplan -control_type aspect_ratio \
-core_utilization 0.7
1
SEE ALSO
set_pad_physical_constraints(2)
create_floorplan
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create_fp_block_shielding
Creates signal shielding for plan groups and soft macros.
SYNTAX
status create_fp_block_shielding
[-inside_boundary]
[-outside_boundary]
[-side_list {left | right | top | bottom}]
[-metal_layers layer_list]
[-shielding_width factor_or_distance]
[-width_in_microns]
[-tie_to_net net]
[-block_level]
[objects]
Data Types
layer_list
factor_or_distance
net
objects
collection
float
collection of one
collection
ARGUMENTS
-inside_boundary
Creates shielding on the inside of plan groups and/or soft macros. If you do not specify
the -inside_boundary and -outside_boundary options, the command creates
shielding on both the interior and exterior sides of the plan groups and/or soft macros.
By default, this option is off (false).
-outside_boundary
Creates shielding on the outside of the plan groups and/or soft macros. If you do not
specify the -inside_boundary and -outside_boundary options, the command creates
shielding on both the interior and exterior sides of the plan groups and/or soft macros.
By default, this option is off (false).
-side_list {left | right | top | bottom}
Indicates the sides on which to create shielding rectangles. By default, the command
creates shielding on all sides of the plan groups and/or soft macros. In the case of a
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rectilinear boundary, all boundary edges which are along the top of the boundary (face
up) will be shielded with "top" rectangles, and those edges which are along the left side
(and face left) will be shielded with "left" shielding rectangles, etc. etc..
-metal_layers layer_list
Specifies a layer object collection indicating the metal layers on which to create
shielding. By default, the command determines the appropriate layers for shielding on
each side. See the explanation in DESCRIPTION for detailed information on automatic
layer selection by the command.
-shielding_width factor_or_distance
Specifies the factor or distance by which the shielding width is multiplied. The shielding
width is determined by a metal layer's pitch, unless you use the -width_in_microns
option, in which case the command interprets the value of factor_or_distance as an
absolute distance in microns. By default, the factor_or_distance value is 3.0.
-width_in_microns
Interprets the value of the -shielding_width option as an absolute distance value in
micron units. By default, this option is off (false).
-tie_to_net net
All shielding rectangles are tied logically to the single net represented by the net
collection. This must be a single net (VSS, VSS1, GND, VDD, etc...) in the collection,
that is, what would be returned by [get_nets -all {VSS}]. By default, all shielding
rectangles are logically floating.
-block_level
This option is for creating block shielding from the inside of a soft macro cell opened for
edit. This will only create shielding around the inside of the cell boundary outline. No
shielding will be created outside of the cell boundary outline. The options
-inside_boundary and -outside_boundary are meaningless and disregarded in the
context of the use of this option. Also, the object_list object collection is meaningless and
disregarded when this option is specified. All other options may be used in combination
with this option. By default, this option is off (false).
objects
Specifies a collection of plan groups and/or soft macros on which to apply route
blockages for signal integrity shielding. By default, the command processes all plan
groups and soft macros.
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DESCRIPTION
This command creates signal shielding for plan groups and soft macros. The shielding is
used to maintain signal integrity when routing a design. Shielding takes the form of metal
rectangles around the boundary of a block. These rectangles are regular route metal
rectangles, subject to all metal layer rules. When shielding would block access to pins along
a side edge on the same layer as the shielding, the shielding is segmented to allow access
to the pins. You can specify a list of plan groups/soft macros for the command to process.
By default, it processes all plan groups/soft macros.
The command can create shielding on the inside and/or outside of a plan group/soft macro.
When the command creates inside shielding for soft macros, it is created at the child level.
The command accepts a list of sides indicating on where to create shielding. By default, the
command creates shielding on all sides, based on the rules provided below.
You can specify the metal layers on which to create shielding. By default, the command
creates shielding on each metal layer and uses each layer's preferred direction to determine
on which sides to create the shielding. For example, if metal 2's preferred direction is
horizontal, the command creates metal 2 blockage rectangle blockages on the top and
bottom sides of the plan group/soft macro. The argument to this option is a collection of layer
objects returned by the get_layer command (for example, [get_layer {metal1 metal2}]).
You can specify the width of the shielding to the command. By default, the command uses
a width of 3 times the route pitch for each respective metal layer. The pitch is multiplied by
the multiplier that you specify by using the -shielding_width option or by the default
multiplier of 3. You can flag the command to use an absolute width of microns instead of the
multiplier by specifying the -width_in_microns option.
The rectangles the command creates are marked in the database, so that they can be
recognized for deletion by the remove_fp_block_shielding command.
If it is desired for the shielding rectangles to be tied to a particular power or ground net, then
the -tie_to_net option may be used to specify which power or ground net to use. This option
may be used by passing a single net name or a net collection of 1, such as may be returned
by the [get_nets -all {VSS}] command. This functionality only logically ties the rectangles to
a particular power or ground net. It is beyond the scope of this option to physically connect
to power or ground.
To create shielding from inside of a soft macro that is opened in IC Compiler for edit, the
-block_level option may be called to create block shielding around the inside of the
opened-for-edit soft macro's inside cell outline boundary.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
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EXAMPLES
The following example creates metal route blockages (shielding) on the top and left interior
sides on metal layers 2, 6, and 7.
prompt> create_fp_block_shielding inside_boundary \
-side_list {top left} \
-metal_layers [get_layer {metal2 metal6 metal7}]
The following example creates exterior metal route blockages (shielding) of width 5 microns
on the specified list of soft macro and plan groups. This example allows the command to
determine on which metal layers and sides to create shielding.
prompt> create_fp_block_shielding -outside_boundary \
-shielding_width 5.0 -width_in_microns [get_cells \
{macro1 macro2 plan_group2 plan_group_8}]
This example creates shielding rectangles on inside and outside boundaries of all plan
groups and soft macros and assigns them to the ground net VSS. This example allows the
command to determine on which metal layers and sides to create shielding.
prompt> create_fp_block_shielding outside_boundary \
-tie_to_net [get_nets -all {VSS}]
This example creates shielding rectangles on the inside of the cell boundary outline of the
cell that is opened for edit. This example allows the command to determine on which metal
layers and sides to create shielding.
prompt> create_fp_block_shielding -block_level
SEE ALSO
get_layers(2)
remove_fp_block_shielding(2)
create_fp_block_shielding
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create_fp_blockages_for_child_hardmacro
Creates routing blockages for hard macros within soft macros.
SYNTAX
status create_fp_blockages_for_child_hardmacro
list_of_softmacros
Data Types
list_of_softmacros
collection
ARGUMENTS
list_of_softmacros
This is a collection of the soft macros which will be processed. If not supplied all soft
macros will be processed.
DESCRIPTION
For each soft macro processed each hard macro within that soft macro will have a
placement blockage created in the top level. This placement blockage will have the same
boundary as the hard macro.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
Create placement blockages for hard macros in all soft macros.
create_fp_blockages_for_child_hardmacro
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create_fp_group_block_ring
Creates a block ring for a group of hard macro blocks.
SYNTAX
status create_fp_group_block_ring
-nets nets
[-horizontal_ring_layer layer]
[-horizontal_ring_offset offset]
[-horizontal_ring_spacing spacing]
[-horizontal_ring_width width]
[-vertical_ring_layer layer]
[-vertical_ring_offset offset]
[-vertical_ring_spacing spacing]
[-vertical_ring_width width]
[-horizontal_strap_width width]
[-horizontal_strap_layer layer]
[-vertical_strap_width width]
[-vertical_strap_layer layer]
[-output_directory directory]
[-skip_strap]
Data Types
nets
layer
offset
spacing
width
directory
collection of list
string
float
float
float
string
ARGUMENTS
-nets nets
Specify the power or ground nets to perform group block ring creation. This is a required
option.
-horizontal_ring_layer layer
Specify the horizontal ring layer, where the default is the top-most horizontal layer.
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-horizontal_ring_offset offset
Specify the horizontal ring offset in microns, where the offset is measured from the block
boundary but not from the PNS region. The default is the minimum spacing between
hard macro blocks and the ring defined in the technology file.
-horizontal_ring_spacing spacing
Specify the horizontal ring spacing in microns between power and ground nets. The
default is minimum spacing defined in the technology file.
-horizontal_ring_width width
Specify the horizontal ring width in microns. The default is the minimum width defined in
the technology file.
-vertical_ring_layer layer
Specify the vertical ring layer, where the default is the top-most vertical layer.
-vertical_ring_offset offset
Specify the vertical ring offset in microns, where the offset is measured from the block
boundary but not from the PNS region. The default is the minimum spacing between
hard macro blocks and the ring defined in the technology file.
-vertical_ring_spacing spacing
Specify the vertical ring spacing in microns between power and ground nets. The default
is minimum spacing defined in the technology file.
-vertical_ring_width width
Specify the vertical ring width in microns. The default is the minimum width defined in the
technology file.
-horizontal_strap_width width
Specify the horizontal strap width, where the default is the minimum width defined in the
technology file. The straps are inserted inside the narrow regions between neighboring
macro blocks.
-horizontal_strap_layer layer
Specify the horizontal strap layer, where the default is the top-most horizontal layer.
-vertical_strap_width width
Specify the vertical strap width, where the default is the minimum width defined in the
technology file. The straps are inserted inside the narrow regions between neighboring
macro blocks.
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-vertical_strap_layer layer
Specify the vertical strap layer, where the default is the top-most vertical layer.
-output_directory directory
Specify the directory in which to store the group block ring creation results. The default
is ./pna_output.
-skip_strap
Specify not to insert straps between hard macro blocks; only rings are created around
the group of macro blocks.
DESCRIPTION
This command creates power and ground rings around a set of hard macro blocks with
either rectangular or rectilinear boundaries. Straps are also inserted between neighboring
blocks unless the -skip_strap option is specified.
A PNS region must first be created by using the set_fp_rail_region_constraints
command. This PNS region provides a guideline for the group block ring contour. For
example, a rectilinear region is needed as a guideline if a rectilinear ring is desired for a
group of hard macro blocks. The specified PNS region is first shrunk based on all hard
macro blocks inside this region to obtain the group block boundary while maintaining the
region topology. Next, a ring is created around the group block boundary.
Channels between neighboring blocks are identified for strap insertion. The straps are
inserted in the middle of each channel unless it is too narrow.
Sandwich-type rings (multiple rings in one layer) are supported by specifying multiple nets,
for example -net {VDD VDD VSS}. Straps in channels are still created as a pair of power
and ground straps in this case.
You can preview the group block ring result before actually committing the group block ring
by using the commit_fp_group_block_ring command.
Remove the PNS region constraint after group block ring creation and before power network
synthesis.
EXAMPLES
The following example shows how to create power (VDD) ground (VSS) group block ring for
those hard macro blocks inside the predefined PNS region. The rings are created on
horizontal layer METAL5 with a ring width of 1.0 micron and an offset of 0.6 micron and on
vertical layer METAL6 with a ring width of 1.0 micron and an offset of 0.6 microns. The
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spacing between horizontal (or vertical) power and ground rings is 0.5 micron. The straps
between neighboring blocks are created on horizontal layer METAL3 with a strap width of
0.5 micron and on vertical layer METAL4 with a strap width of 0.5 micron.
prompt> create_fp_group_block_ring
-nets {VDD VSS}
-horizontal_ring_layer METAL5
-horizontal_ring_offset 0.6
-horizontal_ring_spacing 0.5
-horizontal_ring_width 1.0
-vertical_ring_layer METAL6
-vertical_ring_offset 0.6
-vertical_ring_spacing 0.5
-vertical_ring_width 1.0
-horizontal_strap_width 0.5
-horizontal_strap_layer METAL3
-vertical_strap_width 0.5
-vertical_strap_layer METAL4
SEE ALSO
set_fp_rail_region_constraints(2)
commit_fp_group_block_ring(2)
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create_fp_pins
Creates pins for the specified list of child ports, or creates plan group pins for the specified
list of plan group hierarchical ports.
SYNTAX
collection create_fp_pins
-layer layer
[-side side_num_or_name]
[-width width]
[-step step_num]
[-at location | -offset offset]
ports
Data Types
layer
side_num_or_name
width
step_num
location
offset
ports
layer
string
real
integer
point
real
collection
ARGUMENTS
-layer layer
Specifies the layer name on which to create the pin.
-side side_num_or_name
Specifies a side number or name. If you do not specify the -side option, you must specify
the -at option to create off-edge pins at or near the specified location. If the value
specified is a number (not a name), then it must be a positive integer that starts from 1.
Given any shape (rectangular or rectilinear), the lower left-most vertical edge is the
starting edge (side number 1). The side number of the next edge, going clockwise, is 2,
and so on.
-width width
Specifies the pin width of a pin to be created.
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If user specifies a width that is smaller than the minimum width defined in the technology
file, the tool will enlarge the pin width to honor minimum width rule in the technology file.
At the same time, a warning will be issued to indicate that the pin width has been revised
to honor the minimum width rule.
The pin depth will be the same as the pin width, unless this value violates the minimum
length or minimum area defined in the technology rule. In the latter case, the pin depth
will be enlarged to honor both rules.
-step step_num
Specifies a wire track step for multiple pins to be created. The default is 1.
-at location
Specifies the location of the first pin to be created. For multiple off-edge pin creation, the
first pin is located at the wiretrack intersection closest to the -at location, other pins are
distributed clockwise around the first pin. The -at and -offset options are mutually
exclusive.
The location coordinate is the center of the pin.
-offset offset
Specifies the offset from the start of an edge. The -at and -offset options are mutually
exclusive.
The offset value is measured from the start point of the edge to the center of the pin.
ports
Specifies child ports or plan group hierarchical ports for which to create pins. The ports
argument is a collection of pins.
DESCRIPTION
This command creates pins for the specified list of child ports or plan group hierarchical
ports. Snapping is done automatically using global snap settings.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates pins for all child ports of soft macro u2_large on layer M1.
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prompt> set pins [get_pins -of [get_cell u2_large]]
prompt> set layer [get_layer M1]
prompt> create_fp_pins -side 1 -layer $layer -offset 10 $pins
The following example creates plan group pin plangroup1/p1 for hierarchical port p1 on the
plangroup1 plan group on the metal3 layer with a width of 0.24 at location {100.00 100.00}.
prompt> set pins [get_pins plangroup1/p1]
prompt> set layer [get_layer metal3]
prompt> create_fp_pins -layer $layer -at {100.00 100.00} -width 0.24
$pins
SEE ALSO
get_nets(2)
get_pins(2)
create_fp_pins
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create_fp_placement
Places hard macros and leaf cells.
SYNTAX
status create_fp_placement
[-effort low | high]
[-max_fanout positive_integer]
[-no_hierarchy_gravity]
[-no_legalize]
[-incremental placement_string]
[-congestion_driven]
[-timing_driven]
[-num_cpus number_of_cpus]
[-plan_groups collection_of_plan_groups]
[-voltage_areas collection_of_voltage_areas]
[-optimize_pins]
[-consider_scan]
[-write_placement_blockages]
[-exploration]
Data Types
positive_integer
placement_string
number_of_cpus
collection_of_plan_groups
collection_of_voltage_areas
integer
string
integer
collection
collection
ARGUMENTS
-effort low | high
Sets the level of effort to apply to creating the virtual flat placement. Use this option to
tradeoff the quality of virtual flat placement results (QoR) and the amount of CPU
runtime spent performing a flat placement. Valid values for this option are low and high.
For fast results that provide good, nonoverlapping hard macro locations, set the effort to
low. For higher quality placement, but with an increase in CPU runtime, set the effort to
high. The default is low.
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-max_fanout positive_integer
Specifies that placement ignores nets having a fanout higher than the number specified
by positive_integer. The wire length of nets with a fanout greater than the specified value
are not considered in placement. The default is 512.
-no_hierarchy_gravity
Prevents the grouping of cells within the same hierarchal block. The default is to group
together cells of the same hierarchal block. In general, grouping by using hierarchy
gravity results in better placement because designs tend to partition well along the
hierarchy boundaries. However, you can specify -no_hierarchy_gravity if you know
that the partitioning by hierarchy should be prevented.
-no_legalize
Creates a placement that is not legalized. The default is to create a legalized placement.
-incremental placement_string
Performs an incremental placement of the current placement. The valid values are all,
top_level_cells, plan_groups, and voltage_areas. Use all to perform an incremental
placement on the entire design. Use top_level_cells to run an incremental placement
on top-level cells that do not belong to any plan group or voltage area. Use the
plan_groups keyword together with the -plan_groups option to perform incremental
placement to the cells within the specified plan groups. Use voltage_areas together
with the -voltage_areas option to perform incremental placement to cells within the
specified voltage areas. The default is for the command to run placement without using
previous placement results.
-congestion_driven
Enables congestion-driven placement mode. By default, the command runs with
congestion-driven placement mode off.
-timing_driven
Enables timing-driven placement mode. By default, the command runs with
timing-driven placement mode off.
-num_cpus number_of_cpus
Specifies the number of CPUs used in parallel during coarse placement. The
number_of_cpus is an integer value that is less than or equal to the number of free
CPUs on your machine and greater than or equal to 1. By default, the command uses 1
CPU. Only one IC Compiler-PSYN license is checked out.
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-plan_groups collection_of_plan_groups
Refines the placement for the specified plan groups. This option is valid only for plan
groups placed inside the core area when you specify the -incremental plan_groups
option.
-voltage_areas collection_of_voltage_areas
Performs refine placement for the specified voltage areas. This option is valid only for
voltage areas placed inside the core area when you specify the -incremental
voltage_areas option.
-optimize_pins
Performs simultaneous placement and pin assignment for block level designs. When
you specify this option, IC Compiler performs two iterations of placement and pin
assignment to obtain the best quality placement and pin assignment.
-consider_scan
Considers scan chain connections during placement.
-write_placement_blockages
Writes all the internally-computed blockages during placement to a file named
design_planning_blockages.tcl in the working directory. The file includes blockages due
to channels that are narrower than the sliver size and macro padding blockages. If the
design_planning_blockages.tcl file already exists in the working directory, it is
overwritten.
-exploration
Performs very fast placement intended for hierarchical floorplan exploration. The goal of
this placement is to provide good initial locations of hierarchies during the flat placement
stage and good quality placement of the top level, interface and macros cells during the
hierarchical placement stage when plan groups are in the core. All other cells are placed
very coarsely. Placement is not legalized. This option is incompatible with the
-timing_driven, -congestion_driven and -incremental options.
DESCRIPTION
This command performs a virtual flat placement of standard cells and hard macros. It
provides you with an initial placement for creating a floorplan to determine the relative
locations and shapes of the top-level physical blocks of a flat design with no placed plan
groups or voltage areas. For designs with plan groups or voltage areas placed, it provides
you with a refined placement that honors the exclusive plan groups and voltage areas.
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When you use the -optimize_pins option, the result is a virtual flat placement as described
above, and a pin assignment that respects the pin constraints. In this mode, the placer
understands the pin constraints such as side constraints. The overall quality of placement
and pin assignment is better than running each placement separately. Use this option at the
block level, not at the chip level or with I/O pads.
To further control how the tool performs course placement, set the
placer_max_cell_density_threshold variable. The variable specifies whether cells are
evenly distributed or more tightly clustered together.
Support for Relative Placement Groups
This command places relative placement groups. Both macros and standard cells are
supported in the relative placement groups. For more information about relative placement
groups, see the man page for the create_rp_group command.
Multicorner-Multimode Support
This command uses information from all active scenarios.
EXAMPLES
The following example command creates congestion-driven placement.
prompt> create_fp_placement -congestion_driven
SEE ALSO
set_fp_placement_strategy(2)
report_fp_placement(2)
set_fp_macro_options(2)
set_fp_macro_array(2)
create_rp_group(2)
add_to_rp_group(2)
placer_max_cell_density_threshold(3)
create_fp_placement
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create_fp_plan_group_padding
Creates padding for the specified plan groups.
SYNTAX
status create_fp_plan_group_padding
[-internal_widths {left right top bottom}]
[-external_widths {left right top bottom}]
[plan_groups]
Data Types
left
right
top
bottom
plan_groups
float
float
float
float
collection or list
ARGUMENTS
-internal_widths {left right top bottom}
Specifies the explicit per-side widths of the internal paddings in microns. You can use
this option if you want to specify non-uniform internal padding widths. Specify all 4 sides
in the indicated sequence. By default, this option is {1 1 1 1}.
-external_widths {left right top bottom}
Specifies the explicit per-side widths of the external paddings in microns. You can use
this option if you want to specify non-uniform external padding widths. Specify all 4 sides
in the indicated sequence. By default, this option is {0 0 0 0}.
plan_groups
Applies padding to the specified plan groups. By default, the tool applies padding to all
plan groups in the current design.
DESCRIPTION
This command performs plan group padding, which sets placement blockages on the
internal and external edges of the boundary. The internal padding is equivalent to the
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core-to-boundary spacing of the committed block. External padding is equivalent to macro
padding. Internal padding should be set to at least 1 on all blocks to allow room for pins and
pin routing. You can use the -internal_widths and -external_widths options to create
non-uniform padding widths on a per-side basis. All values are in microns.
To remove plan group padding, use the remove_fp_plan_group_padding command.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example creates internal plan group padding on a per-side basis:
prompt> create_fp_plan_group_padding\
-internal_widths {2 3 4 5}\
-external_widths {6 7 8 9}
SEE ALSO
remove_fp_plan_group_padding(2)
create_fp_plan_group_padding
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create_fp_virtual_pad
Creates virtual power or ground pads for power network analysis and power network
synthesis.
SYNTAX
status create_fp_virtual_pad
[-nets nets]
[-layer layer]
[-point {x y}]
[-load_file pad_file]
[-save_file output_pad_file]
Data Types
nets
layer
x
y
pad_file
output_pad_file
collection
string
float
float
string
string
ARGUMENTS
-nets nets
Specifies the name of the power or ground nets on which to perform network analysis.
You can specify only one net at a time.
-layer layer
Specifies the layer name of a pad that you want to create.
-point {x y}
Specifies a virtual pad point {x y} to place. The x and y values are float numbers. Units
are microns.
-load_file pad_file
Specifies the file name containing a list of virtual power pads.
Chapter 1:
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-save_file output_pad_file
Specifies the file name to save virtual power pads.
DESCRIPTION
Creates virtual power or ground pads based on the specified net or based on the contents
of the virtual pads file.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following command creates virtual pads based on the net names contained in the file
named pads.txt
prompt> create_fp_virtual_pad -load_file pads.txt
SEE ALSO
create_fp_virtual_pad
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create_freeze_silicon_leq_change_list
Maps ECO cells that do not have a matching spare cell to logically equivalent spare cells
and writes out an ECO change list for these cells. This command can be used only in a
freeze silicon ECO flow.
SYNTAX
status create_freeze_silicon_leq_change_list
-cells sorted_eco_cells
-output leq_file_name
[-vth_groups vth_group_list
| -drive_strength higher | lower]
Data Types
sorted_eco_cells
leq_file_name
vth_group_list
collection
string
list
ARGUMENTS
-cells sorted_eco_cells
Specifies the ECO cells to map to logically equivalent spare cells. The specified ECO
cells must have an eco_status attribute of eco_add. The order in which you specify the
ECO cells sets the priority of the ECO cell to spare cell mapping.
This is a required option.
-output leq_file_name
Specifies the name of the generated ECO change list file.
This is a required option.
-vth_groups vth_group_list
Maps to spare cells in the specified threshold voltage groups. If there are several spare
cells available with a threshold voltage in the specified groups, the tool chooses the
spare cell closest to the ECO cell.
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This option is mutually exclusive with the -drive_strength option; you can specify only
one. If you do not specify either option, the tool selects the closest logially equivalent
spare cell.
-drive_strength higher | lower
Maps to spare cells with higher or lower driver strength. If there are several spare cells
available, the tool chooses the spare cell closest to the ECO cell.
This option is mutually exclusive with the -vth_groups option; you can specify only one.
If you do not specify either option, the tool selects the closest logially equivalent spare
cell.
DESCRIPTION
The create_freeze_silicon_leq_change_list command first runs a fast placement of the
ECO cells and then maps the ECO cells that do not have a matching spare cell to logically
equivalent spare cells and writes out an ECO change list for these cells.
The default mapping cost is distance. To change the mapping cost, use the -vth_groups or
-drive_strength option.
This command is used in user-driven freeze silicon QoR tuning flow. The typical usage is as
follows:
1. Apply the ECO changes.
2. Analyze the ECO cells and spare cells by using the check_freeze_silicon command.
3. Map the ECO cells that do not have exactly matching spare cells to logically equivalent
spare cells and generate a change list file by using the
create_freeze_silicon_leq_change_list command.
4. Apply the change list by using the source or eco_netlist command.
5. Get the modified ECO cells.
6. Map the ECO cells to spare cells by using the place_freeze_silicon command.
You can use the -vth_groups or -drive_strength option to find alternative logically
equivalent spare cells that have a different threshold voltage or driver strength, respectively,
based on your timing requirements.
This command does not support gate array ECO cells.
PREREQUISITES
Before running this command, you must apply the ECO changes and insert and place the
spare cells.
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Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example shows the usage of the command.
prompt> create_freeze_silicon_leq_change_list -cells $sorted_eco_cells \
-output leq.tcl
prompt> source leq.tcl
prompt> set modified_eco_cells \
[get_cells -hier -filter "eco_status==eco_add"]
prompt> place_freeze_silicon -trial_map_spare_cells \
-cells $modified_eco_cells
prompt> place_freeze_silicon -map_spare_cells_only
The following example shows a generated change list file.
******************************************************************
# ICC create_freeze_silicon_leq_change_list leq change list
# Design : CORE
# Version: G-2012.06-SP4
# Date
: Mon Sep 24 20:45:23 2012#
******************************************************************
#################
# Cell cell_inst
################
#map reference: NAND2 to module: NAND2_leq
#
#Verilog equivalent:
# module NAND2_leq ( A, B, X ) ;
#
input
A, B;
#
output X;
#
wire
n;
#
AND2 leq_cell_1 ( .A(A), .B(B), .X(n) );
#
INV2 leq_cell_2 ( .A(n), .X(X) );
#endmodule
remove_cell freeze_silicon cell_inst
create_cell hier cell_inst NAND2_leq
current_instance
cell_inst
create_port dir “in” { A, B }
create_port dir “out” { X }
create_cell freeze_silicon leq_cell_1 AND2
create_cell freeze_silicon leq_cell_2 INV2
create_net
{ A, B, X, n }
connect_net A { A leq_cell_1/A }
connect_net B { B leq_cell_1/B }
connect_net X { leq_cell_2/X }
connect_net n { leq_cell_1/X, leq_cell_2/A }
current_instance
connect_net $org_net_A cell_inst/A
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connect_net $org_net_B cell_inst/B
connect_net $org_net_X cell_inst/X
######################
# Cell $instance_name2
######################
...
The following example shows the usage of the -vth_groups and -drive_strength options.
prompt> create_freeze_silicon_leq_change_list -cells $eco_cells \
-output leq_vth_higher.tcl -vth_groups high_vth
prompt> create_freeze_silicon_leq_change_list -cells $eco_cells \
-output leq_ds_higher.tcl -drive_strength higher
SEE ALSO
place_freeze_silicon(2)
map_freeze_silicon(2)
check_freeze_silicon(2)
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create_generated_clock
Creates a generated clock object.
SYNTAX
string create_generated_clock
[-name clock_name]
[-add]
source_objects
-source master_pin
[-master_clock clock]
[-divide_by divide_factor
| -multiply_by multiply_factor]
[-duty_cycle percent]
[-invert]
[-preinvert]
[-edges edge_list]
[-edge_shift edge_shift_list]
[-combinational]
[-comment comment_string]
Data Types
clock_name
source_objects
master_pin
clock
divide_factor
multiply_factor
percent
edge_list
edge_shift_list
comment_string
string
list
list
string
integer
integer
float
list
list
string
ARGUMENTS
-name clock_name
Specifies the name of the generated clock. If you do not use this option, the clock
receives the same name as the first clock source specified in the -source option. If you
specify the -add option, you must use the -name option and the clocks with the same
source must have different names.
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-add
Specifies whether to add this clock to the existing clock or to overwrite. Use this option
to capture the case where multiple generated clocks must be specified on the same
source, because multiple clocks fan into the master pin. Ideally, one generated clock
must be specified for each clock that fans into the master pin. If you specify this option,
you must also use the -name option.
Defining multiple clocks on the same source pin or port causes longer runtime and
higher memory usage than a single clock, because the synthesis timing engine explores
all possible combinations of launch and capture clocks. Use the set_false_path
command to disable unwanted clock combinations. This option is ignored by default,
unless multiple clocks analysis is enabled by setting the
timing_enable_multiple_clocks_per_reg variable to true.
source_objects
Specifies a list of ports or pins defined as generated clock source objects.
-source master_pin
Specifies the master clock pin, which is either a master clock source pin or a pin in the
fanout of the master clock and driving the generated clock definition pin. The clock
waveform at the master pin is used for deriving the generated clock waveform.
-master_clock clock
Specifies the master clock to be used for this generated clock if multiple clocks fan into
the master pin.
-divide_by divide_factor
Specifies the frequency division factor. If the divide_factor is 2, the generated clock
period is twice as long as the master clock period.
-multiply_by multiply_factor
Specifies the frequency multiplication factor. If the multiply_factor is 3, the period is one
third as long as the master clock period.
-duty_cycle percent
Specifies the duty cycle (in percent), if frequency multiplication is used. This is a number
between 0 and 100. The duty cycle is the high pulse width.
-invert
Inverts the generated clock signal regardless of whether the sense of the source clock
on the master pin is unate or non-unate (in case of frequency multiplication and division).
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-preinvert
Creates a generated clock based on the inverted clock signal only when the source
clock on the master pin has a non-unate sense, or the generated clock will not be
inverted just as this option has not been specified. The difference between the -invert
option and the -preinvert option is that the -invert option first creates the generated
clock, then inverts the signal, and the -preinvert option first inverts the signal, and then
creates the generated clock signal.
-edges edge_list
Specifies a list of positive integers that represents the edges from the source clock that
are to form the edges of the generated clock. The edges are interpreted as alternating
rising and falling edges and each edge must be not less than its previous edge. The
number of edges must be an odd number and not less than 3 to make one full clock
cycle of the generated clock waveform. The first edge must be greater than or equal to
1. For example, 1 represents the first source edge, 2 represents the second source
edge, and so on.
-edge_shift edge_shift_list
Specifies a list of floating-point numbers that represents the amount of shift, in library
time units, that the specified edges are to undergo to yield the final generated clock
waveform. The number of edge shifts specified must be equal to the number of edges
specified. The values can be positive or negative, with positive indicating a shift later in
time, and negative a shift earlier in time. For example, 1 indicates that the corresponding
edge is to be shifted by 1 library time unit.
-combinational
Specifies that the source latency paths for this type of generated clock only includes the
logic where the master clock propagates along combinational paths. The source latency
paths will not flow through sequential element clock pins, transparent latch data pins, or
the source pins of other generated clocks.
-comment comment_string
Allows the command to accept a comment string. The tool honors the annotation and
preserves it with the SDC object so that the exact string is written out when the
constraint is written out when you use the write_sdc or write_script command. The
comment remains intact through the synthesis, place-and-route, and timing-analysis
flows.
DESCRIPTION
The create_generated_clock command creates a generated clock object in the current
design. This command defines a list of objects as generated clock sources in the current
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design. You can specify a pin or a port as a generated clock object. The command also
specifies the clock source from which it is generated. The advantage of using this command
is that whenever the master clock changes, the generated clock changes automatically.
The generated clock can be created as a frequency-divided clock with the -divide_by
option, a frequency-multiplied clock with -multiply_by, or an edge-derived clock with
-edges. In addition, the frequency-divided or frequency-multiplied clock can be inverted with
the -invert option. The shifting of edges of the edge-derived clock is specified with the
-edge_shift option. The -edge_shift option is used for intentional edge shifts and not for
clock latency. If a generated clock is specified with a divide_factor that is a power of 2 (1, 2,
4, ...), the rising edges of the master clock are used to determine the edges of the generated
clock. If the divide_factor is not a power of 2, the edges are scaled from the master clock
edges.
Using create_generated_clock on an existing generated_clock object overwrites the
attributes of the generated_clock object.
The generated_clock objects are expanded to real clocks at the time of analysis.
The following commands can reference the generated_clock:
set_clock_latency
set_clock_uncertainty
set_propagated_clock
set_clock_transition
To display information about generated clocks, use the report_clock command.
Multicorner-Multimode Support
This command uses information from the current scenario only.
EXAMPLES
The following example creates a frequency -divide_by 2 generated clock:
prompt> create_generated_clock -divide_by 2 \
-source CLK [get_pins test]
The following example creates a frequency -divide_by 3 generated clock. If the master
clock period is 30, and the master waveform is {24 36}, the generated clock period is 90 with
waveform {72 108}.
prompt> create_generated_clock -divide_by 3 \
-source CLK [get_pins div3/Q]
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The following example creates a frequency -multiply_by 2 generated clock with a duty
cycle of 60%:
prompt> create_generated_clock -multiply_by 2 \
-duty_cycle 60 -source CLK [get_pins test1]
The following example creates a frequency -multiply_by 3 generated clock with a duty
cycle equal to the master clock duty cycle. If the master clock period is 30, and the master
waveform is {24 36}, the generated clock period is 10 with waveform {8 12}.
prompt> create_generated_clock -multiply_by 3 \
-source CLK [get_pins div3/Q]
The following example creates a generated clock whose edges are edges 1, 3, and 5 of the
master clock source. If the master clock period is 30, and the master waveform is {24 36},
the generated clock period is 60 with waveform {24, 54}.
prompt> create_generated_clock -edges {1 3 5} \
-source CLK [get_pins test2]
The following example shows the generated clock in the previous example with each
derived edge shifted by 1 time unit. If the master clock period is 30, and the master
waveform is {24 36}, the generated clock period is 60 with waveform {25, 55}.
prompt> create_generated_clock -edges {1 3 5} \
-edge_shift {1 1 1} -source CLK [get_pins test2]
The following example creates an inverted clock:
prompt> create_generated_clock -divide_by 2 -invert
SEE ALSO
check_timing(2)
create_clock(2)
get_generated_clocks(2)
remove_generated_clock(2)
report_clock(2)
set_clock_latency(2)
set_clock_transition(2)
set_clock_uncertainty(2)
set_propagated_clock(2)
timing_enable_multiple_clocks_per_reg(3)
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create_lib_track
Creates wire tracks for a library.
SYNTAX
status create_lib_track
[-lib lib_name]
[-tile tile_name]
[-dir dir_list]
[-offset offset_list]
Data Types
lib_name
tile_name
dir_list
offset_list
string
string
list
list
ARGUMENTS
-lib lib_name
Specify library where wire track is created. If not specified, the wire tracks will be created
in current open library.
-tile tile_name
Specifies the tile where the wire track information is stored. Default value is "unit" and
therefore the information will stored in unitTile.CEL.
-dir dir_list
Specifies preferred routing direction for each routing layer one by one. The list is
enclosed in parenthesis {}. The format is -dir {poly V/H metal1 V/H metal2 V/H ...} Where
'V' for "vertical"and 'H' for"horizontal". Both mask name and user-defined layer name of
routing layers can be used in the list.
-offset offset_list
Specifies offset for each routing layer one by one. The list is enclosed in parenthesis {}.
The format is -offset {poly value metal1 value metal2 value ...} The unit of value is
micron. Both mask name and user-defined layer name of routing layers can be used in
the list.
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DESCRIPTION
This command creates wire tracks for a library. If some routing directions or offsets in routing
layers and poly layer are not set, Default value will be used. Incremental setting mode is
supported. The recommended value of offset is one half of the pitch. A status indicating
success or failure is returned.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
EXAMPLES
The following example sets routing directions and offset for opened library "design", which
has 9 routing layers. unitTile will store the wire track information.
prompt> open_mw_lib design
prompt> create_lib_track -dir {poly
metal3 H metal4 V metal5 H metal6 V
metal9 H} -offset {poly 0.00 metal1
metal3 0.14 metal4 0.14 metal5 0.14
metal8 0.14 metal9 0.14
1
V metal1 H metal2 V \
metal7 H metal8 V \
0.14 metal2 0.16 \
metal6 0.14 metal7 0.14 \
SEE ALSO
create_mw_lib(2)
open_mw_lib(2)
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create_logic_net
IC Compiler parses, but ignores, this command.
SYNTAX
status create_logic_net
net_name
Data Types
net_name
string
ARGUMENTS
net_name
Specifies the name of the net to create. You must use a simple name.
DESCRIPTION
This command has no function in IC Compiler. It is parsed in the UPF file, but ignored.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
create_net(2)
create_logic_port(2)
connect_logic_net(2)
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create_logic_port
IC Compiler parses, but ignores, this command.
SYNTAX
string create_logic_port
port_name
[-direction in | out | inout]
Data Types
port_name
string
ARGUMENTS
port_name
Specifies the name of the port to create. You must use a simple name.
-direction in | out | inout
Specifies the direction of the port.
The default is in.
DESCRIPTION
This command has no function in IC Compiler. It is parsed in the UPF file, but ignored.
Multicorner-Multimode Support
This command has no dependency on scenario-specific information.
SEE ALSO
create_port(2)
create_logic_net(2)
connect_logic_net(2)
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create_macro_fram
Creates a FRAM view of a macro cell by extracting blockage, pin, and via information from
the CEL view.
SYNTAX
status create_macro_fram
[-library_name library_name]
[-cell_name cell_name]
[-preserve_all_metal_blockage]
[-routing_blockage_output_layer metBlk | rGuide | zeroG]
[-treat_all_blockage_as_thin_wire]
[-treat_metal_blockage_as_thin collection_of_layers]
[-extract_blockage_by_block_core_with_margin
{layer_and_margin_value_pairs}]
[-extract_blockage_by_merge_with_threshold {layer_thresholdtriplets}]
[-identify_macro_pin_by_pin_text]
[-extract_pin_connectivity_through collection_of_layers]
[-poly_pin_text_layers {list_of_layers}]
[-m1_pin_text_layers {list_of_layers}]
[-m2_pin_text_layers {list_of_layers}]
[-m3_pin_text_layers {list_of_layers}]
[-m4_pin_text_layers {list_of_layers}]
[-m5_pin_text_layers {list_of_layers}]
[-m6_pin_text_layers {list_of_layers}]
[-m7_pin_text_layers {list_of_layers}]
[-m8_pin_text_layers {list_of_layers}]
[-m9_pin_text_layers {list_of_layers}]
[-m10_pin_text_layers {list_of_layers}]
[-m11_pin_text_layers {list_of_layers}]
[-m12_pin_text_layers {list_of_layers}]
[-m13_pin_text_layers {list_of_layers}]
[-m14_pin_text_layers {list_of_layers}]
[-m15_pin_text_layers {list_of_layers}]
[-nwell_pin_text_layers {list_of_layers}]
[-pwell_pin_text_layers {list_of_layers}]
[-deep_nwell_pin_text_layers {list_of_layers}]
[-deep_pwell_pin_text_layers {list_of_layers}]
[-bm1_pin_text_layers {list_of_layers}]
[-bm2_pin_text_layers {list_of_layers}]
[-bm3_pin_text_layers {list_of_layers}]
[-pin_must_connect_area_layer_number {layer_and_number_name_pairs}]
[-auto_pin_must_connect_area_threshold {layer_and_threshold_pairs}]
[-extract_via_within_pin_area_only]
[-extract_via_on_layer collection_of_layers]
[-feedthrough_layers {layer_and_number_name_pairs}]
[-create_mask_constraint_route_guides true | false]
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Data Types
library_name
cell_name
collection_of_layers
layer_and_margin_value_pairs
list_of_layers
layer_and_number_name_pairs
layer_and_threshold_pairs
string
string
collection
list
list
list
list
ARGUMENTS
-library_name library_name
Specifies the name of the library containing the macro cell. If this option is not used, then
the currently open library is used.
-cell_name cell_name
Specifies the name of the macro cell for which to create a FRAM view. The CEL view
must already exist in the library. If this option is not used, then the currently open cell is
used.
-preserve_all_metal_blockage
Preserves all system metal blockage layers as they exist in the CEL view and converts
all system metal blockage layers to real metal layers. By default, the extraction process
trims system metal blockages around pins as needed to prevent design rule violations.
Using this option, the system metal blockages are retained exactly, so be sure that the
preserved system metal blockages do not violate the design rules.
-routing_blockage_output_layer metBlk | rGuide | zeroG
Specifies the type of output layer produced in the FRAM view to represent routing
blockages: metBlk (system metal blockage), rGuide (route guide), or zeroG (zero
spacing route guide). The router recognizes all three types of layers as blockage and will
not route over them. The default output layer is metBlk (system metal blockage). The
router treats system metal blockage as thin metal for all design rule checking.
-treat_all_blockage_as_thin_wire
This option works only for non-standard cells. It causes real metal blockages to be
treated as thin wire for design rule checking purposes. By default, real metal blockages
are treated as fat wire if fat or thin wire if thin. The spacing rules can be different for thin
versus fat wire, which affects the spacing required between routes and real metal
blockages. This option setting also affects the trimming of real metal blockages during
extraction. The extraction process trims real metal blockages around pin areas to allow
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connections to be routed to the pins without violating the spacing to the real metal
blockage areas.
-treat_metal_blockage_as_thin collection_of_layers
Use this option when system metal blockage covers all of the cell in a specific layer and
you want the router to keep a spacing of at least minSpacing between the route wire and
the macro cell boundary in that layer. With this option, the command shrinks the system
metal blockage by
(max value in fatTblSpacing) - (minSpacing)
and converts it to real metal blockage. This option still treats the real metal blockage as
fat metal but reshapes the real metal blockage to cause the router to keep a spacing of
at least minSpacing between the route wire and the macro cell boundary in that layer.
These are the mask layers that can specified in this option:
poly m1 m2 m3 ... m15
-extract_blockage_by_block_core_with_margin {layer_and_margin_value_pairs}
Causes each specified layer to be extracted with a core blockage that covers the whole
macro area for that layer, with a specified margin between the blockage area and the
macro cell boundary. The extraction process trims back the blockage away from pins in
the same layer, leaving space between the pins and blockage according to the spacing
rule for that layer, treated as either thin or fat wire, depending on the related option
settings.
Specify each layer name with a single value as in the following example:
{poly 0 m1 -1 m2 0 m3 0.45 ... }
The value for each layer can be -1, 0, or a positive number. The value -1 means do not
create a core blockage; this is the same as omitting the layer name from the list. The
number 0 means use the default margin, which is calculated as twice the spacing value
defined for the layer in the technology file. (This spacing value is the largest of the
following values in the technology file: MinSpacing, fatThinMinSpacing, and the largest
value in the fatTblSpacing table.)
A positive number sets the margin explicitly to that value. The margin is the distance
between the blockage and the macro boundary.
These are the mask layers that can specified in this option:
poly m1 m2 m3 ... m15
If neither -extract_blockage_by_block_core_with_margin nor
-extract_blockage_by_merge_with_threshold is used to specify the type of blockage
to generate for a layer, the command creates a core blockage that covers the whole
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macro area for that layer, except for the trimming of blockage away from pins in the
same layer according to the spacing rules for the layer. This type of blockage extraction
is called "Block All".
-extract_blockage_by_merge_with_threshold {layer_thresholdtriplets}
Causes each specified layer to be extracted as it exists in the CEL view, but with
merging of geometries that are close together. If two nearby geometries are within the
specified spacing threshold, the extraction process fills in the space between the two
shapes, thereby creating a single larger shape for the blockage in the FRAM view.
Specify each layer name with two values. The first value is the X (horizontal) spacing
threshold and the second value is the Y (vertical) spacing threshold. For example,
{m1 3 3 m2 4 4 m3 4 4 ... }
One possible value to use for the spacing thresholds is (2*MinSpacing + MinWidth),
which is the narrowest space that could allow a single route to pass between two shapes
in that layer.
If both thresholds are set to zero for a layer, the geometries are extracted as they exist
in the CEL view without merging.
These are the mask layers that can specified in this option:
poly m1 m2 m3 ... m15
-identify_macro_pin_by_pin_text
Identifies macro pins by considering the text layers associated with the pin layers. By
default, when this option is not used, the extraction process assumes that the macro cell
was created by Synopsys tools and already contains pin data.
When this option is used, the following create_macro_fram command options are also
used to further specify the pin extraction process:
-extract_pin_connectivity_through
-poly_pin_text_layers
-m1_pin_text_layers
-m2_pin_text_layers
-m3_pin_text_layers
...
-m15_pin_text_layers
-nwell_pin_text_layers
-pwell_pin_text_layers
-deep_nwell_pin_text_layers
-deep_pwell_pin_text_layers
-bm1_pin_text_layers
-bm2_pin_text_layers
-bm3_pin_text_layers
Otherwise, these options have no effect.
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-extract_pin_connectivity_through collection_of_layers
Specifies the cut layers through which to extract pin connectivity. Using this option
causes the command to traverse connectivity through the specified cut and via layers to
identify connections between pins on different layers. By default, the tool does not
traverse connectivity through cut layers.
These are the mask layers that can specified in this option:
polyCont v1 v2 v3 ... v14 bv1 bv2
-poly_pin_text_layers {list_of_layers}
Specifies the text layers associated with poly-silicon pins. If the pin text is on the same
layer as the pin geometry, you do not need to use this option. However, if the pin text is
on one or more layers different from the pin geometry layer, use this option to identify the
associated text layers. The layers can be identified by the layer name or layer number.
-m1_pin_text_layers {list_of_layers}
Specifies the text layers associated with m1 pins. If the pin text is on the same layer as
the pin geometry, you do not need to use this option. However, if the pin text is on one
or more layers different from the pin geometry layer, use this option to identify the
associated text layers. The layers can be identified by the layer name or layer number.
-m2_pin_text_layers {list_of_layers}
Specifies the text layers associated with m2 pins.
-m3_pin_text_layers {list_of_layers}
Specifies the text layers associated with m3 pins.
-m4_pin_text_layers {list_of_layers}
Specifies the text layers associated with m4 pins.
-m5_pin_text_layers {list_of_layers}
Specifies the text layers associated with m5 pins.
-m6_pin_text_layers {list_of_layers}
Specifies the text layers associated with m6 pins.
-m7_pin_text_layers {list_of_layers}
Specifies the text layers associated with m7 pins.
-m8_pin_text_layers {list_of_layers}
Specifies the text layers associated with m8 pins.
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-m9_pin_text_layers {list_of_layers}
Specifies the text layers associated with m9 pins.
-m10_pin_text_layers {list_of_layers}
Specifies the text layers associated with m10 pins.
-m11_pin_text_layers {list_of_layers}
Specifies the text layers associated with m11 pins.
-m12_pin_text_layers {list_of_layers}
Specifies the text layers associated with m12 pins.
-m13_pin_text_layers {list_of_layers}
Specifies the text layers associated with m13 pins.
-m14_pin_text_layers {list_of_layers}
Specifies the text layers associated with m14 pins.
-m15_pin_text_layers {list_of_layers}
Specifies the text layers associated with m15 pins.
-nwell_pin_text_layers {list_of_layers}
Specifies the text layers associated with N-well bias Power/Ground pins. If the pin text is
on the same layer as the pin geometry, you do not need to use this option. However, if
the pin text is on one or more layers different from the pin geometry layer, use this option
to identify the associated text layers. The layers can be identified by the layer name or
layer number.
-pwell_pin_text_layers {list_of_layers}
Specifies the text layers associated with P-well bias Power/Ground pins.
-deep_nwell_pin_text_layers {list_of_layers}
Specifies the text layers associated with deep N-well bias Power/Ground pins.
-deep_pwell_pin_text_layers {list_of_layers}
Specifies the text layers associated with deep P-well bias Power/Ground pins.
-bm1_pin_text_layers {list_of_layers}
Specifies the text layers associated with bm1 (backside metal 1) pins.
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-bm2_pin_text_layers {list_of_layers}
Specifies the text layers associated with bm2 (backside metal 2) pins.
-bm3_pin_text_layers {list_of_layers}
Specifies the text layers associated with bm3 (backside metal 3) pins.
-pin_must_connect_area_layer_number {layer_and_number_name_pairs}
Specifies for each connection layer the associated spare layer being used to designate
the required via connection area within the pin geometry. By default, the router can
connect a wire to any part of a large pin. To restrict the connection to a subarea of a
large pin, specify the subarea polygon on a spare layer and specify the spare area
associated with each connection layer using this option. List the connection layers and
associated spare layers as in the following example:
{m1 31 m2 32 m3 33 ...}
You can specify each layer by its layer number or layer name. These are the mask
layers that can specified in this option:
poly m1 m2 m3 ... m15
-auto_pin_must_connect_area_threshold {layer_and_threshold_pairs}
Specifies the width threshold (in unit defined in the technology file) for automatic
determination of the required via connection area within the pin geometry. By default, the
router can connect a wire to any part of a large pin. To automatically restrict the
connection to a subarea of a pin with an irregular shape, use this option and specify
each layer and its associated width threshold. For example,
{m1 0.56 m2 0.63 m3 0.63 ... }
Areas within a pin having a width smaller than the threshold are excluded from allowing
a via connection to be made. For a fat pin, the first-dimension fat contact threshold is
used to calculate the allowed connection area, so that the router does not drop a fat
contact on the thin part of a fat pin.
These are the mask layers that can specified in this option:
poly m1 m2 m3 ... m15
-extract_via_within_pin_area_only
Causes the extraction process to extract vias existing in pin areas in the CEL view. By
default, no vias are extracted from the CEL view. Use this option when you want the
router to be aware of any vias existing in a pin when it makes a connection to the pin.
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-extract_via_on_layer collection_of_layers
Specifies the mask layer or layers from which to extract vias. By default, no vias are
extracted from the CEL view. Use this option when you want the router to be aware of
any vias on the corresponding mask layer when it makes a connection to the pin. These
are the mask layers that can specified in this option:
polyCont v1 v2 ... v14 bv1 bv2
-feedthrough_layers {layer_and_number_name_pairs}
Specifying a feedthrough layer for a metal layer causes the create_macro_fram
command to keep the metal la