DESIGN OF 2 STAGE OTA(OPERATIONAL TRANSCONDUCTANCE AMPLIFIER)
USING Gm/Id TECHNIQUE
A Minor Project Report Submitted to the National Institute of Technology Karnataka-Surathkal in
partialfulfillment of requirements for the award of degree in
Master of Technology
in
VLSI Design
by
Vishal Saini (222VL038)
Under the guidance of
Dr.REKHA S.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
NITK Surathkal
April 2023
1
CERTIFICATE
This is to certify that the Minor Project report entitled DESIGN OF 2 STAGE OTA(OPERATIONAL
TRANSCONDUCTANCE AMPLIFIER) USING
Gm/Id
TECHNIQUE submitted
by
Vishal
Saini (222VL038), to the NITK Surathkal in partial fulfillment of the M.Tech. degree in VLSI Design
is a bona fide record of the work carried out by them under our guidance and supervision. This report
in any form has not been submitted to any other University or Institute for any purpose.
Project Guide
Dr. Rekha S.
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TABLE OF CONTENTS
Sr.No.
1.
TOPIC
PAGE NO.
1.1.
LITERATURE REVIEW
Drawbacks of traditional design and process
4
4
1.2.
Preparation of Gm/Id Charts
4
1.3.
Using Gm/Id charts for circuit design
5
Mosfet Characterization and Simulation Setup
6
2.
2.1. Procedure and Results
6
3.
2 Stage OTA Design
10
3.1. Problem Statement
10
3.2. Schematic
11
3.4 Design and Methodology
11
3.5 Design Summary
12
4
13
Testing of OTA
4.1 Gain Margin and Phase Margin
13
4.2 With load and without load
14
5
15
References
3
Chapter 1
Literature Review
1.1
Drawbacks of traditional design process
Traditional methods of analog circuit design are predominantly based on the square law expression relating
the drain current (Id) of MOSFET with the gate overdrive voltage (Vgs− Vth). The shortcomings of this
method include neglecting several other second-order effects as enlisted below:
1. Drain induced barrier lowering, reverse drain induced barrier lowering.
2. Dependence on VT H of a MOSFET on its dimensions.
3. Channel length modulation
and many more. As a result, there is significant departure of the simulation results from the hand calculations
at sub-micron process nodes.
The gm/Id method aims to address this issue and arrive at better correspondence of hand calculations and
simulation results. The method involves detailed characterization of the MOSFET and prepare lookup
tables to aid hand-calculation.
1.2
Preparation of gm/Id charts
The gm/Id method is based on the following figures of merit:
1. Transit Frequency(fT ) :
gm
2
. This figure is an indication of the device bandwidth.
πCgs
2. Intrinsic Gain : gmro or gm/gds. This figure is an indication of the maximum voltage gain that
can be obtained from the device.
3. Transconductance efficiency : gm/Id. This indicates the transconductance obtained per unit drain
current.
In this method, the MOSFET is characterized to obtain the following plots
1. gm versus Vgs
2. Id versus Vgs
3. gm/Id versus Vgs
4. fT versus Vgs
5. gm/gds versus V gs
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Figure 1.1: Flowchart of gm/Id based design process.
1.3
Using gm/Id charts for circuit design
gm/Id of a MOS transistor is nearly independent of its aspect ratio when the gate overdrive voltage Vov(Vgs
— Vth) > 0. Also, its variation is less significant from one technology to another. The typical range of
gm/Id is 5 to 25. While choosing the gm/Id of each device, the following guidelines maybe followed:
1. A small gm/Id can be chosen for the devices whose transconductance doesn’t contribute to gain (e.g.
active loads) or in cases where small area and high speed is desired.
2. A large gm/Id can be chosen for devices whose transconductance contributes to the gain (e.g. input stage
of an amplifier) or in cases where low flicker noise, less mismatch and large voltage swings are desired.
After choosing the gm/Id for a device, Id has to be chosen as per the power budget.
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Chapter 2
MOSFET Characterization
2.1
Simulation Setup
Figure 2.1: Schematic of NMOS characterization simulation setup in LTSpice
Figure 2.2: Schematic of PMOS characterization simulation setup in LTSpice
2.2 Procedure and Results
For obtaining the gm/Id charts, the first step is to plot Id, gm, gm/Id, fT , gm/gds, vovand Id/W versus
Vgs. The figures show the schematic of the simulation setup in LTSpice for NMOS and PMOS.
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Figure 2 Id vs Vgs for NMOS
Figure 1 Id vs Vgs for NMOS
Figure 3 Id vs Vds for PMOS
Figure 4 Id vs Vgs for PMOS
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Figure 5 Gm/Id vs Vgs
Figure 6 Id/W vs Vgs
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Figure 7 Ft vs Vgs
Figure 8 Gm/Gds vs Vgs
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Chapter 3
Two Stage OTA Design
3.1
Problem Statement
Fig: Basic configuration of 2 Stage OTA
Design a basic two stage OTA based on the following specifications:
Open loop voltage gain ≥
60dB
Unity gain frequency
≥
5 MHz
Phase margin
≥ 75 deg
≤
Power dissipation
2mW
considering VDD = 2.5V, Vss=-2.5V and load capacitance CL=10pF.
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3.2
Schematic
Figure 3.2: LTSpice schematic of two stage OTA
3.3
Design Methodology
1. The starting point of the design is to choose gm/Id for each transistor. It is chosen between 10-20 depending
upon the purpose served by the device in the circuit. But for worst case analysis, we have chosen the maximum
value of gm/Id.
2. The transistors whose transconductance contributes to the gain (M1, M2, M6) need to have a higher
gm/Id.
3. The transistors which act as current source loads (whose 1/gds contributes to the gain) need to
have a lower value of gm/Id.
4. The starting point is chosen as follows: a gm/Id of 32 for M1, M2, M6.
5. The power budget can be used to choose the currents through each transistor.
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3.4
Design Summary
The device sizes and approximate operating conditions as obtained from the previous section are summarised as follows.
Device
L(µm)
W (µm)
M1
1
3
M2
1
3
M3
1
15
M4
1
15
M5
1
4.5
M6
1
94
M7
1
14
M8
1
4.5
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Chapter 4
Testing of the OTA
4.1
Gain Margin and Phase Margin
Magnitude
Response
Phase Response
Figure 4.1: Gain Margin and Phase Margin of OTA
4.1.1
With No Load results
1.DC Gain=77db
2.Phase Margin=132.2°
3.Gain Margin=24db
4.Unity Gain Frequency=672Mhz
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4.1.2
With Load results
1.DC Gain=77db
2.Phase Margin=118.7°
3.Gain Margin=24db
4.Unity Gain Frequency=46.86Mhz
Figure 4.2 Input and Output Voltage Supply
Figure 4.3 Gain of OTA
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Chapter 5
References
1.
Behzad Razavi, ”Design of Analog CMOS Integrated Circuits”, 2ed.
2.
Hafeez K T lectures on gm/Id methodology.
3.
Hesham Omran lecture on ”The gm-Id design methodology
demystified” and accompanying lectureslides.
4.
Sabry, Mostafa N., Hesham Omran, and Mohamed Dessouky. "Systematic design and
optimization of operational transconductance amplifier using gm/ID design
methodology." Microelectronics journal 75 (2018): 87-96.
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