Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ch 7: JFET ( junction field-effect transistor)
In the n-channel JFET the drain is at the upper end, and the
source is at the lower end. Two p-type regions are diffused in the
n-type material to form a channel, and both p-type regions are
connected to the gate
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
VGG sets the reverse-bias voltage between the gate and the
source. The JFET is always operated with the gate-source
reverse-biased. This produces a depletion region along the pn
junction and thus increases its
resistance by restricting the
channel width.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
(Drain to Source current with gate Shorted)
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
For VGS = 0 V (shorting the gate to the source) the value of VDS at
which ID becomes constant (point B) is the pinch-off voltage, VP. A
continued increase in VDS above the pinch off voltage produces an
almost constant drain current. This value of drain current is IDSS
which is the maximum drain current that a specific JFET can
produce, and it is always specified for the condition, VGS = 0 V.
Breakdown occurs when ID begins to increase very rapidly with
any increase in VDS. Breakdown can result in damage to the
device, so JFETs are always operated below breakdown and
within the active region.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 1: For the JFET shown in the figure, VP = 4 V and IDSS = 12
mA. Determine the minimum value of VDD required to put the
device in the constant-current region of operation when VGS = 0 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 2: For a JFET, IDSS = 9 mA and VGS(off) = – 8 V. Determine ID
for VGS = 0 V, – 1 V, and – 4 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
is the change in ID for a given change in VGS with VDS constant
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 3: For a JFET has IDSS = 3 mA, VGS(off) = - 6 V maximum, and
gm0 = 5000 µS. Using these values, determine the forward
transconductance for VGS = -4 V, and find ID at this point.
Solution
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
a JFET operates with its gate-source junction reverse-biased,
which makes the input resistance at the gate very high.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 5: Find VDS and VGS in the shown figure. For the particular
JFET in this circuit, the drain current (ID) is approximately 5 mA.
Solution
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
The basic approach to establishing a JFET bias
point is to determine ID for a desired value of VGS
or vice versa.
Ex 6:
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 7: Determine the value of RS required to self-bias a p-channel
JFET with IDSS = 25 mA and VGS(off) = 15 V. VGS is to be 5 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 8: Select resistor values for RD and RS in
figure shown to set up an approximate
midpoint bias. Use VGS(off) = - 0.5 V and VD =
6 V and IDSS = 1 mA.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 9:
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
MOSFET (metal oxide semiconductor fieldeffect transistor)
the gate is insulated from the channel by a silicon dioxide (SiO2)
layer. The two basic types of MOSFETs are enhancement (E) and
depletion (D).
it has no channel but for n channel device a
+ve gate voltage above a threshold value
induces a channel by creating a thin layer of
–ve charges in the substrate region adjacent
to the SiO2 layer
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 1: Given that ID(on) = 500 mA (minimum) at VGS = 10 V and
VGS(th) = 1 V. Determine the drain current for VGS = 5 V.
Solution
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 2: For a certain D-MOSFET, IDSS = 10 mA and VGS(off) = -8 V.
(a) Is this an n-channel or a p-channel?
(b) Calculate ID at VGS = - 3 V
(c) Calculate ID at VGS = + 3 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
In the voltage divider bias circuit
In the drain-feedback bias circuit there is
negligible gate current and, therefore, no
voltage drop across RG. This makes
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 3: Determine VGS and VDS for the E-
MOSFET circuit shown in the figure. Assume
this particular MOSFET has minimum values of
ID(on) = 200 mA at VGS = 4 V and VGS(th) = 2 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 4: Determine the amount of drain
current in figure shown. The MOSFET
has a VGS(th) = 3 V.
Dr.-Ing. Ahmed Said, PhD in Electrical Engineering, Paderborn University, Germany
Ex 5: Determine the drain-to-source voltage in
the circuit shown in the figure. VGS(off) = - 8 V and
IDSS = 12 mA.