4-1
EJectronk: Devices & Clrcults-1(MU)
Electronic Devices & Circuits-1
Chapter 1 : PN Junction Diode
0.1
OeftM tMmier potential
Ana.:
~ t~ the prese~ce o~ immobile positive and negative ions
on opposite Stdes of the JUnction. an electric tield is created across
tbe ?~on. This ~lc:mc fie!d is known as the "barrier potential"
or 1uncnon potential or cut m voltage. lt has fixed polarities .
Q. 2
Draw symbol of PN Junction Diode .
Ana.:
I
Anode
I
forward biased. Generally a resistance is connected in series with
the diode to limit the current flowing through it. Forward biasing of
a diode is us shown in Pig. l.2(a) and the symbolic representation
is as shown in Pig. l.2(b). The current "lp" is a conventional
current that flows in the circuit due to the forward biasing.
•..····"''j~"·····
Curront
limiting
1'99istor
······:
··...
Cathode
--~
~rode --p-.L--n~.a Elec~rode
1
~
.....··
,______•
, ....
.,
::
v
v
2
(a) Forward biasing of a diode (b) Symbolic representation
(a) A p-o junction forms a semiconductor diode
p-side
n-slde
0
Anode
L.......r>t ...-J
......... ..
a
Ca;:ode
I
{b) Circuit symbol of a diode
(8-17) Fig.
1.1
Q. 2(a)Explaln the operation of a p-n junction diode In
the forward biased condition.
<B-18) Fig.
1.2
Operation of forward biased diode :
Due to the negative terminal of external source connected
to the n-region, free electrons from n-side are pushed towards the
p-side. Similarly the positive end of the supply will push holes
from p-side towards the n-side.
With increase in the external supply voltage V, more and
more number of holes (p-side) and electrons (n-side) st3!t
travelling towards the junction as shown in Fig. 1.3.
Ana. :
If tbe p-region (anode) is connected to the positive terminal
oC lbe external DC source and n-side (cathode) is connected to the
oegative terminal of the DC source then the biasing is said to be
"forward biasing". In other words the diode is then said to be
-- --- --
n
p
-Current
limiting
reeillanoe
Barrier potential decreases
due to reducUon of depletion
region wtdth
' - - - - - - - - - + -Width of depletion region decreases
due to the holes and electrons
1.. . -- -----•;llt----------'
approaching the junction
v
Fig. 1.3 : The etrect of increased forward bias on the depletion region and barrier potential
1be boJe1 wiU start cooverting the negative ions into
DeQtraJ IIOOU and the electrons will coovert the positive ions into
DeUtraJ ai.Oml. AJ a result of dUB, the wid~ of de~letio~ region
. . redtlce. Due 10 reduction in the depleuon reg1on w1dth, the
barrier poceacial will a!Jo reduce. Eventually at a ~articular value of
v the dep&etion region will collapie. There 1s absolutely no
oppoiitioo 10 the now of electrons and holes. Hence a large
ownber of eJectrooJ and holes (majority carriers) can cross the
juoaloc u.oder me influeace of ext.emally connected DC voltage..
The iar&e number of majority caniers crosrring the junction
c:oeliti~U~e& a currena caJJ.cd u the forward current. ·n~e current now
ibowo in fig. 1.3 is the electron current which is in the opposite
I ' ,I •. •
· II
I
II
II
II II ~.
direction to that of a conventional c11rrent. With increase in the
forward bias. the width of the depletion region decreases and so
does the barrier potential.
0.3
Explain the operation of a p-n Junction diode In
the reverse biased condition.
Ana. :
If the p-region of a diode is connected to the negative
tenninal of the external DC supply and n-region is connected to the
positive terminal of the DC supply as shown in Fig. l.4(a) then a
diode is snid to be ·•re\'erse biased". Fig. l.4(b} shows the reverse
E1ectronic Oevice8 & Circuita-l MU
bluina ecbematically. The reverse twTent is denoted bY. ls and it
Oows from tbe cathode to anode of the diode.
Thus rc\"Cf'Se CUJTetlt flows exactly in the opposite direc~o~
to lhit of tbe forward CUJTetlt. Resistance R is connected to limit
the reverse curreot.
"-2
. ( ot allowed to flow into the n-region)
held back on ~e P suit. ~ntains the thermal equilibrium.
·
arc
·at bafOer then maJ
'lbe potenb
_v+
------.1111-----
..........
........... ..... .................,
(.........
....··
....···· Is ··...
'··.... - !-'+_.)__
~
'------t
v
Ec
(b) SymboUc representation
Ev
Opel don of a revene blued diode :
Wben a diode is reverse biased, holes in the p-region are
aaractcd towards the negative terminal of the supply and electrons
011 die n-side are aaracted towards the positive terminal of the·
i'"-rfv!H
EFp -------~-------+-------- EFn
(B-12) Fig. 1.4
~Y
r
1""-..._!
._:
;
-
(b)
(a)
as sbown in Fig. 1.5.
0 Holes
• l3eclron8
6
PoeiUw Immobile ion
8
NegaUv!l Immobile ion
~
EleQt%! q(Vbl
(B-23) Fig. 1.5 :
Operation ora reverse biased diode
EFp ----------1 .
Iacreue in barrier potential : Due to more number of
iom present on opposite sides of the junction, the barrl.er.potential
or juoctioo potential will increase. The process of widening of
deplcQoo regioo does not continue for a long time, because the~ is
no steady flow of holes from right to left i.~~ from the n-side to pside.
Judfy that the apace charge width increase with
,..,.... blued voltage In a p-n juncUon diode.
Q. 4
l•l§MICI
Ane.:
f
Due to tbe movement of electrons and holes away from the
happens due
junction, width of tbe depletion region-increases
to tbe creation of more number of posi~ve and negative immobile
i.ooa.
.nus
Q. 5
Dr8W energy band diagram of PN juncUon for
reveree bias clearly showing
junction diagram, depletion width, Fermi energy
lewl end berr1er potential.
Z«<, forward,
'*hfl101
. Ane.!
The mecbaniJm of current flow in a pn junction with the
:
~ of tbe eoetgy bend diBgrami is as follows
1.
Thet'm8l equJJJbrtum :
The energy bend d!Jtgram of a. pn junction in thermal
eQuilibrium i1 lbown in Fig. 1.6(a). Here the electrons see a large
poteoti.aJ bl.triet bccauJe ot which a large number of electrons are
hekl beck in tbe o-regioo. (they can not flow into the p-region).
Similarly boles .00 see this potential barrier from the p side and
+:
r__f__ ____ EFn
~
Hole flow
(c)
(F-3674) ~-
2.
1.6 : Energy band diagrams of a PN junction
Reverse bias :
~ e~ergy band diagram of a reverse ·biasC!d PN junction is
as shown m Ftg. 1.6~). It shows that potential ofn-region is higher
than that of the p-stde. ~nee the Fermi energy on the n-side is
lower than that m th: p-stde. The total potential hamer is higher
tJtan. that for the no btas condition. Due to this increased potential
b~er the electrons and holes will be held back 'n the n and p
~gto~s respectively and there will be no flow of charges across the
JllnCtion.
Hence
current flowing through the Junction
·
· would be
zero.
.
Forward bias :
.
. ·
The energy band diagram · f. ·
in Fig 1 6(c) It sh
m orward btased state ts shown
lower iev~l ~ th ~~sththat the. Fermi level in the p-region is at
10
is reduced So 1 a
e n-regiOo. The total potential barrier alsO
regions re~pec:v:trons and holes are not held baclc in the n and P
to the process of di~J?e holes and electrons cross the junction due
ston and current starts fl .
The holes · ·
.
owmg.
.
carriers there. Simi;~~ted mto the n~region become min~ty
become minority earn~ the el~tro~s mjected into the P:re~on
of excess carriers will tak · ~ ~ffus10n as well as recombmatton
e P ace m these regions.
Q, 8 01raw and explain V-1 characterlattca of
unctton diOde.
3.
PN
..
4-.3
Me.:
The V-1 characleristi¢S
can be Ul
A:v·dcd.
.
•
·
mto· two pnrts :
~-~. ofp-n junction DIOde •
.LIX: IYIWanf C'bvacteri ti
•
'
c:alfiOde furwanl \!01~ v . ver:u~ ~ the graph of the anode to
diode Ott). The furwant cb~teri . . . fo':"~ c~nt through the
l.
f---VA--ol
+
=~
AB and BC as shown i .,.
sbownin Fig. l.7(b).
1 stic IS ,diVIded mto two portions,
· n r:tg. .7(a) and the
di
correspon ng circuit is
A (_.. ...-·j~·~·i;;·····:·)
-
+
v
AeQ1on A to B :
ln cbe region A to B of the ti
Fig. l.7{a). the forward voltag . orward characteristics shown in
YOJuge. Tbel:eforc lhe forw
e ts small and less than the cut in
small. With fiutbel' increase~
flowing through the diode is
leYel oflhe cut in roltage and th .~ard voltage, it reaches the
(a) Arrangement to reverse bias a diode
c;:eot
~-
e
VR ln. volts
Reverse/;,:,.------...J. · ··10 {Aeverae satura11on
of depletion region goes on
WI
0
breakdown
vollzlge
Bmakdown
current)
~lnmA
Reverae a.rrent
fsin,.A
· (b) Reverse characteristics of a diode
(B-Z7) Fig.
:{,.··
;;ot"-~Cut~-ln-'-v-ol-:-ta-g-e- - - - VF volts
(Knee voltage)
(a) Forward characteristics of a diode
. ;.---V F ----.;
_ _.....
l--1
l
1.8
Current flowing through a diode in .the reverse biased state
is the reverSe saturation current which .f lows due to the minority
ccuriers. Therefore it is treated..as a negative current Hence the
reverse characteristic appears in the third quadrant as shown in Fig.
· l.8(b). As the reverse voltage is increased, the reverse saturation
current remains constant equal to 10 if the temperature is constant
This is because, · reverSe saturation current does not depend on
rev~rse voltage but it depends only on temperature. Bat as the
reverse voltage reaches the breakdown voltage value, large current
flows through the diode. .
·
a. 7
Draw Complete V-1 Characteristiqs of Silicon and
Germanium Diodes :
Ans.:.
Forward """""' (rnA)
(b) Set up to draw the forward characteristics
.(B-26) Fig.
1.7
Region B to C :
As soon as the forward voltage equals the cut in voltage,
aureat through the diode increases suddenly. The nature of this
aureot is ·exponentiaL The large forward current in the region B-C ·
~ tbe forward cb.ataeteristics is limited by connecting a resistor
"R" in series with the diode. Forward current is of the order of a
(ew mA. 1he forward current is a conventional current that flows .
from anode to cathode. Therefore it is considered to be a positive
c:um:ot, and tbe forward cbatacteristic appears in the first quadrant
as libown in Fig. 1.7(a).
Si
Reve""' w1tage (volts) '
.
Reverse ~.6f.ics is ~ gr.q>b
of reverse voltage (Va>
•erau. lhe reverse cwrent ({8 ) as shown in 'Pig. l .8(b).
. · laallliiMmlliiUiiiiil
In 11A
)
r~:~Ge--~,...,....- IIA
..,.---1
Si
0.2
0.6
L-,-t
cut In vohoQes
R<!ve'*' charact.utotlca
(B-Z9)
Fig. 1.9 : V-I characteristics of Silicon and
CuWn voltage (Knee voltage) :
The voltage at which the forward diode curre~t starts
~B r.tpidly is known as the "cut-!n" voltage of a dtode. ~s
lbown in Fig. 1.7{a), the cut-in voltage ts very close to the ?arner
JIOttetial. Qu--in v.oltage is denoted by Vr' C ut in vol~ge ts also
called as kaee yoltage. Geoe.rally a diode is forward .b•ast:d above
lhe cut in volta8e. 1be cutrin voltage for a. silicon dtode ts 0.6 V
IOd that fot a gcrman.ium di.ode is 0.2 V.
1.
ltneniie ~of a Diode :
l1,
Germanium diodes
Q, t
Derive expression for the Diode Current •
Ans.:
The diode current 10 has an exponential shape. It is
mathematically expressed as :
V/1\V
Io
Where , 10
10
]
=1 e T- 1
= Reverse saturation current
0
::;
[
Diode current (forward or reverse)
...(1)
·
4-4
:::::00.
Electronic Devlcee & Clrcuits·l (MU)
=
V't
Ana.:
1x> and it is called as volt equivalent
11
=
of temperature
=
l fur Gennanium ='2 for Silicon.
Temperature in °K
and
Voltage across diode (forward or
reverse)
The constant ll in Equation (1) is called as the emission
coeft'ldeDt or kled~ factor. Its value is 1 for Gertnanium and 2
for Silicoo.
·
1.
Voltage equivalent ot temperature (VT) :
1be voltage equivalent VT at a given temperature ofT °K is
ll
T
V
Two diodes are in paralie1·
- 12
. neverse saturation current, Iot 1 x 10 Amp.
D 1 . .1"
1 10-10
_;....ration current, Io2 = X
Amp.
o2 : Reverse ,...._
...
Total current I =2 mA. ll 1.
:. VT =26mV.
Assuming ' T 300oK
Step 1 :
c~ent throUgh Dt :
Current through Dt is given by,
.I
1
lz
.. :(2)
VT = kTvolts
Where k = Boltzmann's constant
= 8.62 x 10-5 eV 1 °K
T = Temperature in °K
The value of VT at T = 300 °K is equal to 26 mV. The
T
.
:.
.
Iol [
I
.
Vp/TJ VT
2xl0-3
4- "'
-v.,,
But e
=
12
-~;·····T
v
o,
02 .
~~.... . .1
<F-181J) Fig. 1.10
1;
v
a '• V •, II I II I IIIII S
...(2)
V/ttVT
-1
]
V/TJVT
+ I02 e
V/ttVT
...(4)
(1xlO-t2eV/26mV)
e
V/26mV
e
[1
V/26mV)
X
10- 12 + 1 X 10-IO ]
3
=
v
w-3 . =
2x 10l.Ol X 10- 16
6
= 19.8 X 10
16.8
.:- V = 0.4368 Volts.
. ••.Ans.
As both the diodes are connected in pandlel with each
other, the voltage "V" across them will be the
same.
Explain effect of · temperature on
characteristics of PN junction diode: -
the
V-1
Ans.:
· Tbe expression for diode current is
t]
Io
=
Io [e V/'1 VT-
Where , I0
=
Reverse saturation current.
T
VT
=
r,
=
26 x
Q. 9
A diode with a reve..-. saturation current of 10-10 Amp and another with 10
Am~. are connected
In parallel. If the total current of the circuit Is
2 mA, calculate the voltage across the diodes.
Auume 11 1. Refer Rg. 1.1 0.
...(1)
Taking log of both the sides we get,
VT
<<1
-10
...(6)
This expression shows that the reverse current Is of a diode
is negative and constant, equal to 10 (reverse saturation current).
0. 8
e
Vp/11 VT
:. Is ,.,
3
. 2 X 10V/26mV
··
= Ia[e-VR/TJVT_l]
e
_ 10
.
...(5)
This expression shows that the forward current is of _
exponential nature.
3.
Expression for the reverse current (IS) :
Substituting ID =Is and V =- VR in Equation (1) to get,
JS
10 e
]
V/ttVT_t]
+ ( 1x10
...(4)
>> 1 then
.
= 101 e
Substituting ID =IF and V = Vp in Equation (1) to get the
expression for forward diode current as·:
Ife
. -1
SubstituQI1g the values to get,
Expression for the forward current (IF) :
V,ltt VT
]
fr-=10 [ e
-1 -
V/ttVT
V/tt VT . ]
+ I02 [ e
- 1
...(3)
neglecting the - 1 term in both the terms in Equation (3).
temperature
.
[ e
= Ioz [ e
I ;;;
Thus voltage equivalent of temperature is dependent on
temperature.
ol
The total current I :
. I . = II+ lz
Substituting Equations (1) and (2) to get.
T
T
·
(1/8.62 X 10 3) = 11600 ...(3)
and its presence in the equation of diode
- cum:nt indicates that the diode current is dependent on·
I
Step 3 :
vT can be expressed as,
VT = (1/ k)
-
-
Step 2 :
Current through Dz :
Current through D2 is given by,
gi~by,
value of
=
=
=
=
ll
= TI600
=
=
1 forGe diode
=2 for Si diode
V
Diode voltage.
The diode characteristi ·
equation of I . Two
c IS mathematically expressed by the
di~e eucre to
parameters lo and VT in the expression for
is depende:t ~n te::erature dependent. Hence the characteristic
temperature on the V-I :mpera_~e. The effect of change in
c aractenstics are as shown in Fig. 1.l L
i
I
I
\
t
'
,,\
~ Owicel & Circuita-l (MU)
4--5
VT
T
II ,600
=
283
o
= li,600 =24.4 mV at T =283
K
...(1)
The reverse saturation current is given by,
.
I0
= K T" e-voo'"vT
Substituting m "" 1.5, fl
=
=
=2 and V00 :o:: -
1.2 t for a silicoo.
lt is given thatl0 2 nA at T 283° K
3
. . 2xHr9 = Kx(283)'.5xe - J.2112xZ4.4 x tc1"
:. K
Diode current
at
ofaSiBcondiode
~the fig. 1.11. cbe effects of temperature are :
I.
llempeOblre. Therefore at the same forward voltage V Fl a
~ current ~ flows through the diode at increased
~
The tnakdown voltage increases with increase in
lliempenblre.
Reverse satnratioo current increases with increase in
temperature. Io fact it doubles its value for every 10° C rise
in tbe tempcntu.re.
..
Step 4 :
.......aon current?
=283° K :
283° K
2 X 10-9 (e0..4/2 xZ4..4x I0- 3 _
11
7.256 x .to- 6 or 7.256 JLA
...(3)
=70°C i.e. 343° K :
..•(4)
= KT"'re-voo'"vTJ
= 0.02473 (343)1.S [ e -1.2l/2x29.56 x lc1"3)
10 ·~ 0.2042 x 10- 6 A or 0.2042 J.1. A
0. 10 Why doM Ge diode produce higher reverse
To atkulate diode current at T
i.e.343° K:
lz = Jo( eV/TJVT -1)
...(5)
=70°C
Substituting I0 from Equation (5) and v; from Equatioo {4)
Ana.:
to get,
Tbe four valence eleclrons of Ge are in the fourth shell
wbcreu those of a Si atom are in the third shell. Hence the force of
tttractiou berwoeo the nucleus and valence eleclrons is weak in the
IJ'UN"ium atoms as compared to that in the silicon atoms. The
fi:JrtJiddeG energy gap is smaller in Ge than Si atoms. Therefore, at
the same lmlpC:OIDll'e, more valence eleclrons will jump to the
meductioo band to produce higher reverse saturation current
StepS:
Q. 11 Why Sl diode Ia more popular than the Ge diode ?
lz =
0.2042 X 10-6 [e0.-4/2x29.56 x la-3- 1]
1z
1.7698 x
=
=
1be ~everse saturarioo current for a Silicon diode is much
lower lhan tbaf. of a Ge diode. Tberefore even with the two fold
iaaate io 10 aftet every IO"C rise in temperature, the reverse
~ CW'1'eQt through Silicoo diodes will still remain very low.
S. It iacleued ternpeealUI'C5. tbe reverse saturation current
dlroup a Ge diode is very high. of the order of
100 ~ oc so. 1bis level of reverse saturation current is
~ ill JOC(ice. Tberefore the Si diodes are more popular
--Ge~.
ldea!Jy dJe ctiode
cbaraCltristics should not change with
cb1qe io ~and practicaJJy the change in.characteristics
~ be plinimom 'fbe ~cs of Ge dtode are '!lore
. .
.
'licoo diode
,,,._OU~ ·dlanchalofaiJ
·
0 . 12 Fot a •~ diode, the r-.veree saturation current
• 10• c a. ~ .. 2
when the v.o ltage
acrON dloOJ ._ O.A v. wtwt wtJ1 be the% change
In t1llMd to 70° c ?
n.,
CIIMftllll.,..,..,.,...,. ..
w-' Amp.= 176.98 !lA
...(6)
To calculate the % change in diode CWTeDt :
( I2 - I 1)
%change =
X 100
II
176.98 - 7.256
=
7.256
X lOO
Ana.:
An.. ;
=
=
=
To cakul.ate VT and I. at T
343
VT = ll,600 =29.56 mV
ttJmpeodUre.
3.
T
Step 3 :
,_
2.
...(2)
I = 10 [e v ' " vT .:_ I)
.. I 1
Redll<::tioa in tbe cut-in voltage takes place with increase in
0.02473
To calculate the diode current at T
Step 2 :
~ flc. 1.11 : EfPeds ot taapen..re 00 v _
1 cbancteristks
=
2339.2%
0. 13 What Is transition capacitance ? Gl:ve Ita physical
significance. ·
Ana.:
.
In Fig. 1.12, a p-n junction diode is being reverse biased.
W1th rev~rse .voltage applied, the majority earners ~ve away
from the junction. Thus as shown in Fig. 1.12, the boles in the pside and electrons in the n-side move away from the junction.
J
-o:
-o:
-o:
-ot
n-elda
Electronic Devices & Clrcults·l (MU)
ar.ct of chalrge movement :
Due 10 the movement of majority carriers away from the
junction, lbe width of depletion region will increase with increase
in tbe reverse voltage.
Due 10 tbe movement of charge caniers there is a change in
charge (dQ) with change in voltage (dV). This increase in charge
caused by lbe change in.reverse voltage is defined as the transition
capacitance.
.
... c.-
~ I~
.~.(1)
Reverse
voltage (Volta)
- 20
- 15
-10
-5
0
The transition capacitance c; is also referred to as space
. (F-1025) Fig. 1.13.• Va rfation or Cr with reverse voltage
.
cblqe capacitance or barrier capacitance or depletion region
capacitance. .This capacitance is not constant but it depends on the .
. iOn capacitance ? 'Give Ita physical
Q. 14 What Is. dlffu s
magniiUde of reverse voltage.
· significance.
Slgnlftcance of C,. :
·
· 10rw
&
ard b' ..~...~
The basic eqUation relating the voltage o~ C, charge ~d ·Ans·. :
·unctiol1
diode 1s
1...,..... a
capacitance Cis given by,
~en ~e .p-n . J
er than t:he transition capacitance
capaci~ce w~ch lS m~sl~pacitance is called as diffusion
Q = CV
.. Q=CrV
come~
. mto ~xtstWhence.. forward voltage is applied, the barrier
Differentiating both the sides to get,
capacxtance '-1)·
en
·
th
'de
. .
. red d boles from p-side enter mto e n-s1 .
~
,.... dV
.
potential
Is
lowe
an
.
.
'de
1
·
·
...( 2)
dt = "'-T X dt
.
from n-s;de
Similarly eIectrons
~ enter mto
· p-st . t IS converuent
ban to
.
.
.
mental
capacitance
defined
as
the rate of c ge
~
mtroduce an mere
· ·
·tan r ·
But,
dt =
.of·injected charge With applied vol~e. 1bis capact ce '-1> ts
called as the diffusion or storage cavacttance.
dV
i = Crx(it
...(3)
..@_
~..(1)
:. Co = dV
This equation shows that the reverse current "i" through the
It can be proved that the diffusion capacitance is given by,
p-n junction c!iode is proportional to the transition capaci~ce
'tl
"C,-" and the rate of change of reve~ voltage "V". Hence if a
reverse voltage of high dv/dt appears across a diode (that means a
reverse voltage at high frequency) then a large current will flow
through. it, and its reverse blocking capacity will ·be lost. .Hence the
maximum .frequency of operation of a diode is dependent on the
value of<;.
Expression for Cr :
The mathematical expression·for transition capacitance <;
...(2)
Where, 1: = Mean lifetime for holes.
From the Equation (2) , the diffusion capacitance is
proportional to the current I. In the forward biased state the val~
of <:;0 ·is much larger than the ·transition capacitance· <;. For a
reverse bias, C0 must be ~eglected i1S compared to <;. In the
forward biased. condition, C0 appears to be in parallel with the
forward.resistance.
·
time
is given by,
EA
c; - w
...(4)
A - Area of the junction
W = Width of the depletion region
e = Dielectric constant
The value of (;. is inversely proportional to the width of
depletion region W. As W increases, the transition capacitance
decreases.
As this resistance is very small the
constant "rd C "
0
Co will be ineffective for the
normal signals, hence it can be ignored. But for the fast signals Co
becomes effective and hence should be conside~. The variation
in the diffusion capacitance with change in forward voltage is as
. shown in Fig.. l.l4.
.
.
·
will also be very small. Therefore
Diffusion c
capacitance 0
Width of depletion region :
The width of a reverse biased p-n junction is given by the
following expression,
w
Wbere ,
e
112
e (V1- V)J
2
- [ qNA
.
...(5)
E0
= Permittivity of the semiconductor.= e 0 E r
= 8.854 X 10- IZ F/m and
Er
::r
v1
;: Contact potential
16 for German.ium
=12 for siUcon
V = Externally applied reverse voltage.
•iiilmliiliiii
o--~~--~-----FoNmro
0.25 o.s
voltage
<F·lOU) Fig. 1•14: Variation in C
0
with forward voltage
~ the .forward biased state with increase in the current level
the diffusiOn .capacitance C0 becomes more predominant. But
for ~e reverse btased condition, C0 is negligible and c; will be
dommant as sho,wn in Fig. l.l5(a):
·
·
.
..1..
£ectronlc Devices & Cfrcuhs-1 (MU)
•
1be ran~~riti"" effects ,· e r
,
--.---·
,
.._...
• · '1' ....u
4-7
Co are represented by a
concentr.Uon NA of the acceptor atoms on the p
aide Ia much smaller than the concentration of
·
20 I
donor atoms 11'1 the n-materlal. NA 3 x 10 /m.
calculate the width of depletion region for an
applied reverse vOltage of 10 V. Also find the
apace charge capacitance H croas-.sectlonal area
2
of the diode Is 1 mm • Assume: e 0 8.854 pF/m
and Er 16.
cap~C•tor m perallel wtth an ideal diode as shown in Fig. l.lS(b).
=
•'
.~
=
=
'=:
-5
Ana.:
Given :VJ = 0.2 V,
A= 1 mm2,
Forwartl 0.5
0
.
voltage
'(a) Effect or forward and reverse bias voltage on the
1.
[2e
=
2.
•
X
16
112
5.48~m
Q •.17 Why is load line called as DC load line ?
Ans.:
. The word "DC"· represents that the operating conditions are
DC. No~ signal is present. .And it is called as load line because
the slope of this line . is equal to the reciprocal of the load
resistance R.
18 Define Q point.
Ana.:
Varactor is used as a·
/variable capacitance
L
_T he intersection · of diode characteristics and load line is
Q~point. It is possible to change the position of Q
point as per requirement. Load line can be viewed as a· set of ·
infii:rite number of Q points.
called as the
Q. 19 What are the factors affecting the load line and Q
L-~_.----~
point?
tankcirwtt
{h) How to use varactor diode in an LC tank circuit
Ans.:
<F-101.8) Fig. 1.16
The factors affecting the load line and Q point are as
Varac:tor diodes are also referred . to . ~ .varicaps ?r
YOltacaps. The use of a varactor in LC tuned crrcwt ~ ill~~tt;d m
Fig. 1.16(b). Tbe resonant frequency of the tuned crrcwt 1s gtven
follows,
3.
Temperature
by (without varac:tor),
4.
Device to device parameter variations.
~
1
= 2n~
...(1)
.
Wbeo the varactor is connected in parallel wtth LC
COIDpooeoU as shown in Fig. l.16(b}, the resonant frequency gets
moctified tot
,,
1
...(2)
f, = 2 n...ju.c + C,.)
.
~ C,. is tbe variable tranSition capacttance offered by
tbc Yaractor
o. 18 ~ zero votta.,.,.,.., height at an aThlloy
.,....
a. 02 V
8
germanium p-n Junction
·
·
I; ;1 : .
=1.416 X 10-
w=
c.
Q.
(a) Circuit symbol of a varactor diode
(1)
10
To lind the space charge capacitance (Cr ):
6
10
E A
1.416 X 10- X 1 X 1(1
6
=
5.48xlo= 25.8pF .
Based on the principle of voltage variable capacitance a ·
and it exhibits the property · of voltage vrujable . transition
capacitance more predominantly as compared to the conventiOnal
JHl juncti.oo diode. The circuit symbol of a varactor diode is as
sbown in Ftg. l.16(a).
..
~:V)J
10
Ans.:
' /
=
2 X 1.416 X 10- (0.2 + 10)]
W = [
1.6 X 10-19 X 3 X 101ll
1.15
special type of diode is manufac~. It is called as varactor diode
= 16.
112
Where • E :: E o E r =8.854 X l0Substituting values to get,·
Explain how the varicap can be used in an .Lc
resonant circuit-
~
V = - 10 Volts
E
12
(b) lndadiDg tbe effect or transition or dift'usion capacitance .
+Vee
=8.854 pF/m,
W
. 0.
----·--f~(
E0
•
Cr«Co
a. 15
=3 x 10'l!J/m3 ,
To calculate the width of depletion region : .
tnmsitioo and cWrosion capacitance
(F-1027) Fig.
NA
V '• II Ill I I
il II '•
l.
. DC supply voltage . 2. Load resistance R
Q. 20 E~plaln piecewise lln~r model and DC load line
of PN junction diode.
·
Ana.:
The concept of the load line and the piecewise linear model
can be combined together in diode circuit analysis. Considering the
piecewise equivalent circuit of Fig. 1.17(a) and assuming Vy =0.7
V and rp=O, v. =5V andR = lkn, .using the KVL,
V1 - Vy-IpR
0
...(1)
Rearranging the equation to get,
IR
-Vp+V1
=
=
Bectronic Devices & Clrcults-1 MU)
:. I.:
.
v.
1
....(2)
= - R"<Vr>+R
This is a straight line with a slope of - l/R. This is our load
line as shown in Fig. l.l7(b). The two extreme points A and B on
tbe load line are obtained as follows :
Point A : Substituting Vi 0 in Equation (1) to obtain
=
Point 8 :
line
intersects the
piecewise linear
The de • load haraCteristics at Q point as shown in
approximated diode c oding forward diode current is IF :::: 4 3
.
?(b) The correspo
v - 07V
·
Ptg. 1.1
·
fun tion of v and R (as r- . olts). The
mA and it is onl~ the ill ~eep chan~ng when we ch~nge the values
position ofload line w. p·
ll8(a) and (b) respectively.
of V• and R as shown tD tgs. .
point A. It has co-ordinates of (0, 4.3 mA).
This point is obtained by substituting lp = 0 in
Equation (l).lt has co-ordinates of
(5V,OmA).
.c
·:·~- ~~--· ~~~~-- - -~~·~·~.
l ""
.
·V8 =5V +
0.1V
·
·...........
·:
·
Ideal
diode
f
l
......:········'1
I····
r........
j
IF
....................·...........-
(a) Piecewise Unear
(b) DC load Une drawn on approximated circuit piecewise linear characteristics
. (F•31) Fig.
1.17
I (mA)
J.. . . L~.:~.... .... . ..!........: .........!.........~ .....Yf..c:fohs) !..?... .......J.. ... .~....:...l..... ~........! .... -~ . ..
........ J..........t... .....
(a) Effect of Vs on load Hoe
~: !:.......$.... '!.E ~'!olts)
.!......... .......
· (b) Effect of the values of R on the load tine
(F-32) Fig. 1.18
Q. 21 Give comparison of Ideal diode and real diode :
Ans. :
0.6 V for Si, 0.2 V forGe
diode
4.
.Re.verse saturation current
5.
Equivalent circuit in the forward biased state
Zero
D .. D
(F-42)
Few DA for Si diode
Few mA for Ge diode
~l~t-VWy-oK
·.
(F-43)
6,
Equivalent circuit in the reverse biased state
High resistance
~
(F-45)
1: a •, 11 · s ll I II I I II II S
-
4-9
EleCtronic DeviceS & Clrcults-1 (MU)
o. 22
calculate current "I" In the circuit of Fig. 1.19 If
both the dlodM are modeled by R1 • 10 Q and V
11 0•5 Vott. What de •ource ehould be placed 1~
eertea with 20 0 reeletor to Juet reduce I to zero ?
01
150
Co
(a) Complete equivalent circuit (b) Simpllfted equivalent circuit
3V
+
(F-40) Fig.
200
1.21 : Small signal equivalent circuit. of a forward
biased p~n jonction
2
,___ _ _ _ _.__ Loop
_:_:::__J
...i I
(F.St) Fig. 1.19
Ans. : ~ss~ng ~e voltage of the DC source ~quired to. be
~~ m ·~es WI~ 20 Q resistor is Vx. By replacing both the
~ With their _eqwvalent circuits, the equivalent circuit are
obtained as shown m Fig. 1.20.
150
100
o.sv
sv~
100
1711200
500
Loop 1
o.sv
. •
Loop 2
<F-52) Fig.
Vx
Fig. 1.21(a} . shows the complete equivalent circuit and
Fig. 1.2l(b) shows the approximated version of ,it Co is the
diffusion capacitance and CJ is the junction capacitance or
transition capacitance. As Co » C. when the diode is forward
biased, it has.been omitted from the ~pproximate equivalent circuit
of Fig. 1.2l(b). The resistance rd is the ac incremental resistance
and the series resistance r5 accounts for the resistances offered by
neutral n and p regions.
Small Signal Model·for Reverse Biased Diode =
The small signaJ equivalent circuit for a reverse biased
diode is as shown in Fig. 1.22.Resistance r,· is the incremental
resistance when the diode is reverse biased. C,. is the transition
capacitance, The transition capacitance has a significant value only
when the diode is reverse biased.
1.20
Apply KVL to loop 1 to write :
1. .
3
.. 2.5
=
=
(15 + 10 +50) I 1 - 50 I+ 0.5
75 II- 50 I
(F-41) Fig.
. ...(1)
. Applications of Small Signal Equivalent Circuit :·
l.
2.
Apply KVL to loop 2 to write :
0.5 + (10 + 20 +50) I- 50 I 1 =0
.. -50 II + 80 I = - 0.5
SoJyjng Equations (1) and (2) to get,
I = 24.73 mA
From .Fig. 1.20,
'3.
Apply KVL to loop 1 to write :
.;.(2)
1.22 : Small signal model for a reverse bblsed diode
2.
...(3)
t6e ac response of a diode circuit
which is subjected to an ac signal superimposed on the de
signal corresponding to the Q point .
For developing the small signal models of transistors,
which are useful in analysis and design of transistor
amplifiers. .
It is used for obtaining
Q. 24 Discuss
~tentlals.
75 II - 50 I = 2.5 .
But Vx is such that it will make I =0.
. :. 75 II = 2.5
:. 11
0.033 Amp
temperature
effect
on
breakdown.
I111W•U
Ana.=
Effect of Temperature on zener BreakdoWn :
The diode is heavily doped. So the width of depletion
...(4)
region is very small and the intensity of the electric field across it is
high. If the temperature is increased, then the valence electrons will
4.
Apply KVL to loop 2 :
acquire additional energy and it will be easier for the external field
-0.5- (10 + 20 +50) I+ 50 II - vX= 0
to pull such electrons by breaking the covalent bonds. Therefore a
Buti=0,:.-0.5-Vx.+5011 =0
smaller voltage is required for the breakdown to take place.
:. yx = 5011 -0.5 ={50 X 0.033)- 0.5 ·
Therefore the breakdown voltage decreases with the increase in
1.15 Volt
...Ans.
·
temperature.
The
zener
breakdown
is
said to have a negative temperature
Q. 23 Drew and explain small signal model of a forward
coefficient
as
V
DR decreases with increase in temperature. For a
and reverse biased p-n junction diode. What Is ·
zener breakdown, the ·breakdown voltage decreases with the
1 10
the main use of this model ?
increase in temperature.
Ana.:
2
Effect of Temperature on Avalanche
.
The $D1all signal equivalent circuit of a forward biased p-n
Breakdown:
JUnction is as shown in Fig. 1.21.
In the lightly doped diodes, the depletion region is wide and
· field intensity is low theref. . for such'diodes the breakdown takes
place due to the avalanche effect.
1.
=
=
*• 4
1':
a:. II
'• II 1111 IIIII S
1
4-1o
4co;
Electronic Devices & Circuits·! (MU)
With increase in temperature, the atoms start vlbra~ng .wi~
larger amplitudes. This will decrease the possibility of JOtnnSIC
electrons imparting sufficient energy to the vaJence electrons. S~ a
luger voltage is required for initialing .the process of p~er
multiplication. 'Iberefore the breakdown voltage increases Wtth
i~se in temperature. The avalanche breakdown is said to have a
positive temperature coefficient. For the avaJanche breakdown, the
breakdown voltage increases with increase in temperature.
Ana. :
· . ~- drop (VF) :
Forward vo·-.
1.
ode to cathode voltage measured across
.
It JS
T
~~
•od
-~
a
It is denoted by V p· YPJC Y the value Of
forward b~~sed di_ :·is between o.-7 V to 0.9 V whereas VP for the
Vp for a Silicon diod
from 0 3 to 0.4 Volts.
. diode r~ges
·
·
German•uro
f't-- VF 4
Q. 25 Dltrerentiate Silicon and Germanium diodes .
Ana. :
R
. _· t
.
1lo
·-''
Material used
Cut-in voltage
Silicon
0.6 V
3.
Reverse saturation
current
In nanoamp (less)
Maximum reverse peak voltage (VRRM) or PIV:
· tbemaxun·urn reverse peak voltage
It 1s
· that ycan be aPPlied
4.
Effectof
temperature
Less
Maximum reverse de voltage (VR) :
5.
Breakdown voltage
Higher .
6.
Applications
Rectifiers, clippers
clampers,
freewheeling
I.
2.
(F-37(i1)Fig•
1•23 .• Forward voltage drop
repeatedly across· It is same as Peak Inverse oltage (PlY).
This specification specifies . the· ~urn reverse de
.voltage that q_an be applied across the diode.
Lower
Low
. voltage
4:
VRSM:
temperature
applications
:Peak
It is ihe maximum·reverse
value of tbe nonrepetitive
voltage · that can be applied across · a diode without
damagmgit.
· .
Low
5.
Maximum forward current (lq) :
7·
Dynamic resistance :
Q. 26 Give applications of p-n junction diode :
It is defined as the maximum value of forward current that
Ans. : 1be applications of a p-n junction diode as follows :
. can be allowed to pass through a forward biased diode without
I.
Rectifier circuits
· 2. Clipping and clamping damaging it. This rating is also called as peak surge ~urrent rating
cjrcuits
and it is specified only for 1 cycle of input ·ac waveform. It is a
nonrepetitive current rating.
3. Voltage multipliers
4. A. M. detection
· 6.
Reverse saturation current ~
s. Feed9ack di.odes
6. Freewhee~g diodes
The reverse saturati~n current 10 is dependent only on the
7.
Log and antilog
8. Precision rectifiers using · ·temperature and independent of the applied voltage. 1 for the
0
amplifiers using OPOP-AMP.
Silicon diodes is lower than that for the ·G ermanium diodes. Hence
AMP.
they are preferred. 10 for Silicon diodes is few hundred
Q. ZT For the diodes, ·define forward voltage drop, nanoamperes, whereas that for the Germanium diodes is few tens
·
maximum forward current, dynamic resistance, . of microamperes.
are
rever.e saturation current and reverse breakdown
Dec.2014. Dec. 2016
voltage.
.. The_
resistance offered by a · diode to AC operating
con~tions ts known as the dynamic resistance or ac resistance of
the diode.
Chapter 2 : Clippers and Clampers
Q. 1
What Ia clipping circuit?
Ana.;
1be clipping circuits using di~s have_ the abi~ty t~ "clip"
off or remove a portion of the input s1gnal w1thout distorting the
remaioiQg part of the waveform. Clippers are also known as
limiting circuits.
Q. 2
What .,. the types of clipper circuits ?
The diode clipper circuits Cllll be of the following types.
Types of cUpping circuits :
1.
Series clippers •
In thi
·
.
·
· ··
.
. •
s configuration the diode IS
connected tn senes with the load.
2.
~~el clippers :
Q. 3
Write shon note on series negative clipper
. .
clrculta, working and waveforms.
In this configuration the diode appears
m a ranch parallel to the load.
May 06. Dec. 07
~6iai.~tikii~~i.~iibiiffi·om~ii•i••i••iii&~----------------------------~----------------------------------------
Electronic Devices & Clroults-1 (MU)
4-11
.....,
~0~~--~---,--~
(a) A series ntgatlve cllpper
(F-1152)
Fig. 2.3 : Wavefonns for the series positive cOpper with
non-sinusoidal Inputs
Output
voltage
Diode OFF
-10
o~~nu~~+-~~~~+-~
10 V~volts~
Diode
;
ON~
................. -10
(a) With an ideal diode
The basic
configuration of a series negative clipper is as
shown in Fig. 2.I(a). The diode used in this configuration· is
assumed to be an ideal o~e. This clipper is called as a "series
negative clipper'' because it. "clips off' the negative half cycle of
the applied voltage.
,
Diode OFF
Operation of the series negative clipper :
The series negative clipper shown in Fig. 2.1(a) is nOthing
but a simple half wave ·rectifier circuit The waveforms for the
same are· as shown in Fig. 2.I(b). In the positive half cycle of the
sinusoidal input, the diode is forward biased. Being an ideal diode,
it acts as a closed switch and connects the load directly across the
input
The load voltage is therefore equal to the input voltage in
· the positive half cycle. In the negative half cycle of the input, the
diOde is reverse biased and acts as an open circuited switch. The
load voltage is ·therefore zero during the entire negative half cycle.
The negative half cycle is thus "c)ipped off' or "shaved off' by the
series entire negative clipper.
a. 4
Write short note on series positive clipper
circuits, working and waveforms.
(b) With a non ideal Silicon diode
(F-1153) Fig. 2.4 : Transfer characteristics
The transfer characteristics of a series positive clipper with
ideal and non-ideal diodes are as shown in Figs. 2.4(a) and (b)
respectively.
5 Explain biased series negative clipper :
Ana.:
Q.
The addition of a DC supply in the series clipper is as
shown in Fig. 2.5. This will have an altogether different effect.on
the output voltage waveform of the clipper.
.
May 06. May 07. Dec. 07
Ana.:
The series positive clipper configuratio~ is s~~wn ~ Fig.
2.2. As shown in the waveforms of Fig. 2.3, the positive std~ of
each waveform has been clipped off, because now the diode
conducts only in the negative half cycles.
D
(F-1154)
Fig. 2.5 : Series cUpper with a DC supply
Operation:
The OP,eration of this circuit can be divided into three
intervals. The diode is assumed to be ideal.
Or-1151)
Fig. 2.2 : Series posidve cUpper
1.
Operadon when VIn is posidve but less than V :
In the positive half cycle of the input as long as VIn< V, the
diode does QOt get forward biased. Therefore from 0 to t 1 and then
from ~ to T/2 'in Fig. 2.5 the diode will remain in its OFF state and
the output voltage will be zero (Fig.2.6).
·
'
P.<t:>V·SIIIIII I IIIIS
4-12
Electronic Devices & Circuita-l MU
2.
Opention tor V"' poslth:e and greater than V :
At the instant "t.", the positive input voltuge is exactly
equal to "V' Volts and the voltugc across diode D is zero. After
that the diode is turned ON and remains ON until the positive input
voltage is higher than V i.e. up to instant"~", as shown in Fig. 2.6
and the load voltage is V0 =(V10 - V).
3.
Operation for V111 negative :
When VIn is negative, the diode is reverse biased and
therefore remains OFF. The load voltage is zero during the entire
negative half cycle as shown in Fig. 2.6.
v ....l....,
V the diode will be forward biased and the
For V1n < •
output voltage is given_t>Y·v + V
.
Vo In
•
•
ff d
V the diode will remam o an tbe output
When Vin >
voltage will be zero.
I ' Input ~tage !.. .; . ·I . [... 1. ...! ~
1
1.......... .... ..........! '
i
!V i
i
JT I
i !
:..... . -i· ..i .. +· :i" "j
.,..., ...; ......... I ,_,..,.,, ................
i '
Tf2
;t,
•
...
v.-~.-~ - i : ;~1 -~~H- H-=i:f=!--:1
:t: ~.~~.l 1~..t.~.!-.·:~.?.~-.+.:+::.~[J:.:J.:·.tj
...
0 '· ....
Complete negative haH cycle and a part of positive haH oycle.ls clipped off
(F-1151)
.. 'JJ. ._
Fig. 2.6 : Waveforms ofbiasectseries negative clipper
Trausfer characteristic :
TIM: transfer characteristic of tbe biased series negative
(a) waveforms and equivalent circuits Tor a biased series
positive clipper
clipper is as shown in Fig. 2.7. The output voltage is given by,
V0
and
V0
=
=
0
...For(Vin~V)
V in- V
...Fot V;n > V
V0 (volts)
Diode ON
DIOde
OFF
(F-1159)
(b) Transfer characteristics
(F·3569)
Fig. 2.7 : Transfer characteristics
Q. 6
Explain biased series positive clipper.
Ana. : The biased series positive·clipper circuit is as shown in
Fig. 2.8.
Q. 7
Fig. 2.9
For the clipper circuit shown in Fig. 2.10 sketch
the input and output waveform. Write
for V0 •
D
T~l----+---0+
vii
lo--_
_._.~
<F-3568) Flg. 2.8: Biased series positive cOpper
The diode will be off and hence equivalent to an open
circuited switch in the whole positive half cycl~ of _the input and
for a part of negative cycle of the input as shown m F•g: 2.9(a).
tis IIM'M111" 1111111
(C-4823) Fig. 2.10
inFiP
•
•
-
4-13
EJecttoniC Devlcea & Circuita-l (MU)
A na.:
3V
V0 a V1+ 1.6V
...when 0 II ON
V0 a OV
...when D Ia OFF
-Diode ON
0~--~---------~--~~~~~
Diode OFF
1----DiodeON
•14
DiodeOFF-j
(C-4815) Fig.
2.11 : Input output waveforms
Draw output waveform for circuits shown In
Q. 8
. . . .p
Fig. 2.12.
~u·
. 1v
T
,,..
v
Write short note .on parallel poaltlve clipper,
working and appilcatlons rvla 06. Dec 07
An~.:
In the parallel clipper circuits, the clipping diode ~
connected in a branch which is parallel to the load as shown m
Fig. 2.14. ·The d,iode is assumed to be an ideal _one. Resistor R
controls the current flowing through diode D. Thus it is connected
as a currept limiting resistance.
...s-6ftf2.
i
. nttzllne+
o: 9
A
(F-4687) Fig. 2.U
AnL:
Output wavefonn for circuit
1.
Output waveform for circuit
(F-1168)
Fig. 2.14 :Parallel positive clipper
O~ratlon with a slnusoldallnput voltage :
1.
Operation in the positive .half cycle:
In the positive half cycle of the input voltage. diode D is
forward biased and therefore conducts from rot 0 to n. Becau~
the output voltage is equal. to the voltage across the diode the
output voltage will therefore be zero in tbe positive half cycle of ·
the input voltage as shown in Fig. 2.15. the positive half cycle is
thus "c.lipped off'. ·
=
2.
Output
voltage
0~~~~~~~~~~
·rs ID +
A
-
(l-i69l)(b)
(F..-J) (a)
Fig. 2.13
I. 'I'.
V '
II
1111
I II II '•
............-
·A
-1~.
-v,
l. !+
+-
(F-11") Fig. 2.15: Waveforms and equivalent drcults
4-14
Electronic Devices & Circuits-! (MU)
2.
Operation in the negative half cycle :
Io the negative half c9cle, the diode does not conduct and
· therefore. acts as an open switch. The load voltage is equal to the
instantaneous input voltage as shown in Fig. 2.15. Thus_ ~e
negative half cycle a~ars as it is across the load. As the pos~~ve
half cycle is "clip~ off' this circuit is called as parallel pos1ttve
clipper. The operation is mathematically expressed as follows :
V0 = 0
· ..... V1 ~0
V0 -= V1
..... V1 <0.
Write a short note.
Q.12
on ·. Biased negative clipper :
.
Ans. :
.
ws the circuit diagram of a. biased negative
·
Fig. 2.18(a) sho . alled as the external btas. The diode is
.
1be de source V JS c
~~&
.
o be an ideal one.
ed
assum t
. A
Q. 10 A pOsitive shunt clipper circuit having a ±12 V
square· wave input. Sketch the output waveform
for the circuit. ·
·
l•l§Wtj
Ans. : The required waveform is as shown in Fig. 2:16.
(F-1173)
.lS(a) : Biased negative clipper
Fig. 2•
Operation:
:
Mode· 1 .• For V1 positive
•
·u· e diode D is reverse biased and acts as
Wben v . 1s pos1 v ,
vo
I
•
an open switch .
.
lta
The output vqltag~ is equal to the mput vo ge.
.
. v. o = v.
..
I
Mode 11 : v. negativ~ but higher than V :.
.
'd · a portion of the negauve
. half cycle. of V1, m ·
CODSI enng
which V; is higher than V. So the diode remams reverse bJased.
(F-47Si) Fig. 2.16
Q. 11 Explain parallel negative clipper .
:. V 0
Ans.:
The parallel negative clipper is shown io Fig. 2.17(a).
The diod~ will ~ooduct only in the negative half cycle of
the input to clip it off. The positive half cycle will appear as it is
across the load. With an ideal diode, the output voltage is
mathematically iiven by,
• ..... forV1 ~0.
Yo = V1
and V0 =· 0
..... forV1 < 0.
Fig. 2.17(b) shows the input and output waveforms with
ideal and non ideal·diodes.
=
V1
Mode 111: V1 negative and less than V:
As v. becomes less than V in the negative half cycle, the
diode turns ~n. It acts as a closed switch This will connect the de
source across the output terminals.
The output voltage is equal to ~ V
:. vo
= - v
Waveforms : Fig. 2.18(b) shows the waveforms of a biased
negative clipper with an ideal diode.
R
~-··
Input
vottage
t
:
i
~'-'-------~-+-'~----+---..i-T-:.._...,o!. t :
.
l. l
V;
(F-1171) Fig. 2.17(~)
••
••y••
:Parallel negative clipper
.,.•• •• •• ••.••• , ....................... ..
...... . ...... " .... . . :.....
l
·tj J.::
'
.. ~ . . . , .
Output
i
.
;
...
W-ll77) Fig. 2.18(b).: Wavefo~ of·biased ~tive·cupper _
Q.
13
Explain biased positive clipper with ideal diode:
Ans.:
The circuit di:urrun 0. f
.
..
.
.
Fig. 2.19(a). Th~ di~
.......i a btased posttive clipper ts shown JD
wavefoims for the .
. s ~sumed to be an ideal one. The
along with the
smu~l(lal mput are as shown in Fig. 2J9(b)
corresponding equivalent circUits.
(F-1172)
FJg. 2.17(b): Waveforms or negative clipper
~6is~5~mmi-itii•i"i~i·~•imJii•m•·i•·miai~------------------------------~------------------------------------------
Electronic Devices & Circuits-1 (MU)
4-15
·rFl.
A
(F-1180)
-
I
J
Fig. 2.19(a) : Biased positive parallel clipper
Fig.·2.20
Q. 14 EXplain
with neat
following circuit :
waveforms,
I
(F-1306) Fig. 2.21
(F~1181) Fig. 2.19(b) :Input, outp~t wavefonm aiid equivalent
circuits for a biased positive parallel clipper
The diode will conduct only from t = t1 to t = tz, when
V1 ;;::; V. When the diode is conducting the output yoltage is equal
to V. For Vi < V, the:: diode is reverse biased and turned off. So V0
=Vi as shown in Fig. 2.19(b).
Transfer cbar8c~tic :
The circuit diagram of a two way biased parallel clipper is
as shown in Fig. 2.21. It is going .to clip both th~ half cycles .of
input due to the presence of diodes D 1 and D 2 ~ the ~te
directions. Both these diodes are assumed to be tdeal diodes .
Fig. 2.21 shows Two way biased parallel clipper
1.
Operation in the positive half cycle : '
In the positive half cycle, as long as vi < v I• diode Dl wiD
be reverse biased whereas D 2 is reverse biased during the entire
The transfer characteristic is shown in Fig. 2.19(c).
<F-1182) Fig. 2.19(c) :
Ans.:
~~er characteristics of a biased
positive paraUel cUpper
. Biased positive clipper with non. Ideal diodes :
.
.
.
H the diode is assumed to be a non 1'deal silicon diode then
. .
1 ·bile conducting. So the output
voltage drop across lt IS 0.7 Vo ts W
• tead of V volts as
voltage will get clipped at (V + 0 ·7>Volts ms
shown in Fig. 2.20.
e asv
S OIIIIIOII S
(F-1188)
Fig. 2.22 : Input and output voltages for a two way
{W'8llel clipper
1
Electronic Devices & Clrcults-1 (MU)
KCL at node Vt:
It+~
=
=
~
V 1 -V2
9.4-Vt +Y,
6
:. 2000 + 50 50
-3
x 1<J 4 v, + o.o88
:. 4.58 X 10 - 4· 88
.
..
<F-llU) Fig. 2.23 : Transfer characteristics for the two way
=0.166 v,- 0.166 v
2
0.16; vl- 0.166 v2= 0.09258
...(1)
KCL at node Vz:
parallel clipper
2.
Operation in the negative half cy'cle :
Diode D 1 will remain OFF throughout the negative half
cycle. However D2 will be turiled ON when Vi ~ V2·• As long as D2
is. conducting the output voltage is ~qual to - V2 as shown in
. F~g. 2.22. And wben·D 1 and D2 !>9th are OFF, the output voltage is
equal. to input voltage and it is negative. The input and output
voltage wavefonns are as shown in.Fig. 2.22.
Transfer characteristics :
.
.
.O
0.166V1 -
4
. 166
y -0.02 V - 0.012 =5 X 10- Vz +2.5 X 10- 3
2
Q . 15 The cut-In voltage for each diode is 0.6 V.
...(2)
.. 0.166 Vt.- 0.1865-Vz= 2.5 X 10-3
Step 3 : Calculation of V 1 and V 2 :
Solving Equations (1) and (2) to get,
v
4.394 V and V 1
2
It is tbe graph of input voltage pl~tted on the x-axis and
output voltage plotted on the y-axis _as shown in Fig. 2.23.
- 2
=
=4.92~ V
Both the diodes D 2 and D 3 will -be off. So· current through
them will be zero._
Detennlne V1 and V2 and ·each diode current If R1
= 2 leO, R2 = 6 ~· R3 = 2 kQ.
itl§i•fi
IDI =
=
9.4-V1
2050
9.4-4.922 -2184 mA
2050 . - ·
.
Q. 16 State applications
o,f clippers •
.
·Ans: : The applications of clippers ~ • _
I.
2.
+5V
3.
<F·l289) Fig. 2..24
Ana.:
S1ep 1-:
Mark vario-Ds branch currents :
.
4.
·~-
. It is used in Waye shaping circuits and function generators.
To clipp off (remove). a part of input waveform without
distorting the remaining waveform.
As a diode clamp to protect sensitive electronic circuits.
This cin;uit is a combination of positive · and negative
parallel clippers.
As a combinational clipper;
Q'. ~7 What
are clampei'S?
Ans.:
. ·
The "dampers" are used to clamp the input
~ignal t~ a
~erent de_ level.· ~ other words, clamper adds a de voltage to -the
stgnal_ applie~ at tts. input. A clamping circuit is made from a
" +5V
Step2:
1F·U90) Fig. 2.24(a)
A,Pplying KCL at nodes V1 and V2 :
. II
Assuming.
1:
=
'"
=
~
=
13
=
I,
=
Rl'l
=
10-V1 -0.6
9.4- V 1
RI+RFI
2ill+RFI'
0 - V2 -0.6
RPl
4.4
R Pl '·
v,-v2
60
'
·v2 +5 _ V2 +5
~
a ~; V - S ll Ill I I f) II S
_
- 2 k.Q
RPl = Rr·'3
Typea of.clampers :
are
Clampers
of ~0 types :
1.
Positive clamper
2.
Negative damper·
Q.18 Draw and e~plaln poSitive clamper circuit
RF3
5- v, -0.6
capacttor, resistor,
Tbel
. .diode and . sometimes an additi'onal dc surce
o.
· c amper CHcwts are u~ to "clamp" the input signal to a
different dhac level. The ac input signal can be sinusoidal or it can
take any- s pe.
=50 .Q
Ans. :·
Ma 08. Ma
11 . Ma
13. Dec. 14
Fig. 2.25 shows the · . .
The clamping network wi~lfCUtt diagram _of a positive damper.
namely a capacitor a diod
alwa~s conSist of three elements
'
e. and a resistor.
Assumptions :
·
Before analyzing the 1
· . .. .
following assumptions are
d c amper cucu1t of Fig. 2.25.
rna e,
1.
The input is a perfect
waveform
sine
..
.4-17
EJectrOnlc Devices & Circuits-! (MU)
:z.
The values of R and C are chosen such that the time
constant 't == RC is large enough.
The diode is an ideal one.
The RC time constant is much longer as compared to one
cycle period T of the input.
3.
4.
Ana.:
·A negative damper will add a negative de level_to ~e in~ut
signal. Fig. 2.28(a) shows a simple neg~ve damper ~cwt whtc~
adds a negative level to the AC input R 1s the load reststance.
c
RC>lOOT
0
~I
1
1)1
'~•t
••
(F-3579)
Operation :
(F-1200) Fig. 2.25: A positive damper
Operation:
In the first negative half.cycle after turning on the circUit.
tbe diode acts as a closed switch and charges the capacitor to peak
input voltage V m • In all the subseq~ent positive and negative half
cycles, due to large RC time constant. the capacitor does not lose
much cbarge. So Vc almost remains constant. The diode is reverse
biased in both half cycles, therefore it reuiains off.
The expression for V 0 is,
v0 =vi + v m
-c.
Fig. 2.28(a) : A clamper ·c ircuit
(F-l20l(a)) .
Positive DC shift.
·
.
In the first positive half cycle the capacitor will charge
through the forward biased diode to peak vol!_age V m.• The
charging 'takes place very quickly as the diOde resis~ce ~s
negligibly small. Once the capacitor charges to "Vm", the diode tS
reverse biased and stops conducting. The diode is reverse biased.
So remains off.
The expressio~ for output voltage is given by,
Vo== Vi- Vm
.
"-r'
"---+ Negative DC shift
(F-U04(a))
This shows that the negative damper adds a negative DC
shift. Fig. 2.28(b) shows the waveforms for a n~gative damper.
' ""'('"'''": ···
. .J
This shows that the damper adds a positive DC shift. The
input output waveforms for a positive damper are shown in
F.g. 2.26.
!
... ·t ........~. ."'";....
c:IJ~r ·· :
II
•
..i.......(
(F-1205)
-......
Fig; 2.28(b): Input output voltage waveforms fQr a
negative damper '
... ... ·······:·····..(.......•.;
--~-- ..;, ,
:___,.:____ ;.._.....:.....;,......
<F·Uoz) Fig. 2.26: 'Input output waveforms of a positive
clamper
0.19 A positive voltage clamping circuit ~ave a± 12 V
square wave input Sketch the output waveforms
l•l§Mij
for the circuit
Fig. 2.27 shows the required waveform.
Q. 20 Draw and explain negative clamper circuit..
. ~...~
1:
a :. 'J
·
' • II 1111 I II II ~
Dec.02. Dec. 04
Ans. :
The applications of dampers are as 'follows:
2.
In the voltage multipliers, which produce ouqiut voltages
equal to. multiples of input voltage without using a
transformer.
In order to provide de shift to the input waveform.
a. 22
Sketch the output waveform for Fig. 2.29.1111MII
1.
...:b___,
-15Vru ~
(F...f15Z)Fig. 2.27
·
Q. 21 State appUcations of Clampers.
lti§Miel
(F·26Sl)
Fig. 2.29
4-18
Electronic Devices & Circuits-! (MU)
. Pi
Ans.:
The capacitor will be charged to - 13 Volts with the
polarities as shown in Fig. 2.30
35. In the positive half cycle V0
clamper as shown m Jg. 2·
and V =5V.
"' Assuming an ideal diode.
=
=
Vo
..
12
=12 v
Vm+Vc
5 + Vc
.. Vc = 12-5=7V
ButVc = Vm +V
(F-2653)
.. Ym+V = 7V
. V = 7 _ vm =7 - 5 =2Volts.
••
Fig. 2.30
H~nce the output voltage is given by
V0 = V1 +13V
Hence the output waveform is shifted by 13 V on the
positive side as shown in Fig. 231 .
Vc=Vm+V
-... + .
R·
v.
2Volts
(D-1581) Fig. 2.35. :
Proposed circuit
In the negative half cycle,
=
V
0
2 Volts.
... as per given V0 wavefonn.
In the negative half V0 from circuit is,
=
Vo = V 2 Volts
... as D is on.
Thus the circuit of Fig. 2.35 produces the required output
waveform.
Q . 24 Identify the circuit and draw output waveform with
Mill
proper voltage levels. Refer Fig. 2.36.
(F-2654)
·w~f t~ I·~ r
Fig. 2.31 : Input output voltage
Q. 23 .Implement appropriate circuit to generate the
waveform as shown In Fig. 2.32
1MM101
<F-4714) Fig. 2.36
Ana.:
(B-2644)
Fig. 2.32 : Output voltage
Ans.:
Assuming that the input voltage to this circuit is a square
wave having zero average v,_Iue as shown in Fig. 2.33.
The given circuit is a biased damper circuit. The output
voltage waveform is as shown in Fig. 2.37.
.Vo = V.m - V c
But Vc = 7 v
.. Vo = V~n-7V
. . . v. o
"--·;........
...... ._.J.~-"--~-r--r--:-_.:_-H--+-+-~.
i I
...,..._....._......,.
; i
J_.,....,.._.,_....;.,i
. .. l .
,, r
.............
;. !
~
·:.·:!Y.. ~-~'i[--~~-~~
~~-~:_·.~~~.:_.~:~. -~-~-~-'~.....J::
i
i''""'
·! --··--k
... ; · f... ~' "'i....
;
;
.. {
f
. -1'N "-·--~-
'
•
...:. ..a..• J
1
1·
.. .. L..)
...~- ~
··+. · -·t
l
1
;.....q+··-. . :.. . ..,. . . . . . . . .:.t . . . .:·.__.......~·····
.... :.,. :~ . . ~j .......... _!
.._....t........... ...L
Fig. 2.33 : Input voltage
(1)-1580)
Fig.l.34
The input/output waveforms shows that there is a DC shift
of+ 7 Volts, because the average voltage of the output waveform is
+ 7 v as shown in Fig.2.34. Hence this circuit must be a biased
e a s V · S OIIIIIOII S
(F-4'1J> Fig. l.37
: Output voltage waveform
£ectronlc Devices & Clroults-1 (MU)
o 25
•
An.. :
4-19
Explain the difference ..._....__
onr....._n clipping clrculte and clamping ctrculte.
~~
I.
Parameter
2.
Components used
Function
3.
Frequency of input
4.
Applications
5.
Configuration
.
CUpper
Diode, resistors
To remove u part of Input
wavcfoml.
Not important us capacitor i:; not
used.
ca.mper
f,
Diode, capacitor, resistors.
to add a de shift to the input wavefonn.
The value of C needs to be chosen on the
basis of input frequency.
Voltage multipliers.
~~od~ clump, wave shaping
CII'CUJtS.
:.*+r
~~
0
(B-1844)
I
0
.
(B-1845)
Chapter 3 : Bipolar Junction Transistor
Draw construction and ~ymbol of p-n-p and n-p-n transistors,
Q. 1
Ans.:
n-p·n Transistor
p-n-p Transistor
E
(Emitter)
c
(Collector)
B (Base}
E
v
(Emitter)
Q. 2
T
E~ (Collector)
C
C
Coll~ctor}
B(Base)
(B-163)
B(Baoo}
(a) Construe~on
(Emitter)
B(Baae)
(b) Symbol
Fig. 3.1 : Construction and symbols of tr~istors
Why Is BJT called as a Transistor ?
0. 4
Explain construction of BJT.
Ans.:.
Ans.:
The term "transistor" was derived .from the wor~s
TRANSFER and RESISTOR. This tenn was ad~pted because It
best desc ·a.:- th
ration of a tiansjstor, which IS the transfer of
nucs e ope
. 't to a h'gh
1
an input sigDaJ current from a low resistance ctrcut
resistance circuit.
The structure of the p-n-p and n-p-n transistors is as shown
in Fig. 3.2(a) and (b) respectively. The n-p-n transistor is formed
by sandwiching a thin "p" type semiconductor between two "n"
type semiconductors whereas ·a p-n-p transistor is formed by
sandwiching a thin "n" type semiconductor between two p type
Q. 3
Why Is BJT called a "Bipolar" Transistor?
Ana.:
transistor takes place
The conduc ti.on 1.0 a bipolar junction
•
h 't ·s caJied as a
due to both electrons and holes. That ts w Y 1 1
ne
1
"bipolar" ~sistor. If the condu.ction takeths ptla.ceansi~~:r ~ ~:lie: as
·
'ty
earners
then
e
r
.
.
type of earners J.e. maJon
.
device is the field
"unipolar" transistor. The example of a umpo1ar
effect transistor (FET).
e a s v-s olutlon s
semiconduc~ors.
In both the types, base comes in between collecto.r and
emitter region. Base is always a thin and lightly doped layer.
Emitter and collector layers are much wider than the base and are
heavily doped. To be precise, the emitter is the most heavily doped
layer because it has to emit or inject electrons and the collector
area is slightly larger than the emitter area. The collector area 'is
largest because it is required to dissipate more heat. The transistor
has two p-n junctions namely the collector base junction and base
emitter junction.
4-20
"'
Electronic OeYioee & Circuita-l (MU)
Numbef of P"'f'' Junotlona and equivalent clrcutta :
.
. As sbo~ in F"t.gs. 3.2(a) and (b), a transistor bas two p-n
JWIC(IOOs ~ BE (Base to Emitter) junction and CD (Collector
to Base) Junction. A p-n junction is represented by a diode.
~ the P-O-p and n-p-n transistors are equivalent to two
diodes connected badt-to-baclt as shown in Figs. 3.2(a) and (b).
.
n
Emitter
BE
CB · n
p
.
~Collector
~-·_··•--~
- lt'L+~------~
• n
BE
Emmer
oHoles
(b) consti~tion of emitter current
Coll&dor current
CB
~Collector
Base
..
Base
E
(b) Equivalent for p-n-p transistor
(B-IU)
•ElectiOOII
VEE
Base
(a) Equivalent for n-p-n transistor
.......
Fig. 3.2
Explain bale principle of operation of BJT with
the help of construction, minority carrier
dlatrlbutlon and energy band diagrams.
Q. 5
Ma
14. Dec 15
Emitter electron current .
Ana.:
The positi~e supply VEE will forward bias the base-emi~r
juncti.oo and the .voltage Va:. will reverse bias the collector to base
junctioo as shown in Fig. 3.3(a). Thus the Ni>N transistor is biased
to operate in its forward active region. Hence 'tlie width of ·
depletion region for B-E junctiQn is very small, but that at tbe C-8 ·
juoctioo is large.
•• --•••••• --.-.:::,,..••••••• Doplellon rogione
~
c
E
BE~ -
LCBJuncllon
Fcn.d bUsj
-v,.~+
'-------1 .,
OJ-la)
-blued
8
-
duato ~blnation
· (c) Constitution of base and coUector currents
. (B-169) Fig. 3.3
.
2.
Some of the electrons diffuse through the base and
out of the base connection.
·
3.
The remaining large number of electrons will pass
. through the depletion region of CB junction and
pass through the collector region to the positive end
of tbe external power supply V~ as shown in
Fig. 3.3(d). The coUector current Ic is much
larger than the base current (about 98% or total
.emitter current).
e
c
vjUt••,t-------'
+
Fig. 3.3(a) : Transistor (npn) biased to operate
in the active region
Base elec:lron current
~.....
VEE
... 8
Vee
- I;r·-··_. ._.•_~e_._____:-::..l•~t-•.:...__-f--~..J!_
_
flc
Eleolron collolcmr c:unant lc
Operation:
(B-t,O) Fig. 3.3(d): Operation of the n-p-n transistor
1be sequence of operation for an npn transistor is as follows : .
6
Step 1 :
The electrons which are the majority carriers in the n- · Q,
State the configurations of transistor.
type emitter will start flowing towards the p-type
Ans.:
lwe as shown in Fig. 3.3(b). This will constitute the
The common terminal can be base, emitter or collector.
emitter cwrent Je.
~
S&ep 2 :
EJcc::trom moving from tbe emitter to base have three
pending on which terminal is made c~mmon to input
and
option~ as follows:
outp~t port there are three possible configurati'ons of tbe
J.
They recombine with the boles present in the base.
transistor. They are as follows :
AI the base region is thin and lightly doped the
1.
Common Base (CB) configuration
numbu of bolu is few. ~ out of the total
2.
Common Emitter (CE) configuration
injected electronJ from the emitter a very few
recombine witb lbe bo.le.s in the baae resion. This
3. Common Collector (CC) configuration
COMtUIIta lbe bale current fa. Thua base 0.7
c.urnat now. due to recomblnadon'a of
~ ud boles. The base current ia therefore
small u compared to the emitter current {typically
2'*' of total 1£). Tbia is shown in Fig. 3.3(c).
I
I ' 1
•, ltfllltil lt '•
a.ctromc Devtcee & Circuita-l (MU)
4-21
AM.:
Current amplification factor
~ configunttioo for the n-p-n and p-n-p
Q"lll5lsron •s as shown 10 Figs. l~a) and (b).
~
Ro
"'IlK; common
Ic
...(8)
~=r
B
Explain Input characteristic of
mode.
Q.8
1
trlnalstor In CB
Ana.:
ea.
common
(a) eo-oa base coaftgnntion tor n-p-n transistor.
Re
Rc
The input characteristic of CB configuratioo is as shown in
Fig. 3.5.
I.
The input characteristics is identical to the forward I-V
characteristic of a p-n junctioo diode. This is because there
is a p-n junction between the emitter and base of a
tTansistor and it is forward biased.
Emitter current
Vca= 8V
Yca=4V
Input
Ie{mA)
f ... ...........................
(b) Ceulmoa base conftgu.ratiod'for p-n-p transistor
(B-175)
resistance ri
.
.dVBE
1
= Me = Slope
Mt:
~...................... .
Fig. 3.4
'Ibe collector cwrent Ic of the common base configuration
is gi\'eO by,
1.
lc = Ic(INJ) + Icoo
...(1)
1c (INJ) : It is called as the injected collector Cllrrent and it is
due to the number of electrons crossing the collector' base
junctioo.
lao : This is the reverse saturation cllrrent flowing due to
the minority carriers between collector and base when the
emittec is open. 1coo flows due to the reverse biased
.collector base junction. As Irno is negligible as compared
to Ic (00) . It can be neglected in practice.
. . lc = lc<INJJ
...(practically) ...(2)
and
fc
Icoo
...(with emitter open)...(3)
1.
3.
4Vae
(B·l79(a)) Fig. 3.5: input characteristics of traosistor in CB
configuration
2.
3.
Up to the cut-in voltage, the emitter current increases
gradllally but after the cut-in voltage it increases "rapidly in
response to a small increase in the input voltage V EB·
The input resistance "rt of the transistor in CB
configuration is defined as :
=
r;
The name JCoo shows :
Ice
l
(B-177)
0
..
<Xdc
""
lc<INil
r;-
...(4)
l
1bj$
4.
Effect of Vca (output voltage) on the input .
characteristic:
As shown in Fig. 3.6, the emitter cwrent increases slightly
with increase in the output voltage VCB' 'Ibis happens due
to a special phenomenon called ·~Early Effect".
le(mA)
.... ..................,....
~t.........................
. ·
lc <lHJ) • • a* 1£ . .
Heace the expreuioo for lc u Jiven by,
1c .. a.ls + la-o
Bur fceo ia negligibly unalJ.
..
I
I
J
Ic .. awls
,, I II I I ,, II '•
...(5)
·
Emitter current
lnavaaes slightly
due to inoreaee In
v08 at oonllant
...(6)
.....-::::;;._..._"":":"'--_. V8 e{V)
V8E due "> Mrty elfed
(IloilO)
...(7)
...(1)
The value of r; of CB configuration is very small.
lS
. of a ranges between 0.95 to 0.995
~. < f:t.. Typjcally the vaJ.ueof.&.a b~• reg~lOll Larger the thiclaless
devtwting 00 tbe dlieknesi WI> - •
~ lk base. unaJJu iJ me value of adc.
From &,uatloo (4) •
constant VCB
=
..J
fi CB configuration will always be less
The value YJ <Xo~c or
·
because
IbM
Me
Input resistance can be obtained from the input
characteristics. It is eqtial to the reciprocal of the slope of
input characteristics in the linear portion of the
characteristic.
l
: . • r;
Slope
...(2 )
T..EmiUer Is open
ColeQior to base current
Since lcao flows due to thermally ~enerated minority
cauiers it increases with increase m te~rarure. It
doubles• its value for every lO"C rise in temperature.
CllrreDt aanplifk:ation factor or current gain («etc) :
4.
The ~ amplification factor or current gain is the ~o
~
cunem to the total input current For a CB configuratJon,
lc~the output current and 1£ is ootal input cwrent. .
=
Fta. 3.6: Effeet of Vca (Early effect)
That is why the voltage drop across a ttansistor (V()!)~
Electronic Devices & Clrcuits-1(MU)
Explain. outpUt charactMf1ttoa of tnn111tor In CB
Q. I
conftgu,.tton.
Jar e in the active region.
6.
AM. :
!n '!
IcC~
Adlve region
_ _j
(High output ~mle reaetanoe)--.,
7.
I
device.
~
Q. 10 With the help of neat circuH diagram, explain the
common emitter configuration of~ transistor. ·
!
L
2.
.
. rder to operate a tranststor
reo;""
10 0
. . 10 the saturation
ds
C>'v...
Therefore the saturatiO? r~gton correspon to negative
values of vCB as shown 10 Ftg. 3.7. .
The collector current 1c is _not constant but increases
expqpentially with incr~
CB• tow~ds ~o. The
slope of output ch~actenstlcs .'s large m thts region,
Therefore the dynainlc output Ce$1Stance has_ a small value.
That is why the voltage drop across the tranststor ( V CE) is
small in the saturation region.
·
.
In the active region, 1c does not depend on V cs· It depends
only on the input current.18 . That is why the transistor is
called as a ·"current Controlled" 0C "current Operated"
Output cl:l~sdc of any circuit is always a graph of
output ewietlt versus oulpUt voltage. For the CB configuration, the
OUipUt cu.mmt is col.lectQt current (fc) and the output voltage is
collector to base voltage (Vco>· The output characteristic is plotted
fur a CObstant value of input current (It;). Output characteristics of a
n-p-a transistor i5 as shown in Fig. 3.1.
r. . . . . . ....... . . . . . . . . . . . . . . . .
.
Sa~ratlon region : Both th_e JUn~tlons are f~ard bii!Sed
Ans.:
........ ~
A transistor can operate in my of three regions of
operation.
1be regions of operation are : · .
I.
Cutoff region (trmsistor off) ·
2.
Active region
3.
Saturation. region
The biasing of the two junctions of a transistor is done as ·
:(a) Common emitter configuration for n-p-n transistor
........
3.
These regions have been shown in Fig. 3.7. ·
Cutoff region : The region below the curve for IE 0 in
Fig. 3.7 is called as cutoff region. The input current IE= 0
and the transistor is in its off state. The output current
lc ICoo which is very small in magnitude..
Adive region : In this region the collector current 1c is
almost equal to the emitter current IE md it almost remains
constant. That means if IE is constarlt then Ic remains
coost.ant irrespective of the variation in the output voltage
VOJ• 'Therefore the transistor is said to operate as a
"coostant current source·~. (There i.s sligh~ change I Edue
to early effect.)
=
=
4.
in
$.
~
D)'DamJe output resistance of the transistor : The
dynamic output resistance of a trarisistor is defined as :
...(1)
It>. constant
This is nothing bui the reciprocal of slope of the output
characteri.stics in the active region. Slope of the output
c~s in the active region is vecy small. Therefore
tbe dynamic resistance (r0 ) in the active region is large.
f; ,1 ~. 'J
' • II I II I I IJ II S
Emitter Is
oommon
(b) Common emitter confi~rati.on for p-n-p transistor
<B-185) Fig. 3.8 .
transist!!~sc~":on e~Ftt~r configuration for the p-n-p arid n-p-n
own m tg. 3.8(a) and (b).
curren~~r: the CB configuration
, the relation betWeen the three
=
IE
lc + Ia . where
earrange this equation to get,
R
lc - lcao =
lcao
1c
.. a;;:- adc
Ic[a~
-1]
<Xdc IE
= IE=Ic+I8
=
.. Ic [·~:de J : :
I + lcao
B
I
o
<X
de
+~-DO
a de
1c =adc IE + 1cao
~lc Devices & Cfrcults-1 (MU)
~
:.
4-23
la[ 1-· ~a:Jl+ (l.!coo
- ~)
"'
CUfTM'l Gain P. :
...{1)
As fl.sc is tbe ratio
cunent
.
1-c and mput
. of output
·
·
current l ,
cal~ COIJliDOO C~tlter C~nt amplification factor or si
current gun. Thus transt~tor a~ as current amplifier.
mp Y
The value of fl.x Is much higher than ~·
.
.
r
il IS
'
Assuming • aclt =
[1 ~ l = 1
_ !c
- a:J -~ =__!c._
lu-lc -1
Substituting this value in Equation (1) to get,
','
l
"C
But flc~c
:Ar_
...cit~+
=
. . 1 + aclc
=
.. 1 + flctc
=
fcso
.•.(2)
...(3)
~
-
6. VBB
-6. 1a V
Cl!
constant
...(l)
Its value can \)e obtained from the input characteristics
because "rt is equal to the reciprocal of slope of tbe input
characteristics. The value of dynamic input resistance "rt is low
(typically 1 k.Q) for the CE configuration but it is not as low as that
of CB configuration.
Q. 13 Explain output charaCteristics of a translatOr In
(1 - a..t.,)
CEmode.
adc + 1 - a~
+1=
(1- O...C)
1- CX.x
1
<X.sc
(1.
r
i
8
(1 - ~
The input characteristics resembles the forward
characteristics of a p-n junction diode. The reason is that B-E
junction is a forward biased (>:-D junction.
The base current increases rapidly as the base-emitter
voltage crosses the cut in voltage of the BE, p-n junction, The
dynamic input resistance is defined as :
Ans. :
.
-.nctJ
... (4)
Substitute this in Equation (3) to get,
IC = Pc~c Is+ (1 + J3ct) ICoo
Equation (5) can t?e expressed as
lc = l3c~cis +lap
...(5)
AD output characteristic of a CE configuration is the graph
of output Clll'fCnt (Ic) versus output voltage (V~ fo/ various. fixed
values of the input current (18 ) . The typical output characteristics of
a n-p-n transistor operating in the CE configuration are as shown in
Fig. :3.10.
...(6)
wbere Ia;o is the reverse saturation. current for the CE
ooofiguratioo which is given by,
If a..t.,
~oro = . (1 + l3c~c> lcso
...(7)
=0.99 then substituting this value in Equation (2) we
get
0.99
1-0.99 = 99·
Thus J3c~cis much higher than adc.
Cutoff region
Q. 11 Define .the reverse leakage current of a CE
{B-t88) )fig. 3.10 : Output characteristics of a n-p-n transistor ·
configuration.
in CE configuration
Ana.:
The reverse leakage current of a lrallsistor operating in the
CEcoofigw:ation is denoted by" Ia;o'~ and is defined as:
Reverse leakage current (CE configuration) :
As shown mFig. 3.10, there are three regionS of operation
namely the cutoff region, active region and saturation region.
1.
Cutoff region :
Both the BE and CB junctions are reverse biased to oPerate
the transistor in cutoff region. The base current Is = 0 and
the collec_tor current is equal to the reverse leakage current
Ia;0 . The region below the characteristics for I8 = 0 is. ·
cutoff region.
2.
Active region : .
lcm =(1 + f3d.c) lcuo
Q. 12 Explain Input characteristics of a transistor In CE
mode.
AM.:
the
At constant output voltage V CF.
input characteristics .of. a
n-p-~~ transistor is as shown in Fig. 3.9.The input cbaractenstic
also sbows the effect of VCF.:~
.,.U OUIJ*llfe (,.A)
VeE • 5V Vee "' 15V
80
eo ··················
M_.v;-1~
.. ~
uVCE~
<I-1J'7)
2D
~
_:__r
1.0
vfltE
VIII!(Voltl)
111)111 voii4QII
1.6
os11to f the CE
Fig. 3.9: I.Dput ~ ot I tnt
r a
At a constant base current 18 , the B-E junction is forward
biased, and C-B junction is reverse biased to operate ·the lrallsistor
in the active region. The collector current Ic increases slightly with
increase in the voltage V0!: However the collector current. is
largely dependent on the base current Is· At a fixed value of VCl!• if
Is is increased, then it will cause Ic to increase substantially. This
. is because le =J3c~c I8 • This relation is true only for tbe active region
of operation.
3.
Saturation region : ·
The BE junction as well as tlie collector junction must be
forward biased to operate the transistor in its saturation region. The
collocoor base junction can be forward biased if and only if VCF.
CODft radon
1: ;,
~.
II •, 11 I II I I II If S
..
Electronic Devices & Circuita-l (MU)
......... le
drops down 10 about 0.2 Volts. Because then v8 0 • 0.7 Volts will
furward bias lhe CB junction. This is as shown in Fig. 3.11.
U5Ually the satunltlon voltage of a transistor, VCl! <•tl is between
0.1 10 0.3 Vol~
E
The collector cu.rrent increases rapidly with increase in Vca
as sbown in Fig. 3.10Jn this region 1c is approximately
independent of the base current and function of V01. Therefore in
this regioo the transistor is considered 10 be a semiconductor
resistor of very small value. Tile transisiOr is operated as a .switch
, in this regioo.
(a) Conunon coUector configuration for n-p-n
.......·-le
T+
VCE = 0.2 Volts
+
(B-189)
L
Fig. 3.11 : Forward biasing of CB junction .
Dynamic output resistance ( r0 )
4.
E
The dynamic output resistance ( r0
Collector Is common
:
)
of a tr;msistor in CE
. (b) Conunon coUector configuration tl"amistor ror p-o-p
<XIIlfiguration is defined as :
=
ro
Definition of
· 5.
Pc~c
transistor
6. Vrn .
6. r
"C constant 18
(F-21)
...(1)
The v
Fig; 3.12
is input voltage and 18 is the input current whereas
v is the c:=tp'ut voltage and IE is the output current. This
co~guration is also known as "e~tter follower" con.figuration.
Pee :
· Fig. 3.12(a)does not show the pracucal way of.re~sentmg the CC
. configuration. Practically it is drawn as shown.m Ftg. 3.13.
Ic
= T8
The value of f}dc <;an be obtaiD.ed from the output
Current gain of CC configuration :
cbaracteristics. At any point on the characteristics w~ can calculate
The current gain of a transistor in common collector
Pdc by taking the ratio of Ic and 18 at that point. AC beta of. a · configu,ration is denoted by y (gamma) and is defined as,
transistor is :
IE lc+ Is
Current gain y =T =- 1- =(1 + ~de)
s . s
~Ic
floc
= .. I
... 8
V00 constant
...(2) .
•········ lc
r-----o+Vcc
~oc
is the slope of the transfer characteristics. Thus the
value of ac beta can be obtained at a constant value .of Vrn from the
output cbaracteristics. The values of ~de and ~ac · are nearly the
same.·
8.
Maximum Vee and breakdown :·
Ill tbe active region the collector junction is reverse biased,
80 there is a limit on the maximum value of VCE' If V00 exceeds
this maximum value, collector junction will breakdown due to the
punch through effect. A large current will flo~ which will generate
exce.sive beat to damage the transistor. Hence for safe operation
Input
Volt<Jge
VBB
•
:-+ .
<F-13l7)
Fig. 3.13: Practical way to draw the common collector
co~ration
v0!. < vC£ (lllu)"
Q. 14 With the help of neat circuit diagram explain the
common collector configuration of a BJT .
Q. 15 Draw and explain Input characteristics of n-p-n
translator In CC configuration :
AQ8.:
Ana.:·
The Common Collector (CC) configuration for p-n-p and np-n tJaD.Si.ston is as sbown in Figs: 3.12 (a) and (b). In the common
coUcctor coofiguration, the collector is made common to both input
Inp~t characteristics is the graph of input voltage V~
versus ~e ~nput c~nt Is at a constant output voltage VEO ~
shown m Ftg. 3.14. Considering the characteristic for V
1 V.
The. base-emitter junctiQn is not forward biased up to v
1.5 V.
Therefore the base current is zero up to Ysc = 1.5 v. Then it
aod output.
1:
a •, II
•. fi lii I IIIII '•
:==
f)eCtl'onlc Oevtcee & Clrcutta~l (MU)
4-25
1.'
1~ rapidl)' •a the Vlk' Ia lncre48ed be)'ond
beCIUIIC
V. TJds la
Ana.:
8-Bjunction is more and moro forward biased.
Jn order to operate the transistor as a switch, we have to
operate it In the saturation region. In CB configuration, it is
necessary to apply a negative voltage (VCB) to an n-p-n transistor
so as to bias it in the saturation region. Moreover tbe input cwrent
(Jn) required to drive the transistor into saturation is bigb. For a CC
configuration, due to the presence of R£, a high .base voltage is
required to forward bias the BE junction and as the collector is tied
to + Va;. it is not possible to forward bias the CB junction. So a
transistor cannot be saturated. Due to these reasons, tbe CB and CC
configurations are normally not preferred when tbe transistor is to
be used a..s a switch.
l,.,uu OUI'IWII
Itt
(IIA)
70 _................................... ······••·•••••·•••·•· ·•·····••··
20
o~----~~~~~~L-.5
Voc (Vollll)
Q. 19 Write
Input voltage
CF·l321)
Ffa. 3.14: Input characterlstks ofa transistor 1n CC,
output charactertatlca
tranalator In CC configuration.
of
a
An output characteristic is a graph of output voltage y EC
versus the output current IE for constant value of input current 1 .
The ~t ~haracteristics of a n-p-n transistor in C.C.
coofi~tJc:m, IS as shown in Fig. 3.15. From Fig. 3.15, the output
cbaracteriStJc of CC configuration are similar to those for the CE
ooofiguration. This is because Ic is approximately equal to Is:>
=
Hence current gain of CE configuration
7·
I
.
B
~s the vaJue of~ is much higher than 1, the current gain of
~ and CC configuration is large. Hence for a small change in the
o~~~~~~~--~~~--~
Output voltage
VEe (Volts)
Fig. 3.15 : Output characteristic of a tramistor in CC
conftguradon
Q. 17 Give reason : CE configuration of BJT Is preferred
over CB and CC.
= (1 + f3)
B
: -Lt~~~~~==t1~
5
=( = f3
.
IE
And current gain of CC configuration =I
5~-:rj:~~=.=~~
~
...(2)
.
~
3
a Current
IE
(1 + f3)18
The current gain is defined as,
·
Output cutrent
~urrent gain AI = Input current
OUipUI currant
IE (rnA) T
.
2 .
as
When used in the CE configuration, tbe relation between
the output current Oc> and the input current (Is) of a transistor is
given by,
lc = ~18
• • . (1)
And in the CC configuration, the relation between the
output current (IrJ and the input current (18 ) is given by,
n-p-n
Ana.:
e
short note on : Translator
Ana.:
con.ftguradon
Q. 16 Expltlln
a
Am~lffler:
mput curre~ we get a large change in output current Thus current.
amplification takes place and the transistor acts as a current
amplifier. Trao~stor does not act as C1:1I'tent amplifier when used in
the CB configuration.
Q. 20 How transistor works as a voltage amplifier ?
Ans. ; ·. If for a small ch~ge in input voltage, a proporti9nallarge
change m output volt:'ge.IS ~btained, then v~ltage amplification
ha~ taken place. The ClfCU.It diagram is shown in Fig. 3.16:
I.,Jyn:t
Vee
Ana.:
Out of the three configubtions CB,CE and CC, the CE
configuration is the most popular and widely used configuration.
The reasons are as foJiows :
1.
It bas a high voltage gain as well as a high current gain.
2.
As voltage gain as well as current gain is high, it has a very
high power gain. This is .because, power gain is the product
of voltage gain and current gain.
3.
The CE configuration has moderate vaJues of R1 and R0 •
Therefore many such stages can be coupled to each other
without using any additional impedance matchlng circuits.
Due to thl• autornatic impedance matching, maximum
power transfer will take placeJrom one stage to the other.
0.18 Why CE configuration I• preferred over CB and
CC when UNd u a awttch.
·
ii4iili
(.B-230)
Fig. 3.16
The transi~tor is operated in the CE configuration. The
outpu~ voltage V0 1s taken at the collector with respect to ground;
lu.
•·
Yo = VCil
Due to a small change A V11,. ~re will be a small change in
... (1)
I. I ·II
.II III IIIJII ' •
Electronic Devices & Clrcults-1 (MU)
· ,!c
Hence the corresponding change in collector current is
given by.
t:.Ic
=
Pt:.Io
'
.
B
•
•
t:. yo :: lilcRL
... (2)
Substituting the value oft:. Ic to get,
liV0
t:. vln
= PRxRL
8
flR~
. . t:.V0 = Rxt:.Vln
... (3)
B
Q. 21 Deft~ the contributing factors forwards the low
frequency common base current gain of BJT.
,...!!'llm·•--e·•
Ana.:
1be parameters which relate the current components are as .
follows :
1.
5.
·
Current of injected carriers at JE
Tot31 emitter current ··
Where, JE
Emitter base junction. ·
In case of a p-n-p transistor , .
y
Where, Ip,
=
=
t
lpE~~ =
=
=
Small
. .(
2)
( )current amplificat:J'on factor ·and is the ratio of collector current
as
' <lc) to emitter current (Is). ·
_ !.!c at constant collector-base voltage VCB
a -
Hence,
As •
and
1
'· .• ,) v s 1111111 fJ ll ~
=
. .. ('.' .t:.IE=t:.l8 +t:.Ic)
.!:. lc + .!:. Iu
.!:. lu
1
.t:.Ic
=1 + .t:.Ic =1 +~
a
or,
la -- l±.l!
p
and
=
_lL_
p =
......£.._
a
I
+P ..
1-a
. . A small variation in a. corresponds to a large variation in ~­
So, It IS bette~ lo determine Pexperimentally and calculate the
value of a usmg the following expression,
a=.JL ·
...(5)
Since 1c and IE have opposite signs, then a as defined is·
always positive. Typical numerical values of a lie in the range of
0.9 to 0.995.
4.
DC current gain :
If leo is negligibly small as compared to Ic. a
approximately equals to Ic I IE. This is referred to as the de current
gain of the common base transistor and is denoted by adc:.
So,
a = ~- .t:.lc .·
t:. IE - t:. lc + t:. Is
or,
or,
off)
=p ~ 1
p -- . ~
t:. Is
(4) .
Large signal current gain (a) :
It is defined as the ratio of the negative of the collector
current inCrement to the emitter current change from zero (cut
· to as the large signal current gain of a common base transistor, or
t:. Ic .
t:. 18 .
Relation between a and P:
3.
= - !c.=.!w
1E
=
Ana. :
Where, l c = Collector base junction.
In case of p-n-p transistor,
a
P
Q. 22 Derive the relation a
and ~ = Injected electron diffusion current at
emitter junction.
2.
Transport factor P* :
The transport factor is defined-as:
Injected carrier current reaching lc
P~ =
Injected carrier current at JE
...( 3)
..
t:. IE
The beta factor (~) is the current g~ fa~tor (al_so known as
the transport factor) of a common emitter crrcwt and 1s defined as
the ratio of collector current <lc) and base current Os)·
Injected hole diffusion currel!t at emitter
i;I
.
There are two current amplification factors, the alp~ factor
ct ·and the beta factor (.j3) defined as, the alp~a factor (a) ts known
junction:
p• =
.
Current amplification factors :
Hence,
...( 1)
c
SlgD
•
Emitter Injection efficiency (y) :
1be emitter or inj~tion· efficiency 'Y' is defined as :
y
s:.au signal
current gain a.c :
. aJ ~urre
~~lit gain a.c is defined as the ratio of
t to change m eiDJtter currenl
change in collector curren
~ for constant collector-base
aoc = t:. 18
i.e.
voltage VCB
· ct is.. always positive but less than unity (very close
ac
•
'th v I and temperature.
.
to unity). It vanes WI . CB• E
6
Thus fot a small change in Vin • a large change in V0 · is
obtained and the voltage amplification bas taken place. Hence the
BIT acts as a vollage amplifier.
=
IE
. al
nnc:itive and less than unity.
a IS ways r---
t:. vln
= PT
Hence the corresponding change in output voltage 1s gtven
by,
ac~c:
l+P
Q. 23 Ust the Ideal conditions of BJT •
i•MMQ
Ana. : The transistor has the following ideal characteristics
1.
2
·
3
·
4·
5.
6.
All_the regions are uniformly doped.
Emitter and base widths are constant
The energy band gaps are constant
Current densities are uniform.
Low injections.
Junctions are not in breakdown.
'
-
4-27
r:;tectronic Devices & Clrcults-1(MU)
Q . 24 List non-ldealeffecta In BJT.
Ana.:
Early effect in tbe CE configuration :
Ana· : The important nonideai effect are :
1.
2.
3.
4.
5.
6.
Base width modulation
High injection
Emitter band gap nanowing
Current crowding
Non uniform base doping
Breakdown voltage
Q. 25 What Ia base width mOdulation
For • glvaJ value of VIll\• if we inatale VClllhcrl
'
'
'
V CD incre~ as V Cll
t .W V BB is comWll
. • CD jllllCtloo Is IJIOI'e reverse biased
? Explain with the
•• Depletion region extends deeper into the base
help of proper diagrams.
An&:
The total base width is equal to the sum of the widths of the
depletion regions ·extended into the base region from the collector
and emitter.side and the width of the region occupied by the free
cbaige particles. But as the EB junction is forward biased, the
width of its depletion region is very narrow (Fig..3.17). As the CB
junction is reverse biased, the width of its depletion region is much
larger.
Tbus neglecting the width of depletion region at the EB
junction,
Total base width = Width of depletion region at lbe CB
junction inside the base region + Width of the region ·
containing free charge particles.
As VCB is increased, the reverse voltage applied to the CB
junction increases. This widens the depletion region at the collector
junction. Due to this, effective width of the base region (Fig. 3.17)
decreases. This will increase the charge concentration gradient in.
the base region. Due to increased charge carrier concentration,
more number of electrons ·diffuse from the emitter to base i.e.
emitter current increase.s. Hence with increase in Vco the input
current IE increases slightly.
The reduction in effective base width due to increase in
Va~ is called as "Early effect" or "Base Width Modulation".
'
'
,.
:. Width of the nouiral region reduces.
Dec. 03. May 06. Dec. 11 . May 14
t 8lld diffusion current ,
. :. Gradient of minority cairier coocauratioil
> through the bose t
•
. . . ·~
.
J :.' ·Jc.t as,..,.VCil illcreaseli.. .
)
Thus due to Early effect the collector current lc increases
with increase in VCE even when V BE is constant. Therefore the
output characteristics are slanting upwards.
The relation between Ic and V j.. is as foll.ows :
lc = &J (V~ + VA)
Where &! = Output conductance
VA = Early voltage
Q. 27 List Applications of transistor ;:
Ana. : The important applications of a transistor are as follows:
Amplifiers
Oscillators
Logic circuit$
Delay circuits.
1.
3.
5.
7.
Switching circuits
Wave shaping circuits
Timers and multivibrator
2.
·4.
6.
0. 28 Determine lcao at 75° if it has a vaiue of 10 J&A at
30" c.
·~fi.ltlttj
Ana. : ICBO doubles with every .10°C rise in temperature.
:. lcs0 (75°C)'
= l.07'nlrno(30°C)
45
=
(1.07)
X
10 ~ ~ 210 ~
Q. 29 BC147 transistor· has very thin and lightly doped
base region. Justify.
l®fi:lelel:l
Ans.:
-
Tolll-
(a) For smaller values ofVCB (b) For large values ofVCB
(F-tm) Fig. 3.17:
Early effect or base width modulation .
The current gain ~ of transistor BC 147 is very high. In
order to obtain a high value· of ~ it is necessary to keep the base
region as thin as possible. This will reduce the recombination's in
the base region and reduce 18 . It will also increase Ic for the same
value of Is· This results in increased fl as fl := Idf8 .
Q. 30 Complete the sentence : The thermal reverse
Other effects of base width modulation :
·
l.
Since the base width decreases due to th_e early effect, ~e
number of recombinations taking place 10 the base region
will reduce. This will increase the values of both, the
•
r
A* and the common b~ current
transportation ,actor ..,
·
.
v
amplification factor a!,. with increase In the .vo.1tage CB·
2
Due . .
. the charge gradient Within the base,
·
to mcrease m
·
· J'ected
more number df "minority" charge earners are m
f
•
. • crease the current o
across the junction. Tb1s WI11 m
minority carriers.
Q. 28 Explain early effect In the CE configuration.
.....
_
saturation current of transistor -
for every -
oc rise In the C-B junction. Hence calculate the
reverse saturation current of a transistor for
junction temperature of 8JOC if Ita · reverse
saturation current at 23°C ls10nA.·
l~~l§W<nm:l
Ana. : Doubles, l0°C.
Solution or the problem :
lo2
But ~T
:. lo2
=
(J.07)AT
=
87-23 = 64°C, 101 10 nA
64
(l.07) X 10 nA 759.56 nA
=
l ol
=
=
...Ans•
Electronic Oevloes & Circuita-l (MU)
Chapter 4 : DC Circuit Ana
Q. 1
lysis of BJT
Expillln neceulty of bluing for BJT amplifier.
ard active region, saturation and inverse active.
.
·
namely cut-off, forw
b'ased as shown in Table 4.1.
Transistor can opemte in any of the four regtons of operatio~s
h ld be forward or reverse 1
To operate the lranslstor in these regions the two junctions of a transistors ou
.
.
·
tio0 and appJkadons
- '>~'
Table 4.1 : Regions of opera
Ana. :
.
·. 1~
Cut-off
Forward Active
Saturation
Inverse Active
A~ :t·.:
oUet*M:.b~~o •.;~ --· · · · ~
·C ·
·
As a sWitch
Base bitter Juncdon .
Reverse biased
Reverse biased
Forward biased
Forward biased
Reverse biased
Forward biased
Forward biased
Reverse biased
Amplifier
As a switch
In the digital circuits
Rearranging the Equation _(l) to get,
Q. 2
What •re the crlt8rla to select a suitable biasing
networtt 1
I11@W•IOi
Ana. : Following are the important factors to be considered while
designing a biasing circuit :
I.
Position of a Q point
2
Value of Ic (collector current) at quiescent point i.e.lcQ.
Value of every stability factor shquld be as low as possible.
This is essential for ensuring higher stability of the Q-
3.
poDit
4.
Transistor should be biased in the lirie;u portion of its
transfer characteristics.
Q. 3
For a BJT
ampl~r,
show with the
~lp
of
Ma 03. Ma 05
Ana. : To draw de load line , considering the common emitter
CQDfi.guration of Fig. 4.l(a) and the collector circuit of Fig. 4.1(b).
·~-----Ic
T
j__
+
-=-Vee
= [ -~Va:+
Ic
i:
..
(2)
Com~g Equation (~) with the general equation of a
straight line.
...(3)
i.e. y = m.x + C
The comparison yields the .following results,
y = ~
. x = VCE
m = -II~
C = Vex;/~ .
This comparison sho~s that· Equation (3) ~nts a
straight fuie. This straight line is called as the de load line.
1
Ic = [--R 1 Vee +
8
circuit, how to draw 8 d.c. load line ?-
VeE
.
c
vcc
~
c
{B-2544)
·
.
'--r-'
y=-m
X+C
Substituting VCF. 0 in Equation (1) to get ~ Vcc I Rc
which is lc·max or point "A" in Fig. 4.2 and substituting ~ = 0 to
. get Va;: V00 which represents point "B" in Fig. 42. The "DC"
word indicates that this line is drawn under the de operating
conditions without any ac signal at the input And the word load
lint is used because the slope of this line is - 1~ where Rc is the
load resistance. .The de load line is drawn on the output
characteristics as shown in Fig. 4.2.
~
....._,._...., "'--y-'-'
=
=
=
lc(mA)
.
v
lc ...
{a) Common emJUer conllguration
.
,: . . - Adlve region
@ !
----1
= ~ .... ~'f--------'s4 =40 pA
~-------Iss= 30 pA
R
·'
(b) Collec:tor circuit
(J.m) Fig. 4.1
ProceduN to plot the DC load line :
Applying KVL to collector circuit of the CE configuration
drawn in Fig, 4.1(b) to write,
·
... (1)
Vex;- VCE- lcRc '"' 0
1. 1
·;
', II Ill I I II II '•
CutoH region •
<F-284) Fig. 4.2 : DC load lint showing tile Q point on output
characteristics or the ~r
4-29
Electronic Devices & Clrcul18-1(MU)
Q. 4
Drew D.C. load line for the circuit ahown In
Fig. 4.3(a).
••••
+
ev
Explain the Hlectlon of a Q.polnt for 1 tranalatoi'
blaa circuit and dlacuaa the limitation• on the
output voltage awing.
lti§Mt.j
Ana. : Depending on the application, the position of the Q point
can be selected on the load line. This is shown in Table 4.2.
Q. 8
CF·I338) Fig. 4.3(a)
Ana.:
1be given circuit is a CB circuit. 1be output voltage is v
and output current is Jo
CB
Applying KVL to the C-B loop of Fig. 4.3(b) to write ,
· Va:;. = lc Rc + VCB
v v
-ie
+~
This is the equation of de load line.
1
20
:. Ic
4~ VCB + 4k
=-
.
It;;..~.-
I:~,-
:. Ic =
......,..,-
Table 4.2 : Position of Q point aod •ppUcatlon
20V
...(1)
~:~
·,
Open switch
In the·cut off region
Closed switch
In the saturation region
In the active region
Amplifier
The shape -of amplifier output signal depends on the
position of Q point. Considering the three possible positions of Q
point and its effect on the output signal of the amplifier
Effect or Q point close to cut-off :
Fig. 4.4(a) shows that the Q point is adjusted closer to the
cut-off region and an input signal is applied which changes the
base current by 20 JAA. Due to this the positive half cycle of the
outpufvoltage gets distorted as shown in Fig. 4.4(a) and the output
voltage swing with an unqistorted output will be limited.
... (2)
Substituting lc =0 to get VCB(max) = 20 V aDd VCB = 0 to
20
get lc-.: =4k
=5 mA.
The load line-is shown in Fig. 4.3(c).
(F-3!14) Fig. 4.4(a)
: Effect of Q point close to cut-off region
Effect of Q point close to satora~n :
Fig. 4.4(b) shows the effect of Q point adjusted close to the
saturation region. In the positive half cycle of 18 , the transistor goes
into saturation. Henc~ the collector current remains ~onstant at 1c
<sao· Hence the negative half cycle of the output voltage and
positive half cycle of Ic gets distorted as shown in Fig. 4.4(b). This
will limit the output voltage swing with undistorted output to a
very small value.
DIR>Jtlon In
lc(mA)~
· · ~·· .........
:bv ./ ,/
the oolleotor ounent
waveform\
(c) DC load line
<F-1339> FJg.4.3
Q. 5
.
............ . .{;)
.a
.
t ../
··•
Q Point le oloM
k>abJra~
.....
.... ........ i;}\
•t,r.;..;
···~·----~~1 . l
-
Define : Quiescent Point (Q Point) •
Ana.:
1be term quiescent means quiet, still or inactive. Therefore
the Q point is a11o called as "operating point" or "bias point". Q
point is the point 00 the load line which represents the de current
through a transistor <Y and the voltage across it (VCEQ). when no
ac signal is applied at the input. In short it represents the de bias
condition. Co-ordinates of Q point are (VCEQ• ICQ).
!;
a ·. v ·. n11111 1111 s
CF·39S> Fig. 4.4(b) : Effect of Q.point close to saturation region
-
4-30
8ectron1c o.vtoee.& Orcutta·l (MU)
o..Point In the eattYe Nflon :
The criterion of Rl«tlng qu.ieseent point t.o operate the
IJ'IOiillot u an ampUfler Ia as follows :
1.
The Q point should not be too close to the cut-off region.
2.
lbe Q point should not be too close to the satu.ration
... ..T
reak*·
.L--~
The oonditioos (1) and (2) should be satisfied in order to
avoid any waveform distortion in the amplified output
signal.
•i?
.
•tJ?
.
At Vo
.l.
..........
<F-285) Fig. 4.5 : AmpHfler circuit drawn part1ally
J".··
~fJ/···
~--
........
.
. ia~·~
~:~i--~~-/~__. _·~-~
lc (mA)
Q Point VaiUIII
Ioo•so.aA
-1
Slope= <Rc II RJ
Joo•3mA
Vceo ,. 8 Voila
tc•aM
......
~
'<
8
(F-393) Flg. 4.4(c:):
Graphic:al representation of
ampllftc:atiou process
Fig. 4.6: AC and DC load lines
Q. 8
3.
4.
Q. 7
'The Q point should be located at the centre of .the de load
line so tbat the variation in the amplified voltage is equal
correspooding to the positive and negative half cycles of
tbe input signal. 'This will ensure that the amplified signal
will be an exact replica of the input signal.
In Fig. 4.4(c), the component values are so adjusted that the
Q point is situated exactly at the center of the de load line.
The co-ordinates of the Q point are :
Q point = (VCEQ•Iw>= (6 v. 3 mA)
1be value of quiescent base current i.e. 18 Q =30 JA.A..
For a BJT amplifier, ahow with the help of a
circuit, hoW to draw a a.c. load line ?
Ma 03. Ma 05
Ane.:
Pig. 4.5 shows an amplifier circuit partially. The de load
resi.ltaoet: is Rc but the AC load resistance by considering Cc as
sbof1 aod + Vcc coonected. to ground is CRc II RJ. If a load line is
drawn the slope of which is - 1 I (Rc II RJ the!) it is called as an
AC load line and it is to be uJed when tbe transistm: is operating as
an~tier.
The AC Joed line thus represents the AC operating
cood.itions of a circuit. The parallel combination CRc II RJ is
alway• JeQ dwJ ~· Therefore the slope of AC load line is higher
tbao m.t ~the DC 1oed line a.a abown in Fig. 4.6.
tie li&F111D11'1R
What are the factors affecting the stability of Q
point?
Ans.:
The factors affecting the stability of Q point are :
1.
Changes in temperature.
2.
Changes in the value of ~de
3.
Variations of parameters f!om one transistor to the
other. However the Q point instability due to any
reason is not desirable because it will introduce
distortion in the amplified signal. ·
Q. 9
What Is bias stabilization In BJT 1
IMfJU
Ana.:
. Bias stabilization is a process of stabilizing the Q poinr
(bias point) of the circuit. Hence there is need to design a biasing
circuit which will keep the position of Q point stable on the load
·
line.
Q.
10 Deflnestablllty factors of transistor.
Ana.:
The stability of Q point of a transistor amplifier depends on
the following three parameters :
1.
Leakage current leo
2.
~de
3.
Base to emitter voltage
EJectronlc Oevlcee & Chculta-1 (MU)
4-31
The effect of these parameters can be e~~:pressed
mathematically by defining the stabiUty factors for the three
pemneters individually as follows :
1. Stability factor,
A~
s - -
A leo constant vBli and pdc
.
or
Rearranging the Equation (1) to get,
Vee- Vsa
..
Is
=
Rs
Is
a
~
aleo ..•(1)
+
~s represents ~ change in collector current due to
cbaDie m reverse saturation <;urrent leo· 1be other two parameters
dill means V BB and Pc~c are assumed to be constant.
+
2. Stability factor,
a~c
or -va
constant leo and pde
aa
represents the change in Ic due to change in
=
S'
,
s
Ale
A vBB
ooostant leo aud Pc~c·
...(2)
•
v
Bli
3. Stability factor,
s" -
A Ic
pdc
I
CODSUUlt leo an9 V BE or
aIc
apdc
...(3)
0. 11 Which are the bias stabilization techniques ~f
trMslstor ?
.
.
Ana. : Bias stabilization means techniques used to stabilize the Q
poinL Some of them are as follows :
1.
Collector to base bias circuit
2
Voltage divider bias circuit
3.
Flxed bias circuit (Si~$le base resistor biasing)
Q. 12 Discuss fixed bias circuit used for BJT.
Dec 02 r.1a
0-l. l\1a
(F-289) Fig. 4.8
at
: Base drcuit or base lOop
For silicon transistors V BE = 0.7 V and for germanium
ttansistors it is 0.3 V. Therefore VBE < Vee• hence neglecting VBE ,
Vee
Is = R
...(2)
B
This is th~ approximate expression for the base current
corresponding to 9 point i.e. IBQ.
In this equation supply voltage V oc and R8 both are of
fixed value. Therefore the base current 18 also remains cOnstant
Therefore the name or tbis biasing circuit is ''fixed bias
circuit".
Step 2 :
Ex~ression _
for ICQ or Ic :
The fixed bias circuit is designed to operate in the active
.
Hence the collector current is given by the fol1owing
expression :,
~ = 13c~c Is+ lcro
...(3)
But as, Icro << 13c~c 18 It can be neglected to get,
ICQ = 13c~c IBQ
regiop.
05. Dec. 05. Dec. 06. Dec. 08
Ana.:
Tbe simplest biasing circuit used to bias a BIT is ca11ed as
the fixed bias circuit which is as shown j.n Fig. 4.7. In this circuit ,
only ooe power supply (Vcc) has been used to supply power to
coUecror as well as base. R8 is the single base biasing resistor,
heoce this circuit is also called as single base resistor biasing.
Step_3 :
Expression for V CI!Q or V CE :
"" shown in Fig. 4.9. Here
Considering the collector circuit
the base resistance is assumed to be open circuited.
Applying KVL to the collector circuit to write :
Vee-~~- VCEQ =
VCEQ
=
0
Vee-~~
lea
···········r+
+
Vee
+
... (4)
......... .!..
+
-=-Vee
()'-ZI7)
ArWyele:
Step 1 :
Espn:lldoD for bale eurrent lao or •• :
Cooatdering tbe bale circuit shown in Fig. 4.8. Here
.t..a:.............. .
........
Uector resistaDCC Rc is assumed to be open
~y ~ co
. .
circuilt.d. ApplyiDg the Kirchhoff'• voltage Jaw~ the base CJrcuJt
IOJet :
Voc - 18 R8 - V BE
1:
··.........t
Ji"'&. 4•7 : A ftsed bias circuit for n-p-n transiBtor
···.v
=
...(1)
0
•.u l l l l l l l l l '·
(F-290) Fig. 4.9:
Collec:tor clreuit or collector loop·
0.13 Give reuon: Fixed blaa circuit for BJT amplifier
ylelda loweat etablltty of the de operating_point.
IMN•r:ti
Electronic Devices & Circuita-l (MU)
An&. : As temperature increases, Icuo increases. So lc will
Ana. :
lc • ~ Ia + (1 + P>lcuo
.
In the fixed bias cqcuit , 18 is constant. So lc will keep
vacying with change in temperature. The fixed bias c~uit cannot
automatically keep 1c constant and stabilize the Q pomt. Thus no
stabilization is provided by the fixed bias circuit.
. susthecban.ge in TAC due to change in the reverse
S gtve.
nt lcso· As Icso changes by ll Jrno, the base
saturaboln curreWt
'll change by ll Ia and the collector current lc
current a
changes by ll lc
.
the following for ·the fixed blae
configuration of Fig. 4.10:
(a)
I~ and lea
(b)
Vceo
V 8 11k1Vc
(d)
Vee-
For a CE configuration,
~ dc IB + lcro ~de Ia + ( 1 + ~&) lcao
.IC
1-'
Therefore change in lc is given by,
lllc = ~de Ilia+ (1 + f:\~ ll1cso
Dividing both the sides by lllc to get,
~
=
'
02
--.....---t· (---- AC output
..
~de= 50 ·
1-~de[~
. fliCao
But, S
. '
=
. 1 == f:\dc
:. lllc
(F-291) Fig. 4.10
:~\constantV.. ondP.,
n.csW>•ll: :
Q . 14 Determine
(c)
. as fiollows ·.
f: tor "S" ts
•.
i~because,
== . (1
[~ + (l + ~~ [ ~J
+~~[~J
1 - ·~de [ Ilia llllc )
==
(1 + f:\de)
lllc
= lllcso
(1+P~
...(1)
Ana.:
Step 1:
But for the fixed bias circuit,
Obtain IJIQ and ICQ :
Vee- VBE
. Va;- VBB 12-0.7
IBQ =
R8
240x Hr
47.08
J.IA
=
-6
~ = fJde X JBQ =50 X 47 X 10.
= 2.35mA
Stepl :
I-p
...Ans.
•••ADS.
Considering the collector circuit of Fig. 4.10 and applying
the Kirchhoff's voltage law to it •
·
=
VCEQ-ICQRc
...(1)
Substituting the values,
v
CEQ
Step 3 :
=
=
3
3
12-(2.35x10- x 2.2 x l0)
.
.
6.83 Volts.
.Ans.
..
VB and vC are the voltages measured at base and collector
with respect to ground.
...(2)
...Ans.
o.rtve the axp,....lon for .tbe atablllty factor "S"
of • fixed biM circuit Comment on the reaull
()pc 0?. Dec 08
' · " 111111111 '>
s
= (1 +~de)
...(2)
=
Substituting pde 49 in Equation (7), the value of S =50 .
i.e. collector current change is 50 times as large as change in the
reverse sa~tion current Ieoo- Fixed bias circuit thus gives a very
poor stability of the Q point. It is the worst configuration as far as
the stability of Q point is concerned.. ·
S' of
a fixed blaa circuit. Also derive the relation
Q. 16 Derive the expression for the stability factor
between S and S' for the same.
Dec. 02. Dec. 08
.. . .
Ana. :
S' = ·
.
= VaE- VCI!
Substituting the values ,
Vsc = 0.7 - 6.83 =- 6.13 Volts.
. Vsc
t: :t '. \I
.
The stability factor S' as,
= V8E =0.7 Volts
= vCl! = 6.83 Volts.
~VK :
a. 15
hi this equation Vee• VBE and R8 all are fixed Therefore I a
. cannot change. :. MD= 0. Substituting this in Equation (1) to get, ..
Obtain V• 8Dd Vc :
.,.. y 8
and vc
.
Comment on the expression for S :
Obtain V CEQ:
Va;
= . RB
a~c
av
BB constant leo and pde·
For a common emitter configuration,
"·
lc = Pde Ia + (1 + Pde~
...(1)
Substituting IB in terms of VBB into Equation (I). For this,
referring Fig. 4.11 and applying KVL to get,
Vee = 18 R8 + VBB
.,.(2)
Iro.
•,
Electronic Devfoee & Circuha·l (MU)
...(3)
Step I :
Oba.tn the value of Rc :
Considering only the collector circuit of Fig. 4.12 and
apply KVL to it to get,
o
· 'C
+
-
Vcx;-Voo
lCQ
-
...(1)
Substiblting the values we get,
10-5
Rc = 5x 1~r 3
Voc:-=-
=
1000 .Q or 1 kn
•••ADs.
Vcc=10V
<F-m) Fig. "-11 : Bue loop
l
t
lco=5mA
Substiwting Equation (3) into Equation {l) to get,
Ic = ~deL-CC~ VBBJ
len and lcao are one and the same.
+ (l +
~ciJ lao
~de Vcc -~de Vaa + (1 +~de)laoR8
... (4)
Differentiate this expression with respect to V88 to get,
:. lcRs =
a~c
Rsav=
BE
:. Rg S'
S'
=
=
o-~de+o
<F·m> Fig. 4.12
-~de
Step 2 :
-~de
...(5)
Ra
Q. 17 Derive the exprualon for the •!!~~
Obtain the value of Ra :
Considering only the base circuit of Fig. 4.12 and applying
KVL to it to get,
. Vcc- Is Rs - Vaa = 0
..
for a fixed bias circuit
Ana.:
But
The stabilitY factor S" is
..
Vex; - V,8
Ia
5 mA -33 33 J.LA
Is = .!m_
~de- 150 .
Rs
=
Ra =
10-0.7
33.33 xlO- 6 - 279 kn
...(2)
...(3)
•••Am.
Selection of~:
The transistor to be used for this circuit should have the
following specifications :
. Step3:
For a common emitter configuration.
= ~de Is + (1 + ~~ fcao = ~de Is + ~de lao+ lao
Differentiate both sides partially with respect to ~de to get,
lc
a~c
apde = Is + Icao + 0
Neglecting fcao to get,
a1c
S'' =
1c
... (1)
a pde =18 = Pc~c
1bia iJ tbe required expression.
a. 11
DNign a fixed circuit ualng a alllcon n-p-n
~ which hU p•• 150. The do bluing
point Ia at Vca • 5 V and lc • 5 mA. S&Jpply voltage
la10Volt8.
Pc~c · 150,
lal • SmA
I. 1' 'J
11 111111 1 11 •
~de
2.
IC (max)
3.
VCE(max)
4.
Po (max)
.
=
= 2 XlCQ =2 x5 =10 mA
= 2 XVCEQ= 2 X 5 =10 Volts
=
150 atiC 5 mA
= 2 XV03 (maxi X1C (mu)
3
= 2 x lO x lO x 10- =200mW
0.19 For the fixed-blued configuration
determine the following :
,.
1.
lao, lea
2.
Yceo
3.
4.
Ani.:
GIWD:
1.
v..
vrJC
given,
llllltl
Electronic Devloea & Circuita-l (MU)
--------~-----+Voo
lc
R8 a 240k0
Rc=2.2k0
Voo•+12V
'·........ Is
c1 .. c2 =10k0
<F-m>Fig. 4.14 : ~odifted fixed bias circuit
(F-4139) Fig. 4.13
Ana. :
At Q point • assuming that the ac input applied to the circuit
is zero and the ac output produced is also zero. For DC analysis
therefore assume that the capacitors cl' and c2 are open circuited
aDd_hence do not exist in the circuit at all.
Step 1 : - Obtain leQ 8Dd ~ :
Vee- Vas
12-0.7
' RB
= 240 X 103 47.08JJA
lsQ =
~ = Pc~c x IBQ = 75 x 47 x 10Step 2 :
6
=3.525 mA
3.
••.ADs.
•••Ans.
Obtain VCEQ :
.
Considering the collector circuit of Fig. 4.13. Applying the
Kirchhoff's voltage law to it to get,
Vee
Stabilization of Q point:
current (lc) tends to increase due to either
If the collector
1.
'
rise in temperature or change in Pc~c due to replacement of
tranSistor then the emitter current IE also will increase.
2.
Due to increase in IE, the voltage drop across Re i.e. VI!
=
v<l!Q +~Rc
...(1)
will increase.
But VB is constant Therefore V BE will decrease. This will
reduce the value of IB and therefore the increased collector
current will be reduced towards its desired value. Thus tbil
stabilization of Q point takes place.
Q. 21 Dertve the expression for the stability
the modified fixed bias circuit.
Ana.: As,
(l+P~
Substituting the values,
Va:Q = 12- (3.525 X 10· Step3:
3
X
2.2 X 10 3 ) =4.245 Volts. ••.Ans.
/
Obtain V 11 8Dd Vc :
VB and VC Me the VOltages measured at base and COllector
with respect to ground.
:. VB= VBE =0.7Volts .
Obtain Vac:
s
and
Vsc = Vae- VCE
1-Pc~c[AIB'AicJ
=
and obtain the value of
MJMc to get the expression for S.
Me:
To obtain tbe value of AI.~
l.
Considering the base circuit of Fig. 4.15 and applying KVL
to get:
.
Vc= Vrn=4.245Volts.
...(2)
= Is Rs + VsE + <lc +Is) R
8
Substituting the values to get,
VBC = 0.7 - 4.245 =- 3.545 Volts.
••.Ans.
..
Is
..
Is =
Q. 20 Dlecu11 modified fixed bias circuit used for BJT.
Dec. 02. Ma 04. Mn 05. Dec. 06
Ana.:
The modified fixed bias circuit is as shown in Fig. 4.14. A
resistance Re bas been added ~m em\,tter to the ground terminal
in the fixed bias circuit. The remaining circuit is same as the fixed
bias circuit . The emitter resistor improves the bias point stability
as below.
=
Vee-Yae-lcRE
<Rs +Rs)
Vee
<Rs+Rs)
...(1)
VBE
<Rs + Rs)
+Vee
Re
•
......Is
+
Vee
<F-302> Fig. 4.1!: Base circuit
~I
ifMIINIIIIIJi
IcRe
<Rs+IY
,
(
Electronic Devices & Cfrcults-1 (MU)
2.
4-35
Rs fl
But V00 Van• Rli
differentiation of first '
'
de • are
-Ra
= <Ra + ~
-Ra
ale
·· aIC
~
=
.. Ale
(RB +
...(2)
Rs)
Substitute this in equation of stabili'ty ~
lOf
(l+ ~.0
(l+ 13
fi
.
.
Xed btas CLICWt
)
H<o[~~· t+[~\J
s-
wm. be
Q, 23 Draw Collector
to B8H Blu Clrouh uNCI for BJT.
Ane.:
to get,
-
constant. Hence
two tenns Wtth res~t to IC
zero.
The collector to base bias circuit is as shown in Fig. 4.17.
The base resistance R8 is connected to the collector and not to the
supply voltage V cc· Actually R8 is connected between the collector
and base terminals of the transistor. The current flowing through
He is the sum of Ic and 18 as shown in Fig. 4.17
. .(3)
Comment:
The denominator of Equation (3) will al~ays be greater
than ~· Henee S will be less than (l + ~c~c>· ThliS addition of the
.emitter resistance Rt; has improved tbe stability.
DetennJne Rc. R.., R8 , VCE and V8 ,
Q, 22
<F-304) Fig. 4.17 : Collector to base bias clrcu.lt
Ans.:
Given:
Q. 24 Explain Q point a~blllzatlon In collector
Va;=l2V, fc=2mA, Vc=7.6V,
VE=2.4V, ~=80
Step 1:
IC=
Find
Ana.:
fa, IE:
The factors that affect the stability of Q point_are change in
or ICo due tO change in temperature or. due to piece to piece
variation in characteristics.
But ic = 13c~c Io + ICoo
Therefore due to changes in ~de or Iceo. the collector
current chan~es. Assuming that ~de and ICoo increase then the
sequence of events takes place as follows :
~IB
IC
13de
w-3
2x
= ff = 80 =25 f.AA
I£ = ( l + ~ ) 18 = ( 1 + 80 ) x 25 x lQ-6 = 2.02 mA
.. Is
F'md'~, Rc, ~. V CE and V 8 :
Stepl:
Rt;
=
VE
IE
to base
bias circuit .
=
2.4
2.02 X 10-3
=1.18 k.Q
Vcg = Vc-Va=7.6-2.4 =5.2V
...Aos.
...Ans.
12V
..-....-...-ll2mA
{F-306)
Thus the value of IC is maintained constant irrespective of
changes ~n ~de or Iceo. to stabilize the Q_point.
(F-1904) Fig. 4.16
Va;- Vc _12-7.6 =Z.2 k0
IC - 2X 10- 3
Ve +Yse =2.4+0.7.=3.1 V
.. Ra
I;
=
a '. II
Va; - Vs
Ia
= 12 - 3. ~ = 3S6Jal
s Ill II II 1111 '•
25 X 10
Q. 25 Calculate D.C. collector current lc and voltage Vee
...Aos.
...Aos.
...Ans.
for the circuit shown In Fig. 4.18(a)
'Khflil
Electronic Devices & Circuits-1 (MU)
lido= 120
Vcea=SV
Ico=SmA
(F-308) Fig. 4.19
<F-4140) Fig. 4.18(a)
Ana.:
Ana. :
p = 75, R8 = 500 0, Rc; = 2.4 W,
Given :
Rs = 600 W, Vex= 18 V
1. lc 2. VCE
To lind Ia :
To design the collector
to calculate the values of Rs and Rc
·
calculate the value of Rc :
V
Stepl:
To lind :
Step 1 :
Applying KVL to base circuit (Fig. 4.1.8(b)) to get.
Rc
=
. . Vex- Is [(1 + (3) Rc; + Rs + (1 + tl) RsJ .- VsB 0
. :. Is
...(1)
CEQ
~+Is)
S _5 X 10- 3 =4 1.66 f.LA
=
12-5
Rc; = (5 X 10-J + 41.66 X 10 II)
...(2)
=1.39W
...ADs.
Step 2 :
Obtain the value o~ Ra :
Considering the base circuit we get,
= R&+(l +J3)(Rc;+~
18-0.7
=! 600 k + (1 + 75) (24 k + 500)
=
Vee.-
Pc~c - 120
Substitute this value in Equation (l) to get,
. · 'Is
Yex~(1 + (3) Is Rc;-ls Rs- YsE-:-(1 + J3) lsRs = 0
:. Is
=
The value of 18 is unknown ·
V~- <Ic+·ls) Rc-Rs Is- VBE-ac+ls) Rs=O
:.
to base bias circuit means we have
Vex-~ +ls)Rc-ls Rs- VBE =0
OR
21.08 J.LA
V OlQ - 18 R8
.. Rs =
+18V
..
•
Q, 27
Rs
-
V 88
=0
VCEQ- VBE
...(3)
Is
w-6 =103 .2 w
5-0.1
= 41.66x
.Ani.
..
Derive the expreulon for the atablllty factor "S"
of a collector to baae blaa circuit and comment on
the reeult.
Dec 02 Dec 08
Ana.:
As,
And substituting the value of ~ in this equation for the
(F-4141) Fig. 4.18(b)
collector to base bias· circuit to obtain the final expression for S.
To obtain the value of Ala/ Ale:
To lind lc:
Stepl:
Ic
=
=
-6·
f3Is=75x21.08xl0
3
1.581 X 10- = 1.581 mA
•••Ans.
=
y CB = 13.35 Volts.
Vee= Rc(lc+ls>+lsRa+VBE
_
.
'
=
=
2.
~
26 Design 8 collector to bue blu circuit for the
Q.
VCEQ_ 5 ' 1CQ 5 mA, Vee 12 V and Pc.o 120.
Refer Fig. 4.:19. ·
v
For the collector to base bias circuit,
:.
Yes = Vcc-<Ic +lsHRc +Rs}
IS_ ((1.581 X 10-3 + 21.08 X 10~) (2.4 k + 500)
..
l.
To l'lnd Va:
Step 3·:
...(1)
=
3.
Vex
= lc Rc +Is <Ra + Rc> + V BE
O -
:. -a lc Rc =
r.nsv - snluiro u s
...(2)
To find the stability factor S we take into account the
change in Ic due to change in lao. the other two
parameters, VBE and J3dc are assumed to be constants.
When lcso changes by AJCao. 18 changes by Ms and Ic
changes by Me- However v Ct:. and v BE do not cbange.
Therefore Equation (2) gets modified to,
AlcRc+Ms (RB +Rc)
Ms <Rs + Rc)
~lc Devices & Circuita-l (MU)
•
•
-Rc
AJ.B
. . . Aic ... <Ra + Rc>
4.
...(3)
Substituting this value in Equation (l),
(1+ p~
1+ fl
I -fl..
S •
:. S'
[a;!'".J "I + ~« [ R,~d
...(4)
If you co~ th~ expressions for S of fixed bias and
Q. 29 Derive the expression for stability factor S" Of a
Dec. 02. Dec 08
collector to base bias circuit.
The stability factor S" is defi.ited as follows :
1.
_,....!_baset"~~~ cb~~ts then you will find that the value of s
S" .
coUectorfor
~·"'
o uuc tas lS much less This indicate8 th
point stability is better for the collectort.o base b'
. • at the Q
l3S C.LIXWt.
0 •· 28 Derive the expression for S' ot a collector to base
blaclrcull
2.
Dec. 02 Dec. 08
or S'
=
BE
=
. .. .(2)
...(3)
.
.
[ l}clc-1(;\~)
(cl flc~c']
.
...(1)
...........~-~-~-~~...........,
But
af3ilc
alc
. . .(4)
flc~c
0 = Rc + 0 + <Rs + Rc>
1m and flc~c constant
As' Ic flc~c Is+ (l + flc~c> leo
...(1)
Assuming leo and VBE to be constants, and differentiate
Equation (3) with respect to Ic to get,
3.
and flc~c constant
BE
I
aflc1c fco and VBE constant
Vee
I .. . ..
1m
ole I ·
av
= A~
= aIc
From Fig. 4.20,
•.
Vee =
Ana. : The stability factor S' is defined as,
S'
=
This is the required expression.
eomment on the result:
1
= S" Therefore Equati~ (4) gets modified
',
_
!
.........·iRe
. to,
C)J
,:·
~_,..........~
Ra+Rc[f3c~c-lc S"
-Rc = ~
.
•+ .
r
-Rcf3~
..
Rs+Rc
-!,,':.!_Vee
·............ + ........
..
Vae -~
'·.:::.................f .........·
..
Base loop
-.,
II
4-37
.(F-309) Fig. 4.20
: Base circuit
considering 'the baSe circuit shown in Fig. 4.20 and apply
KVL to this circuit to get :
.. · Vcc.
(lc +Is) Rc + 18 R8 + VBE
...(2)
The expression for I8 in terms of V813 is obtained as below ·
and substituting it into Equation (1).
...(3)
..
Vcc. = IcRc +Is Rc +Is Rs + Vse
=
1c• = flc~c Is
Vcc. = f:lc~c Is Rc + I8 Rc +Is Rs + Vse
Vcc.-Vae = IsrRs+Rc(1+f}~]
Vee.- Vse
Is = Ra + Rc (1 + IJc~c)
Substituting Equation (4) into Equation (l) to get,
But
lc
~ and
..
= IJc~c[Rs :~(~~~J + (1 + f:lc~c) lcso
lao are one and tbe same.
f:lc~c Vee.
f:lc~o: Vse
+ (1 + f:l~ Icso
lc • Re+Rc(l+f3~-Rs +Rc(1+f3c~c)
Ditf«.eotiate with respect to Vse to get,
aIc
avBI!
I. ••. 'J
.
I;
f:lc~c
o
o- Ra+O + f:l~Rc +
'.11 111 1 1 11 11 ' •
1(;
S" .
=
1(;
flc~c- S"
=
f3c~c +RB +Rc
lc<Rs +Rc)
S"
..
de
Rcfl~
2
P&: <Rs + Rc> + Rc flc~c
lc<Ra +Rc)
z .
flc1c (RB + Rc) + f}clc Rc
lc<Rs +Rc)
"" f3c~c Rs + flc1c Rc +.f3! Rc
;
l(;(RB +Rc)
S" =
f3c~c [RB + Rc (1 + f3c~c)]
S" =
... (5)
Q. 30 Answer the following questions for the given
circuit
1. · What happens to voltage Vc H resistor Ra Ia
open?
2.
What ah6~d happen to Vee H p Increases
due to temperature ?
·
3.
How will Ve be affected when replacing the
collector resistor with one whose
resistance Is at the lower end of the
tolerance range ?
4.
If the translator . collector connection
becomes open, what will happen to VE ?
5.
What might cause Vee to becomjf~C:1f
18V?
e•
Electronic Devices & Circults-1 (MU)
Bias stabilization using volta~ ~~vlder bias circuit :
'~'to'ahali:e.~l£tlloei'Bi,.IUI_re'_oc:P~:
Q
•
.' ·.
the expression for the stability factor s ot
3~· Derive
the VC?Itage divider bias circuit. Comment on the
Dec. 02. Dec. 08
result.
Ans. : To derive the expresSion for s. , ~e same equation of "S"
for the collector to base bias is used which IS,
(F-1389) Fig. 4.21 .
1 + 13~
.
Ana.:
'
s
=
.
...(1) .
1.
Vc = 18 v because if Rs is open then Is= o
1-13dc [.Ms/Aic]
. :. Ic =Oand Vc =Vcc-IcRc= Vee·.
.
Ms
2.
and ~bsrltuting ~ value of Ale for the self bias circuit to
Vrn should decrease.
3.
As Rc decreases Is, 1c and 16 will increase. So VI! will
· obtain the required expression for S.
increase.
To obtain
value of Ala I 41c :
L -0 th
thr
.
·
Vee- Vae
4.
The Thevenin's equivalent circuit is shown in Fig. 4.23.
. "C e current ough ~ wtl,l be II! = <Rc + Rs + R.J
·
Applying KVL to the base circuit of Fig. 4.23, ·
This is much lower than the originai 16 , :. VI! will reduce
Vm
=
Is
Rs
+
VBE + (lc +Is) Rs
...
(2)
5.
If lc =0 ~en Vce = 18 V. So if the transistor turns off and
Considering
V
BE to be independent of Ic. we can
then.VCB = 18 V. ._
differentiate Equation (2) with respect to Ic to obtain,
Q,_31 Discuss voltage divider bias or self Bias used for
aIs .
iHs
BJT.
0 = Rsalc +O+RE+~alc
the
Dec. 02. May 04. May 05. Dec. 05. Dec. 06. Dec. 08
..
Ana.:
The cj.rcuit diagram of voltage divider bias is as shown in
Fig. 4~22.
.
..
Features of .t he circuit : ·
The resistors R1 and Rz form a potential divider to apply a
fixed voltage Vs to the base. A resistance R., has been connected in
the emitter circuit ·
+Vee
0
a 18
a~c
=
a 18
a~c<Rs+~+~
=
-RE
(RB +R.,)
MD
~
.. Me -
(RB + R.,)
...(3)
'
Substitute this in Equation (1) to obtain,
+Vee
([+Is> 1
••
.....................f+
Vee
_,....~.............tVTH
+
<F·lZ4) Fig. 4 .23 : Thevenin's equivalent circuit for voltage
divider bias circuit
(F·316)'Fig. 4.22 : Voltage divider bias
ca~v - ~ul uiiOIIS
s=
1 + ~de
1
A [
- Pl)c
1 + 13dc
-&__l=
Rs +
RJ
[
RE_l
1 +~de Rs + ~ .
...(4)
~IC
VV>rt'WVV ""' ...,......,,&CJ•t \MU)
_
4-39
For an emitter follower, tbe collector current is given by,
= Pc~c Ig + (1 + p~ Icao
...(2)
From Fig. 4.24 ,
Vm - VBB
lc
-;i3
OertYe the
•=ton
m;•·t•·''''Iii
1be stability factor S' is defined as follows :
S
l
=
t\lc
AV"
85
...(1)
constant JCo and p
For a common emitter circuit
.
de
lc = Pc~clo+(l+Pc~c)~0
the expression for 18 in terms of V
subsbblte it into Equation (2). For this referring the base
me self bias circuit shown in Fig. 4.24
·
and
l!p of
Apply KVL to base loop to get,
18
"
Substituting Equation (3) into Equation (2) to get
Vm-Van_l
lc = Pc~c [ Ra + (l + p~ R;_J + (I + Pc~c) lcao
=
Icso [RB + (1 + Pdc> Rel
1 +Pdc
But~ = 1
~IRe+
(1+jldJ
'\:)~~~BEl~~~ ~ lcao RJ
L~
(21.
(3)
(-4)
Tenn(1)
(5)
J
•.. (-4)
.
Considering the five termS in the above expression . and
obtain their partial differentiation with respect to Pdc·
· ..(3)
Substituting Equation (3) into·Equation (2) to get,
lc ::
:. Ic [RB + (1 + p~ ReJ
=Pc~c (Vn1 - V8n) + ( 1 + fJ~ lcso [R8 + (1 +. p~ RsJ
Dividing both the sides by Pc~c to get.
lc [Ro + (1 +P~ R~
(1+ p~
Pc~c
= <Vm- Vas>+ pdc
.
loRa+ VoE+(l +PjiaRB
Vm - VoE
Rs + (1 + Pc~c Rs)
...(3)
R11 +(1+P~RE
. (F-3l6(a))
Vm = laRs+VoE+IERE
=
=
....(2)
leo and lcao are one and the same.
Obtaining
18
for the atablllty factor S' for
blaa circuit.
the voltage
--.:
... (5)
The .terms·(2), (3) and (4).are constants so their derivative
Will be.O.
Pc~c[Ro :~: ~:~ Rj + (1 + Pc~c> lcpo
... . ....·-.
_.. Base·.\
~
loop
.............··
(F-325) Fig. 4.24:
= . '""B
D
j
• uit
Base loop of self bias care
~de Vm
Pc~c VBE
+ (1 + Pc~c> Icao .
+ (l+P~ Re Rs+(l~~.Rs
v to
Differentiating both
•
• _.,...h"IIY
Sldes i""'~
wtth respect to
...(5)
BE
TermS
Considering tenn 5 of Equation (4) which is. Pc~c leBo Rn
Differentiating with respect to Pdc to get, 1cso Rs
Since Icuo and R8 both are small, we can c;<tuale lcoo-Rn to
S' =
:. lcaoRn = 0
...(6)
Hence the differentiation of Equation (4) is given by.
'
Ana. : The llability factor S" is :
S"
c
L :t •. \1
aIc
a pck:
.
...(1)
coostaDt v
·, 11 I II I l II II '•
S" [
pdc 0 + Pdc) Rn + Pdc Rs] lc
.
+"'RT
pciQ
~-'de
U~c~c Rf! - (1 + P~ Ra- Rs] = 0
Electronic Devicea & Clrcult8·1 (MU)
:. S"
- lc [flo~e R8 - (l +Po~e> Re- R~
Po~e (I +Po~e> Re +~ole Ro
- Po~e Re +(l +p~ Rs +Ro
• Po~e (l +flo~c) Re + Po~e Ro
=
VTH ,._. +V"t
..... ~ .. 12
R, +
l!i
·~12Volla
Re • 88kh23.5 k.. 17Ji k
Dividing numerator and denominator by Re to get,
- Po~e +(1 + Po~e> +(R8 IRs)
S" = Po~e (l + Po~e> +Po~e <Ra IRs) Ic
1 +<RaiRs>
= Po~e [l + Po~e +<Ra I Rs>1 IC
(F-361)
Multiplying Nand D by (l + p~ to get
. (1 + P.J [l + <Ro IRs)]
S" = (1 + p~ Po~e [l +Po~e + <Ra IRs)] IC ...(7)
But S =
=
pis= 180 x 12.68 xto-6 =2.283 mA
...Aas,
=
IE :: (1 + fl) Ia = 181 X 1Z.68 X 10-6 2.2951 mA
(l + P.J [l + (R8 IRs)]
1 + flo~e +<Ro I R_s)
Applying KVL to the collector loop to write
Hence Equation (6) can be written as,
,
Sic
S
=
Calculate Ic and VCE :
Step 4 :
.. IC
Flg. 4•l5(c): Tbevenln's equivalent drcuft
6-
IC Rc - Vcs.-
:. Yes
(l+P~Po~c
Q. 35 An ampllfter circuit Is shown In Fig. 4.25(a).
Determine the co-ordinates of the operatl~t
Q and the thermal stability factc:w S.co·
ltBtD
Step 5 :
=
=
=
=
IE Rs + 6 0
12-ICRc-IERe .
12 _ (2.283 X 2.5) - (2.2951
X
0.94)
4.135 Volts
Calculate S1co :
For a voltage diVider: bias circuit S100 is given by,
.if.
Srco
1 + (Raf Rp)
= d leo= (1 + fl) (1 + fl) + (Rsf Rs)
=
1 + (17.510.94)
(1+180).(1+180)+(17.5/0.94) - 17.79
~·
Q. 35 Design voltage divider biased circuit~
lea= 5 mA, Yceo =5 V and P=100.
lrBIII
An~. :
(a) Glveo clrc:uit
(F·360)
(b) DC equlvaient clrc:uit
Fig. 4.25
Ana.:
Step 1 :
Draw the DC equivalent clrc:uit :
The DC equivalent circuit is as shown in Fig. 4.25(b). This
is obtained by replacing all the capacitors in the given circuit by
opeo circuit
Step 2:
Draw the Theveoin's equivalent cln:uit:
The Tbevenin's equivalent circuit is as shown in
Fig. 4 .25(c).
Given:
VCEQ =5 V, lcQ=5 mA, P= 100
Step 1 :
Calculate v E' ~a; rE :
Assuming Vcc
=
16 V
VB = 0.1 Vcc=0.1 X 16= 1.6 V
lc
p
Ia =
IE
=
5 X 10- 3
100
=50~
(1 + P> Ia = 101 X 50 X 10- 6 = 5.05 mA
Step 3 :
Obtala 18 :
Applying KVL to the base loop ,
Vnt-ls Ra- Yse-l£Re +6 =0
:. - 2.92 -Is Ra -0.7 -(I+ 1})18 Re+ 6 = 0
:. 2.38- Is £Ra + (1 + fl) Re1 = 0
• 2.38
:. ls = Ra + 0 + P> Re
=
Prom tbe data abeet PcrnJic:al). 180 and Re 940 nor 0.94' k.
:. ... •
17.5 k: +
(~i~) X 0.94 k. = 12·68 J.l.A
(B-2653) Fig. 4.26(a)
I' .I ,
V '. II I II I I
II
II ·'
-
e~eetronlo Oevfoee & Circuita-l (MU)
SteP l :
=
cakalate Rt and Rc :
J)
VB
•
18
•'II
•
J.6V
5.0!'1 mA
2.44 Volts
Fig. 4.27(a) shows the Thevenin's equivalent circuit.
=316.83 Q
+12V
Vee- Vc
Rc •
lc
But Vee •
VB+ VC1! = 1.6 + 5 = 6.6 V
16-6.6
5 mA
1.88 k.Q
:. Rc =
=
...Ans.
(F-47l0) Fig. 4.27(a)
18-
..
~· =
Vm- vllll
R8 + (1 + f})R6
2.44-0.7
9.56 k + (101 X 1 k)
=15·74 J.LA
fl 18 =100 X 15.74 X 10-<i
= 1.57 mA
IE = (1 + f}) 18 = 10~ X 15.74 X 10-6
Step 3:
VB =
VE +VB!! =·1.6 + 0.7
=2.3 v
:. Assuming current through R 1 is I 1 and through~ is 12•
11=
:.
:.
~
~
=
=
= I ;.
It
2.3
450 X 10-ii = 5.lll k:Q
16-2.3
= 500x 10-6
=
=
=
VB
= 1.59mA
Step 3 : VCI!Q and operating point :
V CEQ
1018 10 X 50 J.LA = 500 J.LA
Il-18 500-50=450 J.LA
Vee- Vs
Rl =
=
...ADs.
V.ee- IC Rc·- IE RE
12- (1.5? X 2.2)- (1.59 X 1) =6.96 V
:. Operating point
••.Am:
...ADs.
=
(VCEQ• ~
= (6.96V, l.57mA)
Part D : DC load Hoe :
=27.4 W
••.Ans.
Q. 36 For the circuit shown In Fig. 4.27, find operating
point and plot DC load line.
·
i!i4W
The DC load line intersects the X and Y axes at points
A
and 8 respectively. 1'bC:ir co-ordinates are as foUo~s :
A = (V00 0)=(12V,OmA)
8 = (O, Icmax) =(0, VcrJ Rc + Rs) =(0, 3.15 mA)
The DC load line is as plotted in Fig. 4.27(b).
(F-4716) Fig. 4.27
Ani.:
Part I : 0perat1ng point
Step 1 : Draw 'lbevenln's equivalent circuit :
Ra
=
=
RJII ~=47 k ll12k
12
Vn~ ., ~XVa;=4f+i2 X12
Rt+~
t: a :. 'J •• ulultll 11 s
0. 37 .Which bluing will you use If BJT 18 to be used aa
·• conatant currant source? Juatlfy.
9.56~
R.
(F-mt> Fig. 4.27(b): DC load line ·
rvl<l 0-1. r1l<1
05. Dec . 06. Dec 07 Dec 10
Electronic Devlcel & Circuita-l MU
As V8 and Ra
Ana.:
Is cons~t. oflc th•
Irrespective
ev
constant current source.
.
Wh 18 potential divider btaa commonly uaed for
38
Q.
lh/BJT 1
I•J§i•b
The collector current of the self bias circuit remains
constant irrespective of the value of Rc· Considering the self bias
circoit of' Pig. 4.28 and I » 18 , then expression for the base
voltage V8 is.
An•.:
. . ·
r, 11
The advantages of voltage divider bias crrcwt are as .o .ows :
1.
It bas the smallest value of S .among~~ ~ bi:mng circuits.
This shows that the bias pomt stability IS highest for the
... (1)
Tbe value of V8 is constant because R1• R~ and Vee are
coostant.
The emitter voltage with respect to ground is given by,
Vs = Va - VBii
=
Ya - 0.7
both are constants, the emitter current 18 also
= Constant So collector current .IS constant
18
alue of Rc . Thus the self bias circuit acts as a
2.
self bias circuit.
It is possible to avoid the loss of signRal Thig~ bdoeyconnecting
an emitter bypass capacitor across e·
s
s not have
any adverse effect on the other advantages of self bias
3.
R introduces a negative feedback. This will make the self
...(2)
r------voc
circuit.
8
bias circuit more stable. So all the other advantages of
negative feedback get attached to this circuit _
Voltage divider bias circuit is therefore the most widely
used biasing circuit.
Q. 39 State disadvantages
of voltage divider blaa
circuit.
Ans.:
<F·332) Fig. 4.28: Self bias circuit
As Va and 0.7 both are constants, the emitter voltage al~o is
COIISbmt.
Tbe emitter current is given by,
VE
1E = Ra
·
=Constant
...(3)
The disadvantages of voltage divider bias circuit are as
follows,
.
1.
The ratio R8 I R8 needs to be low for better Q-point
stabilization. So R8 should be small and RE high. But this
reduces the input resistance.
2.
Reduction in gain due to negative feedback if R is
onbypassed. .
B
0. 40 Compare various types of biasing techniques used for BJT.
Ans.:
Sr.
Dec. 02. Ma
No.
1.
2.
resistance
Negative
Not used
Included
Included
Poor
Moderate
Good
feedback
3.
4.
s.
Configuration
(F-335)
(f·334)
Vee
Re
t.
I . 'J
, U Ill I IIIII
(F-336)
08. Ma 09
..
~
' ,..
I'
Oevloee & Circuita-l (MU)
:
. 1be collector, to b,Ue bias c~n:.uit and the volta e divider
ciJt111t .., used to mtmmu:e the vanatton In '"'· Q . g
.. --..~ b
· .
•uo
pomt co11ector
cwneot ~ (a.-.u YVanattoos in leo V and A The . ,
.--a.~ o( fcodblct
t'do·
SC CJI'CUJls
.re ~
amplifiers. ' Bll
-~to (tbe' ne)gati':dedfeedback present in these circuits the
~ft~Pti•_...... gam proVt
to the AC signals is reduced
~~- lf. we_annat tolerate the loss of signal due to bias
$11bi!i1.11b0D cli'CWts then the compensation techniques
sed .
<rder to minimize tbe instability of the operating po'•nt arev u ftem
~to..:..:
• and
.
. . ery o n
bod!__..u~
oompen~tt.oo techniques are used to provide
.,antDUtn bias and tbennal stabllJZation.
TypM of compensation techniques :
1. Diode Compensation for VI!IIE :
1be.vob8e divider bias clt:cuit witb diode compensation is
as sbown m Pig. 4 .29. Tbe additional power supply v
is
0
()i«cted in order to forward bias the diode D. This diode ~ of
Slll)e material and type as the transistor. The voltage VP across the
diode bas tbe same temperature coefficient(- 2.5 mV?C) as tbat of
tbe base to enlitter voltage V BE·
C....E l!t'-clll
The materiaJ uiCd for the diode is same as .that for the
transistor and bas same temperature coefficient. Therefore the .
change in voltage ocross the diode (Vp) will be exactly equal to
change In V88 due to variation in temperature. Hence the first two
terms in Equation (4) cancel each other. Thus the change in VB£
due to temperature is compensated by an equal but opposi~ c~~e
in VP and the collector current becomes insensitive to variatlon m
VDB' Thus we minimize the Q point instability due to variations in
VDB by using the diode compensation technique.
2. Diode Compen•atlon for leo :
For tbe germanium transistors, changes in leo due to
variations in temperature are more prominent tban changes in V BE
due to temperature. The diode compensation circuit shown in
Fig. 4.30 offers tbe stabilization against variation in leoCompensation
The diode and the transistor are of same type and material
Therefore tbe reverse saturation current of the diode i.e. lo will
increase witb temperature at tbe same rate as tbat of current leo of
tbe transistor.
From Fig. 4.30,
·.
Vee- VBE Vee
I =
R
- R = Constant.
I
Prml Fig. 4.29 , the KVL for the bS:SC circuit gives :
Vm = Is Ra + VaE + (Ia + Ic> RE- VF
...(1)
But, lc = Pc1c Ia + (1 + P«> lcso
...(2)
:. V111 = Ia<Ra:t-RJ+VaE+IcRE-VF
...(3)
Prml Equati~ (2).
lc
= Pc~c
Ia
(1 + Pdc) Icno
The base current 18
I
=I -JO. Substituting
this value of 18
in the following·equation :
lc = flc1c I a + (1 + flc~c) leo
=
.. lc
flc~c (1- Io) + (1 + P~~o> leo
ll<t: I - llc1c lo + (1 + llcJcllco
=
.
Pc~c
L SoEqual~cancel
opposite terms.
other
they
... (5)
each
If the saturation currenf of tbe diode (lo) is equal to the
leakage current leo of tbe transistor, then ~ last two terms in
Equation (5) will get cancelled.
:. lc =
fl~~o I
... [Since Pc~c lo = (1 + fl«> leo 1
As I = Constant. Ic will also remain · constant and
compensation is successfully provided
From tbe last two terms of Equation (5), if Pc1c >> 1 and if
JO of D and leo of the transistor change equally over the desired
temperature range then Ic will remain constant. Thus compensation
is provided.
<F·337) Fig. 4.29 : Diode c:ompeDS8tion for Vatt
Sobltitutiog this value in Equation (3) to get.
.!c.
V
'111• ~-
:. v
llJ.
at_ + R.,) _
vII! - vp +
(1 +
P«> (Ra + Re)
Pc1c
~
V
+ Ic Re - V"
BB
Ra + RE (1 + ~«> 1 _ <Rs + Re} (1 + P«> 1cso
p
c
pdc
L2._
...
•• IJ I II I I 1111 ' •
(4)
1beie ~en:na are equal and
oppo~ite. So they cancel each
other-
I' · 1
L . +
"CBU
Germanium
tranlllstor
CF-338> Fig. 4.30 : Diode compensation for leo
Elecbonlc Devices & Circuita-l (MU)
Q. 42 Wrtt. ahort
note on : Thenn111 runaway.
Ana.:
Tbe col.lector region of a transistor dissipates heat. As we
i~ the amount of power dissipated in transistor then junction
lelllperature increases. The maximum power that a transistor can
dissipatl'l without getting damaged depends on the maximum
temperature that a collector • base junction can withstand.
Tbe rise in the coUector - base junction takes place due to
two rea.soos :
I.
Due to increase in the ambient (surrounding)
temperature and
2.
Due to the internal heating.
Out of them the internal beating process is cumulative as
explained below :
1.
An increase in coUector current 1e increases the
power dissipated in the collector-base junction of
the transistor.
Po = Ves XIe
2.
This will increase the temperature of C-B junetion.
3.
As the ~sistor has a negative temperature
coefficient of resistivity, increased junction
teJ:ilperature reduces its internal resistance.
4.
The rednced resistance wiU increase the coUector
cmrent further.
This becomes a cumulative process which will fin~y ,
damage tbe transistor due to excessive internal heatiDg. This
pocess is known as "Thermal Runaway'~.
·
1c Increases -............
/
. ·
Resistance of
,
·The power ·devel~ at the collector j~ction in the
absence of ac input signal, IS gtven by,
• Pc = V csle =V CE le
·
...(2)
2
Substituting Equation (1) in Equation ( ) to get,
Powerdl~patk.>n
.
The condition to avoid
(Equation (3)) can be rewritten as:
dPc die
1
ole xorj < 9
ole X;rrj
.
oPe
a~e
Considering Fig. 4.32 and ll$Sumiog that the transistor is in
the active region. By applying KVL around the col1ector loop, to
'. II I II II It II !,
~~ is negative.
.< .o
...(5)
Substituting Equation (3) into Equation (5) to get,
:. Vee- ile eRe+ Rn) < 0
i.e.
lc >.
Vee
2 <Rc + Rs)
...(6)
But from Equation (1) the collector current is expressed as:
Vee-VCE
le = .<Rc + Rs)
.:.(7)
Substituting !IDs in Equation (6) to get,
Vee-Yes
Vee
~+Rs) > 2<Rc+Rs)
..
<Vee-Vc;F) >
Vee
T
: . V CE < Vcc 12
•••Proved.
H V?! is less than Veel~ then the operating point will be in
=
:t ·, 'J
9 will always be positive. .
Hence to avoid thermal runaway.
Ans.:
t;
a~e
or.and
There(ore this equation will .always be satisfied if
common emhter amplifier, the condhlon for
• Vee
thermal 8tabllhy Ia VcE < T·
:. lc ;: <Rc + RE)
runaway
< 1
.
Q. 43 Prove that for a voltage divider bias clrcuh for
=
thermal
J
process
Yes
Vee- Ic CRc; +Rs)-18 Rn
Neglecting the last term,
VCE
Vee- Ic CRc.+Rs)
Vee - Yes
X9
In this expression
Increases
To al'oid the .t hermal runaway ,
(1) Never exceed the collector current beyond a certain
. maximum value specified ·by the manufacturer. (2) Neve( exceed
the internal power dissipation above the maximum permissible
value. (3) Use beat sink: to radiate the heat into atmosphere.
set.
the
dPc die
.
\..
This wtlllncrease the
~reof C-Bjunctlon
<F-342) Fig. 4.31 : Thermal runaway
Pc
...(3)
..
.
2
=
Veclc -Ic<Rc+Rs)
Differentiating this equation with respect to lc•
·
)
the device decreases
<F·l43)Fig. 4.32 : Voltage divider bias circuit
...(l)
the safe ~gt.on, where thermal runaway will not take place. But if
t!'e Q J>(lmt IS located such that VCE > vcc 1 2 then the transistor is
likely to get damaged due to thermal runaway.
Electronic Devices & Circuits-1 (Eiex.-MU)
4-45
Chapter 5 : AC Analysis of BJT Amplifiers
What Ia a linear amplifier ?
Q.1
Ans.: A ~ear amp.lifie.r magnifies the input signal and produces
~ output SJ.gnal which 1§ larger in size as compared to the input
stgn~ and bas sam~ shape as that of the input signal. Amplifier
conSists 9f some active device such as BIT, FET etc.
Define R1, Ro, A~o Av and bandwidth for a voltage
amplifier.
·
Q. 2
Ans.:
1.
Input "resisia~ <Rt> : Input resistance (R;) of an amplifier
~s defined ~ the resistance meas,\lred by looking into the
IDP_Ut termmals ~f an amplifier. The value of input
resistance R; of an Ideal amplifier should be~.
Output resistance (RJ : Output resistllllce of an amplifier
is defined as the resistance measured ~tween the output
terminals looking back into the amplifier with its output ·
terminals open circ~ted and the input voltage source ~bort
~uited, i.e. RL =oo and V s =0. The output resistance of
an ideal amplifier is equal to 0 n.
3.
Current and voltage gains : Current gain A1 is defined as
the rntio of output current of the amplifier· to its input
current
-
... Ax .-
~
~
The overall voltage gain Av of an amplifier is defined as
the rntio of its output voltage to its input voltage.
. Av
..
--
~
v.
I
4.
Hence the voltage gain (Av) of an ideal voltage amplifier is
equal tooo.
Bandwidth (B.W.) : The bandwidth of an amplifi~r is
· defined as the rnnge ·of frequencies over which an amplifier.·
can amplify the input signal satisfactorily.
Operation of the RC coupled CE ampli.fter :
When the ac input signal is absent, the value of de base
purrent of the transistor i~ IBQ which is called as the quiescent point
base current Corresponding to IBQ, a quiesc.ent de collector current
ICQ also flows tbrougb the transistor (~
13dc IBQ) and the
collector emitter voltage is VCEQ' All this happens because we have
biased the transistor in its active region using the biasing
components. When small ac siDusoidal signal is applied a! the_ input
of the amplifier, an alternating base current, starts flow1~g m the
circuit. This base current varies above and below the Q pomt value
of the base current (iBQ) as shown in Fig. 5.2_. Thus ~ ~ si~al is ·
superimposed on the DC current IBQ. Due to these vanations m the
base current, proportional variations take place in the collector ·
current, because 1c j3 Ia· As· Ia increases Ic also increases and
with decrease in Ia, 1c will also decrease as shown in ~g. 5.2. Thus
I and I are in phase but lc is a magnified version of Ia· Ic varies
B
C
•
T
above and below its Q point value IcQ· This varymg 'C passes
through the collector resistOr Rc to produce a varying voltage drop
1c Rc across it. This voltage drop 1c Rc is in phase with the
collector and base currents as shown in Fig. 5.2. .
The collector voltage is given by,
Vc = Va:-lcRc
...(1)
. Therefore. with changes in the voltage drop IcRo the
collector voltage also will vary as shown in Fig. 5.2. However Vc
and Jc Rc will vary in exactly opposite manner with respect to each
other, because as Ic Rc increases Vc has to decrease according to
Equation (1). This collector voltage is then coupled to the load
through the coupling capacitor Cz. It will block the .de part of Yc
and allow only ac part to pass througb as shown in Fig. 5.2. The ac
signal amplitude obtained after Cz. This is the output voltage. Its
. magnitude is much higber than that of the input signal and its shape
is exactly same as that of the input signal. ·Thus the input ac signal
has been successfully amplified
=
=
Explain the operat16n of single stage RC coupled
Q. 3
amplifier.
.
Ans. : A single stage RC coupl~d amplifier using transistor as an
active device is as shown in Fig. 5.1.
.
·
-tVcc
c1 arid c2 are
coupling capacitors
------~----~--~~~=~
(F-~> Fig. 5.1 : Single stage RC coupled cE ampll.fter
.
and C are called as the coupling
2
The capacitors cl •
•
led to the amplifier
capacitors. As the Load resistor RL IS . cou_p
. ailed
RC
.
"t
this amplifier IS c
as
through the couplidg capacl _or, . .
ected in the Common
18
COUple'rl amplifier. The transistor
c:;:n plifier is called CE
Emitter (CE) configuration. Therefore IS am
amplifier.
I!
a •; \1·
S II Ill I I fill •;
I
i :
(F-391) Fig. 5.2
: Waveforms showing the process of
ampllftcation
Electronic Devices & Clrcults-1 (Eiex.-MU) .
As seen from Fig. .5.2. there is u 180° phose shill between
the ~utpu.t. and input or the output is said to be tm "inverted"
VeJ'SI.OO Of IOpUl.
Q. 4
l:xp..ln emitter follower amplifier. Why Ia lte
name emitter follower ?
Ana. : ~ co~mon collector or emitter foll~wer configurotion is
as shown m F1g. 5.3. The resistors R R and R provide de
bia~ing for the transistor. cl and <; are ili~ co~ piing c~:pncitors and
RL Is the external load resistance.
·
(F·398> Fig. 5.5: Common base amplifter
•
c 1 and c2
are me coupling capacitors, and RL is the
external load.
Operation :
•
..
.
.
The input is applied to the errutter wbJie output IS .taken
from the collector. The base is connected to ground (f~r a~ Signals
only) via a large capacitor C which acts as a short ~lfCUJt for ac
signals. Thus the base tenninal is the common t~rmma~ between
input and output. In the positive half cy~le of t~put s1gnal, the
(F-396) Fig. 5.3 : Common collector amplifier ~ircuit
emitter vQltage varies sinusoidally at?ove Jts Q-pomt value. Thus
Wavetonns : ,
when Vbe reduces, Ib and Ic will reduce. So tbe voltage drop across .
The input voltage is applied at the base of the transistor Rc ~ill reduce. ·Hence the collector voltage will increase above its
~~ ~~ to ground and the-output of amplifier is taken from the
Q-point value.
·
Input volta-ge
enutter With respect to ground. As the emitter voltage follows the
Thus· a positive half
vin
base v.oltage, the gain of this amplifier is approximately is equal to.· cycle is obtained at the output
I. A.s shown in .Fig. 5.4, the input and output voltage waveforms
corresponding to the. positive
are m phase With each other. The output voltage amplitude is
half cycle at the input as
exactly equal to that of the input voltage.
shown in Fig. 5.6. Similarly a
negative half cycle is obtained
vm
at the output corresponding to
Input voltage
the negative half cycle at .the
PA~
j ~~~.~~~.:~:~~~:~)~~~:r
i ~••t
input. In this way there is no
phase shift between the input
•and output.
(F-399) Fig. 5.6
6,
, . i~i
:
vm
:
:
~
l
o'@&:
Output voltage
l
(F-m) Y~g.
l~l
List applications of the CB amplifier.
Ans. : The important applications of the CB amplifier are :
1.
As the high frequency amplifier having large bandwidth.
Q. 7
.• t
5.4 : Input output waveforms of an emitter follower
Due to the voltage series negative feedback prese'nt in ~
emitter follower circuit, it possesses all 'the advantages of the
negative feedback. Some of these advantages are very high input
impedance, large bandwidth, low output resistance, low noise, low
distortion. Input impedance of the common collector amplifier is
high and output impedance is low. Input and output signals are in .
·
phase i.e. there is no phase reversal.
As the output (emitter) voltage of CC amplifier is equal to
the input voltage and in phase with input voltage it is said that
emitter follows the base. Hence the name emiiter follower.
2.
For the impedance matching.
·
Q. 8
What do you
by small signal
understand
operation?
Ans: : If.the amplitude of the input ac signal being applied to the
~plifier JS ~mall (few mV), then the amplifier is called as a sma11
Stgnal ~tnplifier, at_~d the Operation of the amplifier is called as
s~all s1gnal operatt~n. As the input signal is small, the transistor
wtll operate ?n th.e linear region of 'its transfer characteristics and
produces a. distort,i.on less output as shown in Fig. 5.7. This is why
the small Signal amplifiers are also called as linear amplifiers.
vo
Q. 5
State applications of the emitter follower:
AM.: The important applications of the emitter follower are :
1.
2.
3.
As buffer amplifier.
For the impedance matching.
As the output stage (Power amplifier).
Q. 6 Explain the operation of common ~·· amplifier .
Ana. : The common base amplifier configuration is as shown in
Fig. 5.5. The resistors R 1, Rz and R1, provide the voltage divider
biasing for the transistor.
(F'-40Q) Fl
e a :; \1 · s 0 IIIII 0 II S
·
· 5.7 : Transfer. characteristics
!!ectronic Devices & Clrcutts-1 (Eiex.-MU)
4-47
Q. 9
Wrtte short notes on • H b
of BJT amplifier.
' y rtd
ft
equivalent circuit
The ac resistance of a diode is given by
26mV
r..,
i
AM. : A transistor can be treated a
in Fig. 5.8(a), and the small signalsha ;;o port n~twork as shown
shown in Fig. 5.8(b).
y nd-1t eqwvalent circuit is
The hybrid-n equivalent circuit consists of
1.
The small signal resistance r
_two components:
r--..:..._--eC +
Where I 0 is the de current flowing through the diode. The
re
=
26mV ·
-I-
.....(3)
·E
Here 15 is the de or Q point emitter current Thus the ac
resistance of the diode in re model is determined by the de value of
I 5 . The diode in Fig. 5.9(1)) i~ replaced by its ac resistance re to get
the final re model for the common base configuration as shown in
Fig. 5.10.
8 + •.!!!......•
E
.....(2)
~-
same equation can be used for the diode shown in the re model in
Fig. 5.9(b). The current 10 is replaced by I2 and r~ is replaced by rt.
;',
A dependent current source ~ Vbe
2.
=
E
(a) Transistor as two port ·
network
.
(b) Bybrid-n eqUivalent
circuit of BJT
<F-1424) Fig. 5.10: Common base re equivalent circuit
(F-1408) Fig. 5.8 . .
Q.11 . Draw and explaln r. model for conimon emitter.
The small signal·resi~tance .rn is defined as,
rn = .
configuration •
.Yc.
I
Ans. ·: The· common emitter configuration is as shown in
b
Fig.
5.ll(a). The input is connected between base and emitter
The alternative expressions for rn are :
terminals and BE junction is forward biased. The output is
~VT
obtained between the collector and emitter and the CB junction is
rn
I
= L_
...(2) · reverse biased. The BE, junction is replaced by · a diode and a
.
BQ "
-cQ
controlled current source appears between the collector and base
.
r,. is called as the diffusion resistance or base-emitter input
reststance. The_value of r, depends on the Q-point parameters. (I~Q terminals as shown in Fig. 5.ll(b): The controlled current source ·
between collector and base
. terminals has a value of I and
and :fw). The output side of the transistor is represented by a
.
I. = Pib
.....(1)
dependent current source marked "g,., Vbe"• where g, is th~
The
current
through
the
diooe
in
Fig.
5.ll(b)
is
given
by:
transconductance of the transistor which is defined as :
Ie = I. + Ib = ( 1 + t} ) ~
.....
(2)
ICQ
...(3)
8m - -
.
=
...(1) .
YL
.
.
-
VT
The small signal transconductance is also a function of the
Q-point parameters and it is directly proportional to the de bias
cnrrent
Q.10 Draw. and explain '• model for common base
configuration .
Ana. : Jk common base configuration of a transistor _is shown .in
Fig. 5.9(lt). The base emitter junction· is forward bt~ while
collector base junction is reverse biased. Th~ forward btased EB
junction ·can be represented by a diode m the re model of
Fig. 5.9(b). For the output side ,
=
aI
.
.
.....(l)
Thus a con;oJled c~nt source appears on the output side
• .
I ·
(a) A common emitter
(b) Approximate model for
configuration
the CE conftgn;.tion
(F-14l5)F1g. 5.11
But as the value of Pis much hi~ than 1 ,
as shown in Fig. 5.9(b).
.
le "" t} Ib
.
,
.....(3)
The diode in the approximate model of Fig. 5.ll(b) is
replaced by the ac resistance re and the re model for the common
emitter configuration is drawn as shown in Fig. 5.12.
C·
It= Ib
······•
8~---..,....~
+
(a) A common base traJ]Sistor
(b) remodel oftbe CD
configuration
(F-1423) Fig. 5.9
f:
a !. 'J · S II I II I I 0
configuration
E
E
<F·14l6>Fig. 5.12: r. model for the CE configuration
II S
•
4-48
ters associated with this model are input
current gain and output conductance.
impedance, voltage ratio, letely different from each other, this set
.
th . units are comp
Smce elf . . 11 d as hybrid parameters.
. .
of parameters IS ca e
.
h parameter model of CE ampiHier.
14 Explain the •
The four param~
0.12 sate merha and demerfla of r. Model.
Ana.:
Merits otre Model are ,
1.
Tile 'pllJ'Ilmeters of r. model can be determined for any
tegioo of operation within the active region.
2.
lt is a simple and less elaborate model of a trnnsistor.
3.
These parameters can be obtained easily from the "h"
parameters which are specified by the manufacturer.
Demerits ol' reModel ,
I.
re model does not account for the output impedance level of
a device and feedback effect from the output to input.
2.
This model is sensitive to the de level of operation of the
amplifier. Therefore the input resistance will vary with the
de operating point. '
a.
Ane .:
. .
the simple CE configuration of Fig. 5.15 (a).
Constdenn? th four variables are as follows :
For this configuration . e
·
1.
Input'current li =lb
.2.
'Input voltage Vi =Vbe
3.
Output current lo =Ic
4.
Output voltage Vo =Va:
..
Q.13 Explain hybrid model of BJT.
Ma 09,Ma 10.Dec.10·
®
'ij;"+
:p•.,O port
Output
port
active
device.
between input and wtpul
(a) CE confi~ration
(b) b-parameter equival~nt for ·
transistor in CE configuration
1
<F-410 ) Fig. 5.13
LEmittor ls ~
: Transistor as a two.port system
The bybrid equivalent circuit consists of four quantities
caUed the hybrid Parameters which are hn, h12, h21 and h22• These
are tbe components of a small signal equivalent circuit. Fig. 5.14
shows the h-parameter equivalent circuit of a two port network.
·
h11
.
1
0
2
(F-414) Fig. 5..15
Applying KVL to the input loop of h-parameter equivalent
circuit of Fig. 5.15(b) to get,
ybe = hje lb + hre vee .
...(l)
Applying KCL at the collector node of Fig. 5.15(b) to get,
lc = bre lb + hoe V ce
.
...(2)
Expressions for h-parameters for CE configuration can be
obtained from Equations (1) and (2) by letting Vee or lb equal to 0.
b-parameters for CE CC?nfi.guratioi,l are :
~
1
\
2
(F-41 I ) Fig. 5.14 :
b-parameter equivalent of a two port network
Table 5.1 lists the h-parameters, their expressions and their ·
names along with their units.
TableS.l
....
8r.
Name
No.
hu
1.
Input
impedance
Ohms
vi
hu=T
I
2.
hl2
Reverse
voltage ratio
V0
h12= v
~~
Current gain
~~ =
4.
~
OUtput
conductance
h21=
I
i.
I
0
e :t '. II
'• II I II I I II II S
i-=0
, I
v ce
Ana. : h·parametera of common base configuration :
hib = ~
.I
v0 = 0
- .•
Vcb=O
I
hn, = t
e
Vcb = O
Siemence
1._
v
I
~
0 ·15 Draw hybrid equivalent model for common base
configuration.
.
·
·
v.
0
3.
hoe ;:::
=0
11= 0
hrb
=~
v cb
I
I. = 0
hob=
V
cb
I.= 0
_:Iectr.onic Devices & Circuits-! (Elex.-MU)
~49
conditions. The parameters of other equivalent circuit <re model)
can ~ determined for any region of operation within the active
region and are not limited by the single set of parameters provided
by the specification sheet.
· Q. 19 For CE amplifier with bypassed Re .d erive the
. expre8slons for Av, " , Z. and Zc,.
(a) Circuit
(May 07. May 14
{b) Hyb 'd
..
n eqwvaient circuit
(F-416) Fig. 5.16 : h-parameter
• al
equav . ent circuit"
Ans.:
Q.16 Draw hybrid equivalent mOdels for ~om
collector configuration.
. mon
Ans. : .h-parameters of eommon coll~t
0.
=
t IV==O
..
.
="';flgu-.,
h,.
Vc,;=O
The CE ampiifier with bypassed Re is shown in
Fig. 5.18(a). R., ~and Rs form the voltage divider biasing circuit
to bias the transistor in the forward active mode. The coupling and
bypass capacitors are assumed to be large enough so that they are
replaced by short circuits in the_ac equivalent circuit
Analysis:
Step 1 :
Draw the ac equivalent circuit :
The ac equivalent circuit, obtained by replacing all the de
short circuit is shown in Fig. .5 .19.
sour~s and capacitors by
I
h.,.,
= vee
(a) Circuit
~=0
Fig. 5.18 :CE amplifier
Fig. 5.19:AC equivalent circuit
(b) Hybrid equivalent circuit
with byp35Se4 RE
<F-417) Fig. 5.17 : h-paramerer equivalent circuit and .
expressions for CC configuration
·a .17 State the typical values of h-parameter for the CE,
CB and CC configurations.
Draw the hybrid-1t equivalent circuit :
Replacing the transistor in ac equivalent circuit_ by the
hybrid 1t equivalent circuit is shown in Fig. 5.20. .
Step 2 :
Ans.:
Table 5.2: Typical values o~ b-parameters for different
configurations
(F-1474)
br
4.
by.
50
4
2.5 X 10-
b0
25 ~
Step3:
1
25 flAIV ·0.49 fJ.AIV
Q.18 State merits and demerits of hybrid model ·
Ana.: MeritS of hybrid model are ,
1.
h plU'3llletecs ~ be easily measured.
2.
·
. .
They can be calculated fiom the static cbaractenstlcs of .
transistor.
. .
beets
Manufacturers pr~vide h parameters ~ tberr _data s. . · :
easily and convemently m crrcUlt
h parameters can be u sed
analysis and design.
Demerits of the b-paramere~ are ,
.
The hybrid parameters suffer from a major disadvan~ge
that they are defined only for a partic~lar set of operating
3.
4.
casv-solutiOIIS
Fig. S.20 : Hybrid'-n equivalent circuit
Expression for voltage gain ( Avs> :
. Avs
=~
Vs
...(l)
But V0 = Voltage developed across (r0 II Rc II ~)
due to current gm V11•
..
vo =
- ~ Vx (roll Rc.ll ~)
...(2)
And v" = Voltage across R.'I wflere R.'I = ( R 8 II r,J.
..
vfl. =
(Ro II r,J
Rs + <Ro II rx) X Vs
... (where R 8 = R 1 II~)
4-50
z::::::o
~lc Devices & Circuita-l (Elex.-MU)
.
...(3)
Io
. _ 8m V" X (r0 II Rc )
(ro II Rc) + RL
...(7)
=
From Fig. 5.22(a) •
, Substituting Equations (2) and (3} into Equation (1) to get,
Avs
'
= - 8m V' (ro II Rc II RtJ X ( Ro II r,J
£Rs +<Roll r,J] v"
Avs ,.. - &n (ro II Rc II Rt.) X
~
Also
R;
(RRII r,J
.
It, r~~
. . .
.
the principle of current diVtston at Node
:. It,
Rs +(Roll r") ...(4 )
=
. V
..
11
Ru r.
R8
+ r11
X
I; ·= <Roll r,. ) I;
v
_ -L<rall(iex(R llrn >I;
lo - .Rt_ + (ro I R:c) .
I
...<~>
= <Rs II r"> = <R, II Rz II r.J
= r"
...(8}
. . th
pression of into expression for 10 to get,
Substituting e ex
·
"
·
me ex,pressioo for R; is,
Step 5 : Expression for output resistance
•
But It, is obtained by ustng
4:Exprealon for tbe input resistance R: :
From Faa. 5.20,
=
B.
'
This is the required expression fur voltage gain. The
negative (-) sign of Avs shows that V0 and V8 are 180° out of
pbase with respect to each other.
Step
V11
"
Current gain
AIS=
'J. =
I
.
B .
.
gm (r0 II'Rc ) <Ru II r,) ·
Rt. + (r0 II Rc) ·
...(9)
•
This is the required expression for the current gam.
the given circuit as shown In Fig. 5.23,
Q.20 For
May 15. 10 Marks
d8termlne Z1, Zc,, Av·
R:·:
The output resistance R' is obtained by setting the
0
independent source Vs to zero. As Vs =0, V" =0 so g.,. V,
the hybrid-n circuit gets modified as shown in Fig. 5.21.
=0 ail<:l
<F-1415) Fig. 5.21 : Equivalent circuit to calculate R:
· So the output resistance looking back into the .output
tenninals is,
,
R0 '
R,
=
=
...(6)
Step .6 : Eq»ression for current gain (Am) :
AIS
= ·~I
(B-2645)
Ans.: .
Giv.e n :~ = 150, Assunie VA =·oo
Type of circuit:
CE amplifier with bypassed RE
Type of mOdel :
Hybrid - n
Part I : DC analysis
Step 1 : Thevenin's DC equivalent :
j
Io Fig. S.22(b) , OutPut current 10 can be obtained by
coosidering the current division at Node A. The current gm V, gets
divided between (r0 II Rc> and R._.
.
Fig. 5.23
Vm
R
B
=
Rz .
16 .
R 1 +Rz xvcc_
=68 + 16 x12=2.29V
= R
l
II '.,'2
D = 16
x 68
16 + 68 =12.95 k.Q
,.----Nodile
.~......
(b)
(a)
<F-147'> Fig. 5.22
Hence using dle current division principle to get.
1:
a :. 1J
•, II I II I I II II S
<B·l64') Fig. S.24(a) : Thevenln's de equivaient
£!ectronlc Devices & Cltcults-1 (Eiex.·MU)
4-51
Step 2 : Find ~ :
In Pig. 5.25(b) , the resistance r0 has been assumed to be oo
Vm-VI_IB
Is
.. lcQ
=
=
=
and we have used the tU11 current source and not Sm V" .
R 8 + ( 1 + ~ ) Ru
. 2.29 - 0.7
12.95k + ( 151 X 1. k)
~ .18
I
Step 1 : Obtain tbe expression ror R, and R1 :
•
=9.71J.A
From Fig. 5.25(b),
~ = Vtflt,
...(1)
But vb = ~r.+J.,Re=lt,t,c+(1+f.\)lt.Re
.. Vb = Ib(r.+(l +f.\) Re]
...(2)
=150 X 9.71J.A =1.46 ntA
Step 3: Find rK, &nand r 0 :
=
v
Assuming, VT 26 mV r
It
.
~
= _.!__
_ 26 x 150
lcQ - 1.46 =2.67 Jc.q
=3
1.46
Substituting Equation (2) into Equation ( 1) to get,
lt,[r,+(l+f.\)Rg]
R1 =It,
..
VT =26 X w-3 =56.15 mAN.
8m
v
ro = f:!:.=oo
"CQ
...
s·mce VA is .not specified. ·
Part II : Small signal analysis
rlt+(l +~) R£
...(3)
Rs II R; =CRt II~ II [ Gt + {1 + ~) Re 1
...(4)
Step 2 :Th.e expression of voltage gain Avs :
St,ep 1 : Draw the smaU signal model :
=
Avs
c
8
+o----.--~
=
=
.. Rl
,
And R.I ·
~
Vs
Referring to·the partial output circuit shown in Fig. 5.26.
r---o----+
8 -·"+
"'
+
lllb
r-
-l
. ~
(B-2650) Fig~ 5.24(b)
Step 2 :
R., R
0,
Vs
Ac
f\.
R'
0
I
.Av
=
(a) Circuit to obtain V0
Vo
-gm V,.Rc
It
I
,
R0
=
A;
Ae ·
V0 • = Voltage developed acroSs (Rc II RJ
.. V0 = - ~~<RciiRJ
.
...(5)
Referring the input circuit shown in Fig. 5.26(b).
Vb = ~R; or ~=Vb/R; ·
•••Ans.
-gm~
...Ans.
185.3
(b)
<F-1478) Fig. 5.26
-
II R; =2.67 k II 12.95k =2.21 k.Q
= v.= V
= - 56.15x3.3= -
R0 =
r r
: SmaU ·signal model (without load)
Av witboot load :
R8
b
Re
A;'
R; =. · r" = 2.67 k.Q
R~
Vo
. Substituting this into Equation (5) to get,
oo
••.Ans.
Rc=3.3W
Vo
=
- f.\Vb<Rc.ll&2
R;
Q. 21 For CE. amplifier with unbypa$sed Re, derive the
expressions for Av, A, , Z, and Zc,.
···~~ijiitl:l•l§Wmlf~~l!'IMI•IMfMd
...(6)
R.
,
xVs
R.+Rg
1
But
Ana.:
The CE amplifier with unbypassed Re is shown in
Fig. 5.25(a) and the bybrid-1t ~u~valent ~ircuit is · shown in
Fig. 5.25(b). The bypass capacitor~ ts not bemg used.
.~ =
.. Vs
Avs
...(7)
:. Avs
This is the exact expression for Avs·
,
But if Rj »
approximated to,
(a) CE.ampUfter with
unbypassed ~
(F-1477)
easv-s oluii OIIS
Avs ""
.(b) Hybrid-1t equivalent
circuit
Fig. 5.25
If
~
Rs
and (1 + ~) »
(l+ f.\ ) Re
=. (1 +f.\) then,
r"
then Avs is
4-52
~
Sectronlc Devloes & Clrcuits·l (Eiex.·MU)
Avs• - CRcRt;II RJJ
(8)
...
This is the required expression for the approximate voltage gain.
St!!p 3 : Output resistaate :
The output resistance is ·obtained by letting V s
0 in
Fig. 5.27. Assuming that a source v. is connected between the
output terminals ~ the current supplied by this source is 1.:· .
=
..
'•
r,.
...(2)
.
'
flo'
<F-1479) Fig. S:J:T :
Orcwt ·to obtain output resistance
=
.
As Vs 0, It, will reduce to zero. Hence j}Ib = 0 so the
depeodeot current source is replaced by .an open circuit, as shown
...(3)
in Fig. 5.27.
. ...( 9)
Q. 22 Draw circuit diagram. ~~ an emitter follower. Derive
expressions f.o r current gain A.. Input resistance
At, output resistance ~. voltage gain A~. Stat8 Its
Important applications. Dec. 03.Ma 06. Ma 12
Ans.:
I
The CC . amPlifier (emitter follower) is shown iD.
Fig. 5.28(a) and the hybrid-1t equivalent circuit is, shown .in
Fig. 5.28(b).
Step 1 : Redraw tbe bybrid-n circuit :
.
The hybrid~1t circuit of Fig. 5.28(b) can ~ redrawn in a
·
simplified manner as shown inFig. 5.29.
R.
Where
I
=
R8 II [rn + (1 + j3) REI
.
Substituting,..the expression for Vb to get,
R'
V0 x [rn .f.. ( 1 ~ ~) (r0
II RE)] =(1 + 13) (ro II RE) X (R~ + Rs ) V s
.
. I
: .. Avs =
· ~s iS the exact
expression
for voltage gain.
.
.
..
Approximate expre&slon :
-
I
..
Step 3 : Input resistance :
Re
(a) Emitter follower ampUfter (b) Hybrid-n equivalent circuit
{F-1480) Fig. 5.28
8
r,.
E
In Fig. '5.30 • applying ~VL to fue input loop ,
. Vb = lbr~t+le~
..
But .le - (1 + j3) Ib
· • Vb = ~ rlt + (1 + j3) It, R6
-
+
.
..
:: ~[r~t+(l+j3)RE)
~
.
R, = ~ =rlt+(l +j3)'Rs
c
: SlmpWled bybrtd..n equivalent drcult
S IJIIIIIIIII ~•
,
...(5)
·
lifi Thi~this the
expression. It is·same as that for the CE
amp er w& unbypassed. Rs·
.
required
R;
1: :1 ~;11
II RE) and R~ >> Rs then
·.
The positive sign is associated with the expressions for
gam. It shows that the phase shift between input and output is 0°. ·
+
v, <
(F-1481) Fig. 5.29
...(4) .
.
- (l+.j3)(roll~)
. ;'-;_.,JAvs - . (1 + j3) (ro II RE) = l
c
Cz
~0
,.
0 . + 13) (rc. II RE )
R.
=
x
'
Vs r,.+(1+j3)(r0 11~) (R.I +Rs)
Ya_
. If rlt <<. (1 + 13 ) (r0
v
-
= Rail
~=Rail [ rlt + (1 + j3) R6 ]
•••(6)
4-53
Electronic Devices & Circuits-! (Eiex.-MU)
--
Ru
• • le
~
········• B
A
t .
..
R8
I
= (1 + p) • RB + RI X~
= 1.. _(l + P> Ru
Ii -
Ra +R;
If R; >> R8 then the expression f01: A1 gets' approximated to,
A1 ~ (l + P>
...(9)
b
a. 23
AI'
Calculate the small signal voltage gain for the
emitter follower circuit shown In Fig. 5.33(a).
Assume that P ; 100, VBE (on)
0.7 V and
VA=100V.
=
<F-1482) Fig.
5.30 : Circuit for obtaining ~ and
a;
Vcc = 6V
Step 4 : Output resistance :
Setting Ys = 0 to ob¥xt the values of R, and R' .. The
0
•
equivalent circuit to obtain the outpt~t resistance · · h
F~g. 5.31.
ts s own m
· · Ro
<Rs II Rs) + r"
=
= (1~ j3) II (ro II Rt,)
and R:
__&__
wbere (l + j3) represents
.
.
.
·- ._..(7)
.
th~ reflected resistance froin base- to.
emitter.
(F-1504)
Fig. S.33(a)
Ans.:
Part I : DC analysis
. Step 1 : Draw Thevenin's equivalent circuit :
The Thevenin's equivalent circuit is as shown in
Fig.5.33(b), ·•·
· Current 80UI'OO
.
act8;8$.oj)fin cil;cuit.
CF-1483) Fig. 5.31: Equivalent circuit to calc~te
'
:. Ro
~
-
R., and
CRsiiRa)+r~t
. (1 + j3) . II (ro IJ REJ
R:
R~ = R[ II~ =40kl(40k'=20k
.
~rn
&
= ..Rt +Rz
=
...(8)
~ Vcc .
. -40k
.
40k+40k x6V=3V
•
+6V
The first term in the above expression represents a very low
resistance. It will further decrease· due to the paralleling effect.
Hence the output resistance of an emitter follower is very low. ·
Step S : Small signal current gain : ·
The small signal current gain is defined as
A1
I/11 where . Ie OUtput current
=
=
Referring Fig. 5.32 t:O·calculate Ar
(F-1505) Fig. S.33(b)
: 'Theveoin's equivalent ckcuit
Step 2 : Calculate 18 and 1c :
At
<F-1485) Fig. 5.32:
But Ie
and.
Equivalent clrcult for obtaining A,
= ( 1 + j3 ) It,
It,= RR!R x~
B
I
r.a s v · s nlutt uus
=
And ~ =
Ia
where
... (neglecting r0 )
Ri = r11+P +13)Rs
Vrn- VaE
3-0.7
Rs + (1 + j3) ~ ·:- 20 k + (101 X 2 k)
(3 Ia = 100 X 10.36 X 10- 6
,.;
1.036 mA
=1?·36 J.lA
I
4-54
8ectronlc Devices & Clrcults-1 (Eiex.-MU)
4co;
Part II : AC analyat8
Avs
Step 1 : Cakulate r.lllld r. :
~
=
r,.
~
=
=
l00x26mV
1.036 mA = 2.509 W
.---+e-.--.. v.
•
(F-1506)
101 X (95.525 k 11 2 k} X 0.9732
2{)().366k
=
101
=
Step l : Draw AC equivalent circuit :
The ac equivalent circuit is shown in Fig. 5.33(c).
· v ..
R,
X 1.959k x 0.9732
: . Avs 0.961
...Ans,
200.366k
Ste 8 . O~tput resiStance :
.
P ' . v
0 for calculating the output resistance. The
Settmg s ·
·
· h
.
. 't to calculate the output resistance 1s s own in
eqwvalent cJfCW
·
.
·
·
Fig. 5.33(e).
=
100
= .!A.
~ .. 1.036 x w-:1 =95.525 w
r.,
=
(1 + P) <ro II Ra ) x 0.9732
E
v, +
Fil.5.33(c): AC equivalent circuit
'\'
<F·~) Fig. s.33(e): Equivalent circuit to obtain the outp~t
step 3 : Draw tbe bybrid-K equivalent circuit :
The bybrid-n equivalent circuit is obtained by replacing the
transistor by its bybrid-n model as shown in Fig. 5.33(d).
As
8 It, ·
E
rx
resistance
fe ·
~~y-~···~
····~~+~~~~~--~~~
---~
..·~~~+
[(Rs II Ru ) + r" J II (r II R )
(1 :1" J3)
o - E
~ The (1 ~~)term is used for reflecting the resistance frombase to emitter.
. . R:
~·
At
= 2·~~ k
<F·15Cr7) Fig. S.33(d): Hybrid-n equivalent circuit
I.
~
=
~
=
=
=
rn + (1 +.f3) (r0 I~RE.)
2.509 k + 101 (95.525 .k lf2 k)
200.366k.Q
=
=
~· II ~ >II ~ =20 k II 200.366 k
I
and R.I
••.Ans.
or 29.22 Q
a common . base · amplifier with potential
divider biasing, derive expression for :
1.
Voltage gah'l : Av
2.
Current gain At
3..
Input .resistance R1
4.
Output resistance Ro
Dec. 05. May 08
Q. 24 For
~ = ~~~
.
Applying KVL to the outer loop ofFig.5.33(d) to get,
vb = ~ r,. + (1 +a>~ <ro II~-> ..
.• Vb = ~[r.+(l+fl)(ro11Ra)1
..
111.959 k
= 0.02922 k.Q
Step 4 : Calculitte R. and a' :
..
[(0.51!2~dl+ 2.509] II (95.525 II 2)
=
~ [r" + (1 +~ )(r0 II Rg )]
Ans.:
The circuit diagram of a CB amplifier is as shown in Fig. 5.34.
~
G,
.
.
~
:fo
~-·
18.18 k.Q
Step S : Calculate output voltage :
=
V.,
(I} It,+ Jb) X (r0
II iy =(1 + f3) ~ (r II Rll)
0
...(1)
Step ' : Calculate vb :
Applying KVL to the Oute[ loop of Fig. 5.33(d) to get,
vb
Jt,r.+(l +P>Ji,.CroiiRs>
. ...(2)
.. vb It, [r.+(l + p)(ro II Rs )] =Jt,RI
..Ya. (1 + P) I,. (r0 II Rg ) _ (1 + p) (r0 II Re )
... (3)
, :. Vb
It, X R,
R,
<F·l486)'Fig. 5~: C~on base amplifter
=
=
=
Step 1 : Draw the ac equivalent clttuit : "'
.
As .
Step 1 : Calculate voltage p1n :
..Ya...Ya.~
s Vb x Vs
Avs • · V
~
But Vs
=
...(4)
,
= Rs +a; =O.S + 18.18 =0.9732
R,
18.18
(5
... )
Subltituting Equations (3) and (5) into Equation (4) to get,
t; : 1 ~.
1J '• II Ill I I IJ II S
9
'i!l!t-----...-~1------0V
(F-to481} Fig. 5.35 : AC equivalent circuit
-
~lc Oevicee & Clreutta-~ (EtelC.·MU)
4-55
s -p l : Draw the hybrid« equivalent drwlt :
But &m r,.
Tbe bybrid-tt eq~ivaJ~t cin:uit of CB Ainpliftet is shown in
Ag. S.36(•): Here the stmphfiod hybrid-It model of the transistor
(withoUt t 0 ) IS used.
·
v ~to+r
[-•- i!.!.ID. +
.'S
"
= IJ
tJ -
- :is_
-R
s
-V
.. .v" =
Assuming
i
= ~
1
+(
:. ·v" = -~s
(a) Slftr..... bybrkl« drcolt
(b) Stnall signal equivalent
ol • traDslstor
drcui_t for CB conftguration
' <F-1481) Flg. 5.36
...(3)
~ ~ + ~E
~ceR=Rslt (l :fj)ll~.
•
xR=-
R!
[Rs
ll(l~f3)11Re]
Substituting Equation (4) into Equation (1) to get.
_ Vo
=
.
v [
(1 + IJ)
J
J
II Re
-<RciiRtJgmx-~ Rsll---r;-IIRE
v =. Avs =+ gm <RcR~
II R, ) [
(1 + 13>
:. V;
Rs II r.
(5)
···
This is the required expression for the voltage gain.
Approximate expression ror.Avs :
= 0, the ~el combination of Rs. (1 + f3}1r.
.
· · Rs II (1 ~ (3) II _
RE = Rs
Assuming that Rs
and RE approaches to Rs.·
·
. . Avs
:.Vo = -(RciiRdgmVn
In Fig. 5.37 , applying KCL at node E to write,
~+'-e
:.•.(1) . ·
=~
As
........
G
E
I.
•·····
=
gm<Rcii&Jxo
Rs
. ~'S
: . Avs = gm <Rc II Rt)
Step 4 : Exi»ression for smaU signal current gain :
Sinau signal current gain A18 =
I., I I;
Applying KCL at the emitter node of Fig. 5.38,
...( 6)
+
B
'
(a)
<F-1489) Fig. 5.37
(b)
(F-1490)
~
But
Ie
=
=
Fig. 5.38.
~+Jb+gm V"-IRB
=
0
~
~
:. ~ +. r. + &m v. + Rs
=
0
:. v"[:" +gm+ ~
= tl
... v. = [~ •
= -~
But 8m r"
...LJ -\[a..u <t:'pi]
.•.(2)
I
• . •
• li
I
II
I
I · ' II '•
...oJ
~
R
.
Referring Fig. 5.38 (b) and writing the expression for
cum:nt (0 using the principle of cunent division. Current (g. V• )
get& divided betw~ Rc and R.. at node A.
Electronic Devices & Clrcuits-1 (Eiex.-MU)
:. l,
=
-&:
Q.25
Rc + RL X gm Vrr.
•••(8)
Substituting Equation (7) for Vtt into Equation (8) to get,
=
I,
••
=
A .
. .'IS
J
-&.,&;
[
r
Rc+RL X -~ REII~
[u
~
~ -
&m Rc
(Rc+RL)
"'E 11--.!L.._]
(l+f\)
(9)
...
This is the required expression for the small signal current
gain.
·
Expression for input resistance :
Assuming ~
=
Resistance seen betwee~ emitter
and ground and
-
Resistance seen by the voltage SOUJ:Ce
I
R1
Referring Fig. 5.39 to obtain the values of~ and R' .
.
.
Ans.:
I
~
= Resistance between emitter and ground
D
=
=
: . ~'i
r,. reflected from base side to emitter
___!a__
.
(1+ ~) =re
(F-J..S al) Fig~ 5.41
...(10)
Given :
p =150,
VEE=-4V,
.Rc=7.lk, .
~
=3.3 k,
Va; =lOV.
. Type of amplifier : C. B.
.
Model used for analysis :.hybrid 1t
Part I : DC aDalysis
Step 1· :
· DC equivalent circuit :
The DC equivalent circuit is .as shown in Fig. 5.42,.
E
Applying KVL to base loop to get,
v~
=
V~;~E +IE Rs•
V £ili- VsE 4-0.7
+
:. IE =
RE
Is -
1 + 13 =
IE
= . 3.3k
1 X 10:- 3
151 .
=1 mA
6.62 ~
I
Fig. 5.39 : Circnit to obtain Rt and R 1
(F-1491)
~ ,;
The resistance looking iDto the emitter with grounded base
is usually defined a8 rc which is e](tremely sinall due to the
presence of ( 1-t: (:\) term in the denominator.
·
Thus R; of a CB amplifier is very small. .
,
Ri
·
=
Pis = 150 x 6:62~
0.993 mA
...(1)
~
= RsiiR;= Rsll (l+P)
...(11)
Due to paralleling the input resistance is reduced further.
Exp~on for output resistance :
For obtaining the expression of output resistance, we have
= o·and-assume that a source Vx is connected between the
output terminals.as shown in Fig. 5.40.
·
. to set Vs
•
(F-lS49)
. Step 2 :
·Fig. 5.42 : DC equivalent circuit
Calculate riP r 0 and &n :
_ . VTP 26mV x 150
r" icQ = 0.993 mA
...Assllilling VT =26 mV
g
Ro
(F-1492) Fig. 5.40 : Equivalent circuit to calculate R.,
.
'
As V5 .o, V" 0, hence &mV11 = 0. So the depen~ot
'
=
=
current source in Fig. 5.40 can be replaced by an open circuit.
;, R0
Rc
...(12)
And R'
0
t;
a ~. II
=
=
Roii~=<RciiRJ
S II IIIII 1111 S
...(13).
icQ
m
0 .993 mA
=3.92 k
=V-,
- 26 x l0-3 =38.19mAN
I
VA
· ro
= icQ =
oo
Since VA is not specified.
. •• •
Electronic Devices & ClrC:uits-1 (Eiex.-MU)
=-
Pa_rt n : AC analysis
0.27 State and explain the Miller's theorem.
Step 1 : Draw the hybrid n equivalent circuit :
Ana.:
· Considering an arbitrary circuit configuration with N
distinct nodes I, 2, 3 ..... N as shown in Fig. 5.44(a).
Assuming the node voltages are v •• v2. v3 .... VN where VN = 0
which means N is being treated as a reference node or ground
Fig. 5.43 shows the hybrid 1t equivalent circuit.
.
n~
z
7-,-~
(F-1550)
Fig. 5:43·: SmaU signal equivalent circuit
Step 2 : Calculate the parameters :
·
Vo -gmVx Rc •
Voltagegam Av=-v _
=g
1.
·
. i
=
:. Av
38.19 X 7.1
2.
Input resistance
r,.
'D
~
=
38.19 X 10-
=
0.9836
~
R'0
=
=
•
••.Ans.
••.Ans.
X R~
I
=38.19 X 10- 3 X 25.76 .
,
...Ans.
00
Rc
that 11 =- 12
{F-458) Fig. 5.44
Output resistance
4. ·
identical node vo~ges. Note
3.92k
p]
3
(b) A network having
N different nodes
••.Ans.
R; = R; II RE = 25.96113300 ~ 25.76 n
Current gain
~ = .&m [ REII I :
(a) A circuit conftgoradon with
m~
= O+~) =T+15Q =25.96 n
R;
3.
=270.936
-~
=7.1 k.Q
Assuming the impedance Z is connected between nodes N 1
and N 2 and the ratio of voltages V.j V1 is denoted by K, wh:e.re K
is a complex number. The circuit configurations drawn in
Figs. 5.44(a) and {b) give identical resuJts in Other words they are
equivalent networks.as shown below :
Stepl:
Disconnecting terminal-! from Z and connect an
impedance Z1 = Z I (1 - K) between terminal 1 and ground as
shown in Fig. 5.44(b). . The expressions for ''I... for both the
arrangements in Figs. 5.44(a) and (b) are obtained as below:
·From Fig. 5.44(a),
·
•••Ans.
Q.26 Compare common base, common collector and
common emitter BJT amplifiers.
I,
But as K =
Dec. 02. Dec. 07. May 08. May 12, May 16
Ans.:
Sr.
NO.
=
V 1 -V2
z
....(1)
v
V
,substituting V = KV in Equation (1)
2
I
.
..
II
=
V 1 -KV 1
..
I,
=
Z I (1 - K)
_
z - -
1
Vdl - K)
z
v
Con~idering
....(2)
Fig. 5.44(b) to wiite,'
I.
Input tenninal
Base
Emitter
2.
Output tenninal
Collector
Collector
Base
Emitter ·
3.
Common terminal
Emitter
Base
Collector
Comparing Equations (2) and (3), they give the same value ofl •
4.
Input resistance (R;)
Medium
Low
High
Step2:
Medium
High
Low
Disconnecting terminal 2 from the· impedance "Z" and
High
' pedance ~ = (i(:"i)
ZK between terminals 2 and
connect an tm
ground·as shown in Fig. 5.44(b).
5.
Output resistance
(RJ
6.
Current Gain (A1)
4
High
Less than
1
7.
High
Voltage Gain (Av)
High '
Applications
Low
AF
noise prevoltage
amplifiers · amplifiers
Less than
1
- "'''*i'•m•''''"
--------lis
Buffer
amplifiers
..
I,
=
.!J..
Z1
v
= Z I (1 -
K)
· ...(3)
1
.
The expressions for "~" from the two configurations shown
m Figs. 5.44(a) and (b) are obtained as belbw :
Considering Fig. 5.44(a)
..
~
_
-
_ V2 - V 1
- 1•Z
....(4)
v
. .
But K =~hence substitute V1 = V2 1 Kin Equation (4) to get,
a~
.gi~e same Val-: . ..
~~~~~~~~~~~~----------~~--~---~~::==~~~~:;::~~~~:~~
~ OevloM & Clreultl-1(Etex.·MU)
V1 - <Va I R)
z
l2 •
12
-
V2 ( 1 - 1 /K)
-- z
-
•
v: (JK _ 1)
"-Zk
-
v
. .. (5)
11 • ZK /(K - 1)
Prom fttl. 5.<4-4(b),
~
v
. • 12 • l.a • ZK I (K - 1)
Comparing Equations (5)
(6) ' they
the
us the identical nodal equatJons are obtamed from two the
of Lz· Th .
of Figs. 5.44(a) and (b) therefore we conclude that
8
configuration
,~ are equivalent. This theorem is useful to m.,~..
these· two
· 1s
· poss1'ble to find
. networ....
·r
d only if it
1 the value of -K by
calculations 1 80
s The transformation of network sh...·- ·
· d pendent mean ·
uuwu tn
~roe 10 e to Pi 5.44(b) is known as Miller's theorem. Tbe
F1g. 5.44(thea)
•~·used for the ana]ysis of circtrits such as CE
Miller's
orem 1
.
ampHfier with collector to base bias.
-
.. . (6)
Chapter 6 : Field Effect Devices ·
0. 1 Juetlfy : FET la a voltage controlled device.
Ana. : The voltage applied between gate and source (V05) controls
lbe drain current 10 • ~fore FET is a voltage controlled device.
'The drain cu:n-ent (lo) is known as the controlled parameter while
gate to source voltage (V05) is called as the controlling parameter.
Q. 2
Justify : FET la a unipolar device,
Ana. : FET is a unipolar device, that means the current flowing
tbrou&h it is. only due to one type of charge particles, boles or
elecuoo.s. 1be conduction taken place only due to electrons in the n
c:bmnet FETs and only due to holes in p channel PETs.
Q. 3
in Fig. 6.2(a). On both sides of ~-type bar,. bea~ly doped ( p )
·
h
been 1&ormed by alloymg or by diffusion to create a I>reg.~ons ave
ected
·
'
·
· ction Both these p regions are conn · together and VIa an
~~=c co~tact the gate terminal is brought out. ~ supply voltage
is connected between the drain and source termmals of a JFET
hence current is cau.sed to flo~ ~ong ~ len~ of.the ~-type bar.
This current is due to the maJonty earners which m this case are
electrons. Fig. 6.2(b) shows the symbol for then-~ JFET. The
arrow on gate terminal indicates the convenbonal cmrent
directions.
~~~
St8tll ttdvantagea of JFET over BJT .
Ana.:
1be PET enjoys several advantages over the conventional
bipolar junction transistor. Some of them are as follows :
1.
It is a unipolar (levice so its operation depends on the flow
of majority carriers onJy.
2.
3.
4.
QA
It is relatively immune to radiation.
fET has a very high input resistance (typically few
megaobms).
FET is less noisy as compared to BIT. It produces less
internal noise.
What are disadvantage of JFET ?
Ana.: Disadvantage of JFET are as follows,
I.
FET amplifiers have lower gain. .
2.
It bas a relatively small gain-bandwidth product as
3.
4.
COIDp8I'Cd with that of a conventional transistor.
It can not be used as a current amplifier.
Tbe value of transconductance &, is small.
.
n
Source (S)
Gtve clualflcatlon of Field Effect Translators •
AM. : 1be f.eld effect transistors are classified as follows :
(b) Symbol of n-cbannel
(a) Structure ofn-cbannel
. JFET
JFET
(B-263) Fig. 6.2
Channel :
Channel is the n-tyj» material between the two gate·
regions. The majority carriers (electrons here) move through this
channel from source to drain. Since the channel is made of n-type
material, this FET is called as n-channel JFET. The electrons enter
the channel through the "source" terminal and leave through the
"drain" tenilinal.
.
·
Q. 7
Q. 5
~Source(S)
Ana. :
Draw and expJaln construction of JFET.
·
umLi
Drain (D)
p-channel
er&in (D)
Gate (G)
<J-%0)
Q. t
Gatf
(G)
Jl'l&. 6.1 : CIMdllcation of FETs
(Jt·r.
11J f.l.t·; 1? lJ Pt. 13 [J1ily 1!J. De c
Nil.:
1!)
Tbe wucwre of an o-duumel field effect transistor is aa
&bowo iJ1 Fis. 6.2(a). A .emiconductor bar of n-type material is
LakeD and ohmic oonliCI.II arc made to the ~wo ends of the bar,
'Jbete are tbc t.enninals named dtain (0) .and ~ (S) ua ahown
lii1***11•D111ll
Sourc8(S)
p
SUtch and explain the conatructlon of JFET.
Souroe (S)
(It) Structure of p-cbannel
(b) Symbol of p-claaDDcl
JFET
JFET
(8-2545)
Flg. 6.3
Electronic Devices & Circuits-! (Eiex.-MU)
---- The construction of. a p-cbannel JFET •
· fig. 6.3(a) and its symbol is as shown in Pi IS as shown in
difference between the p-cbannel and n-cban g. 6-3(b): The only
type semiconductor bar is being used with twnelJFETs ts that a pIn p-cbannel JFET, current flows due to the ~ ~-type ~a~e regions.
bOles are majority carriers in a P. 0 es. This ts because
c;baDDel JFET current flows due to fl~osefIDllconductor bar. In ne ectrons.
Q. 8 ~ketch and eXplain the working of JFET.
Ans.:
·
Dl4Wii
. alA pofsitiJFE
've.Tvolt_ageVis a~plied_between the drain and source
tetJJlln s o a
• I.e. 05 1s positive and
· ·
. be
th
a negative voltage is
applied tween e gate and source tennina1s . V .
.
·
f JFET ·
I.e. GS IS negative
The operation o
IS explained for different a1
·
' foIIows:
v~~Vosas
1.
Operation of n-clumnel JFET with v _ 0 The
GS:
effect
of gate JFET
to source
voltage VGS on the operati'on of a n.
channe1
IS as follows ; In Fig. 6.4(a) in which gate is
connected to source making v GS -- 0• Due to the supp1y
voltage V , current starts flowing through th h
The drain 05
e c anne1.
, current is con~olled solely by the resistance of
the semtconductor matenal between drain and sourc Th
'al h
e. e
n-~ maten . as a finite resistance. Therefore the drain
current flow. causes a voltage drop a1ong the channel. This
~ol~e drop will reverse bias the gate to source· p-n
JUDCbOn.
Operation or n~bannel JFET ror lal'l• value or
negative VGil .: As the negative volt.ugc V011 ill fUrther
increased, the depletion regions spread more Into tho n-typo
bar. At a certain value of negative V0 8, the depletion
regions touch each other as shown In Pig. 6.4(c). AI' thl11
point the channel width is zero and therefore the drnlo
current lo =0. This gate to source voltage ut which the
diain current is cut off is called as Vos toll')'
Thus with increase in the negative gate to source voltaac•
the channel becomes more and more narrow and drain current 10
-reduces. For Vos = 0, maximum dmin current I0.9s will flow
through JFET. The drain current then reduces with increase In the
· negative gate to source bias. Thus JFET is a voltage controlled
device. Cutoff Voltage V0 s <o« > : The vaJue of Vos that makes the
drain current 10 approximately equul to zero is called ll8 cutoff
voltage and it is denoted by Vos <om·
3.
Q, 9
Define pinch off voltage for JFET.
Dec. 14. Ma
lh
Ans.:
The pinch off voltage VP is defined as the value of V03
beyond which the drain current becomes constant. VP is defined
a1ways for Vos =0.
Q. 10 Sketch and explain the charactertatlca of JFET.
Dec.10.Mn 12.Mn 14. Mn l!i.Ucc.l!>
Ans.: Drain characteristics is a plot of drain current 10 (on Y-~is)
versus drain to source volt.uge V00 (on X-axis) at different values
of gate to source voltage V0~.
(a) Operation
with no bias
voltage
(b) Operation with
a small negative
gate source bias
(c) Operation with
a large negative
· gate source bias
~~~,~0--1~
5--~~--------------V~N*l
Fig. 6.4
The depletion region of the reverse biased ~n. jw;tction
·· penetrates more into the n-type bar because 1t ts hghtly
doped as. compared to the ·heavily doped p-type gate. The
penetration of the depletion region into n-type bar depends
on the magnitude of reverse bias voltage. Due to _the
dePletion regions the width of ~e "~banner• available for
.
conduction is reduced, as shown 1n F1g. 6.4(a).
- Source saturation current IDSS : The value of dram
.
- .
' din to v _ ov is called as ·the source
b I
I
current correspon g
.GS -: ·
saturation current and tt JS denoted ~ nss· nss
- ds
.....vimum
drain current because ~e•
C91Tespon
to the ll-U&A-0
•
channel is widest for VGS =OV·
ti v
Operation of a n-cbaDDel JF.ET for small nega ve csd·•
.
lied between the gate an
A small negative voltage ~s app .4(b) Due to the reverse
6
source teroiinals as shown tn Fig.
so~e junction, the .
voltage applied across ~e ga~n into n-type · material
. penetration of the deplett~n reredgt
the channel width
.
forth
This wtll
uce
mcreases
er.
'dth
less number of
1
further. Due to reduced cha::n ;,m source. Therefore
electrons can pass through t6
.
v
drain current Io reduces with incre~ .m - os·
(B-Ui7)
2.
P.:lS\1 - SO I II II O il S
.
V,(lar Voa • CN)
Fig. 6.5 : Drain characteristics or an n-cbannel JFET
The characteristics has been divided into three regions viz.
cut off, saturation and ohmic region.
1.
Cut off region : With increase in the negative Vos voltage,
the channel width available for conduction decreases. At a
certain voltage called "Vos (om" the depletion regions touch
each other to close the channel completely. Hence the cut
off region corresponds to 10 =0 and Vos > Vas (off!· In the
cut off region 10 =0 and there is no effect on its value even
if we change the drain to source voltage (V00). The JFET
operates as an open circuited switch in this region.
2.
Saturation region : As shown in Fig. 6.S, saturation
region is that portion of the characteristics where 10
remains fairly constant and does not change with changes
in Vns· This "saturation" is entirely different than the
"saturation" in a transistor. In order to use the JFET as an
amplifier it is operated in the saturation region.
3.
Ohmic region : The: drain current 10 varies with variation
in the drain to source voltage Vos• in ~ ohmic region as
shown in Fig. 6.5. The JFET is therefore said to be
operating as a. voltage variable resistance (VVR) in the
ohmic region. It is equivalent to a closed switch in this
(B-172)
-
4-6()
Electronic Devioee & Clrcuits-1(Eiex.-MU)
J0 (mA)
region. The resistance offered by the JFET decreases with
decrease in the value of negative gate to source bins
voltage i.e. negative V 011• The FET resistance in the ohmic
region is given by.
Ros = Vp /loss
where. Vp == Pinch off voltage and
loss
Maximum drain current.
FET bl'\'akdown : When a JFET is operating in the
saturation region. 10 does not change with change in V os
upto a certain ·value of V 05. If V 05 is increased further
beyond this value, the gate channel junction breakdown
due to avalanche effect and the drain current shoots up
suddenly as shown in Fig. 6.5. This can damage the device.
The value of breakdown voltage does not remain constant.
In fact it decreases with increase in negative values of V 05•
The operation in the breakdown region should be avoided
in order to protect the JFET against damage. .
Effect of negative VGS bias : With increase in the negative
V05 bias the channel width decreases and drain current ID
~ces proportionally. A family of curves for different
values of V05 is as shown in Fig. 6.5. With increase in the
negative V 05 bias, the breakdown will take place at lower
values of V 05•
·
loee ···············
4
..... ..t. . . . .
=
4.
5.
Sketch and explain transfer characteristics of
Dec. 10. May 14. May 15
JFET.
Ana. : Transfer characteristic is the plot of output current In
versus the input controlling quantity which is Vas in this case. For
a BIT the transfer characteristic is a graph of 1C versps IB: ·
2
. . ........i··········~···· ·······
Yos (vol18)
(B-275)
-1
-2
0
.
. Transfer characteristics of a JFET
F Jg. 6•6 •
the two extreme points on th~ characteristics. The
ese are
,.
.
'th red .
.
haracteristic grows exponential1y WI
uctlon m the
trans .er cV The transfer characteristics defined by tbe Shockley's
negative as·
1c: •
hi
·
affected (remain same) by the networ m w ch the
eqJFEuaTtl~n
are un ted The transfer curve can be obtained using
ts connec .
. .
Shockley's equation or from the drain charactenstlcs
. Th
ti
Q.13 :Draw the structure of p-channel JFET.
Ans.:
Drain (D)
Pinch off Voltage (Vp) : The "pinch off' voltagds the
value of V os• at which the drain current reaches its constant
· saturation value. Any further increase in Vos does nOt have
any effect on the valu~ of 10 . Do not make a confusi~n
between the cut off and pinch off. The pinch off voltage is
denoted by V p·
6.
8
p-channel
Q. 12
Source (S)
(a) Structure. of p-channel
(b) Symbol of p-channel
JFET
JFET
For a bipolar transistor the relation between output current
Ic and input controlling quantity Ia is given by,
(B-254~ Fig. 6.7
1C
f}dc Ia
...(1)
Q.14 Draw drain characteristics of a JM:hannel JFET.
Where ,
f}dc is considered to be a constant.
Ans. : .Fig. . 6.8 shows the drain characteristics of a p-channel
'Therefore the transfer characterjstic of a transistor is a
JFET.
.
straight lioe indicating a linear relation between 1C and lB.
However the relation between 10 and V00 is not linear. The
relationship between In and V05 is defined by Shockley's equation .
which states that,
=
2
lo
=
Vas]
loss [ 1 - Vp
where,
loss
...(2)
.... ........
FET•clau
=
Maximum drain current or source
saturation current
VP
Pinch off voltage
In the Equation (2), I~ and V" are considered to be the
CODStaD1 quantities. The relation between 10 and Vas is therefore a
squared relatiOD.Ship. which produces a curve whic~ is growing
expooentially as shown in Fig. 6.6. As seen from Ftg. ~.6, when
v 0 volt. 10 = foss and when Vas Vp 4 the dram current
~
=
05
=
~=~
= =-
~
(B·l78) Fig. 6.8
: Drain characteristics
.
.
.
or a p-cluumel
JFET
.
The shape of this characteristics is.same as that for tbe nchannel JFET except for the reversal of polarities of V OS .and V
os·
.
Q.15 Draw transfer characteristics of a p-channel JfET.
Ana. : The transfer characteristics of a p-cbannel JFET is shown
in Fig. 6.9. It is mathematically expressed as foUows :
1:
a •, V '• II Ill I I II II S
Electronic Devlcoa & Circuita-l (Eiex.-MU)
4-61
Q, 19 Give reason : JFET can be uHd u
a voltage
ltl§Mtlj
variable reeletor.
Ane.:
8
I
(8.1?9)
2
3
The field effect transistor can be operated as a voltage
variable· resistor (VVR). Refer to the drain characteristics of a
JPET shown in Fig. 6.10. The region before 1'pinch off' is called as
ohmic region. In this region the JFET acts as a variable resistor.
The drain .to source resistance R08 in this region is dependent ontl1e gate to source voltage. As V08 becomes less negative, more
drain current flows and R05 decreases.
For higher negative gate voltage; 10 decreases and Ros will
increase. Thus the JFET acts as a vo1tage variable resistor (VVR).
Vas (voila)
Fig. 6.9 : Transfer characteristics of a p-channel JFET
10 (mA)
. Even though lo. has reversed its directi'on as compared to
.
that tn n-channel devtce, we have not tak
Th· · beca
en 1o as a negative
1
~~ .
IS IS
use lo and loss both have reversed their
directions. VGS and V P are going to be positive for the p-channel
i -- Loous of pinch - off values
I
JFET.
Ohmic region
I•J§MtJ
v08 (volts)
(B-1634) Fig. 6.10 : Ohmic region in which FEl' acts as VVR
corresponding change 10 the drain current, at a constant value of
gate to source voltage. It usually lies in the range of 50.kQ to few
hundred kQ.
'
rd
V08 = - 3V
-::-1~----------
Dynamic drain resistance is an AC resistance of a JFET is
defined as ~ ratio of ~hange in the drain to source voltage to the
..
Voo= - zv
FET acts
as VVR
Ana. :
I
.. ~-------------- V08 : - 1V
---+-
Q . 16 Define drain resistance for a JFET and state It's
typical values.
v08 = ov
loss -··:..; ·' -;·······' :/
Q. 20 Compare BJT and FET.
Dec. 10. Dec. 15
:The rnlmnlln~or'\11
~"'-~
1!1 Vos
1!1Io constant Vas
=
Q. 17 Define transconductance for a JFET.
Ana.:
The transconductance gm is defineq as the ratio of change in
drain current to the corresponding change in gate to source voltage,
at a constant value of drain to source voltage. It is calculated at a
particular operating point.
(No
.1. Io
.1. V GS constant V vs
·g.,- - -
..
-
0.18 Define amplification factor and give relation
between gm , J1 and rd.
Ana. : Amplification factor "J.L" is defined as the ratio of change
in the drain to source voltage, to change in the gate to s?urce
voltage, at a constant value of 10 . It is calculated at a particular
NPN
operating point.
j.L
.1. Vos
.1. Vas 10 constant
= -
...
Relation between the parameter• :
Equation 0 ) can be rearranged as follows :
IJ. =
..
J.L
A 10
x A Vas
...{2)
= rd x 8m
d .
Thus amplification f..ctor J.tl~ equal to the product of raJn
resilltance rd and transconduc!JUlCC Bm·
A&"J.L" is the ra tio of two voltases hence it is unitJess.
ea ~ v
s nlul tfl ll li
(B-l84)
Q . 21 What are the applications of JFET ?
Ane.: The applications of JFET are,
JFET can be used as an amplifier.
JFET can be used as a switch.
2.
3..
It can be used as analog switc~ in cin:uits like sample and
hold, amplitude modulation, ADCJDAC (analog to digital
or digital to analog) converters.
As a voltage variable resistor (VVR).
4.
5.
. In di ital ci.rouits.
1.
avi>S ~
··
(B-283)
...(1)
--
4-62
Electronic Devices & Qirculta-1(Eiex.·MU)
Q: 22 An A-Channel JFET hu to.. • a mA and Vp • - 4
Votta.
1.
If 10 • 3 mA calculate the value of V08•
2.
Calculate Y08 (-') for lo • 3 mA.
Ana. !
Gl"'ftl :
loss = 8 rnA, Vr = - 4 Volts und J0
I.
To <ablate Vcs:
As.
·· Vas
..
Vr:J
lo "' lnss [ 1 -
VGS
=
- 4(l
=
ss
=3 rnA.
(~a&e}
2
vr[t -·~J[iJ
Source
-..JY8] = - 1.55 Volts
...Ans.
(B-1635)
• .• Construction ofn~bannel depletion type
Fig. 611
MOSFET
To calculate Vos <•> :
l.
VOS (Mil
= Vas - Vp= - l.55+4=2.45Volts
Q. 23 For a n-channel JFET with loss
=
.•.Ans.
=8 mA, Yp =- 4 V
tf 10 3 mA calculate the value of Vas
Calculate V06 (SAl) for 10 =3 mA
Calculate transconductance (g.,)
May 16. Dec. 16
Ana. : Transconductance ,
1.
2.
3.
8m
=
VGs]
gmO [ 1 ~ Vp
Where, &no
=
- 2 loss
Vp
=
4x10-
3
- 2 x 8 x 10-3
- 4
=4mAN
=
4 x 10-
3
[
1-
= 2.45 mA
Q. 24 What are the types of MOSFET ? ·
AM.:
Q.26 Explain working principle of D-MOSFET. ·
Dec. 09. May 10. May 14. Dec. 15
Ans. : Working principle of D-MOSFET
...(1)
Substitute this value into Equation (1) to get;
Transconductance, gm
Effect of the Insulating Si02 layer :
Due to the presence of the Si02 layer between ~ate ~al
· hannel the input impedance ofMOSFET ts very high.
_
and n type c
•
high ·
This is a desirable feature of a MOSFET. ~e to .. mput
impedance, the gate current IG = 0 for the de operatmg conditions.
(-l1~)J
..•Ans.
•••••
Operation with VGS =OV :
Fig. 6.12 shows that the gate, sourc~ and substrate
terminals are connected together tO the ground _potDl Thus V GS =0
·volt. A J)ositive voltage V 00 is applied between drain and source.
Due to the positive voltage applied to the drain terminal,
free electrons from the charinel are attracted to the drain and the
drain current starts flowing as· shown in Fig. 6.12. The drain
current at VGs ·= 0 V is called as loss· This- is the maximum
possible value of 10~
MOSFET is the short form of Metal Oxide Semiconductor
Field Effect Transistor. MOSFETs are different from the JFETs in
construction and they are of f.o~owing types : .
1.
Depletion type MOSFET
2.
~ment type MOSFET
3.
Power MOSFET
Q. 25 Explafn .vucture of MOSFET.
Dcc.08.Dec. 10.Ma 14.Dec. 14
AM. :
Construction (structure) of the depletion tyj>e.MOSFET is
as mown in Fig. 6.11. A ~type of semiconductor material (Silicon)
is u6ed as a substrate. Usually the substrate is internally connected
to tbe source terminal. But sometimes it is taken out as a separate
tcnniDaf termed "SS". The drain and so~rce terminals are
~ to the o-type regions through the metallic contacts as
shown in Fig. 6. J J. These n-type regions are linked wit~ ea~h
other by a n-cbannel as shown in Fig. 6.11. The gate termmal 1s
insulated from then-channel by a thin Silicon di-oxide layer (Si02) • .
f: :t ~.
V !, U Ill I I II II
s
(B-1636)
Fig. 6.12 : n-cbannel depletion tjpe MOSFET
With
VGS =0 and applied voltage V DD
.
Operation of depletion MOSFET with negative VGS :
In Fig. 6.13, due to negative voltage applied between gate
and cathode terminals, the gate will tend to repel the free electrOns
towards the p-type substrate and attract the holes from the
substrate. These electrons and holes will recombine inside the
channel as shown in Fig. 6.13. This will n!duce the number of free
electrons available for conduction. Therefore the drain current will
~ecrease with increase in negative value of V 05• Thus as - VGS
mcreases, 10 decreases for a constant value of V os·
~ronic Devices & Circults-1 (Eiex.-MU)
....
Q. 27 Draw the drain characterlatlce of D-MOSFET. ·
Dec 03. Dec. 08. Dec. 09 May 10
Ana.:
Fig. 6.15 shows the drain characteristics of a n-cbannel
depletion MOSFET.
Io<mA>
...,..._...;.._______ v- =ov
08
Fig. 6.13: Effect of negative gate to
source voltage on drain current
(B-1C7)
Depletion
mode
'!'be number of ~omb~ation taking place inside the 0 type
cbaDDCI depends on the ~gnitude of negative bias Vos· As we
~ tbe value of negative V GS• the number of reconibi.Dation ·
will increase. This will reduce the number of free electrons in the
n<baJmel available for conduction.
·
.
Tbe higher the negative bias, the more the recombination
and the less is the drain current. This is as shown in the tr.msfer
characteristics of Fig. 6.14. This mode of operation with negative
v6S is called as depletion mode.
Elfect of positive gate to source voltage :
If tbe gate voltage is made positive with respect to source
tbeo the positive Vas will ·attract additional· electrons
(free electrons) from the p-type substrate .due to reverse leakage
CUJieDl
<F·IfilO) Fig. 6.15 : Drain cb~racteristies of an ~-channel
depletion type MOSFET
Q . 28 Draw
symbols of n and
MOSFETs:
p..type
depletion
Ans.:
Gate
(G)
J0 (mA)
. -r-..
·--~--. . Enhencernent
mode
-·
(a) Symbol oro-channel
· (I)) Symbol ofp-channel
depletion type M()SFET
depletion type MOSFET
·················-~·-·········t·········· ·~
Fig. 6.16
·····g· ·········r········ '~
Vas(Volla)---:=::::::::::~--l.--l:t->:--;t--'1--
Gate
Gate
Vp
(G)
(G)
2
(B-1638)
Fig. 6.14 : Transfer characteristics of an n-cbannel
depletion MOSFET
,
'UJmotch out more electrons
These accelerated electrons WI
th drain current will
due to cOllision in the n type channel. Tbusv e This rise in drain
·
'ti VO1tage GS'
lllcrease as we increase the pos• v,e
fore be aware of the·
~t will be very rapi~. We must ~~~~t exceed Io above that.
!llaUmum drain current rating and sbou
.. nbanced" due to the
1'00s the level of free electrons bas bee~e~fore the region of
application of positive gate volta~~· ate voltage is called as
OJleratioo corre""""Aing to the positiVe g
.on between cutoff
..eahancement" ...I:"'
.....
u·on and the regJ
h
.n
region of opera
.
· 0 This is as s own 1
and saturation iS referred to as deplebon regJthaO.t I has a non-linear
. tics show
o
.
Fig. 6.14. The transfer cbaraetenssed thematically llS.
relation with vas· It can be expres
ma
·
I : : I [ 1 -~]
~
(j;-
2
.
...(1)
(a) n-cbannel
(B-1fi42)
(b) p-clwmel
Fig. 6.17: Simplifted circuit symbols for depletion
MOSFETs
Q.29 State appliCations of DMOSFET •
Ana.:
DMOSFET can be used as an amplifier. It can be used as a .
switch.
a. 30 Explain construction of enhancement mode
MOSFET.
Dec. 08. IVlay 09. Dec. 10. ~ 1\.tln rks. 1\lny 11 .
1\lay 12. Dec. 14
D~~;~~~~V;:p~~~:S~h~OC~~~e:y·~s~~~u~a~h~OD~·
------j_----------------------------------------Tbis equation is )mown tbe
1:
:t ~. II
88
~. 11
I II I I 0 II
~
Electronic Devices & Circuits-! (Eiex.-MU
Ans.:
~::2.---v-----~- Electrons ~JIIracted
The basic construction of an n-channel enhancement type
MOSFET is as shown in Fig. 6. J 8. A slab of p-type semiconductor
(silicon) is used as substmte. The substrate is sometimes connected
to the source or it is brought out as the fourth terminal. The drain
and source terminals are connected to the o-type doped regions
through the metallic contacts. The "channel" is absent here. The
insulating Si02 layer is present (similar to depletion MOSFET)
which isolates gate terminal from the substrate: Thus the
construction is very similar to that of the depletion type MOSFET,
but the channel is not present.
(0)
by positive gate
(Induced n-ohannet)
L------It--Region depleted of
p·type earners (holes)
t - - - l - - t - - Holes repelled by
positive gate
m::o:r-----..,__,-·n-l)rpe doped region
(B·l644)·Fig. 6.19:
channel in n-cbannel enhancement MOSFET
Gate(G)
3.
~ (S)
Fig. 6.18 : Construction of n-chaooel enhancement
MOSFET
Q. 31 Write
short . note · W()rking
enhancement type MOSFET.
of
n-channel
,Die.. OB, ·May·n, May·12
Ans.:
The operation can be explained with two different
operating conditions :
1.
Operation with Vcs = 0 volt : If VGs = 0 and a positive
voltage is applied between its drain and source (positive
Vns), then due to the absence of the n-type channel, a zero
drain current will result. This is exactly opposite to what
· happens in the depletion-type MOSFET, where II? = Inss at
Vas=O.
.
2.
Operation when Vcs is positive : In Fig. 6.19, both VGS
and Vos are positive. The positive potential at the gate
terminal will repel the holes present in the p-type substrate
as shown in Fig. 6.19 This results in creation of a depletion
region near the Si02 insulating layer. But the minority
carriers i.e. the electrons in the p-type substrate will be
attracted towards the positive gate terminal and gather near
the .swface of Si02 as shown in Fig. 6.19.' As we increase
the positive Vas• the nutpber of electrons gathering near the
Si02 layer will increase. The electron concentration near
Si02 layer increases to such an extent that it creates an
induced n-channe1 which connects the n-type doped
regions. The drain current then starts flowing through this
induced channel. 1be value of Vas at which this
conduction begins is called as the ''threshold voltage" and
iB indicated by VT or Vos <THr For an n channel EM OSPET the threshoJd voltage is denoted by V.rn whereas
for a p channell!-MOSFET it is denoted by VTP·
e a S V- s 0 Ill f I 0 JI.S
Effect of increase in the drain to source voltage :
In Fig. 6.20, .the positive gate to source ~oltage. V?Sis kept
constant and the drain to source voltage Vas ts mcreased
gradually. Due to this, the gate te~al becomes less and
Jess positive with respect to the draJD. So less number of
electrons are attracted towards gate terminal and the
"induced channel" becomes narrow as shown in Fig. 6.20.
Eventually, the channel width will be reduced to a point of
pinch off i.e. it remains constant and the .saturation region
will be region, which is same as that in a JFET, or
depletion type MOSFET. That means any further increase
in V08 at the fixed value of Vas ·will not affect the value of
In unless breakdown takes place.
n-type dope.dregion
(B-1643)
Formation ofindnced
~1----4-Pinch off (begiMing)
·'+---+------+- Depletion region
(B~t645). Fig. 6.20: Effect of change in vDS a t
fixed V cs on the channel width
Q. 32 Explain characteristics of ·enhancement
mode
MOSFET.
Dec: 03. Dec. 08, May 09. 4 Marks. May ·11.
Ans.:
· · and transfer characteristics of a n· The drain charactenstJcs
channel e~hancement M0SFET are as shown· F
6 21(b) and.
(a) respecttvely.
m tgs. ·
Electronic Devices & Circuits-! (Eiex.·MU)
4-65
The gate current of a MOSFET i!l almost zero. So the
loading oo the source is considerably reduced.
MOSFETs consume very small power. So bau.ery operated
devices like caJculators, watcheb etc. prefer MOSFLITs.
MOSFETs can operate with positive as well as negative
gate to source voltages.
2.
3.
4.
a. 36
Write a short note on : Input protec1Jon In
Ma 04. Dec. 12
MOSFET.
Ans.:
(a) Transfer characteristics
(b) D ram
· ch aracteristics
<F·"') Fig. 6.21 : Characteristics of ...
..0 n-chann
· · e1 e nbancement
MOSFET
The drain current is zero for V Gs s; VTN· For an n-channel
E-MOSFET the threshold voltage is denoted by vTN and for a pchannel E-MOS~
v Th
. . the threshold voltage is denoted byTP.e
tran_s_tier Vcharac~nsticsd shown in Fig. 6.2l(a) is totally in the
posttive os. regton an remains zero till v Gs -- v m· The re1au·on
between drain current and VGS is given by the following equation,
I
=
.
If we increase the gate to source voltage of a MOSFET
above approximately 30 to 100 Volts, then breakdown will occur.
Breakdown means the Si02 layer beneath the gate layer gets
ruptured. This will lead to a permanent damage to the device. The
gate of an ~ represents one plate of its input capacitance (CP).
·The charge introduced at the gate will remain stored on this plate
of the capacitor and will not leak off. Stray electrostatic charge can
easily develop very high voltage on this capacitor which can result
in· the breakdown. It is interesting to und~rstand that a person
walking across a Jab floor is capable of ge!lerating a static voltage
which is as high as 10 kV. under suitable conditions. lf this person
touches the gate of FET then the device will be easily damaged.
0
2
o
k(VGs-Vm)
... (1)
~ere k is a constant and its value depends on the
construction of the device.
a. 33
Draw symbols of enhancement MOSFET :
~
s
s
(F-1627) Fig. 6.24.:
(b) p-channel
(a) n-channel
(B-1649)
Fig. 6.22: Circuit symbols of enhancement type
MOSFETs
G~
G~
(c) n-channel
(B-1650)
(d) p-chaonel
Fig. 6.23 :. Simplified symbols for enhancement
MOSFETs
0.34 State applications of EMOSFET :
Ana.:
Applications of EMOSFET are ,
.
EMOSFET can be used as a linear amplifier.·
As an inverter.
As an active load (in integrator circuits).
I.
2.
3.
4.
~
a.
CMOS inverter. .
In the digital circuits.
.
35 State advantages of f!!OSFET over JFET •
Ana.:
Advantages of MOSFET over JFET are • . .
JFET
l.
MOSFETs have a higher input reststance than
·
ea s v · S O I IIIIOII S
Diode protection circuit for MOSFET
This type of breakdown is avoided by using the d1ode
prot.r.ction circuit as shown in Fig. 6.24. This circuit is constructed
by the manufacturer at the input of the FET.
~i s typically of 250 Q to l.S kQ. 0 1 and 0 2 are acLUally
present, but 0 3 is formed as a result of the fabrication process of
R5• However 0 3 does not contribute in the protection of gate.
Operation of the protection circuit :
. If the input voltage is positive and excessively large, then
0 1 is forward biased and it "clamps the gate voltage to the drain
voltage . Thus the maximum positive gate voltage is restricted to
+ Vg(m:tx) = (V0 + 0.7) Volts
...(1)
If the negative input voltage exceeds a particular value then
0 2 is forward biased and it clamps the gate voltage to the source
voltage. Hence the maximum negative gate vol.tage is restricted to
...(2)
- Vg lmax> = (Vs - 0.7) Volts
Thus the diode protection circuit will protect the MOSFET
from breaking down.
a. 37
Compare MOSFET and FET.
Dec. 09. Lila 10. fJia 11
Ans.:
Sr.
No.
JFET
MOSFET
1.
JFET are of two types,
p-channel
and
nchannel JFETs.
MOSFETs can be of depletion
type or enhancement type.
Electronic Devices & Clrcults-1 (Eiex.-MU)
J'FET
Sr.
MOSFET
,&, ·
2.
3.
4.
The symbols of JFETs
are as follows :
The symbols of MOSFETs are
as follows :
JFETs do not have the
insulated gate.
Input impedance is
lower than that of the
MOSFEI's.
MOSFETs have the insulated
gate structure.
Input impedance is higher than
that of JFET due to the
insulated gate structure.
resistance is
lower than that of a
MOSFEI'.
Drain resistance is higher than
that of a JFET.
Drain
5.
Ana.:
l.
EMOSFET
DMOSfET
Sr.
No. ·
Symbols of enhancement
MOSFET:
Symbols of depletion
MOSFET :
(B-1658)
(B-1657}
2.'
An insulating oxide layer
The insulating oxide layer
(Si02) is present ~tw~n
gate and channel.
is present between gate and
substrate.
3.
n or p type channel is
present.
4.
For an n-channel
DMOSFET, the V Gs can be
negative for depletion
mode and positive for
enhancement mode.
Channel is not present. At
the time of operation, an
induced channel gets
created.
For an n-channel
EMOSFET, V Gs will be
only positive.
5.
For an n-<:hannel
DMOSFET, 10 decreases
For an n-cbannel •
EMOSFET, 10 increases as
as VGS becomes more and
V Gs becomes more and
more negative.
more positive.
For an n-<:hannel
For an n<hannel
DMQSFET,
EMOSFET,
0.38 Give comparison of JFET and 0-MOSFET.
~:
1.
Symbol of n<hannel
Symbol of n-<:hannel
depletion MOSFET :
JFET :
G~
G~
6.
(F-lUS)
2.
The oxide layer is absent
hence gate is not isolated
from the channel.
3.
4.
s.
Drain
current
decreases
The insulating layer of Si02
is present between the gate
and channel.
Drain current· decreases as
negative VGs is increased.
with increase in the
negative V voltage.
Reduction in drain current Reduction in I 0 is due to the
is due to the narrowing of recombination
process
the channel width with taking place under the
influence of negative V
increase in - V GS'
Drain characteristics are Drain characteristics are
drawn
only
for same as those of JFET
except
for
the
part
V GS S 0 volts.
corresponding to positive
Q. 39 Differentiate between enhancement MOSFET and
deptetlon MOSFET.
Dec 03. f>'l<~
t: :t :. V <; II III I Ill II
s
07. M<~ 08. f>'l<t
16. Dec. 16
Currentlvoltege controlled
Voltage
controlled
Ulipolar
device
2.
3.
Unipolar/bipolar device
Symbol :
4.
Input resistance
5.
6.
Noise produoed
Swilching a,...,..
"""""
Q. 41 Explain
difference
P-channel JFET.
Low or
High
Very h9l
moderate
Hi!jl
Lo
w·
Low
Very loW
,Hqt
between
,H~
N-channel
_,
and
UfiiiD
£!ectronlc Devices & Circuits-! (Eiex.-MU)
4-67
Q. 42 Aa a switch JFET 11 preferred over BJT justify·.
Symbol
IDiml
Ana.:
Substrate
Voltage
P type substrate
(F-1581)
·
.JFET as a switch is preferred over BIT due to tbe following
reasons:
l.
~T is a voltage controlled device. So the switching
s1gnal should be a voltage signal. This is easy to implement
in p~tice.
2.
JFET can. switch on and off at a much faster rate than a
BIT.
JFET is less noisy than a BIT.
- JFET turns off very quickly bec;:ause, it is a majority carrier
N type substrate
<F-1581)
polarities and
cwrent
device. So no time is wasted in the recombination process
at the time of tum off.
On state resistance is low.
•
•
.The state change from ohmic to off and vice versa is easier
and faster than the state change from saturation to cut off in
directions
Negative
BIT.
•
.
Positive
Chapter 7 : DC Circuit Analysis of FET Circuit
Which are different methods ·of f:>lasing for JFET · Ans.:
and MOSFET ?
.
l•l44f.j
The given MOSFET is a depletion type MOSFET and the
type of biasing is self biasing. ·
·
Ana.: Fig. 7.1 shows the classification of biasing circuits for JFET
and MOSFETs.
,
.
•
Q.1
Biasing drcuits
I
+
Step 1 : Find IDQ :
+
+
1. Axed bias
1 . Fixed bias
1. Feedback biasing
2. Self bias
Z. Voltage divider
2. Voltage divider
•
For 0-MOSFET
ForJFET
3. Voltage divider
bias
bias
+
•
Io
Q. 2
Which blaslng method cannot be used for
Dec. 09. Dec. 11
D-MOSFET and why ?
Ans. .: The self bias circuit cannot be used for D-MOSFET
because it cannot provide the positive V,GS r~uired for th~
=
loS&[ 1 -
v~:J
2
[
(-2.410 )]
= 8 1-8
biasing
<F-1650) Fig. 7.1 : Classification of biasing circuits
..
..
Io =
.1
8 (8 - 2.4 10 ]
.2
2
8 In =· 64-38.410 + 5.7f> I
2
0
2
Determine following for the circuit shown In
: . .S.16 I~- 46.4 In+ 64 = 0
. I _ 46.4 ± ')/,..<46-.4_,[,.._-4_x_5-.7-6_x_64_
" n .
2 X 5.76
.
= 6.29 mA or In= 1.77 mA
Selecting IDQ = 1.77 mA
Fig. 7.2: (1) loa and V0 so (2) Yo-
Step 2: Find VGSQ: .
operation of a n-channel depletion MOSFET J.D the enhancement
~
Q. 3
Vos .,;· - 10 Rs = - 2.4 10
For E-MOSFET
VOSQ = - 2.4 IDQ =- 2.4 X 1.77 = - 4.24 V
Step 3 : Find vD :
Ioss=BmA
Vp=-6~
· V0
Q. 4
=
...Ans.
•••Ans.
.
V0 n-10 R0 =20-(l.77x6.2)=9.026V...Ans.
State the regions of MOSFET Operation •
Ans.:
Depending on the demand of an application we have to
operate the MOSFET in any one of the following regions of
operation :
·
(F-J97l) Fig. 7.2
I!
a :, V · s 0 I II I
I ll II S
·s... No.
tlon
l.
Cutoff
As an open switch
2.
Saturation
As an amplifier
3.
Ohmic region
As a closed switch
Wrtta short note : DC Load Une of a MOSFET.
Q. 5
Ana.:
The DC load line is helpful in identifying the region of
operation of a MOSFET. Considering the biasing circuit of
Fag.7 .3(a). The drain-source loop of this circuit is shown in
Fig. 7.3(b). Applying KVL to the drain-source loop to wii.te,
Voo
=
:. lo =
IoRo+Vos
l
Voo
-Ro Vos+ Ro
.
. ..(l)
Q.6
Comparing this equation with the equation of a straigh~ line •
y
mx+C
Equation (l) represents a straight line with a slope
l
·
Voo
m
Ro and y-intercept C Ro . ·
Write short note on : Various biasing schemes
used for EMOSFETs.
=
=-
As
Ans. : The biasing circuits used for the enhancement type
MOSFET are as follows :
=
Ro is the de load reSistance, and the slope of the line
· 1.
represented by Equation (l) is inversely proportional to the de load
resistance, this line is known as de load line. The de load line is
plotted on the drain characteristics as shown in Fig. 7.3(c). The two
extreme points A and B on this line (Fig. 7.3(c)) are obtained by
0 respectively into Equation (1).
substituting Vos 0 and 10
=
Hence
=
~rdinates of point "A" .are A (o. ::) and those of "B"
are B {V00, 0)
.
Io .
·. Feedba~k biasing arrangement for enhana:m~nt
MOSFET : This is one of the most popular btasmg
a.rrapgements for the enbance~ent type M<?SFETs. The
feedback biasing arrangement-Is .as shown m Fig. 7.4(a),
· and the de equivalent network is as shown in Fig. 7.~(b).
When we use · feedback biasing for an amplifier the
feedback resistance ~ will connect a pcpt of output signal
back to input. Hence this circuit is called a feedback
biasing. This arrangement is similar to collector to base
biasing in transistor. The resistor~ of Fig. 7.4(a) brings a
suitably large positive voltage to the gate to turn the
MOSFET "on". Due to the presence of Si02 insulating
layer, the input impedance is very large. Hence Io 0 mA
and V RG 0 Volts. Therefore the drain (D) and gate (G) are
· equipotential points.
i.e.V0
·v 0 and Vns=Vos
...(l)
Therefore, a direct connection (short link) appears between
drain and source terminals as shown in Fig. 7.4(b).
=
=
=
+Voo
(a) Given biasing circuit
(b) Drain source loop
<F-134) Fig. 7.3
The Q-point and transition points also are plotted on the
DC load line as shown in Fig. 7.3(c). The dotted curve corresponds
to the V DS(aal) curve .and the point of intersection of this curve with
de Load line is called as the transition point. The transition point
separates the saturation and non-saturation ·regions as shown in
Fig. 7.3(c). The three regions marked on the load l.ine are as
follows:
Cut off
2. Saturation
3.
Non saturation.
1.
If the gate 10 source voltage V0 s is less than VT• the
MOSFET is in the cut off region.
(a) Feedback biasing
arrangement
The other most popular biasing arrange ment for the
enhancement type MOSFET is voltage divider biasing as
shown in Fig. 7.5.
Analysis of voltage divider biasing circuit :
Obtain the expression for VG :
As Io
Sll llll
IIIIS
the feedback biasing
arrangement
(F-136) Fig. 7.4
2. Voltage divider biasing for enhancement type MOSFET :
Step 1 :
(;;tS
(b) DC equivalent network of
=0, referring to circuit of Fag. 7 .S ,
.
£ectronic Devices & Clrcuits-1 (EiexA-AU)
Step 2 : Calculate IDQ :
...(2)
SteP 2 :
'
Obtain expression for vcs :
=
Vas
ApPlying cbe KVL to the loop shown by thevarrow i~ Fig. 7.5
+Db
Va - Ir>Q Rs=~XVoo - IDQRs
6.8
'
:. Vas= 10 + 6.8 x24 - 0.751DQ=9.7 - 0.75IDQ .
r----..
=
=
:. IDQ
:. IDQ
2
k [Vos - VOSCI'hl]
.
...(1)
=0.55 [9.7 - 0.75 IDQ - 3]
0.55 [6.7- 0.75 IDQ]
2
2
: . 1.82IDQ = 0.56 ?OQ - 10 IOQ + 44.89
2
:. 0.56 I DQ- 11.82 IDQ + 44.89 = 0
11.82 ±yr(l-l-.8-2)....,2---4-x-:-0-:.56-=-x -:-44:-:.8::::9
" IDQ =
2 X 0.56
·····r··
Vo
R2
.....!.....
(F-139) Fig. 7 .S:
But Is =Jn
Step 3 :
VG
VG
:. VGs
··
1
.. IDQ =
1. 8~-~26·26 =1~.14 mA or 4.96 mA
IDQ = 16.14 mA will result in neg~ve V0 SQ
:. · Selecting IDQ
4.96 mA
=
Step 3 : Calculate V0 and Vs :
Voltage divider biasing for a n-cbannel
~nhancement MOSFET
.
=
Vas + VRS =VGs +Is Rs
=· VGS + lo Rs
= Va-I~Rs
V0
=
=
V5
=
...(3) ·
Q, 8
...(4)
V00 -IDQ R0 =24 -(4.96 x2.2)
13.088 Volts
IDQ R5 = 4.96 x 0.75 = 3.72 Volts
In the circuit shown In Fig. 7.7, find value of Ro H
V050
Calculate IDQ :
...Ans.
=3V .
.
Transistor data:· Vm
·
=1 Volt, 1<n = 160 J.IA I Y
..
loQ =
,.~m·a~.,,..,
k (Vas- VGs(Tht
In this expression substituting V GS obtained in Step 2 and
the values of k and Vas (Th) to ob~ the value-of IDQ.
Step 4 :
Obtain the expression for VDSQ :
Considering the output side of Fig. 7.5, applying KVL to
this side to write,
Voo
IoRo+Vos +VRS
.
= 10 R0 + Vos + 10 Rs =Vos +Io <Ro + Rs) ·
· V
= . VDO - .I0 (R0. + R, S )
...(5)
••
OS
0.7
(F-t73)Fig. 7.7
·
A~s.:
.
N2
Given:Vrn = 1 Volt, k;,=l60~
To find :
R~, V os
10Mn
Step I : Calculate Vcs:
2
IOQ = k(Vos- VT)
2
6
160 X 10- 6 = 160 X 10- (VG5 -1 )
160x10~
2
(VGS- l) ·= 160 X 1006
6.8MO
..
(F-4718)
Fig.7.6
:. V GS
= l :. Vas= 1 + 1 =2V
1
=
Yoso ,;, Voo """ IOQ Ro
Ana. :
3
Step I : Obtain k :
k
<Vas-1)2
=
=
:. Ro
(VGS (oo) - V GS (Th)J
5 rnA -0.55 mAJVz
[6 - 3] i
Cti S IJ · 'i iiiiiiiiiii S
Q.9
=
=
Yoo- Voso
IOQ
5 - I~R0
5 - 3 = l2.51dl
160 X 10=6
... Ans.
Write a note on the following : NMOS driver with
enhancement load.
,_
Electronic Devices & Clrcults-1 (Eiex.-MU)
Ana.:
VOS (Ill)
V
If an enhancement load device is connected as a load with
another M<?SFET as shown in Fig. 7.8, then the circuit can be used
~ ~ ~lifier or as an inverter in the digital logic circuit. In the
~~tt di~ of Fig. 7.8 . MOSFET M1 is the load device which
ts biased m saturation and MOSFET Mz operates the driver
MOSFET which operates either in saturation or noosaturation.
05
=
=
V -V ==0 -VT=--VT
OS
T
b
. .
0 becaUse gate and source are s ort crrcwted.
•.. ~~<~~·· · · r··· ···r·····r ····· · ·-··· ·-····· ·······-········· ··-····-. ......
!·-·-· .......L.-...J......i , vDS(.., -.vos- Vr•-Vr
E:~J=li~:dJ)j'
1
~ i : ~ ~ ~ i ~ t t
.·-o
'
i v n~
L ........L. . .vOS(aat) .. "'!........';. _...1L ...J....
OS\·alta)
+Voo
·....-----....... ~ lo1
Load
.(a) A depletion
(b) Output cbaraderistics 8Dd
NMOS with gate
source connected together
<F-163) Fig. 7.9
Vos2
(F-161) Fig. 7.8.:
Driver
NMOS driver with enhancement load '
Considering the circuit shown. in Fig. 7.10 in which the DMOSFET is used as a depletion load device. .The D-MOSFEr can
be biased in the saturation or non satlll'ation regions, depending on
the parameter values ~d V00 and R5 • The D-MOSFET.biased in
. this manner can be used as a resistor. It can replace resistors in the
M:OSFET integrated circuits.
Expression for the transition point :
The 1raosition point is the point that separates the non
saturation and saturation regions of a MOSFET. The expression for
the transition point of the driver MOSFET Mz in Fig. 7.8.
Vos2(at)
=
Vos2- Vn
Q.10 Write a note on the following: Depletion MOSFET
as load device.
Ans.:-'
Fig. 7.9(a) shows a 1)-MOSFET with ·its gate and source
terminals connected together. Fig. 7.9(b) . shows the drain
<F-164)Fig. 7.10: A depletion load device
characteristics of this device.
The D-MOSFET can be biased in the saturation or non
saturation regions. The transition pOint is shown in Fig. 7.9(b). The
threshold voltage VT of an n-cbannel D-MOSFET is negative.
Hence VDS <at>will be positive because, .
·
Chapter 8 : Small Signal·Analysis of FET Amplifiers
Q. 1
What are the three basic conflgur,aflons of
MOSFET amplifiers ?
Ana.:
Fig. 8.l(a) shows a typical ·cs amplifier. The input and
output voltage waveforms are ·180° out of phaSe with respect to
each other. The voltage divider biasing (VDB) is used for biasing
the MOSFET in saturation region.
.
The MOSFET is a three terminal device. Depending on
which terminal is used as signal ground. there are three basic
configurations of the MOSFET amplifiers as :
1.
Common souice configuration.
2.
CollllllPn gate amplifier.
3.
Common drain configuration (source follower).
Q. 2
Wrtte a short note on ~e following : CS MOSFET
amplifier
Ana.: In cs MOSFET ampUtler configuration , the source (S)
terminal acts as the common terminal for input as well as output.
· The input signal is applied at the gate <<:J> tenninal wi!h
respect to source and the llJllplified output is obtatned at the drain
(D) with respect to source.
e a :. v - s n11111 1111 s
(a) CS MOSFET ampllfter (b) Input outpu' waveforms
(F..c852) Fig. 8.1
r
~ Devices & Ciroultf-1 (Eiex.-MU)
4-71
API"~:
1be CS amplifiers Q.U find applications In the
1.
As a pre-amplifier.
- .
fullowtng areas:
As a voltage amplifier.
[n tbe radio and TV amplifier circuits
fNCU"M of CS •mplthr :
·
1.
H'lgb voltage gain.
2.
3.
:z..
LowR.,
3.
4..
Out of phase input and output.
0
Modentely high ~n
0. 3
Write • ahort note on the foil
·
tmptlfter.
owing :CD MOSFET
''"•MI
Ana.: .
The CD configuration of MOSFET
·
· .
cbe CC or emitte£ follower conh~·-tt'
ampflifier ts sunilar to
2(
'"6~... on o a BIT amplifi
sbown tn
. • a). 'lbe input voltage is ap lied
er, as
output is
from the
.
P
to the gate and
..:-it, tbe drain (D) ·
soun-:e termmal. In the ac equivalent
...._.
ts connected to ground Th .
ac voltages are measured with
· . us ~put and output
·
respect to drain terminal Hence the
DIPIC ~ dmin (CD)_amplifier. The voltage divid~r biasing is
used
to bias tbe MOSFET m the saturation reaion Th ·
_........,_
wavefonns
b
.
o- •
e mput output
..~._"'
. are ass own m Fig. 8.2(b). They are in phase
wttb each ocber With voltage gain less than 1.
(a) CG MOSFET ampUfle~
. ';!t!
+Voo
..---+
•
(F-4854) Fig. 8.3
(b) Input output
waveforms ·
.
The voltage divider biasing is used to bias the MOSFET in
the saturation region: The input and output waveforms are ·as
shown _in Fig. ·8.3(b) which shows that they are in phase with each
other. CG amplifier is a wideband amplifier. It has a large
bandwidth.
Features of CG amplifier :
1.
· FJigh voltage gain (Av > 1)
2.
High output resistance.
3.
Low input resistance.
· 4.
It has large bandwidth.
5.
No phase shift between input and output
·Applicatf~n:
.
In the high frequency (RF) amplifiers.
Q. 5
(a) CD or source follower
Coofiguration
(b) Input output waveforms
Compare the three amplifier configurations of
MOSFET amplifiers.
Ans.: Comparison of MOSFET amplifier configurations :
(F~) Fig. 8.2
Feelurea of CD amplifier
l.
Low voltage gain (Av < 1).
2.
Very high input resistance
3.
Very low output resistance.
4.
lao pbase shift between input and output voltages.
. 2. ·
Gate
3.
Drain
Gate
Sowce
Low
Low
Source
Drain
4.
AppHcatlone
1.
As the output amplifier stage.
0. 4
Wrtte a
2.
As a buffer.
•hort note on the following : CG MOSFET
amplifier.
Ana.:
The Common Gate (CG) MOSFET amplifier is as shoW? in
Pig. 8.3(a). The input signal is applied to the Sour~ (S) ~nmnal
with respect k, the Gate (G) and the output voltage 1s obtruned at
tbe ~=- .(D) . ..a.
pect to n<>t~. Thus all the voltages are
•.~uw.t
WJ.w res
&-.
. a1 He
the name
measured witb respect to the Gate (9) tetmJD · nee
Common Gate (CG) ampJjfier.
1: ;; •. II
'• H I II I I II II '>
5.
6.
7.
Q. 6
Output resistance
Draw and explain small signal equivalent circuit
of CS amplifier with voltage divider blas.18@jl0i
Ana. : The basic CS amplifier using MOSFBT (n channel) is
shown in Fig. 8.4.The type of biasing circuit used here is the
voltage divider biasing. 'Resistors R 1 and~ will bias the MOSFET
in its satumtion region.
Eleclronlc Oevioes & Cfrcults-1 (Eiex.-MU)
Ana. : PBrt I : DC •n•lyala
+tOV
Step l : Calculate V<:80 :
V
• y _ y9 • v0
0.
OSQ
, y
..
•
OSQ
R:2
R, + ~
slnce V11 • 0
O
x 5 V • 20: 30 X 5 2 Volts
...
=
Step l : Calculate 100 :
1
IOQ
K(YosQ - V,i= tOO x 10...(1(2 - 1)
=
... lr>Q = 100 J1A
Step 3 : Calculate &n and r 0
8m = 2K(Vos - VT)
:
= 2x l00 X l0- 6 (2 - 1) =200 ~A/V
r0
<F-IIU) ttlg.. 8.4 :
CS am.plUitr with voltage dlvtder biasing
SIMI 8lgnal equtwient circuit :
=
'I
[11. IDQ)
Since A. is not given, assuming that it is equal to zero.
r0 =
..
oo
Part II : AC analysis
Step 1 : Draw the smaU signal equivalent clrcult :
v0
Input resistance :
=
..
Rtll~
+
•
Av
But V0
= v;v..
= Voltage across (r II Ro)
= - &. V p (ro II Ro>
...(2)
0
:. V o
aodVP
=
.. Av
V1 -
ro
Vo
V85
= - gm (Ro II RJ
3
)
= - 200 X 10 -6 X (20 X103 X 47 X 10
3
=-
.(20 + 47) X 10
2.8
...Ans.
Step3: ~and Ra:
R;
= - &. (ro II Ro> •~ + R; X V 1n
vo - ~·R;
:. Av = V itJ =<R,. + R;) · (ro II Ro)
R; = Rtll ~ =20 k 1130 k
:. Vo
Q. 7
=
.
R;
R.;+R; x vin
Om VIlli
(F-1~ Fig. 8.7 : Small signal equivalent circuit
Step 2 : Voltage gain:
vo-- 8.n vg. (Ro II RL)
Av
Vollage gain :
+
@
Vgt
RtiiR2
... (1)
ld
. ......
@
RL
R;
- 1
For the amplifier circuit shown In Fig. 8.6, .derive
the e..,...aons for Ay, R1 and R0 • Compare this
amplifier with C.E. amplifier.
I•J4Me1Cj
+6V
Ro
... (3)
Q. 8
Ans. :
=
k
Ro II RL =20 1147 k -
20
30
5~ = 12 k.Q
20 47
;,
= 14 kQ
...Ans.
...Ans.
~or the circuit shown In Fig. 8.8 ,Find Ay, R1 and
o·
·'fflh"l'
•
30V
47k
VGS(Itl) ,., 3V'
-3
K•0.4 x 10
rd•40k0
O"·Wf>
f• . 1 . 0
·. o I II I I
f1a. 8.6: Glvea amplUier
It II ~.
CC-4816) Ftg.8.8
..
Electronic Devices & Circuits-! (Eiex.-MU)
4-73
Ant· :
= - 1.33 (40 k 113.3 k) =- 1.33 [ : : ~:~]
pert 1: DC analyala :
= - 4.054
S#P 1 : Find VGSQ :
..
VGSQ = Vo- Vs = Vo -lDQ R5
~
and Yo= R I +R2 x Voo
Step 4 : CakuJate R. :
Av
= (rd II R0 ) =40 k IIJ.3 k
= 3.048 k.Q
R0
10
= 40 + 10 X 30 = 6 V
Q. 9
••.Ans.
••.Ans.
For the given E-MOSFET amplifier, determine
I®GiiiOj
R., Av and R0 • Refer Fig. 8.1 0.
.. VGSQ= (6-1.21~
Step 2 : Find IDQ :
= K(VGSQ -VT)2
= 0.4 [6- 1.2 IDQ - 3]2
2
IDQ = 0.4 [3 - 1.2 IDQ1
.
2
IDQ = 0.4 [9 - .7.2 IDQ + 1.44 ~ ]
2
1.44 ~ -9.7 IDQ +9 = 0
IDQ
..
··~
Solving the quadratic equation to get,
2
IDQ
=
-9.7 ±y(- 9.7) - (4 X 1.44 X 9)
2 X 1.44
=
5:62 mA or 1.11 mA
Selecting IDQ
:. VGSQ
=
=
VGS(Th) = 3V,
(B-2648)
1.11 mA
6 - (1.2 X 1.11) = 4.668 V
g, = · 2K(VosQ:....vT)
2 X 0.4 (4.668- 3)
VGS(ON) =&I
Fig. 8.10
Ans...:
Given·:VGS (Th) = 3 V, Io(on) = 5 mA, VGS (on)= 6 V
Type of circuit :
E-MOSFET CS amplifier.
To find : . }\, A v, R0 •
Step 3 : Find &u :
=
IO(ON). = 5mA,
=1.33 mAN
DC AnalysiS :
Part 2 : AC analysis _
;
Step .1 : Draw the DC equivalent circuit :
Step 1 : Draw the small signal equivalent circuit :
The DC equivalent circuit is shown in Fig. 8.11.
Step 2 ; Calculate value of K :
@
(C-4828) Fig.
S.9: AC equival~nt circuit
Sttp 2 : CalcuJate llt :
R;
= R 1 11 Rz =40 111°
=
40X 10 -S MO
so -
.•.Ans.
(B-2651)
Fig. 8.11
S&ep 3 : Calculate Av :
Av
But V0
v
v0
.
= V io But V in =V GS
= Voltage across (rd II Ro)
= - g, V GS (rd II Ro)
:. ~ = - 8m (rd II Ro)
OS
I!:J~>IJ - !;O IIII IO IIS
Step 3 : Calculate VGSQ :
VosQ
=
Vo - Vs
y 0 = Rl ~ Rz x V00 = lO } 6 .8 x 24 = 9.71 Volts
6
Vs = IDQ Rs=0.75IDQ
:. VosQ = (9.71- 0.75 I~
Electronic Devloee & Circuita-l (Elex.-MU) V
Sttp • : Calaalate lOQ :
=
K (VGSQ - V~ ('11\/"' 2.5[9.71 - 0.7S IDQ - 3]
2.5 [6.7 l - 0.7S IDQ12
•
2.5 [45 - 10 too +0.56 ~]
+Voo
1
ioQ "'
· · loQ • 112.5 -
2
2S I1lQ + 1.4 IOQ
1
:. 1.4~ - 26 1{)Q+ll2.5
=
0
Solving we get,
loo = 26 ±:Jr-<2-6-.)2--....(4_x_l-.4-.x-11-2.-5) _ 26 ± 6.78
2 X 1.4
..
=
~
11.7 mA
Discard
2.8
or 6.86 mA
too =
11.7 mA because it produces a
(F-1826} Fig. 8.13
negative V 05 ·
So selecting I~
...
:.
=
=
=
l{)Q
VGSQ
: Source follower amplifier
6.86 mA
6.86 mA
9.71-0.75x6.86=4.57Volts
Step S : Cakalate g., r • :
&..
r0
=
=
2 K (VGSQ- VTn)
[A ~~-
1
=
=2 x 2.5 (4.57- 3) = 7.85 mA!V
oo
AC..tysls:
Fig. 8.14: AC equivalent circuit
SIJep 1 ~ Draw small signal (!quivalent circuit :
Fig. 8.15 shows the small signal equivalent circuit.
Rsl
· -- ---1......-----o
(8-:wl) F1g. 8.12 :
..
, <F-1827) Fig. 8.15 : Small sigDal equivalent circuit
. Expression for voltage gain (Av) :
.
Small signal equivalent
Av =
v o -~ID va Rll
=-g;,RD .
vgs
VID
=
Av
= - 7.85 X 2.2
=
R 1 11~= 10.MOII6.8Mn
=
4.05Mn
=
vo =
vio =
But Vo
=-17.27
:.
•••Ans.
and
Q. 10 Anetyze the CD MOSFET a.mpllfler ualng Ita amall
.. v.. =
.tgnal equivalent circuit.
But V
AM.:
lrJ CD MOSPET amplifier • tbe input is applied to the gate
IIDd output is obtained at tbe source. The source follower amplifier
usiog MOSPE'f islbown in Pig, 8.13.
.
Tbe .-c equivalent circuit i1 shown in Pig. 8.14. In the ac
tJqu.ivaleol cl.rcuit tbe diJin gets connected to ground and all the
volrages are measured with respect to tbe drain. Hence the circuit is
c.a1led u common drain circuit.
' II Ill I I II II '•
~
V;
Voltage across (r0 11 Rg)
gm vgs (ro II Rs)
vss
+Yo
... (1)
... (2)
vgs + gm v gs (ro II Rs) =v 8S [1 + 8m (ro II Rs)]
...Ans.
t· ,, · 'J
.
~......---1----~-~ .
Av
R•
v
vio
... (3)
-~X V1
io- Ra~+~
.. v =
11
(R/(Rli +~)]VI
1 + &m(roll Rs)
Substituting this into expression for V0 to get,
V :; + &m [Ri I (Rt + Ra~)J V1(r0 II Rg)
9
1 + g, (ro II Rs)
... (4)
4-75
eteetronic Devices & Circuits-! (Eiex.-MU)
Vo + 8m lR/<Rt + ~)] (ro II Rs>
:. Av = V;
1 + &m (ro II Rs>
= + g, (ro II Rs> [ R;_1
1 + g, (ro II Rs> R;+'RJ
.......-
Ana.:
Part I : DC analysis
... (5)
Step 1 : Expression for VGSQ :
VGSQ =
'Ibis is the required expression.
Input resistance (R.) :
V0
V5 =V0 -IDQRs
-
~
460
and V0 = R +~ x V00 : 160 + 460 x 12=8.9Volts
R; = <R.II~
output resistance (RJ :
... (6)
R~ucing V; to zero. The equivalent circuit to calculate o
is sboWD m Fig. 8.16. .
·'D
'
=
05
i
2
3
= 4 X 10- [ 7.42-680 IDQ]
3
.
2
= 4 x 10- [55- 10091.2 IDQ + 462400 IDQ]
Nodi A
lo
..... . ...
1
:. VGSQ
(8.9- 680 I~
Step 2 : Cakulate IDQ :
3
IDQ . = K (V Q- Vi=4 x 10- [ (8.9-680IDQ-I.48)
+
..
I~ = 1849.61~ - 40.36 IDQ + 0.22
2
2
. . 1849.6 IDQ
- 41.36 IDQ
+ 0_.22 = 0
~~~------------~--2
41.36 ±y(- 41.36) - (4 X 1849.6 X 0.22)
. ' IDQ =
2 X 1849.6
<F-1828) Fig. 8.16: Circuit to obtain
=
R.
Selecting
Assuming that a voltage source of V 0 volts has been
the current supplied by
this source is ~· Then,
connected between the output source and
~
=
lr
0
0
·will be connected to drain.
:. v, = - v 'Ml =- v 0
~=10
:. ~ =
Av
• [
g,.,+:o
=
J
f
=11.467 ill
118.7 ill
...Ans.
8m (ro II R,) [ R; J
= 1 + g, (ro II Rs) ~ + RJ
c
1
1
3
Step 2 : Voltage gain :
vo[t+~ +gm Vo = vo[g,.,+t+~J
vn-
"
10-~= 297 Volts
Part II : AC analysis
Step 1 : Input resistance :
160 x 460
R1 = R 1 liR2 - 460 + l60
= l,+IRS
= V /r and IRS=VJRs
= vo[t+~
As the current flowing through Rsi and (R1 II ~ is zero, the
voltage drop across it will also be equal to zero. Hence gate (G)
=
=
=
lo+g,.,Vss
.. 10
v
Step 3 : Cakulate GSQ :
VGSQ
(8.9-680 x 8.72 x
and r0 = (A~~- 1 = (0.01 X 8.72 X 10-
Applying KCL at node A to get,
:. lo+8m v ..
=
Step 4 : Cakulate g, and r • :
8m = 2K (VGSQ- VT) 2 X 4 (2.97 - 1.48) = 11.92 mA/V.
Vo/Io
But
13.64 mA or 8.72 mA
.·
IDQ
8.72 mA as the other value yields
a negative VosQ
11.92 (11.467 11 o.68) [
118.7 ]
1+ 11.92 (11.467 11 o.68)· 10 + 118.7
11.92 X 0.6419
1+ (1 1.92 X 0.6419) X 0.9222
=0.8156
_.Am.
Step3:0u~ut~:
+~J
7
... < >
-:l II Rs II ro·
8m
This is the required expression for Ro·
0.11 For the source follower circuit shown In Flg.8.17.
calculate the small signal voltage gain, Input
resistance and output ntSistance.
+12V
~ =0.01
·1
v
2
1
'
1
Ro = &m llroiiRs 1 1.92 X 10-J 0IL467kll0.68k
:. R0 = (83.89 k 1111.467 k II 0.68 k) = (10.08 k II 0.68 k)
:. R0 = 0.63702 ill= 637.02 Q
...Ans.
Q. 12 For the CG ampiHier shown In Fig. 8.18, calculate
the voltage gain Av, R1 and
parameters are VT
=1V, K =
R0 • The MOSFET
1mAI'I and A 0.
=
Also calculate the output voltage H the Input
voltage Is 100 sin mt mV.
• K=4mAIV
VT= 1.48V
. 1--r-:··
CGfio
3.9k.
~f\"'~
+5V
(F.tm>Fig. 8.17: Given
e a s v-s nluJJun s
source follower
(F-1834) Fig. 8.18:
Given CG ampllfter
4-76
'
Electronic Devices & Clroults-1 (Eiex.-MU)
Calculate Av :
Step 2 :
Ana. :
Part I : DC Anelyal8
=
Av
Step 1 : Calculate v GSQ :
=
=
Step 2 :
vo
... (1)
2.095 Volts
Calculate g., :
=
=
R0
... (2)
2.l9m.AIV
2.19 X 2.642 =1.8144
1 + 2.19
Av x y 1
=1.8144 x 100 sin w t m V
sin w t m V
= 181.44
,
Output resistance :
Step 4 :
= 2K (VGSQ- VT) = 2 X 1 (2.095- 1)
&.,
1 + gm R~l
Output voltage :
Step3:
:. VGSQ
p.9ll8.2}
am<Roll RJ = 2.J)+9(2.J9
X 1)
=
Ro II RL
=3.9 ldlll
8.2 ldl =2.642 ldl
•••Ans.
Part II : AC Analysis
Calculate~
Step 1 :
l
R
. -; -8m
:
1
2 19
X
l0-3
456.4 n·
...Ans.
Chapter 9 : Special Semiconductor Devices-1
Q. 1
Write short note on : Zener diode : Principle.
Dec.02. Dec.OB
Ans. : "Zener diode" is a special type of p-n junction
semiconductor diode. Its construction is similar to that of .a
cooventi.onal p-n junction diode. However in constrUcting the
zeoer diodes, the reverse breakdown voltage is adjusted precisely
between 3 V to 200 V.
Its applications are based on this principle hence zener
_
diode is called as a breakdown diode.
The doping level of the impurity added to manufacture the
zeoer diodes is controlled in order to adjust the precise value of
breakdown voltage.
Q. 2
Clear1y describe the phenomenon which governs
Dec. 02. Dec. OB
the working of zener diode.
Reverse biasing of zener diode :
When the cathode is connected to the positive terminal and
anode is connected.to the negative terminal of the de source, the
zener diode is said to be reverse biased. The operation of zener
diode in the reverse biased condition is substantially different from
. that of a diode. The reverse biasing of a zener diode is shown in
Fig. 9.l(c). Zener diode in the reverse biased condition is used as a
voltage regulator.
Q.
3
Write short note on
characteristics.
:
Zener
diode
VII
Dec. ·oa. Dec. 16
Ans.:
Ans.:
The cin:nit symbol of a zener diode is as shown in
Fig. 9.l(a). It is a two terminal device and the terminals are anode
and cathode. The arrowhead in the symbol points towards the
cooventional direction of current through the zener diode, when it
is forward biased
The V-1 characteris~cs of a zener diode can be divided into
two parts:
·
1.
Forward characteristics
2.
Reverse characteristics
J
Calhode
•
The forward biased zener diode behaves identical to a
forward biased diode. The forward biasing of a zener diode is
shown in Fig. 9.l(b). The zener diode is generally not used in the
forward biased condition.
·
rn:-~
,~
-
V-
Anode
IF
;
............/
rn
Curmnt limiting mslslor
v
.
T+
Vz
.L
(a) Circuit
(b) Forward
(c) Reverse biasing of
symbol of a
biasing of a zener
a zener diode
zeaerdiode
diode
(e-42)Fig. 9.1
The forward characteristics of a zener diode is shown in
·
: CircuJt syinbol and biasing of a zener diode
Forward bluing of zener diode :
Wben the anode of the zener diode is connected to the
positive terminal of tbe de sour~ ~~ the. cathode is conne~ted to
tbe negative terminal, the zener diode IS swd to be forward btased.
P.
Forward characteristics :
~ig. ~.2. I~ is almost identical to the forward characteristics of a p-n
JUnction dtode.
Reverse characteristics :
.
The reverse characteristics of a zener diode is substantially
dtfferent from that of the p-n junction diode. As we increase the
reverse voltage, initially a small reverse saturation current "I "
which is in !AA will flow. This current flows due' to the thermallY
generated · ' t
·
mmon Y earners. At a certain value of reverse voltage,
!he_rev_erse current will increase suddenly and sharply. This is an
mdicati~n that the breakdown bas occurred. This breakdown
voltage ts called as zener breakdown voltage or zeoer voltage
and it is denoted by V•• The value of V can be precisely
c_ontrolled by controlling the doping levels ofp ~d n regions at the
time of manufacturing a zener diode. After breakdown has
occurred, the voltage across zener diode remains constant equal to
a s 11 •, IIIII I JIJ II !i
....
3ectronic Devices & Circuits· I (Eiex. ·MU)
4·77
v•. Any increase in the source vo.ltage will result in the increase in
atoms and impart some of the kinetic energy to the valence
reverse zeoer current. The zener curre
electrons present in the covalent bonds.
bfeakdown must be controlled b con
. nt aft?r the . reverse .
with the zener diode. This is es~nlinln:J~ng.: reststor R to series
Due to this additionally acquired energy, these valence
device due to excessive beating.
vot any damage to the electrons will break their covalent bonds and jump into the
conduction bond to become free for conduction. These newly
Region end Its Importance :
generated free electrons will get accelerated. They will knock out
After reverse breakdown, the zener di
.
·some more valence electrons by means of collision. This
region called zener region, as shown in Fig 9 2odie tho~rat~s m a
· ·b · t n IS reg10o the phenomenon is called as "carrier multiplication".
voltage across zener diode remains constant
In 11 very short time, a large number of free minority
~.,.A;nn on the su 1 v 1
U current changes
~·......'6 • •
.PP y o tage. Zener diode is operated in this electrons and holes will be available for conduction, and the carrier
regton when tt IS bemg used as n voltage re 1
.
multiplication process becomes self sustained. This self sustained
V-1 characteristics is as shown in Fig. 9.2. gu ator. The complete
·multiplication is called "Avalanche Effect". A large reverse current
Forward current
· starts flowing through the zener diode and the avalanche
breakdown is said to have occurred.
8l'ellkdoWn YOiage
A current limiting resistor should be connected in series
with the zener diode to protect it against the damage due to
v.
~ 11011age •-"t--------}ro---i(-~F~o:rw~
ard vol1age
excessive heating. The breakdown voltage in the avalanche
l
J
breakdown increases with increase in the junction temperature. The
·,~ 1......................: ::::::0
,
. Zmln. .
Cut In vol1age
V-I
characteristics in the reverse biased region with. avalanche
Knee point
breakdown is shown in Fig. 9.3(b), which shows that the
Zene( >
region
characteristics bas a gradually increasing nat.ure.
zener
!
T
....
1 . . . . . . . . . . .... .........
Jzmax.
. -- - - BI1MII<down vcll!lga - - - - - .
Reverse current
(B-44)Fig. 9.2: V-I characteristics ofa zener diode
Q. 4
Write short note • on : Avalanche · and zener
breakdown mechanism.
-I
Dec. 03 May 06. May 07. May 16
Ans. : In zener diode, there are two different -breakdown
mechanisms. 1bey are :
1.
1.
2·
(a) Zener breakdown
(b) Avalanche breakdown
. <B-4')Fig. 9.3
Zener breakdown
2.
Avalanche breatdown
Q . 5 pifferentiate between zener and avalanche
Zener breakdown : The zener breakdown is observed in
the zener diodes having Vz less than·5 V or betw~n 5 to 8
breakdown.
Volts. When a reverse voltage (5 V or less) is applied to a
Ans.:
zener diode, it causes a very intense electric field to appear
across a narrow depletion region. This intense electric field
is strong enough to pull some of the valence electrons into
This is observed in zener
This is observed in zener.
the conduction band by breaking their covalent bonds.
diodes
having V z between
diodes having V z greater
These electrons. then become free electrons which are
5
to
8
Volts.
than 8 Volts.
available for conduction. · .
A large number of such free electrons will constitute a
2.
The valence electrons are
The valence electrons are
large reverse current through the ·zener diod: and
pulled into conduction
pushed into conduction
band due to very intense
breakdown is said to · have occurred due to the Zener
band due to the energy
electric field appearing
imparted by colliding
effect". A current limiting resistance should.be co~ected
across the narrow
accelerated ~ority
in series with the zener diode to protect tt agamst the .
carriers.
damage due to excessive heating. In zener bn!akdown, the
bieakdown voltage depends on the tempe~~ of P:n
3.. V-I characteristics with
The V-I characteristics
junction. The breakdown voltage decreases WI~ l.ncr~ase m.
the zen~r breakdown is
with the avalanche
the J·unction temperature. The V-I charactenstt.cs m the
very sharp.
breakdown increases
·
. .
· p·g 9 3(a) whtch shows
reverse biased regton IS shown m 1 · • •
· h
gradually.- It is not as
that the characteristics after breakdown IS very s arp,
sharp as that with the
zener breakdown.
almost vertical.
·
1 b
in Zener Diodes : The ava anc e
Avalanche Breakdown .
· diodes having Vz
The breakdown voltage
The breakdown voltage
4.
breakdown is observed to the zener .
f breakdown
decreases with increase in
increases with increase in
higher than 8 V. Even though the mechamsm odiode In the
has cbangi.d. the device is still called ~ zene~ll tak~ place
~: ·
the c.onduetton WI
Q, 6 Give comperlaon of zener diode and p-n )unction
reverse biased conwtton,
.
As we increase the
·
' t earners
diode
only due to the mmon Y
· d' -~A these minority
'ed to the zener IVIW•
l
rev~ voltage app J
te Therefore the kinetic energy
earners teod to accele~ ·
. While travelling. these
6
associated with them ~re~ · llide with the stationary
accelerated minority earners WI co
11
.
Electronic Devices & Circuits-! (Eiex.-MU)
~
Ans.:
1.
· p-njonetion diode
3.
4.
Zener diode
Ans.:
Symbol :
(B-47)
Symbol :
1>1~'1----oo K A o
Ao
2.
lain the principle of operation • of varactor
Exp
diode·
Q. 9
Sr.
No.
This is operated in the
forward biased condition.
V-1 characteristics: Refer
Fig. A
(B-48)
~:Mf----0 K
Zener is operated in the
reverse biased condition.
V-I characteristics: Refer
Fig.B
Applications of zener
diode is in voltage
regulators. voltage limiters
Applications of p-n
junction diodes are in the
rectifiers, clippers,
clampers, voltage.
multipliers.
etc.
Forward current (mA)
Forward
characteristics
The varactor diode is basicall~ a p-n junction_ diode which
ted in the reverse biased regton. The two stdes of a p-n
.
~s o~ra will act as the conducting plates and the depletion region
JUDCbOn
· between tbem to fionn the
the dielectric matenal
behaves as
·
r Thi · h
junction capacitance or transition ca~cttance '-T'
s. ts s own in
Fig. 9.5. This is the principle of operabon o~ varactor diod~.
Thus the transition capacitance extsts at the p-n Junction.
The transition capacitance C,. of a p-njunction diode is given by,
c,.
= e
A
wd
...(I)
where, A = Area of the p-n junction area.
and Wd = Width of the depletion region.
As the reverse voltage increases, the width of depletion
region incre.ases. This will reduce the transition capacitance C,..
The characteristics of varactor diode is as shown in Fig. 9.5(a).
Ge
Capaci1ance CT (pF)
Si
., ... ,_ , .......!
Reverse
Forward
voltage
+:;;::=-:;::;;==r-;:'f-"""":;':'!;-- voHage
(Volts)
. : I, in nA
j
0.2
0.6
CT decreases wi1tl increase
in reverse voltage
(Volts)
(Io in""
Si.
--~
JGe
Reverse
Characteristics
4-78
""
, Reverse current (!lA)
40~
.. ·'
~--
............. ''"' 20
(B-49) Fig. A
Forward current
"'
Reverse
voltage M
-16
-12
-8
"~
-
·~
-4
;
0 '
(a) Variation of C,. with reverse voltage
Reverse c~nt ·
(B-50)
Q,
7
Fig. B
-
Write short note on Zener diode application.
.
I•J§Mel:l
2.
4.
on the voltage-variable capacitance are called as varactor diodes.
A
A
0
0
0
~·
~
0
0
0
0
0
n side
e • • •
e <!> · • •
e6 • • •
e6 • •
r-
1+----t
wd
regtllator.
.
As a regulated power supply.
In the protection circuits for MOSFET and .OPAMPs.
In the clipping circuits , pulse amplifier.
Q. 8 Draw symbol of Varactor (Varicap) Diode.
Ans.: Diodes made especially for the applications·which are based
0
0
Ans.: Zener diode applications are,
1.
As a voltage reference in emitter follower type voltage
3.
Depletion
region
p sde
(b) p-njunction and depletion region
(F-221S)Fig. 9.5
10 S~te ap.pllcatJons of Varactor Diode
Ans. :Vanous applications of a varactor diode are as follows:
1.
FM modulator.
Q.
2.
3
.
4.
Automatic Frequency Control (AFC) t'n d'
.
A t
·
.
. ra to rece1ver.
u omabc tuning circuits.
In TV receivers • Automobile radios
.
Q. 11 Explain construction and working of tunnel diode.
Dec. 14 . Ma 16
Ans.:
K
(F-:UI4)Fig. 9.4 : Symbols of varactor diode
tea easv - so IUIIOIIS
h · "I?e. operation of a tunnel diode is based on a special
c ar_actensttc known as . the negative resistance The
semtcon_ductor materials 'used for constructing the tunnel di~es are
Gel1llaDlum or Gallium Arsenide. ·
~lc Devices & Circuita-l Elex.-Mu
ConstruCtion of a tunnel diOde is . .
4-79
R _ AV..f
F AIF
AVF is Positive but A lp is negative. Hence Rp is caJJed as a
~egative ~esistance. The decrease in Ip with incr~ in Vp
ts oppos!te. to. the Ohm's law. The negative resistanCe
cbaractenstlcs ts utilized in the applications of tunnel diode
such as oscillator and microwave amplifier.
~egion Z onwards : At point Z, the current starts
m~easiog with increase in voltage. So this is a positive
reststance region and the tunnel diode acts as the
conventional diode.
5.
Q. 13 Draw structure of tunnel diode.
Ans.:
The material used for the construction of a tunnel diode is ·
Germanium or Gallium Arsenide. Fig. 9.7 shows the basic
construction of a tunnel diode:
As doped
ball
Dec. 13. Dec.14.May16
AnS.:
The volt ampere characteristics of a tunnel .
. .
in Fig. 9.6(b) and its symbols are shown in Fig. 9.6(~ode ts shown
FOIWard
current IF
Kovar pedestal
<'B-1759) Fig. 9.7
: ConstructiQn of a tnnnel diode
Q. 14 What are the applications of a tunnel diode ?
-
(a) Circuit symbols of
(b) Volt-ampere characteristics of a
tunnel diode
taooel diode
(B-1760) Fig. 9.6
Reverse characteristics :
Due to heavy doping of p and n sides, the depletion region
il extremely narrow when the tunnel diode is · reverse biased.
Therefore the reverse blocking capacity of the junction is lost and
reverse current will start flowing as soon as a very small reverse
voltage is applied. Thus the tunnel diode allows the re~erse
cooductioo to take place for all the reverse voltages. ~ere ~s no
breakdown effect as observed in the conventional rectifier diode.
The:retore we cannot use the tunnel diode as a rectifier.
Ans.: Application of Tunnel Diode are,
1.
One of the important application of a tunnel diode is in
high speed computers where the switching times of the
·order of nanoseconds or picoseconds are desirable.
2.
'Tunnel Diode is used as an Oscillator .
3.
In the digital networks.
4.
As a high speed switl:h.
5.
As a high frequency oscillator.
Q.
15 Give comparison o' tunnel diode and p-n junction
.
diode.
Ana.:
Fonrtard characteristics :
I.
2.
Forward characteristics can be divided into three regions
namely X to Y. Y to Z and Z onwards.
y is
D....c~- X to y .. In this reuion the forward voltage F •
~
•
o·
ill take place m
e~mely smaJJ. But heavy con~uctJo~..wthrough the pn
;:;:~~JI~~tr=s ; : : as a resolt of heavy
3.
4.
doping.
.
oint y the forward
Y to Z : In this regto?• at the forward current
voltaee begins to develop a b~er::; 1·ncrease in Vp· This
ltaiU decreasing inspite of conunu
eifon.
Reaiou
X
region is called as the oegadve. ~~~:mathematically
The diode resistanCe in the regJOo
expressed as,
to
Breakdown
It bas a large reverse
3.
Reverse
blocking
breakdown voltage.
Breakdown due to
avalanche or zener effect
Conventional diode can
block high reverse ·
4.
Doping
levels
Symbol
2.
5.
less than 0.1
volts
Breakdown
does not take
place.
Can not block
the reverse
4-80
Electronic Devices & Clrcults·l (Eiex.·MU)
due to the "majority carriers" o~ly. No mino~ty carriers :;:'
•
d · the process of conductton. Due to th1s heavy flow of
mvo1ve 10
•
h ·
·
diode .
. to metal a region gets created near t e JUnc~on surface
Iectrons m
e
.
h
·u
t · 1 Th' ·
.Ana.:
which is depleted of carriers I;" t ~ Sl con. mat~a ·d.~s IS very
similar to depletion . region m t .ell p-n tJunc .~on ~~ el. These
Advantages of tunnel diOde are aa follows,
. ddi · a1 earners in the metal w1 crea e a nega 1ve ayer or
I.
Low cost.
·' uon
.
.
f
I d
.
wall" inside the metal at the b.ou~darr. orfmetab an. ;~ID.Jbeconductor
2.
The peak point voll.nge and current ( Vp and Ip ) are not
materials. The result of n:Jl thiS ·~ a su are arne
tween the
dependent on tempemture.
two materials, which prevents any further current. ~en w~ aPPly
3.
Tunnel diode needs a small number of external components a forward bias voltage, the str~~gth of tb~ ne~ative bamer wiU
and a de power supply for its opemtion.
duce because the external pos1t1ve potential wtll attract electrons
4.
It consumes low power.
. ~om the p side (metal). Due to this, a heavy flow electrons across
·the junction w111 begin. This f?rward current can be controlled by
Disadvantages
the level of applied bias potential.
l.
No isolation between the input and output.
Q. 19 Write short notes on
Schottky diode2.
Low output voltage swing. So amplification is required.
Dec.
07.Dec.
12. Dec·. 15
characteristics
Q . 17 Write short note on: Schottky Diode Construction
Ans. : The I-V characteristics of a schottky diode is shown in Fig.
Ma 04. Dec. 04, Dec. 07, May 08,
· 9.9. The characteristics of a schottky diode is very similar to that
Ma 11 , Ma 12. Ma 15
of p-n junction diode. But it has a very low cut-in voltage (of the
Ans. :
order of 0.2 Volts).
·
.
.
...
.
:
.
F
Oiward
ciineni
The construction of a schottky diode is as shown in
., ......, ·:·
I.
F~g. 9.&. It is q~te different from the conventional p-n junction
. . -··. ; ;
. ;. t·
d1ode. A metal semiconductor junction is formed between a metal
·· · · · .
. ·'··j·"·····.
- ..
: ~; p-n ll..aion
and n-type semiconductor as shown in Fig. 9.8. Eventhough n-type
dodo ;
diode
.. ; ·
se~conductor . is normally used; sometimes a ·p-type
;
.. . ... --; selll_Iconductor JS used. The metals used are molybden!Jm,
..
--~-:
i
platmum, chrome or tungsten. The characteristics for the device
Re~rse
!:
: FOIWard
will be depende!)t on the technique used for the construction of th~
~~ ~~~~~~--~~~-'~~~~-----. ~
:... .J..
schottky diode. The metal side ·acts as the anode and n-type
i
.......
.-..~.........;... .
semiconductor acts as cathode of the schottky diode.
Q. 16
State actvantligea and disadvantages of tunnel
a
__
:
~
•
. 'i
.
-~-
.,.... ..... .;.............
' ·· Reverse chataci;:~
..... .•
....!. ...
(B-1662)
Metal semiconductor
junction
n-lype silicon
Metal contact
Cathode(-)
(B-788) Fig. 9.8
Q.
: Construction of Schottky barrier diode
ll:t ~. V
Fig. 9.9 : I-V characteristics of a S~hottky diode
Q. 20 Draw equivalent circuit and circuit symbol of
Ans.:
· Anodeo
S IJ IIII J OJI S
a
schottky diode :
Ana. :
Inside the metal which acts as the anode as well as inside
the n-type semiconductor which acts as a cathode, "electrons" are
the majority carriers. Inside metal, the level of minority carriers
(holes) is not significantly high. When the metal and
semiconductor are joined to form the junction, the electrons in ntype material will flow to the metal side. This ·will establish a
heavy flow of majority carriers.
Since the injected carriers have a very high kinetic energy,
compared to the electrons of the metal, they are commonly called
as ~bot carriers". Jn the conventional p-n junction the minority
carriers get injected into the adjoining region. But here the
electrons are injected into a region (metal) where eJecuons only are
the majority carriers. In this aspect the schottky diodes are different
from the conventional diodes. Jn schottky diodes, the conduction is
. .
- ·~· ·-··-···-···
The reverse breakdown voltage of a SGhottky diode is less
than that of a p-~ junction diode. Typically it is about 50 V as
compared to .150 V f~r a ~-n junction diode. The leakage current in
the.reverse b1ased reg10n 1s higher than that of a p-n junction diode.
The _rev~rse leakage current flows due to the electrons in· metal
-passmg mto the semiconduclor material.
18 Write short note on: Schottky Diode: working.
May 04. Dec. 04. Dec. 07, May 08,
Ma 11 . Ma 12. Ma .15
-~~.~ryt.;
o cat~ode
CJ '
Cathode
(a) Approxlotate equivalent circuit
of ll schottky diode
(b) CirCuit ~boi of a
schottky diode
Fig. 9.10
Q. 21 List advantages, disadvantages and applications
of a schottky diode
(iMMfJ
Ana. :
Advantages :
I.
Lo~ on state fo.rward voltage drop.
,
4-81
Electronic Devices & Circuits-1 (l;lex.-MU)
2.
Higher speed of switching. These d.
frequencies in the gigahertz (GHz) r~~:s can be used upto
[l GHz =109 Hz}. .
· g .
3.
Total power dissipation taking place in
. .
is less than conventional. diodes.
the schottky dtode
[)isadvantages :
1.
Low reverse breakdown voltage. th f
inverse voltage) as compared to p'-n ~re ~re lo:-v PIV (peak
JUnctton diodes
· ·
High leakage current.
2.
Applications :
1.
Switching Mode Power Supplies (SMPS).
2.
AC-to-DC converters, Radar systems.
(b) Array of
photovoltaic cells
(a) Construction of selenium
photovoltaic ceU
Q. 22 Differentiate between Schottky Barrier Dio
p-n Junction Diode.
·
<F-1034) Fig. 9.12
de and
Q. 25 What is the basic working principle of solar cell
Ans.:
?
Ma 14. Dec. 15
Ans.:
l.
A~K
(F-969(a)J
2.
Forward
voltage drop
3.
Peak inverse
voltage
Leakage
4.
current
5.
Carriers
(F-969(a))
Typically 0.7 V
for silicon diodes
High . (typically
):.ow (typically 50
150V)
V)
Low (in
amperes)
Between 0 to 0.2 V
High
nano
A solar cell is basically a p-n junction device and no
voltage is directly applied across the junction. In other words we
can say that it is a large photodiode designed to operate as a
"photovoltaic" device and gives as much output power as possible.
The solar cell converts solar energy into electrical energy.
The construction of a solar cell is shown in Fig. 9.13(a) and the
simplified construction·has been shown in Fig. 9.13(b). Wf! can use
it_.to explain the operation of the solar cell.
(in
microamperes)
Condudion ~es
place
due
to
majority
and
minority carriers.
Ughtenergy
@ ' ........
Conduction takes
place only due to ·
majority carriers.
llll
;.
r p-type
h'
"-''":". ....c.~-~:::;;..., _1+--p-n junction
Load
j ·.·.-:.r:=> . rift ,
Q.23 Give Classification of Optoelectronic Devices.
-rEJ
Ana.:
n-type
dlrectlon of electron flow
rfY direction of hole fl~w
Optoelectronic devices
I
(a) Construction of a solar ceU
l
I
l
Light detectors
1
l
Photodlode
LOA
Space cha:rge
. Opto lsOiatorsfoouplers
l
Pholotranslstor
region
l
Sohircells
p
<F·2713) Fig. 9.11 : Classification Qf optoelectronic devices
·
The ~ptoelectronic: devices can als~ be .classified as
photoemissive, photoconductive and photovoltruc devtces.
Q. 24 Write a short note on : Solar cell : characteristics
I•N••tirnfi•'""•l4M•ti•I4•,.i
Ana.:
The photovol.taic cell generates a voltage across it w~ch is
proportional to the intensity of incident lig~t. The phorovoltruc cell
thus operates on the principle of photovolwc effect. .
. .
The construction of a selenium photovoltal~ cell IS as
shown in Fig 9 l2(a) and the practical way of connec~mg a nu~ber
· ·
. F. .., 9 l2(b) The selentum
of &olar cells is as shown JD 1g. ·
· . 00
Photovoltaic cell consists of a base plate made from 1 ~ or stee.l,
Which acts as the positive electrode of the cell: A sel~n.JUm lay~rhiS
Placed above the base plate. Selenium lpyer ~~ senslt~ve to bg 18
.t.
Above this, an electrically ·conducting cadmiUm oxide layer
i!ed, as shown in Fi . 9.1 a·
easv- s olutlnns
n
photo current
~~~_j .......
Photo currsnt
......................•
·..................
+
v
(b) Simplified diagram
(F-1035) Fig. 9.13
. . w_hen the light strikes the space charge region around the
p-n JUnctJO?,. the electrons and holes are generated, due to the
photons stnking the valence electrons and imparting energy t0
them. The optically generated electron-hole pairs are quick!
sep:uated and sw~pt outside the space charge region (depleti~
regiOn) due to the mfluence of the external electric field.
4·82
Electronic Devtcea & Clrculta·l (Eiex.·MU)
These eled:roos and holes now to constitute the
photocun-ent u shown in Fig. 9. t ~(b). This photocurrent produces
• voltage V across tbe load resistance Rt_. Thus solar cell supplies
power to the load.
..
·
Q. 21 eq,laln chantcterlatlca of aolar cell and alao
expWn what Ia the need to connect aolar cells In
of In pt~rallel fuhlon.
Pig. 9.14(b) shows how to connect a gr<>U:P of ~lar cells. Seve-;'
ceiJs in series and/or parallel. connected 10 senes to produce the
required output voltage and . several of these series connected
groups are connected in parallel to supply the required output
current.
Q. 27 State advantages and disadvantages of
cells.
..n..
1\1;~
' 14. Dec. 15.
1\1;~
14. Dec. 15
Ana.:
.n.e typical output characteristics of a power photocell is as
sbown m Fig. 9.14(a).
~r-n::-:--,---.----~--~
··-····'-·
~
7'0
Maximum .! _I_ ..
\
power
paint
~+--1-'-:-!-.....Y~-r
H~~:.:-+-~....J
SOla-;
Ans.:
Advantages,
1.
Th~y respond very well to the incident light over a wide
range of incident wavelength.
No need of external de source for <>J>eration.
Can produce an adequately large ph_otocurrent.
2.
3.
Disadvantages ,
;
·i·:;i"-"
2. ·
3.
Slow operation. The solar cells cannot change their output
rapidly if the light intensity changes rapidly.
Solar cells are temperature.sensitive.
Low output voltage and current.
a. 28
What are the applications of solar cells ?
1.
\ft;_f·1:i
COl
Ans.:
Applications of solar cells are as follows,
2.
3.
Solar cells.are used to power the electronic circuits used in
satellites and space vehicles.
Power supply to calculators , for charging the batteries.
For powering the cars run on solar eitergy. Typically a car
. needs about 8 m 2 of solar cell arrays that can produce 800
W of pciwer on a sunny day at noon.
a. 29
Write short note on : Photodiode.
1.
10
o~~~==~=t~UIIJD
0 .1
0.2
0 .3
0 .4
0.5
0 .6
0 .7
v
OUtput voltage
(a) Typical output characteristics of a solar cell
Dec. 06. Dec. 14. Ma
07. Ma
12. Dec. 13. Dec. 16
Ans.:
13-0011-*'d
c.a.
-r
~. -~-TI
: · !fte photodiode is a p-n junction semiconductor diode
which ts. always operated in the reverse biased condition. The
. ~on~trucllon of a photod.iode and its circuit symbols are as shown
m F1gs. 9.15(a) and (b) respectively.
Photona
v
..
(b)
(F-1037) Fig. 9.14
2
Wbeo the incident illumination is 100 mW/cm • If the cell
is lbort circuited. then the output current is 50 mA but the output
vo~t.a&e iJ zero_ Hence the output power is zero. If the cell is open
cin:ui1ed, then tbe output voltage i.s 0.55 V and the output current is
zero. Tberetore the output power is zero. For muxlmum output
.powet', tbe cell nw.&t be operated in the knee region of the
charaderiitics, as shown in Pig. 9.14(a). Like other devices the
• utpUt power mu.st be derated at increued temperatures.
A photovoiUic cell i.J capable of generating a voltage upto
o.•N aod can supply current In IJ. A range. Therefore in practice
~Yare cooneaed in ~Cries and parallel as shown in Fig. 9, l4(b),
an order to iooruse their tenninal voltage 311d the current sourcing
capability. The ICiies coonec.tjoo inaeues the voltage while
parallel connoctioo will increate the current IIOW'Cing capacity.
L I •. J
•. tl Ill I I II II '•
(a) Construction of a pbotodiode
(b) Symbols of a pbotodiode
(B-lOSO)Fig. 9.15
Conatructlon and Operation :
The light is always focussed throu
junction of the photod.iode.
gh a glass lens on the
~the photod.iode is reverse biased, the depletion region is·
' penetrated on both side of the junction as shown in
~g. 9.~(~). The photons incident on the depleti~ region will
ampart . etr energy to the ions present there and generate electron
hole.pairs.. The n~ber of electron hole pairs will be dependent on
the mtensaty of hght {number of photons). These electrons and
't
qut e
WI
aectrOnic Devices & Circuits-! (Eiex.-MU)
......-
4-83
bOleS will be attracted towards the positive
.
respectively of the external source, to consti:d negative tenninals
With in~rease in the light intensi te the photo current.
_,..,.trOD bole paus are genemted and th hty, more number of
""""
·
e P otocurrent ·
'Jbus cbe photocurrent 1s propoJ:tional to the 1• h .
. Increases.
tg t mtens1ty
PflOIOdlode Charactertstlcs :
The photodiode V~I characteristics
Fig. 9.16(a) and the variation of photocurrent
as shown in Fig. 9.16(b).
.
·
Q . 32 Give comparison between LED and Photodlode ·
Ans.:
. as .shown in
11ght mtensity is
.
LED
Sr.
:UCth
WI
In the fiber optic receiver.
In light intensity meters.
3.
4.
2.
VF
(Vohs)
3.
4.
I._(Reverse CUIT9nt)
(IIA)"
(a) V-I characteristics of a photodiode
LED
is always forward
biased.
GaAs or GaP or GaAsP
are the materials used.
Silicon is used.
Due to recombination .of
electrons ·and holes,
ligh~ is emitted.
Due to generation of
electron bole pairs, the
pbotocurrent will flow:
6.
Circuit s mbol :
Anode
Circuit symbol :
,..
Cathode
intensity of light
Ans.:
(B-208l)Fig. 9.16
The construction of a p-i-n diode is as shown in Fig. 9.17.
A nearly pu.re (lightly doPed) "n" type of semiconductor layer has
been inserted between the heavily doped p and n layerS.
This layer is called as the "intrinsic"· (pme) layer i.e. "i"
layer and the device is"called the p-i-n flhotodiode.
Dark cnrrent : It is the current flowing through a
pbotodiode when there is no incident light on the device.. ( Fig.
9.16(a)). Dark current flows due to the thermally generated
minority carriers, and hence increases with increase in temperature.
The reverse current I (photocurrent) depends only on the
intensity of light incident on ~e junction. It is almost independent
of the reverse voltage as shown in'Fig. 9.16(a).
·
advantages
and
disadvantages
as
of
.
photodiode.
~ Swept minority carrier
Ana.: Advantages,
.
.
L
lligb sensitivity : This means, a large change . m . the
.
mall change m light
photocurrent will take place fior a s
2.
caU,~
(B-2084)
Q. ~3 Write a short note : p-i-n Photodiode .
(b) Variation of photocurrent with
List
,.
c
Electric current proportional
is
intensity
light
to
produced.
It is always reverse biased.
(B-2083)
0. 30
/,
It is a light detecting device.
·~
'
.~
5.
Photocunent
(!lA)
It is a light emitting
device.
Electrical energy is
converted into light.
..
'
.
No.
l.
'
'Pbotodlode.
intensity. .
· LDR (Light
High speed of operation as compared to
·.
Dependent Resistor).
e--
External bias
(L-831) Fig. 9.17
: Construction of p-i-n photodiode
Dlaadvantages of Photodlode :
1.
Dark current increases with temperature.
The intrinsic layer is made thicker so that almost all the
photons which pass through the junction are absorbed within this
layer.
2.
3
·
Poor temperature stability·
.
.
tial for operatton.
Extem.aJ bias voltage IS essen
t current is of small
Operation of p-l·n photodlode :
L
The light which is to be converted into electric signal is
4.
Amplification is required, as the outpu
magnitude.
·
I!MMII
Q. 31 State application~ of photodlode • ·
An .
. .
t.odi.ode are as foiJows,
a.. Applications of pho
.
b'ect counting
h0 todiode IS an 0 ~
I·
Popular application of the P
2.
system.
In the cameras for sensin
r: :t S V · S IIIIIIJOJI S
2.
made to fall on the junction of the photodiode. The
photodiode is reverse biased.
Photons enter the depletion region and encounter with the
atoms within the depletion region, They generate electronhole pairs inside the depletion region.
I
4-84
Electronic Devices & Circuits-! (Eiex.-MU)
Due to the reverse voltage applied across a photodiode.
these electrons and holes are drawn across the junction and
leakage current proportional to intensity of incident light
starts flowing. Thus light is converted into electric current.
Due to wider "i" layer, a more complete absorption of
photons takes place and a larger photocurrent gets
produced. The sensiti_vity of p-i-n photodiodes is therefore
higher than that of a p-n junction diode.
Due to the addition of ''i" layer, the electron-hole pairs
generated due to photons have to travel a longer distance.
Hence p-i-n diodes are slightly slower than the p-n junction
diodes.
3.
4.
s.
a. 35
Dlfferentla
te p-1 n and avalanche photo diodes .
•
-rm:G-
Construction
l.
(L-835)
Biasing
Reverse
biased
Reverse biased
2.
Sensitivity
Higher
than p-n
Very high due
3.
photo
effect.
Q. 34 Describe construction, working and characteristic
Dec. 13. Dec. 16
of avalanche photodlode.
Ana. : The construction of an avalanche photodiode is as shown
in Fig. 9.18. It has a p-i-p-n structure. Light enters through a thin
"n" layer which is heavily doped.
·avalanche
diode but
.lower
than
APD.
4.
Dynamic·response
Slower
than p-n
Slowest due to
photo
transit time.
diode
increased
b~t
faster
External bias
(L-832)
to
than
Fig. 9.18 : Construction of avalanche photodiode
APD.
Operation of avalanclie photodiode :
1.
As negative voltage applied to the diode is increased, the
intensity of the internal field increases proportionally.
2.
The internal field intensity then reaches a threshold so that
the electrons which are being accelerated . through the
junctiqri region will generate secondary eleetron-bole pairs
due to collision.
The number of carriers generated in this manner will
3.
generate many more electrons due 'to collisions. This is
·
called as "avalanche effect".
4.
In avalanche pbotodiodes, the electrons generated due to
the light are accele~ and made to pass through the
junction region. They give rise to avalanche effect and a
large current starts flowing through the device.
.
Due to the avalanche effect a sort of "current
5.
amplification" takes place inside the device to yield a much
higher current. Thus the sensitivity of this device is much
higher than that of a p-i-n diode.
The p-i-p-n structure helps to concentrate the internal field
6.
·near the junction in a better way.
·
5.
Avalanche Multiplication
6.
Noise in the output
Absent
Present
Very
High
due
low
random
to
fluctuations of
avalanche
multiplication
factor
Q. 36 Write short note on : LED construction, working.
Dec. 04. Dec.09
Ans.:
An LED emits light when electrical energy is applied to it
The construction and biasing of LED is as shown in Fig. 9.20(a)
~~
.
Frequency response :
Silicon p-i-n and avalanche diodes typically h~ve a
. frequency response that extends from about 0.6 J.l.m to about 1.2
J.UD as shown in Fig. 9.19.
o.e
0.4
,
0.
1.
Wavelength ).o(J.IIT1)
CL.&Jl) Fig. 9.19 : Spedral response of pin and avalanche diodes
ea s v
SOIUliO IIS
(a) Construction
and principle of
operation of a
LED
(b) LED biasing
(c) Circuit symbol
.. ofLED
(F-1039) Fig.
9.20
e~nic Devices & Circuits-! (Eiex.-~)
4-85
P# ,uvctlon of LED :
COf1 1be construction of LED is same as th
·conductor diode and the LED is operated . at of a p-o junction
::on asTbeshown
in Fig. 9.20(b). R is the CUrren~ :~rw~ biased
LED operates on the Principle Wbi
g reststor.
recombination of electrons and holes tak cb states that when
~eased in the fonn of light. One of the po~lace, an energy is
re sUUction 'is to deposite three semiconduc methods of LED
~..-.H>. as shown in Fig. · 9.20(d). The t?r laye~ on the
su~--
d . .
Th
active re,on
.
n regiOns. e light emerges fro
o • . eXtsts
.10 all the directions when electron hole ..,.....,
n ooi... rec
mb. the active side
om me.
l. Gallium Arsenide ( Ga As)
Infrared (IR)
2. Ga AsP
Red or Yellow
3. Gallium phosphide (GaP)
Red or Green
Q. 37 What are the advantages and disadvantages of
~n the p an
~
(o~~,.....,,.,.~~.,..-.1 } l\ctive region
~""'~~~ri:t~-n'"fegion
Substrate
<F-1040) (d) :
Construction of LED
LEOS?
Ans.: Advantages of LEOs are as follows ;
1.
LEOs are of small size and light weight. Therefore it is
. possible to pack a large number of LED, in a small space
while manufacturing a display.
2.
They are available in different spectral colours.
3.
They have longer life as compared to the lamps.
Disadvantages of LEOs :
'
1. ' Output power is affected by changes in temperature.
2.
Over current can damage it easily.
3.
They need larger power for their operation.
Principle of LED Operation :
When the LED is forward biased, the electrons in the nregioo will cross the junction and recombine with the holes ui the
p-type material. These free electrons reside in the ·conduction band
and hence at a higher energy Level than the holes in the valence
band. When the recombination takes place, these electrons return
back to the valence band which is at a lower energy level than the
conduction band. While returning back. the recombining electrons
give away the excess energy in' the fonn of light. This is shown in
Fig. 9.2L. This process is called as electroluminesceoce. In this
way an LED emits. Light. This is the principle of operation of LED.
Ans.: The typical applications of LED are :
l.
In the optocouplers.
2.
In the infrared remote controls.
3.
As indicators in various electronic circuits.
4.
In seven segment and alphanumeric displays.
Q. 39 Differentiate PN Junction Diode and LED .
Ana.:
Sr.
No
l.
PNlunt!ttOil·
Parameter
Dlbde' .
Symbol
Z
energy gap
• Ught output
~~--+-~~~~------.~~1
'<
·.'·~Cl
~
-
o---{>f------o
.. .. ........ ...... ...... ....... . ....
~J ~ ~ ~ ~ 11 ~ .~
.i:=~~ii~:
..... .. ::i.b~J~~J~
......... .............
Forbidden!
Dec.04. Dcc. 09
Q . 38 State applications of LED
Fig. 9.~
(F-1048)
Silicon
Germanium
Colour of the emitted light :
. clec"ded
by its
1
• ted l"ght
IS
1
The colour of the ellllt .
• ererit materials are as
wavelength. The colours associated wtth diffi
.
follows.
LED
~
//
~
(F-1049)
or
-
Gallium Arsenide
2.
Material used
3.
Capacity
emit light
to
Cannot emit light
Can emit light
when
excited
electrically.
4.
state
On
voltage drop
0.7 V for silicon
diode 0.3 V for
germanium diode
Ranges between
1.2 to 2 Volts
5.
Reverse
High
Very low
Rectifier, clippeJ:,
damper etc.
As a light source
in optical fibre
applications. As
indicator, in 7
segment displays.
Valence band
Recombination
of hole and electron
Fig. 9.21·: Principle of operation of LED
_"\
bre~down
voltage
6.
Applications
&:::
Electronic Devices & Clrcults-1 (E:Iex.-MU)
-
Chapter 10 : Rectifiers & Regulators
Q .• 1
Draw the block diagram of regulated power
at.q)ply.
8. Hence the diode is forward biased and starts conducting. As the
diode starts conducting, the secondary voltage V AB appears almost
as it is ·across the load resistance (as the voltage drop across a
conducting diode is very stnall).
The load voltage is thus positive and almost equal to the
instantaneous secondary voltage V AB' ·The load current has the
same shape as that of the load voltage since· the load is purely
resistive. The waveforms for HWR are . - shown in
Fig: 10.4. The instantiuleous load current i1- is equal to the ratio of
instantaneous secondary voltage (VAB) and total resistance (Rg + Rp
+RJ.
VAB
IL = (R +Rp+RJ
<B-163)
Fig. 10.1 : Block diagram of a regulated power supply
Q. 2
Oeftne rectlfter and rectification.
Ana.: ~edification .is the process of converting the alternating
~tage or current mto the corresponding direct {de) quantity
(direct voltage or cw:rent).The input to a rectifier is an alternating
(ac) voltage whereas 1ts output is unidirectional or de voltage.
1be electronic circuit which carries out rectification is
called as rectifier. Rectifier is an electronic device which is used
~ ~~ning an alternating (ac) voltage or current into a
unidirectional (de) voltage or current
Q. 3
...(l)
8
Operation in the negative half cyde of ac supply (11: to 2,.;) :
In the negati,ve half cycle of the ac supply (1t to 2n),
secondary voltage V AB is· negative, i.e. A is negative with respect
to 8. Hence the diode is reverse biased and offers a very high
resistance. Hence we can replace it by an open circuited switch.
The load is disconnected from the secondary. Hence the
load voltage and load current both are iero and the voltage across
the diode is equal to the instantaneous secondary voltage VAB· The
waveforms are shown in Fig. 10.4.
Claaalfy rectifiers.
Ana.: .
1be classification of rectifier configurations is as shown in
Ftg. 10.2
. .
.
Aacafter clrcul18
tW Wow Railer (HWR)
Ful Wave R9cllfler (FWR)
FWR with oenter
FuR wave bridge
roollfler
tapped tnmlllormer
(B-88)Fig.
Q. 4
10..2 : Classiftcation of rectifiers
Explain the operation of Half. Wave Rectifier
(HWR).
Ana.:
.
In balf wave rectifier, the rectifier is on only during one.
half cycle of the ac supply. So output is produced only in that half
cycle. The output is suppressed (zero) in the other half cycle.
0
T1
(Input transformer)
<J-1') f1&. 10.3 : Half wave reedfter
Operlllort of IN HWR :
Opendoe la the polltlve ball eyde of~ supply '<O-n) :
.. half . ~ycl.e. (O--n>, of ~e ac supply, the
wrond•In vthe posiUve.
ry oltage VAll 111 JlOSltive. t.e. A 1s pos1t1ve with respect to
lit I :t '
\.1
', II I II I I II t1 •,
8
<B-91) Fig. 10.4 :
Waveforms fo~ the HWR
0.5 Derive ILdc • VL rma .IL rma ,Vt.Ato , RF , PLdc p and 11
ofHWR.
·
'
.c
.
~ronic Oeyjces & Circuits-! (Eiex.-MU)
4-87
Ana.: HWR:
·1•
DC or A verkge Load Current (ILd ·\ • By d fi ..
average value of a periodic fun . ~ •
e nttion the
ction ts gi
b
under one cycle of the functio di . ven Y the area
(period). Considering one n rl(;led by the base
O>t =0 to rot =27t of the load c comp ete cycle from
Fig. 10.5.
.
. urrent waveform shown in
=
=
4.
.. lav =
rapea
.. lUc =
J~ sin rot drot =~
[cos rot]
27t
.
=
Im
where,
-I,
• • VLrms= .
5.
11
0
0
•••
(
) •
1
Peak amplitude of the loa4 current
.
.
271; [COS1t- COS 0)
=
-I,
7t [-1-ll
· V m = Maximum or peak secondary voltage
DC or Average Load Voltage (V...J : As the load is
VLdc
2
=
r
6.
112
Vm/1t
r = 1.21 or 121 %
...(8)
DC Output Power PLdc : The de or average output power
delivered to the load is given by,
[I.n]
Pl.dc = ~ xRL = -;
· •
2
2.
.
r
RL ~ .1t
-ll! RL
...(9)
v2 . .
v
7t( Rs + Rp + RJ
...(4)
If RL
.. .(5)
.....t..
=
Peak secandary voltage
.
, AC or
Load Cun:ent (IL em) : Considenng
complete cycle of the load current waveform (0 -
RMs
shown in Fig. 10.5 ,
l/2
[in j I~ dolt]
= [ ~1c~ oo;z )do'l
;in' rot
0
1/2
OlJ_
~b~
n;
7.
v2
=~
Ldc 1t~L
» (Rg + Rp) then,
But V.Jrc
~:
7V ...Appro~
=
[V~nns- V ~de ]
2
.. <Rs+Rp+RJ == RL
Hence Equation (4) can be approxiiJlated as,
~llDI
.. .(7)
Substituting the expression for ~ to get,
xRL ...Exact
·
Usually Rs and Rp are.small as compared to RL
3.
...(Approximate)
[<Vm/2) :... (Vm/1t) ]
·
VLdc· = I,xR
7t
L
V
... (Exact)
Substituting the approximate values to get,
purely resistive the average load voltage is given as :
VLdc = Il.dc x ~
... (3)
Silbstituting the value of Il.dc to get,
where
vm
.
Ia. = Rs + R; + ·~ , it is the peak load current
~ = Di~ forward resistance,
Rs = Transformer secondary·resistance
m
= 2I.n xRL
ILnnsxRL
T
r=
v
VLdc ""
...(6)
2
Ripple Factor (RF) : The rectifier output consists of AC
as well as DC components. The ripple factor me3sures
percentage of AC component in the rectifier output.
Ripple factor is denoted by "r'•.
RMS v~ue of the AC component of output
Ri ·
PP1e fac~r = .
DC or average value of the output
.
...(2)
=
But sin 2rc =0
112
.. Iuc = -;
2.
I,.
2
I,
where,
J
But {Rg + Rp) <« RL
_.
IL de = 27t
n; -!sin 2n;)
ts
• <B-93>J!ig. 10.5 : Load current waveform
7t
1
*{
vm
L This portion of load current wavefonn
'
1/2
AC or RMS Value of Load Voltage (VLnat): Since the
load is purely resistive, the rms value of load voltage is
given by, .
=
Itself. So oonslder It for~latl
average and rms value.
ng
1
; [
=
P
·v2
Pl.dc"'~
Vl.dc,
L
, ..(10)
. AC Input Power (P.J : Th.e ac input power to a rectifier
is the power supplied by the seconrulJ:y winding ~f the
transformer. It is given by,
2
Pac = . Isnns x(R8 +Rp+Rd
...(11)
Where I.mu =RMS value of the secondary current
For a HWR, the secondary current is same as the load
current. Hence RMS vatue of the secondary current is same
as the RMS value of load current.
..
...
I.nns
=
Im
ILnns = 2
2
Pac = ( ; ) (Rs+Rp+RJ
...(12)
-
4-88
Electronic Devices & Circuits-! (Eiex.-MU)
a. 10 Where are HWR are used ?
·r' 2
= 4m <Rs + Rp + RJ
8.
Redifkation
Efficiency :
... (13)
Efficiency
or
Power
Conversion
Rectification efficiency is defined as,
DC output'power
Pl.dc
'll = .AC input power = Pac
Substituting Equations (9) and (13) to get,
'll
2
2
:z . ~oc RL
=__<.;.,}n~'n...;.)_R....:L::.-_
Is rms (R8 +RF + RJ ( ~ /2 ) ( Rs + RF + RJ
=
4
If~ >> <Rs +
efficiency as,
4
;?
step down transfonner having turns ratio 10 ;-;
a.11 A
and input 230 V, 50 Hz Is used In 8
half-wave rectifier. The diode forward resistance
Is 15 ·o hms and reslsta.n ce of secondary winding
Is 10 ohms. Fo.r a load resistance of 4 k-ohms,
calculate average and rms values of load current
and voltage, rectification efficiency and ripple
factor.
R.,), then we get the maximum rectifiCation
·
·
= 0.4 or 40%
... (14)
Define : Voltage Regulation . .
Q. 6
. A HWR is used in the eliminators for pocket radios ·or
eliminators for walkman or in the low cost power supplies.
Rr
=·;( (Rs+Rp+RL)
'llmax =
Ans.:
Ans.:
N1 / N 2 = 10, Vin ·= 230 V, RF = 15 .Q, Rs = 10 Q,
RL =.4 k.Q, Circuit : HWR.
Il.dc, I~..nns, VLdc' VLnns' 11 and ripple factor.
Given:
To find :
l.Rms secondary voltage
v. =
Ans.:
Voltage regulation is defined as :
VNL....:.VFL
.
Voltage regulation =
V . x 100 %
FL
Where , VNL = . Average load voltage at no
load i.e. when RL ::: ~·
··
a. 7
VNL =
vm
1t
3.
a. 8
Define Peak Inverse Voltage {PIV} •
=32.53 Volts
+RF + RJ
32.53
10 + 15)
3
2.57 x 10- A or 2.57 mA
•••Ans.
vm
~
=
5.
2 (RL +Rp + Rs)
32.53
.
2 (4000 + 10 + 15)
=4.04 mA
••.Ans.
Average load voltage VLdc = ILdc RL
to 3
=. 2.57 x w- 3 x 4 x
= 10.28 Volts
=
6.
•••Aos.
=
3
3
Rms load voltage VLnns ILnnsRL 4.04 X 10- x 4 X 10 ·
= 16.16 Volts
•••Aos.
Rectification efficiency
7.
2
'll
PIV is the maxi.mlim. negative voltage which appears across
a nonconducting reverse biased diode. In HWR , the maximum
negative voltage across the diode is -Vm Volt, when the diode is
not conducting. ·
·
·
a. 9
1t (Rs
Rms load current ILnns = 2
4.
Ana.:
.•. PIV
?< 23
1t (4000 .+
=
Ans.:
=
v> ....[2
vm
ILdc =
Define Transformer Utilization Fac;tor (TUF).
. VI"' lx 4c
Vsrmsfsrms
=w
I
Peak secondary voltage
Vm = ....{2 X
Average load current ·
2.
.. . (ForaH.W.R)
The transformer utilization factor (TUF) indicates how well
the input transformer is being utilized. It is deflned as the ratio of
de output power to the ac power ratings of the transformer.
TUF iS defined as :
··
TUF _
DC output power (P.,J
- A C. power rating of the transformer
.
N2 . 230
230xN
=23V.
=
Ans. : Disadvantages of HWR are ,
1.
Ripple factor is high (1.21).
2.
Low rectification efficiency (40 %).
:3.
Low TUF (only 28 %) which indicates that the transformer
is not being used effectively.
Advantages of HWR
1.
Simple constivction.
2. ·
Less number of components are required to be used.
3.
Small size.
£!~1 $ \1-SOIIII!OIIS
~oc RL
.Il.fms ~+ Rs + Rp)
2
= . (2.57x 10-?x4 X IQ3
(4.04 X 10- 3) 2 X 4025
= 0.4021 or 40.21 %
Vm Volts
State advantages and··disadvantages of Half Wave
·Rectifier •
·
=
8. .
2
2
- V )
Ripple factor = 'm•
'4s
.
VLdc
= 1.2129
or 121.29
.
·
[V
%
••.Aos.
112
[(16. 16)2 .:_(10.28)z.,tn .
J
=
10.28
••.Ans.
Q.12 Explain 1he operation of full wave rectifier anddraw the output waveforms for V and I
Ldc
Ldc •
Dec. 09. Ma
10
Ans.:
The_ full . wave rectifier configuj:ation is as shown in
Fig. 1.0.6. It conststs of a step down center tapped transformer 'I\,
two diodes and a purely resistive load RL.
-
Electronic Devices & Circuits-! (Eiex.-MU) ·
4-89
Q. 13 Derive expressions for lm ' IL de'
.
1+
vl.dc. IL rme. vL.....
,RF,PI.dc. Pac: and TJ for FWR•
L
'v
Ans.:
2SOV,AC ··
N
·1. Peak load current lm
Peak load current, I., =
(B·97) Fig.
In the HWR the load current flows in 0 1
the supply but in the fuii wave rectifier it
cycles ofac supply.
·
fl~
Vm =
where,
10.6 : Full wave rectifier
h
':\o:- ~cle
Rg
of
e half
=
RF
operation of FWR :
Operation in the ~tive half·cycle (0 -n) :
In the positive· half cycle of ac supply v .8 . . .
d
.
. • AO 1 posttive an
v80 is negative. Due to the centre .t apped secondary v
dV
·
' AO an BO
are alway~ equal and o~postte to each other. Hence diode n is
1
forward btase<l; and D 2 Is reverse biased. ·The load current starts
flowing from A, through D 1, load resistance RL back to point 0.
Peak secondary voltage for half the
secondary (OA or OB).
Resistance of half the secondary
(OAorOB)
Forward resistance of a diode.
Average Load Current (t de) :
2.
Load
current
_The instantaneous load voltage is positive and.
approXlDlately e<_IUal to V Ao· As the load 'is purely resistive, the
load current iL has the same shape as that of the load voltage. The
voltage and current waveforms are as shown in Fig. 10.7.
Operation in the negative half cycle (7t - 2 n) :
In the negative half cycle of the ac supply, VA~ is negative
and V80 is positive. Hence D 1 is reverse biased and D2 is forward
biased. So D 1 acts as an open circuited switch and D 2 carries the
entire load current. The direction o~ load current ~ is same as
that in the positive baif cycle. That means even in the negative
half cycle, the load current continues to be positive. The
instantineous load voltage vL ·is positive and almost equal to
VIIO.
...(1)
(Rs + RF + RJ
·This portion of load current waveform repeats
itself. So consider it to calculate
average and rms values.
•
(B-102) Fig.,10.8: Load current for
FWR
Considering the load current waveform extending from 0 to
1t because this portion repeats itself again and again.
1t .
J
. . Average load current IL de = ~ I., sin rot dc.ot
.- 0
I.,
-; [-cos c.ot ]
Wavefonns :
.
The voltage and c~rrent waveforms are as shown in Fig. 10.7.
7t
0
-I.n
-I.n
.
-[cos1t-cos0] = - [ - 1-1]
1t
·"
1t
21...
...(2)
1t
where, ~ =
vm
(R8 +RF+RJ
Ave~age Load Voltage (VuJ :
·3.
As the load is purely resistive, the average load voltage of a
full wave rectifier is given by,
=
VLde
ILde X RL
Substituting the value of IL de to get,
Diode
oonent lp1
1&£~~":--~-IT.~T"":S.-:---"''
VLde
:=
~
1t
X
RL
Substitute the value of I.,. to get,
2V
VL de = 1t {Rg + R; + RJ X RL ...(Exact)
=
t
... ' . ... · ·· ···· ·iv
L;;w·· ·
d rrent waveforms
<a-tot) Fig.10.7: Voltage an cu
for a toll wave rectifier
.
ea s v- s olntton s
'
-
m
n[l +
...(3)
(Rs;LRp)J
Assuming that ( R 8 + RF) << RL to get,
.
Vu, =·
ZVm
1t
... (Approximate)
.•.(4)
-
. 4-90
Electronic Devices & Circuita-l (Eiex.·MU)
RMS Load Current (IL ~ : ·
Considering the load current waveform(Fig.
4.
.
Substituting the value of lm to get,
10.8)
~:.[~y:.~ ;:r~J:~~:~r·
=[
fJ
(l - cos2oK)don
r
pK
J
112
' • 11 =
I,.
= ...f2
...<s>
Compared to HWR, the value of IL mu for FWR is higher by
20.7%.
RMS Load Voltage (VL mJ :
'The nos value of load voltage is given by,
VL,_ = llrma X RL
5.
:. VL,...=
I,.
...[2
X
=
(Irrf\lil (Rs + Rp + RJ
8 R1
..:(10)
11
n2 <Rs + Rp .f. RJ
This is the required expression for rectifier efficiency.
Assuming (Rs + Rp) · << RL we get, the maximum value of
efficiency to be,
..
=
· = ~ =0.812 or 81.2%
...(11)
11max
1t
.
'
14 Give reasons : PIV of a FWR with cent~
.
transfoJmer Is 2 Vm·
a.
RL
Substitute the value of I,. to get,
y.
VLIDII
m
"\{i(Rs+Rp+RJ
X
. ...(9)
As,
112 .
I,. [ 1
...f2
; 1t- 2n1 <O>
•
RectHier Efficiency :
9.
= -~[*(rot)~- 2~(sin2rot) ~J
=
..
2
Vz (Rs+Rp+RJ
V
2m(Rs + Rp + Rj i = 2 (Rs + Rp + RJ
II!Bi1l
Ans. :
To obtain the value of PIV, referring Fig. 10.9, which is
:th~ equivalent circuit of FWR in the positive half cycle.
R
L
VMJ
... (Exact)
~
vL,.,. = ...[2
·...<Awroximate>
0~+
...(6)
Ripple Factor (RF) :
6.
2
2
· [VLnns- v Lde]
=
Rippfe factor {RF)
o1 oN
A
Assuming {Rg + Rp) « Rv
~A
112
1---vBA-...j
I
e
VL de
Peak value ol
Substituting the values to get, ·
Mi - (2V
( (V
=
1t)2]
2Vdn
. [1t2
8
(B-103) Fig.
]112
-_1
... (7)
0.48or48%
DC Output Power (P~ :
The de output power is given by,
7.
PLde
=
(de
X
=
21,.
n
vm
and Im =-Rs+ Rp + R1, to gc::t.
4V
..
2
= 1?(Rs+R:+RJ2 x RL
PLde
AC Input Power (P80) :
The ac input power is given by,
P~ •
J;
lllll
x (Rs + Rp+ RJ
= [ ~]
p~
=
1: :1 '. \1
I;
2
10.9 : Peak inverse voltage for FWR
Diode D1 is conducting and it is assumed to be equivalent
to a closed switch. Let us obtain the PIV of D 2 which is no~ OFF.
Fig. 10.9 shows that in the positive half' cycle (0 - ~) the
instantaneous voltage across D 2 is V BA· As shown in the
wavefonns the mllximum negative value of V BA is - 2Vm·
.. PIV
2 Vm Volts
=
RL
Substituting , ILde
1.
VIlA 1& -2Vm
112
m/
RF=
$
...(8)
Q .15 State advantages, disadvantages and applications
of Full Wave Rectifier .
Ana.:
Advantages :
1.
2.
3.
Low ripple factor as compared to HWR
Better rectification efficiency
Better TIJF
Disadvantages :
x(Jts +Rp+RJ
(Jts +R,+RJ
2
', II I II I ! II II ~.
1.
2.
Since PIV of the diodes is 2 Vm' size of the diodes is larger
and they are more costly.
Cost of the center tapped transfonner is high.
~rontc Devices & Ctrcuits-1 (Eiex.-MU)
4-91
APPlications of FWA :
Laboratory power supplies.
}.
High current power supplies.
2.
Battery
chargers.
.
3.
Power
supplies
for
various
electro
.
. .
4
..:-mc cJrcwts.
a. 16 A full wave rectifier Is used employing .
1.
Centre tapped transformer
•
2.
Bridge configuration.
•
To give an output of 9 v peak f
50 Hz supply, compare the tw rom 220 V AC,
0
reference to the rms ou ut c 1rcults with
transformer turns ratio
voltages and
voltage to be o 7 Volts 0' 1
.ume diOde cut-In
•
• scuss relative me Ita 1
the two configurations ·
r o
OperaUon of the Bridge Rectifier :
1.
Operation in the positive bal( cycle (0 !: c.ot !: n) :
In the positive half cycle· of the ac supply the secondary
voltage VAD is positive. Therefore diodes D 1 and D2 are
·forward biased whereas D3 and D4 are reverse biased. The
reverse biased diodes D3 and D4 act as open switches. The
load current and load voltage both are positive as shown in
the waveforms iii Fig. 10.11.
2.
Operation in the negative half cycle (n !: cot!: 2n) :
In the negativ.e half cycle of the ac supply_the secondary
voltage V AB becomes negative. Diodes D3 and 0 4 are
forward biased and start conducting. 0 1 and 0 2 are reverse
biased , hence do not conduct. The waveforms of the
bridge circuit are as shown in Fig. 10.11.
A:
Given :
Peak output voltage V 0 {peak)
Primary voltage =220 V
.
1.
1
-·14••!1
.
Afl$.:
=9 v;
rms
Centre tapped trausfonner FWR :
= 9v
:. Peak secondary voltage (112 winding)
= 9+0.7 9.7 v
RMS secondary voltage
v o (pelk)
=
= 9.7 VI =6.86 V~lts.
.
.
NJ 220 .
:. Transformer turns ratio : N = .86 = 32
6
Vl
.
.
2
.
The ratio is of primary to half the secondary. Hence the
ratio of primary to full secondary is 64.
·
·
·
Brid~ rectifier :
l
vo(pcat)
= 9v
:. Peak secondary voltage
.. RMS secondary voltage
=
=
..
=
Transformer turns ratio
9 +. (2 x 0.7)
=10.4 V '
r./2 =7.35 V
10.4 ·v
N 1 220
·
~=7.35= 29.91
.••Aris.
IMfi•€1
Q. 17 Explain bridge rectifier circuit.
Ani.:
.
The circuit configuration o{ bridg~ rectifier is as sbo~ in
Fig. 10.10. It consists of four diodes c_?nnected ~ :rm~r::=~
The center tapped input transformer ts not reqwr ·
transformer T shown in Fig. 10.10 is a step down transformdert.
I
tifi ti
The diodes con uc
.
B
. ridge rectifier offers full wave rec. ca on. · of diodes either
1D pairs i.e. at any given instant of tune, one patr
DJ D2 or D3 D4 will be conducting.
·
(B-109) Fig.
10.11: Waveforms for the bridge rectifier
Q.18 Whatarethe advantages of bridge rectifier ?
Ans.: The advantages of bridge rectifier are as follows,
I.
It requires a smaU size transformer. Center tap transformer
is not required. This ·makes the bridge rectifier cost
effective.
2.
High average output voltage
3.
Rectifier efficiency TJ is high
4.
Transformer utilization factor TUF is high.
Q. 19 State disadvantages of Bridge RectHier.
Ana.: Disadvantages of bridge rectifier are as follows ,
1.
The number of diodes used is four instead of two for FWR.
2.
As two diodes conduct simultaneously, the voltage drop
across them increases and the output voltage reduces.
a. 20 List appllcaUona of B.rldge Rectifier •
(8.107) Fig.
tiller ctrcult
10.10: ~ brid&e rec
Ana.: Applications of bridge rectifier are as follows,
1.
Laboratory de power supplies.
2.
High current power supplies.
·3.
Battery charger.
4.
DC power supplies for various electronic circuits.
-
4-92
Electronic DeVICes & Circuits·! (Eiex.-MU)
compariao~ .of HWR , FWR and
rectifier. ·
Q . 21 Give
Bridge
AC input power,
Pac ==
3.
152rms X (R5 + 2Rp + RJ
2
.- (1,.1..J2) (Rs + 2Rp + RJ
-3)2
i 20·2 X2 lO X 2012-- 410 mW
Ana.:
·The com~son of the three rectifier circuits is as foiJows,
.· lJWR . FWll
' Sr. '
.. ~ter
- No.
.
J'eCtHiet .:·
.. ··/ l
.,
I.
DC or average
I,.
2 lm
load current (IL de)
1t
2.
Maximum average
load voltage VLde ·
3.
RMS load current
ILnns
4.
RMS load voltage
VLnns
5.
vm
__
2Vm,
2Vm
1t
1t
1t
Ym
'2
12
Maximum
rectification
efficiency (11)
7.
8.
9.
10.
vm
vm
~
~
41
: : RL
6.
~
1m
~
40 %
2
R
% efficiency
=
% regulation ==
4.
VNL ==
VFL ==
~
p
liC
X
331
100 =410 X 100 = 80.73 %••.Ans.
V
X 100
FL
2Vm ~ 2 X 40.65 25 .87 V
1t 1t
ILde X RL
..
2
41 R-L
~
1t
~
81.2%
81.2%
1t
-3
=12:86 X 10
X
...(6)
13
2 X 10
25.72 v
...(7)
25·8 ; 5 ·72 x 100 = 0.5832% ...Ans.
% regulation ==
7
=
Q. 23 What is a filter
i;
?
-
Ans. : Filter is connected after. J]Je rectifier to obtain a ripple free
or pure de voltage whereas voltage regulators are used to deliver a
constant d.c. voltage to the load.
..
· Q ; 24 What are types of filters ?
TUF
Ripple factor
Ripple frequency
28.7%
121 o/~
50Hz
Number of diodes
One
69.3%
48%
100
Hz
Two
81.2%
48%
100Hz
Four
used
Q . 22 A bridge rectifier Is applied with input from a step
do~ transformer having turns ratio 8:1 and input .
230 V, 50 Hz. If the diode forwar(J resistance is
1 0, secondary resistance is 1~ Q and load
resistance connected Is 2 kQ find :
1.
DC power output
2~
PIV across each diode
3.
% efficiency
4.
% regulation at full load.
Ana.: Giyen :
(a)
...(5)
Pac ==
Vm- Ve.
1t
I,
..
!1m
1t
Im
2
DC load power pde
..
.Brldae :·.•
Ans.: Filters are classified depending on the components used'and
depending ·on the configuration in which they are
connected. The important filter types are as follows :
1.
Capadtor input filter (shunt capacitor filter)
2.
Choke input filter (se!ies inductor filter)
3.
LC filter
1t type filter.
4.
RC filter
5.
Q. 25 Draw a circuit diagram of a f ull wave reetlfler wtth
C filter. Derive expression for ripple factor and
also explain the basic rectifier operation.
Dec. 08. May 10, May 11
Ans::
T~e
capacitor input filter ·is used to reduce the ripple
oi a. rectifier to obtain a pure de voltage. A
full wave rectifier along Wltb a capacitor input filter is as shown in
Fig. 10.12."C" is the filter capacitor which is connected across the
~oad· resistapce R.
con~ents· m th~ output
C<tnllttoe> IIIIP
RMS secondary voltage,
down trllnolormot ..
-.§.)
(..· ·~
N - 1
1
V5 rms = gX 230 = 28.75 V
A.
...(1)
. ,..,_
5
Z4tN,
Peak secondary voltage,
Vm = ..J2 V 5 nns = -{2 X 28.75 = 40.65 V
(c)
Peak load current,
vm
40.65
20 2
lu, = <RS + 2Rp +RJ = .(10 + 2 + 2000) = · rnA
L
-o:
-~v
_Q_
"'II .
(b)
(d) ·
...(3)
1t
....(4)
(b) FWR witil capacitor input
filter
D.C. load p<)wer,
2
=
331 mW
PIV across each diQde = Vm =40.65 V
eas v -so luJtons
(F-1093) Fig.
!be
10.12
fil~r capacitor is connected ·across (in shunt with) the
load, this filter ts called as shunt capacitor filter.
1t
-3 2
3
PLdc = ~dcxRL=( 12.86xlO ) x2x10
2
(a) Connection of filter
capacitor
D.C. load current,
ILdc = 21m = 2 X 20.2 - 12.86 mA
1
...(2)
...Ans.
•••Ans.
I
r:rectronic Devices & Circuits-! (EI
ex.-M U)
"'
.......-
operation of FWR with a Shunt Ca
4-93
Fig. 10.13 shows the waver.
P&cltor Filter :
0
various intervals have been shown. ~rm ~ load voltage with th
.
V perauon of the FWR w·th e c~acttor filter. Along with the waveforms the equivalent circuit:> for
1
o
capacitor filter is given in four different intervals.
Voltage
across C or load voltage
l
Cctwges
0-A
throughD2
Ccharges
through
o1
c discharges
o--+--...J -
(F-l094)
through RL
A-B
Fig. 10.13: Load voltage wavefonn and equivalent circuits ofFWR with a capacitor filter
OperatiOn in the interval 0 to A :
The initial voltage on capacitor "C" is assumed to be zero.
IIi the first positive half cycle of the supply, D 1 is forward biased
and starts conducting. 0 2 is reverse biased and acts as an open
switch. Diode 0 1 supplies for the charging current of the capacitor
and the load current.
Capacitor starts charging through D 1 and at the end of this
interval i.e. at "A" it charges to the peak value of secondary
voltage i.e. "Vm".
:. At "A", voltage on C i.e. V c = V m
After point "A" the instantaneous secondary. voltage s~s
reducing as shown by the dotted wave~onn of rectifier ~~t~.ut tn
Fig. 10.13. This will reverse bias the diode D 1• hence a~ A • ~e
diode D is blmed off. The equivalent circuit for this mterval IS
1
diode 0 2 starts conducting at instant B. The capacitor charges
through 0 2 and at the end of this interval i.e. at point "C", the
voltage on capacitor is again equal to +Vm· Due to this D 2 is
reverse biased and stops conducting at point "C" as shown in
Fig. 10.13. The equivalent circuit for this interval is shown in
Fig. 10.13.
Operation in the interval C to D :
The pperation in .this interval is identical to that in the
interval A to B.
Expression for the I.Upple Factor :
To obtain the expression for ripple factor of the output
voltage using a capacitor filter, refer to the two waveforms drawn
in Fig. 10.14(a) and (b). To simplify the mathematics , assuming
that ripple has a triangular shape.
shown in Fig. 10.13.
Operation in the interval A to B :
During this interval voltage on the capacitor is higher than
.
'
· ) H nee D and D both
2
rectifier output (shown by dotted lines · e . 1
remain off. The capacitor discharges exponentially through the
load resistance Rr_.
.
her than R the capacttor
A$ the value of RL is roueh hig
. "R
y alue of C
dischar
1 1 o· h o1ng time constant 1s L •
.
ges sow y. tsc aro~·
, bar ·n time constant as
C"
IS very large in order to make the diS~
gtC:ntent in the output
1
large as possible. This wil~ ~uce the. nrz:rval is shown in Fig.
Voltage. The equivalent ctremt for this
10.13.
voltage
·..,._ Reotlfler
\.,_ OU1put
~~·· .
Q•L-~~T
~,~.:~,---T-2~~:~~--~----------~----.
:.-T/2-l
(a) Load voltage waveform for a full wave rectifier with
capacitor input filter
(F-1097)
Operation in the interval B to C :
· equal to the
_ ,.u'fied voltage ts
At "B" the instantaneous.:~ .
r than c· Therefore
Voltage on capacitor and after "B tt IS greate
'Cis·eas v- s olut• o n s
OutpUt
v
Fig. 10.14contd•••••••
Electronic Devices & Clrcuha-1 (Eiex.-MU)
A-t- the RMS value or ripple voltage (V___ , •
T 0 ObUIUI
•
XIIIIY •
triangular ripple voltage shown m Fig. 10.14(b),
For a..__. formula which states the RMS value of ripPle
Step 2 :
Using a StanUlUu
voltage. It is given by,
v,
V RMS
...(10)
= 'J:\[3
· Substituting the expression for V, from Equation (9) to get,
V RMS
(b) Triangular approximation of ripple voltage
(F-10J7)
Step 3 :
T2• T 1 <<<T2 tbelefure (1fl) =(1 1 + 1 2 ) =12•
Peak to peak ripple voltage is V, Volts.
Derivation :
RF = VRMS
...(1)
VLclc
Where VRMS
RMS value of the ripple voltage
and V Lclc
Average value of the load voltage.
The steps to be followed are as follows :
=
=
To obtain peak to peak ripple voltage Vr
:
Capacitor discharges through load R during the time
interval 1 2• The charge lost by the capacitor during this period is
given by:
1
...(2)
Q = cv,
The discharge current
= ·!!Q
dt
...(3)
T2
f
VLdc
4~fCRVLdc
= Y;:'
1
_,.;
.. RF -
...(12)
4v3fCR
· This is the ripple factor for a full wave '!f bridge ~fier
circuit. For the half wave rectifier the expresston for RF ts as
follows:
1
...(13)
· RFforHWR
l~fCR
=
The ripple factor is defined as,
... Q =
(11)
VRMS
The capacitor charges linearly during period 1 1 aild
discbarges linearly during the period 1 2 as shown in Fig. 10.14(b).
The balf cycle period is ''Tfl" which is equal to the sum of 1j and
i
..
4 3fCR
-
To obtain the ripple ractor :
Fig. 10.14
RF
Step 1 :
Jj "'
-
...(4)
idt=ll..dc 12
The ripple factor is denoted by "r''·
Q, 26 Explain HWR with shunt capacitor filter •
Ans. : The circuit diagram of a HWR with capacitor filter is as
shown in Fig. l0.15(a) and the load voltage waveform along with
the equivalent circuits is shown in Fig. 10.15(b).
Operation and waverorms :
For the intervals 0 to A, B to C the diode is forward biased
and the capacitor charges through the diode almost instantly. For
the intervals A to B, C to D etc. the capacitor voltage is higher than
the instantaneous secondary voltage. Hence the diode is off and tbe
capacitor discharges through RL slowly. The discharging time with
HWR is longer than that with the FWR. Hence the capacitor
discharges to a lower voltage [point B or D in _Fig. 10.15 (b)].
Hence the ripple increases. So the. ripple factor of this circuit is
higher than that of the capacitor filter with FWR.
D
0
This is because the integration gives you the average i.e. de
value. Substituting the value of Q in Equation (2) to get :
1uc T2 = C V,
1L.x T2
v, = c
Hence
...(5)
...(6)
p='.:c LON
. ."II
-~N ·.·
~~~----~----~~~
But T1 << T2 , therefore substituting 1 2 =(T/2)
.. 1z
= I2
But T
=f
1
:. T2
=
B
(a) HWR with capacitor filter
Fig.to.ts
.
where f is the supply frequency.
1
2f
...(7)
Substituting this value in Equation (6) to get,
ILc~c T
JLdc
v, = c-x2 =uc
...(8)
But the average load current
JLc~c
..
This
~
.
Vr
=
,Yu;
R
=~
2fCR
... (9)
tbe required expression for peak to peak ripple
voltage V,.
OloA
;.. loB.
(F-1101) Fla. lO.lS(b) :
Waveform and equivalent circui~ for a
HWR with capacitor ftlter
1:
a!, v •, u11111 1111 s
~ic Devices & Circults-1 (Eiex.-MU)
4-95
Q. rT Wlult ....
.,.._:
advantage.
capecttor Input ftltw ?
and dlaactvantagea of
1be .tvantages of a capacitor input filte
.
Easy to design
r are as follows :
1
R(load)
2.
Rcductioo in tbe ripple COOte
3.
4.
locrease in the average load voltag
Small size aod low cost
e.
wavefoml
nt of the output voltage
02
~ (Umltatlona):
<F·IUI8) Fig. 10.17: Full wave rectifter with tbe inductor ftlter
1be diSIIdvantages of a capacitor input filte
.
1.
Ripple factor is dependent on the ~
are·
2.
Regulation is relatively poor.
·
3.
Diodes have to handle large peak currents.
1
Operation of the Circuit :
The diodes D 1 and D2 conduct alternately in the positive
and negative half cycles to jlroduce a unidirectional current through
the load. Due to the inclusion of inductor L in series with the load.
the current ripple reduces to a great extent and the load current is
smooth as shown in Fig. 10.18. Higher the value of inductor is,
lower will be the peak to peak ripple in the load current waveform.
The load voltage waveform is same as .the load current waveform.
(F-lU)9) Fig. 10.18
: Output current.waveform for the inductor
filter
<F-1140) Fig.10.16
EXpression for the Ripple Factor :
Ripple factor on oo load :
On no load, load resistance R.= oo and load current is zero.
4oh}
Ans.:
VLdc =
=
:. vLdc=
VLdc =
~=
~usc
Vm-4fc
20
:. ~
100 X 10- 3 ·
4 X 50 X 1000 X 10- 6 20-0.5
=
v
Iuscx ~
vl.dc
.. RF on no load
19.5
19.5
lusc = 100 x 10... 3
..
195 n
RP
.
= 3-/2 OOL
...(1)
0
...(2)
Q. 30 State ·advantages and disadvantages of series
Inductor filter.
V, = 2fCR
Ana.:
!9.5
= 2X50.X 1000 X 10- 6 x 195
V, = 1 v This is ripple voltage at the output.
1
1
~
ooo x 10-6 x 195-67·54
4.../3fCR-4xv3 xSOx l
-
- r;
R.P. :: 0.014 or 1.48 %
This is the ripple factor.
Q. 28 Explain operation of full wave rectifier with the
Inductor filter and give the expression for the
ripple factor.
AM.
2
= 3 '\[2 =0.472 =47.2%
Ripple factor on load :
l R
vl.dc
R.p· --
~o
.
Advantages of series Inductor filter are as follows,
1.
Low ripple factor at heavy load currents.
2.
No surge current through the diode.
3.
Reduces ripple in the output
Disadvantages :
1.
It is bulky.
2.
It is more costly.
3.
Ripple factor is poor at light loads (small load current).
4.
Audible noise (bum) is produced.
:Tbe inductor filter is as shown in Fig. 10.17. An mductor
Q. 31 Draw a circuit diagram of a full wave rectifier with
in series with the load R. The
(choke) L
•
.
is that it opposes any change m
property of an inductOI' .
-·--" be to reduce current
current through it is beang uac;u re
ripple iD the outpUt of the rectifier. .
LC filter. Derive expreaalon for ripple factor and
an output voltage. Explain the bale rectifier
operation.
•
_ ----A•AA
15 ~
Dec 03. Dec. 05. M<1y 06. 10. r,1<ly 08. Dec 10
4-96
E1ectronlo Devtces & Circuita-l (Eiex.-MU)
sea
2V
AM.:
The cimlit diagram for an LC filter used with a full wave
Rlctifier is as shown in Fig. 10.19. This is a combination of
inductor filter and a capacitor input filter. Inductor filter is
pre&rmd for low values of R and the capecitor input filter is
~ for high \'alues of load resistance. The L.C. filter can give
low ripple factor irrespective of the load as it is a combination of
cbe CWO filters.
vln
==
4Vm
___!! -
n
- 3 cos 2 c.ot
Ste 2 :
To obtain the de voltage acroa the load :
P The de current in the circuit is given by,
IL de
=
2Vrrf1t
<Rc + Rp)
...(3)
Where , Rp = R II Ra
Therefore the de voltage developed across the load is given by,
·
VLdc
=
rc
==
1\: .. oc .........""" ol L
Ae .. a-lar reelllance
...(2)
n
2Vm
ILdc X Rp
n[
l
=1t (_Rc+ Rp) X Rp
...(4)
+~]
But Rc « Rp therefore Equation (4) gets modified to,
<F· Ill'l F1g. 10.19 : FuU wave rectifter with LC filter
The series connected inductor offers a high reactance to the
t.mooic components (ripple) ·in the output and attenuates them
and die parallel capacitor provides a low reactance by pass path for
diem. This wiU reduce the ripple further.
Role of the bleeder realstance (Ra) :
The resistance Rs connected across the capacitor is called
as bl.eelb resistance. It is used to maintain a continuous current
through tbe filter inductance L. H the current through L is not
cooti:nuous i.e. if it is interrupted then a large b;u:k emf (L di/dt)
will be developed across the inductor. This voltage may exceed the
PIV rating of the rectifier diodes and damage them. This voltage
may exceed the maximum rated voltage of the capacitor as well.
Reoce lbe induced back emf is dangerous for diodes as well as the
capacit«. 1be back emf wiU not appear if the current through L is
cootiDUous. Rs will maintain a continuous current through L. .
WfNeforrna:
1be input output waveforms of the LC filter with full wave
Jrdifier are as shown in Fig. 10.20.
·
2Vm
V Ldc
... (5)
=7
Step 3 :
To obtain the RMS value of ripple :
From Equation (2) the peak value of second harmonic component
ofVin is given by,
Peak value of second harmonic,
4Vm
vm2 = 31t
...(6)
Therefore the peak value of second harmonic current is given by
l,a
vm2
= z;.-
....(7)
Where Zz = Impedance offered by the filter circuit at second
harmonic frequency.
Zz
J
..
= Rc + j2o:IL + G2~ II ~
(8)
But j~C « Rp and Rc << j2o:IL. Therefore the above equation
can be written as :
Zz = j 2IDL
Substituting this value in Equation (7) to get,
~
...(9-)
4Vm
=
...( 10)
31t X j 2roL
Therefore the second harmonic voltage across the load is,
Second harmonic voltage across load =1ua x
1
But j2<oC «
<J'· lll1) Fig. 10.20 : Input output voltage waveforms of
anLCftlter
Stet 1 :
To nprea~ the lo8d voltage In fourier series form :
1be output voltage of a fuU wave rectifier which acts as an
iJipul voltage to lbe filter can be expressed using the fourier series
Via •
zv. 4V.
4Vm
7 - "3,t' eo& 2 wt - IS 1t cos 4 Cl>t
'I ' , ~
', II 11111 11 II ',
Rp. Therefore their parallel combination is
Second harmonic voltage across load =I.ta x
Substituting the value of ~ to get,
Second harmonic voltage across the load
2Vm
1
V
= 3;t(;)L x 'iroC
...(1)
Wbete V• I;< maxiowm value of half secondary voltage.
1be tint term io Bquatioo (I ) repre~ents the de or average value of
tbe ouapw. IC008d ttnn repteaents the sec.ond harmonic, third one
~ tbe fowtb barJDoQic and 10 oo. Nesloctina aU the hiaher
order ~y romponeatl except the second harmonic ,
,.
J
11 Rp
.
1
1
approxunatc y equal to j roC .
2
Exp eeelon for the Ripple Factor :
u!oUow• :
G~
.~
J
=3 1tO);LC
...( ll)
But this is the peak value. To calculate the ripple factor we need
rms value.
· · RMS second harmonic voltage across load
= ~21tm"LC
V•.
...(12)
gectronic Oevlces & Circults-1(Eie>c.·MU)
seep 4 :
4-97
To obtain exp~n .,_
RMS
•vr the ripple factor .
RF
I Jn
r "" ~[
3 4 alLC
Here n =2 (number of L section)
StX'Ond harmonic voltage across lou~
VLdo:
=
vm
= JV
-1.'2 2 X ~.dtm LC 2 Vm-
I
6 -{2. ro2 LC
...(JJ)
·
&advantages of LC Fllte
.
A~:
resiStance.
~[4
.. r
~
VL
=
2 vm
'It -Il...dcR
Where R =(Rs + Rp + Rc)
But the values of Rs, Rp and Rc are not known.
.. v" =
VL
3.
=
2Vm _2.J2x100
7t
7t
90Volts
AC ripple :
Ripple factor r
:. ACripple
._ AC rlpple
v~..
=
-3
r X V L =1.038 X 10 X 90
0.09342 Volts
Vo
:. Lc
'
~
:. Lc
(F-1123) Fig. "10.21
1be double stage is being used in order to improve the
·
quality offiltering.
1be ripple factor of a two stage LC filter is
2
L 1 =L2 , C 1 :::;C2
This shows that ripple factor reduces i.e. gets improved due
to the use of two sections instead of one.
=
=
.
3
500
x 27t x 50
0.5305 ii
The given value of Lc = 2H. Hence the inductance is sufficient.
L...,;~-__._--+---'·········...J.. a. 35
a. 34
1000(;1
The value of L is sufficient if Lc = 3(1)
... . . .. . l.
f [(li~c] ....
Z7 X
3
1.038 X 10-
.
Ans.:Tbe double section L.C filter is shown in Fig. 10.21.
r =
=
X 47t2 X 50z! 2 X
DC load voltage
2.
Draw double section LC Filter. What Is the ripple
factor of a two stage LC filter?
RL ·
= ~ [4 x (2~f);::cJ
~
Actventagea ~f LC filter :
I.
Very good load regulation
2.
Ripple factor is low and d~s n0 t d
.3.
This filter is suitable for light
e r;end on the l~d.
4
Diodes do not h
as we1 as heavy loads.
.
ave to cany surge currents.
Disadvantages of LC Filter :
I.
Audiable noise (hwn) is produced b th .
Du
Y e mductor
2.
e to the use of large value L d C
.
circuit becomes costly. .
an
components the
3.
Due to the USe of inductor the filter is bulky
4Bleeder resistan ·
· .·
ce mcreases the rating of rectifi : ·
5
Power loss tak
I
er cucwt.
.
.
es p ace in the series inductor L due to its de
a. 33
.. r
Sta.. ltdvantagea and dl · ·
Q, 32
Draw a circuit diagram of a full wave rectifier with
7t filter. Derive expressions for ripple factor.
Explain the basic rectifier operation.
16@d•fi
Ans. : The 'It-type filter which is a combination of capacitor input
·
filter and LC filter is as shown in Fig. 10.23. It consists of
two capacitors C1 and Cz along with the inductance L.
Generally both the capacitors are of same value.
~~. - ' - - FWR---+-- Ftlter---41~
L .
In the circuit shown In· Fig. 10.22 determine the de.
load voltage
ac ripple in the output and verify
that the given Inductance value Is sufficient.
Derive necessary expressions. ·
v'-'
(F-1128> Fig. 10.23 :
c, • c2 • 27,F
()1'-UU> Fig. 10.22
Ana. :The .gJVeD
.
. 't 's a multiple section LC filter. Its ripple
CJJ'CU1 I
.
).
factor is given by,
1: a ~. II
s
U I II I I ll II S
n type filter with run wave rectifier
A 'It-type filter can be considered as a combination of shunt
capacitor filter and LC filter. This improves the effectiveness of the
'It-type filter as far as filtering of ripple is concerned. Due to the use
of thre~ filtering elements (C 1, Land C2), the ripple factor of the 'Ittype filter is very low as compared to the other filters. The
capacitors C 1 and G.z provide a low reactance path for the ripple
whereas the series inductor L provides a high reactance to the ac
ripple. The combined effect of this is the reduction in ripple, and
improvement in the output waveform.
...
--
4-98
Electronic Devices & Circuits· l (Eiex.-MU)
ll..de
tnput •nd Output Vottege Wavefonna :
1
=RL
But -VIAe
:. Ripple factor,
Vollagot 801'00111 Cor loed vollnQe
1
.
AecUIIed
'····./output
\ •..
\\
oL---------~w~--------~2.~--------~~~
<F-1131) Fig.
10.24 : Input and output waveforms of n ftlter
El(J)I'eSSlon for Ripple Factor :
The nns value . Qf ripple voltage at the output of th~
capacitor input filter C 1 with a full wave rectifier is given by·: .
y .
v
--j:;
... (1)
=
.....
2 -v 3
=
Where v r
Peak to peak ripple.
The peak to peale ripple voltage for a fu]J wa~e rectifier is
given by,
lLdc
.:.(2)
v. = 2 fC 1
v
ILclc
""' -- 4V3 fC,
...( 3)
This is the ripple voltage at the input of the L-C filter.
Tbe rms ripple voltage. at the output of the LC filter LC2·is
given by:
v
·Xo
XcXo
vi'Dl$
=
""'
..
v
rms
:..( 4)
v rms
=
...( 5)
(XL/Xo) - -1
But XL =
w, L and XC2
. .(
1
10)
..j3f(w:LC
C
RJ
ForFWR
.
2
1
4
. . h
pre·ssion for ripple factor w1th a full wave
This JS t e ex
.
· 1 f
f
.
. . 1 the expresston for the npp e actor o a half
rectifier. Sulll1ar Y
wave -rectifier is :
=
r
I
1·
...( 11)
ForHWR .
h t are the advantages and disadvantages of n
Q. 36 W a .
type filter ?
. Advantages
. of n type fitter are as follows ,
Ans..
1.
Same as those of shunt capacitor fi~ter.
2.
3.
Substituting Equation (2) into ( 1) to get,
I
Rearrangjng,
In addition to that the ripple facto-r IS very low.
High de voltJ,ge (approxirruitely V m>
Disadvantages :
. 1.
2:
3.
. It is bulky due to use of inductance.
Costly due to more number of components.
Current rating of choke needs to be high.
Q. 37. In the ·circuit shown ·in Fig. 10.25 determine
d.cJoad voltage VL, an ac ripple In the output,
verify that the given filter .is sufficient low ripple
· voltage. Derive necessary expression.
lli!JJN•EI
= w,1r'-'2., considering
the second
.
·...,
harmonic frequency w, = 2 w.
Substituting these values and the value of V rms from
Equation (3) into Equation (5) to get,
ILdc
v
-
.
4...{3 fC1 [w, L x w, ~ -1]
rms -
where
w, =
=
.
ro, is the angular ripple frequency. That means
2 1t f,
where, fr= 2
X
(F-im>Fig.l0.2S
50= 100Hz
2
4-../3fC1 [w .LC:z-1]
. ...( 6) .
Ans.:
Step I:
To find DC load voltage :
2Vm
VLdc = __
2
for w LC2 >> 1 ,
1t
JLdc
v,..
... ( 7)
VLdc
The ripple factor is defined as
Rms value of the ripple voltage across the load
r
=
Step II:
Vr
r
=
ILdc
1t
v Ldc =45.0158 v
= 2 "./3
= Ildc
2 fC
.
.
(for a ca~acitor filtt:r)
1
I~
I
from Equation (7) to get
x...J2 x50
vr
V rms
...( 8)
nns
2
To derive expression for Ripple factor ;
Average vol~ge across the load
Substituting lhe expression for V
.=
..
v rms = 4 "./3 rc,
is the ripple at input ofLC ftlter.
The rms ripple voltage at output of LC filter L<; is,
r. .t ,, II
• Ill II II fillS
_:!ectronic Devices & Circuits-! (Eiex.-MU)
4-99
Ana. :
The block diagram of a regulated power supply is as shown .
in Fig. 10.26.
~.....___Unregulated _ _ _ . . J
~power
supply-.,
(F·10l3>Fig. 10.26 : Block diagram of a regulated power supply
Q. 40 Deflne : Load regulation :
.. vrms
'
=
Ripple factor =
..
But
4V3 fC
v'nns.
·%L.R.
ILdc
4V3 fCI (~2 L~) v Ldc
ILdc
.!..
=
R.F.=
4
V33 fw LC
1
c; RL
2
2
X
•
Across the
In series
lOad
with the
Slilable for
light load
applications
load.
Heavy load
applicatiOnS.
ExJlreaeion
taca
4-.fi fCR
CUTent
llrot9l
cildes
brp
1.
Size oilier
~
Cel
charger,
smal
N;ross the
load
r=
_lL
~rol
(ro LC1 Cz RL)
fN2oAc 2-/31
ForFWR
B~
BulkY
Bulky
High current
de power
supplieS
DC poWer
DC power supplies
aupply
f:
a ~. II · '• II Ill I
.
.
42 Define : Source Regulation
Ana. : The source regulation (SR) is defined as ~ change in
regulated .load voltage due to change in line voltage in a
specifiedrange of 230 V ± 10%.
State types of voltage regulators :.
Dec. 10. May 11. May 15. Dec. 12. May 16. Dec 16
Low
·Ana. : The voltage across a zener diode remains constant equal to
Vz when it is operated in the "zener region" Qf the reverse
characteristics (Fig. 10.27(a)). This fact is utilized in the
application of the zeiler diode as a voltage regulator.
2
lated de power
.
l
~
T,. . . . .... . . . . . . . . . ......
---
(a) Reverse cbarac:terlstks .of a
· zeuer diode
~
~·· ~· t
J..
_.__..;.J.. . . .
....(Ytol
___
(b) Regulator dmlit using.
<B·136) Fig. 10.27
I II II ~
.
·zener diode as voltage regulator.
suppHes
Q. 39 Draw the bloCk dJ«tgram of a regu
Vol
Q. 44 Explain characteristics of zener diode. Explain
RF=
R
RF=
100
Ans.:
'l'be two' most widely used types of voltage regulators are :
1.
Shunt voltage regulator .
·
2. · Series voltage regulator
All loads
Low and
need not be·
controlled.
X
ll IL Constant V in and constant temperature
Q.
Ughtas
well as
heavy
loads
Low and
need not
be
controlled.
ellrmlators
fl.
ll
1
.
47 X 10- 6 x 47 X 10- 6 x 1 X 1000
Q. 43
Veryhigl
and must
be
controlled
RF=
V
1
Ana.:
&.ge
VNL-Vfl.
Ana. :The output resistance of a power supply is defined as the
ratio of change in output voltage to the change in load
.current, if. input voltage V in and temperature are held
constant
Compare L-sectlon LC filter , Choke Input fitter ,C
filter and 1t type filter.
{I•AIM
Place of
=
Q. 41 .Define: Output Resistance (RJ of power supply•
RL
4 3 X 50 X (21t X 50)
=0.0132
R.F. = 1.32%
Q. 38
The load regulation (L.R.) is defined as the change in
output voltage when the load current is changed from zero {no
load) to maximum (full load) value.
·
w2 L~
VLdc
V3
llF.
1
R.F, =
VIAe
.
Ana.:
ILdc
zener diode
Regulating Action with • Val)flng Loa~ (VJn Constant) :
Operation of the z.ner rwgulator :
The input voltage V1n is an unregulated de voltage which is
obtained from a rectifier filter combination. R, is the current
limiting resistor and ~ is the load resistor. The input voltage V1n
sbou.ld always be higher than the breakdown voltage V,. Tbe
circuit diagram of Fig. 10.27(b) shows tlmt the zener diode is
reverse biased and operates in the zener region of the reverse
characteristics. lf Vtn is higher than V• and if the zener current I. is
between l z lllln and ~ max then the voltage across the zener will
remain constant equal to V • irrespective of any changes in V1n and
~· As the output voltage is constant and equal to V •' to get a
regulated output voltage. Zener current ~ should not be higher than
I.. m~a· otherwise excessive power dissipation will damage the zener
diode.
I.. should not be less than ~min either because then the zener
diode cannot operate in the zener region and cannot maintain a
constant voltage across it. The regulator should keep the load
voltage constant inspite of changes in input voltage and load
current.
Regulating Action With a Varying Input Vohage
(Constan~
1J:
Assuming tha~ the load resistance RL is constant and V in is
vazying (Fig. l0.28(a)). As RL is con,s~t, IL is also coiistailt
because IL
V/ RL. But supply current keeps changing due to
change in Via as,
.
=
Vm- V,
I =
-
4-100
Electronic Devices & Circuits-! (Etex.-MU)
Assuming that the input voltage IS .constant and load
resistorRL is variable. IfRL increases then IL wlll decrease. But the
total current I is constant as :
I
=
V10 - Vz
...(1)
Therefore. with decrease in IL, the zener current ~ win
increase. This can continue without damaging the zener. diode, as
long as ~ is Jess than. I.. max• and the output vol~ge ~Ill remain
constant. If RL is reduced, 1L ipcreases. But as 1 IS constant, the
zener current will decrease. The output voltage will remain
constant as long as 1, is higher than I.. min' ~us the output voltage
remains constant as long _as the zener current IS between ~min and ~
max'
Q. 45 Whatare the limitations of zener regulators
?
Ans.:
Even though the zener diode provides a very simple means
of ·voltage regulation, these regulators have following
disadvantages :
_
The output voltage of zener regulator is equal to V•. This is
a constant voltage. Therefore these voltage regulator
cannot.provide as adjustable regulated output voltage.
Large power gets dissipated in the series resistor R_,.
2.
i. ·
Q,46 State merits of zener regulator .
Ans.:
Merits of zener regulator are as follows ,
R.
Also I = ~+IL
Rs
····•
IL (constant
1.
2.
3..
Simple circuits~
Only 2 or 3 components are required to be used.
Low cost. .
Q. 4? State applications of z~ner regulator :
Ans. :Applications of zener regulator are as follows ,
1.
2.
(a) Regulation action with a varying input voltage
In the emitter follower regulator.
· As a low cost, regulator with a small load current range
over which V 0 remains constant.
Q. 48 Design a zener voltage regulator for the following
I( constant)
····• .
=
specifications, V1n 20 ± 2 Volts, Output voltage
Yo ·6 V, Load current IL :: 50 mA, 1z (min)
5 rnA,
Zener wattage Pz 0.5 Watts.
=
vin
constant)
Ans.: Given :
=
=
V in (min) -18V
'
vin (max) =22V•vo =6V•
IL =50 rnA, I.. (min>= 5 mA andJ>,
=0.5 W
(b) Regulation action with a varying load resistance
(B-137) Fig.
10.28
If Via is increased, then current I will increase. But ·as V• is
c.oostant an(J RL is also constant, the load current IL wili remain
Step 1 :
To calculate Is (max) :
::._ 0.5 .
Vz = 6 = 83.33 mA
...(1)
constant. Naturally the increase in current "I" will increase the
Step 2 :
To calculate £'1(mln).
v
•
zener current ~· This can continue Juumlessly as long as 12 is less
. When ~ = R s (min)• the source current .J can become
than Jzmu· If V.u, is decreased, I will decrease causing Jz to decrease
maxtmum
corresponding to V in v in (owi>· As the ioad current is
as V.._, and IL are constant. The load voltage will continue to be
constant,
this
.increased source current will flow through tbe zener.
equal to V1 as long as It is higher than Iz min· The zener regulator ·
'!herefore
the
value of .R, <min; should be such that even when
with variable input voltage is shown in Fig. J0.28(a). Thus the
vin
=
in
(max)•
the
zener current ~ ~I.. (max).
output voltage V 0 will remain constant as long as tb~ zener cu~nt
is maintained between Jzmill and lz 0111 • As soon us tt goes outstde
vin(max) - vz
(min)
= [I T
)
•••(2)
these limits, the output voltage will not remain co nstant.
L +": (max)
1z(max) =
=
v
''
I!:ISV-SIIIIIIIOIIS
J\
£!eotronlc Devices & Circuita-l (Eiex.·MU)
4-101
Rl(IDII\)
21 - 6
ae T.s~~~~-( 0 + 83.33] X 10" ~ • 120 .Q
To calculate D. .. .. (1111•).•
''
...Ans.
SteP 3 :
When R"
R, <max) the source c
...inimum corresponding to v
y
urrent I can become
u•
In "'
1
As [ ·
should be taken to ensure thut 1, ~ 1 " <1111"'' • t. 18 constant, cure
V • t.(mln)'
=
,
R. . .
••
emu)
R
••
a(max)
=
=
V.,
[I + 1
]
ln(mln) -
l.
...(3)
'1- (111111)
18 - 6
[50 + 5]
· X to-·;-:r· = 2LS.i8.0.
Tran•former tum• ratio :
vnnn• = 12 Volts given
But
VOntiJI
where V.,
..
v.rm.
Nl = VI nns ~ 230 = 19_166
Nz
Vtrms
12
Thus R ;::: 120 0 and R !:0 218.2 .0.. So, select R = 180 .0..
Ana.:
Sr. R.edltler
'
No.
Its function is to convert
l.
2.
lteaulator
Its function is to maintai~
the output voltage constant.
Output voltage waveform
is pulsating de.
Output voltage waveform is
pure de.
(8·~43)
(D-144)
1
Poor voltage regulation.
V~ry g~ voltage
regulation.
4.
Made of _
diodes.
ContaitJS devices such as
transistor, zener diode.
5.
Types : HWR, FWCT,
Bridge rectifiers. ·
Types : Series or shunt
regulators.
The output voltage varies
to a great extent with
changes in vln• ll. or
temperature.
The output voltage remains
constant irrespective of
changes in vin• IL and
temperature.
Q, 50 Draw a center tapped transformer configuration to
proctuce - 12 V rms Volts at the output of a full
wave. rectifier. Connect a zener diode clrpult to
the o~JWut of this circuit to SU!)PIY a load current .
of 10 .m A at 6V to a load resistance. Calculate
values of all the components shown In your
. .
l•l§•t.l
circuit.
Ana. : Part 1: Full wave rectifier circuit .
. ·
The ce~ter tapped transformer configurauon With full wave
rectifier·is shown in Fig. 10.29.
Vz::6V
L-----41---- +
Dz
m.. 10 29 1 Requited circuit
•
.
.
.
(li'·l:l71) .....
t: a :. V
'i 11 Ill I I II II S
P~ = V~ Iz <max)
T<
"z max) = p z 1 Vz =500 mW/6V = 83.33 rnA
..
Assuming lz<n~n) = 5 mA
Resistance R8 :
Curreni through Rs = Iz (min) + I~ =Is
. . Is = 5 mA + lO mA = 15 mA
Average output voltage of the rectifier
2Vm
3.
230V
50Hz
....An5.
Selection of zeoer diode :
The zener diode vqltage be Vz = 6 V.
· Assuming the maximum zener power dissipation Pz = 500 m~.
..
Vo
·V'\r('''
6.
.•.Ans.
.. Tninsformer turns ratio = 1~.166
PIV of diodes:,
· PIV = 2Vm=2x~xv.rms
= 2·x-{2 x 12 = 33.94 Volts
''
ac input to de output.
Vo
Vml-{2
Peak secondary voltage
vm = -{2 X Vorms = 12 -{2
= secon!lary rms voltage
= Vmt-{2 = 12~1-{2 Volts
. . Primary to secondary turns ratio
..
...A·OS,
Q. 49 Give comparison of rectifier and regulator.
=
=
=
=
:. Rs
1t
2 ..J2 X 12
1t
10.8 Volts
8
= ~~ ~ =320 Q
Selecting the nearest but lower standard value.
Rs = 290Q
Power dissipation of
3
Rs . = I~ R8 =(15 X 10- ) 2 X 320
.. Pas = 72mW
. Hence selecting R8 as 1/4 Watts resistor.
...Ans.
...Ans.
...Ans.
a. 51
A full wave rectifier employing a center tapped
transformer has an output voltage of 15 volts.
Input supply is 240 Volts, 50 Hz. Load resistance
Is 750 0. Calculate transformer tums ratio. If a
zener regulator Is connected to this output to give
9 Volts at 10 mA calculate values of circuit
components.
Soln.:
G'ven :
V01 (av) = 15 Volts, Supply voltage= 240 V,
RL =750.0., V0 =9 Volts, IL =lOrnA
lfud•h
Step 1 : Draw the circuit diagram :
The circuit diagram of the rectifier with zener regulator is
shown in Fig. .10.30.
-
4-102
Electronic Devices & Circuhs-1 (Eiex.-MU)
Ant.:
1be transistor
shunt regulator as shown in
Pig. 10.31. The transi~r Q acts as a shunt control element It is
operated in its active reg1on.
Regulated
output voltage
vo
(F-U71)
Fig. 103o
Step l : c.Jcalate transtonner turns ratio : ·
Rectifier average output voltage \'01 <••> = 15 V ... given
__ _ 2Vm
But V ol (av)
(F-2045) Fig.10.31 :
Jt
Operation:
From Fig. 10.31 ,the output voltage is given by
vo = vz + VBE
...(1)
Vin is the unregulated de power supply sending a current I;
l:brough the current limiting re~istor R.
where Vm = Peak secondary voltage
:. 15 XJt = 2 Vm
Vm = 15 Jtl2 = 23.56 Volts
rms secondary voltage
=
V, rms
:. V,rms
=
Thms ratio
=
Regulation action :
..
The relation between input current, collector current and
load c~nt is as foUows :
Vm!..J2=23.56/...[2
16*66 Volts
N, 240 .
N = 16.66 = 14.4
2
...Ans.
Step 3 : Cakolate PIV of diodes D1 and D1 :
PIV of each diode
=
2 Vm =·2X 23.56 Volts
= 47.12 Volts
Step 4 : Select:ioo of ~ner diode :
AI. the required output voltage is 9 V, we select the zener
diode of V,_ = 9 V. Assuming the maximum power dissipation in
zeocr diode is P ,_ (IDaxJ =500 mW.
A.z(max)
= VzX~(max)
SOO X l0-.3
= vz .
9
~(laiD)
= 0~ 1 ~emu) = 0.1 x 55.55 = 5.55 mA
ButPz(mu)
T
••
p:t(max)
s : Selediot.of Rs : .
Total current through Rs =Is= ~<min>+ IL
..
Ji_ = V,_/RL=9V/7500=12mA
Is = 5.55 + 12= 17.55 mA
¥ 01 -V,.
HenceRs =
. . Rs
=
Is
15 - 9
- 17.55 x w- 3
341.88 Q
Selecting tbe nearest smaller standard value
3300
.. Rs '"'
.
...Ans.
Power dissipated in
Rs ::: ~ Jl., =(17.55 X 10- 3)2 X 341.88 =0.105 W
Hence chooie Rs to be 1/4 W resistor.
Q.
52 Explain the
regulator.
1:
a :. 'J
operation
', U Ill I I II II~
of
tranelator
~ ·= lc +IL
If the output voltage decreases due to any reason, then (Vz
·+ V0~ will also decrease. But V,. is constant so V8 E wiD decrease.
.This will reduce base current 18 of the transistor. This wiD reduce
the coUectOr current lc· So more current will flow througp the load
and the load voltage will increase. This will continue till the load
voltage reaches the desired level. If .the output voltage increases,
then exactly opposite action will take place to regulate the output
voltage.
Q. 53 What are the advantages and disadvantages of
transistor shunt regulator ?
Ana. :
Th¢ advantages -and disadvantages of transistor shunt regulator
are,
1.
It is possible to provide temperature coJDpensation without
My additional circuitry.
.
2.
Output resistance ~ is of low value. This is an imPortant
advantage.
·
3.
Better regul~on as compared to the simple zener
reg~ll~tor. !1'1s IS because, due to presence of transistor, the
vanations m 1z will be smaU.
4.
The only disadvantage is the high power· dissipation taking
place in the series resistor R, zener diode and transistor.
This reduces the efficiency of the circuit.
55.55 mA
Step
• But
Transistor shunt regulator
ehunt
Q! 54 Determine the regulated voltage and circuit
currents for Fig. 10.32 as shown In shunt
regulator.
"
Eectronic Devices & Circults-l (Eiex.·MU)
I5
4-103
330
This will increase the collector to emHter voltage VCE
across the transistor and V0 will be reduced till it reaches the
desired value. This is because,
v = vin - vt.E
...(2)
0
If the output voltage decreases, then exactly opposite action
will take place and the output ~oltage is increased till it reaches the
desired regulated value.
Q. 56 What ·are the limitations of emitter follower
voltage regulator .
Ans.: The limitations of emitter follower voltage regulator are as
<F-2053) Fig.10.32
Ans. :
Step 1 :
Output voltage :
Vo = Vz+VoE=10+0.7=10.7V
...Ans.
Step2:
...Ans.
are
- Q. 57 Determine output voltage and zener current for
V;-Vo 15-10.7
R =
33
== O.l3 A
Is =
. follows,
.
1.
The output voltage is not adjustable.
2.
There is no protection for the transistor if an accidental
short circuit takes place on the ·output side. Such a short
circuit will damage the ·transistor due to excessive power
dissipation.
3.
The output voltage is Vz .: VBE' Since both these voltages
temperature dependent, the output voltage will vary
with tempera~.
...Ans.
Is = IL + IC + Iz
13 =50
=
ButJC 13Iz
.. Is == IL + (l + 13}1z
:.· 0.13 = 0.107 + (1 +50) Iz
=
0.45 mA
And IC = 13~ =50 X 0.45 mA =22.5 mA
:. Iz
Ufi•Q
the circuit shown In Fig.10.34.
+
...Assume p =50
...Ans.
...Ans.
1k
Q. 55 Explain the operation of serieS voltage regulator
(Emitter Follower Regulator).
(F-1143> Fig:
Ans.: The basic series regulator (emitter follower regulator)
circuit is shown in Fig. 10.33.
The transistor Q acts as a control element. Because it is
connected in series with the load. this circuit is called as series
regulator. The transistor is operated in the active region and it ·is
call~ as series pass transistor. The circuit shown in Fig. 10.33 is
also called as emitter follower regulator.
.
A.n s.:
1.
Output voltage:
··~'"''''' '"":'""f
JAB
UnregiAated
Output current 10
v
= -R;_
10
f\
3.
=
.l
Vo
'---___._~--·" ' " "' " .1
. Io = 1+13-
8.9x w-3
51
=174.5~
Current through 200Q resistance :
V;.- V, 22-8.2
IR
200
200 = 69 mA
4.
=
5.
(F·:ZOSS>Fig. 10.33 : Emitter follower regulator
Operation of the circuit :
The series pass transistor operates ~n ~e emitter follower
configuration. Therefore the output voltage IS g•ven by,
.
vo =
?.9 mA
Base current :
Regulated
output voltage
YllltageVIn
=
Vz + V8 E =:= 8.2 + 0.7 = 8.9 Volts...·.Aos.
=IE :
8.9
.
=lk =8.9 mA
Vo
2.
. . IE
R
10.34
...(l)
V,-VBE
.
V" is the zener voltage therefore it is assumed . to be
constant Therefore if the output voltage varies, then there will be a
. .
change in V BE> because V, is constant.
Regulation action : If the output voltage mcreases due to
some reason, then vBE decreases ·(refer to' Equation (1)). Due to
reduction 1·n v
the base current . decreases. Therefore the
BE• · ·
collector cuirent decreases.
I! a:; V · s 0 Ill II II II S
Zenercurrent:
IR
. . Iz
=
=
IB+Iz
68.83 mA
:. 69
=
0.1745+Iz
... Aos.
Q. 58 Differentiate series and ,hunt regulators •
Ans.:
Serles
. . ftgulator
In parallel with load
transistor in the
regulator
In series with
load
·.
Electronic Devices & Clrcults-1 (Eiex.-MU)
I,
Sr•
.N~·····
Power
dissipation
in
current limiting
resistance
3.
voltage stability
factor
High
power Low power
· dissipation in
dissipation in R
R
r, +~e
(l + hre)R + (r, + ~J
Sv is high which is
good.
(r, +~JR
5.
o. 59
z
r.+~e
Active
What Is the maximum reverse voltage (PIV)
across a diode In :
1.
HWR
2.
FWR with center tapped transformer
3.
Bridge type rectifier.
·
Sv is low
which is bad.
(1 + hre)R+ (r, + ~J . (l+~J ··
~ is, low which is ~ is high
gbodo
· which is bad.
of
Region
transistor
operation
r,
Sv=[+R
~·=
Output
resistance
6.
Dec. 09. May 10. Dec. 10. Dec. 11
Ans.:
I.
2.
3.
HWR =Vm
FWR with center tapped.transform.er= 2Vm
. Bridge type rectifier.
=V m
Output voltage
Chatper 1.1 : Design of Electronic Circuits
0.1
Design a single stage RC coupled CE amplifier
using the transistor with the following
apeclflcationa of an amplifier . hht · - · 220,
. ht. = 2.7 leO, ~oe = h,.. = O.The amplifier mu~
have :
.
lAy I ~ 180, ~ -~ 10,' V0
fl!520 Hz. .
Calculate
designed.
~ and
Ay.
Ro
·I
2.
h,~ <&: II R1)
=oo
:.
=3 Volts. Vee= 18 V,
But
.
~e ·
.
But Rr_
:.
Rc II RL =Rc..
I Ay I
.I Ay 1
.
:. Rc
:. Rc
=3 Volts.
S;ro ~ 10,
Vex;= 18 V .
.>
180Xl\c ·
bee
~
For Va; > 10 V, the value of V E should be 5 _v.
:. VE
5v .
2.
Applying KVL to the output loop of Fig. 11.1,
Vex; = ~Rc+VCEQ+VE
.
Va;-VCEQ-VE
. . ~ -~ •
Rc
=
0
4.
Assuming the Q-point is at the center of load line.
:. VCEQ
=
V cc-:- VC5 <sao
:. VCEQ
=
8.5 Volts
2
Value of Rc :
The expreasioo. for gam,
5.
6.
18 - 1
=~
=
Vc;c-Vcyp-Ve _ 1~-8.5-5
Rc,'
- 2.3 X 10 3
= 1.956mA .
...(2)
Io
!w
1.956 mA
Q
hcc
200
9.78 J..LA
...(3)
:. 1cQ
=
Step 1 :
3
2209Q-
· I.
3.
(F-Ull) Ff&.ll.l: Siape stage R.C. coupled ampUJier
.. Rc
180 X 2.7 X 10
-~
220
Srep 2 : . . Emitter resistor RE :
fL!::20Hz.
The single stage RC coupled amplifier is as shown in
Fig.ll.l. Due to high gain requirement, the emitter resistor Re is
bypassed
+Vee
~ .1 80
=
Specifications of the amplifier_:
V0
~
~
· . Selecting the.next higher standard value of Rc·
Rc
2.3 k.Q. ·
= · 220,hie=2.7kO,hoe=~=O
I Ay I ~ 180
=
.~·
~e
·~ 180
of the amplifier you
Ana.:
1.
~ons of the transistor:
flte
A i ·=
. Y
=
=
.. IsQ = lcQ + loQ = 1.956 mA + 9.78 J..LA
. . lao
1.9657 mA
:. The emitter resistor
=
RB
=..!Ji.l~n
........
-
5
- 1.9657 x
w- 3
-
Electronic Devices & Circuits-! (Eiex.-MU)
:. Rt,
Selecting
Step 3 :
RE
=
=
4-105
2.5436 kQ
2.7 kQ
... (4)
To calculate the biasing resistances a and ~ :
1
Fig. 11.2 shows the Thevenin's equivalent circuit f the
0
amplifier of Fig. 11.1. .
RB
and
V
m
=
=
RtiiR2
10
:. 2 7tfLR;
But ~
. :. ~
~
ct
or
c.
10
2: 2 7tfL R ;
~
_ 2.7 X 25.45
2.7 + 25.45
= ~II Ra =b. + R 8
-
••
= 2.440
to
R2
<Rt + Rz) x Vee
... (5)
CI >
2 7t X 20 X 2.44 X 10J
:.
:. c 1
2: 3.26 x 10 -s or C 1 2:32.6 ).IF
.Selecting the standard value C 1
Selection of
c2 :
= 47 ~ 125 ~..
c2 should ~ such that,
Xo
~ut
~
~ 1~ <Rc II RJIAt
=
.. Xcz ~
.. Xcz ~
VTH
1
:. 2 7tfL Cz
~
f
= fL
oo
RcflO
2JOO /10 i.e. 230 Q
230
1
(F-1522)
Fjg. 11.2: Tbevenin's equivalent circuit
The expression for stability factor of the voltage divider
bias circuit is given by,
... (6)
..
But S ~ 10
(1 + 220) (RB + 2.7) < 10
Rg+(1+220)x2.7 - .
...(Given)
: .. Vm
But V 111
. . Rt
RR xVa;
Vrn
Rs
5.95
~1101
Atf
= fL
-
-
10
1
:. CE
2: 2 7t X 270 X 20
:. C 5 2: 29.47 ).IF
Selecting the nearest higher standard value i.e. 47
V. The designed circuit is shown in Fig. 11.3.
0
. .._. .(8}
R, Rz
= 25.45 kO = (RI + Rz)
.•. 0nz = 38 k.O
acitors c 1
'
Step 4 : Calculate the coupling cap
Selection of C1)
.
uld be
.= .
The coupling capacttor c. sbo
~I
. Xc.
=47 ).IF /25 V ·
Bypass capacitor Ce :
~ should be such that
... (7)
.,
:. 25.45 X 77 + 25.45 Rz = ?1 Rz
.
w-$ or C2 2: 34.59 ~­
= 25.45x 18
. = . 77 kJ).
.. Rt
.
. But
3.459 x
< 2700
= (9 .78 X 10- 6 X 25.45 X 10) + 0.7 + 5
= 5.95 Volts
-~ X~
= <Rtltz
+Rz) x Vcc-R 1 +Rz
Rt
=
2 7t X 20 X 230
Selecting the standard value of Cz
. Xa; ~
:. 221 ~ + 596.7 ~ 10 R8 + 5967
:. Ra ~ 25.45 kn
.
Applying KVL tO the base loop of Ft~. 11.2 •
Vm = IaQRa+VaE+VE
. 3
:. Vm
:. Cz 2:
:. Cz ::::
~
10 At f
1
lis '*'"''4jli@liijiiJ
...(9)
47!1f=
cl and I"'-'E ••
such that.
<F-1523) Fig. ll.3 : Designed CE ampllfter
Step 5 : Av, ~ and R,. of the deslgued amplifter :
fL
IAvl =
IAvl =
~
~
187.4
220 X 2.3 X 103
2.1 x 103
J.&F I 25
l
'
-
Electronic Devices & Circults·l (Eiex.-MU)
4-106
Thus voltage gain is higber than 180.
·R; = ~II R0 = 2.7 k lj25.45 1c
R; = 2.44 k.Q
Q. 2
Ana.:
r0 (mA) '
= Rc = 2.3 k.Q
and 1\,
:. Rc .. 2.1 k.O
Decide tbe Q point :
Step 2 :
v
00
Ac
O..lgn alngle stage BJT CE Amplifier for the
following requirements. .
Av:?! 100, Z. >3 kQ, Vee= 18 V
Dec. 09. Mny 10
Spectficatfone are :
1.
3.
Voltage gain I Av I~ 100
Vcc=l8V
2.
~>3k.Q
4.
Assume fL = lO Hz
Assumptions :
Ycecsat)
The .type of biasing circuit : Voltage divider bias. The
emitter resistor Re is bypassed. The CE amplifier circuit to be
designed is as shown in Fig. 11.4
·
Vee - Vcecaat)
<F·l566> Fig. U.S
vo
= vCEQ - v
(peale)
CE(sat)
Assuming Vce (satJ = lV
Vo(p-pJ = Vee.- Vce<.oat)- Vce<w>
= Vee.- 2 Vce(aat)
But VCl!'(sat) = lV
:. Vo(p-p)
Va::. '-2 =18-2
16V
. . Q points S : 16 Volts, 5.5 mS
Step 3 :.
1.
2.
<F·IS65) Fig.ll.4
Selection of emitter resistor RE :
For Va:.> 10 the value of Ve should be 5 V.
Assuming Ve = 5V
Applying KVL to output loop to wrjte,
Vex; = ' lCQRc+VCEQ+Ve
Vee.- VCEQ - Ve
-·
· Specfftcations of transistor BC 1478 :
.
~=4.5.0
~=2x10
he., (miD) = 240
hfE(IIIia) = 20()
h fe (typ) = 330
hFE(typ) = 290
'
Assuming the Q-point is at the center of load line
. Va:.- VCE(sat) 18- l
.. VCEQ . =
2
=~
3.
h fe (max) = 500
b PE (max) =450
. . VCEQ
Design procedure :
=
=
hceRc
100
~
~
~
"CEQ
InQ
5.
6.
100
3
:. Rc
:. Rc
"
4.5 X 10
240
X
100
1.87 ill
SeJecting tbe next higher standard val.ue for Rc
L ;1 •, 11 '. 1J Ill I I ll II '•
8.5 Volts
Vcc-VCEQ.-Ve_ 16-8-5
Rc
=
=
.1aL.
bee (typ)
rnA
1.8 X 103 - 1.6
5 05 "A
1.6 X 10-3
330
·
,.....
- J·
Ii>Q = · lCQ + IBQ = 1.6 X lO
•.• IEQ
1.60 mA
The emitter resistor is given by,
=
hie
Because required 1Av 1~ 100 ,so substituting the mi~imu~
value of 11,.,. so that under running.conditions the voltage gam wrll
be~ dlan 100.
~
4.
oo
:, I Av I =
:. I Avf ~
bee (Jaiol) Rc
=
L_·
The steps to be followed for the amplifier design are as follows :
Step 1 :
Collector resistor Rc :
The expression for voltage gain is,
IAvl
hce<RciiRJ
But~
Rc
:. ICQ
Selecting transistor BC 147 B because it has higherh;e·
Ro '
Selecting R8
Step 4 :
=
=
Vi,
5
IBQ = 1.60 X
w-3
+ S:05·X lO-6
=3.115 k.Q
3.2 k.Q
To calculate tbe biasing resistances R and R, :
1
Thevenin's equivalent circuit of the amplifier of Fig. ll.6.
R8 = R 1 IIR2
~
andVTH = R +~X Vee
1
The expression for stability factor of the voltage
divider bias circuit for good stability is given by,
S ~ 5 .Substituting hPB = hi'B(tYPJ =290 and
remaining values, to get,
Electronic Devices & Circuits 1(
.
.
- Elex.-MU)
+ 107
. c1
:0::
••
10
21t X 10 X 3.32 X 103
=47·9 J.lF
•••Alii.
Selecting the standard value C 1 =47 J.1F I 25 V
Selectioo of C1 :
'1 should be such that,
Xo s
But~
=
1~ <Rc II RJ
I
at f
=fL
oo
.. XC2 S Rc/10
.. X C2 S
.
5 S
5 <Ra + 906.46) .
5Rg + 4532.32
4532.32-906.46
=
=
=
=
<F-1567) Fig. 11.6
(1 + 290) (RB + 3.115)
Rg + (l + 290) X 3.115
(291) <Ra + 3.115)
291Rg + 906.46
R a (29 1 _ 5 )
.. C1
. . C2
=
.~
R +v x Vcx;
: . V 111
=
R x Vcx;
Ra
..
R1 ~
(Rl +~
Xa; S
= -v--= 12.75.7X 16
11{
••
R1
=
19.73 k.Q
should be at least (1/10) of R; at the lowest frequency.
:. .XCt s R~
10
..
lO
,
~
I
at f::; fL
10
lO
2: 27t X lO X 3.115 X 103
0!: 510.93 X 10-
6
lO
:. <;;
=
•
510.93 J.1F
•••Alii.
Selecting C =470 J.1F 1147 JJF.
Step 6 : Av, Rt and R. of the deslgued ampli&r :
R'
,
I
0!: T1tfLRi
R'I
=
4.5 X 12.7
h~c iiRo=(h~e+Rs> 4.5 + 12.7
R:
=
3 .32W
lis '*"**i''lt''''''"
Flg.ll.7
"
=
hc<(cyp) X Rc
~
330 X 1.8 X 1if
4.5 x 103
132 (Greater than 100)
•••Alii.
.. R: = ~liRa
~Ra
But
s
••. Ans.
.. I Ay I
, s c,
c,
3
I Av I =
21t fL R,
..
3.115 ~ 10
10
R,~
R 1 R8
35.64 x 12.7
(R1 - R8 ) = 35~64- 12.7
:s;
CE
ReI loj at f =fL
R,+~
=
1
•••Ans.
35.64 w
:. R:z
21tfL Cl
. . <;;
Vex;
x-
Step S :
Coopting capacitors C 1 and Cz :
The coupling capacitors C 1 should be such that ii:s reactance Xct
..
w-6
I
= R,~
= ~(R, ~ Ra)
~
88.41 x
Vee = 18V
Ra Vex;
-
1
· · 2n fL Cs
Rs
R,RB
R 1 R8 +~R8
..
1
.'2
• :.::
27t X lO X 180
· · C 2 2: 88.41 J.1F
=
ButVm
1
:0::
Selecting c2 =100 JJF/25 v
Bypass capacitor C£ : <;; should be such that,
RB
12.67W
Applying KVL to the base loop of Fig. 11.6 to get,
Vm
IBQ Ra + VaE + VE
6
:. Vm
(5.05 X l0- X 12.7 X 103) +0.7 + 5
: . V 111 - 5.76 V .
·
• • _R1
1.8 X 103
10
=
4.5 X 12.7
4.5 + 12.7
.. ·R'I = 3.32 W (Greater than 3 W)
and Ro = Rc= 1.8W
••.ADs.
••
-
4-108
Electronic Devices & Circults-1 (Eiex.-MU)
Q, 3
DMign a single stlloe CS amplifier for audl~
frequency appllcationa suitable for operation upto
low frequency of 20 Hz. Uae JFET type BFW-11 to
give output voltage of 2 Volta and voltage gain I
Av I • 10. For dealgn u. . mutual characterletica of
Vae- loa (typ) given In the data sheet. Design two
clrculta:
1.
To give zero-temperature drift of the
operating Q-polnt and
1
To give 10 = 108 = i 1088•
2.
Ana.:
Gi'ftll :fL =20 Hz, I Av I
Using the typical mutual transfer characteristics of Fig,
d assuming us obtain the value of IDQ corresponding to
11.38 an
v =_1.87 Volts.
os
·
As shown in Fig.ll.8, the value ofiDQ is given by,
=
·JDQ
1.2 mA
. .
.
Thus the co-ordinates of the Q-pomt are,
=
1 )
(-1.87 V, 1.2 mA)
... (2)
Q (VGSQ• DQ
' '
. "t sed .
If b'
Assuming that the type of b1as1.11g crrc~. u
1s se J.a.S.
Therefore the bias line wiD pass ~ough.the ongm and through the
Q-poiot. The slope of the bias line eq~ to (1/Rg ).
i{
··
Rs
=
Slope of bias line
1.87 v - 1 558 lc.Q .
Rs . = 1.2mA- ·
Seleeting the nearest standard value of 1.5 ill.
.. Rs
1,5ill
..
= 10, IFEI' BFW-11, Yo = 2 Volts
(rms)
=
Part I : Circuit design to give zero-temperature drift :
Steps to be followed :
Step 1 :
Calculate V GSQ :
The condition for zero temperature drift as :
I vp 1- 1vGS I = 0.63
.. Vp = V 08 +0.63
The expression for 10 is, .
.lo
-
•-"*' an=0.5V
Y- "*1an=1mA
10
:. . Io
.·. Io
• [ Vas] .
But g. 1- Vp =g,
· · lo =
SubstiJuting
(F-1798) Fig. 11.8 : Mutual characteristics of BFW-11
Step 3 :
gm
T[Vp- VQs1
= VGS + 0.63 to get,
8m
lo = T CVos +0.63- Vos1
. . Io = 0.315 &o
Substituting the expressions for 10 and gm in the above
2
Ims[l~:;J = ·0.312[g~ (1 - ~:9]
[t-
Vos]2
=
0.312·[-2Ioss]
... (1)
Vp
. Vp
from the wec;ifications of JFET BFW-11 given in the data
~beet we bave tbe typical values as follows :
Io.sc 7 mA. v, = - 2.5 V, rd =50 ill and gmO =5 m mho.
Subldb!Cing lbele valuel in Equation (1) to get,
.~Ans.
VasQ
1.87 Volts
L ..
"08$
t
:t'. r1
'.ll ftlllfJII l•
.
..
[ v ]
~ - = &no 1- v~
Substi~ting the typical s~ifi.ed values fot: BFW-11 to get,
[1
5 >< w-3
.
gm = L26mS
.
&m
=
.(-1.87) ]
(- 2.5)
"
.
For ensuring that the output of the amplifier is not distorted..
VDSQ ~ VP + V0
(nus)
= 2Y.
... (3)
(peale)
But V 0
...G'1ven
..J2
:. Vo (peale> = 2
=2.828 Volts
..
VosQ · ~ 2.5.+ 2.828 =5.3284 Volts
· · Select, V05Q = 6 Volts .
Step 4 :
Drain resistance (Ro) :
The required voltage gain is 1 A 1
amplifier with bypassed Rs.
=-
Step l : 8ourf.e ......oc:e Its ;
The ~ mutual cransfer characteristic of the JFET
BPW- 11 iau 1bowD iD fig. ll.S.
vDSQ :
The transconductance of JFET ·is given by,
Vp
expresiioo to get,
• •
_Calculate the value of
v
I Av I = - 8m R~
where
R'D
..
10
=
10. For a CS
...(5)
Ro
r11 IIRo= rd + Ro
= -s.n~
=
. ..(4)
rd
~lc Devices & Circuits-! (Eiex.-MU)
~
..
"" lQ__
10
8..,- 1.26 X 10:"]'
4-109
=7.93 k.Q
7.93W
7.93 k:.Q
=
Solving for R0 to get.
Rn
SOk X
50k+R0
.
R0 = 9.424 kQ
Selecting tbe nearest highest value .i.e. 10 k.Q.
:. Ro = IO.kQ
Ra
... (6)
Seledion of~:
Tbe value of Rm of the JFET is about 10 u n .
lv~. Hence too
small valueof o&'G will decrease R;.. and very
. high al
.
.
~'-ft
proble
v
ue of~ will
cause 1=.t.llge
m.s.
':. Selecting Ro < 10 Mn
:. . Ro ·= 1Mn
.. ~(7)
StepS:
Supply voltage Vnn :
Applying KVL to the outpu~ loop of self bias circuit-CS amplifier
to get.
Voo :::: VRS + VDSQ + VRD .
Voo :::: IDQRs + V00q+IDQRD
VDD :::: IDQ <Rs + RO) + vDSQ
Von. :::: 1.2 (iO + 1.5) + 6 =19.8·Volts
20V
Voo
~piing capacitors (C1 , Ci) :
..
..
..
..
.
... (9)
3
Xcl = 0.1 R;, = 0.1 X 1 M.Q =100 X 10
1
3
.. 21tfLCI
= 'wo x 10
But
fL
··
Cl
=
1
= 2nx20x100x10 =0..1 JJF/ZSV
c,
Xo =
1
.. 2nfLCz
=
..
:.
Step 7 •
•
OJ. Ro
r
'-'2
Cz
=
=9.5S J.lF
... (11)
10 J.LFI2S V
Bypass capacitor (Cs) :
·
•
,_....aA
satisfy the following condition,
ByPass capacitor C5 JS &eRN..,.. to
Xa = 0.1 Rs
11.8,
=
... (13)
-0.8 Volts .
Therefore the co-ordinates of the Q-point ~•
Q2 (VGSQ• I~ = (- 0.8 v. 3.5 mA)
... (14)
. Step 2 :
Obtain the source resistance Rs :
Draw the second bias line passing through the Q-point Q2
and the origin. -The reciprocal of the slope of this bias line is Rs·
1
0.8V
· · Rs = Slope = 3.5 mA
Rs
=
228.0
Selecting the nearest standard valu~ of 220 .Q.
.. Rs = 220.0
Tranconductance &. :
Step_3 :
~ = g~[ 1- V:sJ
= -2.5 V and VGS = -0.8 V
But gmO = . 5 mS, • Vp
5 X 10-
3
[
1-
(~:~)]
3.4 mS
... (16)
Step 4:
.Calculate Q-polnt draiil to source·voltage VDSQ:
For undistorted ()utput voltage,
VosQ ~ Vp+Vo(pcak>
.. VosQ ~ 2.5 + 2 x-{2
.. Vorms= 2 V
. . VnsQ > 5.32 V
. . Select VosQ
6V
...(17)
Step 5 :
Drain resistance R 0 and biasing resistor Rc :
The required voltage gain · IAv I =
10
=
=
1
0.1 X 1500
2n.fLC5
..
1
53.05 J.LF
/. C 8
2 x n x 20 x ISO
•
hi"""'r s· --"ft,..~ value.
Selectiog the nearest &>- WJUA~U
. <; = 68 J.lF!2S V
..
. ·
shown in Fig. ll.9.
1be complete circwt JS as
=
I
=T :
The procedure to be followed is as follows :
Step 1 :
Obtain VGSQ:
Given that IDSS(typ) =7 mA. Therefore we ha'Ve to design the
amplifier circuit for IDQ = 3.5 inA. ·
Referring the typlt~>mutual characteristics of Fig.11.8 and
finding the value of VGSQ corresponding to IDQ = 3.5 mA. From
.. ~ =
.. gm =
0.1 x7.93W
1
= 21t fL X 793
.
.
Part II : Circuit design to give 10
..
20Hz
= 0.1 J.LF /25 v
....(10)
coupling capacitor ~ is selected to satisfy the
Similarly,
following condition,
,
we
Fig. 11.9 : Complete designed_CS amplifter
VGSQ
The input coup~g capacitor C 1 is _selected to satisfy the following
condition,
(F-1799)
Fi~.
=
Step6:
1MO
=
But
...(12)
IAv I =
gm R
'
D
Substituting the values to get,
'
Ro
=
~
10
gm = 3.4 X 10-3 = 2.941 ill
-
4·110
Bectronlc Devices & Clrcults·l (E1ex.·MU)
But R~
:.
•
rdx R0
(r11 II Ro) "' ;-:;:R"
d
=
2.941 k
0
and rd =50 k.O
50k XRp
(50k + Ro)
Solving for R0 to get,
=
R0
3.12 .k n
Selecting a higher standard value .
.. Ro = 3.3 ill
...(18)
Assuming the self bias circuit used for the amplifier biasing
1MO
Cs=470)1F
to get,
=
'Ro
1 Mn
The selection criterions are same as those used in part I of
this design assignment
Step 6 :
Supply voltage V DD :
In Part I ,
IOQ ( Ro + Rs) + VosQ
..
~ 3.5 ( 3.3 + 0.22) + 6
.. V00 ~ 18.32 Volts.
. . Selecting , V00 = 20 V
... (19)
Step 7 :
Calculate the coupling capacitors (C1, <;> :
FOI' seledioD of c 1 : ·
·
Voo
V DO
~
Xcl
=
R;..Ro
w=w
a. 4
c.s.
Design. a
amplifier using FET type BFW ·- 11
to meet the following specifications :
Av ~ 10, V0 3 Vac , R, better th~n 1 M.O, flbetter
25Hz.
• Assume the ·external· load connecte~ RL 33 kQ
· between the output a~ ground. Assume suitable
supply potential Voo·
H~w- will you proceed for above design If zero
temperature drift Is necessary ?
Dec. 03. May 09
=
than
=
Ans.:
The required circuit diagram is as shown in Fig. 11.11.
1MQ
s
= ---w-=1 x10
..
<F-1800) Fig. 11.10 : Complete designed circuit for part ll
27tfLCI
fL = 20Hz
But
..
1
= 27tX20x1x105
= 79.57nFn5 v
cl
cl
... (20)
For seledioD of<; :
~
Xo = 10
rd xR
But
..
..
0
50x3.3
~ = ( rd + R0 ) =(50 + 3.3) 3.o95 k.Q .
Xo = 309.5 .a
_1_
= 309.5
2mLc;
•• C:z =
• <F·1857) Fig. 11.11 : CS JFET amptifter
Selecting , C:z= 33 ~I 25 V
CakJalate the bypass capacitor Cs :
Step 8 :
For ldedloa of C8
<;
...(21)
:
Xes =
•
.
1
27t X 20 X 309.5 = 25·7 ~
-fg =22 .0
= 2 7t X 201
X
... atfL =20Hz
22
A reasonable minimum drain current level can be assumed
to be 1 rnA.
Step 3 : Cakulate vGSQ :
As,IOQ
=361.7 } J.lF
Select tbe nearest highest value.
: . C8 • 470 J.LF/25 V
... (22)
The complete dealgned circuit is as shown in Fig.ll.lO.
'
Step 1 : Selection of FET :
Selecting FET BFW-11 wifh the following specifications :
loss =7 rnA
VP =- 2.5 V
V DS(max) -'
- 30 V
~=5.6mAIV
rd=50kn
Step :Z :Selecting IDQ.:
= .loss[l- V~oJ2
.
..
·.
1 = 7
V 0 SQ
=-
2
[·~ -~]
-2.5
1.56 Volts
Step 4 : Calculate VD8Q and V8
:
As, VDSQ<mln>:: Vp+lV-V08 = 2.5+1+1.56
t: ' I ' 'J
II Ill I I II II ·,
.;leetronlc Qevloes & Clroulta-1 (Eiex.·MU)
=
Step 5 : Cakulate 1m :
8m =
4-111
1.~ Volts
.. x0 = 5 · 21~ k := 526.1 n
sm0[ 1- v~
''
But gmO = 5.6mAJV
.
&,, =
..
Step 6 : Calculate R0
:
IAvl =
:. 10 =
Gain
19.88 R0
... 19.88+R0
·•
5.6 [ 1 -
=
•5
(- 1.56)]
-2.5
•
.
Ana. :
Given:
4.76
Step l:
LC filter, v l..dc =10 V, Il..dc = too·mA, r = 0.02.
Assuming supply frequency is 50 Hz.
Circuit diagram :
...Ans.
R8
· · Vs
Applying KVL to the drain source circuit to write,
Voo = l~o + VDSQ(min) + Vs
-·
= (1 X 6.26) + 1.94 + 6.26
=
Voo
CRt II Rz) ; : :
RJ
Rz
..,
CRt + Rz)
..
...Ans.
1 ,..n
...(1)
lVL)ot.
=
Rt +Rz xVoo=4.7
+~ X 15
=
4.7
Step 3 :
Rz
=
1.55 MQ
But ~
=
Rt II ~
=
.&
RB
Step 4 :·
-
3.39 X 1.55
Ct= 27t X 25 X 106.3 X 10
Selcctiog C1
= 100 nF
Sinillar1y Xc
=
I!
a :. II •, II Ill I
I II II !,
II RJ
10
...Ans.
(6.26 k !l 33k)
10
0.02
b
3
=
1 X 10
_3 x 21t x 50
00
f.06H
. ~
Step 5 : Selecting L = 2 H (Higher than Lc)
LC = 5.97 X 10-S
5.97 X 10 -S
2
=
2.98 x 10-S
29.8 J.lF
Step 6 :
Rating of the diodes :
Each diode conducts for · one half cycle of the rectifier
output Hence the average current through each diode will be half
of the maximum load current.
ll..dc
. . Average current through diode 2
50 mA
=
=
X
VLdc
.. c =
1
·cis
2
-~- ·
;
,. c =
w =21tfL cl
(R0
~ (50)
Calculate·Lc and selection ofL :
Critical inductance Lc
=3.39 M 111.55 M =3.99 + 1.55
C 1= 59.88 nF
=
R8
I
106.3
6 Vz X 41t2 X (50)2 X LC
=
•••Ans.
.. C
Xct=
=IOO.Q
Assuming bleeder current Ib is 10 % of the load current
. ·· :. Ib - 10 mA
-'
10
... RB = 10 1 k.Q
... at fL - 25 Hz
10
=
LC = 6Vz X 41t2
LC = S.97 X 10-~
Bleeder resistance R8 :
·...(2)
•••Ans.
Step 9 : Coupling capacitors :
Xct
2
0.0
R2
1)
= 0.3I33
Rt + ..'2
.
Substituting Equation (2) into (1) to get,
R 1 X 0.3133 :2:: I MQ
:. Rt ;;::: 3.19 M.Q
. . Select R 1
3.39 Mn
Substituting this value into Equation (2) to get,
. ~ :::= (0.3133 X 3.39) + 0.3133 ~
.
10
1
Va·
:. Rz =
VLdc
I MQ
Vs + VGS =6.26- 1.56 =4.7
••
. Calculate RL , Land C :
RL = -1-= 100mA
l..dc
=
Rz
Step 2 :
:
VG
Also
• • Rl
~
<F-1144) Fig. ll.U
14.46 :Y
Assuming . V00 = 15 Volts
Step 8 : Calculate VG, R1 and R1
Required , R1 :2:: 1 MQ
•.
•••ADS.
= 6.26 kn
= IOQRs =1 X 6.26 =6.26 Volts
Assuming
••
= 12 ~
Dcc.09. Dec. 10 Dec 11
0.02.
8m (rd II Ro II Rl)
2· 1 (50 II Ro II 33) = 2.1 (19.88 11 R )
0
6.26 k.Q
Step 7 : Calculate V ~ R8 and v00 :
Ro =
1
2n X 25 X 526.1
Dealgn for a full wave rectHier, an L type LC filter
J~hlch glvea a de output voltage of 1OV at a load
current of 100 mA. The allowable ripple factor Ia
..
=2.1 mA/V
=
R0
=
C2
..
11¥1
= somA
.=
Electronic Devices & Circults-1 (Eiex.-MU)
.
hi h barges to
The load voltage is the voltage across C w c c
.
Vm volts. With a very small value of r, Assuming that the npp1e
voltage.is small.
:. Vl.dc "t Vm = lo'V
PIV of each dibde = V = tOV
.
·
Hebce selecting. the diode ~ving a PIV rating higher than 10 V.
Step 7 :
~tings of transfonner :
vm
v2
. Nt
• • Turns ratto N
A tuU wave rectifier using a center tapped
· transformer with two diodes gives output voltage
of 250 V to a resistive load, the current being
75 ± 25 mA. H the ripple factor is 0.001, cai.culate ·
the specHication of the devices and components
required If the filter used is n-fllter.Draw comp18te
circuit diagrams In each c~~-
Q. 6
C1
••
cJ =
-2xl0-
4
J.if
200 J.IF
. al
. •
th 1t section filter to be symmetri« ,to get,
Assunung e
..
~
c1 200 J.lF
···Ans.
. .. C and r into Equation (4) to get
Substttuttng 1
"-'2
=
-9
230
= 7.071
= 32.52
2
1
= 2xsox50
..
=
Secondary.nns voltage Vsnns =_r;:, =7.071
.
.. so= 2xso xCJ
3 X 10 0' 0.075 H
L = (200 X 10- :) .
Thus the filter components are
c.
~ = 200 J.lf, L = 0.075 H
1
...Ans,
=
Step 3 :
Ratings of diodes :
The PIV of each diode will be 2 Vm'
. . For a n ~ filter ,
Vl.dc
=
ILdc (max)
Vm- 4fC
... (6)
3
Ans.:
Given :Vl.dc = 250 V,
Il.dc = (75 ± 25) rnA, r = 0.001
Step 1 :
Cakolate the range of RL :
For a full wave rectifier with ·a 1t type filter the expression
for ripple factor is givt)n by , . ·
1
r =
...(1)
4-..f3 f ffi, L C1 c; RL
.
=
ro,
2nf:;;2x3.14 x 100=628.31
... (2)
..
Ruru,;
v;...,
.. Turns ratio
2so ·
= -y
- = 100 mA = 2.5 k.Q
l,.dc(max)
... (3)
Nl
N2
230
·= .176.7 =1.3
rms secondary current
=
Ste., 2 :
Calculate L, C1; C2 : .
Substitute Equations (2) and (3) into Equation (1) to get,
. .
1
1
0.00 = 4-.,J3 X 50 X (628:31l L C1 C2 X_2.5 X 103
i.92
=
=
=
.. Vm
250V
. . PIV ·
2 Vm =500 V
Step 4 :
Transformer ratings :
rms secondary voltage
vm 250
v.(nns) = -../2 =-../2 =176.7 v
Considering the worst case condition RL =~~
·
250
100x 10Vm- 4x50x200X 10- 6
ILdc(max)
01
=100 mA
L
L C1 ~ =:..
X 10- = 3 X 10••• (4)
Calculating the value of C1 with an ass.umption that the
peak to peak ripple voltage across it is one fifth of the average de
9
9
voltage.
. · Ripple voltage ~ . .
.
1
ll VJH = j XYu:
.
250
='·j=50V
02 ·
(F-2672) Fig.
11.13 : Circuit diagram of n type filter
._..(5)
[J[J(J
ea s y
., ______• ---
SOIUliOIIS
--------- ------------- --
...
.
\
~
.