STM32以太网外设
The OSI model
2
TCP / UDP
IP
Physical layer
(PHY)
Ethernet
Media Access Control
(MAC)
TCP-IP Protocol Suite
Other Protocols
Application layer
Presentation Layer
Session Layer
Transport Layer
Network Layer
Data Link Layer :
Manage communication
between network entities:
Physical Layer:
Transport the data on the physical support
STM32
Ethernet
Ethernet Block Diagram
3
Ethernet Block Diagram
DMA
MAC
PHY
Intereface
4
Ethernet Block Diagram
DMA
MAC
PHY
Intereface
5
Physical Layer Interface
• Supports both Media Independent Interface (MII) and Reduced Media
Independent Interface (RMII).
• RMII is a lower pin count alternative, which targets multi-port applications
and low cost design:
• Internal loopback on the MII for debugging.
• MDC/MDIO for the PHY configuration
RMII
interface
Media
Access Control
MAC 802.3
Select
MII
MDC
MDIO
External
PHY
6
Physical Layer Interface
8 data pins
6 control pins
2 Clock signals
2 for PHY configuration
TX_ER(optional, rarely used，
STM32 don’t have this pin)
802.3 MAC
•
•
•
•
•
STM324x7
• MII = 18 pins
TX _CLK
TXD[3:0]
TX_ER
TX_EN
RX _CLK
RXD[3:0]
RX_ER
RX_DV
CRS
COL
MDC
MDIO
7
External
PHY
PHY_CLK
Selected in SYSCFG_PMC
4 data
3 control
1 for the clock
2 for PHY configuration
RX_ER(optional on switches)
802.3 MAC
•
•
•
•
•
STM324x7
• RMII = 10 pins
TXD[1:0]
TX_EN
RXD[1:0]
RX_ER
CRS_DV
External
PHY
MDC
MDIO
REF_CLK
PHY_CLK
Ethernet Interface Block Diagram (1/4)
• One 25Mhz external crystal (internal oscillator)
• The internal PLL to generate HCLK (Core, peripherals…)
• Connected to the MCO to provide the 25Mhz to the PHY
Ethernet
MAC 10/100
XTAL
25MHz
OSC
PLL
MII
15 pins
MDC/MDIO
2 pins
MII+MDC
= 18 pins
HCLK
25MHz
MCO
STM32F107/2x7/4x7
XT1
25MHz
PHY
8
Ethernet Interface Block Diagram (2/4)
• One 50Mhz external oscillator
9
• This 50Mhz output clock is provided to the MAC & the PHY
• One 25Mhz external crystal (internal oscillator)
• The internal PLL to generate HCLK (Core, peripherals…)
• RMII interface
• 7 pins for the communication between the MAC & PHY
• 2 pins for the MDC (PHY control)
• 1 pin for the 50Mhz clock input
Ethernet
MAC 10/100
50MHz
XTAL
25MHz
OSC
PLL
RMII
7 pins
1 pin
MDC/MDIO
2 pins
RMII+MDC
+clock
= 10 pins
HCLK
STM32F107/2x7/4x7
XT1/XT2
OSC
50MHz
50MHz
PHY
Ethernet Interface Block Diagram (3/4)
• One 50Mhz external oscillator
• Connected to the PLL to generate HCLK (Core, peripherals…)
• This 50Mhz output clock is provided to the MAC & the PHY
Ethernet
MAC 10/100
50MHz
OSC
50MHz
PLL
RMII
7 pins
1 pin
MDC/MDIO
2 pins
RMII+MDC
+clock
= 10 pins
HCLK
STM32F107/F4x7
XT1/XT2
50MHz
PHY
10
Ethernet Interface Block Diagram (4/4)
• One 25Mhz external crystal (internal oscillator)
• The internal PLL to generate HCLK (Core, peripherals…)
• Connected to the MCO to provide the 25Mhz to the PHY
• The PHY then generate the 50MHz clock reference clock
11
• RMII interface
• 7 pins for the communication between the MAC & PHY
• 2 pins for the MDC (PHY control)
• 1 pin for the 50Mhz clock input
Ethernet
MAC 10/100
50MHz
RMII
Clk
MDC/MDIO
XTAL
25MHz
OSC
PLL
Clk_out
HCLK
25MHz
STM32F107/2x7/4x7
XT1
50MHz
25MHz
PHY
PLL
PHY Registers
• The PHY Registers are :
• Initialized by the Bootstrap configuration
• Can be accessed by the MCU (providing that the PHY Address is correct)
• There are 3 types of Registers :
• Basic
• Extended
• Vendor Specific
• How to change PHY when using ST’s driver
12
Example LAN 8742A
13
Read the Auto-negotiation’s result of DP83848C (1/3)
14
Read the Auto-negotiation’s result of LAN8742A (2/3)
15
How to change PHY when using ST’s driver (3/3)
• So when you change from PHY to another, the user have to update
this value depending on the used external PHY.
• In file “stm32f7xx_hal_conf.h”
/* The DP83848 PHY status register */
#define PHY_SR
((uint16_t)0x10)
/* PHY status register Offset */
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /* PHY Speed mask
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /* PHY Duplex mask */
16
Media Access Control(MAC)
MAC
17
Media Access Control
18
• Operation modes and PHY support
• 10/100Mbps data rate
• Full-duplex and half-duplex operations
• MII and RMII interface to external PHY
• Offload processing
• Preamble and start-of-frame data (SFD)
insertion or deletion
• Checksum checking of IPv4 header and
TCP, UDP, or ICMP payload
• Calculates and inserts IPv4 header and TCP,
UDP, or ICMP payload checksums
• Low power mode
• Remote wakeup packet and AMD Magic
Packet™ detection
• Processing control
•
•
•
•
MAC address filtering
IEEE 802.3-2002 standard
IEEE 1588-2008/PTPv2 support
Supports network statistics with RMON/MIB
counters (RFC2819/RFC2665)
MAC 802.3
MAC Control
Registers
Offload
Processing
PTP
IEEE1588
PMT
MMC
MAC 802.3 Operation : the frame format
56 bits
8
bits
48 bits
48 bits
16bits
368 to 12000 bits
/ 46 to 1500 bytes
32
bits
Preamble
SFD
Destination
Address
Source
Address
Length
/ Type
Data
FCS
Start of Frame
Destination
MAC Address
Source
MAC Address
Checksum
TCP-IP
Stack data
19
Offload features
Ethernet datagram management overview
• Ethernet datagram offload processing
Preamble & SFD
1
Destination MAC (DA)
2
Source MAC (DA)
3
VLAN
4
Eth Type
5
Payload…
6
CRC
7
1. Preamble and Start-of-Frame tag automatic insertion(Rx) or deletion (Tx)
2. Destination MAC address filtering
3. Source MAC address filtering
4. VLAN tag detection of received frame
5. Checks frame type and size (Rx) or Insert field (Tx)
6. Ethernet payload Checksum computation and insertion (Tx) or checking
(Rx) for:
• IPv4 header
• TCP/UDP/ICMP payload
7. Datagram CRC computation (Tx) and checking (Rx)
20
Automatic CRC and pad generation
When the number of bytes received from the application falls below 60
(DA+SA+LT+Data),zeros are appended to the transmitting frame to make
the data length exactly 46 bytes to meet the minimum data field
requirement of IEEE 802.3.
2KB
RX FIFO
External
PHY
MAC 802.3
DP@TDES0= 0
DC@TDES0=0
DA
SA
LT
Data
<46bytes
Preamble&SFD
DA
SA
LT
Data
Pad
46bytes
CRC
21
Checksum Offload
22
• The Ethernet MAC implements checksum offload feature for
IPv4, ICMP, TCP and UDP protocols.
• Checksum offload engine supports:
• Checksum calculation and insertion for the transmit path.
• Error detection for the receive path.
• Checksum offload feature can be enabled only with Storeand-Forward mode.
TDES1
Transmit:
Receive:
ETH_MACCR
Implement in code(1/2)
• How to enable this feature
• Enable the receive checksum offload by setting the IPCO bit in the
ETH_MACCR register
• Enable checksum calculation and insertion when transmit by setting
CIC bits in TDES1
• Only one step needed to do: fill the initial parameters in
low_level_init()
• Dropping of TCP/IP checksum error frames?
by setting DTCEFD bit in the ETH_DMAOMR register.
Default dropping it.
24
Implement in code(2/2)
• Check the status
IP datapram header error
and payload error during
reception
IP datapram header error
and payload error during
transmission
25
Precision Time Protocol (IEEE1588) : What is it
26
• It is a protocol designed to synchronize real-time clocks of
the devices of a network
• Synchronization is done with the most accurate clock
found in a packet-based network: called the Grand
Master Clock.
• Accuracy is
09:00
Grand
Master
Clock
09:00
09:10
09:00
09:05
09:00
09:01
09:00
09:30
09:00
26
Precision Time Protocol (IEEE1588) : How it works
27
Comparing the transmission of messages
• From the master clock point of view
• From the slave clock point of view
Master Clock
8
9
10
11
Slave Clock
10
11
12
13
Propagation delay
Master Clock
8
Slave Clock
10
9
11
10
12
11
13
Clocks Offset
27
Precision Time Protocol (IEEE1588) : How it works
Master Clock
8
Slave Clock
t1
9
10
A
12
13
t2
12
13
15
16
Computation done
by the slave
PTP
A = t2 - t1 = Delay + Offset
B = t4 - t3 = Delay - Offset
Delay = (A + B)/2
11
14
10
11
t1
28
t3
t4
t4
14
B
15
16
17
Offset = (A - B)/2
This allow the Master
and the slave to be
synchronized with a
sub-µsecond precision
Propagation delay
Clocks Offset
28
Precision Time Protocol : Time stamping
Time stamp is capture by hardware
• As soon as the reception is complete
• When the start of frame is output on the MII
Frames receive with PTP feature
The DMA returns the time
stamp to the Application in the
RX descriptor
DMA
MAC
PTP
IEEE1588
MII
Rx Frame
Frames transmit with PTP feature
The MAC captures the time
stamp as soon as the frame
reception is complete
The MAC detects a
frame at MII level
The DMA returns the time
stamp to the Application in the
TX descriptor
DMA
MAC
PTP
IEEE1588
MII
Tx Frame
The MAC captures the time
stamp when the Tx Frame’s
SFD is output on the MII
29
IEEE 1588
Precision Timing Protocol - PTP
• PTP Objective
• Synchronize all nodes in a local network area (LAN)
with very high accuracy (<1us) by use of HW time
stamping
Master
Time Ref
• PTP protocol define synchronization messages
between nodes and routers.
• STM32F7 MAC features
• MAC is compliant with PTPv2 (IEEE1588-2008)
messages
Path1
delay1
Master
Time Ref
Synchronization
Path2
delay2
Path1
delay1
Path2
delay2
PTP SYNC
Slave1
Slave2
Slave1
Slave2
Time1
Time2
Time Ref
Time Ref
• Accurate timing reference is based on hardware
counter
• 64 internal bits (32 bits for second and 32 bits for
nanosecond counter)
• Counter accuracy on HCLK is down to ~ 5 ns (@
200MHz)
• Export timing reference through output pulse-persecond (PPS) signal
30
Low-power modes
Mode
Description
Run
Active.
Sleep
Active. Peripheral interrupts cause the device to exit Sleep mode.
Stop
The Ethernet peripheral is able to detect frames while the system is in the Stop
mode, provided that the EXTI line 19 is enabled.
Standby
Powered-down. The peripheral must be reinitialized after exiting Standby mode.
31
Power Management
Remote wakeup frame detection
• Power down mode state
• Application and Tx clock are switched-off
• PHY, MII interface and MAC Rx remain
active
Full
Active
DMA/MTL
Power
Down
Off
MAC Rx
MAC Tx
MAC Rx
Off
MII
PHY
Network
MII
PHY
Network
• All packets but wake-up ones are
dropped
• Wake-up
• Wake-up is controlled by the network
• Wake-up packets are
• AMD Magic packet
• User defined
• Wakeup frame detection is an event that
can wakeup the system from STOP mode
32
Ethernet Block Diagram
DMA
MAC
PHY
Intereface
33
Ethernet Block Diagram : FIFO & DMA
• The MAC core has two FIFOs, of 2KB each one, with a configurable
threshold.
• Two modes for popping data towards the MAC, for frames transmission &
for frames reception:
Dedicated DMA
AHB Master
Interface
AHB Bus
BusMatrix
2KB
RX FIFO
Ethernet
DMA
2KB
TX FIFO
Media
Access Control
MAC 802.3
34
Ethernet Block Diagram : FIFO
35
• Two modes for popping data towards the MAC, for frames
transmission:
• Threshold mode: as soon as the threshold level is reached.
• Store-and-Forward mode: a complete frame is stored into the FIFO.
SRAM
DATA
2KB
RX FIFO
Ethernet
DMA
Threshold
DATA
MAC 802.3
External
PHY
Threshold mode
DATA
Transfer complete
Store-and-Forward mode
DATA
DATA
DATA
Ethernet Block Diagram : FIFO
36
• Two modes for popping data towards the DMA, for frames reception:
• Cut-through mode: as soon as the threshold level is reached.
• Store-and-Forward mode: a complete frame is received into the FIFO.
Ethernet
DMA
SRAM
Cut-through mode
2KB
RX FIFO
MAC 802.3
Threshold
DATA
DATA
DATA
Store-and-Forward mode
Transfer complete
DATA
DATA
DATA
External
PHY
Ethernet Block Diagram : FIFO
• Transmission
• TSF:
• TTC:
• ST:
Transmit store and forward
Transmit threshold control
Start/stop transmission
• Reception
• RSF:
• RTC:
• SR:
Receive store and forward
Receive threshold control
Start/stop receive
ETH_DMAOMR
37
DMA Controller
38
• Independent DMA engines for transmit and receive.
• Round-robin or fixed-priority arbitration between transmit and receive
engines.
• Dual-buffer (ring) or linked-list (chained) descriptor chaining.
• Comprehensive status reporting for normal operation and transfers with
errors.
• Interrupt control for transmit and receive.
AHB Master
Interface
BusMatrix
AHB Bus
2KB
RX FIFO
Ethernet
DMA
2KB
TX FIFO
Media
Access Control
MAC 802.3
DMA Controller: Descriptors structure (1/2)
• DMA transfers are managed by descriptors.
• Descriptors are configured by the user and located in the
SRAM.
• Multiple descriptors are prearranged in two structures:
• Ring structure.
• Chain structure.
39
DMA Controller: Descriptors structure (1/2)
• Each descriptor is formed by four 32bit-words:
•
•
•
•
TDES0 :
TDES1 :
TDES2 :
TDES3 :
Control and Status information.
Counts.
(First) Buffer address
Ring mode:
Second Buffer address.
Chain mode:
Next Descriptor address.
Basic address of
transmit descriptor
ETH_DMATDLAR
Transmit
descriptor
Basic address of
receive descriptor
ETH_DMARDLAR
Receive
descriptor
40
DMA Controller: Descriptors Structure (2/2)
Chain mode
Ring mode
• Each descriptor points to one buffer.
• Each descriptor can point to a maximum of
two buffers.
• Each descriptor include the next
descriptor address.
• Configurable descriptor skip length
• hold the status of the transmitted or
received packet.
• The last descriptor point back to the first
entry.
=1
=0
TCH@TDES0
41
Single frame/ Multiple descriptors Chain mode
43
Bit28: First Segment : 1
Bit29: Last Segment : 0
Control / Status
First Buffer
Buffers Count
DMA
Start of Frame
Buffer1 Address
…
Next Desc Address
Second Buffer
Control / Status
Bit28: First Segment : 0
Bit29: Last Segment : 0
Buffers Count
Second Buffer
DMA
Last Buffer
Buffer1 Address
…
First Buffer
Next Desc Address
Bit28: First Segment : 0
Bit29: Last Segment : 1
TX FIFO
Control / Status
Last Buffer
Buffers Count
End of Frame
DMA
Buffer1 Address
Next Desc Address
SRAM
*Bit8/Bit9 used for Rx
Single frame/ Multiple descriptors Ring Mode
44
Bit28: First Segment : 1
Bit29: Last Segment : 0
Control / Status
First Buffer
DMA
Start of Frame
Buffers Count
Buffer1 Address
…
Buffer2 Address
DMA
Second Buffer
Second Buffer
…
First Buffer
Descriptor
skip length
Control / Status
Last Buffer
Bit28: First Segment : 0
Bit29: Last Segment : 1
DMA
Last Buffer
End of Frame
Buffers Count
Buffer1 Address
Buffer2 Address
SRAM
TX FIFO
DMA Descriptor Init
low_level_init
HAL_ETH_DMATxDescListInit
HAL_ETH_DMARxDescListInit
ethernetif.c
Set basic transmit
descriptor address
45
Interrupts
• Ethernet MAC Interrupts are split in three
categories
• DMA Normal Interrupts
• Good transmission or reception
Normal
IT
• DMA Abnormal Interrupts
• Rx FIFOs overflow
• Tx FIFO underflow
• Process stopped
• MAC Interrupts
Abnormal
IT
• PMT: Set when a wakeup packet is received
• MMC: Set when there is a MMC counter event
• TST: Set when target time is reached
• All interrupts can be masked
46
Ethernet over STM32 Family
MCU
Core
Ethernet controller is compliant with the following standards
STM32F107
Cortex-M3
•
•
•
•
IEEE 802.3-2002 for Ethernet MAC
IEEE 1588-2002 standard for precision networked clock synchronization
AMBA 2.0 for AHB Master/Slave ports
RMII specification from RMII consortium
STM32F2
Cortex-M3
•
•
•
•
IEEE 802.3-2002 for Ethernet MAC
IEEE 1588-2008 standard for precision networked clock synchronization
AMBA 2.0 for AHB Master/Slave ports
RMII specification from RMII consortium
STM32F4
Cortex-M4
•
•
•
•
IEEE 802.3-2002 for Ethernet MAC
IEEE 1588-2008 standard for precision networked clock synchronization
AMBA 2.0 for AHB Master/Slave ports
RMII specification from RMII consortium
STM32F7
Cortex-M7
•
•
•
•
IEEE 802.3-2002 for Ethernet MAC
IEEE 1588-2008 standard for precision networked clock synchronization
AMBA 2.0 for AHB Master/Slave ports
RMII specification from RMII consortium
47
Demo ST Provide
F107
F207/ F4x7/ F7*
F217 F4x9
LwIP_HTTP_Server_Netconn_RTOS
Y
Y
Y
LwIP_HTTP_Server_Socket_RTOS
Y
Y
Y
LwIP_HTTP_Server_Raw
Y
Y
Y
LwIP_IAP
Y
Y
Y
LwIP_StreamingServer
Y
LwIP_TCP_Echo_Client
Y
Y
Y
Y
LwIP_TCP_Echo_Server
Y
Y
Y
Y
LwIP_TFTP_Server
Y
Y
Y
LwIP_UDPTCP_Echo_Server_Netconn
_RTOS
Y
Y
Y
LwIP_UDP_Echo_Client
Y
Y
Y
Y
LwIP_UDP_Echo_Server
Y
Y
Y
Y
*except WLCSP180 package
48
stm32f7xx_hal_eth.c
GPIO init
MII or RMII
selection
MAC and DMA
config
Implement by code
——Ethernet Init
49
HAL_ETH_MspInit, call from HAL_ETH_Init
HAL_ETH_Init, call from low_level_init
ETH_MACDMAConfig, call from HAL_ETH_Init
PHY init
HAL_ETH_Init , call from low_level_init
Initialize Tx/Rx
Descriptors list
low_level_init, call from ethernetif_init
Two Rx Mode
Polling Mode
(Standalone)
Interrupt Mode
(RTOS)
50
Polling Rx Mode
The ethernet_input() function implementation differs between
standalone and RTOS modes
Main()
{
……
While(1)
{
ethernetif_input(&gnetif);
……
}
}
void ethernetif_input(struct netif *netif)
{
err_t err;
struct pbuf *p;
/* move received packet into a new pbuf */
p = low_level_input(netif);
/* no packet could be read, silently ignore this */
if (p == NULL) return;
/* entry point to the LwIP stack */
err = netif->input(p, netif);
if (err != ERR_OK)
{
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input
error\n"));
pbuf_free(p);
p = NULL;
}
}
51
Interrupt Rx Mode
Packet received
void ETH_IRQHandler(void)
{
ETHERNET_IRQHandler();
}
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
{
osSemaphoreRelease(s_xSemaphore);
}
Release
semaphore
void ethernetif_input( void const * argument )
{
struct pbuf *p;
struct netif *netif = (struct netif *) argument;
for( ;; )
{
if (osSemaphoreWait( s_xSemaphore,
TIME_WAITING_FOR_INPUT)==osOK)
{
do
{
p = low_level_input( netif );
if (p != NULL)
{
if (netif->input( p, netif) != ERR_OK )
{
pbuf_free(p);
}
}
}while(p!=NULL);
}
}
}
52
Transmission Flow
53
Reception Flow
54
Thanks