Lab 1:
Introduction
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Outline
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Introduction
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Basics of the Verilog Language
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Importance of HDLs
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HDL is an acronym of Hardware Description Language.
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Two most commonly used HDLs:
Verilog HDL (also called Verilog for short)
2. VHDL (Very high-speed integrated circuits HDL)
1.
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Features of HDLs:
Design can be described at a very abstract level.
 Functional verification can be done early in the design cycle.
 Designing with HDLs is analogous to computer programming.
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What is Verilog?
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HDL describe the structure and behavior of digital electronic circuits.
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Verilog is intended to be used for verification through simulation, for
timing analysis, for test analysis (testability analysis and fault
grading) and for logic synthesis.
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Synthesis is the process of converting a high-level description of design
(Verilog/VHDL) into an optimized gate-level representation.
Mixed level modeling
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Behavioral
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Structural
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Algorithmic ( like high level language)
Register transfer (Synthesizable)
Gate (AND, OR ……)
Switch (PMOS, NOMS, JFET ……)
Invented in 1985 and standardized in 1995 under the IEEE 1364-1995
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Cont…
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Verilog designs partitioned in a hierarchy of modules
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Modules communicate using input, output, and inout ports
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Described process is executed in a concurrent manner (in parallel)
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Verilog is case sensitive
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Extra white space is ignored
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Keywords are in lowercase
But whitespace does separate tokens
Comments
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One liners are //
Multiple lines /* */
Comments may not be nested
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Verilog Value Set
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0
represents low logic level or false condition
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1
represents high logic level or true condition
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x
represents unknown logic level
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z
represents high impedance logic level
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Abstraction Levels
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Abstraction Levels are used in engineering to specify
how a system will operate without getting consumed
in implementation details
Each level has requirements/specifications
 The number of details in the requirements is just
enough to characterize the behavior for that level
Abstraction Levels
System (highest)
(generic specs)
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Example
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System - The LAN network speed shall be 10 Gbps
Algorithm – the CPU will get the samples from all temperature sensors,
calculate the average, and send it to the remote server.
RTL – the output of the encryption block shall be stored in 128 bit by
64 locations synchronous FIFO
Gate – The dsign shall be synthesized using gates from the
fab32ntzq65.v cell library
Circuit – the structure of an AND gate shall be the following –
transistor schematic for AND gate
Material – cells from fab32ntzq65.v shall be implemented using a 32 nm
process
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Verilog modeling
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Algorithm (subsystem
specs)
Register Transfer
Level (RTL) (block
level data flow)
Gate
Circuit
Material (lowest)
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Digital Design
Flow
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Tools used
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Electronic Design Automation (EDA) tools are software tools used to
design ICs and PCBs.
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EDA = CAD {computer aided design (create schematics)} + CAE
{Computer aided engineering (analyze schematics)}
Several software packages are
used depending on stage
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Specification
Design
Implementation
Verification
Test
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Verilog Simulators
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ModelSim and Questa (Mentor)
Incisive Enterprise Simulator
(Cadence)
VCS (Synopsys)
Vivado (Xilinx)
Icarius Verilog (Open source)
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Installation
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Intel ® Quartus ® Prime Lite Edition
Complete design and verification flow for Verilog and VHDI
 Comes with Modelsim-intel FPGA Edition (simulation)
 Can synthesize your designs and then upload them in an FPGA (Field
Programmable Gate Arrays) development Board (DE1-SoC)
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https://fpgasoftware.intel.com/?edition=lite
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Create account and download the following and install
Online Simulators
 You also need Notepad++
 https://edaplayground.com/
 https://www.tutorialspoint.com/compile_verilog_online.php
 https://www.jdoodle.com/execute-verilog-online/
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Creating a Hello Message
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Use ModelSim of online simulators
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Create this hello_world file on notepad++ and save it as .v file in you
working folder.
Create another folder within your working folder and name is sim
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Instructions
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Create a project folder
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Open ModelSim
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Go to File ⟶ New ⟶ Project
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On the pop-up window, write the project name then click on browse to
select folder (you created earlier) and click ok.
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Cont…
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A new window opens,
Select add existing file and browse (one
level up), and select the earlier created
hello_world file and click ok and close
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A hello_world can be seen with
a ? Mark. This means that the
file has not been compiled.
Right click and compile all. You will then
have a green √ (successfully compiled.
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Cont…
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Go to menu ⟶ Simulate ⟶
Start Simulation ⟶ Expand the
library work and select
hello_world and click ok. (wait
for all icons to be fully loaded).
Then Run all
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The word hello world will
be displayed on the lower
left section
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Excercise
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Repeat the same process but change from hello-world to something
like this.
I am _____ and this is my first Digital Electronics lab
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Procedure
Change on text editor (notepad++)
 Click on the project (lower left) ⟶ right click ⟶ compile all ⟶ restart ⟶
ok ⟶ run all
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