I2C PROTOCOL
PROTOCOL???
TYPES:
I. INTER SYSTEM PROTOCOL
II. INTRA SYSTEM PROTOCOL
THUMB RULE FOR ANY LEARNING
I2C – INTER-INTEGRATED CIRCUITS – IIC OR TWI
• WHO – PHILIPS SEMICONDUCTOR (NOW NXP SEMICONDUCTORS), ATMEGA,
INTEL
• WHEN – 1982, 1992, 1995
• WHY – ESTABLISH COMMUNICATION BETWEEN TWO OR MORE IC
• WHERE – EEPROM, I/O INTERFACES, PERIPHERAL DEVICES
CONTROLLER AS MASTER & PERIPHERAL DEVICES AS SLAVES
WHAT
• SYNCHRONOUS – SENDER GETS ACK RESPONSE FROM RECEIVER WHEN DATA RECEIVED
SUCCESSFULLY
• HALF DUPLEX BIDIRECTIONAL – DATA FLOW FROM MASTER TO SLAVE OR SLAVE TO
MASTER
• MULTI-CONTROLLER/MULTI-TARGET (MASTER/SLAVE)
• PACKET SWITCHED
• SINGLE-ENDED
• SERIAL COMMUNICATION BUS (TWO WIRED –SDA, SCL)
• BUILT IN COLLISION DETECTION
• CLOCK FREQUENCY – (0-1MHZ) DRIVING AT 30 MILLI AMPS
• OPERATING TEMP - -40 TO +85 DEGREE CELSIUS
• MODES – STANDARD AND FAST COMMONLY USED
• DEVICES – 128 DEVICE (7 BIT ADDRESSING – 0-127 (2^7))
OVERCOME LIMITATION BASED ON OTHER MODES 8,10 BIT ADDRESSING
(8 BIT – 2^8, 10 BIT – 2^10)
I2C Mode
Speed
Standard Mode
Fast Mode
Fast Mode Plus
High Speed Mode
Ultra-Fast Mode
100 kbps
400 kbps
1 Mbps
3.4 Mbps
5 Mbps
• I2C BUS LENGTH – 1 MTR AT 100KBAUD, 10 MTR AT 10KBAUD
• ARDUINO CAN SUPPORT ONLY 100K AND 400KBITS
APPLICATIONS OF I2C INTERFACE
• ATMEL AT24CXX EEPROM CHIPS
• MAXIM DS1307/8 REAL TIME CLOCK CHIPS
• MICROCHIP MCP7941X REAL TIME CLOCK CHIPS
• MCP23017 PORT EXPANDER
• PCA85276 40×2 LCD DRIVE
HOW I2C WORKS
• I2C DATA TRANSFERRED IN MESSAGES.
• MESSAGES BROKEN UPTO INTO FRAMES OF DATA
• EACH MESSAGE HAS ADDRESS FRAME THAT CONTAINS BINARY ADDRESS OF SLAVE
• HTTPS://WWW.CIRCUITBASICS.COM/BASICS-OF-THE-I2C-COMMUNICATION-PROTOCOL/
EXAMPLE
I2C HARDWARE DESIGN - PHYSICAL LAYER
I2C System Features
VDD
SDA
SCL
SDA
DAC
Target 2
Only two communication
lines for all devices on the
bus (SDA, SCL)
Bi-directional
communication, half duplex
Allows for multiple
controllers and multiple
targets
GND
VDD
SCL
SDA
VDD
ADC
Target 1
GND
SCL
SDA
VDD
Microcontroller
Controller 2
GND
GND
Microcontroller
Controller 1
SCL
SDA
VDD
SCL
GND
GND
Requires pull-up resistors
on both SDA and SCL
1
1
I2C PHYSICAL LAYER – OPEN-DRAIN CONNECTION
When NMOS turns ON,
SDA or SCL is pulled low
VDD
Pull-up
resistor
SDA,
SCL
SDA, SCL Voltage
VDD
Device
I2C logic
GND
Open-drain
connection
GND
Quick transition from high to low as NMOS pulls
charge from any bus capacitance from SDA, SCL
1
2
I2C PHYSICAL LAYER – OPEN-DRAIN CONNECTION
When NMOS turns OFF,
SDA or SCL is released and returns
high from the pullup resistor
VDD
Pull-up
resistor
SDA,
SCL
SDA, SCL Voltage
VDD
Device
I2C logic
GND
Open-drain
connection
GND
Exponential rise depends on capacitance on SDA
or SCL and pullup resistor size
Low resistance: faster communication, more power
High resistance: slower communication, less power
9
I2C PHYSICAL LAYER – OPEN COLLECTOR VS PUSH-PULL
VDD
Push Pull
Open Drain
VDD
SDA
Device
I2C logic
Device
I2C logic
Any output that goes
low takes priority
On
Off
Q1
Q2
GND
Open-drain
connection
GND
VDD
Open-drain
connection
VDD
Q1
Q3
On
Off
Device
I2C logic
Off
Q2
Push-Pull
Output tries
to dive high
On
Bus Contention
Output at
indeterminate state
GND
Device
I2C logic
Q4
GND
Push-Pull
Output tries
to dive low
Open Drain
• Open drain output can
connect together
• Any output that goes low
will pull the bus low
• This type of connection is
called a “wired-OR”
Push-Pull
• Open drain output cannot
connect together
• Connecting outputs together
can cause a bus contention
where the output state is
indeterminate
DESIGN (ARCHITECTURE)
• BUS HAS TWO ROLES FOR NODES: MASTER AND SLAVE
• MASTER NODE – NODE GENERATES THE CLOCK AND INITIATES COMMUNICATION WITH SLAVE
• SLAVE NODE – NODE THAT RECEIVES THE CLOCK AND RESPOND WHEN ADDRESSED BY MASTER
• 4 POTENTIAL MODES OF OPERATION FOR BUS DEVICE, MOST DEVICE USE A SINGLE ROLE AND TWO
MODES
•
MASTER TRANSMIT – MASTER NODE SENDING DATA TO SLAVE
•
MASTER RECEIVE - MASTER NODE RECEIVING DATA TO SLAVE
•
SLAVE TRANSMIT - SLAVE NODE SENDING DATA TO MASTER
•
SLAVE RECEIVE - SLAVE NODE RECEIVING DATA TO MASTER
BUILDING BLOCKS OF I2C SERIAL INTERFACE
FRAME FORMAT
REAL TIME ARDUINO EXAMPLE
ADVANTAGE OF I2C
• I2C REQUIRES TWO SIGNALS/PINS TO COMMUNICATE NUMEROUS DEVICES
• USES CHIP ADDRESSING, WE ADD ADDITIONAL DEVICES TO BUS– NO NEED OF WIRING
• DEVICE CAN WORK AS BOTH MASTER AND SLAVE
• EMPLOYS BETTER ERROR HANDLING FUNCTIONALITY
DISADVANTAGE OF I2C
• DUE TO PULL UP RESISTOR – CLOCK SPEED LIMITATION AND POWER DISSIPATION
• COMPLEX HARDWARE AND FIRMWARE COMPARED TO UART, SPI
• HALF DUPLEX PROTOCOL WHICH ADDS COMPLEXITY
• SLOWER DATA TRANSFER RATE THAN SPI
• SIZE OF DATA FRAME IS LIMITED TO 8BITS
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
1. Before the address frame of I2C communication, what actions make up the
START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the SDA low as
an ACK
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
1. Before the address frame of I2C communication, what actions make up the
START condition?
a. The controller device sets the SDA low, and then sets the SCL low
b. The controller device sets the SCL low, and then sets the SDA low
c. The controller device sets the SCL low, and the target device pulls the SDA low as
an ACK
SDA
SCL
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
2. In the address frame, after the controller device sends the 7 bit address, what
is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication coming from
the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from or write to
the target device
c. The controller device send a STOP condition before sending the next data
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
2. In the address frame, after the controller device sends the 7 bit address, what
is the next part of the I2C protocol sent?
a. The target device sends the ACK to acknowledge the communication coming from
the controller device
b. The controller device sends the R/W bit to indicate if it wants to read from or write to
the target device
c. The controller device send a STOP condition before sending the next data
A6
A5
A4
A3
A2
A1
A0
R/W
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
3. Because of the NMOS open-drain connection to SDA and SCL, which part of
the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
3. Because of the NMOS open-drain connection to SDA and SCL, which part of
the communication waveform is faster?
a. The rise time of SDA and SCL
b. The fall time of SDA and SCL
c. The rise time and fall time of SDA and SCL are the same
SDA, SCL Voltage
VDD
GND
Open-drain connections are actively pulled down
instead and are faster than a resistive pull up
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
4. What is the benefit of having an open-drain connection over push-pull outputs
for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when outputs are tied
together
QUIZ: BASICS OF I2C: THE I2C PROTOCOL
4. What is the benefit of having an open-drain connection over push-pull outputs
for I2C?
a. High speed drive for the bus outputs
b. Reduction of bus capacitance
c. Prevents destructive current draw during bus contention when outputs are tied
together
Push-Pull outputs may pull a large current when
the outputs are tied together and there is bus
contention