Integrated Circuits

EEE 329 Linear Integrated Circuits Assoc. Prof. Dr. Murat AKSOY 1 EEE 325 Linear Integrated Circuits ➢ MICROELECTRONICS: Circuit Analysis and Design – Neamen ➢ Microelectronic Circuits – Sedra & Smith ➢ Microelectronic Circuit Design – Jeager ➢ Integrated Electronics – Millman ➢ Engineering Electronics - Mauro 2 1 Contents 1. Integrated Circuit Biasing and Active Loads 2. Differential Amplifier Circuits o BJT & MOSFET Differential Amplifiers 3. Operational Amplifier (Op-Amp) o BJT & MOS Operational Amplifier Circuits o Basic Op Amp Configurations o Nonideal Effects in Operational Amplifier Circuits 4. Application and Design of Integrated Circuits o Current to Voltage Converter / Voltage to Current Converter o Instrumentation Amplifier o Operational Transconductance Amplifier (OTA) o Nonlinear Circuit Applications 5. Power Amplifiers and Output Stages 6. Feedback and Stability 7. Electronic DC Power Supplies 3 Integrated Circuit Biasing and Active Loads 4 2 Up to now, voltage-divider resistor networks can be used as a biasing technique for the discrete circuits (FET and BJT amplifiers). But this technique is not suitable for integrated circuits (ICs). Resistors require relatively large areas on an IC compared to transistors; therefore, a resistor-intensive circuit would necessitate a large chip area. Also, the resistor biasing technique uses extensively coupling capacitors. On an ICs, it is almost impossible to fabricate capacitors in the microfarad range, as would be required for the coupling capacitors. 5 Biasing transistors and transistor circuits in ICs is considerably different from that in discrete transistor designs. Essentially, biasing integrated circuit amplifiers involves the use of constantcurrent sources. Transistors are also used as load devices in BJT and FET amplifier circuits. These transistors, called active loads, replace the discrete collector and drain resistors in BJT and FET circuits. Using an active load eliminates resistors from the IC and achieves a higher small-signal voltage gain. 6 3 Current Source Circuits V+ When the bipolar transistor is used as a linear amplifying device, it IO must be biased in the forwardactive mode. The bias may be a C3 C1 Vin current source that establishes the C2 Vo quiescent RB RL RC collector current as shown in Figure. V− 7 Bipolar Transistor Constant Current Sources I1 = I 2 + I B BJT Current-Source R2 I 2 = VBE + RE I E I=IC IB I2 = VBE + RE I E R2 VEE = R1 I1 + R2 I 2 I1 R1 R2 I2 RE VEE = R1 ( I 2 + I B ) + R2 I 2 -VEE VEE = ( R1 + R2 ) I 2 + R1 I B VEE = ( R1 + R2 ) IB = VEE − ( R1 + R2 ) VBE R2  R1 + ( R1 + R2 ) RE ( 1 +  ) R2  VBE + RE I E + R1 I B R2 IC =  I B = I 8 4 Example: I=IC IB  = 100, VBE ( on ) = 0.7V R1 = R2 = 4.3k , I1 R1 R2 I2 RE = 1.8 k , VEE = 18V RE -VEE 4.3 + 4.3 0.7 4.3 IB = = 45.12  A 4.3 + 4.3 4.3k + 1.8k (1 + 100 ) 4.3 18 − I = I C = 100  I B = 4.512mA 9 PSpice 10 VCE 5 Ic 0 R4 {RL} Q1 V+ I BJT1 0 R3 R1 4.3k 4.3k 0 R2 0.5K IC(Q1)*1000 V- 1.8k 1.0K V(R4:1,R2:2) 1.5K 2.0K 2.5K 3.0K RL PARAMETERS: RL = 1k V1 18 0 LIBRARY: C:\Program Files\Orcad\Capture\w ork\abc1.lib Simulation 10 5 Transistor / Zener Constant Current Source I=IC IE = R1 RE VZ − VBE (on) ; IC = I RE -VEE 11 Two-Transistor Current Source The two transistor current source, also called a current mirror, is the basic building block in the design of integrated circuit current sources. V+ The IC2 = IO IREF basic current-source circuit consists of two matched or identical transistors, Q1 and Q2, operating at Q1 the same temperature, with their IB2 IB1 + VBE Q2 − V- base terminals and emitter terminals connected together. The B-E voltage is therefore the same in the two transistors. Basic two-transistor BJT current source 12 6 Since VBE is the same in both devices, and the transistors are identical, then IB1 = IB2 and IC1=IC2. Transistor Q2 is assumed be biased in the forward active region. I REF = I C 1 + I B1 + I B 2 V+ = IC 2 + 2 I B 2 IC2 = IO IREF IB2 IB1 Q1 = IC 2 + 2 + VBE Q2 −  IC 2 = V- IC 2  I REF = IO 2 1+  Equation gives the ideal output current of the two-transistor current source, taking into account the finite current gain of the transistor. 13 The V+ IREF IC2=IO R1 reference current in two- transistor current source can be established by connecting a resistor Q1 to the positive voltage source. The IB2 IB1 + VBE Q2 reference current is then − V- I REF = V + − VBE − V − R1 14 7 Example: Design a two-transistor current source to provide 200µA output current. Transistor parameters : β =100 and VBE(on)=0.6V. +5 IREF IO = IC 2 = IC2=IO R1 I REF 2 1+   IB2 IB1 Q1 2  I REF = I O  1 +    2   I REF = 200  A  1 + = 204  A 100   Q2 + VBE − R1 = 5 − 0.6 = 21.6 k 204 A 15 200uA R1 V1 R2 {RL} 10k 10 Q1 Q2 I 100uA I BJT1 BJT1 0 PARAMETERS: RL = 1k 0A 0 IC(Q1) 0.4K ABS(I(R1)) 0.8K 1.2K RL LIBRARY: C:\Program Files\Orcad\Capture\work\abc1.lib 16 8 Output Resistance In our previous analysis, we assumed that the Early voltage was infinitive, so that hoe = 0. In actual transistors, the Early voltage is finite, which means that the collector current is a function of the collectoremitter voltage. The stability of a load current generated in a constantcurrent source is a function of the output resistance looking back into the output transistor. IC V + Slope=hoe IC2 = IO IREF Q1 RO IB2 IB1 VA Q2 + VBE VCE I CQ I O 1 = hoe = = RO VA VA − V- 17 Improved Current-Source Circuits Basic Three-Transistor Current Source V+ Assume that all the transistors IREF R1 IC2=IO IB3 IC1 Q1 B-E voltage is the same for Q1 Q3 + VBE3 − I are identical; therefore, since the and Q2, IB1 = IB2 and IC1 = IC2. IB2 B1 + VBE − Q2 Transistor Q3 supplies the base currents to Q1 and Q2. V- 18 9 I REF = I C 1 + I B 3 V+ I E 3 = I B1 + I B 2 = 2I B 2 IREF R1 IC2=IO IB3 Q3 + VBE3 − IC1 IB1 Q1 IB2 + VBE ( 1 +  3 ) I B 3 = 2I B 2 I REF = I C 2 + Q2 − IC 2 = V-  I B3 = 2 I ( 1 + 3 ) B2 2I C 2 2I B 2 = IC 2 + 1 + 3 2 (1 + 3 ) I REF = I0 2 1+ 2 (1 + 3 ) Reference current is I REF = V + − VBE 3 − VBE 2 − V − V + − 2VBE 2 − V − ; R1 R1 19 The output resistance looking into the Output Resistance collector of the output transistor Q2 of the basic three-transistor current source is the V + same as the that of the two-transistor current IREF R1 source; that is, IC2=IO IB3 Q3 + VBE3 IC1 Q1 − I RO IB2 B1 + VBE − V- Q2 RO = 1 V = A hoe 2 I O This means that, in the three-transistor current source, the change in bias current IO with a change in VCE2 is the same as that in the two-transistor current-source. In addition, any mismatch between Q1 and Q2 produces a deviation in the bias current from the ideal. 20 10 Cascode Current Source V+ Current-source circuits can be designed IO IREF RO such that the output resistance is much greater than that of the two-transistor Q3 Q4 circuit. One example is the cascode circuit. In this case, if the transistor are Q1 matched, then the load and the reference Q2 currents are essentially equal. V- 21 Output Resistance IT We Q4 − + Q2 RO may calculate the output resistance RO by considering the VT small-signal equivalent transistor circuits. For a constant reference current, the base voltages of Q2 and Q4 are constant, which implies these terminals are at signal ground. 22 11 IT ib4 hfeib4 hie4 RO ib2 hfeib2 hie2 1/hoe2 ib4 = RO hie4 − + 1/hoe4 VT  1  VT − IT   hie 4 P  hoe 2   IT = hfe ib4 + ( 1 hoe 4 ) IT hfeib4 − + 1/hoe4 − IT ( 1 hoe 2 ) hie 4 + ( 1 hoe 2 )   − IT 1  + hoe 4  VT − IT   hie 4 P   1 + hoe 2 hie 4 hoe 2     hoe 2 hie 4 = 1 and hoe 4 hie 4 = 1 IT = hfe VT RO = 1/hoe2 VT 1 = ( 1 + hfe ) IT hoe 4 23 Wilson Current Source This circuit also has a large output resistance. V+ IC3=IO IREF transistors Assume are that identical; all the therefore, IB3 since the B-E voltage is the same for Q3 IE3 IC1 IB2 IB1 Q1 + VBE − V- Q2 Q1 and Q2, IB1 = IB2 and IC1 = IC2. The current transistors are levels in nearly all the three same; therefore, we can assume that current gains of the three transistors are equal. 24 12 I REF = I C 1 + I B 3  2 I E 3 = IC 2 + 2 I B 2 = IC 2  1 +     V+ IC3=IO IREF IC 2 = IB3 Q3 (1 +  ) IC 3 (1 +  ) IC 3 IE3 = = 2  2 (2 +  ) 1+  1+     IE3 IC1 Q1 I REF = IB2 IB1 + VBE Q2 − IC 3 = V- (1 +  ) I IC 3 + C 3  (2 +  ) I REF = IO 2 1+  (2 +  ) This current relationship is essentially the same as that of the previous tree-transistor current source. 25 Output Resistance The difference between the two three-transistor current source circuits is the output resistance. In the Wilson current source, the output resistance looking into the collector of Q3 is , RO hfe  1    , 2  hoe 3  which is approximately a factor (hfe/2) larger than that of the either the two-transistor source or the basic three-transistor source. This means that, in the Wilson current source, the change in bias current IO with a change in output collector voltage is much smaller. 26 13 Widlar Current Source In integrated circuits, resistors on order of 1MΩ require large areas and difficult to fabricated accurately. We therefore need to limit IC resistor values to the low kΩ range. Widlar current source meets this objective. V+ IREF IC2=IO R1 IC Q1 − IB1 IB2 + + VBE2 VBE1 Q2 −R E V27 Two transistors are identical and ignored the base currents VBE 1 V IREF I REF ; I C 1 = I S e T + IC2=IO R1 VBE 2 I C 2 = I O = I S e T IC Q1 − IB1 IB2 + + VBE2 VBE1 Q2 −R E V-  VBE 1 = T ln I REF IS  VBE 2 = T ln IO IS RE I E 2 = VBE 1 − VBE 2 = T ln RE I O ; T ln I I REF − T ln O IS IS I REF IO This equation gives the relationship between the reference and the bias currents. 28 14 Including the resistor RE gives the designer additional versatility in adjusting the load to reference current ratio. The output resistance RO IT R1 hfeib1 1/ho1 hie1 hie2 hfeib2 −V + 1/ho2 T RO RO1 RE RO 1 = hie 1 P hie 1 1 P P R1 hfe hoe 1 29 Resistance RO1 is in series with hie2, and the since RO1 << hie2, we can neglect the effect of RO1, which means that the base of Q2 is essentially at signal ground. IT hfeib2 hie2 −V + 1/hoe2 T RO RE RO = hfe    VT 1  =  1 + ( RE P hie 2 )  hoe 2 +  IT hoe 2  hie 2    30 15 Example: Design a Widlar current source to produce I REF = 1mA and I O = 12  A Transistor parameters: VBE (on) = 0.7V ,  = 100 , VA = 80V R1 = I I O RE = T ln  REF  IO   +5 IREF IC2=IO R1 IC Q1 − IB1 IB2 + + VBE2 VBE1 5 + 5 − 0.7 = 9.3k  I REF  1mA  12  A  RE = 26mV  ln    12  A   RE = 9.58k  Q2 −R E -5  hfe     1 + ( RE P hie 2 )  hoe 2 +  hie 2     RO = 34.88M  RO = 1 hoe 2 31 Example: Design a current source to produce I O = 12  A Transistor parameters: VBE (on) = 0.7V ,  = 100 , VA = 80V +5 IREF IC2=IO R1 IC Q1 − IO = IC 2 = I REF 2 1+   IB1 IB2 + + VBE2 VBE1 -5 Q2 − 2  I REF = I O  1 +     2   I REF = 12 A  1 + = 12.24  A 100   R1 = 10 − 0.7 = 760k 12.24  A RO = 1 V 80V = A= = 6.67 M  hoe 2 IO 12  A 32 16 Multi-transistor Current Mirrors V+ IREF R1 IO1 QR + VBE − I0N I02 Q2 Q1 QN VThe relationship between each load current and reference current, assuming all transistors are matched, is; I O1 = I O 2 = ........ = I ON = I REF N +1 1+  33 The collectors of multiple output transistors can be connected together, changing the load current versus reference current relationship. V+ IREF R1 I0 IO1 QR + VBE − Q1 I03 I02 Q2 Q3 V- IO 1 = IO 2 = IO 3 , I O = 3I O 1 = 3 I REF 4 1+  34 17 A generalized current mirror V+ QR2 IREF Q3 I03 R1 I02 I0N IO1 QR1 Q2 + VBE − Q1 V- I REF = V + − VEB − VBE − V − R1 35 FET Current Sources JFET Current Source Current sources are also fundamental elements in JFET ICs. The simplest method of forming a current source is to connect the gate and source terminals of an JFET, as shown in Figure. + VDS − IO RO 36 18 + VDS − RO IO The device will remain biased in the saturation region as long as VDS  VDS ( sat )  VGS - VP  VP In the saturation region, the current is  V  I D = I DSS  1 - GS   VP  I O = I DSS 2 ( 1 + VDS ) = I DSS ( 1 + VDS ) The output resistance looking into the drain is, RO = VDS 1 = rd = I D  I DSS 37 Example: Calculate the current through 2k load in the circuit VDD VDD 2k I DSS = 1mA 2k VP = -1.5V  = 0.01V −1 IO R VDS  VP  1.5V I O = I DSS = 1mA RO = rd = 1 1 = = 100k  −1  I DSS 0.01V  1mA I D = I DSS ( 1 + VDS ) = 1mA ( 1 + 0.01V −1  1.5V ) = 1.015mA 38 19 Basic Two Transistor MOSFET Current Source Figure shows a basic two-transistor NMOS current source (mirror). The drain and gate terminals of the NMOS V+ RO IREF transistor M1 are connected, which ID2=IO means that M1 always biased in the saturation region. Assuming λ=0, we M1 can write the reference current as M2 + VGS − I D1 = I REF = kn1 (VGS − VTN 1 ) 2 VSolving for VGS yields VGS = I REF + VT 1 kn1 V+ For the drain current to be independent of the drain-to-source voltage (λ=0), Transistor always biased in RO IREF ID2=IO the saturation region. The load current is M1 + VGS M2 − then IO = kn 2 (VGS − VT 2 ) 39 V- 2 Substituting VGS into the load current equation, we have  I  IO = kn 2  REF + VT 1 − VT 2   k n1  2 40 20 V+ If M1 and M2 are identical transistors, then VT1 = VT2 and kn1 = kn2 ID2=IO RO IREF I O = I REF The relationship between the load current M1 M2 + VGS − and the reference current changes if the V- width-to-length, or aspect ratios, of the two transistors change. If the transistor are matched except for the aspect ratios, we find IO = (W / L ) 2 I (W / L )1 REF The ratio between the load and reference currents is directly proportional to the aspect ratios and gives designers versatility in their circuit designs. 41 Output Resistance V+ The stability of the load current can ID2=IO RO IREF be described in terms of the output resistance. The output resistance, RO M1 RO = VDS 1 = rd = I O  IO + VGS M2 − V- MOSFET current sources require a large output resistance for excellent stability. 42 21 Reference Current V+ The reference current in bipolar current-source circuits is generally M3 established by the bias voltages and a resistor. Since MOSFETs can be −V ID2=IO RO + GS3 IREF configured to act like a resistor, the M1 reference current in MOSFET current M2 + VGS1 = VGS2 − mirrors is usually established using additional transistors. V- Assume that VTN are identical in all transistors. VTN 1 = VTN 2 = VTN 3 = VTN 43 V+ Transistors M1 and M3 are in series; assuming λ = 0, then I D1 = I D 3 M3 kn1 (VGS 1 − VTN ) = kn 3 (VGS 3 − VTN ) 2 VGS 1 =  kn3 k VGS 3 ) +  1 − n3 (  kn1 kn1  2 −V GS3 IREF   VTN  M1 − + V- − VGS 1 + VGS 3 = V − V  VGS 3 = V − V − VGS 1 Therefore, VGS 2 = VGS 1 = k n 3 k n1 1 + k n 3 k n1 (V + −V − ) + IO = I D 2 = kn 2 (VGS 2 − VT ) M2 + VGS1 = VGS2 − From the circuit, + ID2=IO RO + 2 (1 − (1 + k n 3 k n1 k n 3 k n1 )V ) T 44 22 Example: 5V M3 + VGS3 − IREF M1 IO + VGS1 = VGS2 M2 − M2 M2 -5V The transistor parameters are VTN = 2V , kn1 = kn2 = 0.25mA / V 2 and kn3 = 0.1mA / V 2 Determine I REF and IO 45 VGS 1 = kn 3 k n1 k 1 + n3 k n1 (V + −V − )   1 − +   1 +  kn 3 k n1 kn 3 k n1   V T    5V M3 IREF M1 0.1 0.25 = 1 + 0.1 0.25 ( 1− ( (5 + 5) + ) (1 + )2 0.1 0.25 ) 0.1 0.25 + VGS3 − IO + VGS1 = VGS2 − M2 M2 M2 -5V = 4.325V I REF = kn1 (VGS 1 − VT ) = 0.25mA / V 2 ( 4.325 − 2 ) = 1.35mA 2 IO = 3I D2 = 4.05mA 2 46 23 Multi-MOSFET Current Source Circuit MOSFET Cascode Current Mirror In MOSFET current-source circuits, the V+ output resistance is a measure of the ID2=IO IREF RO stability with respect to changes in the output voltage. This output resistance can M3 be increased by modifying the circuits, as M4 shown in Figure, which is a cascode current mirror. M1 M2 Assuming all transistors are identical, V - then IO = IREF. 47 Output Resistance IT To determine the output resistance at −V + M4 T the drain of M4, we use the smallsignal equivalent circuit . Since IREF is constant, the gate voltages to M1 and M2 RO M3, and hence to M2 and M4, are constant. This equivalent to an ac short circuit. 48 24 d4 IT g4 gmVgs4 −V + rd4 T RO s4 rd2 IT = gmVgs 4 + VT − ( −Vgs 4 ) rd 4 Vgs 4 = − IT rd 2 IT = − gm IT rd 2 + RO = VT − IT rd 2 rd 4 VT = rd 4 + rd 2 (1 + gm rd 4 ) IT 49 Bias Independent Current Source In all of the bias current mirror circuits V+ considered up to this point (both BJT M3 M4 IO2 ID1 M2 function of the supply voltages. This implies that the load current is also a ID2 M1 and FET), the reference current is a M6 IO1 M5 function of the supply voltages. In most cases, the supply voltage dependence is undesirable. Circuit designs exist in R which the load currents are essentially V - independent of the bias. One such MOSFET circuit is shown in Figure. 50 25 V+ Since the PMOS devices are matched, the currents ID1 = ID2 must be equal. Equating the M3 M4 M6 IO2 ID1 M2 kn1 (VGS 1 − VTN ) = kn2 (VGS 2 − VTN ) 2 ID2 M1 currents in M1 and M2, we find IO1 M5 R 2 VGS 2 = VGS 1 − RI D 2 R= V- 1 kn1 I D1  k  1 − n1 kn2     This value of resistance R will establish the drain currents ID1 = ID2. the currents ID1 and ID2 are independent of the supply voltages V+ and V- as long as M2 and M3 are biased in the saturation region. As the difference, V+ - V-, increases, the values of VDS2 and VDS3 increase but the currents remain essentially constant. 51 Circuits with Active Loads In bipolar amplifiers, the small-signal voltage gain is directly proportional to the collector resistor RC. To increase the gain, we need to increase the value of RC, but there is a practical limitation. Active loads eliminate this limitation. This load device can be a transistor, which will also occupy less area in an integrated circuit, another advantage of using transistors in place of resistors. In addition, active loads produce a much larger small-signal voltage gain than discrete resistors. 52 26 BJT Active Load Circuit V+ The elements R1, Q1, and Q2 form Q2 active load circuit, and Q2 is Q1 referred to as the active load C device for the driver transistor QO. VO VI R1 QO IREF The combination of R1, Q1, and Q2 RL forms the pnp version of the two- transistor current mirror. 53 Small Signal Analysis To find the small-signal voltage gain of the BJT circuit with an active load, we must determine the resistance looking into the collector of the active load device. hfeib2 ibo Vi 1/hoe2 ib2 ib1 hie2 hie1 hfeib1 1/hoe1 RO R1 hieo hfeibo 1/hoeo RL 54 27 In the Q1 portion of the equivalent circuit, there are no independent ac sources to excite any currents or voltages. Therefore, ib1 = ib2 = 0, which means that the dependent source hfe2ib2 is zero and is equivalent to an open circuit. The resistance looking into the collector of Q2 is just RO = 1 hoe 2 ibo VO Vi hieo hfeibo 1/hoeo 1/hoe2 RL The small-signal gain is then AV =  VO −hfe  1 1 = // // RL   Vi hieo  hoeo hoe 2  55 Example: Determine the small-signal voltage gain for load resistances RL = ∞, 100kΩ, and 10kΩ. VAN =120V, VAP=80V, VEB=0.6V, and β =100. +5 Q2 I REF = Q1 V + − VEB 5V − 0.6V = = 1mA R1 4.4k  IO = IC 2 = C VO VI QO RL 4.4k IREF hie0 = T I BQ I REF 1mA = =0.98mA 2 2 1+ 1+  100 = T I CQ = 100 26mV = 2.65k  0.98mA V 1 80V = AP = = 81.6k  hoe 2 I C 2Q 0.98mA V 1 120V = AN = = 122.45k  hoeo I COQ 0.98mA 56 28 ibo VO Vi hieo VO − hfe = Vi hieo 1/hoeo 1/hoe2 RL  RL   −100 for RL =   AV = ( 122.45k 81.6k ) = −1848 2.65k −100 for RL = 100k  AV = ( 122.45k 81.6k 100k ) = −1240 2.65k −100 for RL = 10k  AV = ( 122.45k 81.6k 10k ) = −313 2.65k AV =  1   hoeo hfeibo 1 hoe 2 The small-signal voltage gain is strong function of the load resistance RL. 57 MOSFET Active Load Circuit V+ M2 M1 Transistors M1 and M2 form a PMOS active load circuit, and M2 is the C VO VI MO RL IREF active load device. 58 29 Small Signal Analysis ib1 + gmVsg2 rd2 The signal voltages Vsg1 and + Vsg2 Vsg1 − − gmVsg1 Vsg2 are zero, since there is no ac excitation in this part of the circuit. This means that RO Vi rd1 gmVsgo gmVgs2 = 0 and RL rdo RO = rd 2 VO + VIac gmVgs rd0 rd2 RL The small-signal gain is then AV = VO = − gm ( rdo P rd 2 P RL ) Vi 59 Example: Determine the small-signal voltage gain for load resistances RL = ∞ and 100kΩ. λn=λp=0.01 V-1, VTN = 1V, kn= 1mA/V2 and Iref= 0.5mA. V+ gm = 2kn (VGS − VTN ) = 2 kn I DQ = 2 kn I REF M2 M1 gm = 2 1  0.5 = 1.41mA / V C rdo = rd 2 = VO VI MO RL IREF 1 1 = = 200k  −1  I REF 0.01V  0.5mA 60 30 VO + VIac AV = gmVgs rd0 rd2 RL VO = − gm ( rdo // rd 2 // RL ) Vi for RL =  AV = −1.41mA / V  ( 200k  // 200k  ) = −141 for RL = 100k  AV = −1.41mA / V  ( 200k  // 200k  // 100k  ) = −70.5 61 Differential Amplifier Circuit 62 31 Differential Amplifier Circuit V+ The Diff-Amp is a fundamental building block of analog circuits. It is RC VC 1 VC 2 Q1 Vin1 RC the input stage of virtually every opamp, and is the basic of a high- Q2 Vin 2 speed logic circuit family, called emitter- coupled logic. The design of IC diff-amps, in IO general, incorporates current-source V− biasing and active loads. 63 Figure shows a block diagram of the diffamp. There are two input terminals and v2 one output terminal. Ideally, the output signal is proportional to only the Difference Amplifier VO v1 difference between the two input signals. The ideal output voltage can be written as VO = AOL ( v1 − v2 ) where AOL is called the open-loop voltage gain. We define the differential mode input voltage as vd = v1 − v 2 and the common mode input voltage as vcm = v1 + v 2 2 64 32 Basic BJT Differential Pair Figure shows the differential-pair V + basic BJT configuration. Two identical transistors, Q1 and Q2, whose emitters are connected together, are RC RC VC 1 VC 2 biased by a constant-current source IQ, which is connected to a negative Q2 Q1 Vin1 Vin 2 supply voltage V -. The collectors of Q1 and Q2 are connected through resistors RC to a positive supply IQ voltage V +. By design, transistors Q1 V− and Q2 are to remain biased in the forward-active region. 65 Since both positive and negative bias voltages DC Analysis are used in the circuit, the need for coupling V+ RC vC 1 vC 2 Q1 Q2 capacitors RC and voltage divider biasing resistors at the inputs of Q1 and Q2 has been eliminated. If the input voltage signals in the circuit are both zero, Q1 and Q2 are still biased in the active region by the current source IQ. Since Q1 and Q2 are matched, current IQ splits IQ evenly between the two transistors, and V− iE 1 = iE 2 = IQ 2 If the base currents are negligible, then iC1 = iE1 and iC1 = iE1 , and vC 1 = V + − IQ 2 RC = vC 2 66 33 Example: Determine the DC bias values of IC, VC1, and VC2. RC = 10kΩ, V+ = 10V, V- = -10V and IQ = 0.8mA. V+ RC vC 1 vC 2 RC Q2 Q1 iE 1 = iE 2 = IQ 2 = 0.8mA = 0.4mA 2 vC = vC 2 = vC 1 = V + − IQ 2 RC vC = 10 − 0.4mA  10k  = 6V IQ V− 67 Example: Determine the DC bias values of IC, VC1, and VC2. RC = 10kΩ. VBE (on) = 0.7V +10V RC VC 1 VC 2 Q1 IQ −10V Q2 RE 10k RC −V − − VBE (on) − RE I Q = 0 IQ = 10V − 0.7V = 0.93mA 10k  vC = vC 2 = vC 1 = V + − IQ R 2 C vC = 10 − 0.465mA  10k  = 5.35V 68 34 Example: Determine the DC bias values of IC, VC1, and VC2. RC = 10kΩ, R1 = 10kΩ, RE = 6kΩ, V+ = 10V, V- = -10V, Vγ = VBE(on)=0.6V and VZ= 6V. V+ RC IREF VC 1 VC 2 RC IE3 = IC 3 = 6V + 0.6V − 0.6V = 1mA = I Q 6k  R1 Q2 Q1 IQ RE vC = vC 2 = vC 1 = V + − Q3 IQ 2 RC vC = 10 − 0.5mA  10k  = 5V RE VZ VZ + V − VBE ( on ) IC 3 V− 69 Example: Determine the DC bias values of IC, VC1, and VC2. RC = 10kΩ, R1 = 19.4kΩ, V+ = 10V, V- = -10V, VBE(on)=0.6V and β = 100. I REF = V+ RC IREF VC 1 VC 2 RC V + − VBE − V − 10V − 0.6V − ( −10V ) = = 1mA R1 19.4k  IQ = IC 4 = R1 Q2 Q1 IC 1 = IC 2 ; IQ Q3 Q4 V− I REF 1mA = =0.98mA 2 2 1+ 1+  100 IQ 2 = 0.49mA vC = vC 2 = vC 1 = V + − IC 1 RC vC = 10 − 0.49mA  10k = 5.1V 70 35 Small-Signal Analysis Single-Ended (Differential) AC Voltage Gain If an input signal is applied to either input with other connected to the ground, the operation is referred as “single ended”. If two opposite polarity input signals are applied, the operation is referred to “double ended”. V+ V+ RC Q2 Q1 + RC RC VC 1 VC 2 Vin 2 Vin IQ RC VC 1 VC 2 Q2 Q1 + −V in − + IQ V− V− 2 71 Single-Ended (Differential) AC Voltage Gain Setting DC voltage sources to zero and replacing them by a short circuit equivalent RC + Vin − vC 1 vC 2 Q1 RC RC Q2 Vin 2 RO + vC 1 vC 2 Q1 Q2 RC −V in − + 2 RO RO is the output resistance of the current source. 72 36 ib Vin 2 vC1 vC2 RC RC −V + − hie hfeib hie hfeib ie collector voltages is called two- + ve − ie The single ended or the vO = vC 2 − vC 1 differential vC 1 = −h fe ib RC   vO = 2h fe ib RC vC 2 = h fe ib RC  Vin  = hie ib + ve   2 Vin = 2hie ib = Vd −Vin = −hie ib + ve   2 voltage h R Vo = Ad = fe C Vd hie Ad = h fe RC T = RC I Q RC 2T 73 I BQ ib + hfeib gain magnitude is; vC2 = vO ib hie 2 RO sided output. − in + The difference between the two Vin 2 ib RC hie hfeib −V in + ie The output voltage which is taken at one collector terminal + ve − with respect to ground is called 2 ie RO The differential gain for the one-sided output is then one-sided output. vO = h fe ib RC Vin  = hie ib + ve   2 Vin = 2hie ib = Vd −Vin = −hie ib + ve   2 h R Vo = Ad = fe C Vd 2hie Ad = hfe RC 2 T I BQ = I Q RC 4T 74 37 Common Mode Operation V+ RC − If the same input are applied to RC both inputs, the operation is called the common mode. Q2 Q1 + Vin VC 1 VC 2 + − IQ Vin V− 75 vC2 = vO ib ib + + Vin − hie hfeib ie RC + ve One-sided output hie hfeib − Vin ie − vO = − h fe ib RC RC RO ( ) Vin = hie ib + RO 2ie = vcm = hie ib + 2RO 1 + h fe ib The common mode gain for the one-sided output is −hfe RC vO = Acm = vcm hie + 2 (1 + hfe ) RO The output voltage, in general form is vO = Ad vd + Acmvcm = hfe RC 2hie vd − hfe RC hie + 2 (1 + hfe ) RO vcm 76 38 Common-Mode Rejection Ratio The ability of a differential amplifier to reject a common-mode signal is described in terms of the common mode rejection ratio (CMRR). The CMRR is a figure of merit for the diff-amp and is defined as CMRR = Ad Acm For an ideal diff-amp, Acm = 0 and CMRR = ∞. Usually, the CMRR is expressed in decibels: CMRRdB = 20 log Ad Acm CMRR of basic BJT diff-amp is then CMRR = ( 1 + hfe ) RO  Ad 1 = 1+  Acm 2  hie   77 Example: Determine (a) Ad , Acm and CMRR, and (b) If V2=0 and V1 = 20 x10-3 sinωt, find vO. RC = 10kΩ, R1 = 19.4kΩ, VA4= 50V, VBE(on)=0.6V and β = 100. I REF = +10V RC IREF IQ = RC vO R1 V1 Q2 Q1 IQ Q3 V2 RO I REF 1mA = =0.98mA 2 2 1+ 1+  100 vOdc = 10 − 0.49mA  10k = 5.1V RO = V 1 50V = A4 = = 51k  hoe 4 IQ 0.98mA Q4 hie =  −10V 10V − 0.6V − ( −10V ) = 1mA 19.4k  T 26mV = 100 = 5.3k I CQ 0.49mA 78 39 Vin 2 ib vC2 = vO ib + − hie hfeib RC RC hie hfeib −V in + ie + ve − 2 ie RO vO = h fe ib RC Vin  = hie ib + ve   2 Vin = 2hie ib = Vd −Vin = −hie ib + ve   2 h R vo 100  10k = Ad = fe C = = 94.3 vd 2hie 2  5.3k vC2 = vO ib 79 ib + + Vin − hie hfeib ie vO = − h fe ib RC RC + ve − RC hie hfeib − Vin ie RO ( ) Vin = hie ib + RO 2ie = vcm = hie ib + 2RO 1 + h fe ib − hfe RC vO −100  10k = Acm = = = −0.097 vcm hie + 2(1 + hfe ) RO 5.3k + 2 ( 1 + 100 ) 51k CMRR = Ad 94.3 = = 972 or CMRR dB = 20 log ( 972 ) = 59.7 dB Acm −0.097 b) vO ac = AdVd = 1.9 sin t vO = vO dc + vO ac = 5.1 + 1.9 sin t 80 40 Example: Determine vO If Vin = 20 x10-3sinωt. RC = 10kΩ, R1 = 19.4kΩ, VA4= 50V, VBE(on)=0.6V and β = 100. I REF = 1mA +10V RC IREF R1 −v O vO 1dc = vO 2dc = 5.1V + vOdc = vO 2dc − vO 1dc = 0V Q2 Q1 + IQ =0.98mA RC Vin IQ Q3 RO hie =  Q4 T 26mV = 100 = 5.3k I CQ 0.49mA −10V 81 ib Vin 2 vC1 vC2 RC RC ib + − hie hfeib hfeib hie −V in + ie + ve − 2 ie RO h R Vo 100  10k = Ad = fe C = = 188.6 Vd hie 5.3k vO ac = AdVd = 3.77 sin t vO = vO dc + vO ac = 3.77 sin t 82 41 Example: Determine vO If Vin = 50x10-3sinωt. RC = 8kΩ, VA= ∞, β =100, and VEB(on)=0.7V. Neglect the base currents. V+ = 5V IQ = 0.5mA Q1 + Vin vOdc = vOdc Q2 RC hie =  RC RC + V − 2 = 0.25mA  8k  − 5 = −3V vO − IQ T 26mV = 100 = 10.4k  I CQ 0.25mA V - = -5V 83 Vin 2 ib vO ib + − hie hfeib RC RC hfeib hie −V in + ie 2 ie h R vo 100  8k  = Ad = fe C = = 38.46 vd 2hie 2  10.4k  vOac = AdVd = 1.92 sin  t vO = vOdc + vOac = −3 + 1.92 sin  t 84 42 Differential- and Common-Mode Input Impedances The input impedance, or resistance, of an amplifier is as important property as the voltage gain. The input resistance determines the loading effect of the circuit on the signal source. ➢ The differential-mode input resistance is the effective resistance between the two input base terminals when a differential-mode signal is applied. ➢ The common-mode input resistance is the resistance seen by a common-mode input signal. 85 Differential-mode input resistance ib Vin 2 vC1 vC2 RC RC ib + − hie hfeib hfeib hie −V in + ie + ve − 2 ie RO Vin  = hie ib + ve  Vd  2 = Rid = 2 hie Vin = 2hie ib = Vd  −Vin i b = − hie ib + ve   2  86 43 Common-mode input resistance vC2 = vO ib ib + + Vin hie − hfeib ie RC RC hie hfeib − Vin ie + ve RO − Vin = hie ib + RO 2ie = vcm = hie ib + 2RO ( 1 + h fe ) ib vcm = 2 Ricm = hie + 2RO ( 1 + hfe ) ib 87 Example: Determine the differential- and common-mode input resistances of a differential amplifier. RC = 8kΩ, R1 = 18.6kΩ, VA = 100V, VBE(on)=0.7V and β = 100. I REF = +5V RC IREF RC R1 V1 Q2 Q1 IQ Q3 RO Q4 −5V 5V − 0.7V − ( −5V ) = 0.5mA  I Q 18.6k  vO IC = IC 1 = IC 2  V2 hie =  RO = IQ 2 = 0.25mA T 26mV = 100 = 10.4k  I CQ 0.25mA V 1 100V = A = = 200k  hoe 4 I Q 0.5mA Rid = 2hie = 2  10.4k  = 20.8k  2Ricm = hie + 2RO ( 1 + hfe ) = 10.4k + 2  200k ( 101 ) Ricm = 20.2M  88 44 Example: Determine the differential-mode gain and the differential-mode input resistance for RE = 0, and 500Ω. RC = 10kΩ, VA = ∞, and β = 100. V+ RC IC = IC 1 = IC 2  RC vO Q1 + vd − hie =  Q2 RE IQ 2 = 0.25mA T 26mV = 100 = 10.4k  I CQ 0.25mA RE I Q = 0.5mA V− 89 vd 2 ib vO ib + − hie hfeib RC RC hie hfeib −v + ie vO = hfe ib RC RE + ve RE d 2 ie RO − vd  = hie ib + RE ie + ve   2  vd = 2hie ib + 2RE ( 1 + hfe ) ib −vd = − hie ib − RE ie + ve   2 hfe RC vO = Ad = vd 2 hie + RE ( 1 + hfe ) Vd = Rid ib ( = 2 (h ie + RE ( 1 + hfe ) )) 90 45 for RE = 500  Ad = Rid ( = 2 (h h fe RC + RE ( 1 + h fe 100  10k  = 8.21 2  ( 10.4k  + 0.5k   101 ) ) ) ) = 2  ( 10.4k  + 0.5k   101 ) = 121.8k  2 hie + RE ( 1 + h fe ) ie = for RE = 0 Ad = h fe RC 2hie = 100  10k  = 48 2  10.4k  Rid = 2hie = 2  10.4k  = 20.8k  Including an emitter resistor RE decreases the voltage gain but increases the input differential-mode resistance. 91 BJT Differential Amplifier with Active Load V+ Transistors Q1 and Q2 are the Q3  I4 I3   I1 Vin1 differential pair biased with a Q4 I2  Q1 Q2 VO Vin 2 constant current IQ, and transistors Q3 and Q4 form the load circuit. From the collectors of Q2 and Q4, we obtain a one sided output. IQ V92 46 V+ If all transistors are matched and Q3 Q4  I1 Vin1 VO I2  Q1 pure common-mode voltage is applied means that  I4 I3  a Vin1 = Vin2 = vCM, then current IQ splits evenly between Q1 and Q2 Vin 2 Q2 . Neglecting base currents of Q3 and Q4 then I3 = I4 and IQ I1 = I 2 = I 3 = I 4 = V- IQ 2 with no load connected at the output. 93 In actual diff-amp circuits, base currents are not zero. In addition, a second amplifiers stage is connected at the differential amplifier output. V+ Q3 I3  IB5  Vin1 Q1  IE5  I4 Q5 I2  V- Q2   I1 Q4 IO Gain stage Vin 2 IQ VAssume all transistor current gains are equal, even though the current level in Q5 is much smaller than in the other transistors. Current IO is the dc bias current from the gain stage. 94 47 V+ Assuming all transistors are matched and Vin1 = Vin2 = Vcm and I 1 = I 2 Q3 IE 5 = IB3 + IB4 =  I3 + I4 I3  = ( 1 +  ) I B5  I3 + I4  (1 +  ) IB5  I1 Vin1 Q1 I2  V If the base currents and IO are small, then - Q2 IO Gain stage Vin 2 IQ IQ ; I 3 + I 4 Therefore, I B5 ;  I4 Q5  I B5 =  + I4  IE5 = I3 Q4  IE5 V- IQ  (1 +  ) For the circuit to be balanced, that is, for I1 = I2 and I3 = I4 I O = I B5 = IQ  (1 +  ) 95 Small Signal Analysis The resistance RL represents V+ the small-signal input resistance Q3 Q4 of the gain stage.  i4 i3  vO C − iB 2  Q2 + + i2  iO − vd 2 V- Q1  Q5  i1 IQ Signal V - ground vd 2 RL Assuming the base currents are negligible, a signal current i3 = i1 is induced in Q3, and the current mirror produces a signal current i4 equal to i3. The two signal currents, i2 and i4, add to produce a signal current in the load resistance RL. 96 48 vO h fe vd 2hie h fe ib4 = h fe vd 1 hoe 2 2hie 1 hoe 4 RL 1 hoe 4 h fe vd 2hie vO h fe ib 2 = RL 1 hoe 2 h fe vd 2hie  h v  1  1 vO = 2  fe d   P P RL   2hie   hoe 2 hoe 4  Ad =  vO  hfe   1 1 = P P RL   vd  hie   hoe 2 hoe 4  97 Example: Determine the differential-mode gain for load resistances RL = ∞, and 100kΩ. β =100 and VA =100V for all transistors. V+ IC = IC 1 = IC 2  Q3 vO  Q5 iO V IQ = 0.2mA Q2 + − Q1 - − vd 2 2 = 0.1mA Q4 C + IQ vd 2 V 1 1 100V = = A = = 1M  hoe 2 hoe 4 I C 0.1mA RL hie =  T 26mV = 100 = 26k  I CQ 0.1mA V98 49 vO h fe vd 2hie h fe vd 1 hoe 2 2hie 1 hoe 4 RL  h  1  1 Ad =  fe   P P RL   hie   hoe 2 hoe 4  100   for RL =   Ad =   ( 1M P 1M ) = 1923 26k    100  for RL = 100k  Ad =   ( 1M P 1M P 100k ) = 321  26k  A finite load resistance RL causes severe loading effects. 99 I1 0.2mA β=100 and VA=100V V1 5 Q4 Q3 V3 VOFF = 0 VA MPL = 100nV FREQ = 1k 0 V2 VBJTP Q2 BJTN BJTP Q1 V 0 BJTN 5 LIBRARY: C:\Program Files\Orcad\Capture\w or k\abc1.lib 200uV 0V -200uV 0s 0.5ms 1.0ms 2000*V(Q3:b) V(Q1:c)+3.2749 Time 1.5ms 2.0ms 100 50 Basic FET Differential Pair V+ i D1  RD  iD 2 RD Figure shows the basic MOSFET VO vG 1 + M2 M1 − − vGS 1 + vGS 2 vG 2 differential pair, with matched transistors M1 and M2 are always biased in the saturation region. IQ V− 101 DC Analysis V I D1  RD I D = I D1 = I D 2 = + RD  ID2 VO + M1 M2 − − VGS 1 + VGS 2 IQ V− IQ 2 I D = kn (VGS − VT ) 2 VGS = VGS 1 = VGS 2 = VT + VGS = VT + ID kn IQ 2kn VS = −VGS VDS = V + − RD I D + VGS 102 51 Small-Signal Analysis We assume the transistors are matched, with λ = 0 for each transistor, and that the constant-current source is represented by a finite output resistance RO. Differential AC Voltage Gain (Differential Mode-Half Circuit) RD vO −v M2 + d 2 103 vd 2 − + vO g gm v gs RD s vO = − gm v gs RD v gs = − vd 2 vO g R = Ad = m D vd 2 104 52 Common-mode AC Voltage Gain (Common Mode-Half Circuit) vO g RD + gm v gs vcm vO RD s M2 + 2RO vcm 2RO vO = − gm v gs RD vcm  vO − gm RD =  Acm = = v gs + 2RO gm v gs  vcm 1 + 2 gm RO The output voltage, in general form is vO = Ad vd + Acm vcm = gm RD gm RD vd − vcm 2 1 + 2 RO gm 105 Common-Mode Rejection Ratio CMRR of basic MOSFET diff-amp is CMRR = Ad 1 = ( 1 + 2gm RO ) Acm 2 Differential- and Common-Mode Input Impedances At low frequencies, the input impedance of a MOSFET is essentially infinite, which means that both the differential and common-mode input resistances of a MOSFET diff-amp are infinite. 106 53 Example: Determine Ad , Acm and CMRR. RD = 16kΩ, R1 = 30kΩ, kn1= kn2= 0.1 mA/V2 , kn3 = kn4= 0.3 mA/V2, and for all transistors, λ=0 and VTN = 1V. Except assume λ = 0.01 V-1 for M4. V + = 10V i D1  RD v1 M1  iD 2 RD R1 vO v2 M2 I REF IQ M4 M3 + vGS 4 − − V = −10V DC Analysis I REF = + V = 10V I D1  RD RD  I D2 vO M1 R1 I REF M2 20 − VGS 4 2 = kn3 (VGS 4 − VTN ) R1 9VGS2 4 − 17VGS 4 − 11 = 0 VGS 4 = 2.4V and I REF = 0.587 mA I Q = I REF = 0.587 mA I D = I D1 = I D 2 = IQ M4 107 IQ 2 VGS 1 = VGS 2 = VT + + vGS 4 − M3 = 0.293mA IQ 2kn = 2.71V VO = V + − RD I D = 5.31V V − = −10V 108 54 Differential AC Voltage Gain vd 2 − vO g gm v gs + RD s gm = 2 kn I DQ = 2kn I Q = 2  0.1m  0.587 m = 0.343mA / V vO = − gm v gs RD v gs = − vd 2 vO g R 0.343  16 = Ad = m D = = 2.744 vd 2 2 109 vO g Common-mode AC Voltage Gain + gm v gs vcm RD s The output resistance of the current source is RO = Acm = 2RO 1 1 = = 170k   I Q 0.01  0.587 m vO − gm RD −0.343m  16k = = = −0.0467 vcm 1 + 2 gm RO 1 + 2  0.343m  170k CMRR = Ad 2.744 = = 58.8 Acm −0.0467 110 55 MOSFET Differential Amplifier with Active Load V+ Transistors M1 and M2 are n- channel devices and form the M3 M4  iD 4 iD 3  vG 1 + iD 2  M2  i D1 M1 − − vGS 1 differential pair biased with IQ. The VO + vG 2 vGS 2 load circuit consists of transistors M3 and M4, both pchannel devices, connected in a current mirror configuration. A one-sided output is taken from IQ V− the common drains of M2 and M4. 111 DC Analysis The V + M3  I D1 M1 + I D2  M2 − − VGS 1 VO + VGS 2 IQ V− IQ splits evenly between M1 and M2,and M4  I D4 I D3  current I D = I D1 = I D 2 = IQ 2 I D = kn (VGS − VT ) 2 VGS = VGS 1 = VGS 2 = VT + VGS = VT + ID kn IQ 2kn 112 56 Small-Signal Analysis M3 M4  id 4 id 3  + vd 2 id 2  M2  id 1 M1 − gm vd 2 vO vO −v gm vd 2 d 2 + Signal ground rd 4 rd 2 g v  vO = 2  m d  ( rd 2 rd 4 )  2  v Ad = O = g m ( rd 2 rd 4 ) vd ZO = rd 2 rd 4 113 Example: IQ=0.2.mA, kn= kp= 0.1 mA/V2 , kn3 = kn4= 0.3 mA/V2, λn = 0.01 V-1, λp = 0.015 V-1, VTN = 1V and VTP = -1V. Determine (a) VDSQ in each transistor (b) Ad and RO. 10V ID = IQ 2 = 0.1mA I D = kn (VGS − VT ) IQ 2 ID 0.1 = 1+ = 2V kn 0.1 VGS 3 = VGS 4 = VTN + v1 M1  i D1 M2 iD 2   iD 4 M4 iD 3  M3 −10 v2 vO I D = k p (VSG + VTP ) 2 VSG 1 = VSG 2 = −VTP + ID 0.1 = 1+ = 2V kn 0.1 VSD1 = VSG 1 − VGS 3 − V − = 2 − 2 − ( −10 ) = 10V = VSD 2 VDS 3 = VGS 3 = 2V = VDS 4 114 57 gm = 2kn (VGS − VTN ) = 2 kn I DQ gm vd 2 gm = 2 ( 0.1mA / V )  ( 0.1mA) = 0.2mA / V rd 2 = 1 rd 2 rd 4 = 2  P I DQ = 1 = 666.7 k  0.015V −1  0.1mA 1 1 = = 1M  −1  N I DQ 0.01V  0.1mA vO gm vd 2 rd 4 g v  vO = 2  m d  ( rd 2 rd 4 )  2  v Ad = O = gm ( rd 2 rd 4 ) vd Ad = 0.2m ( 1M 0.667 M ) = 80 ZO = rd 2 rd 4 = 400k 115 BiCMOS Circuits • Bipolar transistors have a larger voltage gain than MOSFETs biased at the same current levels. • MOSFET circuits have an essentially infinite input impedance at low frequencies, which implies a zero bias current. • These advantages of the two technologies can be exploited by combining bipolar and MOS transistors in the same integrated circuit. The BicMOS technology is especially useful in digital circuit design, but also has applications in analog circuits. 116 58 Basic BiCMOS Differential Amplifier A basic BiCMOS differential amplifier, with a constant-current V+ source bias and a bipolar active Q1 load. The primary advantages are Q2 VO the infinite input resistance and the zero v1 M2 M1 v2 input bias current. One disadvantage of a MOSFET input stage is a relatively high offset IQ V− voltage compared to that of a bipolar input circuit. Offset voltages occur when the differential-pair input transistors are mismatched. 117 Operational Amplifier (Op-Amp) 118 59 The term operational amplifier, or op-amp for short, was coined in 1947 by John R. Ragazzini to denote a special type of amplifier that, by proper selection of its external components, could be configured for a variety of operations such as amplifications, addition, subtraction, differentiation, and integration. The first application of op-amps were analog computers. The ability to perform mathematical operations was the result of combining high gain with negative feedback. Early op-amps were implemented with vacuum tubes, so they were bulky, power-hungry, and expensive. Integrated circuit (IC) op-amp was developed by Robert J. Widlar at Fairchild Semiconductor Corporation in the early 1960s. In 1968 Fairchild introduced the opamp that was to become the industry standard, the popular µA741. 119 Operational Amplifier (Op-Amp) Equivalent circuit, 741 op-amp 120 60 Simplified BJT Operational Amplifier Circuit An operational amplifier (op-amp) is a multistage circuit composed of a differential amplifier input stage, a gain stage and an output stage. V + = 10V R5 RC RC 19.3k 20k 20k VO 2 I1  V1  IC 1 IC 2  Q1 Q2 5k Q3 Q4 Ri 3 Ri 2 V2 R4 11.5k  IQ Q7 Q5 I R6  R6 16.5k Q6 CE Q9 Q8 R2 VO 3  R1 R3 59.6 I R7  VO R7 5k 59.6 V − = −10V 121 Neglect base currents and as simplification, assume VBE = 0.7V, β = 100 and VA = ∞ for all transistors, except Q8 and Q9 in the Widlar current source circuit. Reference current I1 is V + = 10V R1 RC RC 19.3k 20k 20k VO 2 I1  V1  IC 1 IC 2  Q1 Q2 V2  IQ Q7 Q8 R2 I1 = V + − VBE − V − 10 − 0.7 + 10 = = 1mA R1 19.3k  I  I Q R2 = T ln  1   I Q = 0.4mA I   Q IQ IC 1 = IC 2  = 0.2mA 2 DC voltage at the collector of Q2 is VO 2dc = V + − RC IC 2 = 10 − 20  0.2 = 6V 59.6 V − = −10V 122 61 I R4 = V + = 10V VO 2dc − 2VBE 6 − 1.4 = = 0.4mA R4 11.5k R5 VO 3 5k VO 2 Since base current are assumed negligible, the current IR5 is Q3 Q4 I R 5  I R 4 = 0.4mA R4 11.5k VO 3 dc = V + − R5 I R 5 = 10 − 5  0.4 = 8V 123 V + = 10V Transistor Q5 and resistor R6 from the dc voltage level shifting function. Since R3 = R2 , we have VO 3 I R6 = IQ = 0.4mA Q5 The dc voltage at the base of Q6 is found to be I R 6  R6 VB 6 = VO 3dc − VBE (on) − I R 6 R6 16.5k = 8 − 0.7 − 0.4  16.5 = 0.7V Q6 IQ  Q9 I R7  VO R7 R3 5k 59.6 − V = −10V The relationship produces a zero dc output voltage when a zero differential mode voltage is applied at the input. I R7 = VB 6 − VBE (on) − V − 0.7 − 0.7 + 10 = = 2mA R7 5k The overall differential mode gain can be written  V   V  V  Ad = Ad 1 A1 A2 =  O 2   O 3  O   V1 − V2  VO 2  VO 3  124 62 AC Analysis ( 3th stage ) VO 3 Ri 3 hie 2 = ib5 hie5 hfeib5 T 26mV = = 13k  I BQ 2 0.2mA 100 hie 3 = 650k  , hie 4 = 6.5k  , R6 hie 5 = 6.5k  , 16.5k ib6 hie6 = 1.3k  hfeib6 hie6 The combination of Q5 and Q6 forms an emitter follower, and the gain of output VO 5k stage is R7 ( A2 = ) ( VO 1 VO 3 ) Ri 3 = hie 5 + 1 + h fe  R6 + hie6 + 1 + h fe R7  = 52.8M  For Second Stage AC Analysis Ri 2 = hie 3 + ( 1 + h fe ) hie 4 VO 2 Ri 2 ib3 iT hie3 hfeib3 hie4 = 650k + 101  6.5k = 1304k  125 5k VO 3 Ri3 R5 hfeib4 iT = h fe ib 3 + h fe ib 4 = h fe ib 3 + (1 + h fe ) h fe ib 3 VO 3 = − iT ( R5 Ri 3 ) − iT R5 VO 2 = hie 3 ib 3 + hie 4 ib4 = hie 3 ib 3 + hie 4 ( 1 + hfe ) ib 3 A1 = ( ) −5k ( 100 + 100  101) VO 3 − R5 hfe + hfe ( 1 + hfe ) = = = −39 VO 2 650k + 101  6.5k hie 3 + ( 1 + hfe ) hie 4 126 63 For First Stage AC Analysis − vd 2 ib2 VO 2 hie2 RC hfeib2 Ri2 + vO 2 = hfe ib2 ( RC Ri 2 ) vd = 2hie 2 ib2 Ad 1 = vO 2 h fe RC = = 76.9 vd 2hie 2 Ad = 76.9  ( −39 )  1 = −3000 127 The p-channel transistors M1 and M2 CMOS Operational Amplifier form the input differential pair, and the V+ n-channel transistors M3 and M4 form M6 M5 M8 stage is biased by the current mirror  IQ v1 M2 M1 M5 and M6, in which the reference v2 current is determined by an external C I SET  RSET M3 M4 V− the active load. The diff-amp input vO resistor RSET. The second stage, which is also the M7 output stage, consists of the common source connected transistor M7. Transistor M8 provides the bias current for M7 and acts as the active load. An internal compensation capacitor C1 is included to provide stability. 128 64 kn= 250 μA/V2, kp= 125 μA/V2, λn= λp = 0.02 V-1, |VT| = 0.5V V+ =5V and V - =-5V. I D5 = k p (VSG 5 + VT ) = V+ 2 M6 M5 M8  IQ v1  I SET  id 1 id 3  RSET v2 M2 M1 id 2  C vO id 4  M3 M4 M7 V + − V − − VSG 5 RSET 5 + 5 − VSG 5 mA 2 V − 0.5V ) = 2 ( SG 5 V 225k   VSG 5 = 1.06V 0.125 10V − 1.06V = 39.7  A 225k  = 39.7  A I SET = I Q = I D7 = I D8 V− The currents in M1 through M4 are 19.9 μA. 129 gm = 2kn (VGS − VTN ) = 2 kn I DQ gm = 2 gm vd 2 rd 2 ( 125  A / V )  ( 19.9  A) = 0.1mA / V rd 2 = rd 4 = 2 1 1 = = 2.51M  −1  I DQ 0.02V  19.9  A vO 1 gm vd 2 rd 4 g v  vO 1 = 2  m d  ( rd 2 P rd 4 )  2  v Ad = O 1 = gm ( rd 2 P rd 4 ) vd Ad = 0.1m ( 2.51M P 2.51M ) = 125 130 65 gm7 = 2 kn I DQ gm7 = 2 gm v01 =0 rd7 = rd 8 = rd 8 2 1 1 = = 1.26 M  −1  I D7 Q 0.02V  39.7  A vO = − gm7 v01 ( rd7 P rd 8 ) vO gm v01 ( 250  A / V )  ( 39.7  A) = 0.2mA / V A2 = rd7 vO = − gm7 ( rd7 P rd 8 ) v01 A2 = −0.2m ( 1.25 M P 1.25 M ) = −125 AV = Ad  A2 = ( 125 )( −125 ) = −15625 131 Operational Amplifier An operational amplifier (op-amp) is an integrated circuit that amplifies the difference between two input voltages and produces a single output. noninverting input V1 + V2 − inverting input + V+ VO V − + Op-Amp symbol and power supply connections 132 66 An op-amp is a very high gain differential amplifier with high input impedance and low output impedance. An op-amp contains a number of differential amplifier stage achieve a very high voltage gain. VO V1 i1 + V2 RO + Vid − Ri V V+ VO slope = Aod Aod (V1 − V2 ) (V1 − V2 ) i2 Aod : open loop differential voltage gain V V− Equivalent circuit of an op-amp and simplified voltage transfer characteristic 133 V+ V1 V2 Because the device is biased with + both positive and negative power VO − supplies, most op-amps are direct- VO V V− V + slope = Aod (V1 − V2 ) V V− coupled devices (i.e., no coupling capacitors are used on the input). Therefore, the input voltages V1 and V2 can be dc input voltages, which will produce a dc output voltage VO. Output voltage is limited to V ̶ + ΔV < VO < V+ ̶ ΔV. In older op-amp designs, such as the 741, the value of ΔV is between 1 and 2V. However, in never CMOS op-amp designs, the value of ΔV may be as low as 10 mV. A typical value of the maximum output current is on the order of ±20 mA for a general-purpose op-amp. 134 67 For  A-741 op − amp parameters Ri = 2M  V+ V1 RO = 75 V2 Aod = 200V/mV + VO − V− V = 1V unity-gain bandwidth of f BW = 1MHz VO V V+ V1 i1 + Vid V2 VO + − Ri slope = Aod RO (V1 − V2 ) Aod (V1 − V2 ) V i2 V− 135 Ideal Op-Amp • Open-loop gain Aod is very large and approaches infinity. • The differential input voltage (V1-V2) is assumed to be zero. If Aod is very large and if the output voltage VO is finite, two input voltages must be nearly equal. • The effective input resistance to the op-amp is assumed to infinite, so the two input currents, i1 and i2, are essentially zero. • The output resistance RO is assumed to be zero. V2 − Ri =  + V1 + Aod (V1 − V2 ) VO RO = 0 Aod →  136 68 Basic Op Amp Configurations The most basic op amp circuits are the inverting, noninverting, and buffer amplifiers. Inverting Amplifier One of the most widely used op-amp circuits is the inverting amplifier. R1 Vin i2 = 0 R2 I→ → i1 = 0  − R1 Vin R2 V2 − I→ V0 + V0 + + V1 Inverting amplifier and circuit model for its analysis. I= Vin − Vo R1 + R2 V2 = R1 I + V0  V − Vo  V2 = R1  in  + V0  R1 + R2  R1 R2 V2 = Vin + V0 R1 + R2 R1 + R2 V1 = 0 Aod (V1 − V2 ) 137 R1 Vin R2 I→ V2 − + V0 + Aod (V1 − V2 ) V1 VO = Aod (V1 − V2 )    A R  RA R1 R2 VO = Aod  − Vin − Vo   VO  1 + od 2  = − 1 od Vin R1 + R2  R1 + R2  R1 + R2  R1 + R2  A R V R 1  od 2  O = − 1 = ACL R1 + R2 Vin R2 138 69 R1 − i2 = 0 R2 Vin → I→ Virtual ground V0 or Vin − V2 V0 − V2 + = 0, R2 R1 V2  V1 = 0 Vin V0 + =0 R2 R1 +  i1 = 0  V0 R = − 1 = ACL Vin R2 Hw: V+ =10V, V- = -10V R1=2k and R2=1k. Op-amp is ideal. If Vin = 10sinωt, sketch Vin, V2 and V0. 139 Example: Design a circuit such that the voltage gain is ACL = -5. Assume the op-amp is driven by an ideal sinusoidal source, VS = 0.1sinωt (V), that can supply a maximum current of 5μA. Assume that frequency ω is low so that any frequency effects can be neglected. R2 R1 Vin i1 − Vin VS = R1 R1 if i1 (max) = 5  A, then R1 = V0 + i1 = VS (max) 0.1V = = 20k  i1 (max) 5  A Vin V0 R + = 0  ACL = − 2 R1 R2 R1 −5 = − R2  R2 = 100k  20k  140 70 R2 Example: ACL = -5. VS = 0.1sinωt (V), that can supply RS a maximum current of 5μA R1 − Vin and the output resistance of VS V0 + the source is RS = 1kΩ. i1 = Vin VS = R1 R1 + RS if i1 (max) = 5  A, then R1 + RS = VS (max) 0.1V = = 20k  i1 (max) 5  A R1 = 19k  VS V R2 + 0 = 0  ACL = − R1 + RS R2 R1 + RS R2  R2 = 100k  20k  −5 = − Amplifier with a T-Network i1 = This circuit is often used to obtain very high gains without using large 141 Vin = i2 R1 VX = 0 − R2 i2 = − feedback resistors. R2 Vin R1 i2 + i 4 + i 3 = 0 R2 VX R3 i2 − i3 R4  1 1 1  VO = R3  + + V X R R R 3 4   2 i4 R1 Vin i1 − V0 + VX VX VX − VO − − =0 R2 R4 R3 VO − R2 R3  1 1 1  = AV = + +   Vin R1  R2 R3 R4  142 71 Example: An op-amp with a T-network is to be designed as a microphone preamplifier. The maximum microphone output voltage is 12mV(rms) and the microphone has an output resistance of 1kΩ. The op-amp circuit is to be designed such that the maximum output voltage is 1.2V(rms). The input amplifier resistance should be fairly large, but all resistance values should be less than 500kΩ. R2 VX R3 i2 i3 R4 AV = − R2 R3  1 1 1  + +   R1  R2 R3 R4  AV = − R2  R3  R3 1 + − R1  R4  R1 i4 R1 Vin i1 − V0 + 143 R2 AV = R3  R3 − R2  1+ − R1  R4  R1 If we arbitrarily choose, R2 R3 = = 8 then R1 R1 VX R3 R4 R1 Vin − V0 +  R  R −100 = −8  1 + 3  − 8  3 = 10.5 R4  R4  The effective R1 must include the RS resistance of the microphone. If we let R1 = 49kΩ so that R1,eff =50kΩ, then R2 = R3 =400kΩ. AV = −100 = − R2  R3  R3 −400  400  400 =  R4 = 38.1k 1+  − 1+ − R1,eff  R4  R1,eff 50  R4  50 144 72 • The final design should use standard resistor values. In addition, standard resistors with tolerances of ±2 percent are to be considered. R1 = 51kΩ (standard resistance value is selected), so that R1,eff = 52kΩ and R2 = R3 =390kΩ are chosen then AV = −100 = − R2 R1,eff  R3  R3 −390  390  390 =  R4 = 34.4k 1+  − 1+ − 52  R4  52  R4  R1,eff We may use standard resistor of R4 = 33kΩ. AV == − R2  R3  R3 −390  390  390 = = −103.6 1+  − 1+ − R1,eff  R4  R1,eff 52  33  52 145 Standard resistor values with tolerances ±2 percent are used in the design, so the voltage gain can be written as AV = − R2 ( 1  0.02 )  R3 ( 1  0.02 )  R3 ( 1  0.02 )  1 +  − 1k  + R1 ( 1  0.02 )  R4 ( 1  0.02 )  1k  + R1 ( 1  0.02 ) AV max AV min = 111.6 or + 7.72 percent = 96.3 or -7.05 percent 146 73 Summing Amplifier RF R1 − R2 + V1 V2 V0 V V1 V2 V + + ....... + N + O = 0 R1 R2 RN RF V V V  VO = − RF  1 + 2 + ....... + N  RN   R1 R2 RN VN A special case occurs when R1 = R2 = …. = RN = R then VO = − RF (V1 + V2 + ....... + VN ) R This means that the output voltage is the sum of the input voltages, with a single amplification factor. 147 Example: The output signal generated from a BJT emitter follower amplifier is VO1 =5+0.5sinωt (V) and the effective output resistance is RO = 50Ω. Design a summing amplifier to be connected to the emitter follower such that the output signal is VO = -2 sinωt (V). Assume that the frequency ω is quite low, such that the coupling capacitors are impractical. RO=50Ω + 0.5 sin  t + V1 RE V2=-5V 5V RF R1 − R2 + V0 148 74 RF RO=50Ω V1 R1 − R2 + + 0.5 sin  t V0 + 5V If we make R1 = R2 = 30kΩ, V2=-5V then the effect of the 50Ω output resistance of the emitter follower is negligible. RF (V1 + V2 ) R − RF −2 sin  t = ( 5 + 0.5 sin  t − 5 )  RF = 120k  30k  VO = − Summing amplifier gain is AV = − RF = −4 R 149 Standard resistor values with tolerances ±2 percent are used in the design, so the output voltage can be written as VO = − R ( 1  0.02 ) R ( 1  0.02 ) RF R V1 − F V2 = − F ( 5 + 0.5 sin  t ) − F ( −5 ) R R R ( 1  0.02 ) R ( 1  0.02 ) The dc output voltage is in the range -0.816 ≤ VO(dc) ≤ +0.816V and the ac output voltage is in the range 1.92 ≤ VO(ac) ≤ 2.08V (rms). 150 75 Noninverting Amplifier 1 V+ 1 + + Vin 2 − R1 VO V + Vin + 2 − R2 VO Aod (V1 − V2 ) R2 R1 Noninverting amplifier and circuit model for its analysis. The virtual short means that the voltage difference between V1 and V2 is, for all practical purposes, zero. 151 1 + Vin + 2 R1 Aod (V1 − V2 ) VO V1 = Vin V2 = VO R1 R1 + R2 R2 VO = Aod (V1 − V2 )   R2 VO = Aod  Vin − VO  R1 + R2    A R  V Aod VO  1 + od 1  = AodVin  O = = ACL A R R1 + R2  Vin  1 + od 1 R1 + R2 1  AOL R2 R1 + R2 ACL = Aod R + R2 R = 1 = 1+ 2 Aod R1 R1 R1 R1 + R2 closed loop gain 152 76 V+ 1 + + Vin 2 Virtual short VO − V− R2 R1 V1  V2 V2 = V1 = Vin = VO  R1 R1 + R2 VO R = 1 + 2 = ACL Vin R1 153 Example: What is the range of ACL? + Vin + VO − V1  V2 V2 = V1 = Vin = R2 VO R = 1 + 2 = ACL Vin R1 200k 10k R1 10k VO  R1 R1 + R2 if R1 min = 10k  R1 max = 20k  200k = 21 10k 200k ACL = 1 + = 11 20k ACL = 1 + 11  ACL  21 154 77 Voltage Follower (Buffer, or Impedance Transformer) V+ 1 + + VO − Vin 2 R2 R2 →  − R1 = 0 V− V0 Vin + VO = Aod (V1 − V2 ) R1 V1 = Vin V2 = VO VO = Aod (Vin − VO ) VO ( 1 + Aod ) = AodVin VO Aod = = 1 = ACL Vin 1 + A0 d or V1  V2 = Vin = VO − VO = 1 = ACL Vin V0 Vin 155 + − Example: RS=100kΩ V0 RS=100kΩ + + + + Vin VO source RL=1kΩ RL=1kΩ Vin − load If the output impedance of a signal source is large, a voltage follower inserted between the source and a load will prevent loading effects, that is, it will act as a buffer between the source and the load. 156 78 Nonideal Effects in Operational Amplifier Circuits Practical Op-Amp Parameters • Input voltage limits • Output voltage limits • Output current limitations • Finite open-loop voltage gain • Input resistance • Output resistance • Finite bandwidth • Slew rate • Input offset voltage • Input offset currents 157 Input and Output Voltage Limitations For linear circuit operation, all BJTs in an op-amp circuit must be biased in the forward active region and all MOSFETs must be biased in the saturation region. For these reasons, there are limitations to the range of input and output voltages in op-amp circuits. V+ Q5 Vin1 = Vin2 = VCM Q6 R1 Minimum base-collector voltage Q8 Q11 Q9 is zero so that the transistor is Q7 Vin1 Q1 V- V Q2 VO - Vin 2 RL Q12 Q4 Q3 R2 V- Q10 still biased in the active mode. The maximum value of VCM is VCM(max) = V+ ̶ 2VEB(on) and minimum value R3 ̶ of is VCM VCM(min) = V + 2VBE(on). 158 79 For MOS, the maximum value of VCM is VCM(max) = V+ ̶ [VSG1 + (VSG11 + VTP11)] and the minimum value of VCM is VCM(min) = V ̶ + [VGS13 + VTP1]. V+ M 12 M9 M 10 M7 M8 M 11 I REF vO v1 M1 M2 v2 M5 M6 VB 2 M 13 M3 M4 V− 159 Minimum base-collector voltage is zero so that the transistor is still biased in the active mode. The maximum output voltage is VO(max) = V+ - [VEB8(on)+VBE11(on)] and minimum value of VO is VO(min) = V- + [VBE4(on)+ VEB12(on)]. For the all CMOS circuit, the maximum output voltage is VO(max) = V+ - [VSG10+(VSG8+VTP8)] and the minimum output voltage is VO(min) = V- + [(VGS6 -VTN6)+VGS13] 160 80 Finite Open-Loop Gain Inverting Amplifier R1 Vin − R2 + + R2 V R1 ACL = O = Vin R2  1  1+ 1+  AOL  R1  − V0 AOL (V2 − V1 ) In the limit as AOL → ∞ , the closed-loop gain is equal to the ideal value, designated ACL(∞), which for the inverting amplifier is ACL(∞) = -R2 / R1. ACL = ACL (  ) 1+ 1 ( 1 − ACL (  ) ) AOL 161 To determine the variation in the closed-loop gain with changes in openloop gain, we take the derivative of ACL with respect to AOL. ACL (  ) ( 1 − ACL (  ) ) dACL = dAOL  A + ( 1 − A (  ) )  2 CL  OL  which can be rearranged in the form. dACL dAOL = ACL AOL 1 − ACL (  ) AOL  1 − ACL (  )  1+  AOL   Normally, ACL (  ) = AOL dACL dAOL 1 − ACL (  )  ACL AOL AOL 162 81 1+ Noninverting Amplifier R2 − R1 + Vin V ACL = O = Vin + V0 AOL (V2 − V1 ) 1+ R2 R1 R2  1  1+  AOL  R1  In the limit as AOL → ∞ , the closed-loop gain is ACL(∞) = 1 + R2 / R1. ACL = ACL (  ) A () 1 + CL AOL Taking the derivative of ACL with respect to AOL and rearranging terms, we obtain dACL dAOL  ACL  =   ACL AOL  AOL  163 Inverting Amplifier Closed-Loop Input Resistance R2 R2 Rif Rif − R1 Vin i1 V1 V0 + RL i1 → V1 ii − Ri + RO V0 + AOL (V2 − V1 ) RL −V ( A R − 1 R2 ) VO VO − ( − AOLV1 ) VO − V1 + + = 0  VO = 1 OL O RL RO R2 1 RL + 1 RO + 1 R2 i1 = V1 V1 − VO i 1 1 1 1 + AOL + RO RL +  1 = = + Ri R2 V1 Rif Ri R2 1 + RO R2 + RO RL In the limit as AOL → ∞, Rif →0, which means that V1 → 0, or V1 is at virtual ground. This is a characteristic of ideal inverting amplifier. 164 82 Example: Determine the closed-loop input resistance at the inverting terminal of an inverting amplifier. R2 = 10kΩ, AOL = 105 and Ri = 1MΩ. Assume the output resistance RO of the op-amp is negligible. R2 Rif Solution : If RO = 0, then − R1 Vin V1 i1 1 1 1 + AOL 1 1 + 10 5 = + = 6+  10 −6 + 10 Rif Ri R2 10 10 4 V0 + RL The closed-loop input resistance is then Rif  0.1 165 Noninverting Amplifier Closed-Loop Input Resistance R2 R2 R1 − R1 Rif + Vin V1 V1 V0 Rif + RL i1 + − Vd Ri RO V0 AOLVd RL + + i1 → Vin VO VO − AOLVd VO − V1 V R + AOLVd RO + + = 0  VO = 1 2 RL RO R2 1 RL + 1 RO + 1 R2 i1 = V1 V1 − VO + R1 R2 V1 = Vin − Ri i1  R ( 1 + AOL ) + R2 ( 1 + Ri R1 ) Vin = Rif = i i1 1 + R2 R1 In the limit as AOL → ∞, Rif → ∞, which is a property of the ideal noninverting amplifier. 166 83 Example: Determine the closed-loop input resistance at the noninverting terminal of a noninverting amplifier. R1 = 10kΩ, R2 = 100kΩ, AOL = 105 and Ri = 1MΩ. Assume the output resistance RO of the op-amp is negligible. R2 − R1 Solution : Rif + R ( 1 + AOL ) + R2 ( 1 + Ri R1 ) Rif = i 1 + R2 R1 Rif = Vin 10 6 ( 1 + 10 5 ) + 10 5 ( 1 + 10 6 / 10 4 ) 1 + 10 / 10 5 4  V1 V0 + RL i1 10 11  11 167 Nonzero Output Resistance An actual op-amp circuit has a nonzero output resistance, which means that the output voltage, and therefore the closed-loop gain, is a function of the load resistance. R2 R1 V1 − − vd + + Rof iO V0 RL This equivalent circuit of both an inverting and noniverting amplifier is used to find the output resistance. 168 84 R2 R1 RO − Vd Rof Ri iT + + AOLVd Vd ; VT −VT R1 R1 + R2 + iT = VT − AOLVd VT + RO R1 + R2 VT AOL  R1  VT +  VT + RO RO  R1 + R2  R1 + R2 iT 1 AOL  R1  1 = +  + VT RO RO  R1 + R2  R1 + R2 iT = A  R1 iT 1 =  OL  VT Rof RO  R1 + R2  AOL   1 =    RO  1 + R2 R1  169 Example: Determine the closed-loop output resistance an inverting amplifier. R1 = 10kΩ, R2 = 100kΩ, AOL = 105, RO =75Ω and Ri = 2MΩ. R2 R2 R1 − Rof + Vin + iO R1 V0 RL RO − Vd Rof Ri iT + + AOLVd VT +  10 5   1 A  1 1  OL  =  Rof RO  1 + R2 R1  75   1 + 100k 10k  Rof = 8.25m 170 85 Frequency Response Open-loop and Closed-loop Frequency Response The frequency response of the open-loop gain can be written as |AOL| AOL ( f ) = AO 1+ j AO f f PD 1 AO : low-frequency open-loop gain fPD fT f fPD : dominant-pole frequency Bode plot, open-loop gain fT : unity-gain bandwidth fT = f PD  AOL is also called gain-bandwidth product 171 The closed-loop gain ACL can be written ACL = AOL 1 +  AOL where β is the feedback transfer function. For the noninverting amplifier, this feedback transfer function is = ACL ( f ) = 1 R 1+ 2 R1 AO  AO 1+ j 1+ 1 + R2 R1 1 f   AO f PD  1 +  1 + R2 R1   172 86 Normally, AO>> [1+(R2/R1)]; therefore, the low-frequency closed-loop gain is ACLO = 1 + R2 R1 as previously determined. For AOL>> ACLO, Equation is approximately ACL ( f ) = ACLO f 1+ j  A  f PD  O   ACLO  The 3 dB frequency, or small-signal bandwidth, is then  A  f 3dB = f PD  O   ACLO  173 Gain-Bandwidth Product ACL ( f = funity ) = 1 = f unity f PD ( AO ACLO ) where funity is the unitygain frequency of the ACLO   funity 1+   fPD ( AO ACLO )  2 closed-loop system. If AOL>>1, then Equation yields  A   ACLO  f unity = ACLO f PD  O  = AO f PD = fT  ACLO  |A| open loop AO The closed loop unity-gain bandwidth ACLO of frequency the or closed-loop system is essentially the same as 1 that of the open-loop amplifier. fPD f3-dB fT f 174 87 Example : An audio amplifier system is to use an op-amp with an op-amp loop gain of AO = 2x105 and a dominant-pole frequency of 5 Hz. The bandwidth of the audio system is to be 20 kHz. Determine the maximum closed-loop gain for the audio amplifier. Solution : The unity-gain bandwidth is found as fT = AO f PD = ( 5 Hz ) ( 2  10 5 ) = 10 6 Hz = 1MHz Since the gain-bandwidth product is a constant, we have fT = ACL f 3 − dB  ACL = fT f 3 − dB 10 6 Hz = = 50 20  10 3 Comment: If the closed-loop gain is less than or equal to 50, then the required bandwidth of 20 kHz for the audio amplifier will be realized. 175 Slew Rate, SR When a step function is applied at the op-amp input, the output voltage cannot change instantaneously with time because of capacitance effects within the op-amp circuit. The maximum rate at which the output changes with time is called the slew rate. If a large sinusoidal signal or step function is applied to an op-amp circuit, the input stage can be overdriven and the small-signal model will no longer apply. 176 88 V+ V+ IQ Q1  IC 1 Q2 IC 2  C Q3 VO Slope=SR Slope=-SR time  I C 4 VO1 IC 3  Emitter follower output stage  Vin1 input pulse output response IQ Vin 2 I O V(t) Q5 Simplified op-amp circuit Q4 V− V− If a large step voltage greater that 120 mV is applied at V2 with V1 held at ground potential, then Q2 is effectively cutoff, which means IC2 ~ 0, and IC1 = IQ. The entire bias current is switched to Q1. since IC3 ~ IC1, then we also have IC4 ~ IQ. 177 The base current into Q5 is very small; therefore, the current through the compensation current C is IO = IC4 = IQ. Since the voltage gain of the emitter-follower output stage is essentially unity, the capacitor current can be written as IO = C d (VO − VO 1 ) dt The gain of the second stage is large, which means that VO1 << VO. Equation then becomes IO  C dVO dVO IQ = IQ or = dt dt C The maximum current through the compensation capacitor is limited to bias current IQ; consequently, the maximum rate at which the output voltage can change is also limited by the bias current IQ. 178 89 The maximum rate of change of the output voltage is the slew rate of the op-amp, the units of which are usually given as volts per millisecond. IQ  dV  Slew rate( SR) =  O  =  dt max C Although the rate of change of in output voltage can be either positive or negative, the slew rate is defined as a positive quantity. Example: Calculate the slew rate of the 741 op-amp. (IQ = 19μA – bias current, C = 30pF –internal frequency compensation capacitor) Slew rate( SR ) = IQ C = 19  A = 0.63  10 6 V / s = 0.63 V /  s 30 pF 179 Example: SR = 2 V /  S . Vin varies by 0.5V in 10sec. What is the closed-loop voltage gain? O.5V VO = ACLVin VO = ACL Vin ACL = VO Vin  = ACL t t Vin  SR = ACL t 10µA SR 2V /  S = = 40 Vin 0.5V / 10  S t 180 90 Offset Voltage If the two input devices are mismatched, the currents in the two branches of the diff-amp are unequal and this effects the diff-amp dc output voltage. In fact, the internal circuitry of the entire op-amp usually contains imbalances and asymmetries, all of which can cause a nonzero output voltage for a zero input differential voltage. Input Stage Offset Voltage Effects Several possible mismatches in the input diff-amp stage can produce offset voltages. 181 Basic Bipolar Diff-Amp Stage V+ iC 1  RC RC + VO V1 + VBE 1 Q1 − Q2 −  iC 2 + − iC V2 VBE VBE 2 IQ VOS V− The iC versus VBE characteristics for two unmatched bipolar transistors. 182 91 V+ When the transistor are matched and the iC 1  RC collector resistors are matched, which means that the offset voltage is zero. iC 1 = I S 1eVBE 1 iC 2 = I S 2 e + VO V1 The collector currents can be written as RC + VBE 1 Q1 − Q2 −  iC 2 + V2 − VBE 2 IQ T V− VBE 2 T where IS1 and IS2 are related to the reverse-saturation currents in the B-E junctions and are functions of the electrical and geometrical transistor properties. 183 For iC 1 = iC 2 , I S 1eVBE 1 T = I S 2 eVBE 2 T  e( VBE 1 −VBE 2 ) T = IS2 IS1 The offset voltage is defined as VOS = VBE 1 − VBE 2 eVOS T = I  IS2  VOS = T ln  S 2  IS1  IS1  Example: Calculate the offset voltage in a bipolar diff-amp for a given mismatch between the input transistors. I S 1 = 10 −14 Amp and I S 2 = 1.05  10 −14 Amp I  VOS = T ln  S 2  = 1.27 mV  IS1  184 92 Bipolar Active Load Diff-Amp Stage V+ If, however, Q3 and Q4 are not exactly matched, then iC1 and iC2 may not be equal Q3 Q4  iC 1 V1 + VO iC 2  Q1 VBE 1 since the active load influences the split in  iC 4 iC 3  Q2 − − + V2 VBE 2 the bias current, even if Q1 and Q2 are matched. This effect is caused by a finite Early voltage. Taking the Early voltage into account, but neglecting base currents, we IQ can write the collector currents as V- iC 1 = iC 3 = I S 1eVBE 1 T iC 2 = iC 4 = I S 2 eVBE 2 T  vCE 1  VBE 3 1+  = I S 3e VA1    vCE 2 1+ VA2   VBE 4  = I S 4e   vCE 3  1+  VA3   vCE 4  T  1+  VA4  185  T If we assume that Q1 and Q2 are matched IS1 = IS2 =IS and VA1 = VA2 = VAN. Assume that Q3 and Q4 are slightly matched, so that IS3 ≠ IS4 but still assume VA3 = VA4 = VAP. For V1 = V2, we have VBE1 = VBE2; also VEB3 = VEC3 = VEB. Taking the ratio of Equations produces iC 1 iC 2 vCE 1 v 1 + EB I VAN VAP = = S3 v v IS4 1 + CE 2 1 + EC 4 VAN VAP 1+ vCE 1 v 1 + CE 2 I VAN VAN = S3 v v IS4 1 + EB 1 + EC 4 VAP VAP 1+ 186 93 Example: Calculate the change in the output voltage for a given mismatch in the active load transistors. V+ = 10V. Assume that Q1 and Q2 are matched with VBE1 = VBE2 = 0.6V, and assume that VBE3 = VBE4 = VEC3 = 0.6V. Let IS3 = 1.05IS4. also assume that VAN = VAP = 50V. V1 = V2 = 0  V + − v EB 3 − v EB1 − vCE 1 = 0 + V vCE 1 = V + − v EB 3 + v BE 1 = V + = 10V Q3 Q4  iC 4 iC 3   iC 1 V1 + VBE 1 v EC 4 + vCE 2 = V + + v BE 2 = 10.6V VO iC 2  Q1 Q2 − − + VBE 2 IQ V- V2 vCE 2 = 10.6V − v EC 4 vCE 1 10 1+ VAN 50 = 1.186 = v 0.6 1+ 1 + EB 50 VAP 1+ 187 V+ Q3 Q4  iC 4 iC 3  IS3 IS4 v 10.6 − vCE 4 1 + CE 2 1 + VAN 50 = 1.186 = 1.05 v EC 4 v EC 4 1+ 1+ VAP 50 which yields  iC 1 V1 + VBE 1 VO iC 2  Q1 Q2 − − + V2 VBE 2 IQ V- v EC 4 = 1.94V Comment: A 5 percent difference between the properties of Q3 and Q4 produces a change from 0.6 to 1.94V in the E-C voltage of Q4. 188 94 MOSFET Diff-Amp Stage V+ i D1  RD RD functions of the electrical and geometric properties of the two transistor, and the  iD 2 VO vG 1 + M1 M2 − − vGS 1 vG 2 + vGS 2 threshold voltages VTN1 and VTN2 are also functions of the transistor electrical properties. If there is a mismatch in electrical or geometric parameters, then we may have kn1 ≠ kn2 and VTN1 ≠ VTN2. IQ V The conduction parameter kn1 and kn2 are − The drain currents can be As with the bipolar diff-amp, the input offset voltage is defined as the input differential written as i D1 = kn1 (VGS 1 − VTN 1 ) 2 i D 2 = kn2 (VGS 2 − VTN 2 ) 2 voltage that must be applied to produce a zero output voltage, or VOS = VGS 1 − VGS 2 189 When the offset voltage is applied, iD1 = iD2 = IQ /2; when the two drain resistors are equal, then VO = 0. VOS = VGS 1 − VGS 2 =  i  i D1 + VTN 1 −  D 2 + VTN 2  kn1  kn2  The various difference and average quantities are defined as follows kn = kn1 − kn2 kn1 + kn2 2 k kn1 = kn + n 2 k kn2 = kn − n 2 kn = VTN = VTN 1 − VTN 2 VTN 1 + VTN 2 2 VTN = VTN + 2 VTN = VTN − 2 VTN = VTN 1 VTN 2 190 95 VOS =  i  i D1 + VTN 1 −  D 2 + VTN 2  kn1  kn2  VOS =  IQ  1 1 −   + VTN 2  kn + kn 2 kn − kn 2  If we assume that ∆kn << kn then equation reduces to −1 I Q  k n    + VTN 2 2kn  kn  VOS = The offset voltage in the MOSFET diff-amp stage is a function of the differences in conduction parameters and threshold voltages. 191 Example: Calculate the offset voltage in a MOSFET diff-amp. Transistor parameters kn1 = 105 μA/V2, kn2 = 100 μA/V2, and VTN1 = VTN2. Assume IQ = 200μA. kn = kn1 − kn2 = 105 − 100 = 5  A V 2 V+ i D1  RD RD kn =  iD 2 kn1 + kn2 105 + 100 = = 102.5  A V 2 2 2 VO vG 1 + M1 M2 − − vGS 1 + vGS 2 vG 2 The magnitude offset voltage is VOS = 1 I Q  k n    + VTN 2 2kn  kn  VOS = 1 200  5    = 24.1mV 2 2  102.5  102.5  IQ V− 192 96 Offset Voltage Compensation In many applications, especially those for which the input signal is large compared to the offset voltage VOS, the effect of the offset voltage is negligible. However, there are situations in which it is necessary to compensate for, or “null out,” the offset voltage. Two such methods are: (a) an externally connected offset compensation network, and (b) an operational amplifier with offset-null terminals. 193 External Offset Compensation Network Offset compensation circuit for inverting amplifier R2 V + VX VY R3 R5 = R4 − Vin R1 V0 + R5 R5 V −  VY  V+ R4 + R5 R4 + R5 R4 V− R5 Example : R5 = 100Ω, R4 = 100kΩ, and a 100kΩ potentiometer R3. Let V+ = 15V and V- = -15V. Determine voltage range at VY. 0.1 0.1 ( −15 )  VY  ( +15 )  −15mV  VY  +15mV 0.1 + 100 0.1 + 100 194 97 Offset compensation circuit for noninverting amplifier R2 V+ R4 − R1 VX R3 R5 = R4 V0 R5 V− + R5 R5 V −  VX  V+ R4 + R5 R4 + R5 Vin Example : R5 = 100Ω, R4 = 100kΩ, and a 100kΩ potentiometer R3. Let V+ = 15V and V- = -15V. Determine voltage range at VX. 0.1 0.1 ( −15 )  VX  ( +15 )  −15mV  VX  +15mV 0.1 + 100 0.1 + 100 The voltage gain of the noninverting amplifier becomes a function of the compensation network. Since R5 << R4, then the gain of the amplifier, the good approximation, is AV = 1 + R2 R1 + R5 195 Offset Null Terminals Basic bipolar input diff-amp stage, including a pair of offset-null terminals connected to a potentiometer. V+ R2 x = ( R2 // ( 1 − x ) Rx ) IQ Vin1 Q1 Q3 Offset-null terminal −  IC 4 Q4 + − VBE3 VBE4 R1 R2 V− x 1-x V− Vin 2 Q2  iC 1 iC 2  Rx R1 x = ( R1 // xRx ) Offset-null terminal VBE 3 + iC 1 R1 x = VBE 4 + iC 2 R2 x i  VBE 3 = T ln  C 1   IS3  i  VBE 4 = T ln  C 2   IS4  i  i  T ln  C 1  + iC 1 R1 x = T ln  C 2  + iC 2 R2 x  IS3   IS4  196 98 Vin1 V+ If a mismatch occurs between Q3 IQ and Q4, meaning IS3 ≠ IS4, then Q1  iC 1 iC 2  Q3 and R2x can be introduced to  IC 4 compensate Q4 + − Offset-null terminal deliberate mismatch between R1x Vin 2 Q2 − VBE3 VBE4 R1 Offset-null terminal for the transistor mismatch and the adjustment can make R2 iC1 = iC2. Similarly, a deliberate mismatch between R1x V − and R2x can be used to compensate x 1-x for a mismatch between Q1 and Q2. Rx V− 197 Example : Determine the required difference between R1x and R2x, and the value of x in the potentiometer to compensate for a mismatch between active load transistors Q3 and Q4. Assume that IQ =200μA, which means that we want ic1 = ic2 = 100μA. Let IS3 = 10-14A and IS4 = 1.05x10-14A. V+ I Q = 200  A Vin1 Q1  iC 1 iC 2  Q3 Offset-null terminal Vin 2 Q2 −R  IC 4 Q4 + − VBE3 VBE4 1 1k R2 1k V− x 1-x V− Rx = 100k Offset-null terminal i  i  T ln  C 1  + iC 1 R1 x = T ln  C 2  iC 2 R2 x  IS3   IS4  −6  100  10  26mV ln   + 0.1  R1 x −14  10   100  10 −6  = 26mV ln  + 0.1  R2 x −14   1.05  10  which yields R2 x − R1 x = 12.7  = ( R2 // ( 1 − x ) Rx ) − ( R1 // xRx ) x = 0.349 198 99 Input Bias Current The input currents to an ideal op-amp are zero. In actual op-amp, however, the input bias currents are not zero. If the input diff-amp consists of a pair of JFETs, the input bias currents are normally much smaller than those in a bipolar differential pair. A MOSFET input differential pair, generally, must include protection devices, so the input bias currents are also not zero even this case. Bias Current Effects If the input transistors are not exactly identical, − then IB1 ≠ IB2. the input bias current is then I B1 → → IB2 defined as the average of the two input currents ,or + IB = I B1 + I B 2 2 199 The difference between the two input currents is called the input offset current IOS and is given by IOS = I B1 − I B2 Bias Current Compensation R2 R1 I B1 VX → VY − → + IB2 R3 The effect of bias currents in op-amp V0 circuit can be minimized with a simple compensation technique (Resistor R3 is connected to noninverting terminal of op-amp). 200 100 R2  R  VO = I B1 R2 − I B 2 R3  1 + 2  R1   If IB1 = IB2 = IB and the combination of three R1 I B1 VX → VY resistances can be adjusted to produce VO = − V0 → + IB2 R3 0, then   R  0 = I B  R2 − R3  1 + 2    R1      R  RR R2 = R3  1 + 2   R3 = 1 2 = R1 P R2 R1  R1 + R2  Equation shows that R3 should be made equal to the parallel combination of R1 and R2, to eliminate the effect of equal input bias currents. If R3 = R1//R2 and if the bias current s are not equal, then VO = R2 ( I B1 − I B2 ) = R2 IOS 201 Example: Determine the bias current effect in an op-amp circuit, with and without bias compensation. R1 = 10k  and R2 = 100k  . Assume I B1 = 1.1 A and I B1 = 1.0  A VO = R2 I B1 = ( 100k  )( 1.1 A ) = 0.11V We design R3 such that R3 = R1 P R2 = 10 P 100 = 9.09k  VO = R2 ( I B1 − I B 2 ) = 100k  ( 1.1 A − 1 A ) = 0.01V Even if the input offset current is not zero, the effect of the bias currents can be reduced substantially by incorporating resistor R3. 202 101 Additional Nonideal Effects Offset Voltage Temperature Coefficient The electrical properties of transistors are functions of temperature which means that the input offset voltage is a function of temperature. The rate of change of offset voltage with temperature is defined as the temperature coefficient of the offset voltage, or input offset voltage drift, and is given by TCVOS = dVOS dT Input Offset Current Temperature Coefficient The input bias currents are functions of temperature. The input offset current temperature coefficient is TCIOS = dIOS dT 203 Common Mode Rejection Ratio (CMRR) When separate inputs are applied the op-amp, the resulting different signal, is the difference between the two inputs. + Vd + − V+ V0 V− + + V1 + − V2 V+ V0 V− VO = AOLVd = AOL (V1 − V2 ) 204 102 When both input signals are the same a common signal element due to two inputs can be defined as the average of the sum of two signals. + + VC − VC = V+ V0 Output voltage, V0 VO = AdVd + AcVC V− CMRR = 1 (V1 + V2 ) 2 Ad AC or CMRRdB = 20 log Ad dB AC CMRR of a differential amplifier measures its ability to reject common mode noise amplifying the differential portion of the input signal. 205 APPLICATION AND DESIGN of INTEGRATED CIRCUTS 206 103 OP-AMP Applications Current to Voltage Converter In some situations, the output of a device or circuit is a current. An example is the output of a photodiode or photodedector. We may need to convert this output current to an output voltage. RS − − V0 iin V0 iin + + RS iin + VO = RS iin VO = 0  VO = − RS iin RS 207 Voltage to Current Converter i1 1 i1 = i2 = 0 + + Vin i2 IR 2 − V2  V1 = Vin IL ZL IR = Vin = IL R R 208 104 Voltage to Current Converter R2 R1 2 + − Z= R1 Z L R1 + Z L V1 = VX Z = V2 R2 + Z VX Vin 1 + R2 IL  ZL Vin − V2 VX − V2 + =0 R1 R2 R1 Vin VX  1 1  + − +  V1 = 0 R1 R2  R1 R2  209 Vin VX  R1 + R2  Z + − VX = 0  R1 R2  R1 R2  R2 Z R2 R1 2 + − VX Vin 1 + R2 IL  ZL Z ( R1 + R2 )  Vin  1 + −  VX = 0 R1  R2 R1 R2 ( R2 + Z )  R1 R1 R2 + R1 Z − ZR1 − ZR2 R1 R2 ( R2 + Z ) R (R − Z) Vin + 2 1 VX = 0 R1 R2 R1 ( R2 + Z ) VX = Z + R2 Vin Z − R1 210 105 IL = IL = R2 R1 2 + V1 Z Z Z + R2 = VX = Vin Z L Z L ( R2 + Z ) Z L ( R2 + Z ) ( Z − R1 ) Vin R1Vin R1 Z L = ( R1 + Z L ) Z L  R1 Z L − R  R1 Z − R12 − R1 Z  1  R1 + Z L  − IL = VX Vin 1 −Vin R1 + R2 IL  ZL R1 211 Example: Find the range of values of RL for which this circuit operates like constant-current source. I 5V 15 − 10 = 0.1A = 100mA 50 VL min = 0  RL = 0 I= +15V 50 − VL max = 15 − 50  I − VEC ( sat ) 2 RL max 1 + 1k RL VO 15 − 50  0.1 = 10V V 10 = L max = = 100  I 0.1 0  RL  100 212 106 Difference Amplifier R2 Ri i  Vin → i R1 Va Vb x − VO R1 y + R2 An ideal difference amplifier amplifies only the difference between two signals; it rejects any common signals to the two input terminals. For example, a microphone system amplifies an audio signal applied to one terminal of a difference amplifier, and rejects only 50 Hz noise signal or “hum” existing on both terminals. Vy = 213 Vb R2 = Vx R1 + R2 Va − Vx VO − Vx + =0 R1 R2 R2 Ri i  Vin → Va VO  1 1  i + − +  Vx = 0 R1 R2  R1 R2  Va VO  R1 + R2  R2 + − Vb = 0  R1 R2  R1 R2  R1 + R2 VO = R2 (Vb − Va ) R1 Ad = R2 R1 Ri = R1 Va Vb x − VO R1 y + R2 differential gain Vin = 2R1 differential input resistance i 214 107 Example: Design a difference amplifier with a specified gain Ad = 30. standard valued resistors are to be used and the maximum resistor value is to be 500kΩ. R2 Ri i  Vin → i R1 Va Vb x − VO R1 y + R2 Ad = Ri = R2 390k  =  R1 = 13k  R1 R1 Vin = 2R1 = 26k  i 215 Example: Design a difference amplifier with a differential input impedance of Ri =5 kΩ, a differential voltage gain of 100, and a common-mode gain of zero. Ri = 2.5k  2 R R2 Ad = 2 = 100 =  R2 = 250k  R1 2.5k  Ri = 2R1  R1 = When Va = Vb, the input is called a common-mode input signal. The common-mode input voltage is defined as Vcm = Va + Vb 2 The common-mode input voltage is defined as Acm = VO Vcm Ideally, when a common-mode signal is applied, VO = 0 and ACM = 0. 216 108 Example : Calculate the CMRR of a differential amplifier. Let R2 /R1 = 10 and R4 /R3 = 11. R2 R1 Va Vb x − VO R3 y + R4  R4   R   R3  R  Vb − 2 Va VO =  1 + 2   R1   1 + R4  R1    R3    11  VO = ( 1 + 10 )   Vb − 10Va  1 + 11  VO = 10.0833Vb − 10Va 217 R2 VO = 10.0833Vb − 10Va vd = Vb − Va vd 2 v Vb = vcm + d 2 Va = vcm − R1 Va Vb x − VO R3 y + R4 v  VO = 10.0833  vcm + d 2  vd     − 10  vcm −  = 10.042vd + 0.0833vcm 2    10.042  CMRR ( dB ) = 20 log 10   = 41.6dB  0.0833  Comment: For a good differential amplifiers, typical CMRR values are in the range of 80-100dB. This example shows how close the ratios R2 /R1 and R4 /R3 must be in order to achieve a CMRR value in that range. 218 109 Instrumentation Amplifier It is difficult to obtain a high input impedance and a high gain in a difference amplifier with a reasonable resistor values. (One solution is to insert a voltage follower between each source and the corresponding input.) 219 R V2 + − R − R − VO + I − R1 Vd R + R + V1 R R2 R1 Va Vb x − VO R1 y + Vd = Vb − Va  V = Vd R1 = R2 = R  O R2 220 110 I= V2 + − R − V1 − V2 R1 Vd = ( 2R + R1 ) I Vd = I − R1 Vd  2R  Vd =  1 +  (V − V2 ) R1  1  R +  2R  VO =  1 +  (V1 − V2 ) R  1  + V1 2R + R1 (V1 − V2 ) R1 221 Standard IA Symbol V1 + − V+ Sense V− − RG + − V2 V+ V− V+ Load + V− Ref The sense and reference voltages are sensed right at the load terminals, so the effect of any signal losses in the long wires is eliminated by including these losses within the feedback loop. 222 111 AMP-01 (Analog Device) Voltage Gain, G V+ RS  20 RS  G =   RG  14 +IN 18 15 13 1 12 7 Amp-01 RG 2 -IN 9 8 Gain Range, 11 3 10 V 0.1 to 10 000 − 223 Example: Determine the range of differential voltage gain. + V1 − 20k 20k 1k V2 − VO + 100k 50k −  2R  VO =  1 +  (V1 − V2 ) R1   20k 20k +  2R  2  100 if R1 = 1k  Ad =  1 + = 201  = 1+ R 1  1   2R  2  100 if R1 = 51k  Ad =  1 + = 4.92  = 1+ R1  51  112 Example: Determine the range required for resistor R1, to realize a differential gain adjustable from 5 to 501. V2 R + R − VO R 100k I −  2R  VO =  1 +  (V1 − V2 ) R1   V1 − + R1 R1 R R R +  2R  for max differential gain   1 +  = 501 R 1     2R for min differential gain   1 + =5 R1 + 100k   R = 50.4k and R1 = 201 225 Integrator and Differentiator Vi Z1 − Z2 VO + Vi VO V −Z2 + =0 O = Z1 Z 2 Vi Z1 where Z1 and Z2 are generalized impedances Two special circuits can be developed from this generalized inverting amplifier. 226 113 Op-Amp Integrator 1 Z VO = − 2 Vi = − sC Vi Z1 R C R Vi VO = − − 1 V sRC i VO + 1 →  dt s t 1 VO = VC − Vi (t ')dt ' RC 0 where VC is the voltage across the capacitor at t = 0. 227 Op-Amp Differentiator Z2 R Vi = − V 1 i Z1 sC VO = − sRCVi VO = − R C Vi − VO + s→ d dt VO = − RC dVi dt A limitation this circuit is that any discontinuity in the input voltage Vi will cause a spike in the output voltage. 228 114 Example : Determine the time constant required such that the output reaches +10V at t=1ms. Sketch and label the resulting output waveform.(VC(0-)=0V) C −1V R − VO + t t 1 1 t VO = VC − Vi ( t ')dt ' = − ( −1)dt ' =   RC 0 RC 0 RC 10 = 1ms  RC = 0.1ms RC 229 HW: Sketch and label the resulting output waveform.(VC(0-)=0V) 0.1m F Vin(V) 1 Vin t(ms) 1 2 3 4 2kΩ − VO + -1 115 Comparator is an op-amp operated in an open-loop configuration. A comparator compares two voltages to determine which is large. V+ Va + Vb − VO V− Zero-Crossing Detector + + − Vi V+ V + VO   − V VO V− Vi  0 Vi  0 231 Vin Nonlinear Circuit Applications Vm Precision Half-Wave Rectifiers − V0 Vm VO VO1 + Vin IL  RL V01 Vin  0, id = VO1  0, id  0 VO = iL RL VO 1 = V + VO = 0.7 + VO Vm+0.7 +0.7 VO 1 = AOL (V1 − V2 ) = AOL (Vin − VO ) V- 232 116 0.7 + VO = AOL (Vin − VO ) − ( 1 + AOL )VO = −0.7 + AOLVin VO = Vin AOLVin 0.7 − AOL AOL VO = Vin − Vin  0 , VO = 0 , + VO VO1 IL  0.7 AOL for Vin  VO1  0 , RL 0.7 AOL D is OFF − VO1 = V ( sat ) Diode in ON id >0 , whenever Vin is greater than 0.7 / AOL. Thus this rectifier circuit reduces the diode turn-on voltage by the factor AOL. For example, AOL = 104 this means that the turn-on voltage for this precision rectifier will only be 0.07mV instead of 700mV. 233 A potential problem in this circuit exists for Vin < 0. the feedback loop is broken so that the op-amp output voltage VO1 will saturate near the negative supply voltage. Vin switches positive, it will take time for the interval circuit to recover, so the response time of the output voltage may be relatively slow. In addition, for Vin < 0 and VO = 0, there is now a voltage difference applied across the input terminals of the op-amp. Most op-amps provide input voltage protection so the op-amp will not be damaged in this case. However, if the op-amp does not have input protection, the op-amp may be damaged if the input voltage is larger than 5 or 6V. 234 117 Precision Half-Wave Rectifier R D1 R Vin − D2 VO VO1 + RL Vin  0 , VO1  0 , D1 is ON, D2 is OFF VO = 0 , and VO1 = −0.7V Vin  0 , VO1  0 , D1 is OFF, D2 is ON Vin VO + = 0  VO = −Vin R R VO1 = 0.7 + VO 235 R D1 R Vin Vin + V0 Vm − D2 VO VO1 RL -1 Vin V0 Vm V01 V01 Vm+0.7 -1 +0.7 +0.7 -0.7 -0.7 Vin 236 118 Precision Full-Wave Rectifier R Vin R VO 1 − R R − D1 V1 + D2 R VO + VO 2 237 Vin  0 , V1  0 , R Vin R − D1 is ON, D2 is OFF VO 1 + R V V1 + D2 R R − + VO VO 2 Vin VO1 + = 0  VO1 = −Vin R R VO VO1 + = 0  VO = −VO1 = Vin R R  VO = Vin 238 119 Vin  0, V1  0, R VO 1 − R Vin D1 is OFF, D2 is ON R R − D1 + V1 + VO + V R VO 2 Vin VO 2 VO 2 2 + + = 0  VO 2 = − Vin R R 2R 3 VO − VO 2 0 − VO 2 3 + = 0  VO = VO 2 R 2R 2 VO = −Vin R R Vin VO 1 − R R − D1 V1 + 239 VO + D2 Vin Vm R VO 2 V0 V0 Vm -1 1 Vin 240 120 High Resistance AC Voltmeter D2 D1 R2 I→ I R1 − − VO D3 + + D4 VO1 Vin  0, Vin + VO1  0, D1 and D4 are ON D2 and D3 are OFF I = Vin R1 VO = R2 I VO = R2 Vin R1 241 Vin  0, VO1  0, D1 and D4 are OFF D2 and D3 are ON I= −Vin R1 VO = R2 I VO = − R2 Vin R1 Vin Vm V0 V0 Vm -1 1 Vin 242 121 Peak Detector − VO + Vin C 243 Log Amplifier − R1 Vin − vD + The diode is to be forward biased, so the input signal voltage is limited to iD → positive value. The diode current is i1 → VO + iD = I S ( e vD T − 1) If the diode is sufficiently forward biased, (-1) term is negligible and iD  I S e v D T VO = −v D and i1 = Vin = iD = I S e −VO R1 T If we take the natural log of both sides of this Equation, we obtain  V   V  V ln  in  = − O  VO = −T ln  in  T  I S R1   I S R1  244 122 For this circuit, the output voltage is proportional to the log of the input voltage. One disadvantage of this circuit is that the reverse-saturation current IS is a strong function of temperature, and it varies substantially from one diode to another. A more sophisticated circuit uses bipolar transistors to eliminate the IS parameter in the log term. − + i1 → + − VO R2 − R1 V1  i2 V2 + 245 HW: − i1 → y − R1 V1 x + R2  i2 V2 + 20k −333k VO + 20k 333k R V  VO = log 10  1 2   R2 V1  246 123 Antilog Amplifier or Exponential Amplifier + vD − Vin iD → iD  I S e v D R1 −i 1 → VO + T Vin = v D VO = − R1 i1 = − R1 iD = − R1 I S e −Vin T The output voltage is an exponential function of the input voltage. 247 Operational Transconductance Amplifier (OTA) Vp Vn  icont OTA is a voltage-input, current-output → iO amplifier. For ideal OTA, both the input and + gm − output impedance infinite. For ideal OTA, the output current can be written as iO = gm (V p − Vn ) Symbol where gm is called the unloaded transconductance, with units of ampers per volt. Transconductance can be varied by changing the control current. The OTA can then be used to electronically program functions. gm = icont 2T 248 124 Equivalent circuit of ideal OTA iO Vp gm (V p − Vn ) Vn Example: Find the voltage gain, input and output impedances of the OTA circuit. Vin Vn Z in V p − VO = iO RL  icont gm + VO → iO RL ZO ( ) iO = gm V p − Vn = gm ( 0 − Vin ) VO = − gmVin RL VO = − gm RL Vin Z in =  and ZO = RL 249 Example: Find the voltage gain, input and output impedances of the OTA circuit. VO = iO RL Vin Vn Z in V p  icont + gm → iO − VO RL ZO ( ) iO = gm V p − Vn = gm (Vin − 0 ) VO = gmVin RL VO = gm RL Vin Z in =  and ZO = RL 250 125 Example: Find the voltage gain of the OTA circuit. Vin + vD − + gm − VO → iO R1 R2 VO = iO ( R1 + R2 ) iO = gm v D = gm (Vin − iO R2 )  iO = VO = ( R1 + R2 ) AV = gmVin 1 + gm R2 gmVin 1 + gm R2 VO gm ( R1 + R2 ) = Vin 1 + gm R2 251 HW: Find the voltage gain of the OTA circuit. R2 R1 Vin + gm − VO 252 126 Example: Find the voltage gain of the OTA circuit. Vin − gm 1 → iO1 + − gm 2 → iO 2 + VO iO 1 + iO 2 = 0 iO 1 = gm 1 ( 0 − Vin ) = − gm 1Vin iO 2 = gm 2 ( 0 − VO ) = − gm 2VO − gm 1Vin − gm 2VO = 0 VO g = − m1 Vin gm 2 253 Example: Vin + gm → iO − VO = iO VO C 1 1 = gmVin sC sC VO gm = Vin sC 254 127 Example: iO = gm (Vin − VO ) Vin VO = iO + gm → iO VO − 1 sC 1 gm (Vin − VO ) sC g  g  VO  1 + m  = m Vin sC  sC  VO gm = Vin gm + sC VO = C 255 VC Example: Find AV. 25kΩ 33kΩ Vin VO = − RF iO = − RF gm v D VO = − RF gm AV = + R1 470Ω R2 vD −  icont + gm → iO − R2 Vin R2 + R1 RF RC 25kΩ − VO + VO VC R R R R i R R = − F 2 gm = − F 2 cont = − F 2 = −0.27VC Vin R2 + R1 R2 + R1 2T R2 + R1 2T RC The amplification factor is a function of the control voltage VC. This circuit can be used as an amplitude modulator. The Vin input may be the carrier signal and the VC input may be the audio signal. OTAs can also be used to design voltage-controlled filters and voltagecontrolled oscillators. 256 128 OP-AMP CIRCUIT DESIGN Example : Solve the following set of equations using operational amplifiers. 3x + 6 y − 10 = 0 2x − y − 8 = 0 R R1 − R2 + V1 VO 1 V01 V2 10 − 2y 3 −R R = V1 − V2 R1 R2 3 x + 6 y − 10 = 0  x = Let V1 = − 1V , V2 = y, and VO1 = x R 10 R = and =2 R1 3 R2 Let R = 10k   R1 = 3k  and R2 = 5k  257 R − R3 V3 V02 R4 + V4 2x − y − 8 = 0 Let  y = 2x − 8 R R VO 2 = − V3 − V4 R3 R4 V4 = 1V  R = 8  R4 = 1.25k  R4 V3 = − x  R = 2  R3 = 5k  R3 258 129 10k 10k − 3k -1V 5k x − 10k + y -x + 10k 5k − 1.2k + 1V 259 Example : Design a circuit that provides the analog computer solution of a differential equation d2 y dy + 2 + 2y = 0 2 dt dt All resistors used in this circuit are to be 1MΩ y " = −2 y ' − 2 y R y '' C1 − + VO 1 = − 1 RC 1 R = 1M , VO 1 = − y ' y'  y " dt = − RC C 1 = 1 F = − y' 1 260 130 C2 −y' VO 2 = − − R 1 RC 2 R = 1M , y  ( − y ') dt = + RC = 2y 2 C 2 = 0.5  F VO 2 = 2 y + R V2 − R V2 − V1 V3 − V1 + =0 R R V2 − 2V1 + V3 = 0 V3 + V3 = 2V1 − V2 V1 261 1μF y '' 1M 0.5μF − 1M −y' + − 2y + + − 1M 1M 262 131 Reference Voltage Source Design Zener diodes are used to provide a constant or reference voltage source. A limitation, however, was that the reference voltage could never be greater than the zener voltage. A zener diode with an op-amp can be combined to provide more flexibility in the design of reference voltage sources. V+ Rs + + VZ − −  R  VO =  1 + 2  VZ R1   VO R2 R1 263 HW : Design a voltage reference source with an output of 10V. Use a Zener diode with a breakdown voltage of 5.6V. Assume the voltage regulation will be within the specifications if the Zener diode is biased between 1-1.2mA. R1 R2 − VS R3 D1 VO + IF  R4 + VZ RF − 264 132 Difference Amplifier and Bridge Circuit Design A transducer is a device that transforms one form of energy into another form. One type of transducer uses nonelectrical inputs to produce electrical outputs. A pressure transducer is a device in which, for example, a resistance is a function of pressure, so that pressure can be converted to an electrical signal. Often, the output characteristics of this transducer is measured with a bridge circuit. V+ R1 R1 + VO1 − R3=R2(1+δ) Resistance R3 represents the transducer, and parameter δ is the deviation of R3 from R2 due to the input response of the transducer. The R2 output voltage VO1 is a measure of δ. 265 If VO1 is an open circuit voltage , then V + R1 R1 + VO1 R3=R2(1+δ) − R2  R2 ( 1 +  ) R2 VO1 =  −  R1 + R2 ( 1 +  ) R1 + R2  + V  which reduces to  R P R2  + VO1 =   1 V  R1 + R2  VO1 must be connected to an instrumentation amplifier. In addition, VO1 is directly proportional to supply voltage V+; therefore, this bias should be a well-defined voltage reference. 133 HW : Design an amplifier system that will produce an output voltage of ±5V when the resistance R3 deviates by ±1% from the value of R2. V+ R1 + R1 + VO1 − − − R7 R6 R5 R2 R3=R2(1+δ) R8 + R7 − VO R8 + 267 Design Application : Electronic Thermometer with an Instrumentation Amplifier The temperature range to be measured is 0 to 50 ˚C. The output voltage is to be in the range of 0 to 5V with 0V corresponding to 0 ˚C and 5V corresponding to 50 ˚C. Solution : An electronic thermometer is designed by using temperature characteristics of a pn junction diode. Q1 V+ Q2 IREF1 R1 i1 + VD1 − + Q4 Q3 VAT − i2 + VD2 − IREF2 R2 268 134 The two diodes, D1 and D2, are assumed to be matched devices. All transistors are also assumed to be matched. Neglecting base currents, i1 = I REF 1 and i2 = I REF 2 The output voltage is defined as the difference between the voltages across the two diodes, or V+ Q2 Q1 + i1 IREF1 + VD1 R1 Q4 Q3 VAT − − i2 + IREF2 VD2 R2  i i  VAT = VD1 − VD 2 = T  ln 1 − ln 2  IS   IS i I VAT = T ln 1 = T ln REF 1 i2 I REF 2 VAT = − kT I REF 1 ln q I REF 2 The output voltage, VAT, is now directly proportional to absolute temperature T. 269 V+ Q2 Q1 i1 IREF1 + VD1 R1 − + If we let IREF1/IREF2 = 5 Q4 Q3 VAT − i2 + IREF2 VD2 R2 − VAT = kT I REF 1 kT ln = ln ( 5 ) q I REF 2 q VAT = 1.388  10 −4 T T: absolute temp. VAT = 1.388  10 −4 ( TC + 273.15 ) VAT = 1.388  10 −4 TC + 37.913  10 −3 Since neither terminal of the output voltage is at ground potential, this potential is applied to an instrumentation amplifier. + VAT − Instrumentation Amplifier A=? VO1 270 135 + VAT − Instrumentation Amplifier A=? VAT = 6.94  10 −3 A= VO1 −1  −144 VAT VO1 = − A  VAT = −144 ( 1.388  10 −4 TC + 37.913  10 −3 ) VO1 = −20  10 −3 TC − 5.46 The output of the instrumentation amplifier will be applied to a summing amplifier in addition to an offset voltage. RF VO1 R1 − R2 + A VAT VREF V0 271 RF −3 VO1 = −20  10 TC − 5.46 VAT A -144 VO1 VREF R1 − R2 + V0 TC = 0  VO1 = −5.46 VO = − RF R R R VO 1 − F VREF = 0V = − F ( −5.46 ) − F VREF R1 R2 R1 R2 VREF = R2 5.46 let VREF = 5.46V  R2 = R1 R1 TC = 50  VO1 = −6.46 VO = − RF R (VO1 + VREF ) = 5V = − F ( −6.46 + 5.46 ) R1 R1 RF = 5  RF = 5 R1 R1 272 136 Let VZ = 3.6V V+ Rs + + VZ − − VREF R4 R3   R  R  VREF =  1 + 4  VZ = 5.46 =  1 + 4  3.6 R3  R3    R4 = 0.52 R3 273 V+ Q1 Q2 i1 + VD1 IREF1 R1 + VAT The primary advantage of Q4 Q3 − i2 + VD2 − − this system is that the IREF2 R2 output voltage is a linear function of temperature. Instrumentation Amplifier A -144 V + 50k VO1 10k − 10k + 3.6V − + − VREF 10k V0 + 5.2k 10k 274 137 V ( t ) = 0.8sin(0 t ) + 0.5sin(4 0 t ) + 0.2sin(16 0 t ) Active Filters Low pass The world “filter” refers to process of removing undesired portion of the High pass frequency spectrum. The world “active” implies the use of one or more active Band pass devices in the filter circuit. Band reject Frequency Time 275 High Pass Filter C Vin VO T ( s) = R VO ( s ) sRC = Vin ( s ) 1 + sRC Active High Pass Filter − C + Vin VO R 276 138 Low Pass Filter R Vin VO T ( s) = C 1 1 + sRC Active Low Pass Filter − R VO + Vin C 277 General Two Pole Active Filter y3 − y2 y1 Vb Vin + VO Va y4 VO = Vb y1 (Va − Vin ) + y2 (Va − Vb ) + y3 (Va − VO ) = 0 ( y1 + y2 + y3 )Va − y2Vb − y3VO − y1Vin = 0 ( y1 + y2 + y3 )Va − ( y2 + y3 )VO − y1Vin = 0 278 139 y3 y2 (Vb − Va ) + y4 (Vb − 0 ) = 0 − ( y2 + y4 )Vb − y2Va = 0 y2 y1 y + y4 Va = 2 VO y2 Vb Vin VO + Va y4  y 2 + y4  VO − ( y2 + y3 )VO − y1Vin = 0  y2  ( y1 + y2 + y3 ) ( y2 + y4 ) − y2 ( y2 + y3 )  VO − y1 y2Vin = 0 ( y1 + y2 + y3 )  VO ( y1 y2 + y1 y4 + y22 + y2 y4 + y2 y3 + y3 y4 − y22 − y2 y3 ) = y1 y2Vin VO y1 y 2 = = T ( s) Vin y1 y2 + y1 y4 + y2 y4 + y3 y4 279 sn T ( s) = m s + ... m=1 1st order m=2 2nd order : : n=0 n=1 n=2 low pass band pass high pass 280 140 Low Pass Filter T ( s) = y 1 = G1 y2 = G2 y3 = sC 3 y4 = sC 4 1 sC 3 G1G2 G1G2 + sG1C 4 + sG2 C 4 + s 2C 3C 4 G1G2 C 3C 4 O2 = = C (G + C2 )   GG s2 + 4 1 s + 1 2 s 2 +  O  s + O2 C 3C 4 C 3C 4  Q  O2 = − R2 R1 Vin Vb + VO Va Q= G1G2  O = C 3C 4 1 R1 R2C3C4 C 3 R1 R2 C 4 R1 + R2 1 sC 4 281 HW : Design a second order low pass filter. fO = 4980Hz Q = 0.5 0.01μF 2.26k 2.26k Vin + 0.01μF − VO 282 141 HPF y3 y1 = sC 1 y2 = sC 2 − y3 = G3 y4 = G4 y2 y1 Vb Vin VO + Va y4 T ( s) = y1 y2 y1 y2 + y1 y4 + y2 y4 + y3 y4 283 BPF R3 R1 C2 Vin + C1 R2 − VO 142 Example : Find the voltage transfer characteristic equation − Vin gm 1 → iO 1 + + → iO2 gm 2 VO − C1 iO1 = gm1 (Vin − VO ) C2 iO 2 = gm 2 (VP 2 − VO ) VP 2 = iO1 VO = iO 2 1 1 = gm1 (Vin − VO ) sC1 sC1 1 sC 2 285 VO = 1 sC 2  1    gm 2  gm 1 (Vin − VO ) sC − VO       g g g  g g VO  1 + 2m 1 m 2 + m 2  = 2m 1 m 2 Vin s C 1C 2 sC 2  s C 1C 2  − g m1 g m 2 VO = Vin s 2 C 1C 2 + gm2 C 1 s + gm1 gm2 Vin gm 1 → iO 1 + C1 + → iO2 gm 2 VO − C2 gm 1 gm 2 C 1C 2 = = T ( s) gm 2 gm 1 gm 2 2 s +s + C2 C 1C 2 286 143 Example: Show that the circuit simulates a grounded inductance. iO 1 = gm 1V + → iO 1 gm 1 − Leq 1   iO 2 = gm 2  0 − iO 1 sC   1 iO 2 = − gm 2 iO 1 sC − gm 2 gm 1 iO 2 = V = −I sC V C Z in = = s = sLeq I gm 2 gm 1 C − gm 2 +  iO 2 Leq = C gm 2 gm 1 287 Generalized Impedance Converter Zeq Z1 Z2 − + + − Z3 Z4 Z5 288 144 Zeq V − V1 I=  V1 = V − IZ 1 (1) Z1 V − V1 V − V2 + =0 Z2 Z3 + Z1 (2) + V1 V − V2 V + =0 Z4 Z5 − Z2 V V V2 + − =0 Z4 Z5 Z4 V −  Z  V2 =  1 + 4 V Z5   V I V (3) Z3 V2 + Z4 V Substituting Eqn(1) and Eqn(3) into Eqn(2) Z5 V V V1 V2 + − − =0 Z2 Z3 Z2 Z3 289 Zeq Z4 Z −V +I 1 =0 Z3 Z5 Z2 V Z1 Z 3 Z5 = = Z eq I Z2 Z4 + V I V Z1 + V1 Z2 − V −  1 Z4  1  V − IZ 1 1  V + − − 1+ V = 0 Z2 Z3  Z5   Z2 Z3   1 Z  IZ 1 1 1 V + − − − 4 + 1 = 0  Z2 Z3 Z2 Z3 Z3 Z5  Z 2 Z3 V2 + Z4 V Z5 1.All Z’s are resistances, except Z2 (or Z4 ) which is capacitance. Let Z 2 = Z eq = 1 ; sC 2 Z 1 Z 3 Z 5 R1 R3 R5 C RRR RRRC = = s 2 1 3 5 = sL  L = 1 3 5 2 1 Z2 Z4 R4 R4 R4 sC 2 Indicating that circuit simulates a grounded inductance. 290 145 2. All Z’s are resistances, except for Z1 and Z5 which are capacitances. Zeq 1 Let Z 1 = SC 1 1 and Z 5 = SC 5 + V I V Z1 1 1 R SC 1 3 SC 5 R3 Z eq = = 2 R2 R4 S C 1C 5 R2 R4 + V1 Z2 − V Z3 V2 − + s = j  s 2 = − 2 Z4 V − R3 1 Z= 2 =− 2 ;  C1C5 R2 R4  D CC RR D= 1 5 2 4 R3 Z5 This circuit now simulates a grounded frequency dependent negative resistance. 291 Homework : Specify component values for a band pass response with f0 = 2kHz and Q=25. Find k. Vin VO R C R1 + − C2 − + + kVO R3 R4 R5 292 146 Solution : VO + R Vin C L 1 s V RC T ( s) = = O 1 1 Vin s2 + s+ RC LC O = 1 LC , Q=R C L 293 Switched-Capacitor Filter Switched-capacitor filters have the advantage of an all-IC circuit. The filter uses small capacitance values and realizes large effective resistive values by using a combination of capacitors and MOS switching transistors. i V1 + R + V2 R= V1 − V2 i 294 147 Φ1 Φ2 Φ1 V1 V2 M1 TC M2 C Φ2 When Φ1 = 1, Φ2 = 0 ➔ Capacitor charges up to V1. When Φ1 = 0, Φ2 = 1 ➔ Capacitor discharges to V2. (assuming V1>V2) The amount of charge transferred during this time process is Q = C(V1-V2) and the transfer occurs during one clock period TC. The equivalent current is then I eq = V − V2 Q C (V1 − V2 ) = = fC C (V1 − V2 ) = 1 TC TC Req 295 Φ1 i Φ2 Φ1 V1 + R + V1 V2 V2 M1 TC M2 C Φ2 I eq = f C C (V1 − V2 ) = V1 − V2 Req where fC is the clock frequency and Req is the equivalent resistance as given by Req = 1 fC C Using this technique, we can simulate an equivalent resistance by alternately charging and discharging a capacitor between two voltages levels. A large equivalent resistance can be simulated by using a small capacitance and an appropriate clock frequency. 296 148 Example : Determine the clock frequency required to simulate a 1MΩ resistance. Assume a capacitance of C = 20 pF. Φ1 Φ2 Φ1 V1 V2 M1 TC M2 C Φ2 1 1 1  fC = = = 50kHz. fC C CReq ( 20 pF )( 1M  ) Req = 297 T ( s) = RF CF Vin − R1 VO ( s ) − RF 1 = Vin ( s ) R1 1 + sRF C F and the low cutoff frequency VO + Φ1 f 3dB = Φ2 C2 Φ1 R1eq = Φ2 − Vin C1 1 f C C1 1 2 C F RF and RFeq = 1 fC C 2 CF VO + 149 Φ1 Φ2 C2 T ( s) = − RF 1 R1 1 + sRF C F Φ1 T ( s) = − 1 fC C 2 1 1 f C C 1 1 + j 2 fC F fC C 2 T ( s) = −C1 C2 1 + j 1 f f C C 2 2 C F Φ2 − Vin CF C1 VO + = −C1 1 C2 1 + j f f 3dB the low-frequency gain is − C 1 C 2 , and the 3dB frequency is f C C 2 2 C F Example : A one-pole low-pass Φ1 Φ2 switched capacitor filter is to be designed such that the low- C2 frequency gain is -1 and the cutoff Φ1 Φ2 − frequency is 1kHz. Vin −C1 1 T ( s) = C2 1 + j f f 3dB CF C1 VO + −C 1 = −1  C 1 = C 2 = 75 pF C2 If we set the clock frequency to fC = 10kHz, then f 3dB = fC C 2 10kHz  C 2 C = 1kHz =  2 = 0.628  C F  120 pF 2 C F 2 C F CF 150 Sinusoidal Oscillators An oscillator is a circuit that produces an output without the application of an input signal Phase-Shift Oscillator − − + V1 − R V4 R V5 + V2 + V3 C C RF R1 − VO R V6 + C 301 − − + − 1 = RC − RF V1 = V R1 O V5 = V0 =  (s +)  (s +)  (s +) R R V4 V5 + V2 + V3 C C RF R1 − V3 = V1 V1 = − RF R1      + s  VO   V3 = − RF R1      + s  VO   V5 = − RF R1      + s  VO   VO V6 + R C 2 3 − RF    − RF 3 3 = 1  = ( s +  ) = s 3 + 3s 2 + 3s 2 +  3   R1   + s  R1 3 302 151 s = jO  R  s 3 + 3s 2 + 3s 2 +  3  1 + F  = 0 R1     R  j ( −O3 + 3O 2 ) +  −3O2 +  3  1 + F   = 0 14444442 4444443  R1    144444444442 4444444444 3 =0 =0 For frequency of oscillation For condition of oscillation frequency of oscillation, O 3 RC O3 − 3O 2 = 0  O = 3 = 303 Condition of oscillation H ( s) =  R  3O2 −  3  1 + F  = 0 R1    R  3 ( 3 2 ) −  3  1 + F  = 0 R1   R R 9 − 1− F = 0  F = 8 R1 R1 σ h(t) jω jω0 σ t -jω0 (system poles on the jω axis) h(t) jω k  h(t ) = A sin(n t +  ) s + n2 2 h(t) jω t σ t 304 152 HW: Derive the expressions for the frequency of oscillation and the condition of oscillation. C1 C2 − R1 R2 + VO − + V01 R C 305 Wien-Bridge Oscillator R2 − R1 VO + VX x R R C Zp = R 1 + sRC Zs = 1 + sRC sC C 306 153  R  VO =  1 + 2  VX R1   VX = R2 VO Zp Zs + Z p − R1 VO  R  Zp  VO =  1 + 2    VO R1   Z s + Z p    R2   Z p  =1 1+  R1   Z s + Z p   + VX x R R C C     R2   1 =1 1+   R1   3 + sRC + 1   sRC   307 s = jO    R2  1 1+  1 R  1   3 + j RC + O  jO RC    =1    Imaginary component must be zero. jO RC + 1 1 = 0  O = jO RC RC The magnitude condition is them ω0 : frequency of oscillation  R2   1  R2 =2 1+   = 1  R1   3  R1  R2 = 2 states that to ensure the start-up oscillation, R1 we must have R2 2 R1 308 154 Colpitts Oscillator R C2 C1 L L VO g C2 gmVgs R C1 309 1 Vgs = 1 sC 2 sL + sC 2 L VO VO g C2 gmVgs VO V VO + O + gmVgs + =0 1 1 sC 1 R sL + sC 2 R C1  1  VO  gm + sC 2 + ( 1 + s 2 LC 2 )  + sC 1   = 0 R   2 s LC 2 1  s 3 LC 1C 2 + + s ( C 1 + C 2 ) +  gm +  = 0 R R  s = jO  1 O2 LC 2  2  gm + −  + jO ( ( C1 + C 2 ) − O LC1C 2 ) = 0 R R   310 155 The condition of oscillation implies that both the real and imaginary components of equation must be zero. The oscillation frequency, ω0. O = 1 CC L 1 2 C1 + C 2 The condition of oscillation O2 LC 2 R = gm + C 1  2 = gm R R C1 gm R is the magnitude of gain. 311 Crystal Oscillators A piezoelectric crystal, such as quartz, exhibits electromechanical resonance characteristics in response to a voltage applied across the crystal. The oscillations frequency is determined by the crystal dimension. This means that crystal oscillators are fixed frequency devices. L CS CP r The inductance L ~ few hundred henrys CS order of 0.001 pF CP order of a few pF 312 156 R C2 C1 313 Z ( s) = 2 1 s + ( 1 LC S ) sC P 2  C P + C S  s +   LC S C P  reactance Serial resonance ( Z ( jω )=0 ) occurs at inductive 1 fS = 2 LC S Parallel resonance ( Z ( jω ) →∞ ) occurs at capacitive inductive 1 LC S C P 2 CS + CP f fp capacitive capacitive fP = fs Between the resonant frequencies fs and fp, the crystal reactance is inductive, so the crystal can be substituted for an inductance, such as that in a coplitt oscillator. 314 157 HW: Derive the expressions for the frequency of oscillation and the condition of oscillation. λ =0. V+ L C1 C→∞ V 0 I R C2 V− 315 R2 R1 − L VO + C1 C2 316 158 Sample and Hold Circuit A S/H circuit is an essentially analog memory circuit in which a voltage is temporarily stored on a capacitor. S/H circuits are used with A/D converters to hold the input signal constant during the conversion period. C 317 − − VO + Vin + C sample and control signal 318 159 IN OUT IN T.G. OUT control signal control signal IN T.G: Transmission Gate C OUT If Control=15V (logic 1) switch OFF If Control=-15V (logic 0) switch ON 319 Digital-to-Analog (D/A) Converters For the results of digital computations to be used in the analog world, it becomes necessary to convert the digital values to proportional analog values. Figure shows the block diagram of a typical digital-to-analog (D/A) converter, which accepts an n-bit parallel digital code as input and provides an analog current or voltage as output. 320 160 R-2R Resistor Ladder D/A Converter 3R R 0 R 1 R 2 R n−2 2R n −1 − VO 2R 2R 2R 2R b0 b1 b2 2R 2R bn −2 bn −1 + VB b0 : LSB bn−1 : MSB 321 In analyzing the operation of this circuit, the most important fact the observe is that the impedance to the left and to the right of any node in the circuit is always equal to 2R 2R − 3R 2R At node (n-1) VO 2R R + VB 2 VO = + VB + VB 2 3R 2R − VO + 322 161 2R n−2 R 2R VB n −1 −3R 2R VO 2R + VO = + 3R R − 2R VO + VB 4 VB 4 + 323 ( n − 1) (n − 2) VB bn−1 21 V VO = B2 bn− 2 2  VO =    n − ( n − 1) =1 n−n = 0   VB b1 2 n− 1 V VO = Bn b0 2 VO = The overall output from op-amp as b b b  b VO = VB  n−11 + n−22 + .... + n1−1 + 0n  2 2 2   2  decimal equivalent of n - bit binary code  VO = VB   2n   324 162 Example : n=8 (8 bit D/A converter ), DAC VB = 10V VREF b0 b1 b2 b7 b6 b5 b4 b3 b2 b1b0 b3 ( 1 0 0 1 1 1 0 1)2 = ( 157 )10 VO b4 b5 b6 b7 0 1 1 1 0 1 1 0 VO = 10  + 2 + 3 + 4 + 5 + 6 + 7 + 8  = 6.13V 2 2 2 2 2 2 2 2   or  157  VO = 10   8  = 6.13V  2  325 2-bit Flash A/D Converter VREF Vin R 2 3 R 2 ADC − b0 b1 C + − B + − R 1 Vin VREF Priority Encoder bO b1 A + R 2 326 163 VREF for n bit , 2 − 1 comparator Example: n = 2 n Vin 2 2 − 1 = 3 comparator V V1 = REF 3R VREF V2 = 3R V V3 = REF 3R − R 2 3 C + − R + − 2 R VREF = 2 6 3R VREF = 2 2 5R 5 = VREF 2 6 Priority Encoder B R bO b1 A + 1 R 2 ABC b1 b0 Vin  V1 0 0 0 0 0 V1  Vin  V2 1 0 0 0 1 V2  Vin  V3 1 1 0 1 0 V3  Vin 1 1 1 1 1 327 Example : Vin 8 ADC DAC V0 10V 5V 0V 0s V(U2:OUT) 2ms V(U1:IN) 4ms 6ms Time 8ms 10ms 328 164 Power Amplifiers and Output Stages 329 IC A AB B IB=0 C VCE The instantaneous power dissipated in a BJT is equal to Pi = VBE iB + VCE iC  VCE iC The average power dissipated in a transistor may be computed mathematically by averaging the instantaneous power one complete cycle of the input signal. PT = 1 T  T 0 Pi dt = 1 T  T 0 VCE iC dt 330 165 Class A ( Single Ended ) Amplifier VCC iO = iC  iB IC RL vO RB IC,max VCC/RL VCC/2RL + → VCE,max VB VCC VCEQ vin VCE 331 vin VCC iO = iC  iB RB Vm RL vO + → vin t iB VB t iC VCC = iC RL +  CE IC IP iC = I C + I P sin  t IP = VP RL  CE = VCE − VP sin  t t vCE VCE VP t 332 166 VCC 1 T 2 ( i R )dt T 0 C L 1 T PL =  ( I C2 + 2I C I P sin  t + I P2 sin 2  t ) RL dt T 0 I2R T I2R T 1  PL = C L  dt + P L   ( 1 − cos 2 t )  dt T 0 T 0 2  PL = ( PL = I C2 RL + iO = iC  ) 2 P iB RL VO RB + → Vin VB 2 P I RL V = I C2 RL + 2 2RL { { ac power dissipated on RL dc power dissipated on RL The average power delivered to the circuit by the DC supply: Pin = 2 VCC 1 T 1 T V i dt = V I + I sin  t dt = V I = ( ) ( ) ( ) P CC C T 0 CC C T 0 CC C 2RL 333 Power Dissipated in the transistor 1 T ( i ) dt T 0 CE C 1 T =  ( (VCE − VP sin  t )( I C + I P sin  t ) ) dt T 0 1 T =  (VCE I C + VCE I P sin  t − I CVP sin  t − VP I P sin 2  t ) dt T 0 V I  1 T =   VCE I C − P P  dt T 0 2  PD = = VCE I C − VP I P V2 = VCE I C − P 2 2RL Pin = PL + PD 334 167 The efficiency of an amplifier represents the amount of AC power delivered (transferred) from the DC source; = PL,ac Pin  100 = VP2 2 RL  100 2 VCC 2 RL 2 V   =  P   100%  VCC  The circuit efficiency increasing signal to the load. Maximum undistorted output signal is VP = VCC 2 and maximum circuit efficiency is 2 V 2  =  CC   100% = 25%  VCC  335 Example: A class-A emitter follower biased with a constant-current source is given in figure. Determine the value of R that will produce the maximum possible output swing. What are the value of IQ, and the maximum and minimum values of iE1 and iL? β =200, VBE = 0.7V, and VCE(sat) = 0.2V. +15 Vin R Q3 Q1 iE1 IQ Q2 V0 iL RL=1k -15 336 168 +15 Vin R Q3 V0 (max) = 15 − 0.2 = 14.8V Q1 iE1 IQ i L (max) = V0 iL Q2 V0 (max) 14.8V = = 14.8mA RL 1k  I Q = i L (max) = 14.8mA RL=1k i E 1 (max) = I Q + i L (max) = 29.6mA i E 1 (min) = 0 i L (min) = − I Q = −14.8mA -15 R= 15 − 0.7 = 993 14.8m 337 Class A Single Ended Transformer Coupled Amplifier VCC N : 1 → iL RB iC  RL VO C + Vin 338 169 VCC DC equivalent RB VCEQ = VCC AC equivalent resistance V1 N 1 i2 = = =N V2 N 2 i1 i1 → N : 1 → i 2 V1 V2 RL' RL' = V1 i1 RL = V2 i2 RL RL' V1 i2 = = N2 RL V2 i1 N = N1 N2 RL' = N 2 RL 339  iC AC equivalent VO  iL N RL' + Vin = N 2 RL RB VCEQ = VCC ı VCC = VCC + RLı I C iC = I C + I P sin  t  CE = VCE − VP sin  t = VCC − VP sin  t VP RLı DC load line Dynamic load line IC VCC VCC’ VCE,max IP = iC IC,max IC+VCC/RL’ VCE 340 170 Vin Vm 1 T Pin =  (VCC iC ) dt T 0 1 T =  (VCC ( I C + I P sin  t ) ) dt = VCC I C T 0 1 T PL =  ( iL2 RL ) dt T 0 2 = t VCE VCE 1 T  VP  V V sin2  tRLdt = =    T 0  NRL  2N RL 2R 2 P 2 P V 2 2R'L 1 V  = L,ac  100 = P  100 =  P V Pin 2  VCC VCC CC' RL 2 P ' L VP i t C IC    100%  IP t VL if VP = VCC  max = 50% t VP/N 341 Class B Push Pull Amplifier V+ Q1 VL + Vin Q2 RL V− Vin  0, Q1 is ON and Q2 is OFF Vin  0, Q1 is OFF and Q2 is ON 342 171 Vin  0, Q1 is ON and Q2 is OFF Vin Vm V+ t Q1 i C1 → ie 1 + Vin VL iL  Vm/RL RL t vCE1 V+ Vm Vin = Vm sin  t  VL iC 1  ie 1 = i L = Vm sin  t RL t VL Vm iC 2 = 0 t 343 Vin  0, Q1 is OFF and Q2 is ON  ie 1 + Vin V VL iL  Q2 Vin Vm RL t i C2 Vm/RL − t vCE2 t iC 1 = 0 iC 2  ie 2 = − i L =− Vm sin  t RL V − Vm VL Vm t 344 172 1 T (V i + VCC iC 2 ) dt T 0 CC C 1  V 1 T  1 =  2  VCC m sin  t  dt − T 0  RL T  Pin = Pin = 2  VCC  T T 2   Vm sin  t  dt  VCC R  L  = T Vm/RL  VL2  1   dt = T  RL  PL ,ac Pin %= = t i C1 Vm RL  Vm2 sin 2  t  Vm2 dt =   0 0  RL  2RL V V2 2 PD = Pin − PL = VCC m − m  RL 2RL 1 PL = T Vin Vm T t i C2 Vm/RL t i L = iC 1 − iC 2 2RL  Vm = Vm 4 VCC V  CC RL 2 m V 2  Vm 4 VCC t  100 345 PIN PD 2 VCC  2 RL 2 CC 2V  RL VCC 2 Vm  PL  VCC VCC Vm VCC Vm  2 VCC 2 RL 4 VCC Vm 346 173 Crossover Distortion V V in + Vm Q1 t VL + Vin VL RL Q2 Vm − VBE V− −Vm + VBE t Crossover Distortion 347 Class AB Push Pull Power Amplifier Crossover distortion can be virtually eliminated by applying a small quiescent bias on each output transistor , for a zero input signal. V+ + Q1 VL VBB + Vin + VBB Q2 RL V− 348 174 Example: V+ R Q1 C Vin D1 V0 D2 Q2 RL R V− 349 Class C Power Amplifiers Class C amps are never used for audio circuits. They are commonly used in RF circuits. Class C amplifiers operate the output transistor in a state that results in tremendous distortion (it would be totally unsuitable for audio reproduction). However, the RF circuits where Class C amps are used employ filtering so that the final signal is completely acceptable. Class C amps are quite efficient. 350 175 Class D Power amplifier A class-D amplifier is one in which the output transistors are operated as switches. The “D” in class-D is sometimes said to stand for “digital.” This is not correct because the operation of the class-D amplifier is based on analog principles. 351 The network consisting of R1 and C2 compensates for the inductive impedance of the loudspeaker voice coil so that the filter sees a resistive load at high frequencies. The passive filter consisting of L1 and C1 passes the average or lowfrequency value of v’0 to the loudspeaker load and rejects the higher- frequency harmonics of the switching waveform. A class D amplifier is an efficient form of switching amplifier. It can be up to 90% power efficient. 352 176 Vin Example: Sketch the VO and VL. Find the %η. V + = 15V Vin + − 0.1 sin  t VL 10 Q1 VO + VL Q2 R1 RL 10 V − = −15V 99k R2 0.1 V0 10.7 1k +0.7 -0.7 -10.7 353 Vin  0, VO  0 Q1 is ON and Q2 is OFF VL R + R2 R2 = Vin  VL = 1 Vin = 100Vin R1 + R2 R2 VO = 0.7 + VL Vin 0.1 VL 10 Vin  0, VO  0 Q1 is OFF and Q2 is ON  VL R  R2 = Vin  VL =  1 + 1  Vin = 100Vin R1 + R2 R2   VO = −0.7 + VL , Vm = 0.1  100 = 10V PL = Vm2 102 = = 5W 2 RL 2  10 V 2 10 Pin = VCC m = 15 = 9.55W  RL  10 2 PO = Pin − PL = 9.55W − 5W = 4.55W %= 5W  100 = 52% 9.55W V0 10.7 +0.7 -0.7 -10.7 354 177 Thermal Runaway Thermal runaway refers to a situation where an increase in temperature changes the conditions in a way that causes a further increase in temperature leading to a destructive result. ◼ The maximum average power which a transistor can dissipate depends upon the transistor construction and may lie in the range from a few miliwatts to several hundred watts. The maximum power is limited by the temperature that the collector to base junction can withstand. ◼ The junction temperature may rise either because the ambient temperature rises or because of self heating. ◼ It is found experimentally that the steady state temperature rise at collector junction is proportional to the power dissipated at the junction, or TJ − TA =  PD 355 TJ − TA =  PD TJ = junction temperature in ºC TA = ambient temperature in ºC PD = power dissipation in watts θ = thermal resistance ºC/watt ambient case heat sink junction 356 178 Collector to base junction Ambient J C θJC A θCA Case  JA =  JC +  CA PD = TJ − TA  JA = TJ − TA  JC +  CA θJC is determined by the manufacture of transistor. θCA is determined by the surface of case if the surface area is increased, θCA would be decreased. This can be achieved by use of heat sink. 357 IC J θJC θCA C PD θHSA A VCE  JA =  JC + CA //  HSA PC 1  TJ  is the condition which must be satisfied to prevent thermal runaway. PC = ICVCB  ICVCE 358 179 Example: Determine the power dissipation capability  HSA = 10C / W ,  CA = 93C / W ,  JC = 7C / W TA = 50C , TJ = 200C Solution With heat sink  JA =  JC + CA //  HSA = 7 + 93 // 10 = 16 0C / W PD = TJ − TA  JA = 200 − 50 = 9.4W 16 Without heat sink  JA =  JC +  CA = 7 + 93 = 100 0C PD = TJ − TA  JA = 200 − 50 1.5W 100 359 Feedback and Stability 360 180 The small-signal voltage gain and other characteristics of discrete BJT and MOSFET transistor circuit amplifiers are functions of the bipolar current gain and the MOSFET conduction parameter. In general, these transistor parameters vary with temperature and they have a range of values for a given type of transistor group, because of processing and material property tolerances. This means that the Q-point, voltage gain, and other circuit parameters can vary from one circuit to another, and can be functions of temperature. Transistor circuit characteristics can be made essentially independent of the individual transistor parameters by using feedback. The feedback process takes a portion of the output signal and returns it to the input to become part of the input excitation. 361 Feedback Amplifiers Feedback is used in virtually all amplifier systems. In a feedback system, a signal that is proportional to the output is fed back to the input and combined with the input signal to produce a desired system response. Feedback can be either negative (degenerative) or positive (regenerative). In negative feedback, a portion of the output signal is subtracted from the input signal; in positive feedback, a portion of the signal is added to the input signal. Positive feedback is used to in the design of oscillators and in a number of other applications. 362 181 In amplifier design, negative feedback is applied to effect one or more of the following properties: ➢ Gain sensitivity : It makes the closed-loop gain less sensitive to variations that occur in the open-loop gain of the amplifier. ➢ Reduce the nonlinear distortion ➢ Noise Sensitivity : Reduce the effect of noise ➢ Control of the input and output impedances. ➢ Extend the bandwidth of the amplifier Disadvantages ➢ Circuit gain ➢ Stability: there is possibility that the feedback circuit may become unstable (oscillate) at high frequencies. 363 Closed-Loop (Feedback) Amplifier Source Si + Σ Se − Sfb AOL SO Load β Basic configuration of a feedback amplifier 364 182 Ideal closed loop gain Source Si + S fb =  SO Σ Se − Se = Si − S fb = Si −  SO Sfb AOL SO Load β SO = AOL Se = AOL ( Si −  SO ) SO ( 1 + AOL  ) = AOL Si SO AOL A = ACL = = OL Si 1 + AOL  1 + T T = AOL  T is called loop gain ACL  AOL positive feedback ACL  AOL negative feedback 365 For negative feedback, we assume T to be a positive real function. The gain will be negative ( 180 degree phase difference between input and output signals) in some cases which means that the transfer function β will also be negative quantity for a negative feedback circuit. T = AOL  = S fb Se Normally, the error signal is small, so the expected loop gain is large. If the loop gain is large so that βAOL>> 1, then ACL = AOL A 1  OL = 1 +  AOL  AOL  and the gain or transfer function of the feedback amplifier essentially becomes a function of the feedback network only. 366 183 The feedback circuit is usually composed of passive elements, which means that the feedback amplifier gain is almost completely independent of the basic amplifier properties, including individual transistor parameters. Since the feedback amplifier gain is a function of the feedback elements only, the closed loop gain can be designed to be a given value. The individual transistor parameters may vary widely, and may depend on temperature and frequency, but the feedback amplifier gain is constant. The net results of negative feedback is stability in the amplifier characteristics. 367 Assuming a large loop gain, the output signal becomes SO = ACL S i = AOL 1 Si  Si 1 +  AOL  Error signal Se S S e = S i −  SO  S i −   i   =0  with a large loop gain, the error signal decreases to almost zero. 368 184 Gain Sensitivity If the feedback transfer function β is constant, then taking the derivative of ACL with respect to AOL dACL = dAOL ( 1 +  AOL ) 2 Dividing both sides by the closed loop gain yields dACL dAOL ( 1 +  AOL ) dAOL  ACL  dAOL 1 = = =  ACL AOL ( 1 +  AOL ) 1 +  AOL AOL  AOL  AOL 2 Equation shows that the percent change in the closed loop gain ACL is less than the corresponding percent change in the open-loop gain AOL by the factor (1 + βA). The change in the open-loop gain may result from variations in individual transistor parameters in the basic amplifier. 369 Example: AOL =106 and ACL = 100. If the magnitude of AOL decreases by 20 percent, what is the corresponding percent change in ACL? dAOL = 0.2  10 6 = 2  10 5 dACL  ACL  dAOL  100  2  10 5 = = = 2  10 −5 = 0.002%   ACL  AOL  AOL  10 6  10 6 370 185 Bandwidth Extension The amplifier bandwidth is a function of feedback. Assume the frequency response of the basic amplifier can be characterized by a single pole. We can write AOL ( s ) = AO 1+ s H Where AO is the low-frequency or midband gain, and ωH is the upper 3dB or corner frequency. The closed-loop gain of the feedback amplifier can be expressed ACL ( s ) = AOL ( s ) AO = 1 +  AOL ( s ) ( 1 +  AO ) 1 + 1 s  H ( 1 +  AO ) 371 |ACL| AO Open loop closed loop The gain-bandwidth product of a feedback amplifier is constant (=AOωH) AO /(1+βAO) ωH ωH(1+βAO) ω(rad/s) Example: Determine the bandwidth of a feedback amplifier. AOL =104, ACL(0) = 50 and open loop bandwidth =2π(100) rad/s. ACL ( 0 ) = AO 10 4 = 50 =  1 +  AO = 200 1 +  AO ( 1 +  AO ) Closed-loop bandwidth is CLH =  H ( 1 +  AO ) = 2 ( 100 )( 200 ) = 2 ( 20  10 3 ) The bandwidth increases from 100Hz to 20kHz as the gain decreases from 104 to 50. 372 186 Noise Sensitivity In any electronic system, unwanted random and extraneous signals may be present in addition to the desired signal. These random signals are called noise. Electronic noise can be generated within an amplifier, or may enter the amplifier along with the input signal. Negative feedback may reduce the noise level in amplifiers; More accurately, it may increase the signal-tonoise ratio. More precisely, feedback can help reduce the effect of noise generated in an amplifier, but it cannot reduce the effect when the noise is part of the input signal. 373 The input signal-to-noise ratio is defined as ( SNR ) i = Si v = i N i vn The output signal-to-noise ratio is defined as ( SNR )O = SO A S = Ti i N O ATn N i A large signal-to-noise ratio allows the signal to be detected without any loss of information. This is a desirable characteristic. 374 187 Example: vn + + − vi ve A1=103 + + A2=10 vO β=0.01 v fb =  vO ve = vi − v fb = vi −  vO vO = A1 A2 ve + A2 vn = A1 A2 ( vi −  vO ) + A2 v n vO = A1 A2 vi A2 vn + 1 + A1 A2  1 + A1 A2  vO  100vi + 0.1vn ( SNR )O = SO 100vi S = = 1000 i N O 0.1vn Ni 375 Reduction of Nonlinear Distortion Distortion in an output signal is caused by a change in the basic amplifier gain or a change in the slope of the basic amplifier function. The change in gain is a function of the nonlinear properties of bipolar and MOS transistors used in the basic amplifier. SO2 A3=250 A2=500 SO1 Open loop characteristic of basic amplifier A1=1000 Si2 Si1 A3=9.71 SO2 A2=9.9 SO1 β =0.099 A1=10 Si1 Closed loop characteristic of basic amplifier Si2 376 188 Amplifiers Voltage Amp. TransresistanceTransconductance Amp. Amp. Current Amp. 377 Voltage Amplifier RO + for ideal voltage amp Ri =  + + Ri Vi AvVi VO − − RO = 0 Current Amplifier + Vi − ii Ri iO Aiii + RO VO − for ideal current amp. Ri = 0 RO =  378 189 Transresistance Amplifier + RO ii for ideal transresistance amp Ri = 0 + + Vi Ri Azii VO − RO = 0 − Transconductance Amplifier + Vi ii Ri iO AgVi − + RO VO − for ideal transconductance amp Ri =  RO =  379 There are four basic feedback topologies. The types of connections are referred to as : series-shunt, shunt-series, series-series, and shunt-shunt. The first term refers to the connection at the amplifier input, and the second term refers to the connection at the output. Series-Shunt Shunt-Series Feedback Topologies Series-Series Shunt-Shunt 380 190 1) Series-Shunt Feedback Amplifier RS + + Vi Av VO − RL  2) Shunt - Series Feedback Amplifier iO ii Ai RS RL  381 3) Series - Series Feedback Amplifier RS iO + Ag Vi RL  4) Shunt - Shunt Feedback Amplifier + ii RS Az VO − RL  382 191 Ideal Series-Shunt Feedback Amplifier Rif Rof + + Iif + Ve Ri Vi RO + AvVe − + Vfb − + VO − V fb =  VO + VO − βVO Ve = Vi − V fb = Vi −  VO VO = AV Ve = AV (Vi −  VO ) VO ( 1 + AV  ) = AVVi VO AV = ACL = Vi 1 + AV  383 Rif Rof + + Vi Iif + RO + Ve Ri AvVe − + Vfb − + βVO VO − + VO − The input resistance increases with a series input connection. A large input resistance is a desirable property of a voltage amplifier. This Vi = Ve + V fb = Ve +  VO = Ve +  ( AVVe ) eliminates loading effects Vi = Ve ( 1 +  AV ) = Ri I if ( 1 +  AV ) on the input signal source Vi = Rif = Ri ( 1 +  AV ) I if due to the amplifier. 384 192 Rof + RO + Ve Ri IX + AvVe − VX The + + Vfb − βVO output decreases + VO resistance with a shunt output connection. A small − output resistance is a of a IX = VX − AV Ve VX − AV ( −  VX ) = RO RO desirable property voltage amplifier. IX = VX + AV  VX RO eliminates loading effects RO VX = Rof = IX ( 1 +  AV ) an output load is connected. This on the output signal when 385 Example: Determine the input and output resistances. AV =105, ACL = 50, Ri = 10kΩ and RO = 20kΩ. Rif Rof + + ACL = 50 = AV 1 + AV  Vi 10 5  1 + AV  = 2  10 3 1 + AV  Iif + RO + Ve Ri − + Vfb − VO AvVe + βVO − + VO − Rif = Ri ( 1 +  AV ) = 10k  ( 2  10 3 ) = 20M  Rof = RO 20k  = = 10  ( 1 +  AV ) 2  10 3 386 193 Example: Determine closed-loop gain, the input and output resistances. AOL =106, Ri = 2MΩ and RO = 100Ω. Rif + Ve − − + Vi + Vfb R2 − 0.2k ( Rof + Without feedback V fb = 0 ) VO  AOL (V+ − V− ) VO VO = AOLVe = AOLVi R1 = 1.8k VO = AOL = 10 6 Vi 387 With feedback V fb =  VO = Rif + Rof + Ve − − + Vi + Vfb R2 − 0.2k VO R2 VO R1 + R2 0.2 VO = 0.1VO 1.8 + 0.2 VO  AOL (V+ − V− ) = AOLVe = Vi = Ve + V fb  Ve = Vi − V fb R1 = 1.8k VO = AOL (Vi −  VO ) VO ( 1 +  AOL ) = AOLVi VO AOL 10 6 = = Vi 1 +  AOL 1 + 0.1  10 6 10 = ACL or VO 1 1  = = 10 Vi  0.1 388 194 Rif + Rof + Ve − − + Vi + R2 Vfb − 0.2k VO R1 = 1.8k Rif = Ri ( 1 +  AOL ) Rif = 2M  ( 1 + 0.1  10 6 )  2  10 11  Rof = RO 100  =  1  10 −3  6 1 +  A 1 + 0 . 1  10 ( OL ) 389 Example: • What is the feedback topology of this circuit? • Find the feedback transfer function (β). • Find ACL . 10V Vin + A − VO R1 1kΩ R2 10kΩ 0.2mA 390 195 Ideal Shunt - Series Feedback Amplifier Rif Rof ie If the output is essentially a + Vi Ri ii RO Aiie − iO short circuit, then the output current is iO = Ai ie iif βiiO and the feedback current is i fb =  i iO The input signal current is ii = ie + i fb  ie = ii −  i iO iO = Ai ie = Ai ( ii −  i iO )  iO Ai = Aif = ii 1 +  i Ai 391 Rif Rof ie + ii Vi Ri − Aiie RO iO iif βiiO Vi = Ri ie ii = ie + i fb = ie +  i iO = ie +  i ( Ai ie ) = ie ( 1 +  i Ai ) Vi Ri = Rif = ii ( 1 +  i Ai ) The input resistance decreases with a shunt input connection. A small input resistance is a desirable property of a current amplifier. This eliminates loading effects on the input signal current source due to the amplifier. 392 196 Rof ie + Ri Aiie RO VX − Series IX output increases iif connection the output resistance compared to that βiiO of the basic amplifier. A large output resistance is a I X = Ai ie + desirable VX V = Ai ( −  i I X ) + X RO RO property of a current amplifier, to avoid loading effects on the output VX IX = RO ( 1 + Ai  i ) signal due to the load connected to the amplifier VX = Rof = RO ( 1 + Ai  i ) IX output. 393 Example: Determine the input and output resistances. Ai =105, Aif = 50, Ri = 10kΩ and RO = 20kΩ. Rif Rof ie + Aif = 50 = Rif = Ai ii 1 +  i Ai Vi Ri − 10  1 +  i Ai = 2  10 3 1 +  i Ai ( 1 +  i Ai ) iO RO iif 5 Ri Aiie = βiiO 10k  = 5 2  10 3 Rof = RO ( 1 + Ai  i ) = 20k 2  10 3 = 40M  394 197 Example: Determine open- and closed-loop gain. iin is + gm R without feedback i0 io = gm ( Riin − 0 ) = gm Ri s − io = gm R = AiOL is R1 i f =  i0 R2 with feedback i0 = gm R2 ( i0 + i f )  i f = ( 1 − gm R2 i =  i0 gm R2 0 ) i0 = gm Riin = gm R i S − i f = gm R ( i S −  i0 ) i0 gm R = = AiCL i S 1 +  gm R Closed loop gain Example: Determine open- and closed-loop gain. iin is R 100k + gm i0 − gm = 50  A V without feedback io = gm ( Riin − 0 ) = gm Ri s R1 16k i f =  i0 395 io = 50  A V  100k  is AiOL = 5 A A R2 16k with feedback i0 = gm R2 ( i0 + i f )  i f = ( 1 − gm R2 i =  i0 = 0.25i0 gm R2 0 ) i0 = gm Riin = gm R i S − i f = gm R ( i S −  i0 ) i0 gm R 5 = = = 2.22 A A = AiCL i S 1 +  gm R 1 + 0.25  5 396 198 Homework: • What is the feedback topology of this circuit? • Find the feedback transfer function (β). • Find the closed-loop gain • Find input resistance (excluding RS). • Find output resistance (excluding RL). AOL = 104 V+ − Ri = 100k  Ro = 1k  RS is i0 + V− RS = RL = 10k  R = 100 RL RF R RF = 1k  397 Ideal Series-Series Feedback Amplifier Vi = Ve + V fb  Ve = Vi −  z iO Rif + Vi Iif iO = AgVe = Ag (Vi −  z iO ) Rof + Ve Ri AgVe − + Vfb  z iO − + RO iO Ag iO = Agf = Vi 1 +  z Ag ( Rif = Ri 1 + Ag  z ( ) Rof = RO 1 + Ag  z ) 398 199 Example: Determine open- and closed-loop gain. + Vi + Ve + gm iO −− V fb =  z iO = RF iO RL + Vfb RF − -Without feedback + Vi + Ve + iO = gm (V p − Vn ) = gm (Ve ) iO gm iO = gmVi −− RL iO = Ag = gm Vi 399 -With feedback + + Ve Vi + gm iO −− RL + Vfb − RF Vi = Ve + V fb = Ve + RF iO  Ve = Vi − RF iO ( ) iO = gm V p − Vn = gmVe = gm (Vi − RF iO ) iO ( 1 + gm RF ) = gmVi iO gm = Agf = Vi 1 + gm RF Closed loop gain 400 200 Example: Determine open- and closed-loop gain. gm= 50µA/V, RL = 10k, RF = 10k. + + + Vi iO gm Ve −− RL + Vfb − Open loop gain Ag = gm = 50 RF A V Closed loop gain Agf = gm 50  A V = = 33.33  A V 1 + gm RF 1 + 50  A V  10k  401 Ideal Shunt - Shunt Feedback Amplifier ii = ie + i fb  ie = ii −  gVO Rif + ii Vi Ri − RO AZie + ( Rof VO = Az ie = Az ii −  gVO + Az VO = Azf = ii 1 +  g Az ie VO − ) iif βgVO + VO − Rif = Ri (1 +  A ) g Rof = z RO (1 +  A ) g z 402 201 Example: Determine open- and closed-loop gain. i fb → ie → − V0 + ii ie → R0 ie → − Ve RF Ri − + + AOLVe Ve VO − + Ri + R0 +A R i OL i e = Az ie Az = AOL Ri + VO − 403 -Without feedback ie → − + ii R0 ie → + + Ri V0 Az ie VO − VO = − Az ie = − Az ii VO = − Az = − AOL Ri ii 404 202 -With feedback VO = − Az ie i f → RF i i = ie + i f iin → − + Az ie VO Ve Ri ii + + g = − −1 RF VO − Az ie = ii ie + i f if = −Vi − VO −VO  =  gVO Rf Rf − Az ie − Az ie − Az ie VO = = = ii ie +  gV0 ie +  g ( − Az ie ) ie −  g Az ie VO 1 = = − RF ii g  g Az ? 1 405 Effect of feedback connection on input and output impedance. Series Shunt Z if Z of Z i (1 +  A)  Zo  1+  A Series Series Z i (1 +  A)  Zo (1 +  A)  Shunt shunt Zi  1+  A Zo  1+  A Shunt Series Zi  1+  A Zo (1 +  A)  406 203 Stability of the Feedback Circuit In negative feedback, a portion of the output signal is subtracted from the input signal to produce the error signal. However, this subtraction property, or the loop gain, may change as a function of frequency. At some frequencies, the subtraction may actually be addition; that is, the negative feedback may become positive, producing an unstable system. The Stability Problem The ideal closed-loop transfer function of the basic feedback configuration is Af = A 1+  A 407 The open-loop gain is a function of the individual transistor parameters and capacitances, and is therefore a function of frequency. The closedloop gain can then be written as Af ( s ) = A( s) 1 +  A( s) or A f ( j ) = A ( j ) A ( j ) = 1 +  A ( j ) 1 + T ( j ) where T(jω) is the loop gain. The loop gain can be represented by its amplitude and phase, as follows: T ( j ) = T ( j )  408 204 The stability of the feedback circuit is a function of the loop gain T(jω). If the loop gain magnitude is unity when the phase is 180 degrees, then T(jω) = -1 and the closed-loop gain goes to infinity. This implies that an output will exist for a zero input, which means that the circuit will oscillate. If we are trying to build a linear amplifier, an oscillator is considered an unstable circuit. If |T(jω)| < 1 when the phase is 180 degrees, the system is stable, whereas if |T(jω)| ≥ 1 when the phase is 180 degrees, the system is unstable. 409 Bode Plots: One-, Two-, and Three-Pole Amplifiers Single stage amplifier VO ii RB hie C hfeib RC RL Ai dB Aio Ai = Ai = Aio  f  1+ j   f1   f  − tan −1   2  f1   f  1+    f1  Aio -20dB/dec f f1 phase f1 f -45 -90 where Aio is midband gain, and f1 is the upper 3dB frequency. 410 205 Ai Two stage amplifier dB Aio hie1 ii Ai = hfeib C1 RL1 hfeib C2 hie2 -40dB/dec RL2 phase Aio  f  f  1+ j f 1+ j f  1  2   Ai = Aio  f  1+   f1  1 f1 = 2 hie 1C1 2 -20dB/dec f1 f2 f1 f2 f f -45 -90 -135 -180  f   f  − tan −1   − tan −1    f1   f2   f  1+   f2  At high frequencies, the output current 2 becomes 180 degrees out of phase 1 f2 = 2 ( hie 2 P RL1 ) C 2 with respect to the input current. 411 Three stage amplifier Diff-amp An Gain stage Output stage op-amp is a three stage amplifier. Since each stage has an equivalent input resistance and capacitance. A dB Ao A= -20dB/dec -40dB/dec -60dB/dec phase -45 -90 -135 -180 -225 -270 f1 f2 f3 f1 f2 f3 Ao  f  f  f   1+ j  1+ j 1+ j  f1   f2   f3   Where AO is low frequency gain f f factor. Assuming the poles are far apart (let f1 << f2 << f3). At very high frequencies, the phase difference between the output and input signal is -270 degrees. 412 206 For a three-stage amplifier, the loop gain is therefore T( f )=  Ao    f f  f   1+ j  1+ j 1+ j  f1   f2   f3   Both the magnitude and phase of the loop gain are function of frequency. For the three-stage amplifier, the phase will be -180 degrees at same particular frequency, which means that the amplifier may become unstable. 413 Nyquist Stability Criterion Several methods can be used to determine whether a system is stable or unstable. Nyquist stability criterion method not only determines if a system is stable, it also indicates the degree of system stability. The Nyquist diagram is a plot of the real and imaginary components of T(jω) as the frequency ω varies from minus infinity to plus infinity. Although negative frequencies have no physical meaning, they are not mathematically excluded in the loop gain function. The polar plot of for the negative frequencies is the complex conjugate of the polar plot for positive frequencies. 414 207 The loop gain for a two-pole amplifier is  Ao T ( j ) =       1+ j  1+ j     1  2      − tan −1   − tan −1     1  2    1+    2   Ao T ( j ) =   1+    1  2 2 where ω1 and ω2 are the upper 3 dB radian frequencies of the first and second stage, respectively. As Imag. T(jω) ω +∞, approaches the +90 magnitude approaches zero and the +180 -180 -Φ ω=+∞ |T(jω)| ω=0+ approaches -180 degrees. Real T(jω) + ω→ -90 phase 0 415 The loop gain for a three-pole amplifier is  Ao T ( j ) =          1+ j  1+ j 1+ j     1  2  3  T ( j ) =  Ao   1+    1  2   1+    2  2    − tan −1   − tan −1    1  2   1+    3  Imag. T(jω) 2  −1     − tan     3  Imag. T(jω) unstable system stable system ω=0+ Real T(jω) -1,0 ω +∞ß -1,0 ω=0+ Real T(jω) ω +∞ß If the Nyquist plot encircles or goes through the point (-1,0), the amplifier is unstable. (|T(jω)| ≥ 1 at the frequency at which the phase is -180 degrees, then the amplifier is unstable.) 416 208 Example: Determine the stability of a three-pole feedback amplifier with a loop gain given by T( f )=  ( 100 ) f   1+ j 5  10   3 In this case, the three poles all occur at the same frequency. Determine the stability of the amplifier for β =0.2 and β =0.02. 417 Solution: the loop gain can be written in terms of its magnitude and phase, T ( j ) =  f  = −3 tan −1  5  10  ( 100 )      f  −3 tan −1  5   10   f   1+  5    10   2   = −180  3 which yields f180 = 1.73 x 105 Hz. The magnitude of the loop gain at this frequency for β = 0.2, is then 0.2  100 = 2.5 8 for β = 0.02, the magnitude is T ( f 180 ) = T ( f 180 ) = 0.02  100 = 0.25 8 The system is unstable for β = 0.2 and stable for β = 0.02. 418 209 A dB Phase and Gain Margin Ao At the frequency at which the loop gain Gain margin magnitude is unity, if the magnitude of the phase is less than 180 degrees, the system is stable. The difference f phase f (magnitude) between the phase angle at this frequency phase margin -180 and 180 degrees called the phase margin. The loop gain can change due, for example, to temperature variations, and the phase margin indicates how much the loop gain can increase and still maintain stability. A typical desired phase margin is in the range of 45 to 60 degrees. A second term that describes the degree of stability is the gain margin. This value gives an indication of how much the loop gain can increase and still main stability. 419 Example: 420 210 Frequency Compensation The general technique of making a feedback system stable is called frequency compensation. One basic method of frequency compensation involves a introducing a new pole in the loop gain function, at a sufficiently low frequency that |T(f)| = 1 occurs when |Φ| < 180°. A dB A new pole fPD is introduced at a low frequency and since it dominates the Ao 1 f frequency response, it is called a dominant pole. In this situation, the f1 fPD f2 f3 phase magnitude of the loop gain becomes -90 unity when the phase |Φ| < 180°, and -180 f -270 the system is stable. 421 This fourth pole can be introduced by adding a fourth stage with an extremely large input capacitance. Though not practical, this method demonstrates the basic idea of stabilizing a circuit. Instead of adding a fourth dominant pole to achieve a stable system, we can move pole f1, to a low frequency. This can be done by increasing the effective input capacitance to the gain stage. The second inverting stage, amplifier, has an CF a feedback capacitor connected V1 V2 Diff-amp stage -A Output stage VO between the output and input. This capacitor CF is called a compensation capacitor. The effective input Miller capacitance is CM = CF(1+A) 422 211 Electronic DC Power Supplies 423 Electronic Linear DC Power Supplies Transformer Rectifier Filter Voltage Regulator Rectifiers H.W.R N :1 + Vm sin  t − + RL V O T 2 VO ,dc Vin Vm − T V 1 1 =  Vm sin  tdt +  0dt = m T 0 TT  VO 2 T VO ,rms = V 1 2 v (t )dt = m  T 0 2 424 212 F.W.R + + Vm sin  t RL V O Vm − − + Vm sin  t Center tapped Vin − VL + Vm sin  t bridge − + RL T 2 VL,dc VO − T 2V 1 1 =  Vm sin  tdt −  Vm sin  tdt = m T 0 TT  2 T VL,rms = V 1 2 v (t )dt = m  T 0 2 425 Capacitor Filters + D1 Vin C RL VL Vm − D2 Vm Vdc = 1 1+ 4 fRLC VL for FWR ripple factor, r r= rms of ac component of VO dc value of VO r= 1 2 12 fCRL for FWR 426 213 Dual Complementary FWR Vin Vm +− −+ +− −+ D1 D2 + D4 D3 RL V L1 RL VL 2 VL1 − + VL2 − 427 Voltage Regulators A voltage regulator is a circuit or device that provides a constant voltage to a load. The output voltage is controlled by the internal circuitry and relatively independent of the load current supplied by the regulator. Vin (Unregulated input) Control Element Comparator Circuit V0 (Regulated output) Sampling Circuit Referance Voltage 428 214 Since the regulator output voltage is derived from the reference voltage, any variation in that voltage, as the power supply voltage Vin changes, also affect the output voltage. Line regulation is defined as the ratio of the change in output voltage to a given change in the input supply voltage, or line regulation = VO Vin The ideal voltage regulator is equivalent to an ideal voltage source in that the output voltage is independent of the output current and any output load impedance. In actual voltage regulation, however, the output voltage is slight function of output current. This defence is related to the output resistance of the regulator. The output resistance is defined as the rate of change of output voltage with output current, or RO = − VO I O 429 Load regulation is defined as the change in output voltage between a noload current condition and a full-load current condition. Load regulation can expressed as a percentage, or Load regulation = VO ( NL ) − VO ( FL )  100 % VO ( NL ) Example: The output voltage of a power supply is 15V when the load current is zero. When the load current is 250mA, its output voltage decreases to 14.7V. Compute its output resistance and its percent of load regulation. RO = − LR = VO ( 15 − 14.7 )V =− = 1.2 I O ( 0 − 250mA) 15 − 14.7  100 = 2 % 15 The ideal power supply would have a % LR of 0 % 430 215 Simple Series Regulator Vin unregulated input R IB  IR → + − V VO  IL regulated BE RL output  IZ + VZ − Vin R Vin VO = VZ − VBE IR = IZ + IB VO RL 431 Example: Estimate the dc and ripple voltage across the load. f = 50 Hz,  = 100,V = 0V VZ = 5.7V , rZ = 10 I→ N :1 + Vin 1k C − + − V BE  IL VO RL 50 VO ,dc = VZ − VBE = 5 − 0.7 = 5V IL = VO ,dc RL = 5V = 100mA 50  I  I L = 0.1A 432 216 I→ N :1 Vrpp Vrpp ViDC Vrpp Vrpp I T + I = dc 2 = Vin input C f C − 0.1A = = 1V input 50  2000  A Vrpp = Vm − = 10 − 0.5 = 9.5V 2 rZ 10 = Vrpp input =  1 = 9.9mV B rZ + R 10 + 1k ; Vrpp at load at B C 1k − + VBE  IL VO RL 50 = 9.9mV Pin  ViDC  I = 9.5V  0.1A = 0.95W PL = VO ,dc  I L = 5V  0.1A = 0.5W = PL 0.5W  100 0 0 = Pin 0.95W 0 0 = 52.6 0 0 433 Op-Amp Series Regulator Vin VO R VZ = + − VZ R1 VO R2 R1 + R2  R  VO = VZ  1 + 1  R2   R2 H.W: Vrpp at output =? 434 217 Example: Find the range of output voltage. VO Vin RL 1k + − 5V 20k 10k  VO R  R1   R2 = VZ  VO = VZ  1 + 1  = 5  1 +  R1 + R2 R2  10k     R1 = 0  VO = 5V R2 = 20k  VO = 15V 5  VO  15V 435 Current Limiting Circuit Vin VO Rsc Q1 RL 1k + Q2 − 5V R1 R2 Q2 and RSC provide short circuit protection I SC = 0.6 RSC I L , VBE2 , I C2 , I B1 , I E1 , I L  436 218 Example: Regulated power supply Q1 30V VO1 500 + Q2 − 5V VO iO 1 →  IL 10V 1k 1k 1 = 20, 10 RL 2k  2 = 100 Find VO , VO1 and iO1 . Determine the power dissipated in Q1 and Q2 437 Q1 30V a) VO  1k = 5V  VO = 15V 1k + 2k V 15V IL = O = = 1.5 A RL 10  I C 1 = I L = 1.5 A IC 2 = IC 1 1 = iO 1 = I B 2 = VO1 500 + 5V Q2 −  IL 10V 1k 1k VO iO 1 → 2k RL 10 1.5 A = 75mA 20 I C2 2 = 75mA = 0.75mA 100 VO 1 = 500  0.75mA + 0.7 + 10V = 11.075V b) VEC 1 = 30 − VO = 15V P1 = VEC 1 I C 1 = 15  1.5 = 22.5W VCE 2 = 30 − 0.7 − 10 = 19.3V P2 = 19.3V  75mA = 1.4475W 438 219 I.C. Voltage Regulators Vin (Unregulated input) IN V0 (Regulated output) OUT GND Positive Voltage Regulators in 78XX IC Part 7805 7806 7808 7810 7812 7815 7818 7824 Output Voltage (V) +5 +6 +8 +10 +12 +15 +18 +24 Minimum Vin(V) 7.3 8.3 10.5 12.5 14.6 17.7 21.0 27.1 439 78xx IN V0 OUT GND C1 C2 RL Negative Voltage Regulators in 79XX IC Part 7905 7906 7908 7910 7912 7915 7918 7924 Output Voltage (V) -5 -6 -8 -10 -12 -15 -18 -24 440 220 µA7812C electrical characteristics Maximum input voltage 40V. Parameter Min. Typ. Max. Units Output Voltage 11.5 12 12.5 V Ripple rejection 55 71 dB 0.018 Ω 2 V 350 mA Output resistance Dropout voltage Short-circuit O/P current % load regulation 1 441 Ripple Rejection, RR(dB) RR (dB ) = 20 log Vrin ( rms ) Vrout ( rms ) Ripple specification called Ripple (R) R = RR (dB ) + 20log VL 442 221 V0 = I1 R1 + ( I ADJ + I1 ) R2 Adjustable Voltage Regulators Voltage regulators are = ( R1 + R2 ) I1 + R2 I ADJ also available in circuit configurations I1 = that allow the user to set the output voltage to a desired V0 = ( R1 + R2 ) regulated value. LM317 Vin IN OUT IADJ VREF − R1 I1 VREF + R2 I ADJ R1  R  V0 =  1 + 2  VREF + R2 I ADJ R1   V0 + ADJ VREF R1 with typical IC values of VREF = 1.25V and I ADJ (max) = 100 A R2  R  1.25  1 + 2  R1   V0 443 (1.25V to 37V) Ex: Find the dc and ripple voltage across the load.(f=50Hz) LM317: RR=60dB IADJ=100µA VREF=1.25V LM317 IN OUT ADJ 1000uF 2000   V0 = VREF  1 +  + I ADJ  2000 = 13.95V 200   V 13.95V IL = 0 = = 0.279 A RL 50 V0 200 RL 50Ω 2000 Vrpp dV I 0.279 =C  Vrpp = = = 2.79V dt T 2 2 fC 2  50  1000  F Vrpp (in) V (rms ) 2.79 RR = 20 log rin = 20 log = 20 log = 60dB Vro (rms ) Vrpp (out ) Vrpp (out ) i=C 2.79 = 103  Vrpp (out ) = 2.79mV Vrpp (out ) 444 222 445 Switching Regulators The switching regulator is increasing popularity because it offers the advantages of higher power conversion efficiency and increased design flexibility (multiple output voltages of different polarities can be generated from a single input voltage). The operating principles of the four most commonly used switching converter types: Buck : used the reduce a DC voltage to a lower DC voltage. Boost : provides an output voltage that is higher than the input. Buck-Boost: an output voltage is generated opposite in polarity to the input. Flyback : an output voltage that is less than or greater than the input can be generated, as well as multiple outputs. 446 223 Comparison of the typical characteristics of linear and switching regulators Parameters Linear power supply Switching regulator supply 30 – 50 60 – 85 Power out / Volume of the supply (W / cm3) 0.03 0.12 Load and Line regulation(%) 0.1 0.2 Output ripple (mV) 2 50 Noise (mV) - 50 - 200 Efficiency (%) 447 ◼ Forward mode converter (Buck or step down converter) A higher dc voltage is converted to a lower dc voltage. Iin Switch IL L1 Q Vin PWM Control IL Iin Switch on Vin D1 V0 VA I0 C0 D1 IL Iin V0 RL Switch off Vin 448 224 ~VIN Iin VA Switch IL L1 Q ~0 I + L I %40I0 − L iL inductor current Vin PWM Control V0 VA D1 I0 C0 RL I0 equivalent dc load current TON TOFF VLT di VL = L  i L dt L Neglecting VCE ( sat ) and VD (on) i L+ = Vin − V0 tON L1 i L+ = i L− = V0 = Vin i L− = V0 t L1 OFF Vin − V0 V tON tON = 0 tOFF  V0 = Vin L1 L1 tON + tOFF tON T where i IN ( DC ) = I O ( DC ) tON : duty cycle T tON T 449 As Q only conducts during tON. PIN = I 0 ( DC ) V0 I 0 t V ( sat )tON + VD1tOFF I 0 ON Vin + CE I0 T T V0 = tON V ( sat )tON + VD1tOFF V + CE T in T max = max tON V ( sat )tON + VD1tOFF Vin + CE I0 T T P0 = PIN 450 225 Calculating Inductor L1 The current following through L1 is equal to the nominal DC load current plus some ΔIL which is due to the changing voltage across it. A good rule of thumb is to set ΔILpp ≈ 40% x I0. tON = i L+  L1 Vin − V0 tON + tOFF tOFF = i L−  L1 V0 i L+  L1 i L−  L1 =T = + Vin − V0 V0 1 0.4 I 0 L1 0.4 I 0 L1 = + f Vin − V0 V0 L1 = 2.5V0 (Vin − V0 ) I 0Vin f 451 Calculating output filter capacitor C0 It can be seen that current will be flowing into C0 for the second half of tON through the first half of tOFF , or a time The current flowing for this time is tON tOFF + . 2 2 I L . 4 1 I L  tON tOFF  I L  tON + tOFF    + =  C0 4  2 2  4C0  2  V ( T − tON ) V iL = 0 and tON = 0 T L1 Vin VOpp = I L+ I L− I0 I L 2 VOpp TON TOFF C0 =  V  V0  T − 0 T  Vin  T (Vin − V0 ) V0T 2 =  = 4C0 L1 2 8VinC0 L1 (Vin − V0 ) V0 8VOppVin L1 f 2 452 226 For best regulation, the inductor’s current cannot be allowed to fall to zero. Some minimum load current I0 , and thus inductor current, is required as shown below. I 0 (min) = (Vin − V0 ) tON = (Vin − V0 )V0 2 L1 2 fVin L1 453 Example: Find tON, C0 and L1. Iin IL Q L1 Vin Vin (max) = 15V V0 VA C0 D1 VCE ( sat ) = 1V VD (on) = 1V − +  R  V0 =  1 + 1  VREF = 2  2.5V = 5V R2   5V t I0 = = 0.5 A V0 = ON Vin 10 T L1 = − f = 52kHz + 2.5V VREF Triangular waveform generator  tON = RL=10Ω R2 1k + Vrpp = 0.01V R1 1k V0 T = 6.4 s Vin 2.5V0 (Vin − V0 ) 2.5  5  ( 15 − 5 ) = = 320 H I 0Vin f 0.5  15  52k C0 = (Vin − V0 ) V0 8VOppVin L1 f 2 = ( 15 − 5 ) 5 8  0.01  15  320  ( 52k ) 2 = 48 F 454 227 Example: LM2574 0.5A Step-Down Voltage Regulator 40V max. Unregulated DC input LM2574-5 Vin 5 1 4 7 Feedback L1 C 22μF 2 3 ON OFF PWR Signal GND GND V0 (+5V) 330μH D1 Schottky diode C0 220μF 455 456 228 Adjustable Output Voltage LM2574-ADJ Vin 5 1 4 7 L1 C 2 3 V0 D1 R1 C0 RL R2  R  V0 =  1 + 1  VREF R2   VREF=1.23V R2 between 1kΩ and 5kΩ. 457 Boost-Style (Step-up) Converter A lower dc voltage is converted to a higher dc voltage. L D V0 Vin PWM Control L C Q L D V0 Vin Switch ON RL C RL D V0 Vin Switch OFF RL C 458 229 Buck-Boost (Inverting) Regulator Buck-Boost regulator takes a DC input voltage and produces a DC output voltage that is opposite in polarity to the input. D Q PWM Control Vin Switch ON Vin L L D + + RL C Switch OFF V0 C V0 Vin RL D V0 C L + RL 459 Flyback Regulator The flyback is the most versatile of all the topologies, allowing the designer to create one or more output voltages, some of which may be opposite in polarity. D Vin V0 C PWM Control RL Q Basic single-output flyback converter 460 230

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